Alexandre Salconi-Denis / LSM303DLH

My attempt to made a more useful lib. You can get the accelerator and magnetometer.

Fork of LSM303DLH by Michael Shimniok

LSM303DLH_RegisterDef.h@5:48722ae56546, 2017-08-06 (annotated)

Committer:
salco
Date:
Sun Aug 06 19:11:23 2017 +0000
Revision:
5:48722ae56546
Child:
6:86cf2afe3e52
a new morning;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
salco 5:48722ae56546 1 #ifndef __LSM303DLH_REGISTERDEF_H_
salco 5:48722ae56546 2 #define __LSM303DLH_REGISTERDEF_H_
salco 5:48722ae56546 3
salco 5:48722ae56546 4 /** @defgroup regA Register
salco 5:48722ae56546 5 * Register for accelerometer
salco 5:48722ae56546 6 * @{
salco 5:48722ae56546 7 */
salco 5:48722ae56546 8
salco 5:48722ae56546 9 //#if defined(DOXYGEN_ONLY)
salco 5:48722ae56546 10
salco 5:48722ae56546 11 /**@note add LSM303DLH:: to use the docc doxygen for no reason*/
salco 5:48722ae56546 12
salco 5:48722ae56546 13 /** CTRL_REG1_A structure definition
salco 5:48722ae56546 14 */
salco 5:48722ae56546 15 union Ctrl_Reg1_A_t
salco 5:48722ae56546 16 {
salco 5:48722ae56546 17 uint8_t byte; /**< Value in byte.*/
salco 5:48722ae56546 18 struct{
salco 5:48722ae56546 19 uint8_t Xen:1; /**< X axis enable. Default value: 1.*/
salco 5:48722ae56546 20 uint8_t Yen:1; /**< Y axis enable. Default value: 1.*/
salco 5:48722ae56546 21 uint8_t Zen:1; /**< Z axis enable. Default value: 1.*/
salco 5:48722ae56546 22 uint8_t LPen:1;/**< Low-power mode enable. Default value: 0.*/
salco 5:48722ae56546 23 uint8_t ODR:4; /**< Data rate selection. Default value: 0.*/
salco 5:48722ae56546 24 };
salco 5:48722ae56546 25 };
salco 5:48722ae56546 26
salco 5:48722ae56546 27 /** CTRL_REG2_A structure definition
salco 5:48722ae56546 28 */
salco 5:48722ae56546 29 union Ctrl_Reg2_A_t
salco 5:48722ae56546 30 {
salco 5:48722ae56546 31 uint8_t byte; /**< Value in byte.*/
salco 5:48722ae56546 32 struct{
salco 5:48722ae56546 33 uint8_t HPIS1:1; /**< High pass filter enabled for AOI function on Interrupt 1.*/
salco 5:48722ae56546 34 uint8_t HPIS2:1; /**< High pass filter enabled for AOI function on Interrupt 2.*/
salco 5:48722ae56546 35 uint8_t HPCLICK:1; /**< High pass filter enabled for CLICK function.*/
salco 5:48722ae56546 36 uint8_t FDS:1; /**< Filtered data selection. Default value: 0.*/
salco 5:48722ae56546 37 uint8_t HPCF:2; /**< High pass filter cut-off frequency selection.*/
salco 5:48722ae56546 38 uint8_t HPM:2; /**< High pass filter mode selection. Default value: 00*/
salco 5:48722ae56546 39 };
salco 5:48722ae56546 40 };
salco 5:48722ae56546 41
salco 5:48722ae56546 42 /** CTRL_REG3_A structure definition
salco 5:48722ae56546 43 */
salco 5:48722ae56546 44 union Ctrl_Reg3_A_t
salco 5:48722ae56546 45 {
salco 5:48722ae56546 46 uint8_t byte; /**< Value in byte.*/
salco 5:48722ae56546 47 struct{
salco 5:48722ae56546 48 uint8_t _Reserved:1; /**< Do not use.*/
salco 5:48722ae56546 49 uint8_t I1_OVERRUN:1; /**< FIFO overrun interrupt on INT1. Default value 0.*/
salco 5:48722ae56546 50 uint8_t I1_WTM:1; /**< FIFO watermark interrupt on INT1. Default value 0.*/
salco 5:48722ae56546 51 uint8_t I1_DRDY2:1; /**< DRDY2 interrupt on INT1. Default value 0.*/
salco 5:48722ae56546 52 uint8_t I1_DRDY1:1; /**< DRDY1 interrupt on INT1. Default value 0.*/
salco 5:48722ae56546 53 uint8_t I1_AOI2:1; /**< AOI2 interrupt on INT1. Default value 0.*/
salco 5:48722ae56546 54 uint8_t I1_AOI1:1; /**< AOI1 interrupt on INT1. Default value 0.*/
salco 5:48722ae56546 55 uint8_t I1_CLICK:1; /**< CLICK interrupt on INT1. Default value 0.*/
salco 5:48722ae56546 56 };
salco 5:48722ae56546 57 };
salco 5:48722ae56546 58
salco 5:48722ae56546 59 /** CTRL_REG4_A structure definition
salco 5:48722ae56546 60 */
salco 5:48722ae56546 61 union Ctrl_Reg4_A_t
salco 5:48722ae56546 62 {
salco 5:48722ae56546 63 uint8_t byte; /**< Value in byte.*/
salco 5:48722ae56546 64 struct{
salco 5:48722ae56546 65 uint8_t SIM:1; /**< SPI serial interface mode selection. Default value: 0.*/
salco 5:48722ae56546 66 uint8_t _Reserved:2; /**< Do not use.*/
salco 5:48722ae56546 67 uint8_t HR:1; /**< High resolution output mode: Default value: 0.*/
salco 5:48722ae56546 68 uint8_t FS:2; /**< Full-scale selection. Default value: 00.*/
salco 5:48722ae56546 69 uint8_t BLE:1; /**< Big/little endian data selection. Default value 0.*/
salco 5:48722ae56546 70 uint8_t BDU:1; /**< Block data update. Default value: 0.*/
salco 5:48722ae56546 71 };
salco 5:48722ae56546 72 };
salco 5:48722ae56546 73
salco 5:48722ae56546 74 /** CTRL_REG5_A structure definition
salco 5:48722ae56546 75 */
salco 5:48722ae56546 76 union Ctrl_Reg5_A_t
salco 5:48722ae56546 77 {
salco 5:48722ae56546 78 uint8_t byte; /**< Value in byte.*/
salco 5:48722ae56546 79 struct{
salco 5:48722ae56546 80 uint8_t D4D_INT2:1; /**< 4D detection is enabled on INT2 when 6D bit on INT2_CFG is set to 1.*/
salco 5:48722ae56546 81 uint8_t LIR_INT2:1; /**< Latch interrupt request on INT2_SRC register, with INT2_SRC register
salco 5:48722ae56546 82 cleared by reading INT2_SRC itself. Default value: 0.*/
salco 5:48722ae56546 83 uint8_t D4D_INT1:1; /**< 4D detection is enabled on INT1 when 6D bit on INT1_CFG is set to 1.*/
salco 5:48722ae56546 84 uint8_t LIR_INT1:1; /**< Latch interrupt request on INT1_SRC register, with INT1_SRC register
salco 5:48722ae56546 85 cleared by reading INT1_SRC itself. Default value: 0.*/
salco 5:48722ae56546 86 uint8_t _Reserved:2; /**< Do not use.*/
salco 5:48722ae56546 87 uint8_t FIFO_EN:1; /**< FIFO enable. Default value: 0.*/
salco 5:48722ae56546 88 uint8_t BOOT:1; /**< Reboot memory content. Default value: 0.*/
salco 5:48722ae56546 89 };
salco 5:48722ae56546 90 };
salco 5:48722ae56546 91
salco 5:48722ae56546 92
salco 5:48722ae56546 93
salco 5:48722ae56546 94 /** CTRL_REG6_A structure definition
salco 5:48722ae56546 95 */
salco 5:48722ae56546 96 union Ctrl_Reg6_A_t
salco 5:48722ae56546 97 {
salco 5:48722ae56546 98 uint8_t byte; /**< Value in byte.*/
salco 5:48722ae56546 99 struct{
salco 5:48722ae56546 100 uint8_t _Reserved:1; /**< Do not use.*/
salco 5:48722ae56546 101 uint8_t H_LACTIVE:1; /**< Interrupt active high, low. Default value 0.*/
salco 5:48722ae56546 102 uint8_t __Reserved:1; /**< Do not use.*/
salco 5:48722ae56546 103 uint8_t P2_ACT:1; /**< Active function status on PAD2. Default value 0.*/
salco 5:48722ae56546 104 uint8_t BOOT_I1:1; /**< Reboot memory content on PAD2. Default value: 0.*/
salco 5:48722ae56546 105 uint8_t I2_INT2:1; /**< Interrupt 2 on PAD2. Default value 0.*/
salco 5:48722ae56546 106 uint8_t I2_INT1:1; /**< Interrupt 1 on PAD2. Default value 0.*/
salco 5:48722ae56546 107 uint8_t I2_CLICKen:1; /**< CLICK interrupt on PAD2. Default value 0.*/
salco 5:48722ae56546 108 };
salco 5:48722ae56546 109 };
salco 5:48722ae56546 110
salco 5:48722ae56546 111 /** Status_Reg_A structure definition
salco 5:48722ae56546 112 */
salco 5:48722ae56546 113 union Status_Reg_A_t
salco 5:48722ae56546 114 {
salco 5:48722ae56546 115 uint8_t byte; /**< Value in byte.*/
salco 5:48722ae56546 116 struct{
salco 5:48722ae56546 117
salco 5:48722ae56546 118 uint8_t XDA:1; /**< X axis new data available. Default value: 0.*/
salco 5:48722ae56546 119 uint8_t YDA:1; /**< Y axis new data available. Default value: 0.*/
salco 5:48722ae56546 120 uint8_t ZDA:1; /**< Z axis new data available. Default value: 0.*/
salco 5:48722ae56546 121 uint8_t ZYXDA:1; /**< X, Y, and Z axis new data available. Default value: 0.*/
salco 5:48722ae56546 122 uint8_t XOR:1; /**< X axis data overrun. Default value: 0.*/
salco 5:48722ae56546 123 uint8_t YOR:1; /**< Y axis data overrun. Default value: 0.*/
salco 5:48722ae56546 124 uint8_t ZOR:1; /**< Z axis data overrun. Default value: 0.*/
salco 5:48722ae56546 125 uint8_t ZYXOR:1; /**< X, Y, and Z axis data overrun. Default value: 0.*/
salco 5:48722ae56546 126 };
salco 5:48722ae56546 127 };
salco 5:48722ae56546 128
salco 5:48722ae56546 129 /** OUT_XYZ_t structure. The value is expressed in 2’s complement
salco 5:48722ae56546 130 */
salco 5:48722ae56546 131 union OUT_XYZ_t
salco 5:48722ae56546 132 {
salco 5:48722ae56546 133 int16_t value; /**< Value in signed integer.*/
salco 5:48722ae56546 134 uint8_t byte[2];
salco 5:48722ae56546 135 struct{
salco 5:48722ae56546 136 uint8_t UT_L_A; /**< Low register.*/
salco 5:48722ae56546 137 uint8_t UT_H_A; /**< High register.*/
salco 5:48722ae56546 138 };
salco 5:48722ae56546 139 };
salco 5:48722ae56546 140 /** @} */ // end of regA
salco 5:48722ae56546 141
salco 5:48722ae56546 142 /** SR_Reg_M structure definition
salco 5:48722ae56546 143 */
salco 5:48722ae56546 144 union SR_Reg_M_t
salco 5:48722ae56546 145 {
salco 5:48722ae56546 146 uint8_t byte; /**< Value in byte.*/
salco 5:48722ae56546 147 struct{
salco 5:48722ae56546 148 uint8_t DRDY:1; /**< Data output register lock.*/
salco 5:48722ae56546 149 uint8_t LOCK:1; /**< Data ready bit.*/
salco 5:48722ae56546 150 uint8_t _Reserved:8; /**< Do not use.*/
salco 5:48722ae56546 151 };
salco 5:48722ae56546 152 };
salco 5:48722ae56546 153
salco 5:48722ae56546 154 /** CRB_REG_M structure definition
salco 5:48722ae56546 155 */
salco 5:48722ae56546 156 union CRB_REG_M_t
salco 5:48722ae56546 157 {
salco 5:48722ae56546 158 uint8_t byte; /**< Value in byte.*/
salco 5:48722ae56546 159 struct{
salco 5:48722ae56546 160 uint8_t _Reserved:5; /**< Do not use. Must be set to ‘0*/
salco 5:48722ae56546 161 uint8_t GN:3; /**< Gain configuration.*/
salco 5:48722ae56546 162 };
salco 5:48722ae56546 163 };
salco 5:48722ae56546 164
salco 5:48722ae56546 165 #endif //__LSM303DLH_REGISTERDEF_H_