DMA_RAM_DAC - won't compile

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stm32f30x_tim.c@0:b079fa4ed182, 2016-11-02 (annotated)

Committer:: richardv
Date:: Wed Nov 02 23:50:52 2016 +0000
Revision:: 0:b079fa4ed182

DMA RAM DAC

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User	Revision	Line number	New contents of line
richardv	0:b079fa4ed182	1	/**
richardv	0:b079fa4ed182	2	******************************************************************************
richardv	0:b079fa4ed182	3	* @file stm32f30x_tim.c
richardv	0:b079fa4ed182	4	* @author MCD Application Team
richardv	0:b079fa4ed182	5	* @version V1.1.1
richardv	0:b079fa4ed182	6	* @date 04-April-2014
richardv	0:b079fa4ed182	7	* @brief This file provides firmware functions to manage the following
richardv	0:b079fa4ed182	8	* functionalities of the TIM peripheral:
richardv	0:b079fa4ed182	9	* + TimeBase management
richardv	0:b079fa4ed182	10	* + Output Compare management
richardv	0:b079fa4ed182	11	* + Input Capture management
richardv	0:b079fa4ed182	12	* + Advanced-control timers (TIM1 and TIM8) specific features
richardv	0:b079fa4ed182	13	* + Interrupts, DMA and flags management
richardv	0:b079fa4ed182	14	* + Clocks management
richardv	0:b079fa4ed182	15	* + Synchronization management
richardv	0:b079fa4ed182	16	* + Specific interface management
richardv	0:b079fa4ed182	17	* + Specific remapping management
richardv	0:b079fa4ed182	18	*
richardv	0:b079fa4ed182	19	@verbatim
richardv	0:b079fa4ed182	20
richardv	0:b079fa4ed182	21	==============================================================================
richardv	0:b079fa4ed182	22	##### How to use this driver #####
richardv	0:b079fa4ed182	23	==============================================================================
richardv	0:b079fa4ed182	24	[..] This driver provides functions to configure and program the TIM
richardv	0:b079fa4ed182	25	of all stm32f30x devices.
richardv	0:b079fa4ed182	26	These functions are split in 9 groups:
richardv	0:b079fa4ed182	27
richardv	0:b079fa4ed182	28	(#) TIM TimeBase management: this group includes all needed functions
richardv	0:b079fa4ed182	29	to configure the TM Timebase unit:
richardv	0:b079fa4ed182	30	(++) Set/Get Prescaler
richardv	0:b079fa4ed182	31	(++) Set/Get Autoreload
richardv	0:b079fa4ed182	32	(++) Counter modes configuration
richardv	0:b079fa4ed182	33	(++) Set Clock division
richardv	0:b079fa4ed182	34	(++) Select the One Pulse mode
richardv	0:b079fa4ed182	35	(++) Update Request Configuration
richardv	0:b079fa4ed182	36	(++) Update Disable Configuration
richardv	0:b079fa4ed182	37	(++) Auto-Preload Configuration
richardv	0:b079fa4ed182	38	(++) Enable/Disable the counter
richardv	0:b079fa4ed182	39
richardv	0:b079fa4ed182	40	(#) TIM Output Compare management: this group includes all needed
richardv	0:b079fa4ed182	41	functions to configure the Capture/Compare unit used in Output
richardv	0:b079fa4ed182	42	compare mode:
richardv	0:b079fa4ed182	43	(++) Configure each channel, independently, in Output Compare mode
richardv	0:b079fa4ed182	44	(++) Select the output compare modes
richardv	0:b079fa4ed182	45	(++) Select the Polarities of each channel
richardv	0:b079fa4ed182	46	(++) Set/Get the Capture/Compare register values
richardv	0:b079fa4ed182	47	(++) Select the Output Compare Fast mode
richardv	0:b079fa4ed182	48	(++) Select the Output Compare Forced mode
richardv	0:b079fa4ed182	49	(++) Output Compare-Preload Configuration
richardv	0:b079fa4ed182	50	(++) Clear Output Compare Reference
richardv	0:b079fa4ed182	51	(++) Select the OCREF Clear signal
richardv	0:b079fa4ed182	52	(++) Enable/Disable the Capture/Compare Channels
richardv	0:b079fa4ed182	53
richardv	0:b079fa4ed182	54	(#) TIM Input Capture management: this group includes all needed
richardv	0:b079fa4ed182	55	functions to configure the Capture/Compare unit used in
richardv	0:b079fa4ed182	56	Input Capture mode:
richardv	0:b079fa4ed182	57	(++) Configure each channel in input capture mode
richardv	0:b079fa4ed182	58	(++) Configure Channel1/2 in PWM Input mode
richardv	0:b079fa4ed182	59	(++) Set the Input Capture Prescaler
richardv	0:b079fa4ed182	60	(++) Get the Capture/Compare values
richardv	0:b079fa4ed182	61
richardv	0:b079fa4ed182	62	(#) Advanced-control timers (TIM1 and TIM8) specific features
richardv	0:b079fa4ed182	63	(++) Configures the Break input, dead time, Lock level, the OSSI,
richardv	0:b079fa4ed182	64	the OSSR State and the AOE(automatic output enable)
richardv	0:b079fa4ed182	65	(++) Enable/Disable the TIM peripheral Main Outputs
richardv	0:b079fa4ed182	66	(++) Select the Commutation event
richardv	0:b079fa4ed182	67	(++) Set/Reset the Capture Compare Preload Control bit
richardv	0:b079fa4ed182	68
richardv	0:b079fa4ed182	69	(#) TIM interrupts, DMA and flags management
richardv	0:b079fa4ed182	70	(++) Enable/Disable interrupt sources
richardv	0:b079fa4ed182	71	(++) Get flags status
richardv	0:b079fa4ed182	72	(++) Clear flags/ Pending bits
richardv	0:b079fa4ed182	73	(++) Enable/Disable DMA requests
richardv	0:b079fa4ed182	74	(++) Configure DMA burst mode
richardv	0:b079fa4ed182	75	(++) Select CaptureCompare DMA request
richardv	0:b079fa4ed182	76
richardv	0:b079fa4ed182	77	(#) TIM clocks management: this group includes all needed functions
richardv	0:b079fa4ed182	78	to configure the clock controller unit:
richardv	0:b079fa4ed182	79	(++) Select internal/External clock
richardv	0:b079fa4ed182	80	(++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
richardv	0:b079fa4ed182	81
richardv	0:b079fa4ed182	82	(#) TIM synchronization management: this group includes all needed
richardv	0:b079fa4ed182	83	functions to configure the Synchronization unit:
richardv	0:b079fa4ed182	84	(++) Select Input Trigger
richardv	0:b079fa4ed182	85	(++) Select Output Trigger
richardv	0:b079fa4ed182	86	(++) Select Master Slave Mode
richardv	0:b079fa4ed182	87	(++) ETR Configuration when used as external trigger
richardv	0:b079fa4ed182	88
richardv	0:b079fa4ed182	89	(#) TIM specific interface management, this group includes all
richardv	0:b079fa4ed182	90	needed functions to use the specific TIM interface:
richardv	0:b079fa4ed182	91	(++) Encoder Interface Configuration
richardv	0:b079fa4ed182	92	(++) Select Hall Sensor
richardv	0:b079fa4ed182	93
richardv	0:b079fa4ed182	94	(#) TIM specific remapping management includes the Remapping
richardv	0:b079fa4ed182	95	configuration of specific timers
richardv	0:b079fa4ed182	96
richardv	0:b079fa4ed182	97	@endverbatim
richardv	0:b079fa4ed182	98
richardv	0:b079fa4ed182	99	******************************************************************************
richardv	0:b079fa4ed182	100	* @attention
richardv	0:b079fa4ed182	101	*
richardv	0:b079fa4ed182	102	* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
richardv	0:b079fa4ed182	103	*
richardv	0:b079fa4ed182	104	* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
richardv	0:b079fa4ed182	105	* You may not use this file except in compliance with the License.
richardv	0:b079fa4ed182	106	* You may obtain a copy of the License at:
richardv	0:b079fa4ed182	107	*
richardv	0:b079fa4ed182	108	* http://www.st.com/software_license_agreement_liberty_v2
richardv	0:b079fa4ed182	109	*
richardv	0:b079fa4ed182	110	* Unless required by applicable law or agreed to in writing, software
richardv	0:b079fa4ed182	111	* distributed under the License is distributed on an "AS IS" BASIS,
richardv	0:b079fa4ed182	112	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
richardv	0:b079fa4ed182	113	* See the License for the specific language governing permissions and
richardv	0:b079fa4ed182	114	* limitations under the License.
richardv	0:b079fa4ed182	115	*
richardv	0:b079fa4ed182	116	******************************************************************************
richardv	0:b079fa4ed182	117	*/
richardv	0:b079fa4ed182	118
richardv	0:b079fa4ed182	119	/* Includes ------------------------------------------------------------------*/
richardv	0:b079fa4ed182	120	#include "stm32f30x_tim.h"
richardv	0:b079fa4ed182	121	#include "stm32f30x_rcc.h"
richardv	0:b079fa4ed182	122
richardv	0:b079fa4ed182	123	/** @addtogroup STM32F30x_StdPeriph_Driver
richardv	0:b079fa4ed182	124	* @{
richardv	0:b079fa4ed182	125	*/
richardv	0:b079fa4ed182	126
richardv	0:b079fa4ed182	127	/** @defgroup TIM
richardv	0:b079fa4ed182	128	* @brief TIM driver modules
richardv	0:b079fa4ed182	129	* @{
richardv	0:b079fa4ed182	130	*/
richardv	0:b079fa4ed182	131
richardv	0:b079fa4ed182	132	/* Private typedef -----------------------------------------------------------*/
richardv	0:b079fa4ed182	133	/* Private define ------------------------------------------------------------*/
richardv	0:b079fa4ed182	134
richardv	0:b079fa4ed182	135	/* ---------------------- TIM registers bit mask ------------------------ */
richardv	0:b079fa4ed182	136	#define SMCR_ETR_MASK ((uint16_t)0x00FF)
richardv	0:b079fa4ed182	137	#define CCMR_OFFSET ((uint16_t)0x0018)
richardv	0:b079fa4ed182	138	#define CCER_CCE_SET ((uint16_t)0x0001)
richardv	0:b079fa4ed182	139	#define CCER_CCNE_SET ((uint16_t)0x0004)
richardv	0:b079fa4ed182	140	#define CCMR_OC13M_MASK ((uint32_t)0xFFFEFF8F)
richardv	0:b079fa4ed182	141	#define CCMR_OC24M_MASK ((uint32_t)0xFEFF8FFF)
richardv	0:b079fa4ed182	142
richardv	0:b079fa4ed182	143	/* Private macro -------------------------------------------------------------*/
richardv	0:b079fa4ed182	144	/* Private variables ---------------------------------------------------------*/
richardv	0:b079fa4ed182	145	/* Private function prototypes -----------------------------------------------*/
richardv	0:b079fa4ed182	146	static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
richardv	0:b079fa4ed182	147	uint16_t TIM_ICFilter);
richardv	0:b079fa4ed182	148	static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
richardv	0:b079fa4ed182	149	uint16_t TIM_ICFilter);
richardv	0:b079fa4ed182	150	static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
richardv	0:b079fa4ed182	151	uint16_t TIM_ICFilter);
richardv	0:b079fa4ed182	152	static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
richardv	0:b079fa4ed182	153	uint16_t TIM_ICFilter);
richardv	0:b079fa4ed182	154
richardv	0:b079fa4ed182	155	/* Private functions ---------------------------------------------------------*/
richardv	0:b079fa4ed182	156
richardv	0:b079fa4ed182	157	/** @defgroup TIM_Private_Functions
richardv	0:b079fa4ed182	158	* @{
richardv	0:b079fa4ed182	159	*/
richardv	0:b079fa4ed182	160
richardv	0:b079fa4ed182	161	/** @defgroup TIM_Group1 TimeBase management functions
richardv	0:b079fa4ed182	162	* @brief TimeBase management functions
richardv	0:b079fa4ed182	163	*
richardv	0:b079fa4ed182	164	@verbatim
richardv	0:b079fa4ed182	165	===============================================================================
richardv	0:b079fa4ed182	166	##### TimeBase management functions #####
richardv	0:b079fa4ed182	167	===============================================================================
richardv	0:b079fa4ed182	168
richardv	0:b079fa4ed182	169
richardv	0:b079fa4ed182	170	* TIM Driver: how to use it in Timing(Time base) Mode *
richardv	0:b079fa4ed182	171	============================================================
richardv	0:b079fa4ed182	172	[..]
richardv	0:b079fa4ed182	173	To use the Timer in Timing(Time base) mode, the following steps are mandatory:
richardv	0:b079fa4ed182	174
richardv	0:b079fa4ed182	175	(#) Enable TIM clock using
richardv	0:b079fa4ed182	176	RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
richardv	0:b079fa4ed182	177	(#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
richardv	0:b079fa4ed182	178	(#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure
richardv	0:b079fa4ed182	179	the Time Base unit
richardv	0:b079fa4ed182	180	with the corresponding configuration
richardv	0:b079fa4ed182	181	(#) Enable the NVIC if you need to generate the update interrupt.
richardv	0:b079fa4ed182	182	(#) Enable the corresponding interrupt using the function
richardv	0:b079fa4ed182	183	TIM_ITConfig(TIMx, TIM_IT_Update)
richardv	0:b079fa4ed182	184	(#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
richardv	0:b079fa4ed182	185	[..]
richardv	0:b079fa4ed182	186	(@) All other functions can be used separately to modify, if needed,
richardv	0:b079fa4ed182	187	a specific feature of the Timer.
richardv	0:b079fa4ed182	188
richardv	0:b079fa4ed182	189	@endverbatim
richardv	0:b079fa4ed182	190	* @{
richardv	0:b079fa4ed182	191	*/
richardv	0:b079fa4ed182	192
richardv	0:b079fa4ed182	193	/**
richardv	0:b079fa4ed182	194	* @brief Deinitializes the TIMx peripheral registers to their default reset values.
richardv	0:b079fa4ed182	195	* @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	196	* @retval None
richardv	0:b079fa4ed182	197
richardv	0:b079fa4ed182	198	*/
richardv	0:b079fa4ed182	199	void TIM_DeInit(TIM_TypeDef* TIMx)
richardv	0:b079fa4ed182	200	{
richardv	0:b079fa4ed182	201	/* Check the parameters */
richardv	0:b079fa4ed182	202	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	203
richardv	0:b079fa4ed182	204	if (TIMx == TIM1)
richardv	0:b079fa4ed182	205	{
richardv	0:b079fa4ed182	206	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
richardv	0:b079fa4ed182	207	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
richardv	0:b079fa4ed182	208	}
richardv	0:b079fa4ed182	209	else if (TIMx == TIM2)
richardv	0:b079fa4ed182	210	{
richardv	0:b079fa4ed182	211	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
richardv	0:b079fa4ed182	212	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
richardv	0:b079fa4ed182	213	}
richardv	0:b079fa4ed182	214	else if (TIMx == TIM3)
richardv	0:b079fa4ed182	215	{
richardv	0:b079fa4ed182	216	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
richardv	0:b079fa4ed182	217	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
richardv	0:b079fa4ed182	218	}
richardv	0:b079fa4ed182	219	else if (TIMx == TIM4)
richardv	0:b079fa4ed182	220	{
richardv	0:b079fa4ed182	221	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
richardv	0:b079fa4ed182	222	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
richardv	0:b079fa4ed182	223	}
richardv	0:b079fa4ed182	224	else if (TIMx == TIM6)
richardv	0:b079fa4ed182	225	{
richardv	0:b079fa4ed182	226	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
richardv	0:b079fa4ed182	227	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
richardv	0:b079fa4ed182	228	}
richardv	0:b079fa4ed182	229	else if (TIMx == TIM7)
richardv	0:b079fa4ed182	230	{
richardv	0:b079fa4ed182	231	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
richardv	0:b079fa4ed182	232	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
richardv	0:b079fa4ed182	233	}
richardv	0:b079fa4ed182	234	else if (TIMx == TIM8)
richardv	0:b079fa4ed182	235	{
richardv	0:b079fa4ed182	236	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
richardv	0:b079fa4ed182	237	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
richardv	0:b079fa4ed182	238	}
richardv	0:b079fa4ed182	239	else if (TIMx == TIM15)
richardv	0:b079fa4ed182	240	{
richardv	0:b079fa4ed182	241	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
richardv	0:b079fa4ed182	242	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
richardv	0:b079fa4ed182	243	}
richardv	0:b079fa4ed182	244	else if (TIMx == TIM16)
richardv	0:b079fa4ed182	245	{
richardv	0:b079fa4ed182	246	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
richardv	0:b079fa4ed182	247	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
richardv	0:b079fa4ed182	248	}
richardv	0:b079fa4ed182	249	else
richardv	0:b079fa4ed182	250	{
richardv	0:b079fa4ed182	251	if (TIMx == TIM17)
richardv	0:b079fa4ed182	252	{
richardv	0:b079fa4ed182	253	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
richardv	0:b079fa4ed182	254	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
richardv	0:b079fa4ed182	255	}
richardv	0:b079fa4ed182	256	}
richardv	0:b079fa4ed182	257	}
richardv	0:b079fa4ed182	258
richardv	0:b079fa4ed182	259	/**
richardv	0:b079fa4ed182	260	* @brief Initializes the TIMx Time Base Unit peripheral according to
richardv	0:b079fa4ed182	261	* the specified parameters in the TIM_TimeBaseInitStruct.
richardv	0:b079fa4ed182	262	* @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	263	* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
richardv	0:b079fa4ed182	264	* that contains the configuration information for the specified TIM peripheral.
richardv	0:b079fa4ed182	265	* @retval None
richardv	0:b079fa4ed182	266	*/
richardv	0:b079fa4ed182	267	void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
richardv	0:b079fa4ed182	268	{
richardv	0:b079fa4ed182	269	uint16_t tmpcr1 = 0;
richardv	0:b079fa4ed182	270
richardv	0:b079fa4ed182	271	/* Check the parameters */
richardv	0:b079fa4ed182	272	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	273	assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
richardv	0:b079fa4ed182	274	assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
richardv	0:b079fa4ed182	275
richardv	0:b079fa4ed182	276	tmpcr1 = TIMx->CR1;
richardv	0:b079fa4ed182	277
richardv	0:b079fa4ed182	278	if((TIMx == TIM1) \|\| (TIMx == TIM8)\|\| (TIMx == TIM2) \|\|
richardv	0:b079fa4ed182	279	(TIMx == TIM3)\|\| (TIMx == TIM4))
richardv	0:b079fa4ed182	280	{
richardv	0:b079fa4ed182	281	/* Select the Counter Mode */
richardv	0:b079fa4ed182	282	tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR \| TIM_CR1_CMS));
richardv	0:b079fa4ed182	283	tmpcr1 \|= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
richardv	0:b079fa4ed182	284	}
richardv	0:b079fa4ed182	285
richardv	0:b079fa4ed182	286	if((TIMx != TIM6) && (TIMx != TIM7))
richardv	0:b079fa4ed182	287	{
richardv	0:b079fa4ed182	288	/* Set the clock division */
richardv	0:b079fa4ed182	289	tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
richardv	0:b079fa4ed182	290	tmpcr1 \|= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
richardv	0:b079fa4ed182	291	}
richardv	0:b079fa4ed182	292
richardv	0:b079fa4ed182	293	TIMx->CR1 = tmpcr1;
richardv	0:b079fa4ed182	294
richardv	0:b079fa4ed182	295	/* Set the Autoreload value */
richardv	0:b079fa4ed182	296	TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
richardv	0:b079fa4ed182	297
richardv	0:b079fa4ed182	298	/* Set the Prescaler value */
richardv	0:b079fa4ed182	299	TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
richardv	0:b079fa4ed182	300
richardv	0:b079fa4ed182	301	if ((TIMx == TIM1) \|\| (TIMx == TIM8)\|\| (TIMx == TIM15) \|\|
richardv	0:b079fa4ed182	302	(TIMx == TIM16) \|\| (TIMx == TIM17))
richardv	0:b079fa4ed182	303	{
richardv	0:b079fa4ed182	304	/* Set the Repetition Counter value */
richardv	0:b079fa4ed182	305	TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
richardv	0:b079fa4ed182	306	}
richardv	0:b079fa4ed182	307
richardv	0:b079fa4ed182	308	/* Generate an update event to reload the Prescaler
richardv	0:b079fa4ed182	309	and the repetition counter(only for TIM1 and TIM8) value immediatly */
richardv	0:b079fa4ed182	310	TIMx->EGR = TIM_PSCReloadMode_Immediate;
richardv	0:b079fa4ed182	311	}
richardv	0:b079fa4ed182	312
richardv	0:b079fa4ed182	313	/**
richardv	0:b079fa4ed182	314	* @brief Fills each TIM_TimeBaseInitStruct member with its default value.
richardv	0:b079fa4ed182	315	* @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
richardv	0:b079fa4ed182	316	* structure which will be initialized.
richardv	0:b079fa4ed182	317	* @retval None
richardv	0:b079fa4ed182	318	*/
richardv	0:b079fa4ed182	319	void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
richardv	0:b079fa4ed182	320	{
richardv	0:b079fa4ed182	321	/* Set the default configuration */
richardv	0:b079fa4ed182	322	TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
richardv	0:b079fa4ed182	323	TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
richardv	0:b079fa4ed182	324	TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
richardv	0:b079fa4ed182	325	TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
richardv	0:b079fa4ed182	326	TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
richardv	0:b079fa4ed182	327	}
richardv	0:b079fa4ed182	328
richardv	0:b079fa4ed182	329	/**
richardv	0:b079fa4ed182	330	* @brief Configures the TIMx Prescaler.
richardv	0:b079fa4ed182	331	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	332	* @param Prescaler: specifies the Prescaler Register value
richardv	0:b079fa4ed182	333	* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
richardv	0:b079fa4ed182	334	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	335	* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
richardv	0:b079fa4ed182	336	* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
richardv	0:b079fa4ed182	337	* @retval None
richardv	0:b079fa4ed182	338	*/
richardv	0:b079fa4ed182	339	void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
richardv	0:b079fa4ed182	340	{
richardv	0:b079fa4ed182	341	/* Check the parameters */
richardv	0:b079fa4ed182	342	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	343	assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
richardv	0:b079fa4ed182	344	/* Set the Prescaler value */
richardv	0:b079fa4ed182	345	TIMx->PSC = Prescaler;
richardv	0:b079fa4ed182	346	/* Set or reset the UG Bit */
richardv	0:b079fa4ed182	347	TIMx->EGR = TIM_PSCReloadMode;
richardv	0:b079fa4ed182	348	}
richardv	0:b079fa4ed182	349
richardv	0:b079fa4ed182	350	/**
richardv	0:b079fa4ed182	351	* @brief Specifies the TIMx Counter Mode to be used.
richardv	0:b079fa4ed182	352	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	353	* @param TIM_CounterMode: specifies the Counter Mode to be used
richardv	0:b079fa4ed182	354	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	355	* @arg TIM_CounterMode_Up: TIM Up Counting Mode
richardv	0:b079fa4ed182	356	* @arg TIM_CounterMode_Down: TIM Down Counting Mode
richardv	0:b079fa4ed182	357	* @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
richardv	0:b079fa4ed182	358	* @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
richardv	0:b079fa4ed182	359	* @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
richardv	0:b079fa4ed182	360	* @retval None
richardv	0:b079fa4ed182	361	*/
richardv	0:b079fa4ed182	362	void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
richardv	0:b079fa4ed182	363	{
richardv	0:b079fa4ed182	364	uint16_t tmpcr1 = 0;
richardv	0:b079fa4ed182	365
richardv	0:b079fa4ed182	366	/* Check the parameters */
richardv	0:b079fa4ed182	367	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	368	assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
richardv	0:b079fa4ed182	369
richardv	0:b079fa4ed182	370	tmpcr1 = TIMx->CR1;
richardv	0:b079fa4ed182	371
richardv	0:b079fa4ed182	372	/* Reset the CMS and DIR Bits */
richardv	0:b079fa4ed182	373	tmpcr1 &= (uint16_t)~(TIM_CR1_DIR \| TIM_CR1_CMS);
richardv	0:b079fa4ed182	374
richardv	0:b079fa4ed182	375	/* Set the Counter Mode */
richardv	0:b079fa4ed182	376	tmpcr1 \|= TIM_CounterMode;
richardv	0:b079fa4ed182	377
richardv	0:b079fa4ed182	378	/* Write to TIMx CR1 register */
richardv	0:b079fa4ed182	379	TIMx->CR1 = tmpcr1;
richardv	0:b079fa4ed182	380	}
richardv	0:b079fa4ed182	381
richardv	0:b079fa4ed182	382	/**
richardv	0:b079fa4ed182	383	* @brief Sets the TIMx Counter Register value
richardv	0:b079fa4ed182	384	* @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	385	* @param Counter: specifies the Counter register new value.
richardv	0:b079fa4ed182	386	* @retval None
richardv	0:b079fa4ed182	387	*/
richardv	0:b079fa4ed182	388	void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
richardv	0:b079fa4ed182	389	{
richardv	0:b079fa4ed182	390	/* Check the parameters */
richardv	0:b079fa4ed182	391	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	392
richardv	0:b079fa4ed182	393	/* Set the Counter Register value */
richardv	0:b079fa4ed182	394	TIMx->CNT = Counter;
richardv	0:b079fa4ed182	395	}
richardv	0:b079fa4ed182	396
richardv	0:b079fa4ed182	397	/**
richardv	0:b079fa4ed182	398	* @brief Sets the TIMx Autoreload Register value
richardv	0:b079fa4ed182	399	* @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	400	* @param Autoreload: specifies the Autoreload register new value.
richardv	0:b079fa4ed182	401	* @retval None
richardv	0:b079fa4ed182	402	*/
richardv	0:b079fa4ed182	403	void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
richardv	0:b079fa4ed182	404	{
richardv	0:b079fa4ed182	405	/* Check the parameters */
richardv	0:b079fa4ed182	406	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	407
richardv	0:b079fa4ed182	408	/* Set the Autoreload Register value */
richardv	0:b079fa4ed182	409	TIMx->ARR = Autoreload;
richardv	0:b079fa4ed182	410	}
richardv	0:b079fa4ed182	411
richardv	0:b079fa4ed182	412	/**
richardv	0:b079fa4ed182	413	* @brief Gets the TIMx Counter value.
richardv	0:b079fa4ed182	414	* @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	415	* @retval Counter Register value
richardv	0:b079fa4ed182	416	*/
richardv	0:b079fa4ed182	417	uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
richardv	0:b079fa4ed182	418	{
richardv	0:b079fa4ed182	419	/* Check the parameters */
richardv	0:b079fa4ed182	420	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	421
richardv	0:b079fa4ed182	422	/* Get the Counter Register value */
richardv	0:b079fa4ed182	423	return TIMx->CNT;
richardv	0:b079fa4ed182	424	}
richardv	0:b079fa4ed182	425
richardv	0:b079fa4ed182	426	/**
richardv	0:b079fa4ed182	427	* @brief Gets the TIMx Prescaler value.
richardv	0:b079fa4ed182	428	* @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	429	* @retval Prescaler Register value.
richardv	0:b079fa4ed182	430	*/
richardv	0:b079fa4ed182	431	uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
richardv	0:b079fa4ed182	432	{
richardv	0:b079fa4ed182	433	/* Check the parameters */
richardv	0:b079fa4ed182	434	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	435
richardv	0:b079fa4ed182	436	/* Get the Prescaler Register value */
richardv	0:b079fa4ed182	437	return TIMx->PSC;
richardv	0:b079fa4ed182	438	}
richardv	0:b079fa4ed182	439
richardv	0:b079fa4ed182	440	/**
richardv	0:b079fa4ed182	441	* @brief Enables or Disables the TIMx Update event.
richardv	0:b079fa4ed182	442	* @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	443	* @param NewState: new state of the TIMx UDIS bit
richardv	0:b079fa4ed182	444	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	445	* @retval None
richardv	0:b079fa4ed182	446	*/
richardv	0:b079fa4ed182	447	void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	448	{
richardv	0:b079fa4ed182	449	/* Check the parameters */
richardv	0:b079fa4ed182	450	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	451	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	452
richardv	0:b079fa4ed182	453	if (NewState != DISABLE)
richardv	0:b079fa4ed182	454	{
richardv	0:b079fa4ed182	455	/* Set the Update Disable Bit */
richardv	0:b079fa4ed182	456	TIMx->CR1 \|= TIM_CR1_UDIS;
richardv	0:b079fa4ed182	457	}
richardv	0:b079fa4ed182	458	else
richardv	0:b079fa4ed182	459	{
richardv	0:b079fa4ed182	460	/* Reset the Update Disable Bit */
richardv	0:b079fa4ed182	461	TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
richardv	0:b079fa4ed182	462	}
richardv	0:b079fa4ed182	463	}
richardv	0:b079fa4ed182	464
richardv	0:b079fa4ed182	465	/**
richardv	0:b079fa4ed182	466	* @brief Configures the TIMx Update Request Interrupt source.
richardv	0:b079fa4ed182	467	* @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	468	* @param TIM_UpdateSource: specifies the Update source.
richardv	0:b079fa4ed182	469	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	470	* @arg TIM_UpdateSource_Regular: Source of update is the counter
richardv	0:b079fa4ed182	471	* overflow/underflow or the setting of UG bit, or an update
richardv	0:b079fa4ed182	472	* generation through the slave mode controller.
richardv	0:b079fa4ed182	473	* @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
richardv	0:b079fa4ed182	474	* @retval None
richardv	0:b079fa4ed182	475	*/
richardv	0:b079fa4ed182	476	void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
richardv	0:b079fa4ed182	477	{
richardv	0:b079fa4ed182	478	/* Check the parameters */
richardv	0:b079fa4ed182	479	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	480	assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
richardv	0:b079fa4ed182	481
richardv	0:b079fa4ed182	482	if (TIM_UpdateSource != TIM_UpdateSource_Global)
richardv	0:b079fa4ed182	483	{
richardv	0:b079fa4ed182	484	/* Set the URS Bit */
richardv	0:b079fa4ed182	485	TIMx->CR1 \|= TIM_CR1_URS;
richardv	0:b079fa4ed182	486	}
richardv	0:b079fa4ed182	487	else
richardv	0:b079fa4ed182	488	{
richardv	0:b079fa4ed182	489	/* Reset the URS Bit */
richardv	0:b079fa4ed182	490	TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
richardv	0:b079fa4ed182	491	}
richardv	0:b079fa4ed182	492	}
richardv	0:b079fa4ed182	493
richardv	0:b079fa4ed182	494	/**
richardv	0:b079fa4ed182	495	* @brief Sets or resets the update interrupt flag (UIF)status bit Remapping.
richardv	0:b079fa4ed182	496	* when sets, reading TIMx_CNT register returns UIF bit instead of CNT[31]
richardv	0:b079fa4ed182	497	* @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	498	* @param NewState: new state of the UIFREMAP bit.
richardv	0:b079fa4ed182	499	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	500	* @retval None
richardv	0:b079fa4ed182	501	*/
richardv	0:b079fa4ed182	502	void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	503	{
richardv	0:b079fa4ed182	504	/* Check the parameters */
richardv	0:b079fa4ed182	505	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	506	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	507
richardv	0:b079fa4ed182	508	if (NewState != DISABLE)
richardv	0:b079fa4ed182	509	{
richardv	0:b079fa4ed182	510	/* Enable the TIM Counter */
richardv	0:b079fa4ed182	511	TIMx->CR1 \|= TIM_CR1_UIFREMAP;
richardv	0:b079fa4ed182	512	}
richardv	0:b079fa4ed182	513	else
richardv	0:b079fa4ed182	514	{
richardv	0:b079fa4ed182	515	/* Disable the TIM Counter */
richardv	0:b079fa4ed182	516	TIMx->CR1 &= (uint16_t)~TIM_CR1_UIFREMAP;
richardv	0:b079fa4ed182	517	}
richardv	0:b079fa4ed182	518	}
richardv	0:b079fa4ed182	519
richardv	0:b079fa4ed182	520	/**
richardv	0:b079fa4ed182	521	* @brief Enables or disables TIMx peripheral Preload register on ARR.
richardv	0:b079fa4ed182	522	* @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	523	* @param NewState: new state of the TIMx peripheral Preload register
richardv	0:b079fa4ed182	524	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	525	* @retval None
richardv	0:b079fa4ed182	526	*/
richardv	0:b079fa4ed182	527	void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	528	{
richardv	0:b079fa4ed182	529	/* Check the parameters */
richardv	0:b079fa4ed182	530	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	531	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	532
richardv	0:b079fa4ed182	533	if (NewState != DISABLE)
richardv	0:b079fa4ed182	534	{
richardv	0:b079fa4ed182	535	/* Set the ARR Preload Bit */
richardv	0:b079fa4ed182	536	TIMx->CR1 \|= TIM_CR1_ARPE;
richardv	0:b079fa4ed182	537	}
richardv	0:b079fa4ed182	538	else
richardv	0:b079fa4ed182	539	{
richardv	0:b079fa4ed182	540	/* Reset the ARR Preload Bit */
richardv	0:b079fa4ed182	541	TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
richardv	0:b079fa4ed182	542	}
richardv	0:b079fa4ed182	543	}
richardv	0:b079fa4ed182	544
richardv	0:b079fa4ed182	545	/**
richardv	0:b079fa4ed182	546	* @brief Selects the TIMx's One Pulse Mode.
richardv	0:b079fa4ed182	547	* @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	548	* @param TIM_OPMode: specifies the OPM Mode to be used.
richardv	0:b079fa4ed182	549	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	550	* @arg TIM_OPMode_Single
richardv	0:b079fa4ed182	551	* @arg TIM_OPMode_Repetitive
richardv	0:b079fa4ed182	552	* @retval None
richardv	0:b079fa4ed182	553	*/
richardv	0:b079fa4ed182	554	void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
richardv	0:b079fa4ed182	555	{
richardv	0:b079fa4ed182	556	/* Check the parameters */
richardv	0:b079fa4ed182	557	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	558	assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
richardv	0:b079fa4ed182	559
richardv	0:b079fa4ed182	560	/* Reset the OPM Bit */
richardv	0:b079fa4ed182	561	TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
richardv	0:b079fa4ed182	562
richardv	0:b079fa4ed182	563	/* Configure the OPM Mode */
richardv	0:b079fa4ed182	564	TIMx->CR1 \|= TIM_OPMode;
richardv	0:b079fa4ed182	565	}
richardv	0:b079fa4ed182	566
richardv	0:b079fa4ed182	567	/**
richardv	0:b079fa4ed182	568	* @brief Sets the TIMx Clock Division value.
richardv	0:b079fa4ed182	569	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral.
richardv	0:b079fa4ed182	570	* @param TIM_CKD: specifies the clock division value.
richardv	0:b079fa4ed182	571	* This parameter can be one of the following value:
richardv	0:b079fa4ed182	572	* @arg TIM_CKD_DIV1: TDTS = Tck_tim
richardv	0:b079fa4ed182	573	* @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
richardv	0:b079fa4ed182	574	* @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
richardv	0:b079fa4ed182	575	* @retval None
richardv	0:b079fa4ed182	576	*/
richardv	0:b079fa4ed182	577	void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
richardv	0:b079fa4ed182	578	{
richardv	0:b079fa4ed182	579	/* Check the parameters */
richardv	0:b079fa4ed182	580	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	581	assert_param(IS_TIM_CKD_DIV(TIM_CKD));
richardv	0:b079fa4ed182	582
richardv	0:b079fa4ed182	583	/* Reset the CKD Bits */
richardv	0:b079fa4ed182	584	TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
richardv	0:b079fa4ed182	585
richardv	0:b079fa4ed182	586	/* Set the CKD value */
richardv	0:b079fa4ed182	587	TIMx->CR1 \|= TIM_CKD;
richardv	0:b079fa4ed182	588	}
richardv	0:b079fa4ed182	589
richardv	0:b079fa4ed182	590	/**
richardv	0:b079fa4ed182	591	* @brief Enables or disables the specified TIM peripheral.
richardv	0:b079fa4ed182	592	* @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select
richardv	0:b079fa4ed182	593	* the TIMx peripheral.
richardv	0:b079fa4ed182	594	* @param NewState: new state of the TIMx peripheral.
richardv	0:b079fa4ed182	595	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	596	* @retval None
richardv	0:b079fa4ed182	597	*/
richardv	0:b079fa4ed182	598	void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	599	{
richardv	0:b079fa4ed182	600	/* Check the parameters */
richardv	0:b079fa4ed182	601	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	602	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	603
richardv	0:b079fa4ed182	604	if (NewState != DISABLE)
richardv	0:b079fa4ed182	605	{
richardv	0:b079fa4ed182	606	/* Enable the TIM Counter */
richardv	0:b079fa4ed182	607	TIMx->CR1 \|= TIM_CR1_CEN;
richardv	0:b079fa4ed182	608	}
richardv	0:b079fa4ed182	609	else
richardv	0:b079fa4ed182	610	{
richardv	0:b079fa4ed182	611	/* Disable the TIM Counter */
richardv	0:b079fa4ed182	612	TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
richardv	0:b079fa4ed182	613	}
richardv	0:b079fa4ed182	614	}
richardv	0:b079fa4ed182	615	/**
richardv	0:b079fa4ed182	616	* @}
richardv	0:b079fa4ed182	617	*/
richardv	0:b079fa4ed182	618
richardv	0:b079fa4ed182	619	/** @defgroup TIM_Group2 Output Compare management functions
richardv	0:b079fa4ed182	620	* @brief Output Compare management functions
richardv	0:b079fa4ed182	621	*
richardv	0:b079fa4ed182	622	@verbatim
richardv	0:b079fa4ed182	623	===============================================================================
richardv	0:b079fa4ed182	624	##### Output Compare management functions #####
richardv	0:b079fa4ed182	625	===============================================================================
richardv	0:b079fa4ed182	626
richardv	0:b079fa4ed182	627	* TIM Driver: how to use it in Output Compare Mode *
richardv	0:b079fa4ed182	628	========================================================
richardv	0:b079fa4ed182	629	[..]
richardv	0:b079fa4ed182	630	To use the Timer in Output Compare mode, the following steps are mandatory:
richardv	0:b079fa4ed182	631
richardv	0:b079fa4ed182	632	(#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
richardv	0:b079fa4ed182	633
richardv	0:b079fa4ed182	634	(#) Configure the TIM pins by configuring the corresponding GPIO pins
richardv	0:b079fa4ed182	635
richardv	0:b079fa4ed182	636	(#) Configure the Time base unit as described in the first part of this driver,
richardv	0:b079fa4ed182	637	if needed, else the Timer will run with the default configuration:
richardv	0:b079fa4ed182	638	(++) Autoreload value = 0xFFFF
richardv	0:b079fa4ed182	639	(++) Prescaler value = 0x0000
richardv	0:b079fa4ed182	640	(++) Counter mode = Up counting
richardv	0:b079fa4ed182	641	(++) Clock Division = TIM_CKD_DIV1
richardv	0:b079fa4ed182	642	(#) Fill the TIM_OCInitStruct with the desired parameters including:
richardv	0:b079fa4ed182	643	(++) The TIM Output Compare mode: TIM_OCMode
richardv	0:b079fa4ed182	644	(++) TIM Output State: TIM_OutputState
richardv	0:b079fa4ed182	645	(++) TIM Pulse value: TIM_Pulse
richardv	0:b079fa4ed182	646	(++) TIM Output Compare Polarity : TIM_OCPolarity
richardv	0:b079fa4ed182	647
richardv	0:b079fa4ed182	648	(#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the
richardv	0:b079fa4ed182	649	corresponding configuration
richardv	0:b079fa4ed182	650
richardv	0:b079fa4ed182	651	(#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
richardv	0:b079fa4ed182	652	[..]
richardv	0:b079fa4ed182	653	(@) All other functions can be used separately to modify, if needed,
richardv	0:b079fa4ed182	654	a specific feature of the Timer.
richardv	0:b079fa4ed182	655
richardv	0:b079fa4ed182	656	(@) In case of PWM mode, this function is mandatory:
richardv	0:b079fa4ed182	657	TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
richardv	0:b079fa4ed182	658
richardv	0:b079fa4ed182	659	(@) If the corresponding interrupt or DMA request are needed, the user should:
richardv	0:b079fa4ed182	660	(#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
richardv	0:b079fa4ed182	661	(#@) Enable the corresponding interrupt (or DMA request) using the function
richardv	0:b079fa4ed182	662	TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
richardv	0:b079fa4ed182	663
richardv	0:b079fa4ed182	664	@endverbatim
richardv	0:b079fa4ed182	665	* @{
richardv	0:b079fa4ed182	666	*/
richardv	0:b079fa4ed182	667
richardv	0:b079fa4ed182	668	/**
richardv	0:b079fa4ed182	669	* @brief Initializes the TIMx Channel1 according to the specified parameters in
richardv	0:b079fa4ed182	670	* the TIM_OCInitStruct.
richardv	0:b079fa4ed182	671	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral.
richardv	0:b079fa4ed182	672	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
richardv	0:b079fa4ed182	673	* the configuration information for the specified TIM peripheral.
richardv	0:b079fa4ed182	674	* @retval None
richardv	0:b079fa4ed182	675	*/
richardv	0:b079fa4ed182	676	void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
richardv	0:b079fa4ed182	677	{
richardv	0:b079fa4ed182	678	uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
richardv	0:b079fa4ed182	679
richardv	0:b079fa4ed182	680	/* Check the parameters */
richardv	0:b079fa4ed182	681	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	682	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
richardv	0:b079fa4ed182	683	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
richardv	0:b079fa4ed182	684	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
richardv	0:b079fa4ed182	685
richardv	0:b079fa4ed182	686	/* Disable the Channel 1: Reset the CC1E Bit */
richardv	0:b079fa4ed182	687	TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
richardv	0:b079fa4ed182	688
richardv	0:b079fa4ed182	689	/* Get the TIMx CCER register value */
richardv	0:b079fa4ed182	690	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	691	/* Get the TIMx CR2 register value */
richardv	0:b079fa4ed182	692	tmpcr2 = TIMx->CR2;
richardv	0:b079fa4ed182	693
richardv	0:b079fa4ed182	694	/* Get the TIMx CCMR1 register value */
richardv	0:b079fa4ed182	695	tmpccmrx = TIMx->CCMR1;
richardv	0:b079fa4ed182	696
richardv	0:b079fa4ed182	697	/* Reset the Output Compare Mode Bits */
richardv	0:b079fa4ed182	698	tmpccmrx &= (uint32_t)~TIM_CCMR1_OC1M;
richardv	0:b079fa4ed182	699	tmpccmrx &= (uint32_t)~TIM_CCMR1_CC1S;
richardv	0:b079fa4ed182	700	/* Select the Output Compare Mode */
richardv	0:b079fa4ed182	701	tmpccmrx \|= TIM_OCInitStruct->TIM_OCMode;
richardv	0:b079fa4ed182	702
richardv	0:b079fa4ed182	703	/* Reset the Output Polarity level */
richardv	0:b079fa4ed182	704	tmpccer &= (uint32_t)~TIM_CCER_CC1P;
richardv	0:b079fa4ed182	705	/* Set the Output Compare Polarity */
richardv	0:b079fa4ed182	706	tmpccer \|= TIM_OCInitStruct->TIM_OCPolarity;
richardv	0:b079fa4ed182	707
richardv	0:b079fa4ed182	708	/* Set the Output State */
richardv	0:b079fa4ed182	709	tmpccer \|= TIM_OCInitStruct->TIM_OutputState;
richardv	0:b079fa4ed182	710
richardv	0:b079fa4ed182	711	if((TIMx == TIM1) \|\| (TIMx == TIM8) \|\| (TIMx == TIM15) \|\| (TIMx == TIM16) \|\| (TIMx == TIM17))
richardv	0:b079fa4ed182	712	{
richardv	0:b079fa4ed182	713	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
richardv	0:b079fa4ed182	714	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
richardv	0:b079fa4ed182	715	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
richardv	0:b079fa4ed182	716	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
richardv	0:b079fa4ed182	717
richardv	0:b079fa4ed182	718	/* Reset the Output N Polarity level */
richardv	0:b079fa4ed182	719	tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
richardv	0:b079fa4ed182	720	/* Set the Output N Polarity */
richardv	0:b079fa4ed182	721	tmpccer \|= TIM_OCInitStruct->TIM_OCNPolarity;
richardv	0:b079fa4ed182	722	/* Reset the Output N State */
richardv	0:b079fa4ed182	723	tmpccer &= (uint32_t)~TIM_CCER_CC1NE;
richardv	0:b079fa4ed182	724
richardv	0:b079fa4ed182	725	/* Set the Output N State */
richardv	0:b079fa4ed182	726	tmpccer \|= TIM_OCInitStruct->TIM_OutputNState;
richardv	0:b079fa4ed182	727	/* Reset the Output Compare and Output Compare N IDLE State */
richardv	0:b079fa4ed182	728	tmpcr2 &= (uint32_t)~TIM_CR2_OIS1;
richardv	0:b079fa4ed182	729	tmpcr2 &= (uint32_t)~TIM_CR2_OIS1N;
richardv	0:b079fa4ed182	730	/* Set the Output Idle state */
richardv	0:b079fa4ed182	731	tmpcr2 \|= TIM_OCInitStruct->TIM_OCIdleState;
richardv	0:b079fa4ed182	732	/* Set the Output N Idle state */
richardv	0:b079fa4ed182	733	tmpcr2 \|= TIM_OCInitStruct->TIM_OCNIdleState;
richardv	0:b079fa4ed182	734	}
richardv	0:b079fa4ed182	735	/* Write to TIMx CR2 */
richardv	0:b079fa4ed182	736	TIMx->CR2 = tmpcr2;
richardv	0:b079fa4ed182	737
richardv	0:b079fa4ed182	738	/* Write to TIMx CCMR1 */
richardv	0:b079fa4ed182	739	TIMx->CCMR1 = tmpccmrx;
richardv	0:b079fa4ed182	740
richardv	0:b079fa4ed182	741	/* Set the Capture Compare Register value */
richardv	0:b079fa4ed182	742	TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
richardv	0:b079fa4ed182	743
richardv	0:b079fa4ed182	744	/* Write to TIMx CCER */
richardv	0:b079fa4ed182	745	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	746	}
richardv	0:b079fa4ed182	747
richardv	0:b079fa4ed182	748	/**
richardv	0:b079fa4ed182	749	* @brief Initializes the TIMx Channel2 according to the specified parameters
richardv	0:b079fa4ed182	750	* in the TIM_OCInitStruct.
richardv	0:b079fa4ed182	751	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
richardv	0:b079fa4ed182	752	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
richardv	0:b079fa4ed182	753	* the configuration information for the specified TIM peripheral.
richardv	0:b079fa4ed182	754	* @retval None
richardv	0:b079fa4ed182	755	*/
richardv	0:b079fa4ed182	756	void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
richardv	0:b079fa4ed182	757	{
richardv	0:b079fa4ed182	758	uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
richardv	0:b079fa4ed182	759
richardv	0:b079fa4ed182	760	/* Check the parameters */
richardv	0:b079fa4ed182	761	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	762	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
richardv	0:b079fa4ed182	763	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
richardv	0:b079fa4ed182	764	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
richardv	0:b079fa4ed182	765
richardv	0:b079fa4ed182	766	/* Disable the Channel 2: Reset the CC2E Bit */
richardv	0:b079fa4ed182	767	TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
richardv	0:b079fa4ed182	768
richardv	0:b079fa4ed182	769	/* Get the TIMx CCER register value */
richardv	0:b079fa4ed182	770	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	771	/* Get the TIMx CR2 register value */
richardv	0:b079fa4ed182	772	tmpcr2 = TIMx->CR2;
richardv	0:b079fa4ed182	773
richardv	0:b079fa4ed182	774	/* Get the TIMx CCMR1 register value */
richardv	0:b079fa4ed182	775	tmpccmrx = TIMx->CCMR1;
richardv	0:b079fa4ed182	776
richardv	0:b079fa4ed182	777	/* Reset the Output Compare mode and Capture/Compare selection Bits */
richardv	0:b079fa4ed182	778	tmpccmrx &= (uint32_t)~TIM_CCMR1_OC2M;
richardv	0:b079fa4ed182	779	tmpccmrx &= (uint32_t)~TIM_CCMR1_CC2S;
richardv	0:b079fa4ed182	780
richardv	0:b079fa4ed182	781	/* Select the Output Compare Mode */
richardv	0:b079fa4ed182	782	tmpccmrx \|= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
richardv	0:b079fa4ed182	783
richardv	0:b079fa4ed182	784	/* Reset the Output Polarity level */
richardv	0:b079fa4ed182	785	tmpccer &= (uint32_t)~TIM_CCER_CC2P;
richardv	0:b079fa4ed182	786	/* Set the Output Compare Polarity */
richardv	0:b079fa4ed182	787	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 4);
richardv	0:b079fa4ed182	788
richardv	0:b079fa4ed182	789	/* Set the Output State */
richardv	0:b079fa4ed182	790	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 4);
richardv	0:b079fa4ed182	791
richardv	0:b079fa4ed182	792	if((TIMx == TIM1) \|\| (TIMx == TIM8))
richardv	0:b079fa4ed182	793	{
richardv	0:b079fa4ed182	794	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
richardv	0:b079fa4ed182	795	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
richardv	0:b079fa4ed182	796	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
richardv	0:b079fa4ed182	797	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
richardv	0:b079fa4ed182	798
richardv	0:b079fa4ed182	799	/* Reset the Output N Polarity level */
richardv	0:b079fa4ed182	800	tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
richardv	0:b079fa4ed182	801	/* Set the Output N Polarity */
richardv	0:b079fa4ed182	802	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 4);
richardv	0:b079fa4ed182	803	/* Reset the Output N State */
richardv	0:b079fa4ed182	804	tmpccer &= (uint32_t)~TIM_CCER_CC2NE;
richardv	0:b079fa4ed182	805
richardv	0:b079fa4ed182	806	/* Set the Output N State */
richardv	0:b079fa4ed182	807	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 4);
richardv	0:b079fa4ed182	808	/* Reset the Output Compare and Output Compare N IDLE State */
richardv	0:b079fa4ed182	809	tmpcr2 &= (uint32_t)~TIM_CR2_OIS2;
richardv	0:b079fa4ed182	810	tmpcr2 &= (uint32_t)~TIM_CR2_OIS2N;
richardv	0:b079fa4ed182	811	/* Set the Output Idle state */
richardv	0:b079fa4ed182	812	tmpcr2 \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 2);
richardv	0:b079fa4ed182	813	/* Set the Output N Idle state */
richardv	0:b079fa4ed182	814	tmpcr2 \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 2);
richardv	0:b079fa4ed182	815	}
richardv	0:b079fa4ed182	816	/* Write to TIMx CR2 */
richardv	0:b079fa4ed182	817	TIMx->CR2 = tmpcr2;
richardv	0:b079fa4ed182	818
richardv	0:b079fa4ed182	819	/* Write to TIMx CCMR1 */
richardv	0:b079fa4ed182	820	TIMx->CCMR1 = tmpccmrx;
richardv	0:b079fa4ed182	821
richardv	0:b079fa4ed182	822	/* Set the Capture Compare Register value */
richardv	0:b079fa4ed182	823	TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
richardv	0:b079fa4ed182	824
richardv	0:b079fa4ed182	825	/* Write to TIMx CCER */
richardv	0:b079fa4ed182	826	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	827	}
richardv	0:b079fa4ed182	828
richardv	0:b079fa4ed182	829	/**
richardv	0:b079fa4ed182	830	* @brief Initializes the TIMx Channel3 according to the specified parameters
richardv	0:b079fa4ed182	831	* in the TIM_OCInitStruct.
richardv	0:b079fa4ed182	832	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	833	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
richardv	0:b079fa4ed182	834	* the configuration information for the specified TIM peripheral.
richardv	0:b079fa4ed182	835	* @retval None
richardv	0:b079fa4ed182	836	*/
richardv	0:b079fa4ed182	837	void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
richardv	0:b079fa4ed182	838	{
richardv	0:b079fa4ed182	839	uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
richardv	0:b079fa4ed182	840
richardv	0:b079fa4ed182	841	/* Check the parameters */
richardv	0:b079fa4ed182	842	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	843	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
richardv	0:b079fa4ed182	844	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
richardv	0:b079fa4ed182	845	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
richardv	0:b079fa4ed182	846
richardv	0:b079fa4ed182	847	/* Disable the Channel 3: Reset the CC2E Bit */
richardv	0:b079fa4ed182	848	TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
richardv	0:b079fa4ed182	849
richardv	0:b079fa4ed182	850	/* Get the TIMx CCER register value */
richardv	0:b079fa4ed182	851	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	852	/* Get the TIMx CR2 register value */
richardv	0:b079fa4ed182	853	tmpcr2 = TIMx->CR2;
richardv	0:b079fa4ed182	854
richardv	0:b079fa4ed182	855	/* Get the TIMx CCMR2 register value */
richardv	0:b079fa4ed182	856	tmpccmrx = TIMx->CCMR2;
richardv	0:b079fa4ed182	857
richardv	0:b079fa4ed182	858	/* Reset the Output Compare mode and Capture/Compare selection Bits */
richardv	0:b079fa4ed182	859	tmpccmrx &= (uint32_t)~TIM_CCMR2_OC3M;
richardv	0:b079fa4ed182	860	tmpccmrx &= (uint32_t)~TIM_CCMR2_CC3S;
richardv	0:b079fa4ed182	861	/* Select the Output Compare Mode */
richardv	0:b079fa4ed182	862	tmpccmrx \|= TIM_OCInitStruct->TIM_OCMode;
richardv	0:b079fa4ed182	863
richardv	0:b079fa4ed182	864	/* Reset the Output Polarity level */
richardv	0:b079fa4ed182	865	tmpccer &= (uint32_t)~TIM_CCER_CC3P;
richardv	0:b079fa4ed182	866	/* Set the Output Compare Polarity */
richardv	0:b079fa4ed182	867	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 8);
richardv	0:b079fa4ed182	868
richardv	0:b079fa4ed182	869	/* Set the Output State */
richardv	0:b079fa4ed182	870	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 8);
richardv	0:b079fa4ed182	871
richardv	0:b079fa4ed182	872	if((TIMx == TIM1) \|\| (TIMx == TIM8))
richardv	0:b079fa4ed182	873	{
richardv	0:b079fa4ed182	874	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
richardv	0:b079fa4ed182	875	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
richardv	0:b079fa4ed182	876	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
richardv	0:b079fa4ed182	877	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
richardv	0:b079fa4ed182	878
richardv	0:b079fa4ed182	879	/* Reset the Output N Polarity level */
richardv	0:b079fa4ed182	880	tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
richardv	0:b079fa4ed182	881	/* Set the Output N Polarity */
richardv	0:b079fa4ed182	882	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 8);
richardv	0:b079fa4ed182	883	/* Reset the Output N State */
richardv	0:b079fa4ed182	884	tmpccer &= (uint32_t)~TIM_CCER_CC3NE;
richardv	0:b079fa4ed182	885
richardv	0:b079fa4ed182	886	/* Set the Output N State */
richardv	0:b079fa4ed182	887	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 8);
richardv	0:b079fa4ed182	888	/* Reset the Output Compare and Output Compare N IDLE State */
richardv	0:b079fa4ed182	889	tmpcr2 &= (uint32_t)~TIM_CR2_OIS3;
richardv	0:b079fa4ed182	890	tmpcr2 &= (uint32_t)~TIM_CR2_OIS3N;
richardv	0:b079fa4ed182	891	/* Set the Output Idle state */
richardv	0:b079fa4ed182	892	tmpcr2 \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 4);
richardv	0:b079fa4ed182	893	/* Set the Output N Idle state */
richardv	0:b079fa4ed182	894	tmpcr2 \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 4);
richardv	0:b079fa4ed182	895	}
richardv	0:b079fa4ed182	896	/* Write to TIMx CR2 */
richardv	0:b079fa4ed182	897	TIMx->CR2 = tmpcr2;
richardv	0:b079fa4ed182	898
richardv	0:b079fa4ed182	899	/* Write to TIMx CCMR2 */
richardv	0:b079fa4ed182	900	TIMx->CCMR2 = tmpccmrx;
richardv	0:b079fa4ed182	901
richardv	0:b079fa4ed182	902	/* Set the Capture Compare Register value */
richardv	0:b079fa4ed182	903	TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
richardv	0:b079fa4ed182	904
richardv	0:b079fa4ed182	905	/* Write to TIMx CCER */
richardv	0:b079fa4ed182	906	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	907	}
richardv	0:b079fa4ed182	908
richardv	0:b079fa4ed182	909	/**
richardv	0:b079fa4ed182	910	* @brief Initializes the TIMx Channel4 according to the specified parameters
richardv	0:b079fa4ed182	911	* in the TIM_OCInitStruct.
richardv	0:b079fa4ed182	912	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	913	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
richardv	0:b079fa4ed182	914	* the configuration information for the specified TIM peripheral.
richardv	0:b079fa4ed182	915	* @retval None
richardv	0:b079fa4ed182	916	*/
richardv	0:b079fa4ed182	917	void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
richardv	0:b079fa4ed182	918	{
richardv	0:b079fa4ed182	919	uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
richardv	0:b079fa4ed182	920
richardv	0:b079fa4ed182	921	/* Check the parameters */
richardv	0:b079fa4ed182	922	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	923	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
richardv	0:b079fa4ed182	924	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
richardv	0:b079fa4ed182	925	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
richardv	0:b079fa4ed182	926
richardv	0:b079fa4ed182	927	/* Disable the Channel 4: Reset the CC4E Bit */
richardv	0:b079fa4ed182	928	TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
richardv	0:b079fa4ed182	929
richardv	0:b079fa4ed182	930	/* Get the TIMx CCER register value */
richardv	0:b079fa4ed182	931	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	932	/* Get the TIMx CR2 register value */
richardv	0:b079fa4ed182	933	tmpcr2 = TIMx->CR2;
richardv	0:b079fa4ed182	934
richardv	0:b079fa4ed182	935	/* Get the TIMx CCMR2 register value */
richardv	0:b079fa4ed182	936	tmpccmrx = TIMx->CCMR2;
richardv	0:b079fa4ed182	937
richardv	0:b079fa4ed182	938	/* Reset the Output Compare mode and Capture/Compare selection Bits */
richardv	0:b079fa4ed182	939	tmpccmrx &= (uint32_t)~TIM_CCMR2_OC4M;
richardv	0:b079fa4ed182	940	tmpccmrx &= (uint32_t)~TIM_CCMR2_CC4S;
richardv	0:b079fa4ed182	941
richardv	0:b079fa4ed182	942	/* Select the Output Compare Mode */
richardv	0:b079fa4ed182	943	tmpccmrx \|= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
richardv	0:b079fa4ed182	944
richardv	0:b079fa4ed182	945	/* Reset the Output Polarity level */
richardv	0:b079fa4ed182	946	tmpccer &= (uint32_t)~TIM_CCER_CC4P;
richardv	0:b079fa4ed182	947	/* Set the Output Compare Polarity */
richardv	0:b079fa4ed182	948	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 12);
richardv	0:b079fa4ed182	949
richardv	0:b079fa4ed182	950	/* Set the Output State */
richardv	0:b079fa4ed182	951	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 12);
richardv	0:b079fa4ed182	952
richardv	0:b079fa4ed182	953	if((TIMx == TIM1) \|\| (TIMx == TIM8))
richardv	0:b079fa4ed182	954	{
richardv	0:b079fa4ed182	955	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
richardv	0:b079fa4ed182	956	/* Reset the Output Compare IDLE State */
richardv	0:b079fa4ed182	957	tmpcr2 &=(uint32_t) ~TIM_CR2_OIS4;
richardv	0:b079fa4ed182	958	/* Set the Output Idle state */
richardv	0:b079fa4ed182	959	tmpcr2 \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 6);
richardv	0:b079fa4ed182	960	}
richardv	0:b079fa4ed182	961	/* Write to TIMx CR2 */
richardv	0:b079fa4ed182	962	TIMx->CR2 = tmpcr2;
richardv	0:b079fa4ed182	963
richardv	0:b079fa4ed182	964	/* Write to TIMx CCMR2 */
richardv	0:b079fa4ed182	965	TIMx->CCMR2 = tmpccmrx;
richardv	0:b079fa4ed182	966
richardv	0:b079fa4ed182	967	/* Set the Capture Compare Register value */
richardv	0:b079fa4ed182	968	TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
richardv	0:b079fa4ed182	969
richardv	0:b079fa4ed182	970	/* Write to TIMx CCER */
richardv	0:b079fa4ed182	971	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	972	}
richardv	0:b079fa4ed182	973
richardv	0:b079fa4ed182	974	/**
richardv	0:b079fa4ed182	975	* @brief Initializes the TIMx Channel5 according to the specified parameters
richardv	0:b079fa4ed182	976	* in the TIM_OCInitStruct.
richardv	0:b079fa4ed182	977	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	978	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
richardv	0:b079fa4ed182	979	* the configuration information for the specified TIM peripheral.
richardv	0:b079fa4ed182	980	* @retval None
richardv	0:b079fa4ed182	981	*/
richardv	0:b079fa4ed182	982	void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
richardv	0:b079fa4ed182	983	{
richardv	0:b079fa4ed182	984	uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
richardv	0:b079fa4ed182	985
richardv	0:b079fa4ed182	986	/* Check the parameters */
richardv	0:b079fa4ed182	987	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	988	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
richardv	0:b079fa4ed182	989	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
richardv	0:b079fa4ed182	990	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
richardv	0:b079fa4ed182	991
richardv	0:b079fa4ed182	992	/* Disable the Channel 5: Reset the CC5E Bit */
richardv	0:b079fa4ed182	993	TIMx->CCER &= (uint32_t)~TIM_CCER_CC5E; /* to be verified*/
richardv	0:b079fa4ed182	994
richardv	0:b079fa4ed182	995	/* Get the TIMx CCER register value */
richardv	0:b079fa4ed182	996	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	997	/* Get the TIMx CR2 register value */
richardv	0:b079fa4ed182	998	tmpcr2 = TIMx->CR2;
richardv	0:b079fa4ed182	999
richardv	0:b079fa4ed182	1000	/* Get the TIMx CCMR3 register value */
richardv	0:b079fa4ed182	1001	tmpccmrx = TIMx->CCMR3;
richardv	0:b079fa4ed182	1002
richardv	0:b079fa4ed182	1003	/* Reset the Output Compare mode and Capture/Compare selection Bits */
richardv	0:b079fa4ed182	1004	tmpccmrx &= (uint32_t)~TIM_CCMR3_OC5M;
richardv	0:b079fa4ed182	1005
richardv	0:b079fa4ed182	1006	/* Select the Output Compare Mode */
richardv	0:b079fa4ed182	1007	tmpccmrx \|= (uint32_t)(TIM_OCInitStruct->TIM_OCMode);
richardv	0:b079fa4ed182	1008
richardv	0:b079fa4ed182	1009	/* Reset the Output Polarity level */
richardv	0:b079fa4ed182	1010	tmpccer &= (uint32_t)~TIM_CCER_CC5P;
richardv	0:b079fa4ed182	1011	/* Set the Output Compare Polarity */
richardv	0:b079fa4ed182	1012	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 16);
richardv	0:b079fa4ed182	1013
richardv	0:b079fa4ed182	1014	/* Set the Output State */
richardv	0:b079fa4ed182	1015	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 16);
richardv	0:b079fa4ed182	1016
richardv	0:b079fa4ed182	1017	if((TIMx == TIM1) \|\| (TIMx == TIM8))
richardv	0:b079fa4ed182	1018	{
richardv	0:b079fa4ed182	1019	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
richardv	0:b079fa4ed182	1020	/* Reset the Output Compare IDLE State */
richardv	0:b079fa4ed182	1021	tmpcr2 &=(uint32_t) ~TIM_CR2_OIS5;
richardv	0:b079fa4ed182	1022	/* Set the Output Idle state */
richardv	0:b079fa4ed182	1023	tmpcr2 \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 16);
richardv	0:b079fa4ed182	1024	}
richardv	0:b079fa4ed182	1025	/* Write to TIMx CR2 */
richardv	0:b079fa4ed182	1026	TIMx->CR2 = tmpcr2;
richardv	0:b079fa4ed182	1027
richardv	0:b079fa4ed182	1028	/* Write to TIMx CCMR2 */
richardv	0:b079fa4ed182	1029	TIMx->CCMR3 = tmpccmrx;
richardv	0:b079fa4ed182	1030
richardv	0:b079fa4ed182	1031	/* Set the Capture Compare Register value */
richardv	0:b079fa4ed182	1032	TIMx->CCR5 = TIM_OCInitStruct->TIM_Pulse;
richardv	0:b079fa4ed182	1033
richardv	0:b079fa4ed182	1034	/* Write to TIMx CCER */
richardv	0:b079fa4ed182	1035	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	1036	}
richardv	0:b079fa4ed182	1037
richardv	0:b079fa4ed182	1038	/**
richardv	0:b079fa4ed182	1039	* @brief Initializes the TIMx Channel6 according to the specified parameters
richardv	0:b079fa4ed182	1040	* in the TIM_OCInitStruct.
richardv	0:b079fa4ed182	1041	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1042	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
richardv	0:b079fa4ed182	1043	* the configuration information for the specified TIM peripheral.
richardv	0:b079fa4ed182	1044	* @retval None
richardv	0:b079fa4ed182	1045	*/
richardv	0:b079fa4ed182	1046	void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
richardv	0:b079fa4ed182	1047	{
richardv	0:b079fa4ed182	1048	uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
richardv	0:b079fa4ed182	1049
richardv	0:b079fa4ed182	1050	/* Check the parameters */
richardv	0:b079fa4ed182	1051	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1052	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
richardv	0:b079fa4ed182	1053	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
richardv	0:b079fa4ed182	1054	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
richardv	0:b079fa4ed182	1055
richardv	0:b079fa4ed182	1056	/* Disable the Channel 5: Reset the CC5E Bit */
richardv	0:b079fa4ed182	1057	TIMx->CCER &= (uint32_t)~TIM_CCER_CC6E; /* to be verified*/
richardv	0:b079fa4ed182	1058
richardv	0:b079fa4ed182	1059	/* Get the TIMx CCER register value */
richardv	0:b079fa4ed182	1060	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	1061	/* Get the TIMx CR2 register value */
richardv	0:b079fa4ed182	1062	tmpcr2 = TIMx->CR2;
richardv	0:b079fa4ed182	1063
richardv	0:b079fa4ed182	1064	/* Get the TIMx CCMR3 register value */
richardv	0:b079fa4ed182	1065	tmpccmrx = TIMx->CCMR3;
richardv	0:b079fa4ed182	1066
richardv	0:b079fa4ed182	1067	/* Reset the Output Compare mode and Capture/Compare selection Bits */
richardv	0:b079fa4ed182	1068	tmpccmrx &= (uint32_t)~TIM_CCMR3_OC6M;
richardv	0:b079fa4ed182	1069
richardv	0:b079fa4ed182	1070	/* Select the Output Compare Mode */
richardv	0:b079fa4ed182	1071	tmpccmrx \|= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
richardv	0:b079fa4ed182	1072
richardv	0:b079fa4ed182	1073	/* Reset the Output Polarity level */
richardv	0:b079fa4ed182	1074	tmpccer &= (uint32_t)~TIM_CCER_CC6P;
richardv	0:b079fa4ed182	1075	/* Set the Output Compare Polarity */
richardv	0:b079fa4ed182	1076	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 20);
richardv	0:b079fa4ed182	1077
richardv	0:b079fa4ed182	1078	/* Set the Output State */
richardv	0:b079fa4ed182	1079	tmpccer \|= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 20);
richardv	0:b079fa4ed182	1080
richardv	0:b079fa4ed182	1081	if((TIMx == TIM1) \|\| (TIMx == TIM8))
richardv	0:b079fa4ed182	1082	{
richardv	0:b079fa4ed182	1083	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
richardv	0:b079fa4ed182	1084	/* Reset the Output Compare IDLE State */
richardv	0:b079fa4ed182	1085	tmpcr2 &=(uint32_t) ~TIM_CR2_OIS6;
richardv	0:b079fa4ed182	1086	/* Set the Output Idle state */
richardv	0:b079fa4ed182	1087	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 18);
richardv	0:b079fa4ed182	1088	}
richardv	0:b079fa4ed182	1089	/* Write to TIMx CR2 */
richardv	0:b079fa4ed182	1090	TIMx->CR2 = tmpcr2;
richardv	0:b079fa4ed182	1091
richardv	0:b079fa4ed182	1092	/* Write to TIMx CCMR2 */
richardv	0:b079fa4ed182	1093	TIMx->CCMR3 = tmpccmrx;
richardv	0:b079fa4ed182	1094
richardv	0:b079fa4ed182	1095	/* Set the Capture Compare Register value */
richardv	0:b079fa4ed182	1096	TIMx->CCR6 = TIM_OCInitStruct->TIM_Pulse;
richardv	0:b079fa4ed182	1097
richardv	0:b079fa4ed182	1098	/* Write to TIMx CCER */
richardv	0:b079fa4ed182	1099	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	1100	}
richardv	0:b079fa4ed182	1101
richardv	0:b079fa4ed182	1102	/**
richardv	0:b079fa4ed182	1103	* @brief Selects the TIM Group Channel 5 and Channel 1,
richardv	0:b079fa4ed182	1104	OC1REFC is the logical AND of OC1REFC and OC5REF.
richardv	0:b079fa4ed182	1105	* @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
richardv	0:b079fa4ed182	1106	* @param NewState: new state of the Commutation event.
richardv	0:b079fa4ed182	1107	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	1108	* @retval None
richardv	0:b079fa4ed182	1109	*/
richardv	0:b079fa4ed182	1110	void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	1111	{
richardv	0:b079fa4ed182	1112	/* Check the parameters */
richardv	0:b079fa4ed182	1113	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1114	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	1115
richardv	0:b079fa4ed182	1116	if (NewState != DISABLE)
richardv	0:b079fa4ed182	1117	{
richardv	0:b079fa4ed182	1118	/* Set the GC5C1 Bit */
richardv	0:b079fa4ed182	1119	TIMx->CCR5 \|= TIM_CCR5_GC5C1;
richardv	0:b079fa4ed182	1120	}
richardv	0:b079fa4ed182	1121	else
richardv	0:b079fa4ed182	1122	{
richardv	0:b079fa4ed182	1123	/* Reset the GC5C1 Bit */
richardv	0:b079fa4ed182	1124	TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C1;
richardv	0:b079fa4ed182	1125	}
richardv	0:b079fa4ed182	1126	}
richardv	0:b079fa4ed182	1127
richardv	0:b079fa4ed182	1128	/**
richardv	0:b079fa4ed182	1129	* @brief Selects the TIM Group Channel 5 and Channel 2,
richardv	0:b079fa4ed182	1130	OC2REFC is the logical AND of OC2REFC and OC5REF.
richardv	0:b079fa4ed182	1131	* @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
richardv	0:b079fa4ed182	1132	* @param NewState: new state of the Commutation event.
richardv	0:b079fa4ed182	1133	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	1134	* @retval None
richardv	0:b079fa4ed182	1135	*/
richardv	0:b079fa4ed182	1136	void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	1137	{
richardv	0:b079fa4ed182	1138	/* Check the parameters */
richardv	0:b079fa4ed182	1139	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1140	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	1141
richardv	0:b079fa4ed182	1142	if (NewState != DISABLE)
richardv	0:b079fa4ed182	1143	{
richardv	0:b079fa4ed182	1144	/* Set the GC5C2 Bit */
richardv	0:b079fa4ed182	1145	TIMx->CCR5 \|= TIM_CCR5_GC5C2;
richardv	0:b079fa4ed182	1146	}
richardv	0:b079fa4ed182	1147	else
richardv	0:b079fa4ed182	1148	{
richardv	0:b079fa4ed182	1149	/* Reset the GC5C2 Bit */
richardv	0:b079fa4ed182	1150	TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C2;
richardv	0:b079fa4ed182	1151	}
richardv	0:b079fa4ed182	1152	}
richardv	0:b079fa4ed182	1153
richardv	0:b079fa4ed182	1154
richardv	0:b079fa4ed182	1155	/**
richardv	0:b079fa4ed182	1156	* @brief Selects the TIM Group Channel 5 and Channel 3,
richardv	0:b079fa4ed182	1157	OC3REFC is the logical AND of OC3REFC and OC5REF.
richardv	0:b079fa4ed182	1158	* @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
richardv	0:b079fa4ed182	1159	* @param NewState: new state of the Commutation event.
richardv	0:b079fa4ed182	1160	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	1161	* @retval None
richardv	0:b079fa4ed182	1162	*/
richardv	0:b079fa4ed182	1163	void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	1164	{
richardv	0:b079fa4ed182	1165	/* Check the parameters */
richardv	0:b079fa4ed182	1166	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1167	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	1168
richardv	0:b079fa4ed182	1169	if (NewState != DISABLE)
richardv	0:b079fa4ed182	1170	{
richardv	0:b079fa4ed182	1171	/* Set the GC5C3 Bit */
richardv	0:b079fa4ed182	1172	TIMx->CCR5 \|= TIM_CCR5_GC5C3;
richardv	0:b079fa4ed182	1173	}
richardv	0:b079fa4ed182	1174	else
richardv	0:b079fa4ed182	1175	{
richardv	0:b079fa4ed182	1176	/* Reset the GC5C3 Bit */
richardv	0:b079fa4ed182	1177	TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C3;
richardv	0:b079fa4ed182	1178	}
richardv	0:b079fa4ed182	1179	}
richardv	0:b079fa4ed182	1180
richardv	0:b079fa4ed182	1181	/**
richardv	0:b079fa4ed182	1182	* @brief Fills each TIM_OCInitStruct member with its default value.
richardv	0:b079fa4ed182	1183	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
richardv	0:b079fa4ed182	1184	* be initialized.
richardv	0:b079fa4ed182	1185	* @retval None
richardv	0:b079fa4ed182	1186	*/
richardv	0:b079fa4ed182	1187	void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
richardv	0:b079fa4ed182	1188	{
richardv	0:b079fa4ed182	1189	/* Set the default configuration */
richardv	0:b079fa4ed182	1190	TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
richardv	0:b079fa4ed182	1191	TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
richardv	0:b079fa4ed182	1192	TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
richardv	0:b079fa4ed182	1193	TIM_OCInitStruct->TIM_Pulse = 0x00000000;
richardv	0:b079fa4ed182	1194	TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
richardv	0:b079fa4ed182	1195	TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
richardv	0:b079fa4ed182	1196	TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
richardv	0:b079fa4ed182	1197	TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
richardv	0:b079fa4ed182	1198	}
richardv	0:b079fa4ed182	1199
richardv	0:b079fa4ed182	1200	/**
richardv	0:b079fa4ed182	1201	* @brief Selects the TIM Output Compare Mode.
richardv	0:b079fa4ed182	1202	* @note This function disables the selected channel before changing the Output
richardv	0:b079fa4ed182	1203	* Compare Mode. If needed, user has to enable this channel using
richardv	0:b079fa4ed182	1204	* TIM_CCxCmd() and TIM_CCxNCmd() functions.
richardv	0:b079fa4ed182	1205	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	1206	* @param TIM_Channel: specifies the TIM Channel
richardv	0:b079fa4ed182	1207	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1208	* @arg TIM_Channel_1: TIM Channel 1
richardv	0:b079fa4ed182	1209	* @arg TIM_Channel_2: TIM Channel 2
richardv	0:b079fa4ed182	1210	* @arg TIM_Channel_3: TIM Channel 3
richardv	0:b079fa4ed182	1211	* @arg TIM_Channel_4: TIM Channel 4
richardv	0:b079fa4ed182	1212	* @param TIM_OCMode: specifies the TIM Output Compare Mode.
richardv	0:b079fa4ed182	1213	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1214	* @arg TIM_OCMode_Timing
richardv	0:b079fa4ed182	1215	* @arg TIM_OCMode_Active
richardv	0:b079fa4ed182	1216	* @arg TIM_OCMode_Toggle
richardv	0:b079fa4ed182	1217	* @arg TIM_OCMode_PWM1
richardv	0:b079fa4ed182	1218	* @arg TIM_OCMode_PWM2
richardv	0:b079fa4ed182	1219	* @arg TIM_ForcedAction_Active
richardv	0:b079fa4ed182	1220	* @arg TIM_ForcedAction_InActive
richardv	0:b079fa4ed182	1221	* @arg TIM_OCMode_Retrigerrable_OPM1
richardv	0:b079fa4ed182	1222	* @arg TIM_OCMode_Retrigerrable_OPM2
richardv	0:b079fa4ed182	1223	* @arg TIM_OCMode_Combined_PWM1
richardv	0:b079fa4ed182	1224	* @arg TIM_OCMode_Combined_PWM2
richardv	0:b079fa4ed182	1225	* @arg TIM_OCMode_Asymmetric_PWM1
richardv	0:b079fa4ed182	1226	* @arg TIM_OCMode_Asymmetric_PWM2
richardv	0:b079fa4ed182	1227	* @retval None
richardv	0:b079fa4ed182	1228	*/
richardv	0:b079fa4ed182	1229	void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode)
richardv	0:b079fa4ed182	1230	{
richardv	0:b079fa4ed182	1231	uint32_t tmp = 0;
richardv	0:b079fa4ed182	1232	uint16_t tmp1 = 0;
richardv	0:b079fa4ed182	1233
richardv	0:b079fa4ed182	1234	/* Check the parameters */
richardv	0:b079fa4ed182	1235	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	1236	assert_param(IS_TIM_CHANNEL(TIM_Channel));
richardv	0:b079fa4ed182	1237	assert_param(IS_TIM_OCM(TIM_OCMode));
richardv	0:b079fa4ed182	1238
richardv	0:b079fa4ed182	1239	tmp = (uint32_t) TIMx;
richardv	0:b079fa4ed182	1240	tmp += CCMR_OFFSET;
richardv	0:b079fa4ed182	1241
richardv	0:b079fa4ed182	1242	tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
richardv	0:b079fa4ed182	1243
richardv	0:b079fa4ed182	1244	/* Disable the Channel: Reset the CCxE Bit */
richardv	0:b079fa4ed182	1245	TIMx->CCER &= (uint16_t) ~tmp1;
richardv	0:b079fa4ed182	1246
richardv	0:b079fa4ed182	1247	if((TIM_Channel == TIM_Channel_1) \|\|(TIM_Channel == TIM_Channel_3))
richardv	0:b079fa4ed182	1248	{
richardv	0:b079fa4ed182	1249	tmp += (TIM_Channel>>1);
richardv	0:b079fa4ed182	1250
richardv	0:b079fa4ed182	1251	/* Reset the OCxM bits in the CCMRx register */
richardv	0:b079fa4ed182	1252	(__IO uint32_t ) tmp &= CCMR_OC13M_MASK;
richardv	0:b079fa4ed182	1253
richardv	0:b079fa4ed182	1254	/* Configure the OCxM bits in the CCMRx register */
richardv	0:b079fa4ed182	1255	(__IO uint32_t ) tmp \|= TIM_OCMode;
richardv	0:b079fa4ed182	1256	}
richardv	0:b079fa4ed182	1257	else
richardv	0:b079fa4ed182	1258	{
richardv	0:b079fa4ed182	1259	tmp += (uint32_t)(TIM_Channel - (uint32_t)4)>> (uint32_t)1;
richardv	0:b079fa4ed182	1260
richardv	0:b079fa4ed182	1261	/* Reset the OCxM bits in the CCMRx register */
richardv	0:b079fa4ed182	1262	(__IO uint32_t ) tmp &= CCMR_OC24M_MASK;
richardv	0:b079fa4ed182	1263
richardv	0:b079fa4ed182	1264	/* Configure the OCxM bits in the CCMRx register */
richardv	0:b079fa4ed182	1265	(__IO uint32_t ) tmp \|= (uint32_t)(TIM_OCMode << 8);
richardv	0:b079fa4ed182	1266	}
richardv	0:b079fa4ed182	1267	}
richardv	0:b079fa4ed182	1268
richardv	0:b079fa4ed182	1269	/**
richardv	0:b079fa4ed182	1270	* @brief Sets the TIMx Capture Compare1 Register value
richardv	0:b079fa4ed182	1271	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	1272	* @param Compare1: specifies the Capture Compare1 register new value.
richardv	0:b079fa4ed182	1273	* @retval None
richardv	0:b079fa4ed182	1274	*/
richardv	0:b079fa4ed182	1275	void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
richardv	0:b079fa4ed182	1276	{
richardv	0:b079fa4ed182	1277	/* Check the parameters */
richardv	0:b079fa4ed182	1278	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	1279
richardv	0:b079fa4ed182	1280	/* Set the Capture Compare1 Register value */
richardv	0:b079fa4ed182	1281	TIMx->CCR1 = Compare1;
richardv	0:b079fa4ed182	1282	}
richardv	0:b079fa4ed182	1283
richardv	0:b079fa4ed182	1284	/**
richardv	0:b079fa4ed182	1285	* @brief Sets the TIMx Capture Compare2 Register value
richardv	0:b079fa4ed182	1286	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
richardv	0:b079fa4ed182	1287	* peripheral.
richardv	0:b079fa4ed182	1288	* @param Compare2: specifies the Capture Compare2 register new value.
richardv	0:b079fa4ed182	1289	* @retval None
richardv	0:b079fa4ed182	1290	*/
richardv	0:b079fa4ed182	1291	void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
richardv	0:b079fa4ed182	1292	{
richardv	0:b079fa4ed182	1293	/* Check the parameters */
richardv	0:b079fa4ed182	1294	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	1295
richardv	0:b079fa4ed182	1296	/* Set the Capture Compare2 Register value */
richardv	0:b079fa4ed182	1297	TIMx->CCR2 = Compare2;
richardv	0:b079fa4ed182	1298	}
richardv	0:b079fa4ed182	1299
richardv	0:b079fa4ed182	1300	/**
richardv	0:b079fa4ed182	1301	* @brief Sets the TIMx Capture Compare3 Register value
richardv	0:b079fa4ed182	1302	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1303	* @param Compare3: specifies the Capture Compare3 register new value.
richardv	0:b079fa4ed182	1304	* @retval None
richardv	0:b079fa4ed182	1305	*/
richardv	0:b079fa4ed182	1306	void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
richardv	0:b079fa4ed182	1307	{
richardv	0:b079fa4ed182	1308	/* Check the parameters */
richardv	0:b079fa4ed182	1309	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	1310
richardv	0:b079fa4ed182	1311	/* Set the Capture Compare3 Register value */
richardv	0:b079fa4ed182	1312	TIMx->CCR3 = Compare3;
richardv	0:b079fa4ed182	1313	}
richardv	0:b079fa4ed182	1314
richardv	0:b079fa4ed182	1315	/**
richardv	0:b079fa4ed182	1316	* @brief Sets the TIMx Capture Compare4 Register value
richardv	0:b079fa4ed182	1317	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1318	* @param Compare4: specifies the Capture Compare4 register new value.
richardv	0:b079fa4ed182	1319	* @retval None
richardv	0:b079fa4ed182	1320	*/
richardv	0:b079fa4ed182	1321	void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
richardv	0:b079fa4ed182	1322	{
richardv	0:b079fa4ed182	1323	/* Check the parameters */
richardv	0:b079fa4ed182	1324	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	1325
richardv	0:b079fa4ed182	1326	/* Set the Capture Compare4 Register value */
richardv	0:b079fa4ed182	1327	TIMx->CCR4 = Compare4;
richardv	0:b079fa4ed182	1328	}
richardv	0:b079fa4ed182	1329
richardv	0:b079fa4ed182	1330	/**
richardv	0:b079fa4ed182	1331	* @brief Sets the TIMx Capture Compare5 Register value
richardv	0:b079fa4ed182	1332	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1333	* @param Compare5: specifies the Capture Compare5 register new value.
richardv	0:b079fa4ed182	1334	* @retval None
richardv	0:b079fa4ed182	1335	*/
richardv	0:b079fa4ed182	1336	void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5)
richardv	0:b079fa4ed182	1337	{
richardv	0:b079fa4ed182	1338	/* Check the parameters */
richardv	0:b079fa4ed182	1339	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1340
richardv	0:b079fa4ed182	1341	/* Set the Capture Compare5 Register value */
richardv	0:b079fa4ed182	1342	TIMx->CCR5 = Compare5;
richardv	0:b079fa4ed182	1343	}
richardv	0:b079fa4ed182	1344
richardv	0:b079fa4ed182	1345	/**
richardv	0:b079fa4ed182	1346	* @brief Sets the TIMx Capture Compare6 Register value
richardv	0:b079fa4ed182	1347	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1348	* @param Compare6: specifies the Capture Compare5 register new value.
richardv	0:b079fa4ed182	1349	* @retval None
richardv	0:b079fa4ed182	1350	*/
richardv	0:b079fa4ed182	1351	void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6)
richardv	0:b079fa4ed182	1352	{
richardv	0:b079fa4ed182	1353	/* Check the parameters */
richardv	0:b079fa4ed182	1354	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1355
richardv	0:b079fa4ed182	1356	/* Set the Capture Compare6 Register value */
richardv	0:b079fa4ed182	1357	TIMx->CCR6 = Compare6;
richardv	0:b079fa4ed182	1358	}
richardv	0:b079fa4ed182	1359
richardv	0:b079fa4ed182	1360	/**
richardv	0:b079fa4ed182	1361	* @brief Forces the TIMx output 1 waveform to active or inactive level.
richardv	0:b079fa4ed182	1362	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	1363	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
richardv	0:b079fa4ed182	1364	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1365	* @arg TIM_ForcedAction_Active: Force active level on OC1REF
richardv	0:b079fa4ed182	1366	* @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
richardv	0:b079fa4ed182	1367	* @retval None
richardv	0:b079fa4ed182	1368	*/
richardv	0:b079fa4ed182	1369	void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
richardv	0:b079fa4ed182	1370	{
richardv	0:b079fa4ed182	1371	uint32_t tmpccmr1 = 0;
richardv	0:b079fa4ed182	1372
richardv	0:b079fa4ed182	1373	/* Check the parameters */
richardv	0:b079fa4ed182	1374	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	1375	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
richardv	0:b079fa4ed182	1376	tmpccmr1 = TIMx->CCMR1;
richardv	0:b079fa4ed182	1377
richardv	0:b079fa4ed182	1378	/* Reset the OC1M Bits */
richardv	0:b079fa4ed182	1379	tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1M;
richardv	0:b079fa4ed182	1380
richardv	0:b079fa4ed182	1381	/* Configure The Forced output Mode */
richardv	0:b079fa4ed182	1382	tmpccmr1 \|= TIM_ForcedAction;
richardv	0:b079fa4ed182	1383
richardv	0:b079fa4ed182	1384	/* Write to TIMx CCMR1 register */
richardv	0:b079fa4ed182	1385	TIMx->CCMR1 = tmpccmr1;
richardv	0:b079fa4ed182	1386	}
richardv	0:b079fa4ed182	1387
richardv	0:b079fa4ed182	1388	/**
richardv	0:b079fa4ed182	1389	* @brief Forces the TIMx output 2 waveform to active or inactive level.
richardv	0:b079fa4ed182	1390	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
richardv	0:b079fa4ed182	1391	* peripheral.
richardv	0:b079fa4ed182	1392	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
richardv	0:b079fa4ed182	1393	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1394	* @arg TIM_ForcedAction_Active: Force active level on OC2REF
richardv	0:b079fa4ed182	1395	* @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
richardv	0:b079fa4ed182	1396	* @retval None
richardv	0:b079fa4ed182	1397	*/
richardv	0:b079fa4ed182	1398	void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
richardv	0:b079fa4ed182	1399	{
richardv	0:b079fa4ed182	1400	uint32_t tmpccmr1 = 0;
richardv	0:b079fa4ed182	1401
richardv	0:b079fa4ed182	1402	/* Check the parameters */
richardv	0:b079fa4ed182	1403	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	1404	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
richardv	0:b079fa4ed182	1405	tmpccmr1 = TIMx->CCMR1;
richardv	0:b079fa4ed182	1406
richardv	0:b079fa4ed182	1407	/* Reset the OC2M Bits */
richardv	0:b079fa4ed182	1408	tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2M;
richardv	0:b079fa4ed182	1409
richardv	0:b079fa4ed182	1410	/* Configure The Forced output Mode */
richardv	0:b079fa4ed182	1411	tmpccmr1 \|= ((uint32_t)TIM_ForcedAction << 8);
richardv	0:b079fa4ed182	1412
richardv	0:b079fa4ed182	1413	/* Write to TIMx CCMR1 register */
richardv	0:b079fa4ed182	1414	TIMx->CCMR1 = tmpccmr1;
richardv	0:b079fa4ed182	1415	}
richardv	0:b079fa4ed182	1416
richardv	0:b079fa4ed182	1417	/**
richardv	0:b079fa4ed182	1418	* @brief Forces the TIMx output 3 waveform to active or inactive level.
richardv	0:b079fa4ed182	1419	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1420	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
richardv	0:b079fa4ed182	1421	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1422	* @arg TIM_ForcedAction_Active: Force active level on OC3REF
richardv	0:b079fa4ed182	1423	* @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
richardv	0:b079fa4ed182	1424	* @retval None
richardv	0:b079fa4ed182	1425	*/
richardv	0:b079fa4ed182	1426	void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
richardv	0:b079fa4ed182	1427	{
richardv	0:b079fa4ed182	1428	uint32_t tmpccmr2 = 0;
richardv	0:b079fa4ed182	1429
richardv	0:b079fa4ed182	1430	/* Check the parameters */
richardv	0:b079fa4ed182	1431	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	1432	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
richardv	0:b079fa4ed182	1433
richardv	0:b079fa4ed182	1434	tmpccmr2 = TIMx->CCMR2;
richardv	0:b079fa4ed182	1435
richardv	0:b079fa4ed182	1436	/* Reset the OC1M Bits */
richardv	0:b079fa4ed182	1437	tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3M;
richardv	0:b079fa4ed182	1438
richardv	0:b079fa4ed182	1439	/* Configure The Forced output Mode */
richardv	0:b079fa4ed182	1440	tmpccmr2 \|= TIM_ForcedAction;
richardv	0:b079fa4ed182	1441
richardv	0:b079fa4ed182	1442	/* Write to TIMx CCMR2 register */
richardv	0:b079fa4ed182	1443	TIMx->CCMR2 = tmpccmr2;
richardv	0:b079fa4ed182	1444	}
richardv	0:b079fa4ed182	1445
richardv	0:b079fa4ed182	1446	/**
richardv	0:b079fa4ed182	1447	* @brief Forces the TIMx output 4 waveform to active or inactive level.
richardv	0:b079fa4ed182	1448	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1449	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
richardv	0:b079fa4ed182	1450	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1451	* @arg TIM_ForcedAction_Active: Force active level on OC4REF
richardv	0:b079fa4ed182	1452	* @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
richardv	0:b079fa4ed182	1453	* @retval None
richardv	0:b079fa4ed182	1454	*/
richardv	0:b079fa4ed182	1455	void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
richardv	0:b079fa4ed182	1456	{
richardv	0:b079fa4ed182	1457	uint32_t tmpccmr2 = 0;
richardv	0:b079fa4ed182	1458
richardv	0:b079fa4ed182	1459	/* Check the parameters */
richardv	0:b079fa4ed182	1460	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	1461	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
richardv	0:b079fa4ed182	1462	tmpccmr2 = TIMx->CCMR2;
richardv	0:b079fa4ed182	1463
richardv	0:b079fa4ed182	1464	/* Reset the OC2M Bits */
richardv	0:b079fa4ed182	1465	tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4M;
richardv	0:b079fa4ed182	1466
richardv	0:b079fa4ed182	1467	/* Configure The Forced output Mode */
richardv	0:b079fa4ed182	1468	tmpccmr2 \|= ((uint32_t)TIM_ForcedAction << 8);
richardv	0:b079fa4ed182	1469
richardv	0:b079fa4ed182	1470	/* Write to TIMx CCMR2 register */
richardv	0:b079fa4ed182	1471	TIMx->CCMR2 = tmpccmr2;
richardv	0:b079fa4ed182	1472	}
richardv	0:b079fa4ed182	1473
richardv	0:b079fa4ed182	1474	/**
richardv	0:b079fa4ed182	1475	* @brief Forces the TIMx output 5 waveform to active or inactive level.
richardv	0:b079fa4ed182	1476	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1477	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
richardv	0:b079fa4ed182	1478	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1479	* @arg TIM_ForcedAction_Active: Force active level on OC5REF
richardv	0:b079fa4ed182	1480	* @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
richardv	0:b079fa4ed182	1481	* @retval None
richardv	0:b079fa4ed182	1482	*/
richardv	0:b079fa4ed182	1483	void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
richardv	0:b079fa4ed182	1484	{
richardv	0:b079fa4ed182	1485	uint32_t tmpccmr3 = 0;
richardv	0:b079fa4ed182	1486
richardv	0:b079fa4ed182	1487	/* Check the parameters */
richardv	0:b079fa4ed182	1488	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1489	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
richardv	0:b079fa4ed182	1490	tmpccmr3 = TIMx->CCMR3;
richardv	0:b079fa4ed182	1491
richardv	0:b079fa4ed182	1492	/* Reset the OC5M Bits */
richardv	0:b079fa4ed182	1493	tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5M;
richardv	0:b079fa4ed182	1494
richardv	0:b079fa4ed182	1495	/* Configure The Forced output Mode */
richardv	0:b079fa4ed182	1496	tmpccmr3 \|= (uint32_t)(TIM_ForcedAction);
richardv	0:b079fa4ed182	1497
richardv	0:b079fa4ed182	1498	/* Write to TIMx CCMR3 register */
richardv	0:b079fa4ed182	1499	TIMx->CCMR3 = tmpccmr3;
richardv	0:b079fa4ed182	1500	}
richardv	0:b079fa4ed182	1501
richardv	0:b079fa4ed182	1502	/**
richardv	0:b079fa4ed182	1503	* @brief Forces the TIMx output 6 waveform to active or inactive level.
richardv	0:b079fa4ed182	1504	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1505	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
richardv	0:b079fa4ed182	1506	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1507	* @arg TIM_ForcedAction_Active: Force active level on OC5REF
richardv	0:b079fa4ed182	1508	* @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
richardv	0:b079fa4ed182	1509	* @retval None
richardv	0:b079fa4ed182	1510	*/
richardv	0:b079fa4ed182	1511	void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
richardv	0:b079fa4ed182	1512	{
richardv	0:b079fa4ed182	1513	uint32_t tmpccmr3 = 0;
richardv	0:b079fa4ed182	1514
richardv	0:b079fa4ed182	1515	/* Check the parameters */
richardv	0:b079fa4ed182	1516	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1517	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
richardv	0:b079fa4ed182	1518	tmpccmr3 = TIMx->CCMR3;
richardv	0:b079fa4ed182	1519
richardv	0:b079fa4ed182	1520	/* Reset the OC6M Bits */
richardv	0:b079fa4ed182	1521	tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6M;
richardv	0:b079fa4ed182	1522
richardv	0:b079fa4ed182	1523	/* Configure The Forced output Mode */
richardv	0:b079fa4ed182	1524	tmpccmr3 \|= ((uint32_t)TIM_ForcedAction << 8);
richardv	0:b079fa4ed182	1525
richardv	0:b079fa4ed182	1526	/* Write to TIMx CCMR3 register */
richardv	0:b079fa4ed182	1527	TIMx->CCMR3 = tmpccmr3;
richardv	0:b079fa4ed182	1528	}
richardv	0:b079fa4ed182	1529
richardv	0:b079fa4ed182	1530	/**
richardv	0:b079fa4ed182	1531	* @brief Enables or disables the TIMx peripheral Preload register on CCR1.
richardv	0:b079fa4ed182	1532	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	1533	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
richardv	0:b079fa4ed182	1534	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1535	* @arg TIM_OCPreload_Enable
richardv	0:b079fa4ed182	1536	* @arg TIM_OCPreload_Disable
richardv	0:b079fa4ed182	1537	* @retval None
richardv	0:b079fa4ed182	1538	*/
richardv	0:b079fa4ed182	1539	void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
richardv	0:b079fa4ed182	1540	{
richardv	0:b079fa4ed182	1541	uint32_t tmpccmr1 = 0;
richardv	0:b079fa4ed182	1542
richardv	0:b079fa4ed182	1543	/* Check the parameters */
richardv	0:b079fa4ed182	1544	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	1545	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
richardv	0:b079fa4ed182	1546
richardv	0:b079fa4ed182	1547	tmpccmr1 = TIMx->CCMR1;
richardv	0:b079fa4ed182	1548
richardv	0:b079fa4ed182	1549	/* Reset the OC1PE Bit */
richardv	0:b079fa4ed182	1550	tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC1PE);
richardv	0:b079fa4ed182	1551
richardv	0:b079fa4ed182	1552	/* Enable or Disable the Output Compare Preload feature */
richardv	0:b079fa4ed182	1553	tmpccmr1 \|= TIM_OCPreload;
richardv	0:b079fa4ed182	1554
richardv	0:b079fa4ed182	1555	/* Write to TIMx CCMR1 register */
richardv	0:b079fa4ed182	1556	TIMx->CCMR1 = tmpccmr1;
richardv	0:b079fa4ed182	1557	}
richardv	0:b079fa4ed182	1558
richardv	0:b079fa4ed182	1559	/**
richardv	0:b079fa4ed182	1560	* @brief Enables or disables the TIMx peripheral Preload register on CCR2.
richardv	0:b079fa4ed182	1561	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
richardv	0:b079fa4ed182	1562	* peripheral.
richardv	0:b079fa4ed182	1563	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
richardv	0:b079fa4ed182	1564	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1565	* @arg TIM_OCPreload_Enable
richardv	0:b079fa4ed182	1566	* @arg TIM_OCPreload_Disable
richardv	0:b079fa4ed182	1567	* @retval None
richardv	0:b079fa4ed182	1568	*/
richardv	0:b079fa4ed182	1569	void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
richardv	0:b079fa4ed182	1570	{
richardv	0:b079fa4ed182	1571	uint32_t tmpccmr1 = 0;
richardv	0:b079fa4ed182	1572
richardv	0:b079fa4ed182	1573	/* Check the parameters */
richardv	0:b079fa4ed182	1574	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	1575	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
richardv	0:b079fa4ed182	1576
richardv	0:b079fa4ed182	1577	tmpccmr1 = TIMx->CCMR1;
richardv	0:b079fa4ed182	1578
richardv	0:b079fa4ed182	1579	/* Reset the OC2PE Bit */
richardv	0:b079fa4ed182	1580	tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2PE);
richardv	0:b079fa4ed182	1581
richardv	0:b079fa4ed182	1582	/* Enable or Disable the Output Compare Preload feature */
richardv	0:b079fa4ed182	1583	tmpccmr1 \|= ((uint32_t)TIM_OCPreload << 8);
richardv	0:b079fa4ed182	1584
richardv	0:b079fa4ed182	1585	/* Write to TIMx CCMR1 register */
richardv	0:b079fa4ed182	1586	TIMx->CCMR1 = tmpccmr1;
richardv	0:b079fa4ed182	1587	}
richardv	0:b079fa4ed182	1588
richardv	0:b079fa4ed182	1589	/**
richardv	0:b079fa4ed182	1590	* @brief Enables or disables the TIMx peripheral Preload register on CCR3.
richardv	0:b079fa4ed182	1591	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1592	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
richardv	0:b079fa4ed182	1593	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1594	* @arg TIM_OCPreload_Enable
richardv	0:b079fa4ed182	1595	* @arg TIM_OCPreload_Disable
richardv	0:b079fa4ed182	1596	* @retval None
richardv	0:b079fa4ed182	1597	*/
richardv	0:b079fa4ed182	1598	void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
richardv	0:b079fa4ed182	1599	{
richardv	0:b079fa4ed182	1600	uint32_t tmpccmr2 = 0;
richardv	0:b079fa4ed182	1601
richardv	0:b079fa4ed182	1602	/* Check the parameters */
richardv	0:b079fa4ed182	1603	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	1604	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
richardv	0:b079fa4ed182	1605
richardv	0:b079fa4ed182	1606	tmpccmr2 = TIMx->CCMR2;
richardv	0:b079fa4ed182	1607
richardv	0:b079fa4ed182	1608	/* Reset the OC3PE Bit */
richardv	0:b079fa4ed182	1609	tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC3PE);
richardv	0:b079fa4ed182	1610
richardv	0:b079fa4ed182	1611	/* Enable or Disable the Output Compare Preload feature */
richardv	0:b079fa4ed182	1612	tmpccmr2 \|= TIM_OCPreload;
richardv	0:b079fa4ed182	1613
richardv	0:b079fa4ed182	1614	/* Write to TIMx CCMR2 register */
richardv	0:b079fa4ed182	1615	TIMx->CCMR2 = tmpccmr2;
richardv	0:b079fa4ed182	1616	}
richardv	0:b079fa4ed182	1617
richardv	0:b079fa4ed182	1618	/**
richardv	0:b079fa4ed182	1619	* @brief Enables or disables the TIMx peripheral Preload register on CCR4.
richardv	0:b079fa4ed182	1620	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1621	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
richardv	0:b079fa4ed182	1622	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1623	* @arg TIM_OCPreload_Enable
richardv	0:b079fa4ed182	1624	* @arg TIM_OCPreload_Disable
richardv	0:b079fa4ed182	1625	* @retval None
richardv	0:b079fa4ed182	1626	*/
richardv	0:b079fa4ed182	1627	void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
richardv	0:b079fa4ed182	1628	{
richardv	0:b079fa4ed182	1629	uint32_t tmpccmr2 = 0;
richardv	0:b079fa4ed182	1630
richardv	0:b079fa4ed182	1631	/* Check the parameters */
richardv	0:b079fa4ed182	1632	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	1633	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
richardv	0:b079fa4ed182	1634
richardv	0:b079fa4ed182	1635	tmpccmr2 = TIMx->CCMR2;
richardv	0:b079fa4ed182	1636
richardv	0:b079fa4ed182	1637	/* Reset the OC4PE Bit */
richardv	0:b079fa4ed182	1638	tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4PE);
richardv	0:b079fa4ed182	1639
richardv	0:b079fa4ed182	1640	/* Enable or Disable the Output Compare Preload feature */
richardv	0:b079fa4ed182	1641	tmpccmr2 \|= ((uint32_t)TIM_OCPreload << 8);
richardv	0:b079fa4ed182	1642
richardv	0:b079fa4ed182	1643	/* Write to TIMx CCMR2 register */
richardv	0:b079fa4ed182	1644	TIMx->CCMR2 = tmpccmr2;
richardv	0:b079fa4ed182	1645	}
richardv	0:b079fa4ed182	1646
richardv	0:b079fa4ed182	1647	/**
richardv	0:b079fa4ed182	1648	* @brief Enables or disables the TIMx peripheral Preload register on CCR5.
richardv	0:b079fa4ed182	1649	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1650	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
richardv	0:b079fa4ed182	1651	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1652	* @arg TIM_OCPreload_Enable
richardv	0:b079fa4ed182	1653	* @arg TIM_OCPreload_Disable
richardv	0:b079fa4ed182	1654	* @retval None
richardv	0:b079fa4ed182	1655	*/
richardv	0:b079fa4ed182	1656	void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
richardv	0:b079fa4ed182	1657	{
richardv	0:b079fa4ed182	1658	uint32_t tmpccmr3 = 0;
richardv	0:b079fa4ed182	1659
richardv	0:b079fa4ed182	1660	/* Check the parameters */
richardv	0:b079fa4ed182	1661	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1662	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
richardv	0:b079fa4ed182	1663
richardv	0:b079fa4ed182	1664	tmpccmr3 = TIMx->CCMR3;
richardv	0:b079fa4ed182	1665
richardv	0:b079fa4ed182	1666	/* Reset the OC5PE Bit */
richardv	0:b079fa4ed182	1667	tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC5PE);
richardv	0:b079fa4ed182	1668
richardv	0:b079fa4ed182	1669	/* Enable or Disable the Output Compare Preload feature */
richardv	0:b079fa4ed182	1670	tmpccmr3 \|= (uint32_t)(TIM_OCPreload);
richardv	0:b079fa4ed182	1671
richardv	0:b079fa4ed182	1672	/* Write to TIMx CCMR3 register */
richardv	0:b079fa4ed182	1673	TIMx->CCMR3 = tmpccmr3;
richardv	0:b079fa4ed182	1674	}
richardv	0:b079fa4ed182	1675
richardv	0:b079fa4ed182	1676	/**
richardv	0:b079fa4ed182	1677	* @brief Enables or disables the TIMx peripheral Preload register on CCR6.
richardv	0:b079fa4ed182	1678	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1679	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
richardv	0:b079fa4ed182	1680	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1681	* @arg TIM_OCPreload_Enable
richardv	0:b079fa4ed182	1682	* @arg TIM_OCPreload_Disable
richardv	0:b079fa4ed182	1683	* @retval None
richardv	0:b079fa4ed182	1684	*/
richardv	0:b079fa4ed182	1685	void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
richardv	0:b079fa4ed182	1686	{
richardv	0:b079fa4ed182	1687	uint32_t tmpccmr3 = 0;
richardv	0:b079fa4ed182	1688
richardv	0:b079fa4ed182	1689	/* Check the parameters */
richardv	0:b079fa4ed182	1690	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1691	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
richardv	0:b079fa4ed182	1692
richardv	0:b079fa4ed182	1693	tmpccmr3 = TIMx->CCMR3;
richardv	0:b079fa4ed182	1694
richardv	0:b079fa4ed182	1695	/* Reset the OC5PE Bit */
richardv	0:b079fa4ed182	1696	tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC6PE);
richardv	0:b079fa4ed182	1697
richardv	0:b079fa4ed182	1698	/* Enable or Disable the Output Compare Preload feature */
richardv	0:b079fa4ed182	1699	tmpccmr3 \|= ((uint32_t)TIM_OCPreload << 8);
richardv	0:b079fa4ed182	1700
richardv	0:b079fa4ed182	1701	/* Write to TIMx CCMR3 register */
richardv	0:b079fa4ed182	1702	TIMx->CCMR3 = tmpccmr3;
richardv	0:b079fa4ed182	1703	}
richardv	0:b079fa4ed182	1704
richardv	0:b079fa4ed182	1705	/**
richardv	0:b079fa4ed182	1706	* @brief Configures the TIMx Output Compare 1 Fast feature.
richardv	0:b079fa4ed182	1707	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	1708	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
richardv	0:b079fa4ed182	1709	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1710	* @arg TIM_OCFast_Enable: TIM output compare fast enable
richardv	0:b079fa4ed182	1711	* @arg TIM_OCFast_Disable: TIM output compare fast disable
richardv	0:b079fa4ed182	1712	* @retval None
richardv	0:b079fa4ed182	1713	*/
richardv	0:b079fa4ed182	1714	void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
richardv	0:b079fa4ed182	1715	{
richardv	0:b079fa4ed182	1716	uint32_t tmpccmr1 = 0;
richardv	0:b079fa4ed182	1717
richardv	0:b079fa4ed182	1718	/* Check the parameters */
richardv	0:b079fa4ed182	1719	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	1720	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
richardv	0:b079fa4ed182	1721
richardv	0:b079fa4ed182	1722	/* Get the TIMx CCMR1 register value */
richardv	0:b079fa4ed182	1723	tmpccmr1 = TIMx->CCMR1;
richardv	0:b079fa4ed182	1724
richardv	0:b079fa4ed182	1725	/* Reset the OC1FE Bit */
richardv	0:b079fa4ed182	1726	tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1FE;
richardv	0:b079fa4ed182	1727
richardv	0:b079fa4ed182	1728	/* Enable or Disable the Output Compare Fast Bit */
richardv	0:b079fa4ed182	1729	tmpccmr1 \|= TIM_OCFast;
richardv	0:b079fa4ed182	1730
richardv	0:b079fa4ed182	1731	/* Write to TIMx CCMR1 */
richardv	0:b079fa4ed182	1732	TIMx->CCMR1 = tmpccmr1;
richardv	0:b079fa4ed182	1733	}
richardv	0:b079fa4ed182	1734
richardv	0:b079fa4ed182	1735	/**
richardv	0:b079fa4ed182	1736	* @brief Configures the TIMx Output Compare 2 Fast feature.
richardv	0:b079fa4ed182	1737	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
richardv	0:b079fa4ed182	1738	* peripheral.
richardv	0:b079fa4ed182	1739	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
richardv	0:b079fa4ed182	1740	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1741	* @arg TIM_OCFast_Enable: TIM output compare fast enable
richardv	0:b079fa4ed182	1742	* @arg TIM_OCFast_Disable: TIM output compare fast disable
richardv	0:b079fa4ed182	1743	* @retval None
richardv	0:b079fa4ed182	1744	*/
richardv	0:b079fa4ed182	1745	void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
richardv	0:b079fa4ed182	1746	{
richardv	0:b079fa4ed182	1747	uint32_t tmpccmr1 = 0;
richardv	0:b079fa4ed182	1748
richardv	0:b079fa4ed182	1749	/* Check the parameters */
richardv	0:b079fa4ed182	1750	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	1751	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
richardv	0:b079fa4ed182	1752
richardv	0:b079fa4ed182	1753	/* Get the TIMx CCMR1 register value */
richardv	0:b079fa4ed182	1754	tmpccmr1 = TIMx->CCMR1;
richardv	0:b079fa4ed182	1755
richardv	0:b079fa4ed182	1756	/* Reset the OC2FE Bit */
richardv	0:b079fa4ed182	1757	tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2FE);
richardv	0:b079fa4ed182	1758
richardv	0:b079fa4ed182	1759	/* Enable or Disable the Output Compare Fast Bit */
richardv	0:b079fa4ed182	1760	tmpccmr1 \|= ((uint32_t)TIM_OCFast << 8);
richardv	0:b079fa4ed182	1761
richardv	0:b079fa4ed182	1762	/* Write to TIMx CCMR1 */
richardv	0:b079fa4ed182	1763	TIMx->CCMR1 = tmpccmr1;
richardv	0:b079fa4ed182	1764	}
richardv	0:b079fa4ed182	1765
richardv	0:b079fa4ed182	1766	/**
richardv	0:b079fa4ed182	1767	* @brief Configures the TIMx Output Compare 3 Fast feature.
richardv	0:b079fa4ed182	1768	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1769	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
richardv	0:b079fa4ed182	1770	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1771	* @arg TIM_OCFast_Enable: TIM output compare fast enable
richardv	0:b079fa4ed182	1772	* @arg TIM_OCFast_Disable: TIM output compare fast disable
richardv	0:b079fa4ed182	1773	* @retval None
richardv	0:b079fa4ed182	1774	*/
richardv	0:b079fa4ed182	1775	void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
richardv	0:b079fa4ed182	1776	{
richardv	0:b079fa4ed182	1777	uint32_t tmpccmr2 = 0;
richardv	0:b079fa4ed182	1778
richardv	0:b079fa4ed182	1779	/* Check the parameters */
richardv	0:b079fa4ed182	1780	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	1781	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
richardv	0:b079fa4ed182	1782
richardv	0:b079fa4ed182	1783	/* Get the TIMx CCMR2 register value */
richardv	0:b079fa4ed182	1784	tmpccmr2 = TIMx->CCMR2;
richardv	0:b079fa4ed182	1785
richardv	0:b079fa4ed182	1786	/* Reset the OC3FE Bit */
richardv	0:b079fa4ed182	1787	tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3FE;
richardv	0:b079fa4ed182	1788
richardv	0:b079fa4ed182	1789	/* Enable or Disable the Output Compare Fast Bit */
richardv	0:b079fa4ed182	1790	tmpccmr2 \|= TIM_OCFast;
richardv	0:b079fa4ed182	1791
richardv	0:b079fa4ed182	1792	/* Write to TIMx CCMR2 */
richardv	0:b079fa4ed182	1793	TIMx->CCMR2 = tmpccmr2;
richardv	0:b079fa4ed182	1794	}
richardv	0:b079fa4ed182	1795
richardv	0:b079fa4ed182	1796	/**
richardv	0:b079fa4ed182	1797	* @brief Configures the TIMx Output Compare 4 Fast feature.
richardv	0:b079fa4ed182	1798	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1799	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
richardv	0:b079fa4ed182	1800	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1801	* @arg TIM_OCFast_Enable: TIM output compare fast enable
richardv	0:b079fa4ed182	1802	* @arg TIM_OCFast_Disable: TIM output compare fast disable
richardv	0:b079fa4ed182	1803	* @retval None
richardv	0:b079fa4ed182	1804	*/
richardv	0:b079fa4ed182	1805	void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
richardv	0:b079fa4ed182	1806	{
richardv	0:b079fa4ed182	1807	uint32_t tmpccmr2 = 0;
richardv	0:b079fa4ed182	1808
richardv	0:b079fa4ed182	1809	/* Check the parameters */
richardv	0:b079fa4ed182	1810	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	1811	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
richardv	0:b079fa4ed182	1812
richardv	0:b079fa4ed182	1813	/* Get the TIMx CCMR2 register value */
richardv	0:b079fa4ed182	1814	tmpccmr2 = TIMx->CCMR2;
richardv	0:b079fa4ed182	1815
richardv	0:b079fa4ed182	1816	/* Reset the OC4FE Bit */
richardv	0:b079fa4ed182	1817	tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4FE);
richardv	0:b079fa4ed182	1818
richardv	0:b079fa4ed182	1819	/* Enable or Disable the Output Compare Fast Bit */
richardv	0:b079fa4ed182	1820	tmpccmr2 \|= ((uint32_t)TIM_OCFast << 8);
richardv	0:b079fa4ed182	1821
richardv	0:b079fa4ed182	1822	/* Write to TIMx CCMR2 */
richardv	0:b079fa4ed182	1823	TIMx->CCMR2 = tmpccmr2;
richardv	0:b079fa4ed182	1824	}
richardv	0:b079fa4ed182	1825
richardv	0:b079fa4ed182	1826	/**
richardv	0:b079fa4ed182	1827	* @brief Clears or safeguards the OCREF1 signal on an external event
richardv	0:b079fa4ed182	1828	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	1829	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
richardv	0:b079fa4ed182	1830	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1831	* @arg TIM_OCClear_Enable: TIM Output clear enable
richardv	0:b079fa4ed182	1832	* @arg TIM_OCClear_Disable: TIM Output clear disable
richardv	0:b079fa4ed182	1833	* @retval None
richardv	0:b079fa4ed182	1834	*/
richardv	0:b079fa4ed182	1835	void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
richardv	0:b079fa4ed182	1836	{
richardv	0:b079fa4ed182	1837	uint32_t tmpccmr1 = 0;
richardv	0:b079fa4ed182	1838
richardv	0:b079fa4ed182	1839	/* Check the parameters */
richardv	0:b079fa4ed182	1840	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	1841	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
richardv	0:b079fa4ed182	1842
richardv	0:b079fa4ed182	1843	tmpccmr1 = TIMx->CCMR1;
richardv	0:b079fa4ed182	1844
richardv	0:b079fa4ed182	1845	/* Reset the OC1CE Bit */
richardv	0:b079fa4ed182	1846	tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1CE;
richardv	0:b079fa4ed182	1847
richardv	0:b079fa4ed182	1848	/* Enable or Disable the Output Compare Clear Bit */
richardv	0:b079fa4ed182	1849	tmpccmr1 \|= TIM_OCClear;
richardv	0:b079fa4ed182	1850
richardv	0:b079fa4ed182	1851	/* Write to TIMx CCMR1 register */
richardv	0:b079fa4ed182	1852	TIMx->CCMR1 = tmpccmr1;
richardv	0:b079fa4ed182	1853	}
richardv	0:b079fa4ed182	1854
richardv	0:b079fa4ed182	1855	/**
richardv	0:b079fa4ed182	1856	* @brief Clears or safeguards the OCREF2 signal on an external event
richardv	0:b079fa4ed182	1857	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
richardv	0:b079fa4ed182	1858	* peripheral.
richardv	0:b079fa4ed182	1859	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
richardv	0:b079fa4ed182	1860	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1861	* @arg TIM_OCClear_Enable: TIM Output clear enable
richardv	0:b079fa4ed182	1862	* @arg TIM_OCClear_Disable: TIM Output clear disable
richardv	0:b079fa4ed182	1863	* @retval None
richardv	0:b079fa4ed182	1864	*/
richardv	0:b079fa4ed182	1865	void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
richardv	0:b079fa4ed182	1866	{
richardv	0:b079fa4ed182	1867	uint32_t tmpccmr1 = 0;
richardv	0:b079fa4ed182	1868
richardv	0:b079fa4ed182	1869	/* Check the parameters */
richardv	0:b079fa4ed182	1870	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	1871	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
richardv	0:b079fa4ed182	1872
richardv	0:b079fa4ed182	1873	tmpccmr1 = TIMx->CCMR1;
richardv	0:b079fa4ed182	1874
richardv	0:b079fa4ed182	1875	/* Reset the OC2CE Bit */
richardv	0:b079fa4ed182	1876	tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2CE;
richardv	0:b079fa4ed182	1877
richardv	0:b079fa4ed182	1878	/* Enable or Disable the Output Compare Clear Bit */
richardv	0:b079fa4ed182	1879	tmpccmr1 \|= ((uint32_t)TIM_OCClear << 8);
richardv	0:b079fa4ed182	1880
richardv	0:b079fa4ed182	1881	/* Write to TIMx CCMR1 register */
richardv	0:b079fa4ed182	1882	TIMx->CCMR1 = tmpccmr1;
richardv	0:b079fa4ed182	1883	}
richardv	0:b079fa4ed182	1884
richardv	0:b079fa4ed182	1885	/**
richardv	0:b079fa4ed182	1886	* @brief Clears or safeguards the OCREF3 signal on an external event
richardv	0:b079fa4ed182	1887	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1888	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
richardv	0:b079fa4ed182	1889	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1890	* @arg TIM_OCClear_Enable: TIM Output clear enable
richardv	0:b079fa4ed182	1891	* @arg TIM_OCClear_Disable: TIM Output clear disable
richardv	0:b079fa4ed182	1892	* @retval None
richardv	0:b079fa4ed182	1893	*/
richardv	0:b079fa4ed182	1894	void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
richardv	0:b079fa4ed182	1895	{
richardv	0:b079fa4ed182	1896	uint32_t tmpccmr2 = 0;
richardv	0:b079fa4ed182	1897
richardv	0:b079fa4ed182	1898	/* Check the parameters */
richardv	0:b079fa4ed182	1899	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	1900	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
richardv	0:b079fa4ed182	1901
richardv	0:b079fa4ed182	1902	tmpccmr2 = TIMx->CCMR2;
richardv	0:b079fa4ed182	1903
richardv	0:b079fa4ed182	1904	/* Reset the OC3CE Bit */
richardv	0:b079fa4ed182	1905	tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3CE;
richardv	0:b079fa4ed182	1906
richardv	0:b079fa4ed182	1907	/* Enable or Disable the Output Compare Clear Bit */
richardv	0:b079fa4ed182	1908	tmpccmr2 \|= TIM_OCClear;
richardv	0:b079fa4ed182	1909
richardv	0:b079fa4ed182	1910	/* Write to TIMx CCMR2 register */
richardv	0:b079fa4ed182	1911	TIMx->CCMR2 = tmpccmr2;
richardv	0:b079fa4ed182	1912	}
richardv	0:b079fa4ed182	1913
richardv	0:b079fa4ed182	1914	/**
richardv	0:b079fa4ed182	1915	* @brief Clears or safeguards the OCREF4 signal on an external event
richardv	0:b079fa4ed182	1916	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1917	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
richardv	0:b079fa4ed182	1918	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1919	* @arg TIM_OCClear_Enable: TIM Output clear enable
richardv	0:b079fa4ed182	1920	* @arg TIM_OCClear_Disable: TIM Output clear disable
richardv	0:b079fa4ed182	1921	* @retval None
richardv	0:b079fa4ed182	1922	*/
richardv	0:b079fa4ed182	1923	void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
richardv	0:b079fa4ed182	1924	{
richardv	0:b079fa4ed182	1925	uint32_t tmpccmr2 = 0;
richardv	0:b079fa4ed182	1926
richardv	0:b079fa4ed182	1927	/* Check the parameters */
richardv	0:b079fa4ed182	1928	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	1929	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
richardv	0:b079fa4ed182	1930
richardv	0:b079fa4ed182	1931	tmpccmr2 = TIMx->CCMR2;
richardv	0:b079fa4ed182	1932
richardv	0:b079fa4ed182	1933	/* Reset the OC4CE Bit */
richardv	0:b079fa4ed182	1934	tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4CE;
richardv	0:b079fa4ed182	1935
richardv	0:b079fa4ed182	1936	/* Enable or Disable the Output Compare Clear Bit */
richardv	0:b079fa4ed182	1937	tmpccmr2 \|= ((uint32_t)TIM_OCClear << 8);
richardv	0:b079fa4ed182	1938
richardv	0:b079fa4ed182	1939	/* Write to TIMx CCMR2 register */
richardv	0:b079fa4ed182	1940	TIMx->CCMR2 = tmpccmr2;
richardv	0:b079fa4ed182	1941	}
richardv	0:b079fa4ed182	1942
richardv	0:b079fa4ed182	1943	/**
richardv	0:b079fa4ed182	1944	* @brief Clears or safeguards the OCREF5 signal on an external event
richardv	0:b079fa4ed182	1945	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1946	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
richardv	0:b079fa4ed182	1947	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1948	* @arg TIM_OCClear_Enable: TIM Output clear enable
richardv	0:b079fa4ed182	1949	* @arg TIM_OCClear_Disable: TIM Output clear disable
richardv	0:b079fa4ed182	1950	* @retval None
richardv	0:b079fa4ed182	1951	*/
richardv	0:b079fa4ed182	1952	void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
richardv	0:b079fa4ed182	1953	{
richardv	0:b079fa4ed182	1954	uint32_t tmpccmr3 = 0;
richardv	0:b079fa4ed182	1955
richardv	0:b079fa4ed182	1956	/* Check the parameters */
richardv	0:b079fa4ed182	1957	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1958	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
richardv	0:b079fa4ed182	1959
richardv	0:b079fa4ed182	1960	tmpccmr3 = TIMx->CCMR3;
richardv	0:b079fa4ed182	1961
richardv	0:b079fa4ed182	1962	/* Reset the OC5CE Bit */
richardv	0:b079fa4ed182	1963	tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5CE;
richardv	0:b079fa4ed182	1964
richardv	0:b079fa4ed182	1965	/* Enable or Disable the Output Compare Clear Bit */
richardv	0:b079fa4ed182	1966	tmpccmr3 \|= (uint32_t)(TIM_OCClear);
richardv	0:b079fa4ed182	1967
richardv	0:b079fa4ed182	1968	/* Write to TIMx CCMR3 register */
richardv	0:b079fa4ed182	1969	TIMx->CCMR3 = tmpccmr3;
richardv	0:b079fa4ed182	1970	}
richardv	0:b079fa4ed182	1971
richardv	0:b079fa4ed182	1972	/**
richardv	0:b079fa4ed182	1973	* @brief Clears or safeguards the OCREF6 signal on an external event
richardv	0:b079fa4ed182	1974	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	1975	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
richardv	0:b079fa4ed182	1976	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	1977	* @arg TIM_OCClear_Enable: TIM Output clear enable
richardv	0:b079fa4ed182	1978	* @arg TIM_OCClear_Disable: TIM Output clear disable
richardv	0:b079fa4ed182	1979	* @retval None
richardv	0:b079fa4ed182	1980	*/
richardv	0:b079fa4ed182	1981	void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
richardv	0:b079fa4ed182	1982	{
richardv	0:b079fa4ed182	1983	uint32_t tmpccmr3 = 0;
richardv	0:b079fa4ed182	1984
richardv	0:b079fa4ed182	1985	/* Check the parameters */
richardv	0:b079fa4ed182	1986	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	1987	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
richardv	0:b079fa4ed182	1988
richardv	0:b079fa4ed182	1989	tmpccmr3 = TIMx->CCMR3;
richardv	0:b079fa4ed182	1990
richardv	0:b079fa4ed182	1991	/* Reset the OC5CE Bit */
richardv	0:b079fa4ed182	1992	tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6CE;
richardv	0:b079fa4ed182	1993
richardv	0:b079fa4ed182	1994	/* Enable or Disable the Output Compare Clear Bit */
richardv	0:b079fa4ed182	1995	tmpccmr3 \|= ((uint32_t)TIM_OCClear << 8);
richardv	0:b079fa4ed182	1996
richardv	0:b079fa4ed182	1997	/* Write to TIMx CCMR3 register */
richardv	0:b079fa4ed182	1998	TIMx->CCMR3 = tmpccmr3;
richardv	0:b079fa4ed182	1999	}
richardv	0:b079fa4ed182	2000
richardv	0:b079fa4ed182	2001	/**
richardv	0:b079fa4ed182	2002	* @brief Selects the OCReference Clear source.
richardv	0:b079fa4ed182	2003	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	2004	* @param TIM_OCReferenceClear: specifies the OCReference Clear source.
richardv	0:b079fa4ed182	2005	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2006	* @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
richardv	0:b079fa4ed182	2007	* @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
richardv	0:b079fa4ed182	2008	* @retval None
richardv	0:b079fa4ed182	2009	*/
richardv	0:b079fa4ed182	2010	void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
richardv	0:b079fa4ed182	2011	{
richardv	0:b079fa4ed182	2012	/* Check the parameters */
richardv	0:b079fa4ed182	2013	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	2014	assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
richardv	0:b079fa4ed182	2015
richardv	0:b079fa4ed182	2016	/* Set the TIM_OCReferenceClear source */
richardv	0:b079fa4ed182	2017	TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
richardv	0:b079fa4ed182	2018	TIMx->SMCR \|= TIM_OCReferenceClear;
richardv	0:b079fa4ed182	2019	}
richardv	0:b079fa4ed182	2020
richardv	0:b079fa4ed182	2021	/**
richardv	0:b079fa4ed182	2022	* @brief Configures the TIMx channel 1 polarity.
richardv	0:b079fa4ed182	2023	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	2024	* @param TIM_OCPolarity: specifies the OC1 Polarity
richardv	0:b079fa4ed182	2025	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2026	* @arg TIM_OCPolarity_High: Output Compare active high
richardv	0:b079fa4ed182	2027	* @arg TIM_OCPolarity_Low: Output Compare active low
richardv	0:b079fa4ed182	2028	* @retval None
richardv	0:b079fa4ed182	2029	*/
richardv	0:b079fa4ed182	2030	void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
richardv	0:b079fa4ed182	2031	{
richardv	0:b079fa4ed182	2032	uint32_t tmpccer = 0;
richardv	0:b079fa4ed182	2033
richardv	0:b079fa4ed182	2034	/* Check the parameters */
richardv	0:b079fa4ed182	2035	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	2036	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
richardv	0:b079fa4ed182	2037
richardv	0:b079fa4ed182	2038	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	2039
richardv	0:b079fa4ed182	2040	/* Set or Reset the CC1P Bit */
richardv	0:b079fa4ed182	2041	tmpccer &= (uint32_t)(~TIM_CCER_CC1P);
richardv	0:b079fa4ed182	2042	tmpccer \|= TIM_OCPolarity;
richardv	0:b079fa4ed182	2043
richardv	0:b079fa4ed182	2044	/* Write to TIMx CCER register */
richardv	0:b079fa4ed182	2045	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	2046	}
richardv	0:b079fa4ed182	2047
richardv	0:b079fa4ed182	2048	/**
richardv	0:b079fa4ed182	2049	* @brief Configures the TIMx Channel 1N polarity.
richardv	0:b079fa4ed182	2050	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	2051	* @param TIM_OCNPolarity: specifies the OC1N Polarity
richardv	0:b079fa4ed182	2052	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2053	* @arg TIM_OCNPolarity_High: Output Compare active high
richardv	0:b079fa4ed182	2054	* @arg TIM_OCNPolarity_Low: Output Compare active low
richardv	0:b079fa4ed182	2055	* @retval None
richardv	0:b079fa4ed182	2056	*/
richardv	0:b079fa4ed182	2057	void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
richardv	0:b079fa4ed182	2058	{
richardv	0:b079fa4ed182	2059	uint32_t tmpccer = 0;
richardv	0:b079fa4ed182	2060	/* Check the parameters */
richardv	0:b079fa4ed182	2061	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
richardv	0:b079fa4ed182	2062	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
richardv	0:b079fa4ed182	2063
richardv	0:b079fa4ed182	2064	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	2065
richardv	0:b079fa4ed182	2066	/* Set or Reset the CC1NP Bit */
richardv	0:b079fa4ed182	2067	tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
richardv	0:b079fa4ed182	2068	tmpccer \|= TIM_OCNPolarity;
richardv	0:b079fa4ed182	2069
richardv	0:b079fa4ed182	2070	/* Write to TIMx CCER register */
richardv	0:b079fa4ed182	2071	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	2072	}
richardv	0:b079fa4ed182	2073
richardv	0:b079fa4ed182	2074	/**
richardv	0:b079fa4ed182	2075	* @brief Configures the TIMx channel 2 polarity.
richardv	0:b079fa4ed182	2076	* @param TIMx: where x can be 1, 2, 3, 4 8 or 15 to select the TIM
richardv	0:b079fa4ed182	2077	* peripheral.
richardv	0:b079fa4ed182	2078	* @param TIM_OCPolarity: specifies the OC2 Polarity
richardv	0:b079fa4ed182	2079	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2080	* @arg TIM_OCPolarity_High: Output Compare active high
richardv	0:b079fa4ed182	2081	* @arg TIM_OCPolarity_Low: Output Compare active low
richardv	0:b079fa4ed182	2082	* @retval None
richardv	0:b079fa4ed182	2083	*/
richardv	0:b079fa4ed182	2084	void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
richardv	0:b079fa4ed182	2085	{
richardv	0:b079fa4ed182	2086	uint32_t tmpccer = 0;
richardv	0:b079fa4ed182	2087
richardv	0:b079fa4ed182	2088	/* Check the parameters */
richardv	0:b079fa4ed182	2089	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	2090	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
richardv	0:b079fa4ed182	2091
richardv	0:b079fa4ed182	2092	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	2093
richardv	0:b079fa4ed182	2094	/* Set or Reset the CC2P Bit */
richardv	0:b079fa4ed182	2095	tmpccer &= (uint32_t)(~TIM_CCER_CC2P);
richardv	0:b079fa4ed182	2096	tmpccer \|= ((uint32_t)TIM_OCPolarity << 4);
richardv	0:b079fa4ed182	2097
richardv	0:b079fa4ed182	2098	/* Write to TIMx CCER register */
richardv	0:b079fa4ed182	2099	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	2100	}
richardv	0:b079fa4ed182	2101
richardv	0:b079fa4ed182	2102	/**
richardv	0:b079fa4ed182	2103	* @brief Configures the TIMx Channel 2N polarity.
richardv	0:b079fa4ed182	2104	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	2105	* @param TIM_OCNPolarity: specifies the OC2N Polarity
richardv	0:b079fa4ed182	2106	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2107	* @arg TIM_OCNPolarity_High: Output Compare active high
richardv	0:b079fa4ed182	2108	* @arg TIM_OCNPolarity_Low: Output Compare active low
richardv	0:b079fa4ed182	2109	* @retval None
richardv	0:b079fa4ed182	2110	*/
richardv	0:b079fa4ed182	2111	void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
richardv	0:b079fa4ed182	2112	{
richardv	0:b079fa4ed182	2113	uint32_t tmpccer = 0;
richardv	0:b079fa4ed182	2114
richardv	0:b079fa4ed182	2115	/* Check the parameters */
richardv	0:b079fa4ed182	2116	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	2117	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
richardv	0:b079fa4ed182	2118
richardv	0:b079fa4ed182	2119	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	2120
richardv	0:b079fa4ed182	2121	/* Set or Reset the CC2NP Bit */
richardv	0:b079fa4ed182	2122	tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
richardv	0:b079fa4ed182	2123	tmpccer \|= ((uint32_t)TIM_OCNPolarity << 4);
richardv	0:b079fa4ed182	2124
richardv	0:b079fa4ed182	2125	/* Write to TIMx CCER register */
richardv	0:b079fa4ed182	2126	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	2127	}
richardv	0:b079fa4ed182	2128
richardv	0:b079fa4ed182	2129	/**
richardv	0:b079fa4ed182	2130	* @brief Configures the TIMx channel 3 polarity.
richardv	0:b079fa4ed182	2131	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	2132	* @param TIM_OCPolarity: specifies the OC3 Polarity
richardv	0:b079fa4ed182	2133	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2134	* @arg TIM_OCPolarity_High: Output Compare active high
richardv	0:b079fa4ed182	2135	* @arg TIM_OCPolarity_Low: Output Compare active low
richardv	0:b079fa4ed182	2136	* @retval None
richardv	0:b079fa4ed182	2137	*/
richardv	0:b079fa4ed182	2138	void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
richardv	0:b079fa4ed182	2139	{
richardv	0:b079fa4ed182	2140	uint32_t tmpccer = 0;
richardv	0:b079fa4ed182	2141
richardv	0:b079fa4ed182	2142	/* Check the parameters */
richardv	0:b079fa4ed182	2143	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	2144	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
richardv	0:b079fa4ed182	2145
richardv	0:b079fa4ed182	2146	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	2147
richardv	0:b079fa4ed182	2148	/* Set or Reset the CC3P Bit */
richardv	0:b079fa4ed182	2149	tmpccer &= (uint32_t)~TIM_CCER_CC3P;
richardv	0:b079fa4ed182	2150	tmpccer \|= ((uint32_t)TIM_OCPolarity << 8);
richardv	0:b079fa4ed182	2151
richardv	0:b079fa4ed182	2152	/* Write to TIMx CCER register */
richardv	0:b079fa4ed182	2153	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	2154	}
richardv	0:b079fa4ed182	2155
richardv	0:b079fa4ed182	2156	/**
richardv	0:b079fa4ed182	2157	* @brief Configures the TIMx Channel 3N polarity.
richardv	0:b079fa4ed182	2158	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	2159	* @param TIM_OCNPolarity: specifies the OC3N Polarity
richardv	0:b079fa4ed182	2160	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2161	* @arg TIM_OCNPolarity_High: Output Compare active high
richardv	0:b079fa4ed182	2162	* @arg TIM_OCNPolarity_Low: Output Compare active low
richardv	0:b079fa4ed182	2163	* @retval None
richardv	0:b079fa4ed182	2164	*/
richardv	0:b079fa4ed182	2165	void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
richardv	0:b079fa4ed182	2166	{
richardv	0:b079fa4ed182	2167	uint32_t tmpccer = 0;
richardv	0:b079fa4ed182	2168
richardv	0:b079fa4ed182	2169	/* Check the parameters */
richardv	0:b079fa4ed182	2170	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	2171	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
richardv	0:b079fa4ed182	2172
richardv	0:b079fa4ed182	2173	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	2174
richardv	0:b079fa4ed182	2175	/* Set or Reset the CC3NP Bit */
richardv	0:b079fa4ed182	2176	tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
richardv	0:b079fa4ed182	2177	tmpccer \|= ((uint32_t)TIM_OCNPolarity << 8);
richardv	0:b079fa4ed182	2178
richardv	0:b079fa4ed182	2179	/* Write to TIMx CCER register */
richardv	0:b079fa4ed182	2180	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	2181	}
richardv	0:b079fa4ed182	2182
richardv	0:b079fa4ed182	2183	/**
richardv	0:b079fa4ed182	2184	* @brief Configures the TIMx channel 4 polarity.
richardv	0:b079fa4ed182	2185	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	2186	* @param TIM_OCPolarity: specifies the OC4 Polarity
richardv	0:b079fa4ed182	2187	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2188	* @arg TIM_OCPolarity_High: Output Compare active high
richardv	0:b079fa4ed182	2189	* @arg TIM_OCPolarity_Low: Output Compare active low
richardv	0:b079fa4ed182	2190	* @retval None
richardv	0:b079fa4ed182	2191	*/
richardv	0:b079fa4ed182	2192	void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
richardv	0:b079fa4ed182	2193	{
richardv	0:b079fa4ed182	2194	uint32_t tmpccer = 0;
richardv	0:b079fa4ed182	2195
richardv	0:b079fa4ed182	2196	/* Check the parameters */
richardv	0:b079fa4ed182	2197	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	2198	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
richardv	0:b079fa4ed182	2199
richardv	0:b079fa4ed182	2200	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	2201
richardv	0:b079fa4ed182	2202	/* Set or Reset the CC4P Bit */
richardv	0:b079fa4ed182	2203	tmpccer &= (uint32_t)~TIM_CCER_CC4P;
richardv	0:b079fa4ed182	2204	tmpccer \|= ((uint32_t)TIM_OCPolarity << 12);
richardv	0:b079fa4ed182	2205
richardv	0:b079fa4ed182	2206	/* Write to TIMx CCER register */
richardv	0:b079fa4ed182	2207	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	2208	}
richardv	0:b079fa4ed182	2209
richardv	0:b079fa4ed182	2210	/**
richardv	0:b079fa4ed182	2211	* @brief Configures the TIMx channel 5 polarity.
richardv	0:b079fa4ed182	2212	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	2213	* @param TIM_OCPolarity: specifies the OC5 Polarity
richardv	0:b079fa4ed182	2214	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2215	* @arg TIM_OCPolarity_High: Output Compare active high
richardv	0:b079fa4ed182	2216	* @arg TIM_OCPolarity_Low: Output Compare active low
richardv	0:b079fa4ed182	2217	* @retval None
richardv	0:b079fa4ed182	2218	*/
richardv	0:b079fa4ed182	2219	void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
richardv	0:b079fa4ed182	2220	{
richardv	0:b079fa4ed182	2221	uint32_t tmpccer = 0;
richardv	0:b079fa4ed182	2222
richardv	0:b079fa4ed182	2223	/* Check the parameters */
richardv	0:b079fa4ed182	2224	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	2225	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
richardv	0:b079fa4ed182	2226
richardv	0:b079fa4ed182	2227	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	2228
richardv	0:b079fa4ed182	2229	/* Set or Reset the CC5P Bit */
richardv	0:b079fa4ed182	2230	tmpccer &= (uint32_t)~TIM_CCER_CC5P;
richardv	0:b079fa4ed182	2231	tmpccer \|= ((uint32_t)TIM_OCPolarity << 16);
richardv	0:b079fa4ed182	2232
richardv	0:b079fa4ed182	2233	/* Write to TIMx CCER register */
richardv	0:b079fa4ed182	2234	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	2235	}
richardv	0:b079fa4ed182	2236
richardv	0:b079fa4ed182	2237	/**
richardv	0:b079fa4ed182	2238	* @brief Configures the TIMx channel 6 polarity.
richardv	0:b079fa4ed182	2239	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	2240	* @param TIM_OCPolarity: specifies the OC6 Polarity
richardv	0:b079fa4ed182	2241	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2242	* @arg TIM_OCPolarity_High: Output Compare active high
richardv	0:b079fa4ed182	2243	* @arg TIM_OCPolarity_Low: Output Compare active low
richardv	0:b079fa4ed182	2244	* @retval None
richardv	0:b079fa4ed182	2245	*/
richardv	0:b079fa4ed182	2246	void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
richardv	0:b079fa4ed182	2247	{
richardv	0:b079fa4ed182	2248	uint32_t tmpccer = 0;
richardv	0:b079fa4ed182	2249
richardv	0:b079fa4ed182	2250	/* Check the parameters */
richardv	0:b079fa4ed182	2251	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	2252	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
richardv	0:b079fa4ed182	2253
richardv	0:b079fa4ed182	2254	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	2255
richardv	0:b079fa4ed182	2256	/* Set or Reset the CC6P Bit */
richardv	0:b079fa4ed182	2257	tmpccer &= (uint32_t)~TIM_CCER_CC6P;
richardv	0:b079fa4ed182	2258	tmpccer \|= ((uint32_t)TIM_OCPolarity << 20);
richardv	0:b079fa4ed182	2259
richardv	0:b079fa4ed182	2260	/* Write to TIMx CCER register */
richardv	0:b079fa4ed182	2261	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	2262	}
richardv	0:b079fa4ed182	2263
richardv	0:b079fa4ed182	2264	/**
richardv	0:b079fa4ed182	2265	* @brief Enables or disables the TIM Capture Compare Channel x.
richardv	0:b079fa4ed182	2266	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	2267	* @param TIM_Channel: specifies the TIM Channel
richardv	0:b079fa4ed182	2268	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2269	* @arg TIM_Channel_1: TIM Channel 1
richardv	0:b079fa4ed182	2270	* @arg TIM_Channel_2: TIM Channel 2
richardv	0:b079fa4ed182	2271	* @arg TIM_Channel_3: TIM Channel 3
richardv	0:b079fa4ed182	2272	* @arg TIM_Channel_4: TIM Channel 4
richardv	0:b079fa4ed182	2273	* @arg TIM_Channel_5: TIM Channel 5
richardv	0:b079fa4ed182	2274	* @arg TIM_Channel_6: TIM Channel 6
richardv	0:b079fa4ed182	2275	* @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
richardv	0:b079fa4ed182	2276	* This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
richardv	0:b079fa4ed182	2277	* @retval None
richardv	0:b079fa4ed182	2278	*/
richardv	0:b079fa4ed182	2279	void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
richardv	0:b079fa4ed182	2280	{
richardv	0:b079fa4ed182	2281	uint32_t tmp = 0;
richardv	0:b079fa4ed182	2282
richardv	0:b079fa4ed182	2283	/* Check the parameters */
richardv	0:b079fa4ed182	2284	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	2285	assert_param(IS_TIM_CHANNEL(TIM_Channel));
richardv	0:b079fa4ed182	2286	assert_param(IS_TIM_CCX(TIM_CCx));
richardv	0:b079fa4ed182	2287
richardv	0:b079fa4ed182	2288	tmp = (uint32_t)CCER_CCE_SET << (uint32_t)TIM_Channel;
richardv	0:b079fa4ed182	2289
richardv	0:b079fa4ed182	2290	/* Reset the CCxE Bit */
richardv	0:b079fa4ed182	2291	TIMx->CCER &= (uint32_t)(~tmp);
richardv	0:b079fa4ed182	2292
richardv	0:b079fa4ed182	2293	/* Set or reset the CCxE Bit */
richardv	0:b079fa4ed182	2294	TIMx->CCER \|= ((uint32_t)TIM_CCx << (uint32_t)TIM_Channel);
richardv	0:b079fa4ed182	2295	}
richardv	0:b079fa4ed182	2296
richardv	0:b079fa4ed182	2297	/**
richardv	0:b079fa4ed182	2298	* @brief Enables or disables the TIM Capture Compare Channel xN.
richardv	0:b079fa4ed182	2299	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	2300	* @param TIM_Channel: specifies the TIM Channel
richardv	0:b079fa4ed182	2301	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2302	* @arg TIM_Channel_1: TIM Channel 1
richardv	0:b079fa4ed182	2303	* @arg TIM_Channel_2: TIM Channel 2
richardv	0:b079fa4ed182	2304	* @arg TIM_Channel_3: TIM Channel 3
richardv	0:b079fa4ed182	2305	* @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
richardv	0:b079fa4ed182	2306	* This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
richardv	0:b079fa4ed182	2307	* @retval None
richardv	0:b079fa4ed182	2308	*/
richardv	0:b079fa4ed182	2309	void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
richardv	0:b079fa4ed182	2310	{
richardv	0:b079fa4ed182	2311	uint32_t tmp = 0;
richardv	0:b079fa4ed182	2312
richardv	0:b079fa4ed182	2313	/* Check the parameters */
richardv	0:b079fa4ed182	2314	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
richardv	0:b079fa4ed182	2315	assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
richardv	0:b079fa4ed182	2316	assert_param(IS_TIM_CCXN(TIM_CCxN));
richardv	0:b079fa4ed182	2317
richardv	0:b079fa4ed182	2318	tmp = (uint32_t)CCER_CCNE_SET << (uint32_t)TIM_Channel;
richardv	0:b079fa4ed182	2319
richardv	0:b079fa4ed182	2320	/* Reset the CCxNE Bit */
richardv	0:b079fa4ed182	2321	TIMx->CCER &= (uint32_t) ~tmp;
richardv	0:b079fa4ed182	2322
richardv	0:b079fa4ed182	2323	/* Set or reset the CCxNE Bit */
richardv	0:b079fa4ed182	2324	TIMx->CCER \|= ((uint32_t)TIM_CCxN << (uint32_t)TIM_Channel);
richardv	0:b079fa4ed182	2325	}
richardv	0:b079fa4ed182	2326	/**
richardv	0:b079fa4ed182	2327	* @}
richardv	0:b079fa4ed182	2328	*/
richardv	0:b079fa4ed182	2329
richardv	0:b079fa4ed182	2330	/** @defgroup TIM_Group3 Input Capture management functions
richardv	0:b079fa4ed182	2331	* @brief Input Capture management functions
richardv	0:b079fa4ed182	2332	*
richardv	0:b079fa4ed182	2333	@verbatim
richardv	0:b079fa4ed182	2334	===============================================================================
richardv	0:b079fa4ed182	2335	##### Input Capture management functions #####
richardv	0:b079fa4ed182	2336	===============================================================================
richardv	0:b079fa4ed182	2337
richardv	0:b079fa4ed182	2338	* TIM Driver: how to use it in Input Capture Mode *
richardv	0:b079fa4ed182	2339	=======================================================
richardv	0:b079fa4ed182	2340	[..]
richardv	0:b079fa4ed182	2341	To use the Timer in Input Capture mode, the following steps are mandatory:
richardv	0:b079fa4ed182	2342
richardv	0:b079fa4ed182	2343	(#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
richardv	0:b079fa4ed182	2344
richardv	0:b079fa4ed182	2345	(#) Configure the TIM pins by configuring the corresponding GPIO pins
richardv	0:b079fa4ed182	2346
richardv	0:b079fa4ed182	2347	(#) Configure the Time base unit as described in the first part of this driver,
richardv	0:b079fa4ed182	2348	if needed, else the Timer will run with the default configuration:
richardv	0:b079fa4ed182	2349	(++) Autoreload value = 0xFFFF
richardv	0:b079fa4ed182	2350	(++) Prescaler value = 0x0000
richardv	0:b079fa4ed182	2351	(++) Counter mode = Up counting
richardv	0:b079fa4ed182	2352	(++) Clock Division = TIM_CKD_DIV1
richardv	0:b079fa4ed182	2353
richardv	0:b079fa4ed182	2354	(#) Fill the TIM_ICInitStruct with the desired parameters including:
richardv	0:b079fa4ed182	2355	(++) TIM Channel: TIM_Channel
richardv	0:b079fa4ed182	2356	(++) TIM Input Capture polarity: TIM_ICPolarity
richardv	0:b079fa4ed182	2357	(++) TIM Input Capture selection: TIM_ICSelection
richardv	0:b079fa4ed182	2358	(++) TIM Input Capture Prescaler: TIM_ICPrescaler
richardv	0:b079fa4ed182	2359	(++) TIM Input CApture filter value: TIM_ICFilter
richardv	0:b079fa4ed182	2360
richardv	0:b079fa4ed182	2361	(#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the
richardv	0:b079fa4ed182	2362	corresponding configuration and to measure only frequency or duty cycle of the input signal,
richardv	0:b079fa4ed182	2363	or,
richardv	0:b079fa4ed182	2364	Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the
richardv	0:b079fa4ed182	2365	corresponding configuration and to measure the frequency and the duty cycle of the input signal
richardv	0:b079fa4ed182	2366
richardv	0:b079fa4ed182	2367	(#) Enable the NVIC or the DMA to read the measured frequency.
richardv	0:b079fa4ed182	2368
richardv	0:b079fa4ed182	2369	(#) Enable the corresponding interrupt (or DMA request) to read the Captured value,
richardv	0:b079fa4ed182	2370	using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
richardv	0:b079fa4ed182	2371
richardv	0:b079fa4ed182	2372	(#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
richardv	0:b079fa4ed182	2373
richardv	0:b079fa4ed182	2374	(#) Use TIM_GetCapturex(TIMx); to read the captured value.
richardv	0:b079fa4ed182	2375	[..]
richardv	0:b079fa4ed182	2376	(@) All other functions can be used separately to modify, if needed,
richardv	0:b079fa4ed182	2377	a specific feature of the Timer.
richardv	0:b079fa4ed182	2378
richardv	0:b079fa4ed182	2379	@endverbatim
richardv	0:b079fa4ed182	2380	* @{
richardv	0:b079fa4ed182	2381	*/
richardv	0:b079fa4ed182	2382
richardv	0:b079fa4ed182	2383	/**
richardv	0:b079fa4ed182	2384	* @brief Initializes the TIM peripheral according to the specified parameters
richardv	0:b079fa4ed182	2385	* in the TIM_ICInitStruct.
richardv	0:b079fa4ed182	2386	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	2387	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
richardv	0:b079fa4ed182	2388	* the configuration information for the specified TIM peripheral.
richardv	0:b079fa4ed182	2389	* @retval None
richardv	0:b079fa4ed182	2390	*/
richardv	0:b079fa4ed182	2391	void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
richardv	0:b079fa4ed182	2392	{
richardv	0:b079fa4ed182	2393	/* Check the parameters */
richardv	0:b079fa4ed182	2394	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	2395	assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
richardv	0:b079fa4ed182	2396	assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
richardv	0:b079fa4ed182	2397	assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
richardv	0:b079fa4ed182	2398	assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
richardv	0:b079fa4ed182	2399
richardv	0:b079fa4ed182	2400	if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
richardv	0:b079fa4ed182	2401	{
richardv	0:b079fa4ed182	2402	/* TI1 Configuration */
richardv	0:b079fa4ed182	2403	TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
richardv	0:b079fa4ed182	2404	TIM_ICInitStruct->TIM_ICSelection,
richardv	0:b079fa4ed182	2405	TIM_ICInitStruct->TIM_ICFilter);
richardv	0:b079fa4ed182	2406	/* Set the Input Capture Prescaler value */
richardv	0:b079fa4ed182	2407	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
richardv	0:b079fa4ed182	2408	}
richardv	0:b079fa4ed182	2409	else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
richardv	0:b079fa4ed182	2410	{
richardv	0:b079fa4ed182	2411	/* TI2 Configuration */
richardv	0:b079fa4ed182	2412	TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
richardv	0:b079fa4ed182	2413	TIM_ICInitStruct->TIM_ICSelection,
richardv	0:b079fa4ed182	2414	TIM_ICInitStruct->TIM_ICFilter);
richardv	0:b079fa4ed182	2415	/* Set the Input Capture Prescaler value */
richardv	0:b079fa4ed182	2416	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
richardv	0:b079fa4ed182	2417	}
richardv	0:b079fa4ed182	2418	else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
richardv	0:b079fa4ed182	2419	{
richardv	0:b079fa4ed182	2420	/* TI3 Configuration */
richardv	0:b079fa4ed182	2421	TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
richardv	0:b079fa4ed182	2422	TIM_ICInitStruct->TIM_ICSelection,
richardv	0:b079fa4ed182	2423	TIM_ICInitStruct->TIM_ICFilter);
richardv	0:b079fa4ed182	2424	/* Set the Input Capture Prescaler value */
richardv	0:b079fa4ed182	2425	TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
richardv	0:b079fa4ed182	2426	}
richardv	0:b079fa4ed182	2427	else
richardv	0:b079fa4ed182	2428	{
richardv	0:b079fa4ed182	2429	/* TI4 Configuration */
richardv	0:b079fa4ed182	2430	TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
richardv	0:b079fa4ed182	2431	TIM_ICInitStruct->TIM_ICSelection,
richardv	0:b079fa4ed182	2432	TIM_ICInitStruct->TIM_ICFilter);
richardv	0:b079fa4ed182	2433	/* Set the Input Capture Prescaler value */
richardv	0:b079fa4ed182	2434	TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
richardv	0:b079fa4ed182	2435	}
richardv	0:b079fa4ed182	2436	}
richardv	0:b079fa4ed182	2437
richardv	0:b079fa4ed182	2438	/**
richardv	0:b079fa4ed182	2439	* @brief Fills each TIM_ICInitStruct member with its default value.
richardv	0:b079fa4ed182	2440	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
richardv	0:b079fa4ed182	2441	* be initialized.
richardv	0:b079fa4ed182	2442	* @retval None
richardv	0:b079fa4ed182	2443	*/
richardv	0:b079fa4ed182	2444	void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
richardv	0:b079fa4ed182	2445	{
richardv	0:b079fa4ed182	2446	/* Set the default configuration */
richardv	0:b079fa4ed182	2447	TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
richardv	0:b079fa4ed182	2448	TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
richardv	0:b079fa4ed182	2449	TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
richardv	0:b079fa4ed182	2450	TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
richardv	0:b079fa4ed182	2451	TIM_ICInitStruct->TIM_ICFilter = 0x00;
richardv	0:b079fa4ed182	2452	}
richardv	0:b079fa4ed182	2453
richardv	0:b079fa4ed182	2454	/**
richardv	0:b079fa4ed182	2455	* @brief Configures the TIM peripheral according to the specified parameters
richardv	0:b079fa4ed182	2456	* in the TIM_ICInitStruct to measure an external PWM signal.
richardv	0:b079fa4ed182	2457	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
richardv	0:b079fa4ed182	2458	* peripheral.
richardv	0:b079fa4ed182	2459	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
richardv	0:b079fa4ed182	2460	* the configuration information for the specified TIM peripheral.
richardv	0:b079fa4ed182	2461	* @retval None
richardv	0:b079fa4ed182	2462	*/
richardv	0:b079fa4ed182	2463	void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
richardv	0:b079fa4ed182	2464	{
richardv	0:b079fa4ed182	2465	uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
richardv	0:b079fa4ed182	2466	uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
richardv	0:b079fa4ed182	2467
richardv	0:b079fa4ed182	2468	/* Check the parameters */
richardv	0:b079fa4ed182	2469	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	2470
richardv	0:b079fa4ed182	2471	/* Select the Opposite Input Polarity */
richardv	0:b079fa4ed182	2472	if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
richardv	0:b079fa4ed182	2473	{
richardv	0:b079fa4ed182	2474	icoppositepolarity = TIM_ICPolarity_Falling;
richardv	0:b079fa4ed182	2475	}
richardv	0:b079fa4ed182	2476	else
richardv	0:b079fa4ed182	2477	{
richardv	0:b079fa4ed182	2478	icoppositepolarity = TIM_ICPolarity_Rising;
richardv	0:b079fa4ed182	2479	}
richardv	0:b079fa4ed182	2480	/* Select the Opposite Input */
richardv	0:b079fa4ed182	2481	if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
richardv	0:b079fa4ed182	2482	{
richardv	0:b079fa4ed182	2483	icoppositeselection = TIM_ICSelection_IndirectTI;
richardv	0:b079fa4ed182	2484	}
richardv	0:b079fa4ed182	2485	else
richardv	0:b079fa4ed182	2486	{
richardv	0:b079fa4ed182	2487	icoppositeselection = TIM_ICSelection_DirectTI;
richardv	0:b079fa4ed182	2488	}
richardv	0:b079fa4ed182	2489	if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
richardv	0:b079fa4ed182	2490	{
richardv	0:b079fa4ed182	2491	/* TI1 Configuration */
richardv	0:b079fa4ed182	2492	TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
richardv	0:b079fa4ed182	2493	TIM_ICInitStruct->TIM_ICFilter);
richardv	0:b079fa4ed182	2494	/* Set the Input Capture Prescaler value */
richardv	0:b079fa4ed182	2495	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
richardv	0:b079fa4ed182	2496	/* TI2 Configuration */
richardv	0:b079fa4ed182	2497	TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
richardv	0:b079fa4ed182	2498	/* Set the Input Capture Prescaler value */
richardv	0:b079fa4ed182	2499	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
richardv	0:b079fa4ed182	2500	}
richardv	0:b079fa4ed182	2501	else
richardv	0:b079fa4ed182	2502	{
richardv	0:b079fa4ed182	2503	/* TI2 Configuration */
richardv	0:b079fa4ed182	2504	TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
richardv	0:b079fa4ed182	2505	TIM_ICInitStruct->TIM_ICFilter);
richardv	0:b079fa4ed182	2506	/* Set the Input Capture Prescaler value */
richardv	0:b079fa4ed182	2507	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
richardv	0:b079fa4ed182	2508	/* TI1 Configuration */
richardv	0:b079fa4ed182	2509	TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
richardv	0:b079fa4ed182	2510	/* Set the Input Capture Prescaler value */
richardv	0:b079fa4ed182	2511	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
richardv	0:b079fa4ed182	2512	}
richardv	0:b079fa4ed182	2513	}
richardv	0:b079fa4ed182	2514
richardv	0:b079fa4ed182	2515	/**
richardv	0:b079fa4ed182	2516	* @brief Gets the TIMx Input Capture 1 value.
richardv	0:b079fa4ed182	2517	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	2518	* @retval Capture Compare 1 Register value.
richardv	0:b079fa4ed182	2519	*/
richardv	0:b079fa4ed182	2520	uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
richardv	0:b079fa4ed182	2521	{
richardv	0:b079fa4ed182	2522	/* Check the parameters */
richardv	0:b079fa4ed182	2523	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	2524
richardv	0:b079fa4ed182	2525	/* Get the Capture 1 Register value */
richardv	0:b079fa4ed182	2526	return TIMx->CCR1;
richardv	0:b079fa4ed182	2527	}
richardv	0:b079fa4ed182	2528
richardv	0:b079fa4ed182	2529	/**
richardv	0:b079fa4ed182	2530	* @brief Gets the TIMx Input Capture 2 value.
richardv	0:b079fa4ed182	2531	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
richardv	0:b079fa4ed182	2532	* peripheral.
richardv	0:b079fa4ed182	2533	* @retval Capture Compare 2 Register value.
richardv	0:b079fa4ed182	2534	*/
richardv	0:b079fa4ed182	2535	uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
richardv	0:b079fa4ed182	2536	{
richardv	0:b079fa4ed182	2537	/* Check the parameters */
richardv	0:b079fa4ed182	2538	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	2539
richardv	0:b079fa4ed182	2540	/* Get the Capture 2 Register value */
richardv	0:b079fa4ed182	2541	return TIMx->CCR2;
richardv	0:b079fa4ed182	2542	}
richardv	0:b079fa4ed182	2543
richardv	0:b079fa4ed182	2544	/**
richardv	0:b079fa4ed182	2545	* @brief Gets the TIMx Input Capture 3 value.
richardv	0:b079fa4ed182	2546	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	2547	* @retval Capture Compare 3 Register value.
richardv	0:b079fa4ed182	2548	*/
richardv	0:b079fa4ed182	2549	uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
richardv	0:b079fa4ed182	2550	{
richardv	0:b079fa4ed182	2551	/* Check the parameters */
richardv	0:b079fa4ed182	2552	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	2553
richardv	0:b079fa4ed182	2554	/* Get the Capture 3 Register value */
richardv	0:b079fa4ed182	2555	return TIMx->CCR3;
richardv	0:b079fa4ed182	2556	}
richardv	0:b079fa4ed182	2557
richardv	0:b079fa4ed182	2558	/**
richardv	0:b079fa4ed182	2559	* @brief Gets the TIMx Input Capture 4 value.
richardv	0:b079fa4ed182	2560	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	2561	* @retval Capture Compare 4 Register value.
richardv	0:b079fa4ed182	2562	*/
richardv	0:b079fa4ed182	2563	uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
richardv	0:b079fa4ed182	2564	{
richardv	0:b079fa4ed182	2565	/* Check the parameters */
richardv	0:b079fa4ed182	2566	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	2567
richardv	0:b079fa4ed182	2568	/* Get the Capture 4 Register value */
richardv	0:b079fa4ed182	2569	return TIMx->CCR4;
richardv	0:b079fa4ed182	2570	}
richardv	0:b079fa4ed182	2571
richardv	0:b079fa4ed182	2572	/**
richardv	0:b079fa4ed182	2573	* @brief Sets the TIMx Input Capture 1 prescaler.
richardv	0:b079fa4ed182	2574	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	2575	* @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
richardv	0:b079fa4ed182	2576	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2577	* @arg TIM_ICPSC_DIV1: no prescaler
richardv	0:b079fa4ed182	2578	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
richardv	0:b079fa4ed182	2579	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
richardv	0:b079fa4ed182	2580	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
richardv	0:b079fa4ed182	2581	* @retval None
richardv	0:b079fa4ed182	2582	*/
richardv	0:b079fa4ed182	2583	void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
richardv	0:b079fa4ed182	2584	{
richardv	0:b079fa4ed182	2585	/* Check the parameters */
richardv	0:b079fa4ed182	2586	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	2587	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
richardv	0:b079fa4ed182	2588
richardv	0:b079fa4ed182	2589	/* Reset the IC1PSC Bits */
richardv	0:b079fa4ed182	2590	TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC1PSC;
richardv	0:b079fa4ed182	2591
richardv	0:b079fa4ed182	2592	/* Set the IC1PSC value */
richardv	0:b079fa4ed182	2593	TIMx->CCMR1 \|= TIM_ICPSC;
richardv	0:b079fa4ed182	2594	}
richardv	0:b079fa4ed182	2595
richardv	0:b079fa4ed182	2596	/**
richardv	0:b079fa4ed182	2597	* @brief Sets the TIMx Input Capture 2 prescaler.
richardv	0:b079fa4ed182	2598	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
richardv	0:b079fa4ed182	2599	* peripheral.
richardv	0:b079fa4ed182	2600	* @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
richardv	0:b079fa4ed182	2601	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2602	* @arg TIM_ICPSC_DIV1: no prescaler
richardv	0:b079fa4ed182	2603	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
richardv	0:b079fa4ed182	2604	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
richardv	0:b079fa4ed182	2605	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
richardv	0:b079fa4ed182	2606	* @retval None
richardv	0:b079fa4ed182	2607	*/
richardv	0:b079fa4ed182	2608	void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
richardv	0:b079fa4ed182	2609	{
richardv	0:b079fa4ed182	2610	/* Check the parameters */
richardv	0:b079fa4ed182	2611	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	2612	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
richardv	0:b079fa4ed182	2613
richardv	0:b079fa4ed182	2614	/* Reset the IC2PSC Bits */
richardv	0:b079fa4ed182	2615	TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC2PSC;
richardv	0:b079fa4ed182	2616
richardv	0:b079fa4ed182	2617	/* Set the IC2PSC value */
richardv	0:b079fa4ed182	2618	TIMx->CCMR1 \|= (uint32_t)((uint32_t)TIM_ICPSC << 8);
richardv	0:b079fa4ed182	2619	}
richardv	0:b079fa4ed182	2620
richardv	0:b079fa4ed182	2621	/**
richardv	0:b079fa4ed182	2622	* @brief Sets the TIMx Input Capture 3 prescaler.
richardv	0:b079fa4ed182	2623	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	2624	* @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
richardv	0:b079fa4ed182	2625	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2626	* @arg TIM_ICPSC_DIV1: no prescaler
richardv	0:b079fa4ed182	2627	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
richardv	0:b079fa4ed182	2628	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
richardv	0:b079fa4ed182	2629	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
richardv	0:b079fa4ed182	2630	* @retval None
richardv	0:b079fa4ed182	2631	*/
richardv	0:b079fa4ed182	2632	void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
richardv	0:b079fa4ed182	2633	{
richardv	0:b079fa4ed182	2634	/* Check the parameters */
richardv	0:b079fa4ed182	2635	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	2636	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
richardv	0:b079fa4ed182	2637
richardv	0:b079fa4ed182	2638	/* Reset the IC3PSC Bits */
richardv	0:b079fa4ed182	2639	TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
richardv	0:b079fa4ed182	2640
richardv	0:b079fa4ed182	2641	/* Set the IC3PSC value */
richardv	0:b079fa4ed182	2642	TIMx->CCMR2 \|= TIM_ICPSC;
richardv	0:b079fa4ed182	2643	}
richardv	0:b079fa4ed182	2644
richardv	0:b079fa4ed182	2645	/**
richardv	0:b079fa4ed182	2646	* @brief Sets the TIMx Input Capture 4 prescaler.
richardv	0:b079fa4ed182	2647	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	2648	* @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
richardv	0:b079fa4ed182	2649	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2650	* @arg TIM_ICPSC_DIV1: no prescaler
richardv	0:b079fa4ed182	2651	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
richardv	0:b079fa4ed182	2652	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
richardv	0:b079fa4ed182	2653	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
richardv	0:b079fa4ed182	2654	* @retval None
richardv	0:b079fa4ed182	2655	*/
richardv	0:b079fa4ed182	2656	void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
richardv	0:b079fa4ed182	2657	{
richardv	0:b079fa4ed182	2658	/* Check the parameters */
richardv	0:b079fa4ed182	2659	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	2660	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
richardv	0:b079fa4ed182	2661
richardv	0:b079fa4ed182	2662	/* Reset the IC4PSC Bits */
richardv	0:b079fa4ed182	2663	TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
richardv	0:b079fa4ed182	2664
richardv	0:b079fa4ed182	2665	/* Set the IC4PSC value */
richardv	0:b079fa4ed182	2666	TIMx->CCMR2 \|= (uint16_t)(TIM_ICPSC << 8);
richardv	0:b079fa4ed182	2667	}
richardv	0:b079fa4ed182	2668	/**
richardv	0:b079fa4ed182	2669	* @}
richardv	0:b079fa4ed182	2670	*/
richardv	0:b079fa4ed182	2671
richardv	0:b079fa4ed182	2672	/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
richardv	0:b079fa4ed182	2673	* @brief Advanced-control timers (TIM1 and TIM8) specific features
richardv	0:b079fa4ed182	2674	*
richardv	0:b079fa4ed182	2675	@verbatim
richardv	0:b079fa4ed182	2676	===============================================================================
richardv	0:b079fa4ed182	2677	##### Advanced-control timers (TIM1 and TIM8) specific features #####
richardv	0:b079fa4ed182	2678	===============================================================================
richardv	0:b079fa4ed182	2679
richardv	0:b079fa4ed182	2680	* TIM Driver: how to use the Break feature *
richardv	0:b079fa4ed182	2681	================================================
richardv	0:b079fa4ed182	2682	[..]
richardv	0:b079fa4ed182	2683	After configuring the Timer channel(s) in the appropriate Output Compare mode:
richardv	0:b079fa4ed182	2684
richardv	0:b079fa4ed182	2685	(#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
richardv	0:b079fa4ed182	2686	Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
richardv	0:b079fa4ed182	2687	AOE(automatic output enable).
richardv	0:b079fa4ed182	2688
richardv	0:b079fa4ed182	2689	(#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
richardv	0:b079fa4ed182	2690
richardv	0:b079fa4ed182	2691	(#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
richardv	0:b079fa4ed182	2692
richardv	0:b079fa4ed182	2693	(#) Once the break even occurs, the Timer's output signals are put in reset
richardv	0:b079fa4ed182	2694	state or in a known state (according to the configuration made in
richardv	0:b079fa4ed182	2695	TIM_BDTRConfig() function).
richardv	0:b079fa4ed182	2696
richardv	0:b079fa4ed182	2697	@endverbatim
richardv	0:b079fa4ed182	2698	* @{
richardv	0:b079fa4ed182	2699	*/
richardv	0:b079fa4ed182	2700
richardv	0:b079fa4ed182	2701	/**
richardv	0:b079fa4ed182	2702	* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
richardv	0:b079fa4ed182	2703	* and the AOE(automatic output enable).
richardv	0:b079fa4ed182	2704	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM
richardv	0:b079fa4ed182	2705	* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
richardv	0:b079fa4ed182	2706	* contains the BDTR Register configuration information for the TIM peripheral.
richardv	0:b079fa4ed182	2707	* @retval None
richardv	0:b079fa4ed182	2708	*/
richardv	0:b079fa4ed182	2709	void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
richardv	0:b079fa4ed182	2710	{
richardv	0:b079fa4ed182	2711	/* Check the parameters */
richardv	0:b079fa4ed182	2712	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
richardv	0:b079fa4ed182	2713	assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
richardv	0:b079fa4ed182	2714	assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
richardv	0:b079fa4ed182	2715	assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
richardv	0:b079fa4ed182	2716	assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
richardv	0:b079fa4ed182	2717	assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
richardv	0:b079fa4ed182	2718	assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
richardv	0:b079fa4ed182	2719
richardv	0:b079fa4ed182	2720	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
richardv	0:b079fa4ed182	2721	the OSSI State, the dead time value and the Automatic Output Enable Bit */
richardv	0:b079fa4ed182	2722	TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState \| TIM_BDTRInitStruct->TIM_OSSIState \|
richardv	0:b079fa4ed182	2723	TIM_BDTRInitStruct->TIM_LOCKLevel \| TIM_BDTRInitStruct->TIM_DeadTime \|
richardv	0:b079fa4ed182	2724	TIM_BDTRInitStruct->TIM_Break \| TIM_BDTRInitStruct->TIM_BreakPolarity \|
richardv	0:b079fa4ed182	2725	TIM_BDTRInitStruct->TIM_AutomaticOutput;
richardv	0:b079fa4ed182	2726	}
richardv	0:b079fa4ed182	2727
richardv	0:b079fa4ed182	2728	/**
richardv	0:b079fa4ed182	2729	* @brief Configures the Break1 feature.
richardv	0:b079fa4ed182	2730	* @param TIMx: where x can be 1 or 8 to select the TIM
richardv	0:b079fa4ed182	2731	* @param TIM_Break1Polarity: specifies the Break1 polarity.
richardv	0:b079fa4ed182	2732	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2733	* @arg TIM_Break1Polarity_Low: Break1 input is active low
richardv	0:b079fa4ed182	2734	* @arg TIM_Break1Polarity_High: Break1 input is active high
richardv	0:b079fa4ed182	2735	* @param TIM_Break1Filter: specifies the Break1 filter value.
richardv	0:b079fa4ed182	2736	* This parameter must be a value between 0x00 and 0x0F
richardv	0:b079fa4ed182	2737	* @retval None
richardv	0:b079fa4ed182	2738	*/
richardv	0:b079fa4ed182	2739	void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter)
richardv	0:b079fa4ed182	2740	{ /* Check the parameters */
richardv	0:b079fa4ed182	2741	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	2742	assert_param(IS_TIM_BREAK1_FILTER(TIM_Break1Filter));
richardv	0:b079fa4ed182	2743
richardv	0:b079fa4ed182	2744	/* Reset the BKP and BKF Bits */
richardv	0:b079fa4ed182	2745	TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BKP \| TIM_BDTR_BKF);
richardv	0:b079fa4ed182	2746	/* Configure the Break1 polarity and filter */
richardv	0:b079fa4ed182	2747	TIMx->BDTR \|= TIM_Break1Polarity \|((uint32_t)TIM_Break1Filter << 16);
richardv	0:b079fa4ed182	2748	}
richardv	0:b079fa4ed182	2749
richardv	0:b079fa4ed182	2750	/**
richardv	0:b079fa4ed182	2751	* @brief Configures the Break2 feature.
richardv	0:b079fa4ed182	2752	* @param TIMx: where x can be 1 or 8 to select the TIM
richardv	0:b079fa4ed182	2753	* @param TIM_Break2Polarity: specifies the Break2 polarity.
richardv	0:b079fa4ed182	2754	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	2755	* @arg TIM_Break2Polarity_Low: Break2 input is active low
richardv	0:b079fa4ed182	2756	* @arg TIM_Break2Polarity_High: Break2 input is active high
richardv	0:b079fa4ed182	2757	* @param TIM_Break2Filter: specifies the Break2 filter value.
richardv	0:b079fa4ed182	2758	* This parameter must be a value between 0x00 and 0x0F
richardv	0:b079fa4ed182	2759	* @retval None
richardv	0:b079fa4ed182	2760	*/
richardv	0:b079fa4ed182	2761	void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter)
richardv	0:b079fa4ed182	2762	{
richardv	0:b079fa4ed182	2763	/* Check the parameters */
richardv	0:b079fa4ed182	2764	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	2765	assert_param(IS_TIM_BREAK2_FILTER(TIM_Break2Filter));
richardv	0:b079fa4ed182	2766
richardv	0:b079fa4ed182	2767	/* Reset the BKP and BKF Bits */
richardv	0:b079fa4ed182	2768	TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BK2P \| TIM_BDTR_BK2F);
richardv	0:b079fa4ed182	2769
richardv	0:b079fa4ed182	2770	/* Configure the Break1 polarity and filter */
richardv	0:b079fa4ed182	2771	TIMx->BDTR \|= TIM_Break2Polarity \|((uint32_t)TIM_Break2Filter << 20);
richardv	0:b079fa4ed182	2772	}
richardv	0:b079fa4ed182	2773
richardv	0:b079fa4ed182	2774	/**
richardv	0:b079fa4ed182	2775	* @brief Enables or disables the TIM Break1 input.
richardv	0:b079fa4ed182	2776	* @param TIMx: where x can be 1, 8, 1, 16 or 17 to select the TIMx peripheral.
richardv	0:b079fa4ed182	2777	* @param NewState: new state of the TIM Break1 input.
richardv	0:b079fa4ed182	2778	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	2779	* @retval None
richardv	0:b079fa4ed182	2780	*/
richardv	0:b079fa4ed182	2781	void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	2782	{
richardv	0:b079fa4ed182	2783	/* Check the parameters */
richardv	0:b079fa4ed182	2784	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
richardv	0:b079fa4ed182	2785	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	2786
richardv	0:b079fa4ed182	2787	if (NewState != DISABLE)
richardv	0:b079fa4ed182	2788	{
richardv	0:b079fa4ed182	2789	/* Enable the Break1 */
richardv	0:b079fa4ed182	2790	TIMx->BDTR \|= TIM_BDTR_BKE;
richardv	0:b079fa4ed182	2791	}
richardv	0:b079fa4ed182	2792	else
richardv	0:b079fa4ed182	2793	{
richardv	0:b079fa4ed182	2794	/* Disable the Break1 */
richardv	0:b079fa4ed182	2795	TIMx->BDTR &= (uint32_t)~TIM_BDTR_BKE;
richardv	0:b079fa4ed182	2796	}
richardv	0:b079fa4ed182	2797	}
richardv	0:b079fa4ed182	2798
richardv	0:b079fa4ed182	2799	/**
richardv	0:b079fa4ed182	2800	* @brief Enables or disables the TIM Break2 input.
richardv	0:b079fa4ed182	2801	* @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
richardv	0:b079fa4ed182	2802	* @param NewState: new state of the TIM Break2 input.
richardv	0:b079fa4ed182	2803	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	2804	* @retval None
richardv	0:b079fa4ed182	2805	*/
richardv	0:b079fa4ed182	2806	void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	2807	{
richardv	0:b079fa4ed182	2808	/* Check the parameters */
richardv	0:b079fa4ed182	2809	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	2810	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	2811
richardv	0:b079fa4ed182	2812	if (NewState != DISABLE)
richardv	0:b079fa4ed182	2813	{
richardv	0:b079fa4ed182	2814	/* Enable the Break1 */
richardv	0:b079fa4ed182	2815	TIMx->BDTR \|= TIM_BDTR_BK2E;
richardv	0:b079fa4ed182	2816	}
richardv	0:b079fa4ed182	2817	else
richardv	0:b079fa4ed182	2818	{
richardv	0:b079fa4ed182	2819	/* Disable the Break1 */
richardv	0:b079fa4ed182	2820	TIMx->BDTR &= (uint32_t)~TIM_BDTR_BK2E;
richardv	0:b079fa4ed182	2821	}
richardv	0:b079fa4ed182	2822	}
richardv	0:b079fa4ed182	2823
richardv	0:b079fa4ed182	2824	/**
richardv	0:b079fa4ed182	2825	* @brief Fills each TIM_BDTRInitStruct member with its default value.
richardv	0:b079fa4ed182	2826	* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
richardv	0:b079fa4ed182	2827	* will be initialized.
richardv	0:b079fa4ed182	2828	* @retval None
richardv	0:b079fa4ed182	2829	*/
richardv	0:b079fa4ed182	2830	void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
richardv	0:b079fa4ed182	2831	{
richardv	0:b079fa4ed182	2832	/* Set the default configuration */
richardv	0:b079fa4ed182	2833	TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
richardv	0:b079fa4ed182	2834	TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
richardv	0:b079fa4ed182	2835	TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
richardv	0:b079fa4ed182	2836	TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
richardv	0:b079fa4ed182	2837	TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
richardv	0:b079fa4ed182	2838	TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
richardv	0:b079fa4ed182	2839	TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
richardv	0:b079fa4ed182	2840	}
richardv	0:b079fa4ed182	2841
richardv	0:b079fa4ed182	2842	/**
richardv	0:b079fa4ed182	2843	* @brief Enables or disables the TIM peripheral Main Outputs.
richardv	0:b079fa4ed182	2844	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
richardv	0:b079fa4ed182	2845	* @param NewState: new state of the TIM peripheral Main Outputs.
richardv	0:b079fa4ed182	2846	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	2847	* @retval None
richardv	0:b079fa4ed182	2848	*/
richardv	0:b079fa4ed182	2849	void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	2850	{
richardv	0:b079fa4ed182	2851	/* Check the parameters */
richardv	0:b079fa4ed182	2852	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
richardv	0:b079fa4ed182	2853	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	2854
richardv	0:b079fa4ed182	2855	if (NewState != DISABLE)
richardv	0:b079fa4ed182	2856	{
richardv	0:b079fa4ed182	2857	/* Enable the TIM Main Output */
richardv	0:b079fa4ed182	2858	TIMx->BDTR \|= TIM_BDTR_MOE;
richardv	0:b079fa4ed182	2859	}
richardv	0:b079fa4ed182	2860	else
richardv	0:b079fa4ed182	2861	{
richardv	0:b079fa4ed182	2862	/* Disable the TIM Main Output */
richardv	0:b079fa4ed182	2863	TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
richardv	0:b079fa4ed182	2864	}
richardv	0:b079fa4ed182	2865	}
richardv	0:b079fa4ed182	2866
richardv	0:b079fa4ed182	2867	/**
richardv	0:b079fa4ed182	2868	* @brief Selects the TIM peripheral Commutation event.
richardv	0:b079fa4ed182	2869	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
richardv	0:b079fa4ed182	2870	* @param NewState: new state of the Commutation event.
richardv	0:b079fa4ed182	2871	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	2872	* @retval None
richardv	0:b079fa4ed182	2873	*/
richardv	0:b079fa4ed182	2874	void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	2875	{
richardv	0:b079fa4ed182	2876	/* Check the parameters */
richardv	0:b079fa4ed182	2877	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
richardv	0:b079fa4ed182	2878	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	2879
richardv	0:b079fa4ed182	2880	if (NewState != DISABLE)
richardv	0:b079fa4ed182	2881	{
richardv	0:b079fa4ed182	2882	/* Set the COM Bit */
richardv	0:b079fa4ed182	2883	TIMx->CR2 \|= TIM_CR2_CCUS;
richardv	0:b079fa4ed182	2884	}
richardv	0:b079fa4ed182	2885	else
richardv	0:b079fa4ed182	2886	{
richardv	0:b079fa4ed182	2887	/* Reset the COM Bit */
richardv	0:b079fa4ed182	2888	TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
richardv	0:b079fa4ed182	2889	}
richardv	0:b079fa4ed182	2890	}
richardv	0:b079fa4ed182	2891
richardv	0:b079fa4ed182	2892	/**
richardv	0:b079fa4ed182	2893	* @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
richardv	0:b079fa4ed182	2894	* @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
richardv	0:b079fa4ed182	2895	* @param NewState: new state of the Capture Compare Preload Control bit
richardv	0:b079fa4ed182	2896	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	2897	* @retval None
richardv	0:b079fa4ed182	2898	*/
richardv	0:b079fa4ed182	2899	void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	2900	{
richardv	0:b079fa4ed182	2901	/* Check the parameters */
richardv	0:b079fa4ed182	2902	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
richardv	0:b079fa4ed182	2903	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	2904	if (NewState != DISABLE)
richardv	0:b079fa4ed182	2905	{
richardv	0:b079fa4ed182	2906	/* Set the CCPC Bit */
richardv	0:b079fa4ed182	2907	TIMx->CR2 \|= TIM_CR2_CCPC;
richardv	0:b079fa4ed182	2908	}
richardv	0:b079fa4ed182	2909	else
richardv	0:b079fa4ed182	2910	{
richardv	0:b079fa4ed182	2911	/* Reset the CCPC Bit */
richardv	0:b079fa4ed182	2912	TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
richardv	0:b079fa4ed182	2913	}
richardv	0:b079fa4ed182	2914	}
richardv	0:b079fa4ed182	2915	/**
richardv	0:b079fa4ed182	2916	* @}
richardv	0:b079fa4ed182	2917	*/
richardv	0:b079fa4ed182	2918
richardv	0:b079fa4ed182	2919	/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
richardv	0:b079fa4ed182	2920	* @brief Interrupts, DMA and flags management functions
richardv	0:b079fa4ed182	2921	*
richardv	0:b079fa4ed182	2922	@verbatim
richardv	0:b079fa4ed182	2923	===============================================================================
richardv	0:b079fa4ed182	2924	##### Interrupts, DMA and flags management functions #####
richardv	0:b079fa4ed182	2925	===============================================================================
richardv	0:b079fa4ed182	2926
richardv	0:b079fa4ed182	2927	@endverbatim
richardv	0:b079fa4ed182	2928	* @{
richardv	0:b079fa4ed182	2929	*/
richardv	0:b079fa4ed182	2930
richardv	0:b079fa4ed182	2931	/**
richardv	0:b079fa4ed182	2932	* @brief Enables or disables the specified TIM interrupts.
richardv	0:b079fa4ed182	2933	* @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIMx peripheral.
richardv	0:b079fa4ed182	2934	* @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
richardv	0:b079fa4ed182	2935	* This parameter can be any combination of the following values:
richardv	0:b079fa4ed182	2936	* @arg TIM_IT_Update: TIM update Interrupt source
richardv	0:b079fa4ed182	2937	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
richardv	0:b079fa4ed182	2938	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
richardv	0:b079fa4ed182	2939	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
richardv	0:b079fa4ed182	2940	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
richardv	0:b079fa4ed182	2941	* @arg TIM_IT_COM: TIM Commutation Interrupt source
richardv	0:b079fa4ed182	2942	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
richardv	0:b079fa4ed182	2943	* @arg TIM_IT_Break: TIM Break Interrupt source
richardv	0:b079fa4ed182	2944	*
richardv	0:b079fa4ed182	2945	* @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
richardv	0:b079fa4ed182	2946	* @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
richardv	0:b079fa4ed182	2947	* TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
richardv	0:b079fa4ed182	2948	* @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
richardv	0:b079fa4ed182	2949	* be used: TIM_IT_Update or TIM_IT_CC1
richardv	0:b079fa4ed182	2950	* @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
richardv	0:b079fa4ed182	2951	*
richardv	0:b079fa4ed182	2952	* @param NewState: new state of the TIM interrupts.
richardv	0:b079fa4ed182	2953	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	2954	* @retval None
richardv	0:b079fa4ed182	2955	*/
richardv	0:b079fa4ed182	2956	void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
richardv	0:b079fa4ed182	2957	{
richardv	0:b079fa4ed182	2958	/* Check the parameters */
richardv	0:b079fa4ed182	2959	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	2960	assert_param(IS_TIM_IT(TIM_IT));
richardv	0:b079fa4ed182	2961	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	2962
richardv	0:b079fa4ed182	2963	if (NewState != DISABLE)
richardv	0:b079fa4ed182	2964	{
richardv	0:b079fa4ed182	2965	/* Enable the Interrupt sources */
richardv	0:b079fa4ed182	2966	TIMx->DIER \|= TIM_IT;
richardv	0:b079fa4ed182	2967	}
richardv	0:b079fa4ed182	2968	else
richardv	0:b079fa4ed182	2969	{
richardv	0:b079fa4ed182	2970	/* Disable the Interrupt sources */
richardv	0:b079fa4ed182	2971	TIMx->DIER &= (uint16_t)~TIM_IT;
richardv	0:b079fa4ed182	2972	}
richardv	0:b079fa4ed182	2973	}
richardv	0:b079fa4ed182	2974
richardv	0:b079fa4ed182	2975	/**
richardv	0:b079fa4ed182	2976	* @brief Configures the TIMx event to be generate by software.
richardv	0:b079fa4ed182	2977	* @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	2978	* @param TIM_EventSource: specifies the event source.
richardv	0:b079fa4ed182	2979	* This parameter can be one or more of the following values:
richardv	0:b079fa4ed182	2980	* @arg TIM_EventSource_Update: Timer update Event source
richardv	0:b079fa4ed182	2981	* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
richardv	0:b079fa4ed182	2982	* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
richardv	0:b079fa4ed182	2983	* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
richardv	0:b079fa4ed182	2984	* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
richardv	0:b079fa4ed182	2985	* @arg TIM_EventSource_COM: Timer COM event source
richardv	0:b079fa4ed182	2986	* @arg TIM_EventSource_Trigger: Timer Trigger Event source
richardv	0:b079fa4ed182	2987	* @arg TIM_EventSource_Break: Timer Break event source
richardv	0:b079fa4ed182	2988	*
richardv	0:b079fa4ed182	2989	* @note TIM6 and TIM7 can only generate an update event.
richardv	0:b079fa4ed182	2990	* @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
richardv	0:b079fa4ed182	2991	*
richardv	0:b079fa4ed182	2992	* @retval None
richardv	0:b079fa4ed182	2993	*/
richardv	0:b079fa4ed182	2994	void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
richardv	0:b079fa4ed182	2995	{
richardv	0:b079fa4ed182	2996	/* Check the parameters */
richardv	0:b079fa4ed182	2997	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	2998	assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
richardv	0:b079fa4ed182	2999
richardv	0:b079fa4ed182	3000	/* Set the event sources */
richardv	0:b079fa4ed182	3001	TIMx->EGR = TIM_EventSource;
richardv	0:b079fa4ed182	3002	}
richardv	0:b079fa4ed182	3003
richardv	0:b079fa4ed182	3004	/**
richardv	0:b079fa4ed182	3005	* @brief Checks whether the specified TIM flag is set or not.
richardv	0:b079fa4ed182	3006	* @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	3007	* @param TIM_FLAG: specifies the flag to check.
richardv	0:b079fa4ed182	3008	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3009	* @arg TIM_FLAG_Update: TIM update Flag
richardv	0:b079fa4ed182	3010	* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
richardv	0:b079fa4ed182	3011	* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
richardv	0:b079fa4ed182	3012	* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
richardv	0:b079fa4ed182	3013	* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
richardv	0:b079fa4ed182	3014	* @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
richardv	0:b079fa4ed182	3015	* @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag
richardv	0:b079fa4ed182	3016	* @arg TIM_FLAG_COM: TIM Commutation Flag
richardv	0:b079fa4ed182	3017	* @arg TIM_FLAG_Trigger: TIM Trigger Flag
richardv	0:b079fa4ed182	3018	* @arg TIM_FLAG_Break: TIM Break Flag
richardv	0:b079fa4ed182	3019	* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
richardv	0:b079fa4ed182	3020	* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
richardv	0:b079fa4ed182	3021	* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
richardv	0:b079fa4ed182	3022	* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
richardv	0:b079fa4ed182	3023	*
richardv	0:b079fa4ed182	3024	* @note TIM6 and TIM7 can have only one update flag.
richardv	0:b079fa4ed182	3025	* @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
richardv	0:b079fa4ed182	3026	*
richardv	0:b079fa4ed182	3027	* @retval The new state of TIM_FLAG (SET or RESET).
richardv	0:b079fa4ed182	3028	*/
richardv	0:b079fa4ed182	3029	FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG)
richardv	0:b079fa4ed182	3030	{
richardv	0:b079fa4ed182	3031	ITStatus bitstatus = RESET;
richardv	0:b079fa4ed182	3032	/* Check the parameters */
richardv	0:b079fa4ed182	3033	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	3034	assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
richardv	0:b079fa4ed182	3035
richardv	0:b079fa4ed182	3036
richardv	0:b079fa4ed182	3037	if ((TIMx->SR & TIM_FLAG) != RESET)
richardv	0:b079fa4ed182	3038	{
richardv	0:b079fa4ed182	3039	bitstatus = SET;
richardv	0:b079fa4ed182	3040	}
richardv	0:b079fa4ed182	3041	else
richardv	0:b079fa4ed182	3042	{
richardv	0:b079fa4ed182	3043	bitstatus = RESET;
richardv	0:b079fa4ed182	3044	}
richardv	0:b079fa4ed182	3045	return bitstatus;
richardv	0:b079fa4ed182	3046	}
richardv	0:b079fa4ed182	3047
richardv	0:b079fa4ed182	3048	/**
richardv	0:b079fa4ed182	3049	* @brief Clears the TIMx's pending flags.
richardv	0:b079fa4ed182	3050	* @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	3051	* @param TIM_FLAG: specifies the flag bit to clear.
richardv	0:b079fa4ed182	3052	* This parameter can be any combination of the following values:
richardv	0:b079fa4ed182	3053	* @arg TIM_FLAG_Update: TIM update Flag
richardv	0:b079fa4ed182	3054	* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
richardv	0:b079fa4ed182	3055	* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
richardv	0:b079fa4ed182	3056	* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
richardv	0:b079fa4ed182	3057	* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
richardv	0:b079fa4ed182	3058	* @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
richardv	0:b079fa4ed182	3059	* @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag
richardv	0:b079fa4ed182	3060	* @arg TIM_FLAG_COM: TIM Commutation Flag
richardv	0:b079fa4ed182	3061	* @arg TIM_FLAG_Trigger: TIM Trigger Flag
richardv	0:b079fa4ed182	3062	* @arg TIM_FLAG_Break: TIM Break Flag
richardv	0:b079fa4ed182	3063	* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
richardv	0:b079fa4ed182	3064	* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
richardv	0:b079fa4ed182	3065	* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
richardv	0:b079fa4ed182	3066	* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
richardv	0:b079fa4ed182	3067	*
richardv	0:b079fa4ed182	3068	* @note TIM6 and TIM7 can have only one update flag.
richardv	0:b079fa4ed182	3069	* @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
richardv	0:b079fa4ed182	3070	*
richardv	0:b079fa4ed182	3071	* @retval None
richardv	0:b079fa4ed182	3072	*/
richardv	0:b079fa4ed182	3073	void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
richardv	0:b079fa4ed182	3074	{
richardv	0:b079fa4ed182	3075	/* Check the parameters */
richardv	0:b079fa4ed182	3076	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	3077
richardv	0:b079fa4ed182	3078	/* Clear the flags */
richardv	0:b079fa4ed182	3079	TIMx->SR = (uint16_t)~TIM_FLAG;
richardv	0:b079fa4ed182	3080	}
richardv	0:b079fa4ed182	3081
richardv	0:b079fa4ed182	3082	/**
richardv	0:b079fa4ed182	3083	* @brief Checks whether the TIM interrupt has occurred or not.
richardv	0:b079fa4ed182	3084	* @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	3085	* @param TIM_IT: specifies the TIM interrupt source to check.
richardv	0:b079fa4ed182	3086	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3087	* @arg TIM_IT_Update: TIM update Interrupt source
richardv	0:b079fa4ed182	3088	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
richardv	0:b079fa4ed182	3089	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
richardv	0:b079fa4ed182	3090	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
richardv	0:b079fa4ed182	3091	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
richardv	0:b079fa4ed182	3092	* @arg TIM_IT_COM: TIM Commutation Interrupt source
richardv	0:b079fa4ed182	3093	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
richardv	0:b079fa4ed182	3094	* @arg TIM_IT_Break: TIM Break Interrupt source
richardv	0:b079fa4ed182	3095	*
richardv	0:b079fa4ed182	3096	* @note TIM6 and TIM7 can generate only an update interrupt.
richardv	0:b079fa4ed182	3097	* @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
richardv	0:b079fa4ed182	3098	*
richardv	0:b079fa4ed182	3099	* @retval The new state of the TIM_IT(SET or RESET).
richardv	0:b079fa4ed182	3100	*/
richardv	0:b079fa4ed182	3101	ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
richardv	0:b079fa4ed182	3102	{
richardv	0:b079fa4ed182	3103	ITStatus bitstatus = RESET;
richardv	0:b079fa4ed182	3104	uint16_t itstatus = 0x0, itenable = 0x0;
richardv	0:b079fa4ed182	3105	/* Check the parameters */
richardv	0:b079fa4ed182	3106	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	3107	assert_param(IS_TIM_GET_IT(TIM_IT));
richardv	0:b079fa4ed182	3108
richardv	0:b079fa4ed182	3109	itstatus = TIMx->SR & TIM_IT;
richardv	0:b079fa4ed182	3110
richardv	0:b079fa4ed182	3111	itenable = TIMx->DIER & TIM_IT;
richardv	0:b079fa4ed182	3112	if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
richardv	0:b079fa4ed182	3113	{
richardv	0:b079fa4ed182	3114	bitstatus = SET;
richardv	0:b079fa4ed182	3115	}
richardv	0:b079fa4ed182	3116	else
richardv	0:b079fa4ed182	3117	{
richardv	0:b079fa4ed182	3118	bitstatus = RESET;
richardv	0:b079fa4ed182	3119	}
richardv	0:b079fa4ed182	3120	return bitstatus;
richardv	0:b079fa4ed182	3121	}
richardv	0:b079fa4ed182	3122
richardv	0:b079fa4ed182	3123	/**
richardv	0:b079fa4ed182	3124	* @brief Clears the TIMx's interrupt pending bits.
richardv	0:b079fa4ed182	3125	* @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	3126	* @param TIM_IT: specifies the pending bit to clear.
richardv	0:b079fa4ed182	3127	* This parameter can be any combination of the following values:
richardv	0:b079fa4ed182	3128	* @arg TIM_IT_Update: TIM1 update Interrupt source
richardv	0:b079fa4ed182	3129	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
richardv	0:b079fa4ed182	3130	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
richardv	0:b079fa4ed182	3131	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
richardv	0:b079fa4ed182	3132	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
richardv	0:b079fa4ed182	3133	* @arg TIM_IT_COM: TIM Commutation Interrupt source
richardv	0:b079fa4ed182	3134	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
richardv	0:b079fa4ed182	3135	* @arg TIM_IT_Break: TIM Break Interrupt source
richardv	0:b079fa4ed182	3136	*
richardv	0:b079fa4ed182	3137	* @note TIM6 and TIM7 can generate only an update interrupt.
richardv	0:b079fa4ed182	3138	* @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
richardv	0:b079fa4ed182	3139	*
richardv	0:b079fa4ed182	3140	* @retval None
richardv	0:b079fa4ed182	3141	*/
richardv	0:b079fa4ed182	3142	void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
richardv	0:b079fa4ed182	3143	{
richardv	0:b079fa4ed182	3144	/* Check the parameters */
richardv	0:b079fa4ed182	3145	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	3146
richardv	0:b079fa4ed182	3147	/* Clear the IT pending Bit */
richardv	0:b079fa4ed182	3148	TIMx->SR = (uint16_t)~TIM_IT;
richardv	0:b079fa4ed182	3149	}
richardv	0:b079fa4ed182	3150
richardv	0:b079fa4ed182	3151	/**
richardv	0:b079fa4ed182	3152	* @brief Configures the TIMx's DMA interface.
richardv	0:b079fa4ed182	3153	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	3154	* @param TIM_DMABase: DMA Base address.
richardv	0:b079fa4ed182	3155	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3156	* @arg TIM_DMABase_CR1
richardv	0:b079fa4ed182	3157	* @arg TIM_DMABase_CR2
richardv	0:b079fa4ed182	3158	* @arg TIM_DMABase_SMCR
richardv	0:b079fa4ed182	3159	* @arg TIM_DMABase_DIER
richardv	0:b079fa4ed182	3160	* @arg TIM1_DMABase_SR
richardv	0:b079fa4ed182	3161	* @arg TIM_DMABase_EGR
richardv	0:b079fa4ed182	3162	* @arg TIM_DMABase_CCMR1
richardv	0:b079fa4ed182	3163	* @arg TIM_DMABase_CCMR2
richardv	0:b079fa4ed182	3164	* @arg TIM_DMABase_CCER
richardv	0:b079fa4ed182	3165	* @arg TIM_DMABase_CNT
richardv	0:b079fa4ed182	3166	* @arg TIM_DMABase_PSC
richardv	0:b079fa4ed182	3167	* @arg TIM_DMABase_ARR
richardv	0:b079fa4ed182	3168	* @arg TIM_DMABase_RCR
richardv	0:b079fa4ed182	3169	* @arg TIM_DMABase_CCR1
richardv	0:b079fa4ed182	3170	* @arg TIM_DMABase_CCR2
richardv	0:b079fa4ed182	3171	* @arg TIM_DMABase_CCR3
richardv	0:b079fa4ed182	3172	* @arg TIM_DMABase_CCR4
richardv	0:b079fa4ed182	3173	* @arg TIM_DMABase_BDTR
richardv	0:b079fa4ed182	3174	* @arg TIM_DMABase_DCR
richardv	0:b079fa4ed182	3175	* @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
richardv	0:b079fa4ed182	3176	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
richardv	0:b079fa4ed182	3177	* @retval None
richardv	0:b079fa4ed182	3178	*/
richardv	0:b079fa4ed182	3179	void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
richardv	0:b079fa4ed182	3180	{
richardv	0:b079fa4ed182	3181	/* Check the parameters */
richardv	0:b079fa4ed182	3182	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	3183	assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
richardv	0:b079fa4ed182	3184	assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
richardv	0:b079fa4ed182	3185
richardv	0:b079fa4ed182	3186	/* Set the DMA Base and the DMA Burst Length */
richardv	0:b079fa4ed182	3187	TIMx->DCR = TIM_DMABase \| TIM_DMABurstLength;
richardv	0:b079fa4ed182	3188	}
richardv	0:b079fa4ed182	3189
richardv	0:b079fa4ed182	3190	/**
richardv	0:b079fa4ed182	3191	* @brief Enables or disables the TIMx's DMA Requests.
richardv	0:b079fa4ed182	3192	* @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	3193	* @param TIM_DMASource: specifies the DMA Request sources.
richardv	0:b079fa4ed182	3194	* This parameter can be any combination of the following values:
richardv	0:b079fa4ed182	3195	* @arg TIM_DMA_Update: TIM update Interrupt source
richardv	0:b079fa4ed182	3196	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
richardv	0:b079fa4ed182	3197	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
richardv	0:b079fa4ed182	3198	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
richardv	0:b079fa4ed182	3199	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
richardv	0:b079fa4ed182	3200	* @arg TIM_DMA_COM: TIM Commutation DMA source
richardv	0:b079fa4ed182	3201	* @arg TIM_DMA_Trigger: TIM Trigger DMA source
richardv	0:b079fa4ed182	3202	* @param NewState: new state of the DMA Request sources.
richardv	0:b079fa4ed182	3203	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	3204	* @retval None
richardv	0:b079fa4ed182	3205	*/
richardv	0:b079fa4ed182	3206	void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
richardv	0:b079fa4ed182	3207	{
richardv	0:b079fa4ed182	3208	/* Check the parameters */
richardv	0:b079fa4ed182	3209	assert_param(IS_TIM_ALL_PERIPH(TIMx));
richardv	0:b079fa4ed182	3210	assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
richardv	0:b079fa4ed182	3211	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	3212
richardv	0:b079fa4ed182	3213	if (NewState != DISABLE)
richardv	0:b079fa4ed182	3214	{
richardv	0:b079fa4ed182	3215	/* Enable the DMA sources */
richardv	0:b079fa4ed182	3216	TIMx->DIER \|= TIM_DMASource;
richardv	0:b079fa4ed182	3217	}
richardv	0:b079fa4ed182	3218	else
richardv	0:b079fa4ed182	3219	{
richardv	0:b079fa4ed182	3220	/* Disable the DMA sources */
richardv	0:b079fa4ed182	3221	TIMx->DIER &= (uint16_t)~TIM_DMASource;
richardv	0:b079fa4ed182	3222	}
richardv	0:b079fa4ed182	3223	}
richardv	0:b079fa4ed182	3224
richardv	0:b079fa4ed182	3225	/**
richardv	0:b079fa4ed182	3226	* @brief Selects the TIMx peripheral Capture Compare DMA source.
richardv	0:b079fa4ed182	3227	* @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
richardv	0:b079fa4ed182	3228	* @param NewState: new state of the Capture Compare DMA source
richardv	0:b079fa4ed182	3229	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	3230	* @retval None
richardv	0:b079fa4ed182	3231	*/
richardv	0:b079fa4ed182	3232	void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	3233	{
richardv	0:b079fa4ed182	3234	/* Check the parameters */
richardv	0:b079fa4ed182	3235	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
richardv	0:b079fa4ed182	3236	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	3237
richardv	0:b079fa4ed182	3238	if (NewState != DISABLE)
richardv	0:b079fa4ed182	3239	{
richardv	0:b079fa4ed182	3240	/* Set the CCDS Bit */
richardv	0:b079fa4ed182	3241	TIMx->CR2 \|= TIM_CR2_CCDS;
richardv	0:b079fa4ed182	3242	}
richardv	0:b079fa4ed182	3243	else
richardv	0:b079fa4ed182	3244	{
richardv	0:b079fa4ed182	3245	/* Reset the CCDS Bit */
richardv	0:b079fa4ed182	3246	TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
richardv	0:b079fa4ed182	3247	}
richardv	0:b079fa4ed182	3248	}
richardv	0:b079fa4ed182	3249	/**
richardv	0:b079fa4ed182	3250	* @}
richardv	0:b079fa4ed182	3251	*/
richardv	0:b079fa4ed182	3252
richardv	0:b079fa4ed182	3253	/** @defgroup TIM_Group6 Clocks management functions
richardv	0:b079fa4ed182	3254	* @brief Clocks management functions
richardv	0:b079fa4ed182	3255	*
richardv	0:b079fa4ed182	3256	@verbatim
richardv	0:b079fa4ed182	3257	===============================================================================
richardv	0:b079fa4ed182	3258	##### Clocks management functions #####
richardv	0:b079fa4ed182	3259	===============================================================================
richardv	0:b079fa4ed182	3260
richardv	0:b079fa4ed182	3261	@endverbatim
richardv	0:b079fa4ed182	3262	* @{
richardv	0:b079fa4ed182	3263	*/
richardv	0:b079fa4ed182	3264
richardv	0:b079fa4ed182	3265	/**
richardv	0:b079fa4ed182	3266	* @brief Configures the TIMx internal Clock
richardv	0:b079fa4ed182	3267	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
richardv	0:b079fa4ed182	3268	* peripheral.
richardv	0:b079fa4ed182	3269	* @retval None
richardv	0:b079fa4ed182	3270	*/
richardv	0:b079fa4ed182	3271	void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
richardv	0:b079fa4ed182	3272	{
richardv	0:b079fa4ed182	3273	/* Check the parameters */
richardv	0:b079fa4ed182	3274	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	3275
richardv	0:b079fa4ed182	3276	/* Disable slave mode to clock the prescaler directly with the internal clock */
richardv	0:b079fa4ed182	3277	TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
richardv	0:b079fa4ed182	3278	}
richardv	0:b079fa4ed182	3279
richardv	0:b079fa4ed182	3280	/**
richardv	0:b079fa4ed182	3281	* @brief Configures the TIMx Internal Trigger as External Clock
richardv	0:b079fa4ed182	3282	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
richardv	0:b079fa4ed182	3283	* peripheral.
richardv	0:b079fa4ed182	3284	* @param TIM_InputTriggerSource: Trigger source.
richardv	0:b079fa4ed182	3285	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3286	* @arg TIM_TS_ITR0: Internal Trigger 0
richardv	0:b079fa4ed182	3287	* @arg TIM_TS_ITR1: Internal Trigger 1
richardv	0:b079fa4ed182	3288	* @arg TIM_TS_ITR2: Internal Trigger 2
richardv	0:b079fa4ed182	3289	* @arg TIM_TS_ITR3: Internal Trigger 3
richardv	0:b079fa4ed182	3290	* @retval None
richardv	0:b079fa4ed182	3291	*/
richardv	0:b079fa4ed182	3292	void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
richardv	0:b079fa4ed182	3293	{
richardv	0:b079fa4ed182	3294	/* Check the parameters */
richardv	0:b079fa4ed182	3295	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	3296	assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
richardv	0:b079fa4ed182	3297
richardv	0:b079fa4ed182	3298	/* Select the Internal Trigger */
richardv	0:b079fa4ed182	3299	TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
richardv	0:b079fa4ed182	3300
richardv	0:b079fa4ed182	3301	/* Select the External clock mode1 */
richardv	0:b079fa4ed182	3302	TIMx->SMCR \|= TIM_SlaveMode_External1;
richardv	0:b079fa4ed182	3303	}
richardv	0:b079fa4ed182	3304
richardv	0:b079fa4ed182	3305	/**
richardv	0:b079fa4ed182	3306	* @brief Configures the TIMx Trigger as External Clock
richardv	0:b079fa4ed182	3307	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15
richardv	0:b079fa4ed182	3308	* to select the TIM peripheral.
richardv	0:b079fa4ed182	3309	* @param TIM_TIxExternalCLKSource: Trigger source.
richardv	0:b079fa4ed182	3310	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3311	* @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
richardv	0:b079fa4ed182	3312	* @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
richardv	0:b079fa4ed182	3313	* @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
richardv	0:b079fa4ed182	3314	* @param TIM_ICPolarity: specifies the TIx Polarity.
richardv	0:b079fa4ed182	3315	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3316	* @arg TIM_ICPolarity_Rising
richardv	0:b079fa4ed182	3317	* @arg TIM_ICPolarity_Falling
richardv	0:b079fa4ed182	3318	* @param ICFilter: specifies the filter value.
richardv	0:b079fa4ed182	3319	* This parameter must be a value between 0x0 and 0xF.
richardv	0:b079fa4ed182	3320	* @retval None
richardv	0:b079fa4ed182	3321	*/
richardv	0:b079fa4ed182	3322	void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
richardv	0:b079fa4ed182	3323	uint16_t TIM_ICPolarity, uint16_t ICFilter)
richardv	0:b079fa4ed182	3324	{
richardv	0:b079fa4ed182	3325	/* Check the parameters */
richardv	0:b079fa4ed182	3326	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	3327	assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
richardv	0:b079fa4ed182	3328	assert_param(IS_TIM_IC_FILTER(ICFilter));
richardv	0:b079fa4ed182	3329
richardv	0:b079fa4ed182	3330	/* Configure the Timer Input Clock Source */
richardv	0:b079fa4ed182	3331	if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
richardv	0:b079fa4ed182	3332	{
richardv	0:b079fa4ed182	3333	TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
richardv	0:b079fa4ed182	3334	}
richardv	0:b079fa4ed182	3335	else
richardv	0:b079fa4ed182	3336	{
richardv	0:b079fa4ed182	3337	TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
richardv	0:b079fa4ed182	3338	}
richardv	0:b079fa4ed182	3339	/* Select the Trigger source */
richardv	0:b079fa4ed182	3340	TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
richardv	0:b079fa4ed182	3341	/* Select the External clock mode1 */
richardv	0:b079fa4ed182	3342	TIMx->SMCR \|= TIM_SlaveMode_External1;
richardv	0:b079fa4ed182	3343	}
richardv	0:b079fa4ed182	3344
richardv	0:b079fa4ed182	3345	/**
richardv	0:b079fa4ed182	3346	* @brief Configures the External clock Mode1
richardv	0:b079fa4ed182	3347	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	3348	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
richardv	0:b079fa4ed182	3349	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3350	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
richardv	0:b079fa4ed182	3351	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
richardv	0:b079fa4ed182	3352	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
richardv	0:b079fa4ed182	3353	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
richardv	0:b079fa4ed182	3354	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
richardv	0:b079fa4ed182	3355	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3356	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
richardv	0:b079fa4ed182	3357	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
richardv	0:b079fa4ed182	3358	* @param ExtTRGFilter: External Trigger Filter.
richardv	0:b079fa4ed182	3359	* This parameter must be a value between 0x00 and 0x0F
richardv	0:b079fa4ed182	3360	* @retval None
richardv	0:b079fa4ed182	3361	*/
richardv	0:b079fa4ed182	3362	void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
richardv	0:b079fa4ed182	3363	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
richardv	0:b079fa4ed182	3364	{
richardv	0:b079fa4ed182	3365	uint16_t tmpsmcr = 0;
richardv	0:b079fa4ed182	3366
richardv	0:b079fa4ed182	3367	/* Check the parameters */
richardv	0:b079fa4ed182	3368	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	3369	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
richardv	0:b079fa4ed182	3370	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
richardv	0:b079fa4ed182	3371	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
richardv	0:b079fa4ed182	3372	/* Configure the ETR Clock source */
richardv	0:b079fa4ed182	3373	TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
richardv	0:b079fa4ed182	3374
richardv	0:b079fa4ed182	3375	/* Get the TIMx SMCR register value */
richardv	0:b079fa4ed182	3376	tmpsmcr = TIMx->SMCR;
richardv	0:b079fa4ed182	3377
richardv	0:b079fa4ed182	3378	/* Reset the SMS Bits */
richardv	0:b079fa4ed182	3379	tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
richardv	0:b079fa4ed182	3380
richardv	0:b079fa4ed182	3381	/* Select the External clock mode1 */
richardv	0:b079fa4ed182	3382	tmpsmcr \|= TIM_SlaveMode_External1;
richardv	0:b079fa4ed182	3383
richardv	0:b079fa4ed182	3384	/* Select the Trigger selection : ETRF */
richardv	0:b079fa4ed182	3385	tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
richardv	0:b079fa4ed182	3386	tmpsmcr \|= TIM_TS_ETRF;
richardv	0:b079fa4ed182	3387
richardv	0:b079fa4ed182	3388	/* Write to TIMx SMCR */
richardv	0:b079fa4ed182	3389	TIMx->SMCR = tmpsmcr;
richardv	0:b079fa4ed182	3390	}
richardv	0:b079fa4ed182	3391
richardv	0:b079fa4ed182	3392	/**
richardv	0:b079fa4ed182	3393	* @brief Configures the External clock Mode2
richardv	0:b079fa4ed182	3394	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	3395	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
richardv	0:b079fa4ed182	3396	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3397	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
richardv	0:b079fa4ed182	3398	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
richardv	0:b079fa4ed182	3399	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
richardv	0:b079fa4ed182	3400	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
richardv	0:b079fa4ed182	3401	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
richardv	0:b079fa4ed182	3402	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3403	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
richardv	0:b079fa4ed182	3404	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
richardv	0:b079fa4ed182	3405	* @param ExtTRGFilter: External Trigger Filter.
richardv	0:b079fa4ed182	3406	* This parameter must be a value between 0x00 and 0x0F
richardv	0:b079fa4ed182	3407	* @retval None
richardv	0:b079fa4ed182	3408	*/
richardv	0:b079fa4ed182	3409	void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
richardv	0:b079fa4ed182	3410	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
richardv	0:b079fa4ed182	3411	{
richardv	0:b079fa4ed182	3412	/* Check the parameters */
richardv	0:b079fa4ed182	3413	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	3414	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
richardv	0:b079fa4ed182	3415	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
richardv	0:b079fa4ed182	3416	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
richardv	0:b079fa4ed182	3417
richardv	0:b079fa4ed182	3418	/* Configure the ETR Clock source */
richardv	0:b079fa4ed182	3419	TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
richardv	0:b079fa4ed182	3420
richardv	0:b079fa4ed182	3421	/* Enable the External clock mode2 */
richardv	0:b079fa4ed182	3422	TIMx->SMCR \|= TIM_SMCR_ECE;
richardv	0:b079fa4ed182	3423	}
richardv	0:b079fa4ed182	3424	/**
richardv	0:b079fa4ed182	3425	* @}
richardv	0:b079fa4ed182	3426	*/
richardv	0:b079fa4ed182	3427
richardv	0:b079fa4ed182	3428	/** @defgroup TIM_Group7 Synchronization management functions
richardv	0:b079fa4ed182	3429	* @brief Synchronization management functions
richardv	0:b079fa4ed182	3430	*
richardv	0:b079fa4ed182	3431	@verbatim
richardv	0:b079fa4ed182	3432	===============================================================================
richardv	0:b079fa4ed182	3433	##### Synchronization management functions #####
richardv	0:b079fa4ed182	3434	===============================================================================
richardv	0:b079fa4ed182	3435
richardv	0:b079fa4ed182	3436	* TIM Driver: how to use it in synchronization Mode *
richardv	0:b079fa4ed182	3437	=========================================================
richardv	0:b079fa4ed182	3438	[..] Case of two/several Timers
richardv	0:b079fa4ed182	3439
richardv	0:b079fa4ed182	3440	(#) Configure the Master Timers using the following functions:
richardv	0:b079fa4ed182	3441	(++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
richardv	0:b079fa4ed182	3442	(++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
richardv	0:b079fa4ed182	3443	(#) Configure the Slave Timers using the following functions:
richardv	0:b079fa4ed182	3444	(++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
richardv	0:b079fa4ed182	3445	(++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
richardv	0:b079fa4ed182	3446
richardv	0:b079fa4ed182	3447	[..] Case of Timers and external trigger(ETR pin)
richardv	0:b079fa4ed182	3448
richardv	0:b079fa4ed182	3449	(#) Configure the External trigger using this function:
richardv	0:b079fa4ed182	3450	(++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
richardv	0:b079fa4ed182	3451	uint16_t ExtTRGFilter);
richardv	0:b079fa4ed182	3452	(#) Configure the Slave Timers using the following functions:
richardv	0:b079fa4ed182	3453	(++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
richardv	0:b079fa4ed182	3454	(++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
richardv	0:b079fa4ed182	3455
richardv	0:b079fa4ed182	3456	@endverbatim
richardv	0:b079fa4ed182	3457	* @{
richardv	0:b079fa4ed182	3458	*/
richardv	0:b079fa4ed182	3459
richardv	0:b079fa4ed182	3460	/**
richardv	0:b079fa4ed182	3461	* @brief Selects the Input Trigger source
richardv	0:b079fa4ed182	3462	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15
richardv	0:b079fa4ed182	3463	* to select the TIM peripheral.
richardv	0:b079fa4ed182	3464	* @param TIM_InputTriggerSource: The Input Trigger source.
richardv	0:b079fa4ed182	3465	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3466	* @arg TIM_TS_ITR0: Internal Trigger 0
richardv	0:b079fa4ed182	3467	* @arg TIM_TS_ITR1: Internal Trigger 1
richardv	0:b079fa4ed182	3468	* @arg TIM_TS_ITR2: Internal Trigger 2
richardv	0:b079fa4ed182	3469	* @arg TIM_TS_ITR3: Internal Trigger 3
richardv	0:b079fa4ed182	3470	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
richardv	0:b079fa4ed182	3471	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
richardv	0:b079fa4ed182	3472	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
richardv	0:b079fa4ed182	3473	* @arg TIM_TS_ETRF: External Trigger input
richardv	0:b079fa4ed182	3474	* @retval None
richardv	0:b079fa4ed182	3475	*/
richardv	0:b079fa4ed182	3476	void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
richardv	0:b079fa4ed182	3477	{
richardv	0:b079fa4ed182	3478	uint16_t tmpsmcr = 0;
richardv	0:b079fa4ed182	3479
richardv	0:b079fa4ed182	3480	/* Check the parameters */
richardv	0:b079fa4ed182	3481	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	3482	assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
richardv	0:b079fa4ed182	3483
richardv	0:b079fa4ed182	3484	/* Get the TIMx SMCR register value */
richardv	0:b079fa4ed182	3485	tmpsmcr = TIMx->SMCR;
richardv	0:b079fa4ed182	3486
richardv	0:b079fa4ed182	3487	/* Reset the TS Bits */
richardv	0:b079fa4ed182	3488	tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
richardv	0:b079fa4ed182	3489
richardv	0:b079fa4ed182	3490	/* Set the Input Trigger source */
richardv	0:b079fa4ed182	3491	tmpsmcr \|= TIM_InputTriggerSource;
richardv	0:b079fa4ed182	3492
richardv	0:b079fa4ed182	3493	/* Write to TIMx SMCR */
richardv	0:b079fa4ed182	3494	TIMx->SMCR = tmpsmcr;
richardv	0:b079fa4ed182	3495	}
richardv	0:b079fa4ed182	3496
richardv	0:b079fa4ed182	3497	/**
richardv	0:b079fa4ed182	3498	* @brief Selects the TIMx Trigger Output Mode.
richardv	0:b079fa4ed182	3499	* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8 or 15 to select the TIM peripheral.
richardv	0:b079fa4ed182	3500	*
richardv	0:b079fa4ed182	3501	* @param TIM_TRGOSource: specifies the Trigger Output source.
richardv	0:b079fa4ed182	3502	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3503	*
richardv	0:b079fa4ed182	3504	* - For all TIMx
richardv	0:b079fa4ed182	3505	* @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
richardv	0:b079fa4ed182	3506	* @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
richardv	0:b079fa4ed182	3507	* @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
richardv	0:b079fa4ed182	3508	*
richardv	0:b079fa4ed182	3509	* - For all TIMx except TIM6 and TIM7
richardv	0:b079fa4ed182	3510	* @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
richardv	0:b079fa4ed182	3511	* is to be set, as soon as a capture or compare match occurs(TRGO)
richardv	0:b079fa4ed182	3512	* @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
richardv	0:b079fa4ed182	3513	* @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
richardv	0:b079fa4ed182	3514	* @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
richardv	0:b079fa4ed182	3515	* @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
richardv	0:b079fa4ed182	3516	*
richardv	0:b079fa4ed182	3517	* @retval None
richardv	0:b079fa4ed182	3518	*/
richardv	0:b079fa4ed182	3519	void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
richardv	0:b079fa4ed182	3520	{
richardv	0:b079fa4ed182	3521	/* Check the parameters */
richardv	0:b079fa4ed182	3522	assert_param(IS_TIM_LIST7_PERIPH(TIMx));
richardv	0:b079fa4ed182	3523	assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
richardv	0:b079fa4ed182	3524
richardv	0:b079fa4ed182	3525	/* Reset the MMS Bits */
richardv	0:b079fa4ed182	3526	TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
richardv	0:b079fa4ed182	3527	/* Select the TRGO source */
richardv	0:b079fa4ed182	3528	TIMx->CR2 \|= TIM_TRGOSource;
richardv	0:b079fa4ed182	3529	}
richardv	0:b079fa4ed182	3530
richardv	0:b079fa4ed182	3531	/**
richardv	0:b079fa4ed182	3532	* @brief Selects the TIMx Trigger Output Mode2 (TRGO2).
richardv	0:b079fa4ed182	3533	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	3534	*
richardv	0:b079fa4ed182	3535	* @param TIM_TRGO2Source: specifies the Trigger Output source.
richardv	0:b079fa4ed182	3536	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3537	*
richardv	0:b079fa4ed182	3538	* - For all TIMx
richardv	0:b079fa4ed182	3539	* @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3540	* @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3541	* @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3542	* @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
richardv	0:b079fa4ed182	3543	* is to be set, as soon as a capture or compare match occurs(TRGO2)
richardv	0:b079fa4ed182	3544	* @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3545	* @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3546	* @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3547	* @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3548	* @arg TIM_TRGO2Source_OC4Ref_RisingFalling: OC4Ref Rising and Falling are used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3549	* @arg TIM_TRGO2Source_OC6Ref_RisingFalling: OC6Ref Rising and Falling are used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3550	* @arg TIM_TRGO2Source_OC4RefRising_OC6RefRising: OC4Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3551	* @arg TIM_TRGO2Source_OC4RefRising_OC6RefFalling: OC4Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3552	* @arg TIM_TRGO2Source_OC5RefRising_OC6RefRising: OC5Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3553	* @arg TIM_TRGO2Source_OC5RefRising_OC6RefFalling: OC5Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
richardv	0:b079fa4ed182	3554	*
richardv	0:b079fa4ed182	3555	* @retval None
richardv	0:b079fa4ed182	3556	*/
richardv	0:b079fa4ed182	3557	void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source)
richardv	0:b079fa4ed182	3558	{
richardv	0:b079fa4ed182	3559	/* Check the parameters */
richardv	0:b079fa4ed182	3560	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
richardv	0:b079fa4ed182	3561	assert_param(IS_TIM_TRGO2_SOURCE(TIM_TRGO2Source));
richardv	0:b079fa4ed182	3562
richardv	0:b079fa4ed182	3563	/* Reset the MMS Bits */
richardv	0:b079fa4ed182	3564	TIMx->CR2 &= (uint32_t)~TIM_CR2_MMS2;
richardv	0:b079fa4ed182	3565	/* Select the TRGO source */
richardv	0:b079fa4ed182	3566	TIMx->CR2 \|= TIM_TRGO2Source;
richardv	0:b079fa4ed182	3567	}
richardv	0:b079fa4ed182	3568
richardv	0:b079fa4ed182	3569	/**
richardv	0:b079fa4ed182	3570	* @brief Selects the TIMx Slave Mode.
richardv	0:b079fa4ed182	3571	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
richardv	0:b079fa4ed182	3572	* @param TIM_SlaveMode: specifies the Timer Slave Mode.
richardv	0:b079fa4ed182	3573	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3574	* @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize
richardv	0:b079fa4ed182	3575	* the counter and triggers an update of the registers
richardv	0:b079fa4ed182	3576	* @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
richardv	0:b079fa4ed182	3577	* @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
richardv	0:b079fa4ed182	3578	* @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
richardv	0:b079fa4ed182	3579	* @arg TIM_SlaveMode_Combined_ResetTrigger: Rising edge of the selected trigger input (TRGI)
richardv	0:b079fa4ed182	3580	* reinitializes the counter, generates an update
richardv	0:b079fa4ed182	3581	* of the registers and starts the counter.
richardv	0:b079fa4ed182	3582	* @retval None
richardv	0:b079fa4ed182	3583	*/
richardv	0:b079fa4ed182	3584	void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode)
richardv	0:b079fa4ed182	3585	{
richardv	0:b079fa4ed182	3586	/* Check the parameters */
richardv	0:b079fa4ed182	3587	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	3588	assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
richardv	0:b079fa4ed182	3589
richardv	0:b079fa4ed182	3590	/* Reset the SMS Bits */
richardv	0:b079fa4ed182	3591	TIMx->SMCR &= (uint32_t)~TIM_SMCR_SMS;
richardv	0:b079fa4ed182	3592
richardv	0:b079fa4ed182	3593	/* Select the Slave Mode */
richardv	0:b079fa4ed182	3594	TIMx->SMCR \|= (uint32_t)TIM_SlaveMode;
richardv	0:b079fa4ed182	3595	}
richardv	0:b079fa4ed182	3596
richardv	0:b079fa4ed182	3597	/**
richardv	0:b079fa4ed182	3598	* @brief Sets or Resets the TIMx Master/Slave Mode.
richardv	0:b079fa4ed182	3599	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
richardv	0:b079fa4ed182	3600	* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
richardv	0:b079fa4ed182	3601	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3602	* @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
richardv	0:b079fa4ed182	3603	* and its slaves (through TRGO)
richardv	0:b079fa4ed182	3604	* @arg TIM_MasterSlaveMode_Disable: No action
richardv	0:b079fa4ed182	3605	* @retval None
richardv	0:b079fa4ed182	3606	*/
richardv	0:b079fa4ed182	3607	void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
richardv	0:b079fa4ed182	3608	{
richardv	0:b079fa4ed182	3609	/* Check the parameters */
richardv	0:b079fa4ed182	3610	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	3611	assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
richardv	0:b079fa4ed182	3612
richardv	0:b079fa4ed182	3613	/* Reset the MSM Bit */
richardv	0:b079fa4ed182	3614	TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
richardv	0:b079fa4ed182	3615
richardv	0:b079fa4ed182	3616	/* Set or Reset the MSM Bit */
richardv	0:b079fa4ed182	3617	TIMx->SMCR \|= TIM_MasterSlaveMode;
richardv	0:b079fa4ed182	3618	}
richardv	0:b079fa4ed182	3619
richardv	0:b079fa4ed182	3620	/**
richardv	0:b079fa4ed182	3621	* @brief Configures the TIMx External Trigger (ETR).
richardv	0:b079fa4ed182	3622	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	3623	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
richardv	0:b079fa4ed182	3624	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3625	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
richardv	0:b079fa4ed182	3626	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
richardv	0:b079fa4ed182	3627	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
richardv	0:b079fa4ed182	3628	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
richardv	0:b079fa4ed182	3629	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
richardv	0:b079fa4ed182	3630	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3631	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
richardv	0:b079fa4ed182	3632	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
richardv	0:b079fa4ed182	3633	* @param ExtTRGFilter: External Trigger Filter.
richardv	0:b079fa4ed182	3634	* This parameter must be a value between 0x00 and 0x0F
richardv	0:b079fa4ed182	3635	* @retval None
richardv	0:b079fa4ed182	3636	*/
richardv	0:b079fa4ed182	3637	void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
richardv	0:b079fa4ed182	3638	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
richardv	0:b079fa4ed182	3639	{
richardv	0:b079fa4ed182	3640	uint16_t tmpsmcr = 0;
richardv	0:b079fa4ed182	3641
richardv	0:b079fa4ed182	3642	/* Check the parameters */
richardv	0:b079fa4ed182	3643	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	3644	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
richardv	0:b079fa4ed182	3645	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
richardv	0:b079fa4ed182	3646	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
richardv	0:b079fa4ed182	3647
richardv	0:b079fa4ed182	3648	tmpsmcr = TIMx->SMCR;
richardv	0:b079fa4ed182	3649
richardv	0:b079fa4ed182	3650	/* Reset the ETR Bits */
richardv	0:b079fa4ed182	3651	tmpsmcr &= SMCR_ETR_MASK;
richardv	0:b079fa4ed182	3652
richardv	0:b079fa4ed182	3653	/* Set the Prescaler, the Filter value and the Polarity */
richardv	0:b079fa4ed182	3654	tmpsmcr \|= (uint16_t)(TIM_ExtTRGPrescaler \| (uint16_t)(TIM_ExtTRGPolarity \| (uint16_t)(ExtTRGFilter << (uint16_t)8)));
richardv	0:b079fa4ed182	3655
richardv	0:b079fa4ed182	3656	/* Write to TIMx SMCR */
richardv	0:b079fa4ed182	3657	TIMx->SMCR = tmpsmcr;
richardv	0:b079fa4ed182	3658	}
richardv	0:b079fa4ed182	3659	/**
richardv	0:b079fa4ed182	3660	* @}
richardv	0:b079fa4ed182	3661	*/
richardv	0:b079fa4ed182	3662
richardv	0:b079fa4ed182	3663	/** @defgroup TIM_Group8 Specific interface management functions
richardv	0:b079fa4ed182	3664	* @brief Specific interface management functions
richardv	0:b079fa4ed182	3665	*
richardv	0:b079fa4ed182	3666	@verbatim
richardv	0:b079fa4ed182	3667	===============================================================================
richardv	0:b079fa4ed182	3668	##### Specific interface management functions #####
richardv	0:b079fa4ed182	3669	===============================================================================
richardv	0:b079fa4ed182	3670
richardv	0:b079fa4ed182	3671	@endverbatim
richardv	0:b079fa4ed182	3672	* @{
richardv	0:b079fa4ed182	3673	*/
richardv	0:b079fa4ed182	3674
richardv	0:b079fa4ed182	3675	/**
richardv	0:b079fa4ed182	3676	* @brief Configures the TIMx Encoder Interface.
richardv	0:b079fa4ed182	3677	* @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM
richardv	0:b079fa4ed182	3678	* peripheral.
richardv	0:b079fa4ed182	3679	* @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
richardv	0:b079fa4ed182	3680	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3681	* @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
richardv	0:b079fa4ed182	3682	* @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
richardv	0:b079fa4ed182	3683	* @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
richardv	0:b079fa4ed182	3684	* on the level of the other input.
richardv	0:b079fa4ed182	3685	* @param TIM_IC1Polarity: specifies the IC1 Polarity
richardv	0:b079fa4ed182	3686	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3687	* @arg TIM_ICPolarity_Falling: IC Falling edge.
richardv	0:b079fa4ed182	3688	* @arg TIM_ICPolarity_Rising: IC Rising edge.
richardv	0:b079fa4ed182	3689	* @param TIM_IC2Polarity: specifies the IC2 Polarity
richardv	0:b079fa4ed182	3690	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3691	* @arg TIM_ICPolarity_Falling: IC Falling edge.
richardv	0:b079fa4ed182	3692	* @arg TIM_ICPolarity_Rising: IC Rising edge.
richardv	0:b079fa4ed182	3693	* @retval None
richardv	0:b079fa4ed182	3694	*/
richardv	0:b079fa4ed182	3695	void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
richardv	0:b079fa4ed182	3696	uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
richardv	0:b079fa4ed182	3697	{
richardv	0:b079fa4ed182	3698	uint16_t tmpsmcr = 0;
richardv	0:b079fa4ed182	3699	uint16_t tmpccmr1 = 0;
richardv	0:b079fa4ed182	3700	uint16_t tmpccer = 0;
richardv	0:b079fa4ed182	3701
richardv	0:b079fa4ed182	3702	/* Check the parameters */
richardv	0:b079fa4ed182	3703	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
richardv	0:b079fa4ed182	3704	assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
richardv	0:b079fa4ed182	3705	assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
richardv	0:b079fa4ed182	3706	assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
richardv	0:b079fa4ed182	3707
richardv	0:b079fa4ed182	3708	/* Get the TIMx SMCR register value */
richardv	0:b079fa4ed182	3709	tmpsmcr = TIMx->SMCR;
richardv	0:b079fa4ed182	3710
richardv	0:b079fa4ed182	3711	/* Get the TIMx CCMR1 register value */
richardv	0:b079fa4ed182	3712	tmpccmr1 = TIMx->CCMR1;
richardv	0:b079fa4ed182	3713
richardv	0:b079fa4ed182	3714	/* Get the TIMx CCER register value */
richardv	0:b079fa4ed182	3715	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	3716
richardv	0:b079fa4ed182	3717	/* Set the encoder Mode */
richardv	0:b079fa4ed182	3718	tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
richardv	0:b079fa4ed182	3719	tmpsmcr \|= TIM_EncoderMode;
richardv	0:b079fa4ed182	3720
richardv	0:b079fa4ed182	3721	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
richardv	0:b079fa4ed182	3722	tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
richardv	0:b079fa4ed182	3723	tmpccmr1 \|= TIM_CCMR1_CC1S_0 \| TIM_CCMR1_CC2S_0;
richardv	0:b079fa4ed182	3724
richardv	0:b079fa4ed182	3725	/* Set the TI1 and the TI2 Polarities */
richardv	0:b079fa4ed182	3726	tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
richardv	0:b079fa4ed182	3727	tmpccer \|= (uint16_t)(TIM_IC1Polarity \| (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
richardv	0:b079fa4ed182	3728
richardv	0:b079fa4ed182	3729	/* Write to TIMx SMCR */
richardv	0:b079fa4ed182	3730	TIMx->SMCR = tmpsmcr;
richardv	0:b079fa4ed182	3731
richardv	0:b079fa4ed182	3732	/* Write to TIMx CCMR1 */
richardv	0:b079fa4ed182	3733	TIMx->CCMR1 = tmpccmr1;
richardv	0:b079fa4ed182	3734
richardv	0:b079fa4ed182	3735	/* Write to TIMx CCER */
richardv	0:b079fa4ed182	3736	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	3737	}
richardv	0:b079fa4ed182	3738
richardv	0:b079fa4ed182	3739	/**
richardv	0:b079fa4ed182	3740	* @brief Enables or disables the TIMx's Hall sensor interface.
richardv	0:b079fa4ed182	3741	* @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
richardv	0:b079fa4ed182	3742	* peripheral.
richardv	0:b079fa4ed182	3743	* @param NewState: new state of the TIMx Hall sensor interface.
richardv	0:b079fa4ed182	3744	* This parameter can be: ENABLE or DISABLE.
richardv	0:b079fa4ed182	3745	* @retval None
richardv	0:b079fa4ed182	3746	*/
richardv	0:b079fa4ed182	3747	void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
richardv	0:b079fa4ed182	3748	{
richardv	0:b079fa4ed182	3749	/* Check the parameters */
richardv	0:b079fa4ed182	3750	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
richardv	0:b079fa4ed182	3751	assert_param(IS_FUNCTIONAL_STATE(NewState));
richardv	0:b079fa4ed182	3752
richardv	0:b079fa4ed182	3753	if (NewState != DISABLE)
richardv	0:b079fa4ed182	3754	{
richardv	0:b079fa4ed182	3755	/* Set the TI1S Bit */
richardv	0:b079fa4ed182	3756	TIMx->CR2 \|= TIM_CR2_TI1S;
richardv	0:b079fa4ed182	3757	}
richardv	0:b079fa4ed182	3758	else
richardv	0:b079fa4ed182	3759	{
richardv	0:b079fa4ed182	3760	/* Reset the TI1S Bit */
richardv	0:b079fa4ed182	3761	TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
richardv	0:b079fa4ed182	3762	}
richardv	0:b079fa4ed182	3763	}
richardv	0:b079fa4ed182	3764	/**
richardv	0:b079fa4ed182	3765	* @}
richardv	0:b079fa4ed182	3766	*/
richardv	0:b079fa4ed182	3767
richardv	0:b079fa4ed182	3768	/** @defgroup TIM_Group9 Specific remapping management function
richardv	0:b079fa4ed182	3769	* @brief Specific remapping management function
richardv	0:b079fa4ed182	3770	*
richardv	0:b079fa4ed182	3771	@verbatim
richardv	0:b079fa4ed182	3772	===============================================================================
richardv	0:b079fa4ed182	3773	##### Specific remapping management function #####
richardv	0:b079fa4ed182	3774	===============================================================================
richardv	0:b079fa4ed182	3775
richardv	0:b079fa4ed182	3776	@endverbatim
richardv	0:b079fa4ed182	3777	* @{
richardv	0:b079fa4ed182	3778	*/
richardv	0:b079fa4ed182	3779
richardv	0:b079fa4ed182	3780	/**
richardv	0:b079fa4ed182	3781	* @brief Configures the TIM16 Remapping input Capabilities.
richardv	0:b079fa4ed182	3782	* @param TIMx: where x can be 1, 8 or 16 to select the TIM peripheral.
richardv	0:b079fa4ed182	3783	* @param TIM_Remap: specifies the TIM input reampping source.
richardv	0:b079fa4ed182	3784	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3785	* @arg TIM16_GPIO: TIM16 Channel 1 is connected to GPIO.
richardv	0:b079fa4ed182	3786	* @arg TIM16_RTC_CLK: TIM16 Channel 1 is connected to RTC input clock.
richardv	0:b079fa4ed182	3787	* @arg TIM16_HSE_DIV32: TIM16 Channel 1 is connected to HSE/32 clock.
richardv	0:b079fa4ed182	3788	* @arg TIM16_MCO: TIM16 Channel 1 is connected to MCO clock.
richardv	0:b079fa4ed182	3789	* @arg TIM1_ADC1_AWDG1: TIM1 ETR is connected to ADC1 AWDG1.
richardv	0:b079fa4ed182	3790	* @arg TIM1_ADC1_AWDG2: TIM1 ETR is connected to ADC1 AWDG2.
richardv	0:b079fa4ed182	3791	* @arg TIM1_ADC1_AWDG3: TIM1 ETR is connected to ADC1 AWDG3.
richardv	0:b079fa4ed182	3792	* @arg TIM1_ADC4_AWDG1: TIM1 ETR is connected to ADC4 AWDG1.
richardv	0:b079fa4ed182	3793	* @arg TIM1_ADC4_AWDG2: TIM1 ETR is connected to ADC4 AWDG2.
richardv	0:b079fa4ed182	3794	* @arg TIM1_ADC4_AWDG3: TIM1 ETR is connected to ADC4 AWDG3.
richardv	0:b079fa4ed182	3795	* @arg TIM8_ADC2_AWDG1: TIM8 ETR is connected to ADC2 AWDG1.
richardv	0:b079fa4ed182	3796	* @arg TIM8_ADC2_AWDG2: TIM8 ETR is connected to ADC2 AWDG2.
richardv	0:b079fa4ed182	3797	* @arg TIM8_ADC2_AWDG3: TIM8 ETR is connected to ADC2 AWDG3.
richardv	0:b079fa4ed182	3798	* @arg TIM8_ADC4_AWDG1: TIM8 ETR is connected to ADC4 AWDG1.
richardv	0:b079fa4ed182	3799	* @arg TIM8_ADC4_AWDG2: TIM8 ETR is connected to ADC4 AWDG2.
richardv	0:b079fa4ed182	3800	* @arg TIM8_ADC4_AWDG3: TIM8 ETR is connected to ADC4 AWDG3.
richardv	0:b079fa4ed182	3801	* @retval : None
richardv	0:b079fa4ed182	3802	*/
richardv	0:b079fa4ed182	3803	void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
richardv	0:b079fa4ed182	3804	{
richardv	0:b079fa4ed182	3805	/* Check the parameters */
richardv	0:b079fa4ed182	3806	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
richardv	0:b079fa4ed182	3807	assert_param(IS_TIM_REMAP(TIM_Remap));
richardv	0:b079fa4ed182	3808
richardv	0:b079fa4ed182	3809	/* Set the Timer remapping configuration */
richardv	0:b079fa4ed182	3810	TIMx->OR = TIM_Remap;
richardv	0:b079fa4ed182	3811	}
richardv	0:b079fa4ed182	3812	/**
richardv	0:b079fa4ed182	3813	* @}
richardv	0:b079fa4ed182	3814	*/
richardv	0:b079fa4ed182	3815
richardv	0:b079fa4ed182	3816	/**
richardv	0:b079fa4ed182	3817	* @brief Configure the TI1 as Input.
richardv	0:b079fa4ed182	3818	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
richardv	0:b079fa4ed182	3819	* to select the TIM peripheral.
richardv	0:b079fa4ed182	3820	* @param TIM_ICPolarity : The Input Polarity.
richardv	0:b079fa4ed182	3821	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3822	* @arg TIM_ICPolarity_Rising
richardv	0:b079fa4ed182	3823	* @arg TIM_ICPolarity_Falling
richardv	0:b079fa4ed182	3824	* @arg TIM_ICPolarity_BothEdge
richardv	0:b079fa4ed182	3825	* @param TIM_ICSelection: specifies the input to be used.
richardv	0:b079fa4ed182	3826	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3827	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
richardv	0:b079fa4ed182	3828	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
richardv	0:b079fa4ed182	3829	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
richardv	0:b079fa4ed182	3830	* @param TIM_ICFilter: Specifies the Input Capture Filter.
richardv	0:b079fa4ed182	3831	* This parameter must be a value between 0x00 and 0x0F.
richardv	0:b079fa4ed182	3832	* @retval None
richardv	0:b079fa4ed182	3833	*/
richardv	0:b079fa4ed182	3834	static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
richardv	0:b079fa4ed182	3835	uint16_t TIM_ICFilter)
richardv	0:b079fa4ed182	3836	{
richardv	0:b079fa4ed182	3837	uint32_t tmpccmr1 = 0, tmpccer = 0;
richardv	0:b079fa4ed182	3838
richardv	0:b079fa4ed182	3839	/* Disable the Channel 1: Reset the CC1E Bit */
richardv	0:b079fa4ed182	3840	TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
richardv	0:b079fa4ed182	3841	tmpccmr1 = TIMx->CCMR1;
richardv	0:b079fa4ed182	3842	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	3843
richardv	0:b079fa4ed182	3844	/* Select the Input and set the filter */
richardv	0:b079fa4ed182	3845	tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC1S) & ((uint32_t)~TIM_CCMR1_IC1F);
richardv	0:b079fa4ed182	3846	tmpccmr1 \|= (uint32_t)(TIM_ICSelection \| (uint32_t)((uint32_t)TIM_ICFilter << 4));
richardv	0:b079fa4ed182	3847
richardv	0:b079fa4ed182	3848	/* Select the Polarity and set the CC1E Bit */
richardv	0:b079fa4ed182	3849	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
richardv	0:b079fa4ed182	3850	tmpccer \|= (uint32_t)(TIM_ICPolarity \| (uint32_t)TIM_CCER_CC1E);
richardv	0:b079fa4ed182	3851
richardv	0:b079fa4ed182	3852	/* Write to TIMx CCMR1 and CCER registers */
richardv	0:b079fa4ed182	3853	TIMx->CCMR1 = tmpccmr1;
richardv	0:b079fa4ed182	3854	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	3855	}
richardv	0:b079fa4ed182	3856
richardv	0:b079fa4ed182	3857	/**
richardv	0:b079fa4ed182	3858	* @brief Configure the TI2 as Input.
richardv	0:b079fa4ed182	3859	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
richardv	0:b079fa4ed182	3860	* peripheral.
richardv	0:b079fa4ed182	3861	* @param TIM_ICPolarity : The Input Polarity.
richardv	0:b079fa4ed182	3862	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3863	* @arg TIM_ICPolarity_Rising
richardv	0:b079fa4ed182	3864	* @arg TIM_ICPolarity_Falling
richardv	0:b079fa4ed182	3865	* @arg TIM_ICPolarity_BothEdge
richardv	0:b079fa4ed182	3866	* @param TIM_ICSelection: specifies the input to be used.
richardv	0:b079fa4ed182	3867	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3868	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
richardv	0:b079fa4ed182	3869	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
richardv	0:b079fa4ed182	3870	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
richardv	0:b079fa4ed182	3871	* @param TIM_ICFilter: Specifies the Input Capture Filter.
richardv	0:b079fa4ed182	3872	* This parameter must be a value between 0x00 and 0x0F.
richardv	0:b079fa4ed182	3873	* @retval None
richardv	0:b079fa4ed182	3874	*/
richardv	0:b079fa4ed182	3875	static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
richardv	0:b079fa4ed182	3876	uint16_t TIM_ICFilter)
richardv	0:b079fa4ed182	3877	{
richardv	0:b079fa4ed182	3878	uint32_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
richardv	0:b079fa4ed182	3879
richardv	0:b079fa4ed182	3880	/* Disable the Channel 2: Reset the CC2E Bit */
richardv	0:b079fa4ed182	3881	TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
richardv	0:b079fa4ed182	3882	tmpccmr1 = TIMx->CCMR1;
richardv	0:b079fa4ed182	3883	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	3884	tmp = (uint16_t)(TIM_ICPolarity << 4);
richardv	0:b079fa4ed182	3885
richardv	0:b079fa4ed182	3886	/* Select the Input and set the filter */
richardv	0:b079fa4ed182	3887	tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC2S) & ((uint32_t)~TIM_CCMR1_IC2F);
richardv	0:b079fa4ed182	3888	tmpccmr1 \|= (uint32_t)((uint32_t)TIM_ICFilter << 12);
richardv	0:b079fa4ed182	3889	tmpccmr1 \|= (uint32_t)((uint32_t)TIM_ICSelection << 8);
richardv	0:b079fa4ed182	3890
richardv	0:b079fa4ed182	3891	/* Select the Polarity and set the CC2E Bit */
richardv	0:b079fa4ed182	3892	tmpccer &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
richardv	0:b079fa4ed182	3893	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC2E);
richardv	0:b079fa4ed182	3894
richardv	0:b079fa4ed182	3895	/* Write to TIMx CCMR1 and CCER registers */
richardv	0:b079fa4ed182	3896	TIMx->CCMR1 = tmpccmr1 ;
richardv	0:b079fa4ed182	3897	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	3898	}
richardv	0:b079fa4ed182	3899
richardv	0:b079fa4ed182	3900	/**
richardv	0:b079fa4ed182	3901	* @brief Configure the TI3 as Input.
richardv	0:b079fa4ed182	3902	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	3903	* @param TIM_ICPolarity : The Input Polarity.
richardv	0:b079fa4ed182	3904	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3905	* @arg TIM_ICPolarity_Rising
richardv	0:b079fa4ed182	3906	* @arg TIM_ICPolarity_Falling
richardv	0:b079fa4ed182	3907	* @arg TIM_ICPolarity_BothEdge
richardv	0:b079fa4ed182	3908	* @param TIM_ICSelection: specifies the input to be used.
richardv	0:b079fa4ed182	3909	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3910	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
richardv	0:b079fa4ed182	3911	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
richardv	0:b079fa4ed182	3912	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
richardv	0:b079fa4ed182	3913	* @param TIM_ICFilter: Specifies the Input Capture Filter.
richardv	0:b079fa4ed182	3914	* This parameter must be a value between 0x00 and 0x0F.
richardv	0:b079fa4ed182	3915	* @retval None
richardv	0:b079fa4ed182	3916	*/
richardv	0:b079fa4ed182	3917	static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
richardv	0:b079fa4ed182	3918	uint16_t TIM_ICFilter)
richardv	0:b079fa4ed182	3919	{
richardv	0:b079fa4ed182	3920	uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
richardv	0:b079fa4ed182	3921
richardv	0:b079fa4ed182	3922	/* Disable the Channel 3: Reset the CC3E Bit */
richardv	0:b079fa4ed182	3923	TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
richardv	0:b079fa4ed182	3924	tmpccmr2 = TIMx->CCMR2;
richardv	0:b079fa4ed182	3925	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	3926	tmp = (uint16_t)(TIM_ICPolarity << 8);
richardv	0:b079fa4ed182	3927
richardv	0:b079fa4ed182	3928	/* Select the Input and set the filter */
richardv	0:b079fa4ed182	3929	tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
richardv	0:b079fa4ed182	3930	tmpccmr2 \|= (uint16_t)(TIM_ICSelection \| (uint16_t)(TIM_ICFilter << (uint16_t)4));
richardv	0:b079fa4ed182	3931
richardv	0:b079fa4ed182	3932	/* Select the Polarity and set the CC3E Bit */
richardv	0:b079fa4ed182	3933	tmpccer &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
richardv	0:b079fa4ed182	3934	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC3E);
richardv	0:b079fa4ed182	3935
richardv	0:b079fa4ed182	3936	/* Write to TIMx CCMR2 and CCER registers */
richardv	0:b079fa4ed182	3937	TIMx->CCMR2 = tmpccmr2;
richardv	0:b079fa4ed182	3938	TIMx->CCER = tmpccer;
richardv	0:b079fa4ed182	3939	}
richardv	0:b079fa4ed182	3940
richardv	0:b079fa4ed182	3941	/**
richardv	0:b079fa4ed182	3942	* @brief Configure the TI4 as Input.
richardv	0:b079fa4ed182	3943	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
richardv	0:b079fa4ed182	3944	* @param TIM_ICPolarity : The Input Polarity.
richardv	0:b079fa4ed182	3945	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3946	* @arg TIM_ICPolarity_Rising
richardv	0:b079fa4ed182	3947	* @arg TIM_ICPolarity_Falling
richardv	0:b079fa4ed182	3948	* @arg TIM_ICPolarity_BothEdge
richardv	0:b079fa4ed182	3949	* @param TIM_ICSelection: specifies the input to be used.
richardv	0:b079fa4ed182	3950	* This parameter can be one of the following values:
richardv	0:b079fa4ed182	3951	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
richardv	0:b079fa4ed182	3952	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
richardv	0:b079fa4ed182	3953	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
richardv	0:b079fa4ed182	3954	* @param TIM_ICFilter: Specifies the Input Capture Filter.
richardv	0:b079fa4ed182	3955	* This parameter must be a value between 0x00 and 0x0F.
richardv	0:b079fa4ed182	3956	* @retval None
richardv	0:b079fa4ed182	3957	*/
richardv	0:b079fa4ed182	3958	static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
richardv	0:b079fa4ed182	3959	uint16_t TIM_ICFilter)
richardv	0:b079fa4ed182	3960	{
richardv	0:b079fa4ed182	3961	uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
richardv	0:b079fa4ed182	3962
richardv	0:b079fa4ed182	3963	/* Disable the Channel 4: Reset the CC4E Bit */
richardv	0:b079fa4ed182	3964	TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
richardv	0:b079fa4ed182	3965	tmpccmr2 = TIMx->CCMR2;
richardv	0:b079fa4ed182	3966	tmpccer = TIMx->CCER;
richardv	0:b079fa4ed182	3967	tmp = (uint16_t)(TIM_ICPolarity << 12);
richardv	0:b079fa4ed182	3968
richardv	0:b079fa4ed182	3969	/* Select the Input and set the filter */
richardv	0:b079fa4ed182	3970	tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
richardv	0:b079fa4ed182	3971	tmpccmr2 \|= (uint16_t)(TIM_ICSelection << 8);
richardv	0:b079fa4ed182	3972	tmpccmr2 \|= (uint16_t)(TIM_ICFilter << 12);
richardv	0:b079fa4ed182	3973
richardv	0:b079fa4ed182	3974	/* Select the Polarity and set the CC4E Bit */
richardv	0:b079fa4ed182	3975	tmpccer &= (uint16_t)~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
richardv	0:b079fa4ed182	3976	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC4E);
richardv	0:b079fa4ed182	3977
richardv	0:b079fa4ed182	3978	/* Write to TIMx CCMR2 and CCER registers */
richardv	0:b079fa4ed182	3979	TIMx->CCMR2 = tmpccmr2;
richardv	0:b079fa4ed182	3980	TIMx->CCER = tmpccer ;
richardv	0:b079fa4ed182	3981	}
richardv	0:b079fa4ed182	3982
richardv	0:b079fa4ed182	3983	/**
richardv	0:b079fa4ed182	3984	* @}
richardv	0:b079fa4ed182	3985	*/
richardv	0:b079fa4ed182	3986
richardv	0:b079fa4ed182	3987	/**
richardv	0:b079fa4ed182	3988	* @}
richardv	0:b079fa4ed182	3989	*/
richardv	0:b079fa4ed182	3990
richardv	0:b079fa4ed182	3991	/**
richardv	0:b079fa4ed182	3992	* @}
richardv	0:b079fa4ed182	3993	*/
richardv	0:b079fa4ed182	3994
richardv	0:b079fa4ed182	3995	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	02 Nov 2016
Imports:	8
Forks:	0
Commits:	1
Dependents:	0
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stm32f30x_tim.c@0:b079fa4ed182, 2016-11-02 (annotated)

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