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TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h@99:dbbf35b96557, 2015-05-13 (annotated)

Committer:: Kojto
Date:: Wed May 13 08:08:21 2015 +0200
Revision:: 99:dbbf35b96557
Parent:: 90:cb3d968589d8
Child:: 106:ba1f97679dad

Release 99 of the mbed library



Changes:

 - new targets - MAXWSNENV, DISCO_L053C8

 - STM32F4xx - ST Cube driver

 - KSDK mcu - SPI timing fix

 - Nordic - update to softdevice s130

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_hal_tim.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
Kojto	99:dbbf35b96557	5	* @version V1.3.0
Kojto	99:dbbf35b96557	6	* @date 09-March-2015
emilmont	77:869cf507173a	7	* @brief Header file of TIM HAL module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
Kojto	99:dbbf35b96557	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_HAL_TIM_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_HAL_TIM_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	47	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	48
Kojto	99:dbbf35b96557	49	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	50	* @{
emilmont	77:869cf507173a	51	*/
emilmont	77:869cf507173a	52
emilmont	77:869cf507173a	53	/** @addtogroup TIM
emilmont	77:869cf507173a	54	* @{
bogdanm	85:024bf7f99721	55	*/
emilmont	77:869cf507173a	56
bogdanm	85:024bf7f99721	57	/* Exported types ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	58	/** @defgroup TIM_Exported_Types TIM Exported Types
Kojto	99:dbbf35b96557	59	* @{
Kojto	99:dbbf35b96557	60	*/
Kojto	99:dbbf35b96557	61
emilmont	77:869cf507173a	62	/**
emilmont	77:869cf507173a	63	* @brief TIM Time base Configuration Structure definition
emilmont	77:869cf507173a	64	*/
emilmont	77:869cf507173a	65	typedef struct
emilmont	77:869cf507173a	66	{
emilmont	77:869cf507173a	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
emilmont	77:869cf507173a	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
emilmont	77:869cf507173a	69
emilmont	77:869cf507173a	70	uint32_t CounterMode; /*!< Specifies the counter mode.
emilmont	77:869cf507173a	71	This parameter can be a value of @ref TIM_Counter_Mode */
emilmont	77:869cf507173a	72
emilmont	77:869cf507173a	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
emilmont	77:869cf507173a	74	Auto-Reload Register at the next update event.
bogdanm	85:024bf7f99721	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
emilmont	77:869cf507173a	76
emilmont	77:869cf507173a	77	uint32_t ClockDivision; /*!< Specifies the clock division.
emilmont	77:869cf507173a	78	This parameter can be a value of @ref TIM_ClockDivision */
emilmont	77:869cf507173a	79
emilmont	77:869cf507173a	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
emilmont	77:869cf507173a	81	reaches zero, an update event is generated and counting restarts
emilmont	77:869cf507173a	82	from the RCR value (N).
emilmont	77:869cf507173a	83	This means in PWM mode that (N+1) corresponds to:
emilmont	77:869cf507173a	84	- the number of PWM periods in edge-aligned mode
emilmont	77:869cf507173a	85	- the number of half PWM period in center-aligned mode
emilmont	77:869cf507173a	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
emilmont	77:869cf507173a	87	@note This parameter is valid only for TIM1 and TIM8. */
emilmont	77:869cf507173a	88	} TIM_Base_InitTypeDef;
emilmont	77:869cf507173a	89
emilmont	77:869cf507173a	90	/**
emilmont	77:869cf507173a	91	* @brief TIM Output Compare Configuration Structure definition
emilmont	77:869cf507173a	92	*/
emilmont	77:869cf507173a	93
emilmont	77:869cf507173a	94	typedef struct
bogdanm	85:024bf7f99721	95	{
emilmont	77:869cf507173a	96	uint32_t OCMode; /*!< Specifies the TIM mode.
emilmont	77:869cf507173a	97	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
emilmont	77:869cf507173a	98
emilmont	77:869cf507173a	99	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	85:024bf7f99721	100	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
emilmont	77:869cf507173a	101
emilmont	77:869cf507173a	102	uint32_t OCPolarity; /*!< Specifies the output polarity.
emilmont	77:869cf507173a	103	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
emilmont	77:869cf507173a	104
emilmont	77:869cf507173a	105	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
emilmont	77:869cf507173a	106	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
emilmont	77:869cf507173a	107	@note This parameter is valid only for TIM1 and TIM8. */
emilmont	77:869cf507173a	108
emilmont	77:869cf507173a	109	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
emilmont	77:869cf507173a	110	This parameter can be a value of @ref TIM_Output_Fast_State
emilmont	77:869cf507173a	111	@note This parameter is valid only in PWM1 and PWM2 mode. */
emilmont	77:869cf507173a	112
emilmont	77:869cf507173a	113
emilmont	77:869cf507173a	114	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
emilmont	77:869cf507173a	115	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
emilmont	77:869cf507173a	116	@note This parameter is valid only for TIM1 and TIM8. */
emilmont	77:869cf507173a	117
emilmont	77:869cf507173a	118	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
emilmont	77:869cf507173a	119	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
emilmont	77:869cf507173a	120	@note This parameter is valid only for TIM1 and TIM8. */
emilmont	77:869cf507173a	121	} TIM_OC_InitTypeDef;
emilmont	77:869cf507173a	122
emilmont	77:869cf507173a	123	/**
emilmont	77:869cf507173a	124	* @brief TIM One Pulse Mode Configuration Structure definition
emilmont	77:869cf507173a	125	*/
emilmont	77:869cf507173a	126	typedef struct
bogdanm	85:024bf7f99721	127	{
emilmont	77:869cf507173a	128	uint32_t OCMode; /*!< Specifies the TIM mode.
emilmont	77:869cf507173a	129	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
emilmont	77:869cf507173a	130
emilmont	77:869cf507173a	131	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	85:024bf7f99721	132	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
emilmont	77:869cf507173a	133
emilmont	77:869cf507173a	134	uint32_t OCPolarity; /*!< Specifies the output polarity.
emilmont	77:869cf507173a	135	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
emilmont	77:869cf507173a	136
emilmont	77:869cf507173a	137	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
emilmont	77:869cf507173a	138	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
emilmont	77:869cf507173a	139	@note This parameter is valid only for TIM1 and TIM8. */
emilmont	77:869cf507173a	140
emilmont	77:869cf507173a	141	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
emilmont	77:869cf507173a	142	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
emilmont	77:869cf507173a	143	@note This parameter is valid only for TIM1 and TIM8. */
emilmont	77:869cf507173a	144
emilmont	77:869cf507173a	145	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
emilmont	77:869cf507173a	146	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
emilmont	77:869cf507173a	147	@note This parameter is valid only for TIM1 and TIM8. */
emilmont	77:869cf507173a	148
emilmont	77:869cf507173a	149	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
emilmont	77:869cf507173a	150	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
emilmont	77:869cf507173a	151
emilmont	77:869cf507173a	152	uint32_t ICSelection; /*!< Specifies the input.
emilmont	77:869cf507173a	153	This parameter can be a value of @ref TIM_Input_Capture_Selection */
emilmont	77:869cf507173a	154
emilmont	77:869cf507173a	155	uint32_t ICFilter; /*!< Specifies the input capture filter.
emilmont	77:869cf507173a	156	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
emilmont	77:869cf507173a	157	} TIM_OnePulse_InitTypeDef;
emilmont	77:869cf507173a	158
emilmont	77:869cf507173a	159
emilmont	77:869cf507173a	160	/**
emilmont	77:869cf507173a	161	* @brief TIM Input Capture Configuration Structure definition
emilmont	77:869cf507173a	162	*/
emilmont	77:869cf507173a	163
emilmont	77:869cf507173a	164	typedef struct
bogdanm	85:024bf7f99721	165	{
emilmont	77:869cf507173a	166	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
emilmont	77:869cf507173a	167	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
emilmont	77:869cf507173a	168
emilmont	77:869cf507173a	169	uint32_t ICSelection; /*!< Specifies the input.
emilmont	77:869cf507173a	170	This parameter can be a value of @ref TIM_Input_Capture_Selection */
emilmont	77:869cf507173a	171
emilmont	77:869cf507173a	172	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
emilmont	77:869cf507173a	173	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
emilmont	77:869cf507173a	174
emilmont	77:869cf507173a	175	uint32_t ICFilter; /*!< Specifies the input capture filter.
emilmont	77:869cf507173a	176	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
emilmont	77:869cf507173a	177	} TIM_IC_InitTypeDef;
emilmont	77:869cf507173a	178
emilmont	77:869cf507173a	179	/**
emilmont	77:869cf507173a	180	* @brief TIM Encoder Configuration Structure definition
emilmont	77:869cf507173a	181	*/
emilmont	77:869cf507173a	182
emilmont	77:869cf507173a	183	typedef struct
emilmont	77:869cf507173a	184	{
emilmont	77:869cf507173a	185	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
emilmont	77:869cf507173a	186	This parameter can be a value of @ref TIM_Encoder_Mode */
emilmont	77:869cf507173a	187
emilmont	77:869cf507173a	188	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
emilmont	77:869cf507173a	189	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
emilmont	77:869cf507173a	190
emilmont	77:869cf507173a	191	uint32_t IC1Selection; /*!< Specifies the input.
emilmont	77:869cf507173a	192	This parameter can be a value of @ref TIM_Input_Capture_Selection */
emilmont	77:869cf507173a	193
emilmont	77:869cf507173a	194	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
emilmont	77:869cf507173a	195	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
emilmont	77:869cf507173a	196
emilmont	77:869cf507173a	197	uint32_t IC1Filter; /*!< Specifies the input capture filter.
emilmont	77:869cf507173a	198	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
emilmont	77:869cf507173a	199
emilmont	77:869cf507173a	200	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
emilmont	77:869cf507173a	201	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
emilmont	77:869cf507173a	202
emilmont	77:869cf507173a	203	uint32_t IC2Selection; /*!< Specifies the input.
emilmont	77:869cf507173a	204	This parameter can be a value of @ref TIM_Input_Capture_Selection */
emilmont	77:869cf507173a	205
emilmont	77:869cf507173a	206	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
emilmont	77:869cf507173a	207	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
emilmont	77:869cf507173a	208
emilmont	77:869cf507173a	209	uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm	85:024bf7f99721	210	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
emilmont	77:869cf507173a	211	} TIM_Encoder_InitTypeDef;
emilmont	77:869cf507173a	212
emilmont	77:869cf507173a	213	/**
emilmont	77:869cf507173a	214	* @brief Clock Configuration Handle Structure definition
emilmont	77:869cf507173a	215	*/
emilmont	77:869cf507173a	216	typedef struct
emilmont	77:869cf507173a	217	{
bogdanm	85:024bf7f99721	218	uint32_t ClockSource; /*!< TIM clock sources.
emilmont	77:869cf507173a	219	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	85:024bf7f99721	220	uint32_t ClockPolarity; /*!< TIM clock polarity.
emilmont	77:869cf507173a	221	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	85:024bf7f99721	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
emilmont	77:869cf507173a	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	85:024bf7f99721	224	uint32_t ClockFilter; /*!< TIM clock filter.
bogdanm	85:024bf7f99721	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
emilmont	77:869cf507173a	226	}TIM_ClockConfigTypeDef;
emilmont	77:869cf507173a	227
emilmont	77:869cf507173a	228	/**
emilmont	77:869cf507173a	229	* @brief Clear Input Configuration Handle Structure definition
emilmont	77:869cf507173a	230	*/
emilmont	77:869cf507173a	231	typedef struct
emilmont	77:869cf507173a	232	{
bogdanm	85:024bf7f99721	233	uint32_t ClearInputState; /*!< TIM clear Input state.
emilmont	77:869cf507173a	234	This parameter can be ENABLE or DISABLE */
bogdanm	85:024bf7f99721	235	uint32_t ClearInputSource; /*!< TIM clear Input sources.
emilmont	77:869cf507173a	236	This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm	85:024bf7f99721	237	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
emilmont	77:869cf507173a	238	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	85:024bf7f99721	239	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
emilmont	77:869cf507173a	240	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	85:024bf7f99721	241	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
bogdanm	85:024bf7f99721	242	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
emilmont	77:869cf507173a	243	}TIM_ClearInputConfigTypeDef;
emilmont	77:869cf507173a	244
emilmont	77:869cf507173a	245	/**
emilmont	77:869cf507173a	246	* @brief TIM Slave configuration Structure definition
emilmont	77:869cf507173a	247	*/
emilmont	77:869cf507173a	248	typedef struct {
emilmont	77:869cf507173a	249	uint32_t SlaveMode; /*!< Slave mode selection
emilmont	77:869cf507173a	250	This parameter can be a value of @ref TIM_Slave_Mode */
emilmont	77:869cf507173a	251	uint32_t InputTrigger; /*!< Input Trigger source
emilmont	77:869cf507173a	252	This parameter can be a value of @ref TIM_Trigger_Selection */
emilmont	77:869cf507173a	253	uint32_t TriggerPolarity; /*!< Input Trigger polarity
emilmont	77:869cf507173a	254	This parameter can be a value of @ref TIM_Trigger_Polarity */
emilmont	77:869cf507173a	255	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
emilmont	77:869cf507173a	256	This parameter can be a value of @ref TIM_Trigger_Prescaler */
emilmont	77:869cf507173a	257	uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm	85:024bf7f99721	258	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
emilmont	77:869cf507173a	259
emilmont	77:869cf507173a	260	}TIM_SlaveConfigTypeDef;
emilmont	77:869cf507173a	261
emilmont	77:869cf507173a	262	/**
emilmont	77:869cf507173a	263	* @brief HAL State structures definition
emilmont	77:869cf507173a	264	*/
emilmont	77:869cf507173a	265	typedef enum
emilmont	77:869cf507173a	266	{
emilmont	77:869cf507173a	267	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
emilmont	77:869cf507173a	268	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	85:024bf7f99721	269	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	85:024bf7f99721	270	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	85:024bf7f99721	271	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
emilmont	77:869cf507173a	272	}HAL_TIM_StateTypeDef;
emilmont	77:869cf507173a	273
emilmont	77:869cf507173a	274	/**
emilmont	77:869cf507173a	275	* @brief HAL Active channel structures definition
emilmont	77:869cf507173a	276	*/
emilmont	77:869cf507173a	277	typedef enum
emilmont	77:869cf507173a	278	{
emilmont	77:869cf507173a	279	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
emilmont	77:869cf507173a	280	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
bogdanm	85:024bf7f99721	281	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
emilmont	77:869cf507173a	282	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
bogdanm	85:024bf7f99721	283	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
emilmont	77:869cf507173a	284	}HAL_TIM_ActiveChannel;
emilmont	77:869cf507173a	285
emilmont	77:869cf507173a	286	/**
emilmont	77:869cf507173a	287	* @brief TIM Time Base Handle Structure definition
emilmont	77:869cf507173a	288	*/
emilmont	77:869cf507173a	289	typedef struct
emilmont	77:869cf507173a	290	{
bogdanm	85:024bf7f99721	291	TIM_TypeDef Instance; /!< Register base address */
emilmont	77:869cf507173a	292	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
bogdanm	85:024bf7f99721	293	HAL_TIM_ActiveChannel Channel; /!< Active channel /
emilmont	77:869cf507173a	294	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
emilmont	77:869cf507173a	295	This array is accessed by a @ref DMA_Handle_index */
emilmont	77:869cf507173a	296	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	85:024bf7f99721	297	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
emilmont	77:869cf507173a	298	}TIM_HandleTypeDef;
Kojto	99:dbbf35b96557	299	/**
Kojto	99:dbbf35b96557	300	* @}
Kojto	99:dbbf35b96557	301	*/
emilmont	77:869cf507173a	302
emilmont	77:869cf507173a	303	/* Exported constants --------------------------------------------------------*/
Kojto	99:dbbf35b96557	304	/** @defgroup TIM_Exported_Constants TIM Exported Constants
emilmont	77:869cf507173a	305	* @{
emilmont	77:869cf507173a	306	*/
emilmont	77:869cf507173a	307
Kojto	99:dbbf35b96557	308	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
emilmont	77:869cf507173a	309	* @{
emilmont	77:869cf507173a	310	*/
emilmont	77:869cf507173a	311	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
emilmont	77:869cf507173a	312	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
emilmont	77:869cf507173a	313	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
emilmont	77:869cf507173a	314	/**
emilmont	77:869cf507173a	315	* @}
emilmont	77:869cf507173a	316	*/
emilmont	77:869cf507173a	317
Kojto	99:dbbf35b96557	318	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
emilmont	77:869cf507173a	319	* @{
emilmont	77:869cf507173a	320	*/
bogdanm	85:024bf7f99721	321	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
bogdanm	85:024bf7f99721	322	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
emilmont	77:869cf507173a	323	/**
emilmont	77:869cf507173a	324	* @}
emilmont	77:869cf507173a	325	*/
emilmont	77:869cf507173a	326
Kojto	99:dbbf35b96557	327	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
emilmont	77:869cf507173a	328	* @{
bogdanm	85:024bf7f99721	329	*/
emilmont	77:869cf507173a	330	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
emilmont	77:869cf507173a	331	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
emilmont	77:869cf507173a	332	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
emilmont	77:869cf507173a	333	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
emilmont	77:869cf507173a	334	/**
emilmont	77:869cf507173a	335	* @}
emilmont	77:869cf507173a	336	*/
emilmont	77:869cf507173a	337
Kojto	99:dbbf35b96557	338	/** @defgroup TIM_Counter_Mode TIM Counter Mode
emilmont	77:869cf507173a	339	* @{
emilmont	77:869cf507173a	340	*/
emilmont	77:869cf507173a	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
emilmont	77:869cf507173a	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
emilmont	77:869cf507173a	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
emilmont	77:869cf507173a	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
emilmont	77:869cf507173a	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
emilmont	77:869cf507173a	346	/**
emilmont	77:869cf507173a	347	* @}
bogdanm	85:024bf7f99721	348	*/
bogdanm	85:024bf7f99721	349
Kojto	99:dbbf35b96557	350	/** @defgroup TIM_ClockDivision TIM Clock Division
emilmont	77:869cf507173a	351	* @{
emilmont	77:869cf507173a	352	*/
emilmont	77:869cf507173a	353	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
emilmont	77:869cf507173a	354	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
emilmont	77:869cf507173a	355	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
emilmont	77:869cf507173a	356	/**
emilmont	77:869cf507173a	357	* @}
emilmont	77:869cf507173a	358	*/
emilmont	77:869cf507173a	359
Kojto	99:dbbf35b96557	360	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
emilmont	77:869cf507173a	361	* @{
emilmont	77:869cf507173a	362	*/
emilmont	77:869cf507173a	363	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
emilmont	77:869cf507173a	364	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
emilmont	77:869cf507173a	365	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
emilmont	77:869cf507173a	366	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
emilmont	77:869cf507173a	367	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
emilmont	77:869cf507173a	368	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
emilmont	77:869cf507173a	369	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
emilmont	77:869cf507173a	370	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
emilmont	77:869cf507173a	371
emilmont	77:869cf507173a	372	/**
emilmont	77:869cf507173a	373	* @}
emilmont	77:869cf507173a	374	*/
emilmont	77:869cf507173a	375
Kojto	99:dbbf35b96557	376	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
emilmont	77:869cf507173a	377	* @{
emilmont	77:869cf507173a	378	*/
Kojto	99:dbbf35b96557	379	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
Kojto	99:dbbf35b96557	380	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
emilmont	77:869cf507173a	381	/**
emilmont	77:869cf507173a	382	* @}
bogdanm	85:024bf7f99721	383	*/
bogdanm	85:024bf7f99721	384
Kojto	99:dbbf35b96557	385	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
emilmont	77:869cf507173a	386	* @{
emilmont	77:869cf507173a	387	*/
Kojto	99:dbbf35b96557	388	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
Kojto	99:dbbf35b96557	389	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
emilmont	77:869cf507173a	390	/**
emilmont	77:869cf507173a	391	* @}
bogdanm	85:024bf7f99721	392	*/
bogdanm	85:024bf7f99721	393
Kojto	99:dbbf35b96557	394	/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
emilmont	77:869cf507173a	395	* @{
emilmont	77:869cf507173a	396	*/
emilmont	77:869cf507173a	397	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
emilmont	77:869cf507173a	398	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
emilmont	77:869cf507173a	399	/**
emilmont	77:869cf507173a	400	* @}
emilmont	77:869cf507173a	401	*/
emilmont	77:869cf507173a	402
Kojto	99:dbbf35b96557	403	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
emilmont	77:869cf507173a	404	* @{
emilmont	77:869cf507173a	405	*/
emilmont	77:869cf507173a	406	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
emilmont	77:869cf507173a	407	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
emilmont	77:869cf507173a	408	/**
emilmont	77:869cf507173a	409	* @}
emilmont	77:869cf507173a	410	*/
emilmont	77:869cf507173a	411
Kojto	99:dbbf35b96557	412	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
emilmont	77:869cf507173a	413	* @{
emilmont	77:869cf507173a	414	*/
emilmont	77:869cf507173a	415	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
emilmont	77:869cf507173a	416	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
emilmont	77:869cf507173a	417	/**
emilmont	77:869cf507173a	418	* @}
emilmont	77:869cf507173a	419	*/
emilmont	77:869cf507173a	420
Kojto	99:dbbf35b96557	421	/** @defgroup TIM_Channel TIM Channel
emilmont	77:869cf507173a	422	* @{
emilmont	77:869cf507173a	423	*/
emilmont	77:869cf507173a	424	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
emilmont	77:869cf507173a	425	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
emilmont	77:869cf507173a	426	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
emilmont	77:869cf507173a	427	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
emilmont	77:869cf507173a	428	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
emilmont	77:869cf507173a	429
emilmont	77:869cf507173a	430	/**
emilmont	77:869cf507173a	431	* @}
bogdanm	85:024bf7f99721	432	*/
emilmont	77:869cf507173a	433
Kojto	99:dbbf35b96557	434	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
emilmont	77:869cf507173a	435	* @{
emilmont	77:869cf507173a	436	*/
emilmont	77:869cf507173a	437	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
emilmont	77:869cf507173a	438	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
emilmont	77:869cf507173a	439	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
emilmont	77:869cf507173a	440	/**
emilmont	77:869cf507173a	441	* @}
bogdanm	85:024bf7f99721	442	*/
emilmont	77:869cf507173a	443
Kojto	99:dbbf35b96557	444	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
emilmont	77:869cf507173a	445	* @{
emilmont	77:869cf507173a	446	*/
emilmont	77:869cf507173a	447	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
emilmont	77:869cf507173a	448	connected to IC1, IC2, IC3 or IC4, respectively */
emilmont	77:869cf507173a	449	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
emilmont	77:869cf507173a	450	connected to IC2, IC1, IC4 or IC3, respectively */
emilmont	77:869cf507173a	451	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
emilmont	77:869cf507173a	452
emilmont	77:869cf507173a	453	/**
emilmont	77:869cf507173a	454	* @}
bogdanm	85:024bf7f99721	455	*/
emilmont	77:869cf507173a	456
Kojto	99:dbbf35b96557	457	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
emilmont	77:869cf507173a	458	* @{
emilmont	77:869cf507173a	459	*/
emilmont	77:869cf507173a	460	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
emilmont	77:869cf507173a	461	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
emilmont	77:869cf507173a	462	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
emilmont	77:869cf507173a	463	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
emilmont	77:869cf507173a	464	/**
emilmont	77:869cf507173a	465	* @}
emilmont	77:869cf507173a	466	*/
emilmont	77:869cf507173a	467
Kojto	99:dbbf35b96557	468	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
emilmont	77:869cf507173a	469	* @{
emilmont	77:869cf507173a	470	*/
emilmont	77:869cf507173a	471	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
emilmont	77:869cf507173a	472	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
emilmont	77:869cf507173a	473	/**
emilmont	77:869cf507173a	474	* @}
bogdanm	85:024bf7f99721	475	*/
bogdanm	85:024bf7f99721	476
Kojto	99:dbbf35b96557	477	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
emilmont	77:869cf507173a	478	* @{
bogdanm	85:024bf7f99721	479	*/
emilmont	77:869cf507173a	480	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
emilmont	77:869cf507173a	481	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
emilmont	77:869cf507173a	482	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
Kojto	99:dbbf35b96557	483
emilmont	77:869cf507173a	484	/**
emilmont	77:869cf507173a	485	* @}
bogdanm	85:024bf7f99721	486	*/
bogdanm	85:024bf7f99721	487
Kojto	99:dbbf35b96557	488	/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
emilmont	77:869cf507173a	489	* @{
emilmont	77:869cf507173a	490	*/
emilmont	77:869cf507173a	491	#define TIM_IT_UPDATE (TIM_DIER_UIE)
emilmont	77:869cf507173a	492	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
emilmont	77:869cf507173a	493	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
emilmont	77:869cf507173a	494	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
emilmont	77:869cf507173a	495	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
emilmont	77:869cf507173a	496	#define TIM_IT_COM (TIM_DIER_COMIE)
emilmont	77:869cf507173a	497	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
emilmont	77:869cf507173a	498	#define TIM_IT_BREAK (TIM_DIER_BIE)
emilmont	77:869cf507173a	499	/**
emilmont	77:869cf507173a	500	* @}
emilmont	77:869cf507173a	501	*/
Kojto	99:dbbf35b96557	502
Kojto	99:dbbf35b96557	503	/** @defgroup TIM_Commutation_Source TIM Commutation Source
Kojto	99:dbbf35b96557	504	* @{
Kojto	99:dbbf35b96557	505	*/
Kojto	90:cb3d968589d8	506	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
Kojto	90:cb3d968589d8	507	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
Kojto	99:dbbf35b96557	508	/**
Kojto	99:dbbf35b96557	509	* @}
Kojto	99:dbbf35b96557	510	*/
emilmont	77:869cf507173a	511
Kojto	99:dbbf35b96557	512	/** @defgroup TIM_DMA_sources TIM DMA sources
emilmont	77:869cf507173a	513	* @{
emilmont	77:869cf507173a	514	*/
emilmont	77:869cf507173a	515	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
emilmont	77:869cf507173a	516	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
emilmont	77:869cf507173a	517	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
emilmont	77:869cf507173a	518	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
emilmont	77:869cf507173a	519	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
emilmont	77:869cf507173a	520	#define TIM_DMA_COM (TIM_DIER_COMDE)
emilmont	77:869cf507173a	521	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
emilmont	77:869cf507173a	522	/**
emilmont	77:869cf507173a	523	* @}
emilmont	77:869cf507173a	524	*/
bogdanm	85:024bf7f99721	525
Kojto	99:dbbf35b96557	526	/** @defgroup TIM_Event_Source TIM Event Source
emilmont	77:869cf507173a	527	* @{
emilmont	77:869cf507173a	528	*/
Kojto	99:dbbf35b96557	529	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
Kojto	99:dbbf35b96557	530	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
Kojto	99:dbbf35b96557	531	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
Kojto	99:dbbf35b96557	532	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
Kojto	99:dbbf35b96557	533	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
Kojto	99:dbbf35b96557	534	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
Kojto	99:dbbf35b96557	535	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
Kojto	99:dbbf35b96557	536	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
Kojto	99:dbbf35b96557	537
emilmont	77:869cf507173a	538	/**
emilmont	77:869cf507173a	539	* @}
bogdanm	85:024bf7f99721	540	*/
emilmont	77:869cf507173a	541
Kojto	99:dbbf35b96557	542	/** @defgroup TIM_Flag_definition TIM Flag definition
emilmont	77:869cf507173a	543	* @{
bogdanm	85:024bf7f99721	544	*/
emilmont	77:869cf507173a	545	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
emilmont	77:869cf507173a	546	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
emilmont	77:869cf507173a	547	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
emilmont	77:869cf507173a	548	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
emilmont	77:869cf507173a	549	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
emilmont	77:869cf507173a	550	#define TIM_FLAG_COM (TIM_SR_COMIF)
emilmont	77:869cf507173a	551	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
emilmont	77:869cf507173a	552	#define TIM_FLAG_BREAK (TIM_SR_BIF)
emilmont	77:869cf507173a	553	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
emilmont	77:869cf507173a	554	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
emilmont	77:869cf507173a	555	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
emilmont	77:869cf507173a	556	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
emilmont	77:869cf507173a	557	/**
emilmont	77:869cf507173a	558	* @}
emilmont	77:869cf507173a	559	*/
emilmont	77:869cf507173a	560
Kojto	99:dbbf35b96557	561	/** @defgroup TIM_Clock_Source TIM Clock Source
emilmont	77:869cf507173a	562	* @{
bogdanm	85:024bf7f99721	563	*/
emilmont	77:869cf507173a	564	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
emilmont	77:869cf507173a	565	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
emilmont	77:869cf507173a	566	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
emilmont	77:869cf507173a	567	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
emilmont	77:869cf507173a	568	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
emilmont	77:869cf507173a	569	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
emilmont	77:869cf507173a	570	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
emilmont	77:869cf507173a	571	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
emilmont	77:869cf507173a	572	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
emilmont	77:869cf507173a	573	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
emilmont	77:869cf507173a	574	/**
emilmont	77:869cf507173a	575	* @}
bogdanm	85:024bf7f99721	576	*/
emilmont	77:869cf507173a	577
Kojto	99:dbbf35b96557	578	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
emilmont	77:869cf507173a	579	* @{
emilmont	77:869cf507173a	580	*/
emilmont	77:869cf507173a	581	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
emilmont	77:869cf507173a	582	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
emilmont	77:869cf507173a	583	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
emilmont	77:869cf507173a	584	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
emilmont	77:869cf507173a	585	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
emilmont	77:869cf507173a	586	/**
emilmont	77:869cf507173a	587	* @}
emilmont	77:869cf507173a	588	*/
bogdanm	85:024bf7f99721	589
Kojto	99:dbbf35b96557	590	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
emilmont	77:869cf507173a	591	* @{
bogdanm	85:024bf7f99721	592	*/
Kojto	99:dbbf35b96557	593	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
Kojto	99:dbbf35b96557	594	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
Kojto	99:dbbf35b96557	595	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
Kojto	99:dbbf35b96557	596	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
emilmont	77:869cf507173a	597	/**
emilmont	77:869cf507173a	598	* @}
bogdanm	85:024bf7f99721	599	*/
bogdanm	85:024bf7f99721	600
Kojto	99:dbbf35b96557	601	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
emilmont	77:869cf507173a	602	* @{
emilmont	77:869cf507173a	603	*/
emilmont	77:869cf507173a	604	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
emilmont	77:869cf507173a	605	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
emilmont	77:869cf507173a	606	/**
emilmont	77:869cf507173a	607	* @}
emilmont	77:869cf507173a	608	*/
emilmont	77:869cf507173a	609
Kojto	99:dbbf35b96557	610	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
emilmont	77:869cf507173a	611	* @{
emilmont	77:869cf507173a	612	*/
emilmont	77:869cf507173a	613	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
emilmont	77:869cf507173a	614	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
emilmont	77:869cf507173a	615	/**
emilmont	77:869cf507173a	616	* @}
bogdanm	85:024bf7f99721	617	*/
emilmont	77:869cf507173a	618
Kojto	99:dbbf35b96557	619	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
emilmont	77:869cf507173a	620	* @{
emilmont	77:869cf507173a	621	*/
emilmont	77:869cf507173a	622	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
emilmont	77:869cf507173a	623	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
emilmont	77:869cf507173a	624	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
emilmont	77:869cf507173a	625	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
emilmont	77:869cf507173a	626	/**
emilmont	77:869cf507173a	627	* @}
emilmont	77:869cf507173a	628	*/
emilmont	77:869cf507173a	629
Kojto	99:dbbf35b96557	630	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
Kojto	90:cb3d968589d8	631	* @{
Kojto	90:cb3d968589d8	632	*/
Kojto	90:cb3d968589d8	633	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
Kojto	99:dbbf35b96557	634	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
Kojto	90:cb3d968589d8	635	/**
Kojto	90:cb3d968589d8	636	* @}
Kojto	90:cb3d968589d8	637	*/
Kojto	90:cb3d968589d8	638
Kojto	99:dbbf35b96557	639	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
Kojto	90:cb3d968589d8	640	* @{
Kojto	90:cb3d968589d8	641	*/
Kojto	90:cb3d968589d8	642	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
Kojto	90:cb3d968589d8	643	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
Kojto	90:cb3d968589d8	644	/**
Kojto	90:cb3d968589d8	645	* @}
Kojto	90:cb3d968589d8	646	*/
Kojto	99:dbbf35b96557	647
Kojto	99:dbbf35b96557	648	/** @defgroup TIM_Lock_level TIM Lock level
Kojto	90:cb3d968589d8	649	* @{
Kojto	90:cb3d968589d8	650	*/
Kojto	90:cb3d968589d8	651	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
Kojto	90:cb3d968589d8	652	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
Kojto	90:cb3d968589d8	653	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
Kojto	90:cb3d968589d8	654	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
Kojto	90:cb3d968589d8	655	/**
Kojto	90:cb3d968589d8	656	* @}
Kojto	90:cb3d968589d8	657	*/
Kojto	99:dbbf35b96557	658	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
Kojto	90:cb3d968589d8	659	* @{
Kojto	90:cb3d968589d8	660	*/
Kojto	90:cb3d968589d8	661	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
Kojto	90:cb3d968589d8	662	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
Kojto	90:cb3d968589d8	663	/**
Kojto	90:cb3d968589d8	664	* @}
Kojto	90:cb3d968589d8	665	*/
Kojto	99:dbbf35b96557	666
Kojto	99:dbbf35b96557	667	/** @defgroup TIM_Break_Polarity TIM Break Polarity
Kojto	90:cb3d968589d8	668	* @{
Kojto	90:cb3d968589d8	669	*/
Kojto	90:cb3d968589d8	670	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
Kojto	90:cb3d968589d8	671	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
Kojto	90:cb3d968589d8	672	/**
Kojto	90:cb3d968589d8	673	* @}
Kojto	90:cb3d968589d8	674	*/
Kojto	99:dbbf35b96557	675
Kojto	99:dbbf35b96557	676	/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
Kojto	90:cb3d968589d8	677	* @{
Kojto	90:cb3d968589d8	678	*/
Kojto	90:cb3d968589d8	679	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
Kojto	90:cb3d968589d8	680	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
Kojto	90:cb3d968589d8	681	/**
Kojto	90:cb3d968589d8	682	* @}
Kojto	90:cb3d968589d8	683	*/
Kojto	90:cb3d968589d8	684
Kojto	99:dbbf35b96557	685	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
Kojto	90:cb3d968589d8	686	* @{
Kojto	90:cb3d968589d8	687	*/
Kojto	90:cb3d968589d8	688	#define TIM_TRGO_RESET ((uint32_t)0x0000)
Kojto	90:cb3d968589d8	689	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
Kojto	90:cb3d968589d8	690	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
Kojto	90:cb3d968589d8	691	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
Kojto	90:cb3d968589d8	692	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
Kojto	90:cb3d968589d8	693	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
Kojto	90:cb3d968589d8	694	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
Kojto	99:dbbf35b96557	695	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
Kojto	90:cb3d968589d8	696	/**
Kojto	90:cb3d968589d8	697	* @}
Kojto	90:cb3d968589d8	698	*/
Kojto	99:dbbf35b96557	699
Kojto	99:dbbf35b96557	700	/** @defgroup TIM_Slave_Mode TIM Slave Mode
emilmont	77:869cf507173a	701	* @{
emilmont	77:869cf507173a	702	*/
emilmont	77:869cf507173a	703	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
emilmont	77:869cf507173a	704	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
emilmont	77:869cf507173a	705	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
emilmont	77:869cf507173a	706	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
emilmont	77:869cf507173a	707	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
emilmont	77:869cf507173a	708	/**
emilmont	77:869cf507173a	709	* @}
emilmont	77:869cf507173a	710	*/
emilmont	77:869cf507173a	711
Kojto	99:dbbf35b96557	712	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
Kojto	90:cb3d968589d8	713	* @{
Kojto	90:cb3d968589d8	714	*/
Kojto	90:cb3d968589d8	715	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
Kojto	90:cb3d968589d8	716	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
Kojto	90:cb3d968589d8	717	/**
Kojto	90:cb3d968589d8	718	* @}
Kojto	90:cb3d968589d8	719	*/
Kojto	99:dbbf35b96557	720
Kojto	99:dbbf35b96557	721	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
emilmont	77:869cf507173a	722	* @{
emilmont	77:869cf507173a	723	*/
emilmont	77:869cf507173a	724	#define TIM_TS_ITR0 ((uint32_t)0x0000)
emilmont	77:869cf507173a	725	#define TIM_TS_ITR1 ((uint32_t)0x0010)
emilmont	77:869cf507173a	726	#define TIM_TS_ITR2 ((uint32_t)0x0020)
emilmont	77:869cf507173a	727	#define TIM_TS_ITR3 ((uint32_t)0x0030)
emilmont	77:869cf507173a	728	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
emilmont	77:869cf507173a	729	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
emilmont	77:869cf507173a	730	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
emilmont	77:869cf507173a	731	#define TIM_TS_ETRF ((uint32_t)0x0070)
emilmont	77:869cf507173a	732	#define TIM_TS_NONE ((uint32_t)0xFFFF)
emilmont	77:869cf507173a	733	/**
emilmont	77:869cf507173a	734	* @}
emilmont	77:869cf507173a	735	*/
emilmont	77:869cf507173a	736
Kojto	99:dbbf35b96557	737	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
emilmont	77:869cf507173a	738	* @{
emilmont	77:869cf507173a	739	*/
emilmont	77:869cf507173a	740	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
emilmont	77:869cf507173a	741	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
emilmont	77:869cf507173a	742	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
emilmont	77:869cf507173a	743	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
emilmont	77:869cf507173a	744	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
emilmont	77:869cf507173a	745	/**
emilmont	77:869cf507173a	746	* @}
emilmont	77:869cf507173a	747	*/
emilmont	77:869cf507173a	748
Kojto	99:dbbf35b96557	749	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
emilmont	77:869cf507173a	750	* @{
bogdanm	85:024bf7f99721	751	*/
emilmont	77:869cf507173a	752	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
emilmont	77:869cf507173a	753	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
emilmont	77:869cf507173a	754	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
emilmont	77:869cf507173a	755	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
emilmont	77:869cf507173a	756	/**
emilmont	77:869cf507173a	757	* @}
emilmont	77:869cf507173a	758	*/
emilmont	77:869cf507173a	759
emilmont	77:869cf507173a	760
Kojto	99:dbbf35b96557	761	/** @defgroup TIM_TI1_Selection TIM TI1 Selection
emilmont	77:869cf507173a	762	* @{
emilmont	77:869cf507173a	763	*/
emilmont	77:869cf507173a	764	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
emilmont	77:869cf507173a	765	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
emilmont	77:869cf507173a	766	/**
emilmont	77:869cf507173a	767	* @}
emilmont	77:869cf507173a	768	*/
bogdanm	85:024bf7f99721	769
Kojto	99:dbbf35b96557	770	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
emilmont	77:869cf507173a	771	* @{
emilmont	77:869cf507173a	772	*/
Kojto	99:dbbf35b96557	773	#define TIM_DMABASE_CR1 (0x00000000)
Kojto	99:dbbf35b96557	774	#define TIM_DMABASE_CR2 (0x00000001)
Kojto	99:dbbf35b96557	775	#define TIM_DMABASE_SMCR (0x00000002)
Kojto	99:dbbf35b96557	776	#define TIM_DMABASE_DIER (0x00000003)
Kojto	99:dbbf35b96557	777	#define TIM_DMABASE_SR (0x00000004)
Kojto	99:dbbf35b96557	778	#define TIM_DMABASE_EGR (0x00000005)
Kojto	99:dbbf35b96557	779	#define TIM_DMABASE_CCMR1 (0x00000006)
Kojto	99:dbbf35b96557	780	#define TIM_DMABASE_CCMR2 (0x00000007)
Kojto	99:dbbf35b96557	781	#define TIM_DMABASE_CCER (0x00000008)
Kojto	99:dbbf35b96557	782	#define TIM_DMABASE_CNT (0x00000009)
Kojto	99:dbbf35b96557	783	#define TIM_DMABASE_PSC (0x0000000A)
Kojto	99:dbbf35b96557	784	#define TIM_DMABASE_ARR (0x0000000B)
Kojto	99:dbbf35b96557	785	#define TIM_DMABASE_RCR (0x0000000C)
Kojto	99:dbbf35b96557	786	#define TIM_DMABASE_CCR1 (0x0000000D)
Kojto	99:dbbf35b96557	787	#define TIM_DMABASE_CCR2 (0x0000000E)
Kojto	99:dbbf35b96557	788	#define TIM_DMABASE_CCR3 (0x0000000F)
Kojto	99:dbbf35b96557	789	#define TIM_DMABASE_CCR4 (0x00000010)
Kojto	99:dbbf35b96557	790	#define TIM_DMABASE_BDTR (0x00000011)
Kojto	99:dbbf35b96557	791	#define TIM_DMABASE_DCR (0x00000012)
Kojto	99:dbbf35b96557	792	#define TIM_DMABASE_OR (0x00000013)
emilmont	77:869cf507173a	793	/**
emilmont	77:869cf507173a	794	* @}
emilmont	77:869cf507173a	795	*/
emilmont	77:869cf507173a	796
Kojto	99:dbbf35b96557	797	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
emilmont	77:869cf507173a	798	* @{
emilmont	77:869cf507173a	799	*/
Kojto	99:dbbf35b96557	800	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
Kojto	99:dbbf35b96557	801	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
Kojto	99:dbbf35b96557	802	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
Kojto	99:dbbf35b96557	803	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
Kojto	99:dbbf35b96557	804	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
Kojto	99:dbbf35b96557	805	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
Kojto	99:dbbf35b96557	806	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
Kojto	99:dbbf35b96557	807	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
Kojto	99:dbbf35b96557	808	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
Kojto	99:dbbf35b96557	809	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
Kojto	99:dbbf35b96557	810	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
Kojto	99:dbbf35b96557	811	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
Kojto	99:dbbf35b96557	812	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
Kojto	99:dbbf35b96557	813	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
Kojto	99:dbbf35b96557	814	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
Kojto	99:dbbf35b96557	815	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
Kojto	99:dbbf35b96557	816	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
Kojto	99:dbbf35b96557	817	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
emilmont	77:869cf507173a	818	/**
emilmont	77:869cf507173a	819	* @}
bogdanm	85:024bf7f99721	820	*/
bogdanm	85:024bf7f99721	821
Kojto	99:dbbf35b96557	822	/** @defgroup DMA_Handle_index DMA Handle index
emilmont	77:869cf507173a	823	* @{
emilmont	77:869cf507173a	824	*/
emilmont	77:869cf507173a	825	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
emilmont	77:869cf507173a	826	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
emilmont	77:869cf507173a	827	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
emilmont	77:869cf507173a	828	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
emilmont	77:869cf507173a	829	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
emilmont	77:869cf507173a	830	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
emilmont	77:869cf507173a	831	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
emilmont	77:869cf507173a	832	/**
emilmont	77:869cf507173a	833	* @}
emilmont	77:869cf507173a	834	*/
emilmont	77:869cf507173a	835
Kojto	99:dbbf35b96557	836	/** @defgroup Channel_CC_State Channel CC State
emilmont	77:869cf507173a	837	* @{
emilmont	77:869cf507173a	838	*/
emilmont	77:869cf507173a	839	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
emilmont	77:869cf507173a	840	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
emilmont	77:869cf507173a	841	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
emilmont	77:869cf507173a	842	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
emilmont	77:869cf507173a	843	/**
emilmont	77:869cf507173a	844	* @}
emilmont	77:869cf507173a	845	*/
emilmont	77:869cf507173a	846
emilmont	77:869cf507173a	847	/**
emilmont	77:869cf507173a	848	* @}
emilmont	77:869cf507173a	849	*/
emilmont	77:869cf507173a	850
emilmont	77:869cf507173a	851	/* Exported macro ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	852	/** @defgroup TIM_Exported_Macros TIM Exported Macros
Kojto	99:dbbf35b96557	853	* @{
Kojto	99:dbbf35b96557	854	*/
bogdanm	85:024bf7f99721	855	/** @brief Reset TIM handle state
bogdanm	85:024bf7f99721	856	* @param __HANDLE__: TIM handle
bogdanm	85:024bf7f99721	857	* @retval None
bogdanm	85:024bf7f99721	858	*/
bogdanm	85:024bf7f99721	859	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	85:024bf7f99721	860
emilmont	77:869cf507173a	861	/**
emilmont	77:869cf507173a	862	* @brief Enable the TIM peripheral.
emilmont	77:869cf507173a	863	* @param __HANDLE__: TIM handle
emilmont	77:869cf507173a	864	* @retval None
emilmont	77:869cf507173a	865	*/
emilmont	77:869cf507173a	866	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
emilmont	77:869cf507173a	867
emilmont	77:869cf507173a	868	/**
emilmont	77:869cf507173a	869	* @brief Enable the TIM main Output.
emilmont	77:869cf507173a	870	* @param __HANDLE__: TIM handle
emilmont	77:869cf507173a	871	* @retval None
emilmont	77:869cf507173a	872	*/
emilmont	77:869cf507173a	873	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
emilmont	77:869cf507173a	874
emilmont	77:869cf507173a	875
emilmont	77:869cf507173a	876	/**
emilmont	77:869cf507173a	877	* @brief Disable the TIM peripheral.
emilmont	77:869cf507173a	878	* @param __HANDLE__: TIM handle
emilmont	77:869cf507173a	879	* @retval None
emilmont	77:869cf507173a	880	*/
emilmont	77:869cf507173a	881	#define __HAL_TIM_DISABLE(__HANDLE__) \
emilmont	77:869cf507173a	882	do { \
Kojto	99:dbbf35b96557	883	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
emilmont	77:869cf507173a	884	{ \
Kojto	99:dbbf35b96557	885	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
emilmont	77:869cf507173a	886	{ \
emilmont	77:869cf507173a	887	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
emilmont	77:869cf507173a	888	} \
emilmont	77:869cf507173a	889	} \
emilmont	77:869cf507173a	890	} while(0)
emilmont	77:869cf507173a	891
bogdanm	85:024bf7f99721	892	/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
bogdanm	85:024bf7f99721	893	channels have been disabled */
emilmont	77:869cf507173a	894	/**
emilmont	77:869cf507173a	895	* @brief Disable the TIM main Output.
emilmont	77:869cf507173a	896	* @param __HANDLE__: TIM handle
emilmont	77:869cf507173a	897	* @retval None
emilmont	77:869cf507173a	898	*/
emilmont	77:869cf507173a	899	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
emilmont	77:869cf507173a	900	do { \
Kojto	99:dbbf35b96557	901	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
emilmont	77:869cf507173a	902	{ \
Kojto	99:dbbf35b96557	903	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
emilmont	77:869cf507173a	904	{ \
emilmont	77:869cf507173a	905	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
emilmont	77:869cf507173a	906	} \
emilmont	77:869cf507173a	907	} \
bogdanm	85:024bf7f99721	908	} while(0)
emilmont	77:869cf507173a	909
emilmont	77:869cf507173a	910	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
emilmont	77:869cf507173a	911	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
emilmont	77:869cf507173a	912	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	913	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
emilmont	77:869cf507173a	914	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Kojto	90:cb3d968589d8	915	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
emilmont	77:869cf507173a	916
Kojto	99:dbbf35b96557	917	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Kojto	90:cb3d968589d8	918	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
emilmont	77:869cf507173a	919
Kojto	99:dbbf35b96557	920	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Kojto	99:dbbf35b96557	921	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
emilmont	77:869cf507173a	922
Kojto	99:dbbf35b96557	923	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
emilmont	77:869cf507173a	924	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
emilmont	77:869cf507173a	925	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
emilmont	77:869cf507173a	926	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
emilmont	77:869cf507173a	927	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
emilmont	77:869cf507173a	928
Kojto	99:dbbf35b96557	929	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
emilmont	77:869cf507173a	930	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
emilmont	77:869cf507173a	931	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
emilmont	77:869cf507173a	932	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
emilmont	77:869cf507173a	933	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm	85:024bf7f99721	934
Kojto	99:dbbf35b96557	935	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
Kojto	99:dbbf35b96557	936	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
Kojto	99:dbbf35b96557	937	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
Kojto	99:dbbf35b96557	938	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
Kojto	99:dbbf35b96557	939	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
Kojto	99:dbbf35b96557	940
Kojto	99:dbbf35b96557	941	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
Kojto	99:dbbf35b96557	942	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
Kojto	99:dbbf35b96557	943	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
Kojto	99:dbbf35b96557	944	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
Kojto	99:dbbf35b96557	945	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
Kojto	99:dbbf35b96557	946
emilmont	77:869cf507173a	947	/**
emilmont	77:869cf507173a	948	* @brief Sets the TIM Capture Compare Register value on runtime without
emilmont	77:869cf507173a	949	* calling another time ConfigChannel function.
emilmont	77:869cf507173a	950	* @param __HANDLE__: TIM handle.
emilmont	77:869cf507173a	951	* @param __CHANNEL__ : TIM Channels to be configured.
emilmont	77:869cf507173a	952	* This parameter can be one of the following values:
emilmont	77:869cf507173a	953	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
emilmont	77:869cf507173a	954	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
emilmont	77:869cf507173a	955	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
emilmont	77:869cf507173a	956	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
emilmont	77:869cf507173a	957	* @param __COMPARE__: specifies the Capture Compare register new value.
emilmont	77:869cf507173a	958	* @retval None
emilmont	77:869cf507173a	959	*/
Kojto	99:dbbf35b96557	960	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
emilmont	77:869cf507173a	961	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
emilmont	77:869cf507173a	962
emilmont	77:869cf507173a	963	/**
bogdanm	85:024bf7f99721	964	* @brief Gets the TIM Capture Compare Register value on runtime
bogdanm	85:024bf7f99721	965	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	966	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm	85:024bf7f99721	967	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	968	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	85:024bf7f99721	969	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	85:024bf7f99721	970	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	85:024bf7f99721	971	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	85:024bf7f99721	972	* @retval None
bogdanm	85:024bf7f99721	973	*/
Kojto	99:dbbf35b96557	974	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
bogdanm	85:024bf7f99721	975	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm	85:024bf7f99721	976
bogdanm	85:024bf7f99721	977	/**
emilmont	77:869cf507173a	978	* @brief Sets the TIM Counter Register value on runtime.
emilmont	77:869cf507173a	979	* @param __HANDLE__: TIM handle.
emilmont	77:869cf507173a	980	* @param __COUNTER__: specifies the Counter register new value.
emilmont	77:869cf507173a	981	* @retval None
emilmont	77:869cf507173a	982	*/
Kojto	99:dbbf35b96557	983	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	85:024bf7f99721	984
bogdanm	85:024bf7f99721	985	/**
bogdanm	85:024bf7f99721	986	* @brief Gets the TIM Counter Register value on runtime.
bogdanm	85:024bf7f99721	987	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	988	* @retval None
bogdanm	85:024bf7f99721	989	*/
Kojto	99:dbbf35b96557	990	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
emilmont	77:869cf507173a	991
emilmont	77:869cf507173a	992	/**
emilmont	77:869cf507173a	993	* @brief Sets the TIM Autoreload Register value on runtime without calling
emilmont	77:869cf507173a	994	* another time any Init function.
emilmont	77:869cf507173a	995	* @param __HANDLE__: TIM handle.
emilmont	77:869cf507173a	996	* @param __AUTORELOAD__: specifies the Counter register new value.
emilmont	77:869cf507173a	997	* @retval None
emilmont	77:869cf507173a	998	*/
Kojto	99:dbbf35b96557	999	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
bogdanm	85:024bf7f99721	1000	do{ \
bogdanm	85:024bf7f99721	1001	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	85:024bf7f99721	1002	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
emilmont	77:869cf507173a	1003	} while(0)
bogdanm	85:024bf7f99721	1004	/**
bogdanm	85:024bf7f99721	1005	* @brief Gets the TIM Autoreload Register value on runtime
bogdanm	85:024bf7f99721	1006	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1007	* @retval None
bogdanm	85:024bf7f99721	1008	*/
Kojto	99:dbbf35b96557	1009	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
emilmont	77:869cf507173a	1010
emilmont	77:869cf507173a	1011	/**
emilmont	77:869cf507173a	1012	* @brief Sets the TIM Clock Division value on runtime without calling
emilmont	77:869cf507173a	1013	* another time any Init function.
emilmont	77:869cf507173a	1014	* @param __HANDLE__: TIM handle.
emilmont	77:869cf507173a	1015	* @param __CKD__: specifies the clock division value.
emilmont	77:869cf507173a	1016	* This parameter can be one of the following value:
emilmont	77:869cf507173a	1017	* @arg TIM_CLOCKDIVISION_DIV1
emilmont	77:869cf507173a	1018	* @arg TIM_CLOCKDIVISION_DIV2
bogdanm	85:024bf7f99721	1019	* @arg TIM_CLOCKDIVISION_DIV4
emilmont	77:869cf507173a	1020	* @retval None
emilmont	77:869cf507173a	1021	*/
Kojto	99:dbbf35b96557	1022	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
bogdanm	85:024bf7f99721	1023	do{ \
emilmont	77:869cf507173a	1024	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm	85:024bf7f99721	1025	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
emilmont	77:869cf507173a	1026	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
emilmont	77:869cf507173a	1027	} while(0)
bogdanm	85:024bf7f99721	1028	/**
bogdanm	85:024bf7f99721	1029	* @brief Gets the TIM Clock Division value on runtime
bogdanm	85:024bf7f99721	1030	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1031	* @retval None
bogdanm	85:024bf7f99721	1032	*/
Kojto	99:dbbf35b96557	1033	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm	85:024bf7f99721	1034
emilmont	77:869cf507173a	1035	/**
emilmont	77:869cf507173a	1036	* @brief Sets the TIM Input Capture prescaler on runtime without calling
emilmont	77:869cf507173a	1037	* another time HAL_TIM_IC_ConfigChannel() function.
emilmont	77:869cf507173a	1038	* @param __HANDLE__: TIM handle.
emilmont	77:869cf507173a	1039	* @param __CHANNEL__ : TIM Channels to be configured.
emilmont	77:869cf507173a	1040	* This parameter can be one of the following values:
emilmont	77:869cf507173a	1041	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
emilmont	77:869cf507173a	1042	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
emilmont	77:869cf507173a	1043	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
emilmont	77:869cf507173a	1044	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
emilmont	77:869cf507173a	1045	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
emilmont	77:869cf507173a	1046	* This parameter can be one of the following values:
emilmont	77:869cf507173a	1047	* @arg TIM_ICPSC_DIV1: no prescaler
emilmont	77:869cf507173a	1048	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
emilmont	77:869cf507173a	1049	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
emilmont	77:869cf507173a	1050	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
emilmont	77:869cf507173a	1051	* @retval None
emilmont	77:869cf507173a	1052	*/
Kojto	99:dbbf35b96557	1053	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
emilmont	77:869cf507173a	1054	do{ \
Kojto	99:dbbf35b96557	1055	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
Kojto	99:dbbf35b96557	1056	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm	85:024bf7f99721	1057	} while(0)
emilmont	77:869cf507173a	1058
emilmont	77:869cf507173a	1059	/**
bogdanm	85:024bf7f99721	1060	* @brief Gets the TIM Input Capture prescaler on runtime
bogdanm	85:024bf7f99721	1061	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1062	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	85:024bf7f99721	1063	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1064	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	85:024bf7f99721	1065	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	85:024bf7f99721	1066	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	85:024bf7f99721	1067	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	85:024bf7f99721	1068	* @retval None
bogdanm	85:024bf7f99721	1069	*/
Kojto	99:dbbf35b96557	1070	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
bogdanm	85:024bf7f99721	1071	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm	85:024bf7f99721	1072	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm	85:024bf7f99721	1073	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm	85:024bf7f99721	1074	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
Kojto	99:dbbf35b96557	1075
Kojto	99:dbbf35b96557	1076	/**
Kojto	99:dbbf35b96557	1077	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
Kojto	99:dbbf35b96557	1078	* @param __HANDLE__: TIM handle.
Kojto	99:dbbf35b96557	1079	* @note When the USR bit of the TIMx_CR1 register is set, only counter
Kojto	99:dbbf35b96557	1080	* overflow/underflow generates an update interrupt or DMA request (if
Kojto	99:dbbf35b96557	1081	* enabled)
Kojto	99:dbbf35b96557	1082	* @retval None
Kojto	99:dbbf35b96557	1083	*/
Kojto	99:dbbf35b96557	1084	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
Kojto	99:dbbf35b96557	1085	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
Kojto	99:dbbf35b96557	1086
Kojto	99:dbbf35b96557	1087	/**
Kojto	99:dbbf35b96557	1088	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
Kojto	99:dbbf35b96557	1089	* @param __HANDLE__: TIM handle.
Kojto	99:dbbf35b96557	1090	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
Kojto	99:dbbf35b96557	1091	* following events generate an update interrupt or DMA request (if
Kojto	99:dbbf35b96557	1092	* enabled):
Kojto	99:dbbf35b96557	1093	* Counter overflow/underflow
Kojto	99:dbbf35b96557	1094	* Setting the UG bit
Kojto	99:dbbf35b96557	1095	* Update generation through the slave mode controller
Kojto	99:dbbf35b96557	1096	* @retval None
Kojto	99:dbbf35b96557	1097	*/
Kojto	99:dbbf35b96557	1098	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
Kojto	99:dbbf35b96557	1099	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Kojto	99:dbbf35b96557	1100
Kojto	99:dbbf35b96557	1101	/**
Kojto	99:dbbf35b96557	1102	* @brief Sets the TIM Capture x input polarity on runtime.
Kojto	99:dbbf35b96557	1103	* @param __HANDLE__: TIM handle.
Kojto	99:dbbf35b96557	1104	* @param __CHANNEL__: TIM Channels to be configured.
Kojto	99:dbbf35b96557	1105	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	1106	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
Kojto	99:dbbf35b96557	1107	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
Kojto	99:dbbf35b96557	1108	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
Kojto	99:dbbf35b96557	1109	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
Kojto	99:dbbf35b96557	1110	* @param __POLARITY__: Polarity for TIx source
Kojto	99:dbbf35b96557	1111	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
Kojto	99:dbbf35b96557	1112	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
Kojto	99:dbbf35b96557	1113	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Kojto	99:dbbf35b96557	1114	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
Kojto	99:dbbf35b96557	1115	* @retval None
Kojto	99:dbbf35b96557	1116	*/
Kojto	99:dbbf35b96557	1117	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
Kojto	99:dbbf35b96557	1118	do{ \
Kojto	99:dbbf35b96557	1119	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
Kojto	99:dbbf35b96557	1120	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
Kojto	99:dbbf35b96557	1121	}while(0)
bogdanm	85:024bf7f99721	1122	/**
emilmont	77:869cf507173a	1123	* @}
emilmont	77:869cf507173a	1124	*/
emilmont	77:869cf507173a	1125
emilmont	77:869cf507173a	1126	/* Include TIM HAL Extension module */
emilmont	77:869cf507173a	1127	#include "stm32f4xx_hal_tim_ex.h"
emilmont	77:869cf507173a	1128
emilmont	77:869cf507173a	1129	/* Exported functions --------------------------------------------------------*/
Kojto	99:dbbf35b96557	1130	/** @addtogroup TIM_Exported_Functions
Kojto	99:dbbf35b96557	1131	* @{
Kojto	99:dbbf35b96557	1132	*/
Kojto	99:dbbf35b96557	1133
Kojto	99:dbbf35b96557	1134	/** @addtogroup TIM_Exported_Functions_Group1
Kojto	99:dbbf35b96557	1135	* @{
Kojto	99:dbbf35b96557	1136	*/
emilmont	77:869cf507173a	1137
emilmont	77:869cf507173a	1138	/* Time Base functions ********************************************************/
emilmont	77:869cf507173a	1139	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1140	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1141	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1142	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1143	/* Blocking mode: Polling */
emilmont	77:869cf507173a	1144	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1145	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1146	/* Non-Blocking mode: Interrupt */
emilmont	77:869cf507173a	1147	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1148	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1149	/* Non-Blocking mode: DMA */
emilmont	77:869cf507173a	1150	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
emilmont	77:869cf507173a	1151	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
Kojto	99:dbbf35b96557	1152	/**
Kojto	99:dbbf35b96557	1153	* @}
Kojto	99:dbbf35b96557	1154	*/
emilmont	77:869cf507173a	1155
Kojto	99:dbbf35b96557	1156	/** @addtogroup TIM_Exported_Functions_Group2
Kojto	99:dbbf35b96557	1157	* @{
Kojto	99:dbbf35b96557	1158	*/
emilmont	77:869cf507173a	1159	/* Timer Output Compare functions **********************************************/
emilmont	77:869cf507173a	1160	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1161	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1162	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1163	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1164	/* Blocking mode: Polling */
emilmont	77:869cf507173a	1165	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1166	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1167	/* Non-Blocking mode: Interrupt */
emilmont	77:869cf507173a	1168	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1169	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1170	/* Non-Blocking mode: DMA */
emilmont	77:869cf507173a	1171	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
emilmont	77:869cf507173a	1172	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1173
Kojto	99:dbbf35b96557	1174	/**
Kojto	99:dbbf35b96557	1175	* @}
Kojto	99:dbbf35b96557	1176	*/
Kojto	99:dbbf35b96557	1177
Kojto	99:dbbf35b96557	1178	/** @addtogroup TIM_Exported_Functions_Group3
Kojto	99:dbbf35b96557	1179	* @{
Kojto	99:dbbf35b96557	1180	*/
emilmont	77:869cf507173a	1181	/* Timer PWM functions *********************************************************/
emilmont	77:869cf507173a	1182	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1183	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1184	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1185	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1186	/* Blocking mode: Polling */
emilmont	77:869cf507173a	1187	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1188	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1189	/* Non-Blocking mode: Interrupt */
emilmont	77:869cf507173a	1190	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1191	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1192	/* Non-Blocking mode: DMA */
emilmont	77:869cf507173a	1193	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
emilmont	77:869cf507173a	1194	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1195
Kojto	99:dbbf35b96557	1196	/**
Kojto	99:dbbf35b96557	1197	* @}
Kojto	99:dbbf35b96557	1198	*/
Kojto	99:dbbf35b96557	1199
Kojto	99:dbbf35b96557	1200	/** @addtogroup TIM_Exported_Functions_Group4
Kojto	99:dbbf35b96557	1201	* @{
Kojto	99:dbbf35b96557	1202	*/
emilmont	77:869cf507173a	1203	/* Timer Input Capture functions ***********************************************/
emilmont	77:869cf507173a	1204	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1205	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1206	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1207	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1208	/* Blocking mode: Polling */
emilmont	77:869cf507173a	1209	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1210	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1211	/* Non-Blocking mode: Interrupt */
emilmont	77:869cf507173a	1212	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1213	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1214	/* Non-Blocking mode: DMA */
emilmont	77:869cf507173a	1215	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
emilmont	77:869cf507173a	1216	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1217
Kojto	99:dbbf35b96557	1218	/**
Kojto	99:dbbf35b96557	1219	* @}
Kojto	99:dbbf35b96557	1220	*/
Kojto	99:dbbf35b96557	1221
Kojto	99:dbbf35b96557	1222	/** @addtogroup TIM_Exported_Functions_Group5
Kojto	99:dbbf35b96557	1223	* @{
Kojto	99:dbbf35b96557	1224	*/
emilmont	77:869cf507173a	1225	/* Timer One Pulse functions ***************************************************/
emilmont	77:869cf507173a	1226	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
emilmont	77:869cf507173a	1227	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1228	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1229	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1230	/* Blocking mode: Polling */
emilmont	77:869cf507173a	1231	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
emilmont	77:869cf507173a	1232	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
emilmont	77:869cf507173a	1233
emilmont	77:869cf507173a	1234	/* Non-Blocking mode: Interrupt */
emilmont	77:869cf507173a	1235	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
emilmont	77:869cf507173a	1236	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
emilmont	77:869cf507173a	1237
Kojto	99:dbbf35b96557	1238	/**
Kojto	99:dbbf35b96557	1239	* @}
Kojto	99:dbbf35b96557	1240	*/
Kojto	99:dbbf35b96557	1241
Kojto	99:dbbf35b96557	1242	/** @addtogroup TIM_Exported_Functions_Group6
Kojto	99:dbbf35b96557	1243	* @{
Kojto	99:dbbf35b96557	1244	*/
emilmont	77:869cf507173a	1245	/* Timer Encoder functions *****************************************************/
emilmont	77:869cf507173a	1246	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
emilmont	77:869cf507173a	1247	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1248	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1249	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1250	/* Blocking mode: Polling */
emilmont	77:869cf507173a	1251	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1252	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1253	/* Non-Blocking mode: Interrupt */
emilmont	77:869cf507173a	1254	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1255	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1256	/* Non-Blocking mode: DMA */
emilmont	77:869cf507173a	1257	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
emilmont	77:869cf507173a	1258	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1259
Kojto	99:dbbf35b96557	1260	/**
Kojto	99:dbbf35b96557	1261	* @}
Kojto	99:dbbf35b96557	1262	*/
Kojto	99:dbbf35b96557	1263
Kojto	99:dbbf35b96557	1264	/** @addtogroup TIM_Exported_Functions_Group7
Kojto	99:dbbf35b96557	1265	* @{
Kojto	99:dbbf35b96557	1266	*/
emilmont	77:869cf507173a	1267	/* Interrupt Handler functions **********************************************/
emilmont	77:869cf507173a	1268	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1269
Kojto	99:dbbf35b96557	1270	/**
Kojto	99:dbbf35b96557	1271	* @}
Kojto	99:dbbf35b96557	1272	*/
Kojto	99:dbbf35b96557	1273
Kojto	99:dbbf35b96557	1274	/** @addtogroup TIM_Exported_Functions_Group8
Kojto	99:dbbf35b96557	1275	* @{
Kojto	99:dbbf35b96557	1276	*/
emilmont	77:869cf507173a	1277	/* Control functions *********************************************************/
emilmont	77:869cf507173a	1278	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
emilmont	77:869cf507173a	1279	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
emilmont	77:869cf507173a	1280	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
emilmont	77:869cf507173a	1281	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
emilmont	77:869cf507173a	1282	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
emilmont	77:869cf507173a	1283	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
emilmont	77:869cf507173a	1284	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
emilmont	77:869cf507173a	1285	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
Kojto	99:dbbf35b96557	1286	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
emilmont	77:869cf507173a	1287	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
emilmont	77:869cf507173a	1288	uint32_t *BurstBuffer, uint32_t BurstLength);
emilmont	77:869cf507173a	1289	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
emilmont	77:869cf507173a	1290	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
emilmont	77:869cf507173a	1291	uint32_t *BurstBuffer, uint32_t BurstLength);
emilmont	77:869cf507173a	1292	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
emilmont	77:869cf507173a	1293	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
emilmont	77:869cf507173a	1294	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
emilmont	77:869cf507173a	1295
Kojto	99:dbbf35b96557	1296	/**
Kojto	99:dbbf35b96557	1297	* @}
Kojto	99:dbbf35b96557	1298	*/
Kojto	99:dbbf35b96557	1299
Kojto	99:dbbf35b96557	1300	/** @addtogroup TIM_Exported_Functions_Group9
Kojto	99:dbbf35b96557	1301	* @{
Kojto	99:dbbf35b96557	1302	*/
emilmont	77:869cf507173a	1303	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	81:7d30d6019079	1304	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	81:7d30d6019079	1305	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	81:7d30d6019079	1306	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	81:7d30d6019079	1307	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	81:7d30d6019079	1308	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	81:7d30d6019079	1309	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1310
Kojto	99:dbbf35b96557	1311	/**
Kojto	99:dbbf35b96557	1312	* @}
Kojto	99:dbbf35b96557	1313	*/
Kojto	99:dbbf35b96557	1314
Kojto	99:dbbf35b96557	1315	/** @addtogroup TIM_Exported_Functions_Group10
Kojto	99:dbbf35b96557	1316	* @{
Kojto	99:dbbf35b96557	1317	*/
emilmont	77:869cf507173a	1318	/* Peripheral State functions **************************************************/
emilmont	77:869cf507173a	1319	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1320	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1321	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1322	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1323	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1324	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
emilmont	77:869cf507173a	1325
Kojto	99:dbbf35b96557	1326	/**
Kojto	99:dbbf35b96557	1327	* @}
Kojto	99:dbbf35b96557	1328	*/
Kojto	99:dbbf35b96557	1329
Kojto	99:dbbf35b96557	1330	/**
Kojto	99:dbbf35b96557	1331	* @}
Kojto	99:dbbf35b96557	1332	*/
Kojto	99:dbbf35b96557	1333
Kojto	99:dbbf35b96557	1334	/* Private macros ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	1335	/** @defgroup TIM_Private_Macros TIM Private Macros
Kojto	99:dbbf35b96557	1336	* @{
Kojto	99:dbbf35b96557	1337	*/
Kojto	99:dbbf35b96557	1338
Kojto	99:dbbf35b96557	1339	/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
Kojto	99:dbbf35b96557	1340	* @{
Kojto	99:dbbf35b96557	1341	*/
Kojto	99:dbbf35b96557	1342	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
Kojto	99:dbbf35b96557	1343	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
Kojto	99:dbbf35b96557	1344	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
Kojto	99:dbbf35b96557	1345	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
Kojto	99:dbbf35b96557	1346	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
Kojto	99:dbbf35b96557	1347
Kojto	99:dbbf35b96557	1348	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
Kojto	99:dbbf35b96557	1349	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
Kojto	99:dbbf35b96557	1350	((DIV) == TIM_CLOCKDIVISION_DIV4))
Kojto	99:dbbf35b96557	1351
Kojto	99:dbbf35b96557	1352	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
Kojto	99:dbbf35b96557	1353	((MODE) == TIM_OCMODE_PWM2))
Kojto	99:dbbf35b96557	1354
Kojto	99:dbbf35b96557	1355	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
Kojto	99:dbbf35b96557	1356	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
Kojto	99:dbbf35b96557	1357	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
Kojto	99:dbbf35b96557	1358	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
Kojto	99:dbbf35b96557	1359	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
Kojto	99:dbbf35b96557	1360	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
Kojto	99:dbbf35b96557	1361
Kojto	99:dbbf35b96557	1362	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1363	((STATE) == TIM_OCFAST_ENABLE))
Kojto	99:dbbf35b96557	1364
Kojto	99:dbbf35b96557	1365	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
Kojto	99:dbbf35b96557	1366	((POLARITY) == TIM_OCPOLARITY_LOW))
Kojto	99:dbbf35b96557	1367
Kojto	99:dbbf35b96557	1368	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
Kojto	99:dbbf35b96557	1369	((POLARITY) == TIM_OCNPOLARITY_LOW))
Kojto	99:dbbf35b96557	1370
Kojto	99:dbbf35b96557	1371	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
Kojto	99:dbbf35b96557	1372	((STATE) == TIM_OCIDLESTATE_RESET))
Kojto	99:dbbf35b96557	1373
Kojto	99:dbbf35b96557	1374	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
Kojto	99:dbbf35b96557	1375	((STATE) == TIM_OCNIDLESTATE_RESET))
Kojto	99:dbbf35b96557	1376
Kojto	99:dbbf35b96557	1377	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	99:dbbf35b96557	1378	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	99:dbbf35b96557	1379	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	99:dbbf35b96557	1380	((CHANNEL) == TIM_CHANNEL_4) \|\| \
Kojto	99:dbbf35b96557	1381	((CHANNEL) == TIM_CHANNEL_ALL))
Kojto	99:dbbf35b96557	1382
Kojto	99:dbbf35b96557	1383	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	99:dbbf35b96557	1384	((CHANNEL) == TIM_CHANNEL_2))
Kojto	99:dbbf35b96557	1385
Kojto	99:dbbf35b96557	1386	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	99:dbbf35b96557	1387	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	99:dbbf35b96557	1388	((CHANNEL) == TIM_CHANNEL_3))
Kojto	99:dbbf35b96557	1389
Kojto	99:dbbf35b96557	1390	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
Kojto	99:dbbf35b96557	1391	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
Kojto	99:dbbf35b96557	1392	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
Kojto	99:dbbf35b96557	1393
Kojto	99:dbbf35b96557	1394	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
Kojto	99:dbbf35b96557	1395	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
Kojto	99:dbbf35b96557	1396	((SELECTION) == TIM_ICSELECTION_TRC))
Kojto	99:dbbf35b96557	1397
Kojto	99:dbbf35b96557	1398	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
Kojto	99:dbbf35b96557	1399	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
Kojto	99:dbbf35b96557	1400	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
Kojto	99:dbbf35b96557	1401	((PRESCALER) == TIM_ICPSC_DIV8))
Kojto	99:dbbf35b96557	1402
Kojto	99:dbbf35b96557	1403	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
Kojto	99:dbbf35b96557	1404	((MODE) == TIM_OPMODE_REPETITIVE))
Kojto	99:dbbf35b96557	1405
Kojto	99:dbbf35b96557	1406	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
Kojto	99:dbbf35b96557	1407
Kojto	99:dbbf35b96557	1408	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
Kojto	99:dbbf35b96557	1409	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
Kojto	99:dbbf35b96557	1410	((MODE) == TIM_ENCODERMODE_TI12))
Kojto	99:dbbf35b96557	1411
Kojto	99:dbbf35b96557	1412	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
Kojto	99:dbbf35b96557	1413
Kojto	99:dbbf35b96557	1414	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
Kojto	99:dbbf35b96557	1415	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
Kojto	99:dbbf35b96557	1416	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
Kojto	99:dbbf35b96557	1417	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
Kojto	99:dbbf35b96557	1418	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
Kojto	99:dbbf35b96557	1419	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
Kojto	99:dbbf35b96557	1420	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
Kojto	99:dbbf35b96557	1421	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
Kojto	99:dbbf35b96557	1422	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
Kojto	99:dbbf35b96557	1423	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
Kojto	99:dbbf35b96557	1424
Kojto	99:dbbf35b96557	1425	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
Kojto	99:dbbf35b96557	1426	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
Kojto	99:dbbf35b96557	1427	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
Kojto	99:dbbf35b96557	1428	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
Kojto	99:dbbf35b96557	1429	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
Kojto	99:dbbf35b96557	1430
Kojto	99:dbbf35b96557	1431	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
Kojto	99:dbbf35b96557	1432	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
Kojto	99:dbbf35b96557	1433	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
Kojto	99:dbbf35b96557	1434	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
Kojto	99:dbbf35b96557	1435
Kojto	99:dbbf35b96557	1436	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
Kojto	99:dbbf35b96557	1437
Kojto	99:dbbf35b96557	1438	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
Kojto	99:dbbf35b96557	1439	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
Kojto	99:dbbf35b96557	1440
Kojto	99:dbbf35b96557	1441	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
Kojto	99:dbbf35b96557	1442	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
Kojto	99:dbbf35b96557	1443
Kojto	99:dbbf35b96557	1444	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
Kojto	99:dbbf35b96557	1445	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
Kojto	99:dbbf35b96557	1446	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
Kojto	99:dbbf35b96557	1447	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
Kojto	99:dbbf35b96557	1448
Kojto	99:dbbf35b96557	1449	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
Kojto	99:dbbf35b96557	1450
Kojto	99:dbbf35b96557	1451	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
Kojto	99:dbbf35b96557	1452	((STATE) == TIM_OSSR_DISABLE))
Kojto	99:dbbf35b96557	1453
Kojto	99:dbbf35b96557	1454	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
Kojto	99:dbbf35b96557	1455	((STATE) == TIM_OSSI_DISABLE))
Kojto	99:dbbf35b96557	1456
Kojto	99:dbbf35b96557	1457	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
Kojto	99:dbbf35b96557	1458	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
Kojto	99:dbbf35b96557	1459	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
Kojto	99:dbbf35b96557	1460	((LEVEL) == TIM_LOCKLEVEL_3))
Kojto	99:dbbf35b96557	1461
Kojto	99:dbbf35b96557	1462	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
Kojto	99:dbbf35b96557	1463	((STATE) == TIM_BREAK_DISABLE))
Kojto	99:dbbf35b96557	1464
Kojto	99:dbbf35b96557	1465	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
Kojto	99:dbbf35b96557	1466	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
Kojto	99:dbbf35b96557	1467
Kojto	99:dbbf35b96557	1468	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
Kojto	99:dbbf35b96557	1469	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
Kojto	99:dbbf35b96557	1470
Kojto	99:dbbf35b96557	1471	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
Kojto	99:dbbf35b96557	1472	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
Kojto	99:dbbf35b96557	1473	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
Kojto	99:dbbf35b96557	1474	((SOURCE) == TIM_TRGO_OC1) \|\| \
Kojto	99:dbbf35b96557	1475	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
Kojto	99:dbbf35b96557	1476	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
Kojto	99:dbbf35b96557	1477	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
Kojto	99:dbbf35b96557	1478	((SOURCE) == TIM_TRGO_OC4REF))
Kojto	99:dbbf35b96557	1479
Kojto	99:dbbf35b96557	1480	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1481	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
Kojto	99:dbbf35b96557	1482	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
Kojto	99:dbbf35b96557	1483	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
Kojto	99:dbbf35b96557	1484	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
Kojto	99:dbbf35b96557	1485
Kojto	99:dbbf35b96557	1486	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
Kojto	99:dbbf35b96557	1487	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
Kojto	99:dbbf35b96557	1488
Kojto	99:dbbf35b96557	1489	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
Kojto	99:dbbf35b96557	1490	((SELECTION) == TIM_TS_ITR1) \|\| \
Kojto	99:dbbf35b96557	1491	((SELECTION) == TIM_TS_ITR2) \|\| \
Kojto	99:dbbf35b96557	1492	((SELECTION) == TIM_TS_ITR3) \|\| \
Kojto	99:dbbf35b96557	1493	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
Kojto	99:dbbf35b96557	1494	((SELECTION) == TIM_TS_TI1FP1) \|\| \
Kojto	99:dbbf35b96557	1495	((SELECTION) == TIM_TS_TI2FP2) \|\| \
Kojto	99:dbbf35b96557	1496	((SELECTION) == TIM_TS_ETRF))
Kojto	99:dbbf35b96557	1497
Kojto	99:dbbf35b96557	1498	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
Kojto	99:dbbf35b96557	1499	((SELECTION) == TIM_TS_ITR1) \|\| \
Kojto	99:dbbf35b96557	1500	((SELECTION) == TIM_TS_ITR2) \|\| \
Kojto	99:dbbf35b96557	1501	((SELECTION) == TIM_TS_ITR3) \|\| \
Kojto	99:dbbf35b96557	1502	((SELECTION) == TIM_TS_NONE))
Kojto	99:dbbf35b96557	1503	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
Kojto	99:dbbf35b96557	1504	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
Kojto	99:dbbf35b96557	1505	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
Kojto	99:dbbf35b96557	1506	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
Kojto	99:dbbf35b96557	1507	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
Kojto	99:dbbf35b96557	1508
Kojto	99:dbbf35b96557	1509	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
Kojto	99:dbbf35b96557	1510	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
Kojto	99:dbbf35b96557	1511	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
Kojto	99:dbbf35b96557	1512	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
Kojto	99:dbbf35b96557	1513
Kojto	99:dbbf35b96557	1514	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
Kojto	99:dbbf35b96557	1515
Kojto	99:dbbf35b96557	1516	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
Kojto	99:dbbf35b96557	1517	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
Kojto	99:dbbf35b96557	1518
Kojto	99:dbbf35b96557	1519	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
Kojto	99:dbbf35b96557	1520	((BASE) == TIM_DMABASE_CR2) \|\| \
Kojto	99:dbbf35b96557	1521	((BASE) == TIM_DMABASE_SMCR) \|\| \
Kojto	99:dbbf35b96557	1522	((BASE) == TIM_DMABASE_DIER) \|\| \
Kojto	99:dbbf35b96557	1523	((BASE) == TIM_DMABASE_SR) \|\| \
Kojto	99:dbbf35b96557	1524	((BASE) == TIM_DMABASE_EGR) \|\| \
Kojto	99:dbbf35b96557	1525	((BASE) == TIM_DMABASE_CCMR1) \|\| \
Kojto	99:dbbf35b96557	1526	((BASE) == TIM_DMABASE_CCMR2) \|\| \
Kojto	99:dbbf35b96557	1527	((BASE) == TIM_DMABASE_CCER) \|\| \
Kojto	99:dbbf35b96557	1528	((BASE) == TIM_DMABASE_CNT) \|\| \
Kojto	99:dbbf35b96557	1529	((BASE) == TIM_DMABASE_PSC) \|\| \
Kojto	99:dbbf35b96557	1530	((BASE) == TIM_DMABASE_ARR) \|\| \
Kojto	99:dbbf35b96557	1531	((BASE) == TIM_DMABASE_RCR) \|\| \
Kojto	99:dbbf35b96557	1532	((BASE) == TIM_DMABASE_CCR1) \|\| \
Kojto	99:dbbf35b96557	1533	((BASE) == TIM_DMABASE_CCR2) \|\| \
Kojto	99:dbbf35b96557	1534	((BASE) == TIM_DMABASE_CCR3) \|\| \
Kojto	99:dbbf35b96557	1535	((BASE) == TIM_DMABASE_CCR4) \|\| \
Kojto	99:dbbf35b96557	1536	((BASE) == TIM_DMABASE_BDTR) \|\| \
Kojto	99:dbbf35b96557	1537	((BASE) == TIM_DMABASE_DCR) \|\| \
Kojto	99:dbbf35b96557	1538	((BASE) == TIM_DMABASE_OR))
Kojto	99:dbbf35b96557	1539
Kojto	99:dbbf35b96557	1540	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
Kojto	99:dbbf35b96557	1541	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1542	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1543	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1544	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1545	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1546	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1547	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1548	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1549	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1550	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1551	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1552	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1553	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1554	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1555	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1556	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
Kojto	99:dbbf35b96557	1557	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
Kojto	99:dbbf35b96557	1558
Kojto	99:dbbf35b96557	1559	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
Kojto	99:dbbf35b96557	1560	/**
Kojto	99:dbbf35b96557	1561	* @}
Kojto	99:dbbf35b96557	1562	*/
Kojto	99:dbbf35b96557	1563
Kojto	99:dbbf35b96557	1564	/** @defgroup TIM_Mask_Definitions TIM Mask Definition
Kojto	99:dbbf35b96557	1565	* @{
Kojto	99:dbbf35b96557	1566	*/
Kojto	99:dbbf35b96557	1567	/* The counter of a timer instance is disabled only if all the CCx and CCxN
Kojto	99:dbbf35b96557	1568	channels have been disabled */
Kojto	99:dbbf35b96557	1569	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
Kojto	99:dbbf35b96557	1570	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
Kojto	99:dbbf35b96557	1571	/**
Kojto	99:dbbf35b96557	1572	* @}
Kojto	99:dbbf35b96557	1573	*/
Kojto	99:dbbf35b96557	1574
Kojto	99:dbbf35b96557	1575	/**
Kojto	99:dbbf35b96557	1576	* @}
Kojto	99:dbbf35b96557	1577	*/
Kojto	99:dbbf35b96557	1578
Kojto	99:dbbf35b96557	1579	/* Private functions ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	1580	/** @defgroup TIM_Private_Functions TIM Private Functions
Kojto	99:dbbf35b96557	1581	* @{
Kojto	99:dbbf35b96557	1582	*/
emilmont	77:869cf507173a	1583	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
emilmont	77:869cf507173a	1584	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
emilmont	77:869cf507173a	1585	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
Kojto	99:dbbf35b96557	1586	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
Kojto	99:dbbf35b96557	1587	void TIM_DMAError(DMA_HandleTypeDef *hdma);
Kojto	99:dbbf35b96557	1588	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
Kojto	99:dbbf35b96557	1589	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
Kojto	99:dbbf35b96557	1590	/**
Kojto	99:dbbf35b96557	1591	* @}
Kojto	99:dbbf35b96557	1592	*/
Kojto	99:dbbf35b96557	1593
emilmont	77:869cf507173a	1594	/**
emilmont	77:869cf507173a	1595	* @}
emilmont	77:869cf507173a	1596	*/
emilmont	77:869cf507173a	1597
emilmont	77:869cf507173a	1598	/**
emilmont	77:869cf507173a	1599	* @}
emilmont	77:869cf507173a	1600	*/
emilmont	77:869cf507173a	1601
emilmont	77:869cf507173a	1602	#ifdef __cplusplus
emilmont	77:869cf507173a	1603	}
emilmont	77:869cf507173a	1604	#endif
emilmont	77:869cf507173a	1605
emilmont	77:869cf507173a	1606	#endif /* __STM32F4xx_HAL_TIM_H */
emilmont	77:869cf507173a	1607
emilmont	77:869cf507173a	1608	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Created:	05 Apr 2016
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TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h@99:dbbf35b96557, 2015-05-13 (annotated)

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