meh
Fork of mbed by
TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h@81:7d30d6019079, 2014-03-19 (annotated)
- Committer:
- bogdanm
- Date:
- Wed Mar 19 18:28:32 2014 +0000
- Revision:
- 81:7d30d6019079
- Parent:
- 77:869cf507173a
- Child:
- 85:024bf7f99721
Release 81 of the mbed library
Main changes:
- Updates and fixes for many targets
- LPC1768: serial interface code fixes
- nRF51822 targets now output a .hex file
- More exporters
- More flexible GPIO API
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
emilmont | 77:869cf507173a | 1 | /** |
emilmont | 77:869cf507173a | 2 | ****************************************************************************** |
emilmont | 77:869cf507173a | 3 | * @file stm32f4xx_hal_tim.h |
emilmont | 77:869cf507173a | 4 | * @author MCD Application Team |
bogdanm | 81:7d30d6019079 | 5 | * @version V1.0.0 |
bogdanm | 81:7d30d6019079 | 6 | * @date 18-February-2014 |
emilmont | 77:869cf507173a | 7 | * @brief Header file of TIM HAL module. |
emilmont | 77:869cf507173a | 8 | ****************************************************************************** |
emilmont | 77:869cf507173a | 9 | * @attention |
emilmont | 77:869cf507173a | 10 | * |
emilmont | 77:869cf507173a | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
emilmont | 77:869cf507173a | 12 | * |
emilmont | 77:869cf507173a | 13 | * Redistribution and use in source and binary forms, with or without modification, |
emilmont | 77:869cf507173a | 14 | * are permitted provided that the following conditions are met: |
emilmont | 77:869cf507173a | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
emilmont | 77:869cf507173a | 16 | * this list of conditions and the following disclaimer. |
emilmont | 77:869cf507173a | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
emilmont | 77:869cf507173a | 18 | * this list of conditions and the following disclaimer in the documentation |
emilmont | 77:869cf507173a | 19 | * and/or other materials provided with the distribution. |
emilmont | 77:869cf507173a | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
emilmont | 77:869cf507173a | 21 | * may be used to endorse or promote products derived from this software |
emilmont | 77:869cf507173a | 22 | * without specific prior written permission. |
emilmont | 77:869cf507173a | 23 | * |
emilmont | 77:869cf507173a | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
emilmont | 77:869cf507173a | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
emilmont | 77:869cf507173a | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
emilmont | 77:869cf507173a | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
emilmont | 77:869cf507173a | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
emilmont | 77:869cf507173a | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
emilmont | 77:869cf507173a | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
emilmont | 77:869cf507173a | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
emilmont | 77:869cf507173a | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
emilmont | 77:869cf507173a | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
emilmont | 77:869cf507173a | 34 | * |
emilmont | 77:869cf507173a | 35 | ****************************************************************************** |
emilmont | 77:869cf507173a | 36 | */ |
emilmont | 77:869cf507173a | 37 | |
emilmont | 77:869cf507173a | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
emilmont | 77:869cf507173a | 39 | #ifndef __STM32F4xx_HAL_TIM_H |
emilmont | 77:869cf507173a | 40 | #define __STM32F4xx_HAL_TIM_H |
emilmont | 77:869cf507173a | 41 | |
emilmont | 77:869cf507173a | 42 | #ifdef __cplusplus |
emilmont | 77:869cf507173a | 43 | extern "C" { |
emilmont | 77:869cf507173a | 44 | #endif |
emilmont | 77:869cf507173a | 45 | |
emilmont | 77:869cf507173a | 46 | /* Includes ------------------------------------------------------------------*/ |
emilmont | 77:869cf507173a | 47 | #include "stm32f4xx_hal_def.h" |
emilmont | 77:869cf507173a | 48 | |
emilmont | 77:869cf507173a | 49 | /** @addtogroup STM32F4xx_HAL |
emilmont | 77:869cf507173a | 50 | * @{ |
emilmont | 77:869cf507173a | 51 | */ |
emilmont | 77:869cf507173a | 52 | |
emilmont | 77:869cf507173a | 53 | /** @addtogroup TIM |
emilmont | 77:869cf507173a | 54 | * @{ |
emilmont | 77:869cf507173a | 55 | */ |
emilmont | 77:869cf507173a | 56 | |
emilmont | 77:869cf507173a | 57 | /* Exported types ------------------------------------------------------------*/ |
emilmont | 77:869cf507173a | 58 | |
emilmont | 77:869cf507173a | 59 | /** |
emilmont | 77:869cf507173a | 60 | * @brief TIM Time base Configuration Structure definition |
emilmont | 77:869cf507173a | 61 | */ |
emilmont | 77:869cf507173a | 62 | typedef struct |
emilmont | 77:869cf507173a | 63 | { |
emilmont | 77:869cf507173a | 64 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
emilmont | 77:869cf507173a | 65 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
emilmont | 77:869cf507173a | 66 | |
emilmont | 77:869cf507173a | 67 | uint32_t CounterMode; /*!< Specifies the counter mode. |
emilmont | 77:869cf507173a | 68 | This parameter can be a value of @ref TIM_Counter_Mode */ |
emilmont | 77:869cf507173a | 69 | |
emilmont | 77:869cf507173a | 70 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
emilmont | 77:869cf507173a | 71 | Auto-Reload Register at the next update event. |
emilmont | 77:869cf507173a | 72 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
emilmont | 77:869cf507173a | 73 | |
emilmont | 77:869cf507173a | 74 | uint32_t ClockDivision; /*!< Specifies the clock division. |
emilmont | 77:869cf507173a | 75 | This parameter can be a value of @ref TIM_ClockDivision */ |
emilmont | 77:869cf507173a | 76 | |
emilmont | 77:869cf507173a | 77 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
emilmont | 77:869cf507173a | 78 | reaches zero, an update event is generated and counting restarts |
emilmont | 77:869cf507173a | 79 | from the RCR value (N). |
emilmont | 77:869cf507173a | 80 | This means in PWM mode that (N+1) corresponds to: |
emilmont | 77:869cf507173a | 81 | - the number of PWM periods in edge-aligned mode |
emilmont | 77:869cf507173a | 82 | - the number of half PWM period in center-aligned mode |
emilmont | 77:869cf507173a | 83 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
emilmont | 77:869cf507173a | 84 | @note This parameter is valid only for TIM1 and TIM8. */ |
emilmont | 77:869cf507173a | 85 | } TIM_Base_InitTypeDef; |
emilmont | 77:869cf507173a | 86 | |
emilmont | 77:869cf507173a | 87 | /** |
emilmont | 77:869cf507173a | 88 | * @brief TIM Output Compare Configuration Structure definition |
emilmont | 77:869cf507173a | 89 | */ |
emilmont | 77:869cf507173a | 90 | |
emilmont | 77:869cf507173a | 91 | typedef struct |
emilmont | 77:869cf507173a | 92 | { |
emilmont | 77:869cf507173a | 93 | uint32_t OCMode; /*!< Specifies the TIM mode. |
emilmont | 77:869cf507173a | 94 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
emilmont | 77:869cf507173a | 95 | |
emilmont | 77:869cf507173a | 96 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
emilmont | 77:869cf507173a | 97 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
emilmont | 77:869cf507173a | 98 | |
emilmont | 77:869cf507173a | 99 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
emilmont | 77:869cf507173a | 100 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
emilmont | 77:869cf507173a | 101 | |
emilmont | 77:869cf507173a | 102 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
emilmont | 77:869cf507173a | 103 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
emilmont | 77:869cf507173a | 104 | @note This parameter is valid only for TIM1 and TIM8. */ |
emilmont | 77:869cf507173a | 105 | |
emilmont | 77:869cf507173a | 106 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
emilmont | 77:869cf507173a | 107 | This parameter can be a value of @ref TIM_Output_Fast_State |
emilmont | 77:869cf507173a | 108 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
emilmont | 77:869cf507173a | 109 | |
emilmont | 77:869cf507173a | 110 | |
emilmont | 77:869cf507173a | 111 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
emilmont | 77:869cf507173a | 112 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
emilmont | 77:869cf507173a | 113 | @note This parameter is valid only for TIM1 and TIM8. */ |
emilmont | 77:869cf507173a | 114 | |
emilmont | 77:869cf507173a | 115 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
emilmont | 77:869cf507173a | 116 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
emilmont | 77:869cf507173a | 117 | @note This parameter is valid only for TIM1 and TIM8. */ |
emilmont | 77:869cf507173a | 118 | } TIM_OC_InitTypeDef; |
emilmont | 77:869cf507173a | 119 | |
emilmont | 77:869cf507173a | 120 | /** |
emilmont | 77:869cf507173a | 121 | * @brief TIM One Pulse Mode Configuration Structure definition |
emilmont | 77:869cf507173a | 122 | */ |
emilmont | 77:869cf507173a | 123 | typedef struct |
emilmont | 77:869cf507173a | 124 | { |
emilmont | 77:869cf507173a | 125 | uint32_t OCMode; /*!< Specifies the TIM mode. |
emilmont | 77:869cf507173a | 126 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
emilmont | 77:869cf507173a | 127 | |
emilmont | 77:869cf507173a | 128 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
emilmont | 77:869cf507173a | 129 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
emilmont | 77:869cf507173a | 130 | |
emilmont | 77:869cf507173a | 131 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
emilmont | 77:869cf507173a | 132 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
emilmont | 77:869cf507173a | 133 | |
emilmont | 77:869cf507173a | 134 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
emilmont | 77:869cf507173a | 135 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
emilmont | 77:869cf507173a | 136 | @note This parameter is valid only for TIM1 and TIM8. */ |
emilmont | 77:869cf507173a | 137 | |
emilmont | 77:869cf507173a | 138 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
emilmont | 77:869cf507173a | 139 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
emilmont | 77:869cf507173a | 140 | @note This parameter is valid only for TIM1 and TIM8. */ |
emilmont | 77:869cf507173a | 141 | |
emilmont | 77:869cf507173a | 142 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
emilmont | 77:869cf507173a | 143 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
emilmont | 77:869cf507173a | 144 | @note This parameter is valid only for TIM1 and TIM8. */ |
emilmont | 77:869cf507173a | 145 | |
emilmont | 77:869cf507173a | 146 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
emilmont | 77:869cf507173a | 147 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
emilmont | 77:869cf507173a | 148 | |
emilmont | 77:869cf507173a | 149 | uint32_t ICSelection; /*!< Specifies the input. |
emilmont | 77:869cf507173a | 150 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
emilmont | 77:869cf507173a | 151 | |
emilmont | 77:869cf507173a | 152 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
emilmont | 77:869cf507173a | 153 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
emilmont | 77:869cf507173a | 154 | } TIM_OnePulse_InitTypeDef; |
emilmont | 77:869cf507173a | 155 | |
emilmont | 77:869cf507173a | 156 | |
emilmont | 77:869cf507173a | 157 | /** |
emilmont | 77:869cf507173a | 158 | * @brief TIM Input Capture Configuration Structure definition |
emilmont | 77:869cf507173a | 159 | */ |
emilmont | 77:869cf507173a | 160 | |
emilmont | 77:869cf507173a | 161 | typedef struct |
emilmont | 77:869cf507173a | 162 | { |
emilmont | 77:869cf507173a | 163 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
emilmont | 77:869cf507173a | 164 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
emilmont | 77:869cf507173a | 165 | |
emilmont | 77:869cf507173a | 166 | uint32_t ICSelection; /*!< Specifies the input. |
emilmont | 77:869cf507173a | 167 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
emilmont | 77:869cf507173a | 168 | |
emilmont | 77:869cf507173a | 169 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
emilmont | 77:869cf507173a | 170 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
emilmont | 77:869cf507173a | 171 | |
emilmont | 77:869cf507173a | 172 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
emilmont | 77:869cf507173a | 173 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
emilmont | 77:869cf507173a | 174 | } TIM_IC_InitTypeDef; |
emilmont | 77:869cf507173a | 175 | |
emilmont | 77:869cf507173a | 176 | /** |
emilmont | 77:869cf507173a | 177 | * @brief TIM Encoder Configuration Structure definition |
emilmont | 77:869cf507173a | 178 | */ |
emilmont | 77:869cf507173a | 179 | |
emilmont | 77:869cf507173a | 180 | typedef struct |
emilmont | 77:869cf507173a | 181 | { |
emilmont | 77:869cf507173a | 182 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
emilmont | 77:869cf507173a | 183 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
emilmont | 77:869cf507173a | 184 | |
emilmont | 77:869cf507173a | 185 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
emilmont | 77:869cf507173a | 186 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
emilmont | 77:869cf507173a | 187 | |
emilmont | 77:869cf507173a | 188 | uint32_t IC1Selection; /*!< Specifies the input. |
emilmont | 77:869cf507173a | 189 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
emilmont | 77:869cf507173a | 190 | |
emilmont | 77:869cf507173a | 191 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
emilmont | 77:869cf507173a | 192 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
emilmont | 77:869cf507173a | 193 | |
emilmont | 77:869cf507173a | 194 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
emilmont | 77:869cf507173a | 195 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
emilmont | 77:869cf507173a | 196 | |
emilmont | 77:869cf507173a | 197 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
emilmont | 77:869cf507173a | 198 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
emilmont | 77:869cf507173a | 199 | |
emilmont | 77:869cf507173a | 200 | uint32_t IC2Selection; /*!< Specifies the input. |
emilmont | 77:869cf507173a | 201 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
emilmont | 77:869cf507173a | 202 | |
emilmont | 77:869cf507173a | 203 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
emilmont | 77:869cf507173a | 204 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
emilmont | 77:869cf507173a | 205 | |
emilmont | 77:869cf507173a | 206 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
emilmont | 77:869cf507173a | 207 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
emilmont | 77:869cf507173a | 208 | } TIM_Encoder_InitTypeDef; |
emilmont | 77:869cf507173a | 209 | |
emilmont | 77:869cf507173a | 210 | /** |
emilmont | 77:869cf507173a | 211 | * @brief Clock Configuration Handle Structure definition |
emilmont | 77:869cf507173a | 212 | */ |
emilmont | 77:869cf507173a | 213 | typedef struct |
emilmont | 77:869cf507173a | 214 | { |
emilmont | 77:869cf507173a | 215 | uint32_t ClockSource; /*!< TIM clock sources |
emilmont | 77:869cf507173a | 216 | This parameter can be a value of @ref TIM_Clock_Source */ |
emilmont | 77:869cf507173a | 217 | uint32_t ClockPolarity; /*!< TIM clock polarity |
emilmont | 77:869cf507173a | 218 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
emilmont | 77:869cf507173a | 219 | uint32_t ClockPrescaler; /*!< TIM clock prescaler |
emilmont | 77:869cf507173a | 220 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
emilmont | 77:869cf507173a | 221 | uint32_t ClockFilter; /*!< TIM clock filter |
emilmont | 77:869cf507173a | 222 | This parameter can be a value of @ref TIM_Clock_Filter */ |
emilmont | 77:869cf507173a | 223 | }TIM_ClockConfigTypeDef; |
emilmont | 77:869cf507173a | 224 | |
emilmont | 77:869cf507173a | 225 | /** |
emilmont | 77:869cf507173a | 226 | * @brief Clear Input Configuration Handle Structure definition |
emilmont | 77:869cf507173a | 227 | */ |
emilmont | 77:869cf507173a | 228 | typedef struct |
emilmont | 77:869cf507173a | 229 | { |
emilmont | 77:869cf507173a | 230 | uint32_t ClearInputState; /*!< TIM clear Input state |
emilmont | 77:869cf507173a | 231 | This parameter can be ENABLE or DISABLE */ |
emilmont | 77:869cf507173a | 232 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
emilmont | 77:869cf507173a | 233 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
emilmont | 77:869cf507173a | 234 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
emilmont | 77:869cf507173a | 235 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
emilmont | 77:869cf507173a | 236 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
emilmont | 77:869cf507173a | 237 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
emilmont | 77:869cf507173a | 238 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
emilmont | 77:869cf507173a | 239 | This parameter can be a value of @ref TIM_ClearInput_Filter */ |
emilmont | 77:869cf507173a | 240 | }TIM_ClearInputConfigTypeDef; |
emilmont | 77:869cf507173a | 241 | |
emilmont | 77:869cf507173a | 242 | /** |
emilmont | 77:869cf507173a | 243 | * @brief TIM Slave configuration Structure definition |
emilmont | 77:869cf507173a | 244 | */ |
emilmont | 77:869cf507173a | 245 | typedef struct { |
emilmont | 77:869cf507173a | 246 | uint32_t SlaveMode; /*!< Slave mode selection |
emilmont | 77:869cf507173a | 247 | This parameter can be a value of @ref TIM_Slave_Mode */ |
emilmont | 77:869cf507173a | 248 | uint32_t InputTrigger; /*!< Input Trigger source |
emilmont | 77:869cf507173a | 249 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
emilmont | 77:869cf507173a | 250 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
emilmont | 77:869cf507173a | 251 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
emilmont | 77:869cf507173a | 252 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
emilmont | 77:869cf507173a | 253 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
emilmont | 77:869cf507173a | 254 | uint32_t TriggerFilter; /*!< Input trigger filter |
emilmont | 77:869cf507173a | 255 | This parameter can be a value of @ref TIM_Trigger_Filter */ |
emilmont | 77:869cf507173a | 256 | |
emilmont | 77:869cf507173a | 257 | }TIM_SlaveConfigTypeDef; |
emilmont | 77:869cf507173a | 258 | |
emilmont | 77:869cf507173a | 259 | /** |
emilmont | 77:869cf507173a | 260 | * @brief HAL State structures definition |
emilmont | 77:869cf507173a | 261 | */ |
emilmont | 77:869cf507173a | 262 | typedef enum |
emilmont | 77:869cf507173a | 263 | { |
emilmont | 77:869cf507173a | 264 | HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ |
emilmont | 77:869cf507173a | 265 | HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ |
emilmont | 77:869cf507173a | 266 | HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
emilmont | 77:869cf507173a | 267 | HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
emilmont | 77:869cf507173a | 268 | HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ |
emilmont | 77:869cf507173a | 269 | }HAL_TIM_StateTypeDef; |
emilmont | 77:869cf507173a | 270 | |
emilmont | 77:869cf507173a | 271 | /** |
emilmont | 77:869cf507173a | 272 | * @brief HAL Active channel structures definition |
emilmont | 77:869cf507173a | 273 | */ |
emilmont | 77:869cf507173a | 274 | typedef enum |
emilmont | 77:869cf507173a | 275 | { |
emilmont | 77:869cf507173a | 276 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ |
emilmont | 77:869cf507173a | 277 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ |
emilmont | 77:869cf507173a | 278 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ |
emilmont | 77:869cf507173a | 279 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ |
emilmont | 77:869cf507173a | 280 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ |
emilmont | 77:869cf507173a | 281 | }HAL_TIM_ActiveChannel; |
emilmont | 77:869cf507173a | 282 | |
emilmont | 77:869cf507173a | 283 | /** |
emilmont | 77:869cf507173a | 284 | * @brief TIM Time Base Handle Structure definition |
emilmont | 77:869cf507173a | 285 | */ |
emilmont | 77:869cf507173a | 286 | typedef struct |
emilmont | 77:869cf507173a | 287 | { |
emilmont | 77:869cf507173a | 288 | TIM_TypeDef *Instance; /*!< Register base address */ |
emilmont | 77:869cf507173a | 289 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
emilmont | 77:869cf507173a | 290 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
emilmont | 77:869cf507173a | 291 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
emilmont | 77:869cf507173a | 292 | This array is accessed by a @ref DMA_Handle_index */ |
emilmont | 77:869cf507173a | 293 | HAL_LockTypeDef Lock; /*!< Locking object */ |
emilmont | 77:869cf507173a | 294 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
emilmont | 77:869cf507173a | 295 | }TIM_HandleTypeDef; |
emilmont | 77:869cf507173a | 296 | |
emilmont | 77:869cf507173a | 297 | /* Exported constants --------------------------------------------------------*/ |
emilmont | 77:869cf507173a | 298 | /** @defgroup TIM_Exported_Constants |
emilmont | 77:869cf507173a | 299 | * @{ |
emilmont | 77:869cf507173a | 300 | */ |
emilmont | 77:869cf507173a | 301 | |
emilmont | 77:869cf507173a | 302 | /** @defgroup TIM_Input_Channel_Polarity |
emilmont | 77:869cf507173a | 303 | * @{ |
emilmont | 77:869cf507173a | 304 | */ |
emilmont | 77:869cf507173a | 305 | #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ |
emilmont | 77:869cf507173a | 306 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
emilmont | 77:869cf507173a | 307 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
emilmont | 77:869cf507173a | 308 | /** |
emilmont | 77:869cf507173a | 309 | * @} |
emilmont | 77:869cf507173a | 310 | */ |
emilmont | 77:869cf507173a | 311 | |
emilmont | 77:869cf507173a | 312 | /** @defgroup TIM_ETR_Polarity |
emilmont | 77:869cf507173a | 313 | * @{ |
emilmont | 77:869cf507173a | 314 | */ |
emilmont | 77:869cf507173a | 315 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
emilmont | 77:869cf507173a | 316 | #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ |
emilmont | 77:869cf507173a | 317 | /** |
emilmont | 77:869cf507173a | 318 | * @} |
emilmont | 77:869cf507173a | 319 | */ |
emilmont | 77:869cf507173a | 320 | |
emilmont | 77:869cf507173a | 321 | /** @defgroup TIM_ETR_Prescaler |
emilmont | 77:869cf507173a | 322 | * @{ |
emilmont | 77:869cf507173a | 323 | */ |
emilmont | 77:869cf507173a | 324 | #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ |
emilmont | 77:869cf507173a | 325 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ |
emilmont | 77:869cf507173a | 326 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ |
emilmont | 77:869cf507173a | 327 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ |
emilmont | 77:869cf507173a | 328 | /** |
emilmont | 77:869cf507173a | 329 | * @} |
emilmont | 77:869cf507173a | 330 | */ |
emilmont | 77:869cf507173a | 331 | |
emilmont | 77:869cf507173a | 332 | /** @defgroup TIM_Counter_Mode |
emilmont | 77:869cf507173a | 333 | * @{ |
emilmont | 77:869cf507173a | 334 | */ |
emilmont | 77:869cf507173a | 335 | |
emilmont | 77:869cf507173a | 336 | #define TIM_COUNTERMODE_UP ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 337 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
emilmont | 77:869cf507173a | 338 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
emilmont | 77:869cf507173a | 339 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
emilmont | 77:869cf507173a | 340 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
emilmont | 77:869cf507173a | 341 | |
emilmont | 77:869cf507173a | 342 | #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ |
emilmont | 77:869cf507173a | 343 | ((MODE) == TIM_COUNTERMODE_DOWN) || \ |
emilmont | 77:869cf507173a | 344 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
emilmont | 77:869cf507173a | 345 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
emilmont | 77:869cf507173a | 346 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) |
emilmont | 77:869cf507173a | 347 | /** |
emilmont | 77:869cf507173a | 348 | * @} |
emilmont | 77:869cf507173a | 349 | */ |
emilmont | 77:869cf507173a | 350 | |
emilmont | 77:869cf507173a | 351 | /** @defgroup TIM_ClockDivision |
emilmont | 77:869cf507173a | 352 | * @{ |
emilmont | 77:869cf507173a | 353 | */ |
emilmont | 77:869cf507173a | 354 | |
emilmont | 77:869cf507173a | 355 | #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 356 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
emilmont | 77:869cf507173a | 357 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
emilmont | 77:869cf507173a | 358 | |
emilmont | 77:869cf507173a | 359 | #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ |
emilmont | 77:869cf507173a | 360 | ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ |
emilmont | 77:869cf507173a | 361 | ((DIV) == TIM_CLOCKDIVISION_DIV4)) |
emilmont | 77:869cf507173a | 362 | /** |
emilmont | 77:869cf507173a | 363 | * @} |
emilmont | 77:869cf507173a | 364 | */ |
emilmont | 77:869cf507173a | 365 | |
emilmont | 77:869cf507173a | 366 | /** @defgroup TIM_Output_Compare_and_PWM_modes |
emilmont | 77:869cf507173a | 367 | * @{ |
emilmont | 77:869cf507173a | 368 | */ |
emilmont | 77:869cf507173a | 369 | |
emilmont | 77:869cf507173a | 370 | #define TIM_OCMODE_TIMING ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 371 | #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) |
emilmont | 77:869cf507173a | 372 | #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) |
emilmont | 77:869cf507173a | 373 | #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) |
emilmont | 77:869cf507173a | 374 | #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
emilmont | 77:869cf507173a | 375 | #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) |
emilmont | 77:869cf507173a | 376 | #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
emilmont | 77:869cf507173a | 377 | #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) |
emilmont | 77:869cf507173a | 378 | |
emilmont | 77:869cf507173a | 379 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ |
emilmont | 77:869cf507173a | 380 | ((MODE) == TIM_OCMODE_PWM2)) |
emilmont | 77:869cf507173a | 381 | |
emilmont | 77:869cf507173a | 382 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ |
emilmont | 77:869cf507173a | 383 | ((MODE) == TIM_OCMODE_ACTIVE) || \ |
emilmont | 77:869cf507173a | 384 | ((MODE) == TIM_OCMODE_INACTIVE) || \ |
emilmont | 77:869cf507173a | 385 | ((MODE) == TIM_OCMODE_TOGGLE) || \ |
emilmont | 77:869cf507173a | 386 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ |
emilmont | 77:869cf507173a | 387 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) |
emilmont | 77:869cf507173a | 388 | /** |
emilmont | 77:869cf507173a | 389 | * @} |
emilmont | 77:869cf507173a | 390 | */ |
emilmont | 77:869cf507173a | 391 | |
emilmont | 77:869cf507173a | 392 | /** @defgroup TIM_Output_Compare_State |
emilmont | 77:869cf507173a | 393 | * @{ |
emilmont | 77:869cf507173a | 394 | */ |
emilmont | 77:869cf507173a | 395 | |
emilmont | 77:869cf507173a | 396 | #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 397 | #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) |
emilmont | 77:869cf507173a | 398 | |
emilmont | 77:869cf507173a | 399 | #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ |
emilmont | 77:869cf507173a | 400 | ((STATE) == TIM_OUTPUTSTATE_ENABLE)) |
emilmont | 77:869cf507173a | 401 | /** |
emilmont | 77:869cf507173a | 402 | * @} |
emilmont | 77:869cf507173a | 403 | */ |
emilmont | 77:869cf507173a | 404 | /** @defgroup TIM_Output_Fast_State |
emilmont | 77:869cf507173a | 405 | * @{ |
emilmont | 77:869cf507173a | 406 | */ |
emilmont | 77:869cf507173a | 407 | #define TIM_OCFAST_DISABLE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 408 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
emilmont | 77:869cf507173a | 409 | |
emilmont | 77:869cf507173a | 410 | #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ |
emilmont | 77:869cf507173a | 411 | ((STATE) == TIM_OCFAST_ENABLE)) |
emilmont | 77:869cf507173a | 412 | /** |
emilmont | 77:869cf507173a | 413 | * @} |
emilmont | 77:869cf507173a | 414 | */ |
emilmont | 77:869cf507173a | 415 | /** @defgroup TIM_Output_Compare_N_State |
emilmont | 77:869cf507173a | 416 | * @{ |
emilmont | 77:869cf507173a | 417 | */ |
emilmont | 77:869cf507173a | 418 | |
emilmont | 77:869cf507173a | 419 | #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 420 | #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) |
emilmont | 77:869cf507173a | 421 | |
emilmont | 77:869cf507173a | 422 | #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ |
emilmont | 77:869cf507173a | 423 | ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) |
emilmont | 77:869cf507173a | 424 | /** |
emilmont | 77:869cf507173a | 425 | * @} |
emilmont | 77:869cf507173a | 426 | */ |
emilmont | 77:869cf507173a | 427 | |
emilmont | 77:869cf507173a | 428 | /** @defgroup TIM_Output_Compare_Polarity |
emilmont | 77:869cf507173a | 429 | * @{ |
emilmont | 77:869cf507173a | 430 | */ |
emilmont | 77:869cf507173a | 431 | |
emilmont | 77:869cf507173a | 432 | #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 433 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
emilmont | 77:869cf507173a | 434 | |
emilmont | 77:869cf507173a | 435 | #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ |
emilmont | 77:869cf507173a | 436 | ((POLARITY) == TIM_OCPOLARITY_LOW)) |
emilmont | 77:869cf507173a | 437 | /** |
emilmont | 77:869cf507173a | 438 | * @} |
emilmont | 77:869cf507173a | 439 | */ |
emilmont | 77:869cf507173a | 440 | |
emilmont | 77:869cf507173a | 441 | /** @defgroup TIM_Output_Compare_N_Polarity |
emilmont | 77:869cf507173a | 442 | * @{ |
emilmont | 77:869cf507173a | 443 | */ |
emilmont | 77:869cf507173a | 444 | |
emilmont | 77:869cf507173a | 445 | #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 446 | #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) |
emilmont | 77:869cf507173a | 447 | |
emilmont | 77:869cf507173a | 448 | #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ |
emilmont | 77:869cf507173a | 449 | ((POLARITY) == TIM_OCNPOLARITY_LOW)) |
emilmont | 77:869cf507173a | 450 | /** |
emilmont | 77:869cf507173a | 451 | * @} |
emilmont | 77:869cf507173a | 452 | */ |
emilmont | 77:869cf507173a | 453 | |
emilmont | 77:869cf507173a | 454 | /** @defgroup TIM_Output_Compare_Idle_State |
emilmont | 77:869cf507173a | 455 | * @{ |
emilmont | 77:869cf507173a | 456 | */ |
emilmont | 77:869cf507173a | 457 | |
emilmont | 77:869cf507173a | 458 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) |
emilmont | 77:869cf507173a | 459 | #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 460 | #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ |
emilmont | 77:869cf507173a | 461 | ((STATE) == TIM_OCIDLESTATE_RESET)) |
emilmont | 77:869cf507173a | 462 | /** |
emilmont | 77:869cf507173a | 463 | * @} |
emilmont | 77:869cf507173a | 464 | */ |
emilmont | 77:869cf507173a | 465 | |
emilmont | 77:869cf507173a | 466 | /** @defgroup TIM_Output_Compare_N_Idle_State |
emilmont | 77:869cf507173a | 467 | * @{ |
emilmont | 77:869cf507173a | 468 | */ |
emilmont | 77:869cf507173a | 469 | |
emilmont | 77:869cf507173a | 470 | #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) |
emilmont | 77:869cf507173a | 471 | #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 472 | #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ |
emilmont | 77:869cf507173a | 473 | ((STATE) == TIM_OCNIDLESTATE_RESET)) |
emilmont | 77:869cf507173a | 474 | /** |
emilmont | 77:869cf507173a | 475 | * @} |
emilmont | 77:869cf507173a | 476 | */ |
emilmont | 77:869cf507173a | 477 | |
emilmont | 77:869cf507173a | 478 | /** @defgroup TIM_Channel |
emilmont | 77:869cf507173a | 479 | * @{ |
emilmont | 77:869cf507173a | 480 | */ |
emilmont | 77:869cf507173a | 481 | |
emilmont | 77:869cf507173a | 482 | #define TIM_CHANNEL_1 ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 483 | #define TIM_CHANNEL_2 ((uint32_t)0x0004) |
emilmont | 77:869cf507173a | 484 | #define TIM_CHANNEL_3 ((uint32_t)0x0008) |
emilmont | 77:869cf507173a | 485 | #define TIM_CHANNEL_4 ((uint32_t)0x000C) |
emilmont | 77:869cf507173a | 486 | #define TIM_CHANNEL_ALL ((uint32_t)0x0018) |
emilmont | 77:869cf507173a | 487 | |
emilmont | 77:869cf507173a | 488 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
emilmont | 77:869cf507173a | 489 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
emilmont | 77:869cf507173a | 490 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
emilmont | 77:869cf507173a | 491 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
emilmont | 77:869cf507173a | 492 | ((CHANNEL) == TIM_CHANNEL_ALL)) |
emilmont | 77:869cf507173a | 493 | |
emilmont | 77:869cf507173a | 494 | #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
emilmont | 77:869cf507173a | 495 | ((CHANNEL) == TIM_CHANNEL_2)) |
emilmont | 77:869cf507173a | 496 | |
emilmont | 77:869cf507173a | 497 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
emilmont | 77:869cf507173a | 498 | ((CHANNEL) == TIM_CHANNEL_2)) |
emilmont | 77:869cf507173a | 499 | |
emilmont | 77:869cf507173a | 500 | #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
emilmont | 77:869cf507173a | 501 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
emilmont | 77:869cf507173a | 502 | ((CHANNEL) == TIM_CHANNEL_3)) |
emilmont | 77:869cf507173a | 503 | /** |
emilmont | 77:869cf507173a | 504 | * @} |
emilmont | 77:869cf507173a | 505 | */ |
emilmont | 77:869cf507173a | 506 | |
emilmont | 77:869cf507173a | 507 | |
emilmont | 77:869cf507173a | 508 | /** @defgroup TIM_Input_Capture_Polarity |
emilmont | 77:869cf507173a | 509 | * @{ |
emilmont | 77:869cf507173a | 510 | */ |
emilmont | 77:869cf507173a | 511 | |
emilmont | 77:869cf507173a | 512 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING |
emilmont | 77:869cf507173a | 513 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING |
emilmont | 77:869cf507173a | 514 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE |
emilmont | 77:869cf507173a | 515 | |
emilmont | 77:869cf507173a | 516 | #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ |
emilmont | 77:869cf507173a | 517 | ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ |
emilmont | 77:869cf507173a | 518 | ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) |
emilmont | 77:869cf507173a | 519 | /** |
emilmont | 77:869cf507173a | 520 | * @} |
emilmont | 77:869cf507173a | 521 | */ |
emilmont | 77:869cf507173a | 522 | |
emilmont | 77:869cf507173a | 523 | /** @defgroup TIM_Input_Capture_Selection |
emilmont | 77:869cf507173a | 524 | * @{ |
emilmont | 77:869cf507173a | 525 | */ |
emilmont | 77:869cf507173a | 526 | |
emilmont | 77:869cf507173a | 527 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
emilmont | 77:869cf507173a | 528 | connected to IC1, IC2, IC3 or IC4, respectively */ |
emilmont | 77:869cf507173a | 529 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
emilmont | 77:869cf507173a | 530 | connected to IC2, IC1, IC4 or IC3, respectively */ |
emilmont | 77:869cf507173a | 531 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
emilmont | 77:869cf507173a | 532 | |
emilmont | 77:869cf507173a | 533 | #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ |
emilmont | 77:869cf507173a | 534 | ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ |
emilmont | 77:869cf507173a | 535 | ((SELECTION) == TIM_ICSELECTION_TRC)) |
emilmont | 77:869cf507173a | 536 | /** |
emilmont | 77:869cf507173a | 537 | * @} |
emilmont | 77:869cf507173a | 538 | */ |
emilmont | 77:869cf507173a | 539 | |
emilmont | 77:869cf507173a | 540 | /** @defgroup TIM_Input_Capture_Prescaler |
emilmont | 77:869cf507173a | 541 | * @{ |
emilmont | 77:869cf507173a | 542 | */ |
emilmont | 77:869cf507173a | 543 | |
emilmont | 77:869cf507173a | 544 | #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ |
emilmont | 77:869cf507173a | 545 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
emilmont | 77:869cf507173a | 546 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
emilmont | 77:869cf507173a | 547 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
emilmont | 77:869cf507173a | 548 | |
emilmont | 77:869cf507173a | 549 | #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ |
emilmont | 77:869cf507173a | 550 | ((PRESCALER) == TIM_ICPSC_DIV2) || \ |
emilmont | 77:869cf507173a | 551 | ((PRESCALER) == TIM_ICPSC_DIV4) || \ |
emilmont | 77:869cf507173a | 552 | ((PRESCALER) == TIM_ICPSC_DIV8)) |
emilmont | 77:869cf507173a | 553 | /** |
emilmont | 77:869cf507173a | 554 | * @} |
emilmont | 77:869cf507173a | 555 | */ |
emilmont | 77:869cf507173a | 556 | |
emilmont | 77:869cf507173a | 557 | /** @defgroup TIM_One_Pulse_Mode |
emilmont | 77:869cf507173a | 558 | * @{ |
emilmont | 77:869cf507173a | 559 | */ |
emilmont | 77:869cf507173a | 560 | |
emilmont | 77:869cf507173a | 561 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
emilmont | 77:869cf507173a | 562 | #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 563 | #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ |
emilmont | 77:869cf507173a | 564 | ((MODE) == TIM_OPMODE_REPETITIVE)) |
emilmont | 77:869cf507173a | 565 | /** |
emilmont | 77:869cf507173a | 566 | * @} |
emilmont | 77:869cf507173a | 567 | */ |
emilmont | 77:869cf507173a | 568 | /** @defgroup TIM_Encoder_Mode |
emilmont | 77:869cf507173a | 569 | * @{ |
emilmont | 77:869cf507173a | 570 | */ |
emilmont | 77:869cf507173a | 571 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
emilmont | 77:869cf507173a | 572 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
emilmont | 77:869cf507173a | 573 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
emilmont | 77:869cf507173a | 574 | #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ |
emilmont | 77:869cf507173a | 575 | ((MODE) == TIM_ENCODERMODE_TI2) || \ |
emilmont | 77:869cf507173a | 576 | ((MODE) == TIM_ENCODERMODE_TI12)) |
emilmont | 77:869cf507173a | 577 | /** |
emilmont | 77:869cf507173a | 578 | * @} |
emilmont | 77:869cf507173a | 579 | */ |
emilmont | 77:869cf507173a | 580 | /** @defgroup TIM_Interrupt_definition |
emilmont | 77:869cf507173a | 581 | * @{ |
emilmont | 77:869cf507173a | 582 | */ |
emilmont | 77:869cf507173a | 583 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
emilmont | 77:869cf507173a | 584 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
emilmont | 77:869cf507173a | 585 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
emilmont | 77:869cf507173a | 586 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
emilmont | 77:869cf507173a | 587 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
emilmont | 77:869cf507173a | 588 | #define TIM_IT_COM (TIM_DIER_COMIE) |
emilmont | 77:869cf507173a | 589 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
emilmont | 77:869cf507173a | 590 | #define TIM_IT_BREAK (TIM_DIER_BIE) |
emilmont | 77:869cf507173a | 591 | |
emilmont | 77:869cf507173a | 592 | #define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000)) |
emilmont | 77:869cf507173a | 593 | |
emilmont | 77:869cf507173a | 594 | #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \ |
emilmont | 77:869cf507173a | 595 | ((IT) == TIM_IT_CC1) || \ |
emilmont | 77:869cf507173a | 596 | ((IT) == TIM_IT_CC2) || \ |
emilmont | 77:869cf507173a | 597 | ((IT) == TIM_IT_CC3) || \ |
emilmont | 77:869cf507173a | 598 | ((IT) == TIM_IT_CC4) || \ |
emilmont | 77:869cf507173a | 599 | ((IT) == TIM_IT_COM) || \ |
emilmont | 77:869cf507173a | 600 | ((IT) == TIM_IT_TRIGGER) || \ |
emilmont | 77:869cf507173a | 601 | ((IT) == TIM_IT_BREAK)) |
emilmont | 77:869cf507173a | 602 | /** |
emilmont | 77:869cf507173a | 603 | * @} |
emilmont | 77:869cf507173a | 604 | */ |
emilmont | 77:869cf507173a | 605 | #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) |
emilmont | 77:869cf507173a | 606 | #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 607 | |
emilmont | 77:869cf507173a | 608 | /** @defgroup TIM_DMA_sources |
emilmont | 77:869cf507173a | 609 | * @{ |
emilmont | 77:869cf507173a | 610 | */ |
emilmont | 77:869cf507173a | 611 | |
emilmont | 77:869cf507173a | 612 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
emilmont | 77:869cf507173a | 613 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
emilmont | 77:869cf507173a | 614 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
emilmont | 77:869cf507173a | 615 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
emilmont | 77:869cf507173a | 616 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
emilmont | 77:869cf507173a | 617 | #define TIM_DMA_COM (TIM_DIER_COMDE) |
emilmont | 77:869cf507173a | 618 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
emilmont | 77:869cf507173a | 619 | #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) |
emilmont | 77:869cf507173a | 620 | |
emilmont | 77:869cf507173a | 621 | /** |
emilmont | 77:869cf507173a | 622 | * @} |
emilmont | 77:869cf507173a | 623 | */ |
emilmont | 77:869cf507173a | 624 | |
emilmont | 77:869cf507173a | 625 | /** @defgroup TIM_Event_Source |
emilmont | 77:869cf507173a | 626 | * @{ |
emilmont | 77:869cf507173a | 627 | */ |
emilmont | 77:869cf507173a | 628 | |
emilmont | 77:869cf507173a | 629 | #define TIM_EventSource_Update TIM_EGR_UG |
emilmont | 77:869cf507173a | 630 | #define TIM_EventSource_CC1 TIM_EGR_CC1G |
emilmont | 77:869cf507173a | 631 | #define TIM_EventSource_CC2 TIM_EGR_CC2G |
emilmont | 77:869cf507173a | 632 | #define TIM_EventSource_CC3 TIM_EGR_CC3G |
emilmont | 77:869cf507173a | 633 | #define TIM_EventSource_CC4 TIM_EGR_CC4G |
emilmont | 77:869cf507173a | 634 | #define TIM_EventSource_COM TIM_EGR_COMG |
emilmont | 77:869cf507173a | 635 | #define TIM_EventSource_Trigger TIM_EGR_TG |
emilmont | 77:869cf507173a | 636 | #define TIM_EventSource_Break TIM_EGR_BG |
emilmont | 77:869cf507173a | 637 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) |
emilmont | 77:869cf507173a | 638 | |
emilmont | 77:869cf507173a | 639 | /** |
emilmont | 77:869cf507173a | 640 | * @} |
emilmont | 77:869cf507173a | 641 | */ |
emilmont | 77:869cf507173a | 642 | |
emilmont | 77:869cf507173a | 643 | /** @defgroup TIM_Flag_definition |
emilmont | 77:869cf507173a | 644 | * @{ |
emilmont | 77:869cf507173a | 645 | */ |
emilmont | 77:869cf507173a | 646 | |
emilmont | 77:869cf507173a | 647 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
emilmont | 77:869cf507173a | 648 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
emilmont | 77:869cf507173a | 649 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
emilmont | 77:869cf507173a | 650 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
emilmont | 77:869cf507173a | 651 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
emilmont | 77:869cf507173a | 652 | #define TIM_FLAG_COM (TIM_SR_COMIF) |
emilmont | 77:869cf507173a | 653 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
emilmont | 77:869cf507173a | 654 | #define TIM_FLAG_BREAK (TIM_SR_BIF) |
emilmont | 77:869cf507173a | 655 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
emilmont | 77:869cf507173a | 656 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
emilmont | 77:869cf507173a | 657 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
emilmont | 77:869cf507173a | 658 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
emilmont | 77:869cf507173a | 659 | |
emilmont | 77:869cf507173a | 660 | #define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \ |
emilmont | 77:869cf507173a | 661 | ((FLAG) == TIM_FLAG_CC1) || \ |
emilmont | 77:869cf507173a | 662 | ((FLAG) == TIM_FLAG_CC2) || \ |
emilmont | 77:869cf507173a | 663 | ((FLAG) == TIM_FLAG_CC3) || \ |
emilmont | 77:869cf507173a | 664 | ((FLAG) == TIM_FLAG_CC4) || \ |
emilmont | 77:869cf507173a | 665 | ((FLAG) == TIM_FLAG_COM) || \ |
emilmont | 77:869cf507173a | 666 | ((FLAG) == TIM_FLAG_TRIGGER) || \ |
emilmont | 77:869cf507173a | 667 | ((FLAG) == TIM_FLAG_BREAK) || \ |
emilmont | 77:869cf507173a | 668 | ((FLAG) == TIM_FLAG_CC1OF) || \ |
emilmont | 77:869cf507173a | 669 | ((FLAG) == TIM_FLAG_CC2OF) || \ |
emilmont | 77:869cf507173a | 670 | ((FLAG) == TIM_FLAG_CC3OF) || \ |
emilmont | 77:869cf507173a | 671 | ((FLAG) == TIM_FLAG_CC4OF)) |
emilmont | 77:869cf507173a | 672 | /** |
emilmont | 77:869cf507173a | 673 | * @} |
emilmont | 77:869cf507173a | 674 | */ |
emilmont | 77:869cf507173a | 675 | |
emilmont | 77:869cf507173a | 676 | /** @defgroup TIM_Clock_Source |
emilmont | 77:869cf507173a | 677 | * @{ |
emilmont | 77:869cf507173a | 678 | */ |
emilmont | 77:869cf507173a | 679 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
emilmont | 77:869cf507173a | 680 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
emilmont | 77:869cf507173a | 681 | #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 682 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
emilmont | 77:869cf507173a | 683 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
emilmont | 77:869cf507173a | 684 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
emilmont | 77:869cf507173a | 685 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
emilmont | 77:869cf507173a | 686 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
emilmont | 77:869cf507173a | 687 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
emilmont | 77:869cf507173a | 688 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
emilmont | 77:869cf507173a | 689 | |
emilmont | 77:869cf507173a | 690 | #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ |
emilmont | 77:869cf507173a | 691 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
emilmont | 77:869cf507173a | 692 | ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ |
emilmont | 77:869cf507173a | 693 | ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ |
emilmont | 77:869cf507173a | 694 | ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ |
emilmont | 77:869cf507173a | 695 | ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ |
emilmont | 77:869cf507173a | 696 | ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ |
emilmont | 77:869cf507173a | 697 | ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ |
emilmont | 77:869cf507173a | 698 | ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ |
emilmont | 77:869cf507173a | 699 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) |
emilmont | 77:869cf507173a | 700 | /** |
emilmont | 77:869cf507173a | 701 | * @} |
emilmont | 77:869cf507173a | 702 | */ |
emilmont | 77:869cf507173a | 703 | |
emilmont | 77:869cf507173a | 704 | /** @defgroup TIM_Clock_Polarity |
emilmont | 77:869cf507173a | 705 | * @{ |
emilmont | 77:869cf507173a | 706 | */ |
emilmont | 77:869cf507173a | 707 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
emilmont | 77:869cf507173a | 708 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
emilmont | 77:869cf507173a | 709 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
emilmont | 77:869cf507173a | 710 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
emilmont | 77:869cf507173a | 711 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
emilmont | 77:869cf507173a | 712 | |
emilmont | 77:869cf507173a | 713 | #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ |
emilmont | 77:869cf507173a | 714 | ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
emilmont | 77:869cf507173a | 715 | ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ |
emilmont | 77:869cf507173a | 716 | ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ |
emilmont | 77:869cf507173a | 717 | ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
emilmont | 77:869cf507173a | 718 | /** |
emilmont | 77:869cf507173a | 719 | * @} |
emilmont | 77:869cf507173a | 720 | */ |
emilmont | 77:869cf507173a | 721 | /** @defgroup TIM_Clock_Prescaler |
emilmont | 77:869cf507173a | 722 | * @{ |
emilmont | 77:869cf507173a | 723 | */ |
emilmont | 77:869cf507173a | 724 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
emilmont | 77:869cf507173a | 725 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
emilmont | 77:869cf507173a | 726 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
emilmont | 77:869cf507173a | 727 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
emilmont | 77:869cf507173a | 728 | |
emilmont | 77:869cf507173a | 729 | #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ |
emilmont | 77:869cf507173a | 730 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ |
emilmont | 77:869cf507173a | 731 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ |
emilmont | 77:869cf507173a | 732 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) |
emilmont | 77:869cf507173a | 733 | /** |
emilmont | 77:869cf507173a | 734 | * @} |
emilmont | 77:869cf507173a | 735 | */ |
emilmont | 77:869cf507173a | 736 | /** @defgroup TIM_Clock_Filter |
emilmont | 77:869cf507173a | 737 | * @{ |
emilmont | 77:869cf507173a | 738 | */ |
emilmont | 77:869cf507173a | 739 | |
emilmont | 77:869cf507173a | 740 | #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) |
emilmont | 77:869cf507173a | 741 | /** |
emilmont | 77:869cf507173a | 742 | * @} |
emilmont | 77:869cf507173a | 743 | */ |
emilmont | 77:869cf507173a | 744 | |
emilmont | 77:869cf507173a | 745 | /** @defgroup TIM_ClearInput_Source |
emilmont | 77:869cf507173a | 746 | * @{ |
emilmont | 77:869cf507173a | 747 | */ |
emilmont | 77:869cf507173a | 748 | #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) |
emilmont | 77:869cf507173a | 749 | #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 750 | |
emilmont | 77:869cf507173a | 751 | #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ |
emilmont | 77:869cf507173a | 752 | ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) |
emilmont | 77:869cf507173a | 753 | /** |
emilmont | 77:869cf507173a | 754 | * @} |
emilmont | 77:869cf507173a | 755 | */ |
emilmont | 77:869cf507173a | 756 | |
emilmont | 77:869cf507173a | 757 | /** @defgroup TIM_ClearInput_Polarity |
emilmont | 77:869cf507173a | 758 | * @{ |
emilmont | 77:869cf507173a | 759 | */ |
emilmont | 77:869cf507173a | 760 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
emilmont | 77:869cf507173a | 761 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
emilmont | 77:869cf507173a | 762 | #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
emilmont | 77:869cf507173a | 763 | ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
emilmont | 77:869cf507173a | 764 | /** |
emilmont | 77:869cf507173a | 765 | * @} |
emilmont | 77:869cf507173a | 766 | */ |
emilmont | 77:869cf507173a | 767 | |
emilmont | 77:869cf507173a | 768 | /** @defgroup TIM_ClearInput_Prescaler |
emilmont | 77:869cf507173a | 769 | * @{ |
emilmont | 77:869cf507173a | 770 | */ |
emilmont | 77:869cf507173a | 771 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
emilmont | 77:869cf507173a | 772 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
emilmont | 77:869cf507173a | 773 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
emilmont | 77:869cf507173a | 774 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
emilmont | 77:869cf507173a | 775 | #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
emilmont | 77:869cf507173a | 776 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
emilmont | 77:869cf507173a | 777 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
emilmont | 77:869cf507173a | 778 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) |
emilmont | 77:869cf507173a | 779 | /** |
emilmont | 77:869cf507173a | 780 | * @} |
emilmont | 77:869cf507173a | 781 | */ |
emilmont | 77:869cf507173a | 782 | |
emilmont | 77:869cf507173a | 783 | /** @defgroup TIM_ClearInput_Filter |
emilmont | 77:869cf507173a | 784 | * @{ |
emilmont | 77:869cf507173a | 785 | */ |
emilmont | 77:869cf507173a | 786 | |
emilmont | 77:869cf507173a | 787 | #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
emilmont | 77:869cf507173a | 788 | /** |
emilmont | 77:869cf507173a | 789 | * @} |
emilmont | 77:869cf507173a | 790 | */ |
emilmont | 77:869cf507173a | 791 | |
emilmont | 77:869cf507173a | 792 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state |
emilmont | 77:869cf507173a | 793 | * @{ |
emilmont | 77:869cf507173a | 794 | */ |
emilmont | 77:869cf507173a | 795 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) |
emilmont | 77:869cf507173a | 796 | #define TIM_OSSR_DISABLE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 797 | |
emilmont | 77:869cf507173a | 798 | #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ |
emilmont | 77:869cf507173a | 799 | ((STATE) == TIM_OSSR_DISABLE)) |
emilmont | 77:869cf507173a | 800 | /** |
emilmont | 77:869cf507173a | 801 | * @} |
emilmont | 77:869cf507173a | 802 | */ |
emilmont | 77:869cf507173a | 803 | |
emilmont | 77:869cf507173a | 804 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state |
emilmont | 77:869cf507173a | 805 | * @{ |
emilmont | 77:869cf507173a | 806 | */ |
emilmont | 77:869cf507173a | 807 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) |
emilmont | 77:869cf507173a | 808 | #define TIM_OSSI_DISABLE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 809 | |
emilmont | 77:869cf507173a | 810 | #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ |
emilmont | 77:869cf507173a | 811 | ((STATE) == TIM_OSSI_DISABLE)) |
emilmont | 77:869cf507173a | 812 | /** |
emilmont | 77:869cf507173a | 813 | * @} |
emilmont | 77:869cf507173a | 814 | */ |
emilmont | 77:869cf507173a | 815 | /** @defgroup TIM_Lock_level |
emilmont | 77:869cf507173a | 816 | * @{ |
emilmont | 77:869cf507173a | 817 | */ |
emilmont | 77:869cf507173a | 818 | #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 819 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) |
emilmont | 77:869cf507173a | 820 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) |
emilmont | 77:869cf507173a | 821 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) |
emilmont | 77:869cf507173a | 822 | |
emilmont | 77:869cf507173a | 823 | #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ |
emilmont | 77:869cf507173a | 824 | ((LEVEL) == TIM_LOCKLEVEL_1) || \ |
emilmont | 77:869cf507173a | 825 | ((LEVEL) == TIM_LOCKLEVEL_2) || \ |
emilmont | 77:869cf507173a | 826 | ((LEVEL) == TIM_LOCKLEVEL_3)) |
emilmont | 77:869cf507173a | 827 | /** |
emilmont | 77:869cf507173a | 828 | * @} |
emilmont | 77:869cf507173a | 829 | */ |
emilmont | 77:869cf507173a | 830 | /** @defgroup TIM_Break_Input_enable_disable |
emilmont | 77:869cf507173a | 831 | * @{ |
emilmont | 77:869cf507173a | 832 | */ |
emilmont | 77:869cf507173a | 833 | #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) |
emilmont | 77:869cf507173a | 834 | #define TIM_BREAK_DISABLE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 835 | |
emilmont | 77:869cf507173a | 836 | #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ |
emilmont | 77:869cf507173a | 837 | ((STATE) == TIM_BREAK_DISABLE)) |
emilmont | 77:869cf507173a | 838 | /** |
emilmont | 77:869cf507173a | 839 | * @} |
emilmont | 77:869cf507173a | 840 | */ |
emilmont | 77:869cf507173a | 841 | /** @defgroup TIM_Break_Polarity |
emilmont | 77:869cf507173a | 842 | * @{ |
emilmont | 77:869cf507173a | 843 | */ |
emilmont | 77:869cf507173a | 844 | #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 845 | #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) |
emilmont | 77:869cf507173a | 846 | |
emilmont | 77:869cf507173a | 847 | #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ |
emilmont | 77:869cf507173a | 848 | ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) |
emilmont | 77:869cf507173a | 849 | /** |
emilmont | 77:869cf507173a | 850 | * @} |
emilmont | 77:869cf507173a | 851 | */ |
emilmont | 77:869cf507173a | 852 | /** @defgroup TIM_AOE_Bit_Set_Reset |
emilmont | 77:869cf507173a | 853 | * @{ |
emilmont | 77:869cf507173a | 854 | */ |
emilmont | 77:869cf507173a | 855 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) |
emilmont | 77:869cf507173a | 856 | #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 857 | |
emilmont | 77:869cf507173a | 858 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
emilmont | 77:869cf507173a | 859 | ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) |
emilmont | 77:869cf507173a | 860 | /** |
emilmont | 77:869cf507173a | 861 | * @} |
emilmont | 77:869cf507173a | 862 | */ |
emilmont | 77:869cf507173a | 863 | |
emilmont | 77:869cf507173a | 864 | /** @defgroup TIM_Master_Mode_Selection |
emilmont | 77:869cf507173a | 865 | * @{ |
emilmont | 77:869cf507173a | 866 | */ |
emilmont | 77:869cf507173a | 867 | #define TIM_TRGO_RESET ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 868 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
emilmont | 77:869cf507173a | 869 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
emilmont | 77:869cf507173a | 870 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
emilmont | 77:869cf507173a | 871 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
emilmont | 77:869cf507173a | 872 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
emilmont | 77:869cf507173a | 873 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
emilmont | 77:869cf507173a | 874 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
emilmont | 77:869cf507173a | 875 | |
emilmont | 77:869cf507173a | 876 | #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ |
emilmont | 77:869cf507173a | 877 | ((SOURCE) == TIM_TRGO_ENABLE) || \ |
emilmont | 77:869cf507173a | 878 | ((SOURCE) == TIM_TRGO_UPDATE) || \ |
emilmont | 77:869cf507173a | 879 | ((SOURCE) == TIM_TRGO_OC1) || \ |
emilmont | 77:869cf507173a | 880 | ((SOURCE) == TIM_TRGO_OC1REF) || \ |
emilmont | 77:869cf507173a | 881 | ((SOURCE) == TIM_TRGO_OC2REF) || \ |
emilmont | 77:869cf507173a | 882 | ((SOURCE) == TIM_TRGO_OC3REF) || \ |
emilmont | 77:869cf507173a | 883 | ((SOURCE) == TIM_TRGO_OC4REF)) |
emilmont | 77:869cf507173a | 884 | |
emilmont | 77:869cf507173a | 885 | |
emilmont | 77:869cf507173a | 886 | /** |
emilmont | 77:869cf507173a | 887 | * @} |
emilmont | 77:869cf507173a | 888 | */ |
emilmont | 77:869cf507173a | 889 | /** @defgroup TIM_Slave_Mode |
emilmont | 77:869cf507173a | 890 | * @{ |
emilmont | 77:869cf507173a | 891 | */ |
emilmont | 77:869cf507173a | 892 | #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 893 | #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) |
emilmont | 77:869cf507173a | 894 | #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) |
emilmont | 77:869cf507173a | 895 | #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) |
emilmont | 77:869cf507173a | 896 | #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) |
emilmont | 77:869cf507173a | 897 | |
emilmont | 77:869cf507173a | 898 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ |
emilmont | 77:869cf507173a | 899 | ((MODE) == TIM_SLAVEMODE_GATED) || \ |
emilmont | 77:869cf507173a | 900 | ((MODE) == TIM_SLAVEMODE_RESET) || \ |
emilmont | 77:869cf507173a | 901 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ |
emilmont | 77:869cf507173a | 902 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) |
emilmont | 77:869cf507173a | 903 | /** |
emilmont | 77:869cf507173a | 904 | * @} |
emilmont | 77:869cf507173a | 905 | */ |
emilmont | 77:869cf507173a | 906 | |
emilmont | 77:869cf507173a | 907 | /** @defgroup TIM_Master_Slave_Mode |
emilmont | 77:869cf507173a | 908 | * @{ |
emilmont | 77:869cf507173a | 909 | */ |
emilmont | 77:869cf507173a | 910 | |
emilmont | 77:869cf507173a | 911 | #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) |
emilmont | 77:869cf507173a | 912 | #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 913 | #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
emilmont | 77:869cf507173a | 914 | ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) |
emilmont | 77:869cf507173a | 915 | /** |
emilmont | 77:869cf507173a | 916 | * @} |
emilmont | 77:869cf507173a | 917 | */ |
emilmont | 77:869cf507173a | 918 | /** @defgroup TIM_Trigger_Selection |
emilmont | 77:869cf507173a | 919 | * @{ |
emilmont | 77:869cf507173a | 920 | */ |
emilmont | 77:869cf507173a | 921 | |
emilmont | 77:869cf507173a | 922 | #define TIM_TS_ITR0 ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 923 | #define TIM_TS_ITR1 ((uint32_t)0x0010) |
emilmont | 77:869cf507173a | 924 | #define TIM_TS_ITR2 ((uint32_t)0x0020) |
emilmont | 77:869cf507173a | 925 | #define TIM_TS_ITR3 ((uint32_t)0x0030) |
emilmont | 77:869cf507173a | 926 | #define TIM_TS_TI1F_ED ((uint32_t)0x0040) |
emilmont | 77:869cf507173a | 927 | #define TIM_TS_TI1FP1 ((uint32_t)0x0050) |
emilmont | 77:869cf507173a | 928 | #define TIM_TS_TI2FP2 ((uint32_t)0x0060) |
emilmont | 77:869cf507173a | 929 | #define TIM_TS_ETRF ((uint32_t)0x0070) |
emilmont | 77:869cf507173a | 930 | #define TIM_TS_NONE ((uint32_t)0xFFFF) |
emilmont | 77:869cf507173a | 931 | #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
emilmont | 77:869cf507173a | 932 | ((SELECTION) == TIM_TS_ITR1) || \ |
emilmont | 77:869cf507173a | 933 | ((SELECTION) == TIM_TS_ITR2) || \ |
emilmont | 77:869cf507173a | 934 | ((SELECTION) == TIM_TS_ITR3) || \ |
emilmont | 77:869cf507173a | 935 | ((SELECTION) == TIM_TS_TI1F_ED) || \ |
emilmont | 77:869cf507173a | 936 | ((SELECTION) == TIM_TS_TI1FP1) || \ |
emilmont | 77:869cf507173a | 937 | ((SELECTION) == TIM_TS_TI2FP2) || \ |
emilmont | 77:869cf507173a | 938 | ((SELECTION) == TIM_TS_ETRF)) |
emilmont | 77:869cf507173a | 939 | #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
emilmont | 77:869cf507173a | 940 | ((SELECTION) == TIM_TS_ITR1) || \ |
emilmont | 77:869cf507173a | 941 | ((SELECTION) == TIM_TS_ITR2) || \ |
emilmont | 77:869cf507173a | 942 | ((SELECTION) == TIM_TS_ITR3)) |
emilmont | 77:869cf507173a | 943 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
emilmont | 77:869cf507173a | 944 | ((SELECTION) == TIM_TS_ITR1) || \ |
emilmont | 77:869cf507173a | 945 | ((SELECTION) == TIM_TS_ITR2) || \ |
emilmont | 77:869cf507173a | 946 | ((SELECTION) == TIM_TS_ITR3) || \ |
emilmont | 77:869cf507173a | 947 | ((SELECTION) == TIM_TS_NONE)) |
emilmont | 77:869cf507173a | 948 | /** |
emilmont | 77:869cf507173a | 949 | * @} |
emilmont | 77:869cf507173a | 950 | */ |
emilmont | 77:869cf507173a | 951 | |
emilmont | 77:869cf507173a | 952 | /** @defgroup TIM_Trigger_Polarity |
emilmont | 77:869cf507173a | 953 | * @{ |
emilmont | 77:869cf507173a | 954 | */ |
emilmont | 77:869cf507173a | 955 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
emilmont | 77:869cf507173a | 956 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
emilmont | 77:869cf507173a | 957 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
emilmont | 77:869cf507173a | 958 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
emilmont | 77:869cf507173a | 959 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
emilmont | 77:869cf507173a | 960 | |
emilmont | 77:869cf507173a | 961 | #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
emilmont | 77:869cf507173a | 962 | ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
emilmont | 77:869cf507173a | 963 | ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ |
emilmont | 77:869cf507173a | 964 | ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
emilmont | 77:869cf507173a | 965 | ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
emilmont | 77:869cf507173a | 966 | /** |
emilmont | 77:869cf507173a | 967 | * @} |
emilmont | 77:869cf507173a | 968 | */ |
emilmont | 77:869cf507173a | 969 | |
emilmont | 77:869cf507173a | 970 | /** @defgroup TIM_Trigger_Prescaler |
emilmont | 77:869cf507173a | 971 | * @{ |
emilmont | 77:869cf507173a | 972 | */ |
emilmont | 77:869cf507173a | 973 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
emilmont | 77:869cf507173a | 974 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
emilmont | 77:869cf507173a | 975 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
emilmont | 77:869cf507173a | 976 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
emilmont | 77:869cf507173a | 977 | |
emilmont | 77:869cf507173a | 978 | #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ |
emilmont | 77:869cf507173a | 979 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ |
emilmont | 77:869cf507173a | 980 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ |
emilmont | 77:869cf507173a | 981 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) |
emilmont | 77:869cf507173a | 982 | /** |
emilmont | 77:869cf507173a | 983 | * @} |
emilmont | 77:869cf507173a | 984 | */ |
emilmont | 77:869cf507173a | 985 | |
emilmont | 77:869cf507173a | 986 | /** @defgroup TIM_Trigger_Filter |
emilmont | 77:869cf507173a | 987 | * @{ |
emilmont | 77:869cf507173a | 988 | */ |
emilmont | 77:869cf507173a | 989 | |
emilmont | 77:869cf507173a | 990 | #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) |
emilmont | 77:869cf507173a | 991 | /** |
emilmont | 77:869cf507173a | 992 | * @} |
emilmont | 77:869cf507173a | 993 | */ |
emilmont | 77:869cf507173a | 994 | |
emilmont | 77:869cf507173a | 995 | /** @defgroup TIM_TI1_Selection |
emilmont | 77:869cf507173a | 996 | * @{ |
emilmont | 77:869cf507173a | 997 | */ |
emilmont | 77:869cf507173a | 998 | |
emilmont | 77:869cf507173a | 999 | #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 1000 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
emilmont | 77:869cf507173a | 1001 | |
emilmont | 77:869cf507173a | 1002 | #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ |
emilmont | 77:869cf507173a | 1003 | ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) |
emilmont | 77:869cf507173a | 1004 | |
emilmont | 77:869cf507173a | 1005 | /** |
emilmont | 77:869cf507173a | 1006 | * @} |
emilmont | 77:869cf507173a | 1007 | */ |
emilmont | 77:869cf507173a | 1008 | |
emilmont | 77:869cf507173a | 1009 | /** @defgroup TIM_DMA_Base_address |
emilmont | 77:869cf507173a | 1010 | * @{ |
emilmont | 77:869cf507173a | 1011 | */ |
emilmont | 77:869cf507173a | 1012 | |
emilmont | 77:869cf507173a | 1013 | #define TIM_DMABase_CR1 (0x00000000) |
emilmont | 77:869cf507173a | 1014 | #define TIM_DMABase_CR2 (0x00000001) |
emilmont | 77:869cf507173a | 1015 | #define TIM_DMABase_SMCR (0x00000002) |
emilmont | 77:869cf507173a | 1016 | #define TIM_DMABase_DIER (0x00000003) |
emilmont | 77:869cf507173a | 1017 | #define TIM_DMABase_SR (0x00000004) |
emilmont | 77:869cf507173a | 1018 | #define TIM_DMABase_EGR (0x00000005) |
emilmont | 77:869cf507173a | 1019 | #define TIM_DMABase_CCMR1 (0x00000006) |
emilmont | 77:869cf507173a | 1020 | #define TIM_DMABase_CCMR2 (0x00000007) |
emilmont | 77:869cf507173a | 1021 | #define TIM_DMABase_CCER (0x00000008) |
emilmont | 77:869cf507173a | 1022 | #define TIM_DMABase_CNT (0x00000009) |
emilmont | 77:869cf507173a | 1023 | #define TIM_DMABase_PSC (0x0000000A) |
emilmont | 77:869cf507173a | 1024 | #define TIM_DMABase_ARR (0x0000000B) |
emilmont | 77:869cf507173a | 1025 | #define TIM_DMABase_RCR (0x0000000C) |
emilmont | 77:869cf507173a | 1026 | #define TIM_DMABase_CCR1 (0x0000000D) |
emilmont | 77:869cf507173a | 1027 | #define TIM_DMABase_CCR2 (0x0000000E) |
emilmont | 77:869cf507173a | 1028 | #define TIM_DMABase_CCR3 (0x0000000F) |
emilmont | 77:869cf507173a | 1029 | #define TIM_DMABase_CCR4 (0x00000010) |
emilmont | 77:869cf507173a | 1030 | #define TIM_DMABase_BDTR (0x00000011) |
emilmont | 77:869cf507173a | 1031 | #define TIM_DMABase_DCR (0x00000012) |
emilmont | 77:869cf507173a | 1032 | #define TIM_DMABase_OR (0x00000013) |
emilmont | 77:869cf507173a | 1033 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ |
emilmont | 77:869cf507173a | 1034 | ((BASE) == TIM_DMABase_CR2) || \ |
emilmont | 77:869cf507173a | 1035 | ((BASE) == TIM_DMABase_SMCR) || \ |
emilmont | 77:869cf507173a | 1036 | ((BASE) == TIM_DMABase_DIER) || \ |
emilmont | 77:869cf507173a | 1037 | ((BASE) == TIM_DMABase_SR) || \ |
emilmont | 77:869cf507173a | 1038 | ((BASE) == TIM_DMABase_EGR) || \ |
emilmont | 77:869cf507173a | 1039 | ((BASE) == TIM_DMABase_CCMR1) || \ |
emilmont | 77:869cf507173a | 1040 | ((BASE) == TIM_DMABase_CCMR2) || \ |
emilmont | 77:869cf507173a | 1041 | ((BASE) == TIM_DMABase_CCER) || \ |
emilmont | 77:869cf507173a | 1042 | ((BASE) == TIM_DMABase_CNT) || \ |
emilmont | 77:869cf507173a | 1043 | ((BASE) == TIM_DMABase_PSC) || \ |
emilmont | 77:869cf507173a | 1044 | ((BASE) == TIM_DMABase_ARR) || \ |
emilmont | 77:869cf507173a | 1045 | ((BASE) == TIM_DMABase_RCR) || \ |
emilmont | 77:869cf507173a | 1046 | ((BASE) == TIM_DMABase_CCR1) || \ |
emilmont | 77:869cf507173a | 1047 | ((BASE) == TIM_DMABase_CCR2) || \ |
emilmont | 77:869cf507173a | 1048 | ((BASE) == TIM_DMABase_CCR3) || \ |
emilmont | 77:869cf507173a | 1049 | ((BASE) == TIM_DMABase_CCR4) || \ |
emilmont | 77:869cf507173a | 1050 | ((BASE) == TIM_DMABase_BDTR) || \ |
emilmont | 77:869cf507173a | 1051 | ((BASE) == TIM_DMABase_DCR) || \ |
emilmont | 77:869cf507173a | 1052 | ((BASE) == TIM_DMABase_OR)) |
emilmont | 77:869cf507173a | 1053 | /** |
emilmont | 77:869cf507173a | 1054 | * @} |
emilmont | 77:869cf507173a | 1055 | */ |
emilmont | 77:869cf507173a | 1056 | |
emilmont | 77:869cf507173a | 1057 | /** @defgroup TIM_DMA_Burst_Length |
emilmont | 77:869cf507173a | 1058 | * @{ |
emilmont | 77:869cf507173a | 1059 | */ |
emilmont | 77:869cf507173a | 1060 | |
emilmont | 77:869cf507173a | 1061 | #define TIM_DMABurstLength_1Transfer (0x00000000) |
emilmont | 77:869cf507173a | 1062 | #define TIM_DMABurstLength_2Transfers (0x00000100) |
emilmont | 77:869cf507173a | 1063 | #define TIM_DMABurstLength_3Transfers (0x00000200) |
emilmont | 77:869cf507173a | 1064 | #define TIM_DMABurstLength_4Transfers (0x00000300) |
emilmont | 77:869cf507173a | 1065 | #define TIM_DMABurstLength_5Transfers (0x00000400) |
emilmont | 77:869cf507173a | 1066 | #define TIM_DMABurstLength_6Transfers (0x00000500) |
emilmont | 77:869cf507173a | 1067 | #define TIM_DMABurstLength_7Transfers (0x00000600) |
emilmont | 77:869cf507173a | 1068 | #define TIM_DMABurstLength_8Transfers (0x00000700) |
emilmont | 77:869cf507173a | 1069 | #define TIM_DMABurstLength_9Transfers (0x00000800) |
emilmont | 77:869cf507173a | 1070 | #define TIM_DMABurstLength_10Transfers (0x00000900) |
emilmont | 77:869cf507173a | 1071 | #define TIM_DMABurstLength_11Transfers (0x00000A00) |
emilmont | 77:869cf507173a | 1072 | #define TIM_DMABurstLength_12Transfers (0x00000B00) |
emilmont | 77:869cf507173a | 1073 | #define TIM_DMABurstLength_13Transfers (0x00000C00) |
emilmont | 77:869cf507173a | 1074 | #define TIM_DMABurstLength_14Transfers (0x00000D00) |
emilmont | 77:869cf507173a | 1075 | #define TIM_DMABurstLength_15Transfers (0x00000E00) |
emilmont | 77:869cf507173a | 1076 | #define TIM_DMABurstLength_16Transfers (0x00000F00) |
emilmont | 77:869cf507173a | 1077 | #define TIM_DMABurstLength_17Transfers (0x00001000) |
emilmont | 77:869cf507173a | 1078 | #define TIM_DMABurstLength_18Transfers (0x00001100) |
emilmont | 77:869cf507173a | 1079 | #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ |
emilmont | 77:869cf507173a | 1080 | ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ |
emilmont | 77:869cf507173a | 1081 | ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ |
emilmont | 77:869cf507173a | 1082 | ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ |
emilmont | 77:869cf507173a | 1083 | ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ |
emilmont | 77:869cf507173a | 1084 | ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ |
emilmont | 77:869cf507173a | 1085 | ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ |
emilmont | 77:869cf507173a | 1086 | ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ |
emilmont | 77:869cf507173a | 1087 | ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ |
emilmont | 77:869cf507173a | 1088 | ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ |
emilmont | 77:869cf507173a | 1089 | ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ |
emilmont | 77:869cf507173a | 1090 | ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ |
emilmont | 77:869cf507173a | 1091 | ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ |
emilmont | 77:869cf507173a | 1092 | ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ |
emilmont | 77:869cf507173a | 1093 | ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ |
emilmont | 77:869cf507173a | 1094 | ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ |
emilmont | 77:869cf507173a | 1095 | ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ |
emilmont | 77:869cf507173a | 1096 | ((LENGTH) == TIM_DMABurstLength_18Transfers)) |
emilmont | 77:869cf507173a | 1097 | /** |
emilmont | 77:869cf507173a | 1098 | * @} |
emilmont | 77:869cf507173a | 1099 | */ |
emilmont | 77:869cf507173a | 1100 | /** @defgroup TIM_Input_Capture_Filer_Value |
emilmont | 77:869cf507173a | 1101 | * @{ |
emilmont | 77:869cf507173a | 1102 | */ |
emilmont | 77:869cf507173a | 1103 | |
emilmont | 77:869cf507173a | 1104 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
emilmont | 77:869cf507173a | 1105 | /** |
emilmont | 77:869cf507173a | 1106 | * @} |
emilmont | 77:869cf507173a | 1107 | */ |
emilmont | 77:869cf507173a | 1108 | |
emilmont | 77:869cf507173a | 1109 | /** @defgroup DMA_Handle_index |
emilmont | 77:869cf507173a | 1110 | * @{ |
emilmont | 77:869cf507173a | 1111 | */ |
emilmont | 77:869cf507173a | 1112 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ |
emilmont | 77:869cf507173a | 1113 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
emilmont | 77:869cf507173a | 1114 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
emilmont | 77:869cf507173a | 1115 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
emilmont | 77:869cf507173a | 1116 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
emilmont | 77:869cf507173a | 1117 | #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ |
emilmont | 77:869cf507173a | 1118 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ |
emilmont | 77:869cf507173a | 1119 | /** |
emilmont | 77:869cf507173a | 1120 | * @} |
emilmont | 77:869cf507173a | 1121 | */ |
emilmont | 77:869cf507173a | 1122 | |
emilmont | 77:869cf507173a | 1123 | /** @defgroup Channel_CC_State |
emilmont | 77:869cf507173a | 1124 | * @{ |
emilmont | 77:869cf507173a | 1125 | */ |
emilmont | 77:869cf507173a | 1126 | #define TIM_CCx_ENABLE ((uint32_t)0x0001) |
emilmont | 77:869cf507173a | 1127 | #define TIM_CCx_DISABLE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 1128 | #define TIM_CCxN_ENABLE ((uint32_t)0x0004) |
emilmont | 77:869cf507173a | 1129 | #define TIM_CCxN_DISABLE ((uint32_t)0x0000) |
emilmont | 77:869cf507173a | 1130 | /** |
emilmont | 77:869cf507173a | 1131 | * @} |
emilmont | 77:869cf507173a | 1132 | */ |
emilmont | 77:869cf507173a | 1133 | |
emilmont | 77:869cf507173a | 1134 | /** |
emilmont | 77:869cf507173a | 1135 | * @} |
emilmont | 77:869cf507173a | 1136 | */ |
emilmont | 77:869cf507173a | 1137 | |
emilmont | 77:869cf507173a | 1138 | /* Exported macro ------------------------------------------------------------*/ |
emilmont | 77:869cf507173a | 1139 | |
emilmont | 77:869cf507173a | 1140 | /** |
emilmont | 77:869cf507173a | 1141 | * @brief Enable the TIM peripheral. |
emilmont | 77:869cf507173a | 1142 | * @param __HANDLE__: TIM handle |
emilmont | 77:869cf507173a | 1143 | * @retval None |
emilmont | 77:869cf507173a | 1144 | */ |
emilmont | 77:869cf507173a | 1145 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
emilmont | 77:869cf507173a | 1146 | |
emilmont | 77:869cf507173a | 1147 | /** |
emilmont | 77:869cf507173a | 1148 | * @brief Enable the TIM main Output. |
emilmont | 77:869cf507173a | 1149 | * @param __HANDLE__: TIM handle |
emilmont | 77:869cf507173a | 1150 | * @retval None |
emilmont | 77:869cf507173a | 1151 | */ |
emilmont | 77:869cf507173a | 1152 | #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) |
emilmont | 77:869cf507173a | 1153 | |
emilmont | 77:869cf507173a | 1154 | |
emilmont | 77:869cf507173a | 1155 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
emilmont | 77:869cf507173a | 1156 | channels have been disabled */ |
emilmont | 77:869cf507173a | 1157 | #define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
emilmont | 77:869cf507173a | 1158 | #define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) |
emilmont | 77:869cf507173a | 1159 | |
emilmont | 77:869cf507173a | 1160 | /** |
emilmont | 77:869cf507173a | 1161 | * @brief Disable the TIM peripheral. |
emilmont | 77:869cf507173a | 1162 | * @param __HANDLE__: TIM handle |
emilmont | 77:869cf507173a | 1163 | * @retval None |
emilmont | 77:869cf507173a | 1164 | */ |
emilmont | 77:869cf507173a | 1165 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
emilmont | 77:869cf507173a | 1166 | do { \ |
emilmont | 77:869cf507173a | 1167 | if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ |
emilmont | 77:869cf507173a | 1168 | { \ |
emilmont | 77:869cf507173a | 1169 | if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \ |
emilmont | 77:869cf507173a | 1170 | { \ |
emilmont | 77:869cf507173a | 1171 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
emilmont | 77:869cf507173a | 1172 | } \ |
emilmont | 77:869cf507173a | 1173 | } \ |
emilmont | 77:869cf507173a | 1174 | } while(0) |
emilmont | 77:869cf507173a | 1175 | |
emilmont | 77:869cf507173a | 1176 | /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN |
emilmont | 77:869cf507173a | 1177 | channels have been disabled */ |
emilmont | 77:869cf507173a | 1178 | /** |
emilmont | 77:869cf507173a | 1179 | * @brief Disable the TIM main Output. |
emilmont | 77:869cf507173a | 1180 | * @param __HANDLE__: TIM handle |
emilmont | 77:869cf507173a | 1181 | * @retval None |
emilmont | 77:869cf507173a | 1182 | */ |
emilmont | 77:869cf507173a | 1183 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
emilmont | 77:869cf507173a | 1184 | do { \ |
emilmont | 77:869cf507173a | 1185 | if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ |
emilmont | 77:869cf507173a | 1186 | { \ |
emilmont | 77:869cf507173a | 1187 | if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \ |
emilmont | 77:869cf507173a | 1188 | { \ |
emilmont | 77:869cf507173a | 1189 | (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ |
emilmont | 77:869cf507173a | 1190 | } \ |
emilmont | 77:869cf507173a | 1191 | } \ |
emilmont | 77:869cf507173a | 1192 | } while(0) |
emilmont | 77:869cf507173a | 1193 | |
emilmont | 77:869cf507173a | 1194 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
emilmont | 77:869cf507173a | 1195 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
emilmont | 77:869cf507173a | 1196 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
emilmont | 77:869cf507173a | 1197 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
emilmont | 77:869cf507173a | 1198 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
emilmont | 77:869cf507173a | 1199 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__)) |
emilmont | 77:869cf507173a | 1200 | |
emilmont | 77:869cf507173a | 1201 | #define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
emilmont | 77:869cf507173a | 1202 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR &= ~(__INTERRUPT__)) |
emilmont | 77:869cf507173a | 1203 | |
emilmont | 77:869cf507173a | 1204 | #define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
emilmont | 77:869cf507173a | 1205 | #define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC |= (__PRESC__)) |
emilmont | 77:869cf507173a | 1206 | |
emilmont | 77:869cf507173a | 1207 | #define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
emilmont | 77:869cf507173a | 1208 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
emilmont | 77:869cf507173a | 1209 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ |
emilmont | 77:869cf507173a | 1210 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
emilmont | 77:869cf507173a | 1211 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) |
emilmont | 77:869cf507173a | 1212 | |
emilmont | 77:869cf507173a | 1213 | #define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \ |
emilmont | 77:869cf507173a | 1214 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ |
emilmont | 77:869cf507173a | 1215 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ |
emilmont | 77:869cf507173a | 1216 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ |
emilmont | 77:869cf507173a | 1217 | ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) |
emilmont | 77:869cf507173a | 1218 | |
emilmont | 77:869cf507173a | 1219 | /** |
emilmont | 77:869cf507173a | 1220 | * @brief Sets the TIM Capture Compare Register value on runtime without |
emilmont | 77:869cf507173a | 1221 | * calling another time ConfigChannel function. |
emilmont | 77:869cf507173a | 1222 | * @param __HANDLE__: TIM handle. |
emilmont | 77:869cf507173a | 1223 | * @param __CHANNEL__ : TIM Channels to be configured. |
emilmont | 77:869cf507173a | 1224 | * This parameter can be one of the following values: |
emilmont | 77:869cf507173a | 1225 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
emilmont | 77:869cf507173a | 1226 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
emilmont | 77:869cf507173a | 1227 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
emilmont | 77:869cf507173a | 1228 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
emilmont | 77:869cf507173a | 1229 | * @param __COMPARE__: specifies the Capture Compare register new value. |
emilmont | 77:869cf507173a | 1230 | * @retval None |
emilmont | 77:869cf507173a | 1231 | */ |
emilmont | 77:869cf507173a | 1232 | #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
emilmont | 77:869cf507173a | 1233 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) |
emilmont | 77:869cf507173a | 1234 | |
emilmont | 77:869cf507173a | 1235 | /** |
emilmont | 77:869cf507173a | 1236 | * @brief Sets the TIM Counter Register value on runtime. |
emilmont | 77:869cf507173a | 1237 | * @param __HANDLE__: TIM handle. |
emilmont | 77:869cf507173a | 1238 | * @param __COUNTER__: specifies the Counter register new value. |
emilmont | 77:869cf507173a | 1239 | * @retval None |
emilmont | 77:869cf507173a | 1240 | */ |
emilmont | 77:869cf507173a | 1241 | #define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
emilmont | 77:869cf507173a | 1242 | |
emilmont | 77:869cf507173a | 1243 | /** |
emilmont | 77:869cf507173a | 1244 | * @brief Sets the TIM Autoreload Register value on runtime without calling |
emilmont | 77:869cf507173a | 1245 | * another time any Init function. |
emilmont | 77:869cf507173a | 1246 | * @param __HANDLE__: TIM handle. |
emilmont | 77:869cf507173a | 1247 | * @param __AUTORELOAD__: specifies the Counter register new value. |
emilmont | 77:869cf507173a | 1248 | * @retval None |
emilmont | 77:869cf507173a | 1249 | */ |
emilmont | 77:869cf507173a | 1250 | #define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ |
emilmont | 77:869cf507173a | 1251 | do{ \ |
emilmont | 77:869cf507173a | 1252 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
emilmont | 77:869cf507173a | 1253 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
emilmont | 77:869cf507173a | 1254 | } while(0) |
emilmont | 77:869cf507173a | 1255 | |
emilmont | 77:869cf507173a | 1256 | /** |
emilmont | 77:869cf507173a | 1257 | * @brief Sets the TIM Clock Division value on runtime without calling |
emilmont | 77:869cf507173a | 1258 | * another time any Init function. |
emilmont | 77:869cf507173a | 1259 | * @param __HANDLE__: TIM handle. |
emilmont | 77:869cf507173a | 1260 | * @param __CKD__: specifies the clock division value. |
emilmont | 77:869cf507173a | 1261 | * This parameter can be one of the following value: |
emilmont | 77:869cf507173a | 1262 | * @arg TIM_CLOCKDIVISION_DIV1 |
emilmont | 77:869cf507173a | 1263 | * @arg TIM_CLOCKDIVISION_DIV2 |
emilmont | 77:869cf507173a | 1264 | * @arg TIM_CLOCKDIVISION_DIV4 |
emilmont | 77:869cf507173a | 1265 | * @retval None |
emilmont | 77:869cf507173a | 1266 | */ |
emilmont | 77:869cf507173a | 1267 | #define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \ |
emilmont | 77:869cf507173a | 1268 | do{ \ |
emilmont | 77:869cf507173a | 1269 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ |
emilmont | 77:869cf507173a | 1270 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
emilmont | 77:869cf507173a | 1271 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
emilmont | 77:869cf507173a | 1272 | } while(0) |
emilmont | 77:869cf507173a | 1273 | |
emilmont | 77:869cf507173a | 1274 | /** |
emilmont | 77:869cf507173a | 1275 | * @brief Sets the TIM Input Capture prescaler on runtime without calling |
emilmont | 77:869cf507173a | 1276 | * another time HAL_TIM_IC_ConfigChannel() function. |
emilmont | 77:869cf507173a | 1277 | * @param __HANDLE__: TIM handle. |
emilmont | 77:869cf507173a | 1278 | * @param __CHANNEL__ : TIM Channels to be configured. |
emilmont | 77:869cf507173a | 1279 | * This parameter can be one of the following values: |
emilmont | 77:869cf507173a | 1280 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
emilmont | 77:869cf507173a | 1281 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
emilmont | 77:869cf507173a | 1282 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
emilmont | 77:869cf507173a | 1283 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
emilmont | 77:869cf507173a | 1284 | * @param __ICPSC__: specifies the Input Capture4 prescaler new value. |
emilmont | 77:869cf507173a | 1285 | * This parameter can be one of the following values: |
emilmont | 77:869cf507173a | 1286 | * @arg TIM_ICPSC_DIV1: no prescaler |
emilmont | 77:869cf507173a | 1287 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
emilmont | 77:869cf507173a | 1288 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
emilmont | 77:869cf507173a | 1289 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
emilmont | 77:869cf507173a | 1290 | * @retval None |
emilmont | 77:869cf507173a | 1291 | */ |
emilmont | 77:869cf507173a | 1292 | #define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
emilmont | 77:869cf507173a | 1293 | do{ \ |
emilmont | 77:869cf507173a | 1294 | __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \ |
emilmont | 77:869cf507173a | 1295 | __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
emilmont | 77:869cf507173a | 1296 | } while(0) |
emilmont | 77:869cf507173a | 1297 | |
emilmont | 77:869cf507173a | 1298 | /** |
emilmont | 77:869cf507173a | 1299 | * @} |
emilmont | 77:869cf507173a | 1300 | */ |
emilmont | 77:869cf507173a | 1301 | |
emilmont | 77:869cf507173a | 1302 | /* Include TIM HAL Extension module */ |
emilmont | 77:869cf507173a | 1303 | #include "stm32f4xx_hal_tim_ex.h" |
emilmont | 77:869cf507173a | 1304 | |
emilmont | 77:869cf507173a | 1305 | /* Exported functions --------------------------------------------------------*/ |
emilmont | 77:869cf507173a | 1306 | |
emilmont | 77:869cf507173a | 1307 | /* Time Base functions ********************************************************/ |
emilmont | 77:869cf507173a | 1308 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1309 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1310 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1311 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1312 | /* Blocking mode: Polling */ |
emilmont | 77:869cf507173a | 1313 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1314 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1315 | /* Non-Blocking mode: Interrupt */ |
emilmont | 77:869cf507173a | 1316 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1317 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1318 | /* Non-Blocking mode: DMA */ |
emilmont | 77:869cf507173a | 1319 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
emilmont | 77:869cf507173a | 1320 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1321 | |
emilmont | 77:869cf507173a | 1322 | /* Timer Output Compare functions **********************************************/ |
emilmont | 77:869cf507173a | 1323 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1324 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1325 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1326 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1327 | /* Blocking mode: Polling */ |
emilmont | 77:869cf507173a | 1328 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1329 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1330 | /* Non-Blocking mode: Interrupt */ |
emilmont | 77:869cf507173a | 1331 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1332 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1333 | /* Non-Blocking mode: DMA */ |
emilmont | 77:869cf507173a | 1334 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
emilmont | 77:869cf507173a | 1335 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1336 | |
emilmont | 77:869cf507173a | 1337 | /* Timer PWM functions *********************************************************/ |
emilmont | 77:869cf507173a | 1338 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1339 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1340 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1341 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1342 | /* Blocking mode: Polling */ |
emilmont | 77:869cf507173a | 1343 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1344 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1345 | /* Non-Blocking mode: Interrupt */ |
emilmont | 77:869cf507173a | 1346 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1347 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1348 | /* Non-Blocking mode: DMA */ |
emilmont | 77:869cf507173a | 1349 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
emilmont | 77:869cf507173a | 1350 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1351 | |
emilmont | 77:869cf507173a | 1352 | /* Timer Input Capture functions ***********************************************/ |
emilmont | 77:869cf507173a | 1353 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1354 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1355 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1356 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1357 | /* Blocking mode: Polling */ |
emilmont | 77:869cf507173a | 1358 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1359 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1360 | /* Non-Blocking mode: Interrupt */ |
emilmont | 77:869cf507173a | 1361 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1362 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1363 | /* Non-Blocking mode: DMA */ |
emilmont | 77:869cf507173a | 1364 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
emilmont | 77:869cf507173a | 1365 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1366 | |
emilmont | 77:869cf507173a | 1367 | /* Timer One Pulse functions ***************************************************/ |
emilmont | 77:869cf507173a | 1368 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
emilmont | 77:869cf507173a | 1369 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1370 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1371 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1372 | /* Blocking mode: Polling */ |
emilmont | 77:869cf507173a | 1373 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
emilmont | 77:869cf507173a | 1374 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
emilmont | 77:869cf507173a | 1375 | |
emilmont | 77:869cf507173a | 1376 | /* Non-Blocking mode: Interrupt */ |
emilmont | 77:869cf507173a | 1377 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
emilmont | 77:869cf507173a | 1378 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
emilmont | 77:869cf507173a | 1379 | |
emilmont | 77:869cf507173a | 1380 | /* Timer Encoder functions *****************************************************/ |
emilmont | 77:869cf507173a | 1381 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
emilmont | 77:869cf507173a | 1382 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1383 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1384 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1385 | /* Blocking mode: Polling */ |
emilmont | 77:869cf507173a | 1386 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1387 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1388 | /* Non-Blocking mode: Interrupt */ |
emilmont | 77:869cf507173a | 1389 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1390 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1391 | /* Non-Blocking mode: DMA */ |
emilmont | 77:869cf507173a | 1392 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
emilmont | 77:869cf507173a | 1393 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1394 | |
emilmont | 77:869cf507173a | 1395 | /* Interrupt Handler functions **********************************************/ |
emilmont | 77:869cf507173a | 1396 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1397 | |
emilmont | 77:869cf507173a | 1398 | /* Control functions *********************************************************/ |
emilmont | 77:869cf507173a | 1399 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
emilmont | 77:869cf507173a | 1400 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
emilmont | 77:869cf507173a | 1401 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
emilmont | 77:869cf507173a | 1402 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
emilmont | 77:869cf507173a | 1403 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
emilmont | 77:869cf507173a | 1404 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
emilmont | 77:869cf507173a | 1405 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
emilmont | 77:869cf507173a | 1406 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
emilmont | 77:869cf507173a | 1407 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
emilmont | 77:869cf507173a | 1408 | uint32_t *BurstBuffer, uint32_t BurstLength); |
emilmont | 77:869cf507173a | 1409 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
emilmont | 77:869cf507173a | 1410 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
emilmont | 77:869cf507173a | 1411 | uint32_t *BurstBuffer, uint32_t BurstLength); |
emilmont | 77:869cf507173a | 1412 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
emilmont | 77:869cf507173a | 1413 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
emilmont | 77:869cf507173a | 1414 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
emilmont | 77:869cf507173a | 1415 | |
emilmont | 77:869cf507173a | 1416 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
bogdanm | 81:7d30d6019079 | 1417 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
bogdanm | 81:7d30d6019079 | 1418 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
bogdanm | 81:7d30d6019079 | 1419 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
bogdanm | 81:7d30d6019079 | 1420 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
bogdanm | 81:7d30d6019079 | 1421 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
bogdanm | 81:7d30d6019079 | 1422 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1423 | |
emilmont | 77:869cf507173a | 1424 | /* Peripheral State functions **************************************************/ |
emilmont | 77:869cf507173a | 1425 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1426 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1427 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1428 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1429 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1430 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
emilmont | 77:869cf507173a | 1431 | |
emilmont | 77:869cf507173a | 1432 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); |
emilmont | 77:869cf507173a | 1433 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
emilmont | 77:869cf507173a | 1434 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
emilmont | 77:869cf507173a | 1435 | void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
emilmont | 77:869cf507173a | 1436 | void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma); |
emilmont | 77:869cf507173a | 1437 | void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
emilmont | 77:869cf507173a | 1438 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); |
emilmont | 77:869cf507173a | 1439 | |
emilmont | 77:869cf507173a | 1440 | /** |
emilmont | 77:869cf507173a | 1441 | * @} |
emilmont | 77:869cf507173a | 1442 | */ |
emilmont | 77:869cf507173a | 1443 | |
emilmont | 77:869cf507173a | 1444 | /** |
emilmont | 77:869cf507173a | 1445 | * @} |
emilmont | 77:869cf507173a | 1446 | */ |
emilmont | 77:869cf507173a | 1447 | |
emilmont | 77:869cf507173a | 1448 | #ifdef __cplusplus |
emilmont | 77:869cf507173a | 1449 | } |
emilmont | 77:869cf507173a | 1450 | #endif |
emilmont | 77:869cf507173a | 1451 | |
emilmont | 77:869cf507173a | 1452 | #endif /* __STM32F4xx_HAL_TIM_H */ |
emilmont | 77:869cf507173a | 1453 | |
emilmont | 77:869cf507173a | 1454 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |