Ricardo Benitez / mbed

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TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h@99:dbbf35b96557, 2015-05-13 (annotated)

Committer:
Kojto
Date:
Wed May 13 08:08:21 2015 +0200
Revision:
99:dbbf35b96557
Parent:
90:cb3d968589d8
Child:
106:ba1f97679dad
Release 99 of the mbed library



Changes:

 - new targets - MAXWSNENV, DISCO_L053C8

 - STM32F4xx - ST Cube driver

 - KSDK mcu - SPI timing fix

 - Nordic - update to softdevice s130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_dma.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 99:dbbf35b96557 5 * @version V1.3.0
Kojto 99:dbbf35b96557 6 * @date 09-March-2015
emilmont 77:869cf507173a 7 * @brief Header file of DMA HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_DMA_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_DMA_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
emilmont 77:869cf507173a 52
emilmont 77:869cf507173a 53 /** @addtogroup DMA
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
bogdanm 85:024bf7f99721 57 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 58
Kojto 99:dbbf35b96557 59 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 99:dbbf35b96557 60 * @brief DMA Exported Types
Kojto 99:dbbf35b96557 61 * @{
Kojto 99:dbbf35b96557 62 */
Kojto 99:dbbf35b96557 63
emilmont 77:869cf507173a 64 /**
bogdanm 85:024bf7f99721 65 * @brief DMA Configuration Structure definition
emilmont 77:869cf507173a 66 */
emilmont 77:869cf507173a 67 typedef struct
emilmont 77:869cf507173a 68 {
emilmont 77:869cf507173a 69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
emilmont 77:869cf507173a 70 This parameter can be a value of @ref DMA_Channel_selection */
bogdanm 85:024bf7f99721 71
emilmont 77:869cf507173a 72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
emilmont 77:869cf507173a 73 from memory to memory or from peripheral to memory.
emilmont 77:869cf507173a 74 This parameter can be a value of @ref DMA_Data_transfer_direction */
emilmont 77:869cf507173a 75
emilmont 77:869cf507173a 76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 85:024bf7f99721 77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 85:024bf7f99721 78
emilmont 77:869cf507173a 79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
emilmont 77:869cf507173a 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 85:024bf7f99721 81
emilmont 77:869cf507173a 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 85:024bf7f99721 83 This parameter can be a value of @ref DMA_Peripheral_data_size */
emilmont 77:869cf507173a 84
emilmont 77:869cf507173a 85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
emilmont 77:869cf507173a 86 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 85:024bf7f99721 87
emilmont 77:869cf507173a 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
emilmont 77:869cf507173a 89 This parameter can be a value of @ref DMA_mode
emilmont 77:869cf507173a 90 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 85:024bf7f99721 91 data transfer is configured on the selected Stream */
emilmont 77:869cf507173a 92
emilmont 77:869cf507173a 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
emilmont 77:869cf507173a 94 This parameter can be a value of @ref DMA_Priority_level */
emilmont 77:869cf507173a 95
emilmont 77:869cf507173a 96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
emilmont 77:869cf507173a 97 This parameter can be a value of @ref DMA_FIFO_direct_mode
emilmont 77:869cf507173a 98 @note The Direct mode (FIFO mode disabled) cannot be used if the
emilmont 77:869cf507173a 99 memory-to-memory data transfer is configured on the selected stream */
bogdanm 85:024bf7f99721 100
emilmont 77:869cf507173a 101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
emilmont 77:869cf507173a 102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
bogdanm 85:024bf7f99721 103
emilmont 77:869cf507173a 104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
Kojto 99:dbbf35b96557 105 It specifies the amount of data to be transferred in a single non interruptible
bogdanm 85:024bf7f99721 106 transaction.
emilmont 77:869cf507173a 107 This parameter can be a value of @ref DMA_Memory_burst
emilmont 77:869cf507173a 108 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 85:024bf7f99721 109
emilmont 77:869cf507173a 110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
emilmont 77:869cf507173a 111 It specifies the amount of data to be transferred in a single non interruptable
emilmont 77:869cf507173a 112 transaction.
emilmont 77:869cf507173a 113 This parameter can be a value of @ref DMA_Peripheral_burst
emilmont 77:869cf507173a 114 @note The burst mode is possible only if the address Increment mode is enabled. */
emilmont 77:869cf507173a 115 }DMA_InitTypeDef;
emilmont 77:869cf507173a 116
Kojto 99:dbbf35b96557 117
emilmont 77:869cf507173a 118 /**
bogdanm 85:024bf7f99721 119 * @brief HAL DMA State structures definition
bogdanm 85:024bf7f99721 120 */
emilmont 77:869cf507173a 121 typedef enum
emilmont 77:869cf507173a 122 {
bogdanm 85:024bf7f99721 123 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
emilmont 77:869cf507173a 124 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
emilmont 77:869cf507173a 125 HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
bogdanm 85:024bf7f99721 126 HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
emilmont 77:869cf507173a 127 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
bogdanm 85:024bf7f99721 128 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
emilmont 77:869cf507173a 129 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
emilmont 77:869cf507173a 130 HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
bogdanm 85:024bf7f99721 131 HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
bogdanm 85:024bf7f99721 132 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
emilmont 77:869cf507173a 133 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
emilmont 77:869cf507173a 134 }HAL_DMA_StateTypeDef;
emilmont 77:869cf507173a 135
emilmont 77:869cf507173a 136 /**
bogdanm 85:024bf7f99721 137 * @brief HAL DMA Error Code structure definition
bogdanm 85:024bf7f99721 138 */
emilmont 77:869cf507173a 139 typedef enum
emilmont 77:869cf507173a 140 {
emilmont 77:869cf507173a 141 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
emilmont 77:869cf507173a 142 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
emilmont 77:869cf507173a 143 }HAL_DMA_LevelCompleteTypeDef;
emilmont 77:869cf507173a 144
emilmont 77:869cf507173a 145 /**
bogdanm 85:024bf7f99721 146 * @brief DMA handle Structure definition
bogdanm 85:024bf7f99721 147 */
emilmont 77:869cf507173a 148 typedef struct __DMA_HandleTypeDef
bogdanm 85:024bf7f99721 149 {
emilmont 77:869cf507173a 150 DMA_Stream_TypeDef *Instance; /*!< Register base address */
bogdanm 85:024bf7f99721 151
emilmont 77:869cf507173a 152 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 85:024bf7f99721 153
emilmont 77:869cf507173a 154 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 85:024bf7f99721 155
emilmont 77:869cf507173a 156 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 85:024bf7f99721 157
emilmont 77:869cf507173a 158 void *Parent; /*!< Parent object state */
bogdanm 85:024bf7f99721 159
emilmont 77:869cf507173a 160 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 85:024bf7f99721 161
emilmont 77:869cf507173a 162 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 85:024bf7f99721 163
emilmont 77:869cf507173a 164 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
bogdanm 85:024bf7f99721 165
emilmont 77:869cf507173a 166 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
emilmont 77:869cf507173a 167
Kojto 99:dbbf35b96557 168 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 85:024bf7f99721 169 }DMA_HandleTypeDef;
emilmont 77:869cf507173a 170
Kojto 99:dbbf35b96557 171 /**
Kojto 99:dbbf35b96557 172 * @}
Kojto 99:dbbf35b96557 173 */
Kojto 99:dbbf35b96557 174
emilmont 77:869cf507173a 175 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 176
Kojto 99:dbbf35b96557 177 /** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto 99:dbbf35b96557 178 * @brief DMA Exported constants
emilmont 77:869cf507173a 179 * @{
emilmont 77:869cf507173a 180 */
emilmont 77:869cf507173a 181
Kojto 99:dbbf35b96557 182 /** @defgroup DMA_Error_Code DMA Error Code
Kojto 99:dbbf35b96557 183 * @brief DMA Error Code
emilmont 77:869cf507173a 184 * @{
emilmont 77:869cf507173a 185 */
emilmont 77:869cf507173a 186 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
emilmont 77:869cf507173a 187 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 85:024bf7f99721 188 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
emilmont 77:869cf507173a 189 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
emilmont 77:869cf507173a 190 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
emilmont 77:869cf507173a 191 /**
emilmont 77:869cf507173a 192 * @}
emilmont 77:869cf507173a 193 */
emilmont 77:869cf507173a 194
Kojto 99:dbbf35b96557 195 /** @defgroup DMA_Channel_selection DMA Channel selection
Kojto 99:dbbf35b96557 196 * @brief DMA channel selection
emilmont 77:869cf507173a 197 * @{
emilmont 77:869cf507173a 198 */
emilmont 77:869cf507173a 199 #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
emilmont 77:869cf507173a 200 #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
emilmont 77:869cf507173a 201 #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
emilmont 77:869cf507173a 202 #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
emilmont 77:869cf507173a 203 #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
emilmont 77:869cf507173a 204 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
emilmont 77:869cf507173a 205 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
emilmont 77:869cf507173a 206 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
emilmont 77:869cf507173a 207 /**
emilmont 77:869cf507173a 208 * @}
emilmont 77:869cf507173a 209 */
emilmont 77:869cf507173a 210
Kojto 99:dbbf35b96557 211 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto 99:dbbf35b96557 212 * @brief DMA data transfer direction
emilmont 77:869cf507173a 213 * @{
emilmont 77:869cf507173a 214 */
emilmont 77:869cf507173a 215 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
emilmont 77:869cf507173a 216 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
emilmont 77:869cf507173a 217 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
emilmont 77:869cf507173a 218 /**
emilmont 77:869cf507173a 219 * @}
Kojto 99:dbbf35b96557 220 */
emilmont 77:869cf507173a 221
Kojto 99:dbbf35b96557 222 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto 99:dbbf35b96557 223 * @brief DMA peripheral incremented mode
emilmont 77:869cf507173a 224 * @{
emilmont 77:869cf507173a 225 */
emilmont 77:869cf507173a 226 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
emilmont 77:869cf507173a 227 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
emilmont 77:869cf507173a 228 /**
emilmont 77:869cf507173a 229 * @}
emilmont 77:869cf507173a 230 */
emilmont 77:869cf507173a 231
Kojto 99:dbbf35b96557 232 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto 99:dbbf35b96557 233 * @brief DMA memory incremented mode
emilmont 77:869cf507173a 234 * @{
emilmont 77:869cf507173a 235 */
emilmont 77:869cf507173a 236 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
emilmont 77:869cf507173a 237 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
emilmont 77:869cf507173a 238 /**
emilmont 77:869cf507173a 239 * @}
emilmont 77:869cf507173a 240 */
emilmont 77:869cf507173a 241
Kojto 99:dbbf35b96557 242 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto 99:dbbf35b96557 243 * @brief DMA peripheral data size
emilmont 77:869cf507173a 244 * @{
emilmont 77:869cf507173a 245 */
emilmont 77:869cf507173a 246 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
emilmont 77:869cf507173a 247 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
emilmont 77:869cf507173a 248 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
emilmont 77:869cf507173a 249 /**
emilmont 77:869cf507173a 250 * @}
emilmont 77:869cf507173a 251 */
emilmont 77:869cf507173a 252
Kojto 99:dbbf35b96557 253 /** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto 99:dbbf35b96557 254 * @brief DMA memory data size
emilmont 77:869cf507173a 255 * @{
emilmont 77:869cf507173a 256 */
emilmont 77:869cf507173a 257 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
emilmont 77:869cf507173a 258 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
emilmont 77:869cf507173a 259 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
emilmont 77:869cf507173a 260 /**
emilmont 77:869cf507173a 261 * @}
emilmont 77:869cf507173a 262 */
emilmont 77:869cf507173a 263
Kojto 99:dbbf35b96557 264 /** @defgroup DMA_mode DMA mode
Kojto 99:dbbf35b96557 265 * @brief DMA mode
emilmont 77:869cf507173a 266 * @{
emilmont 77:869cf507173a 267 */
emilmont 77:869cf507173a 268 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
emilmont 77:869cf507173a 269 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
emilmont 77:869cf507173a 270 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
emilmont 77:869cf507173a 271 /**
emilmont 77:869cf507173a 272 * @}
emilmont 77:869cf507173a 273 */
emilmont 77:869cf507173a 274
Kojto 99:dbbf35b96557 275 /** @defgroup DMA_Priority_level DMA Priority level
Kojto 99:dbbf35b96557 276 * @brief DMA priority levels
emilmont 77:869cf507173a 277 * @{
emilmont 77:869cf507173a 278 */
emilmont 77:869cf507173a 279 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
emilmont 77:869cf507173a 280 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
emilmont 77:869cf507173a 281 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
emilmont 77:869cf507173a 282 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
emilmont 77:869cf507173a 283 /**
emilmont 77:869cf507173a 284 * @}
emilmont 77:869cf507173a 285 */
emilmont 77:869cf507173a 286
Kojto 99:dbbf35b96557 287 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
Kojto 99:dbbf35b96557 288 * @brief DMA FIFO direct mode
emilmont 77:869cf507173a 289 * @{
emilmont 77:869cf507173a 290 */
emilmont 77:869cf507173a 291 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
emilmont 77:869cf507173a 292 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
emilmont 77:869cf507173a 293 /**
emilmont 77:869cf507173a 294 * @}
emilmont 77:869cf507173a 295 */
emilmont 77:869cf507173a 296
Kojto 99:dbbf35b96557 297 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
Kojto 99:dbbf35b96557 298 * @brief DMA FIFO level
emilmont 77:869cf507173a 299 * @{
emilmont 77:869cf507173a 300 */
emilmont 77:869cf507173a 301 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
emilmont 77:869cf507173a 302 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
emilmont 77:869cf507173a 303 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
emilmont 77:869cf507173a 304 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
emilmont 77:869cf507173a 305 /**
emilmont 77:869cf507173a 306 * @}
emilmont 77:869cf507173a 307 */
emilmont 77:869cf507173a 308
Kojto 99:dbbf35b96557 309 /** @defgroup DMA_Memory_burst DMA Memory burst
Kojto 99:dbbf35b96557 310 * @brief DMA memory burst
emilmont 77:869cf507173a 311 * @{
emilmont 77:869cf507173a 312 */
emilmont 77:869cf507173a 313 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
emilmont 77:869cf507173a 314 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
emilmont 77:869cf507173a 315 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
emilmont 77:869cf507173a 316 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
emilmont 77:869cf507173a 317 /**
emilmont 77:869cf507173a 318 * @}
emilmont 77:869cf507173a 319 */
emilmont 77:869cf507173a 320
Kojto 99:dbbf35b96557 321 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
Kojto 99:dbbf35b96557 322 * @brief DMA peripheral burst
emilmont 77:869cf507173a 323 * @{
emilmont 77:869cf507173a 324 */
emilmont 77:869cf507173a 325 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
emilmont 77:869cf507173a 326 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
emilmont 77:869cf507173a 327 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
emilmont 77:869cf507173a 328 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
emilmont 77:869cf507173a 329 /**
emilmont 77:869cf507173a 330 * @}
emilmont 77:869cf507173a 331 */
emilmont 77:869cf507173a 332
Kojto 99:dbbf35b96557 333 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto 99:dbbf35b96557 334 * @brief DMA interrupts definition
emilmont 77:869cf507173a 335 * @{
emilmont 77:869cf507173a 336 */
emilmont 77:869cf507173a 337 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
emilmont 77:869cf507173a 338 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
emilmont 77:869cf507173a 339 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
emilmont 77:869cf507173a 340 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
emilmont 77:869cf507173a 341 #define DMA_IT_FE ((uint32_t)0x00000080)
emilmont 77:869cf507173a 342 /**
emilmont 77:869cf507173a 343 * @}
emilmont 77:869cf507173a 344 */
emilmont 77:869cf507173a 345
Kojto 99:dbbf35b96557 346 /** @defgroup DMA_flag_definitions DMA flag definitions
Kojto 99:dbbf35b96557 347 * @brief DMA flag definitions
emilmont 77:869cf507173a 348 * @{
emilmont 77:869cf507173a 349 */
emilmont 77:869cf507173a 350 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
emilmont 77:869cf507173a 351 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
emilmont 77:869cf507173a 352 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 353 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 354 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 355 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 356 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 357 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 358 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 359 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 360 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 361 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 362 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 363 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 364 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 365 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 366 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 367 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 368 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 369 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 370 /**
emilmont 77:869cf507173a 371 * @}
emilmont 77:869cf507173a 372 */
Kojto 99:dbbf35b96557 373
emilmont 77:869cf507173a 374 /**
emilmont 77:869cf507173a 375 * @}
emilmont 77:869cf507173a 376 */
Kojto 99:dbbf35b96557 377
emilmont 77:869cf507173a 378 /* Exported macro ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 379
bogdanm 85:024bf7f99721 380 /** @brief Reset DMA handle state
bogdanm 85:024bf7f99721 381 * @param __HANDLE__: specifies the DMA handle.
bogdanm 85:024bf7f99721 382 * @retval None
bogdanm 85:024bf7f99721 383 */
bogdanm 85:024bf7f99721 384 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 85:024bf7f99721 385
emilmont 77:869cf507173a 386 /**
emilmont 77:869cf507173a 387 * @brief Return the current DMA Stream FIFO filled level.
emilmont 77:869cf507173a 388 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 389 * @retval The FIFO filling state.
emilmont 77:869cf507173a 390 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
emilmont 77:869cf507173a 391 * and not empty.
emilmont 77:869cf507173a 392 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
emilmont 77:869cf507173a 393 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
emilmont 77:869cf507173a 394 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
emilmont 77:869cf507173a 395 * - DMA_FIFOStatus_Empty: when FIFO is empty
emilmont 77:869cf507173a 396 * - DMA_FIFOStatus_Full: when FIFO is full
emilmont 77:869cf507173a 397 */
emilmont 77:869cf507173a 398 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
emilmont 77:869cf507173a 399
emilmont 77:869cf507173a 400 /**
emilmont 77:869cf507173a 401 * @brief Enable the specified DMA Stream.
emilmont 77:869cf507173a 402 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 403 * @retval None
emilmont 77:869cf507173a 404 */
emilmont 77:869cf507173a 405 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
emilmont 77:869cf507173a 406
emilmont 77:869cf507173a 407 /**
emilmont 77:869cf507173a 408 * @brief Disable the specified DMA Stream.
emilmont 77:869cf507173a 409 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 410 * @retval None
emilmont 77:869cf507173a 411 */
emilmont 77:869cf507173a 412 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
emilmont 77:869cf507173a 413
emilmont 77:869cf507173a 414 /* Interrupt & Flag management */
emilmont 77:869cf507173a 415
emilmont 77:869cf507173a 416 /**
emilmont 77:869cf507173a 417 * @brief Return the current DMA Stream transfer complete flag.
emilmont 77:869cf507173a 418 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 419 * @retval The specified transfer complete flag index.
emilmont 77:869cf507173a 420 */
emilmont 77:869cf507173a 421 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
emilmont 77:869cf507173a 422 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
emilmont 77:869cf507173a 423 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
emilmont 77:869cf507173a 424 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
emilmont 77:869cf507173a 425 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
emilmont 77:869cf507173a 426 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
emilmont 77:869cf507173a 427 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
emilmont 77:869cf507173a 428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
emilmont 77:869cf507173a 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
emilmont 77:869cf507173a 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
emilmont 77:869cf507173a 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
emilmont 77:869cf507173a 432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
emilmont 77:869cf507173a 433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
emilmont 77:869cf507173a 434 DMA_FLAG_TCIF3_7)
emilmont 77:869cf507173a 435
emilmont 77:869cf507173a 436 /**
emilmont 77:869cf507173a 437 * @brief Return the current DMA Stream half transfer complete flag.
emilmont 77:869cf507173a 438 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 439 * @retval The specified half transfer complete flag index.
emilmont 77:869cf507173a 440 */
emilmont 77:869cf507173a 441 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
emilmont 77:869cf507173a 442 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
emilmont 77:869cf507173a 443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
emilmont 77:869cf507173a 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
emilmont 77:869cf507173a 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
emilmont 77:869cf507173a 446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
emilmont 77:869cf507173a 447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
emilmont 77:869cf507173a 448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
emilmont 77:869cf507173a 449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
emilmont 77:869cf507173a 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
emilmont 77:869cf507173a 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
emilmont 77:869cf507173a 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
emilmont 77:869cf507173a 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
emilmont 77:869cf507173a 454 DMA_FLAG_HTIF3_7)
emilmont 77:869cf507173a 455
emilmont 77:869cf507173a 456 /**
emilmont 77:869cf507173a 457 * @brief Return the current DMA Stream transfer error flag.
emilmont 77:869cf507173a 458 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 459 * @retval The specified transfer error flag index.
emilmont 77:869cf507173a 460 */
emilmont 77:869cf507173a 461 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
emilmont 77:869cf507173a 462 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
emilmont 77:869cf507173a 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
emilmont 77:869cf507173a 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
emilmont 77:869cf507173a 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
emilmont 77:869cf507173a 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
emilmont 77:869cf507173a 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
emilmont 77:869cf507173a 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
emilmont 77:869cf507173a 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
emilmont 77:869cf507173a 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
emilmont 77:869cf507173a 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
emilmont 77:869cf507173a 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
emilmont 77:869cf507173a 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
emilmont 77:869cf507173a 474 DMA_FLAG_TEIF3_7)
emilmont 77:869cf507173a 475
emilmont 77:869cf507173a 476 /**
emilmont 77:869cf507173a 477 * @brief Return the current DMA Stream FIFO error flag.
emilmont 77:869cf507173a 478 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 479 * @retval The specified FIFO error flag index.
emilmont 77:869cf507173a 480 */
emilmont 77:869cf507173a 481 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
emilmont 77:869cf507173a 482 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
emilmont 77:869cf507173a 483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
emilmont 77:869cf507173a 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
emilmont 77:869cf507173a 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
emilmont 77:869cf507173a 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
emilmont 77:869cf507173a 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
emilmont 77:869cf507173a 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
emilmont 77:869cf507173a 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
emilmont 77:869cf507173a 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
emilmont 77:869cf507173a 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
emilmont 77:869cf507173a 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
emilmont 77:869cf507173a 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
emilmont 77:869cf507173a 494 DMA_FLAG_FEIF3_7)
emilmont 77:869cf507173a 495
emilmont 77:869cf507173a 496 /**
emilmont 77:869cf507173a 497 * @brief Return the current DMA Stream direct mode error flag.
emilmont 77:869cf507173a 498 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 499 * @retval The specified direct mode error flag index.
emilmont 77:869cf507173a 500 */
emilmont 77:869cf507173a 501 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
emilmont 77:869cf507173a 502 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
emilmont 77:869cf507173a 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
emilmont 77:869cf507173a 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
emilmont 77:869cf507173a 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
emilmont 77:869cf507173a 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
emilmont 77:869cf507173a 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
emilmont 77:869cf507173a 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
emilmont 77:869cf507173a 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
emilmont 77:869cf507173a 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
emilmont 77:869cf507173a 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
emilmont 77:869cf507173a 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
emilmont 77:869cf507173a 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
emilmont 77:869cf507173a 514 DMA_FLAG_DMEIF3_7)
emilmont 77:869cf507173a 515
emilmont 77:869cf507173a 516 /**
emilmont 77:869cf507173a 517 * @brief Get the DMA Stream pending flags.
emilmont 77:869cf507173a 518 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 519 * @param __FLAG__: Get the specified flag.
emilmont 77:869cf507173a 520 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 521 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
emilmont 77:869cf507173a 522 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
emilmont 77:869cf507173a 523 * @arg DMA_FLAG_TEIFx: Transfer error flag.
emilmont 77:869cf507173a 524 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
emilmont 77:869cf507173a 525 * @arg DMA_FLAG_FEIFx: FIFO error flag.
emilmont 77:869cf507173a 526 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
emilmont 77:869cf507173a 527 * @retval The state of FLAG (SET or RESET).
emilmont 77:869cf507173a 528 */
emilmont 77:869cf507173a 529 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
emilmont 77:869cf507173a 530 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
emilmont 77:869cf507173a 531 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
emilmont 77:869cf507173a 532 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
emilmont 77:869cf507173a 533
emilmont 77:869cf507173a 534 /**
emilmont 77:869cf507173a 535 * @brief Clear the DMA Stream pending flags.
emilmont 77:869cf507173a 536 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 537 * @param __FLAG__: specifies the flag to clear.
emilmont 77:869cf507173a 538 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 539 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
emilmont 77:869cf507173a 540 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
emilmont 77:869cf507173a 541 * @arg DMA_FLAG_TEIFx: Transfer error flag.
emilmont 77:869cf507173a 542 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
emilmont 77:869cf507173a 543 * @arg DMA_FLAG_FEIFx: FIFO error flag.
emilmont 77:869cf507173a 544 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
emilmont 77:869cf507173a 545 * @retval None
emilmont 77:869cf507173a 546 */
emilmont 77:869cf507173a 547 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
Kojto 90:cb3d968589d8 548 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
Kojto 90:cb3d968589d8 549 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
Kojto 90:cb3d968589d8 550 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
emilmont 77:869cf507173a 551
emilmont 77:869cf507173a 552 /**
emilmont 77:869cf507173a 553 * @brief Enable the specified DMA Stream interrupts.
emilmont 77:869cf507173a 554 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 555 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
emilmont 77:869cf507173a 556 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 557 * @arg DMA_IT_TC: Transfer complete interrupt mask.
emilmont 77:869cf507173a 558 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
emilmont 77:869cf507173a 559 * @arg DMA_IT_TE: Transfer error interrupt mask.
emilmont 77:869cf507173a 560 * @arg DMA_IT_FE: FIFO error interrupt mask.
emilmont 77:869cf507173a 561 * @arg DMA_IT_DME: Direct mode error interrupt.
emilmont 77:869cf507173a 562 * @retval None
emilmont 77:869cf507173a 563 */
emilmont 77:869cf507173a 564 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
emilmont 77:869cf507173a 565 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
emilmont 77:869cf507173a 566
emilmont 77:869cf507173a 567 /**
emilmont 77:869cf507173a 568 * @brief Disable the specified DMA Stream interrupts.
emilmont 77:869cf507173a 569 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 570 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
emilmont 77:869cf507173a 571 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 572 * @arg DMA_IT_TC: Transfer complete interrupt mask.
emilmont 77:869cf507173a 573 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
emilmont 77:869cf507173a 574 * @arg DMA_IT_TE: Transfer error interrupt mask.
emilmont 77:869cf507173a 575 * @arg DMA_IT_FE: FIFO error interrupt mask.
emilmont 77:869cf507173a 576 * @arg DMA_IT_DME: Direct mode error interrupt.
emilmont 77:869cf507173a 577 * @retval None
emilmont 77:869cf507173a 578 */
emilmont 77:869cf507173a 579 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
emilmont 77:869cf507173a 580 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
emilmont 77:869cf507173a 581
emilmont 77:869cf507173a 582 /**
emilmont 77:869cf507173a 583 * @brief Check whether the specified DMA Stream interrupt has occurred or not.
emilmont 77:869cf507173a 584 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 585 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
emilmont 77:869cf507173a 586 * This parameter can be one of the following values:
emilmont 77:869cf507173a 587 * @arg DMA_IT_TC: Transfer complete interrupt mask.
emilmont 77:869cf507173a 588 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
emilmont 77:869cf507173a 589 * @arg DMA_IT_TE: Transfer error interrupt mask.
emilmont 77:869cf507173a 590 * @arg DMA_IT_FE: FIFO error interrupt mask.
emilmont 77:869cf507173a 591 * @arg DMA_IT_DME: Direct mode error interrupt.
emilmont 77:869cf507173a 592 * @retval The state of DMA_IT.
emilmont 77:869cf507173a 593 */
bogdanm 81:7d30d6019079 594 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
emilmont 77:869cf507173a 595 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
emilmont 77:869cf507173a 596 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
emilmont 77:869cf507173a 597
emilmont 77:869cf507173a 598 /**
emilmont 77:869cf507173a 599 * @brief Writes the number of data units to be transferred on the DMA Stream.
emilmont 77:869cf507173a 600 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 601 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
emilmont 77:869cf507173a 602 * Number of data items depends only on the Peripheral data format.
emilmont 77:869cf507173a 603 *
emilmont 77:869cf507173a 604 * @note If Peripheral data format is Bytes: number of data units is equal
emilmont 77:869cf507173a 605 * to total number of bytes to be transferred.
emilmont 77:869cf507173a 606 *
emilmont 77:869cf507173a 607 * @note If Peripheral data format is Half-Word: number of data units is
emilmont 77:869cf507173a 608 * equal to total number of bytes to be transferred / 2.
emilmont 77:869cf507173a 609 *
emilmont 77:869cf507173a 610 * @note If Peripheral data format is Word: number of data units is equal
emilmont 77:869cf507173a 611 * to total number of bytes to be transferred / 4.
emilmont 77:869cf507173a 612 *
emilmont 77:869cf507173a 613 * @retval The number of remaining data units in the current DMAy Streamx transfer.
emilmont 77:869cf507173a 614 */
emilmont 77:869cf507173a 615 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
emilmont 77:869cf507173a 616
emilmont 77:869cf507173a 617 /**
emilmont 77:869cf507173a 618 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
emilmont 77:869cf507173a 619 * @param __HANDLE__: DMA handle
emilmont 77:869cf507173a 620 *
emilmont 77:869cf507173a 621 * @retval The number of remaining data units in the current DMA Stream transfer.
emilmont 77:869cf507173a 622 */
emilmont 77:869cf507173a 623 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
emilmont 77:869cf507173a 624
emilmont 77:869cf507173a 625
emilmont 77:869cf507173a 626 /* Include DMA HAL Extension module */
emilmont 77:869cf507173a 627 #include "stm32f4xx_hal_dma_ex.h"
emilmont 77:869cf507173a 628
emilmont 77:869cf507173a 629 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 630
Kojto 99:dbbf35b96557 631 /** @defgroup DMA_Exported_Functions DMA Exported Functions
Kojto 99:dbbf35b96557 632 * @brief DMA Exported functions
Kojto 99:dbbf35b96557 633 * @{
Kojto 99:dbbf35b96557 634 */
Kojto 99:dbbf35b96557 635
Kojto 99:dbbf35b96557 636 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 99:dbbf35b96557 637 * @brief Initialization and de-initialization functions
Kojto 99:dbbf35b96557 638 * @{
Kojto 99:dbbf35b96557 639 */
emilmont 77:869cf507173a 640 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 641 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 642 /**
Kojto 99:dbbf35b96557 643 * @}
Kojto 99:dbbf35b96557 644 */
emilmont 77:869cf507173a 645
Kojto 99:dbbf35b96557 646 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
Kojto 99:dbbf35b96557 647 * @brief I/O operation functions
Kojto 99:dbbf35b96557 648 * @{
Kojto 99:dbbf35b96557 649 */
emilmont 77:869cf507173a 650 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
emilmont 77:869cf507173a 651 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
emilmont 77:869cf507173a 652 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 653 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
emilmont 77:869cf507173a 654 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 655 /**
Kojto 99:dbbf35b96557 656 * @}
Kojto 99:dbbf35b96557 657 */
emilmont 77:869cf507173a 658
Kojto 99:dbbf35b96557 659 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
Kojto 99:dbbf35b96557 660 * @brief Peripheral State functions
Kojto 99:dbbf35b96557 661 * @{
Kojto 99:dbbf35b96557 662 */
emilmont 77:869cf507173a 663 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 664 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 665 /**
Kojto 99:dbbf35b96557 666 * @}
Kojto 99:dbbf35b96557 667 */
Kojto 99:dbbf35b96557 668 /**
Kojto 99:dbbf35b96557 669 * @}
Kojto 99:dbbf35b96557 670 */
Kojto 99:dbbf35b96557 671 /* Private Constants -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 672 /** @defgroup DMA_Private_Constants DMA Private Constants
Kojto 99:dbbf35b96557 673 * @brief DMA private defines and constants
Kojto 99:dbbf35b96557 674 * @{
Kojto 99:dbbf35b96557 675 */
Kojto 99:dbbf35b96557 676 /**
Kojto 99:dbbf35b96557 677 * @}
Kojto 99:dbbf35b96557 678 */
Kojto 99:dbbf35b96557 679
Kojto 99:dbbf35b96557 680 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 681 /** @defgroup DMA_Private_Macros DMA Private Macros
Kojto 99:dbbf35b96557 682 * @brief DMA private macros
Kojto 99:dbbf35b96557 683 * @{
Kojto 99:dbbf35b96557 684 */
Kojto 99:dbbf35b96557 685 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
Kojto 99:dbbf35b96557 686 ((CHANNEL) == DMA_CHANNEL_1) || \
Kojto 99:dbbf35b96557 687 ((CHANNEL) == DMA_CHANNEL_2) || \
Kojto 99:dbbf35b96557 688 ((CHANNEL) == DMA_CHANNEL_3) || \
Kojto 99:dbbf35b96557 689 ((CHANNEL) == DMA_CHANNEL_4) || \
Kojto 99:dbbf35b96557 690 ((CHANNEL) == DMA_CHANNEL_5) || \
Kojto 99:dbbf35b96557 691 ((CHANNEL) == DMA_CHANNEL_6) || \
Kojto 99:dbbf35b96557 692 ((CHANNEL) == DMA_CHANNEL_7))
Kojto 99:dbbf35b96557 693
Kojto 99:dbbf35b96557 694 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 99:dbbf35b96557 695 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 99:dbbf35b96557 696 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 99:dbbf35b96557 697
Kojto 99:dbbf35b96557 698 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
Kojto 99:dbbf35b96557 699
Kojto 99:dbbf35b96557 700 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 99:dbbf35b96557 701 ((STATE) == DMA_PINC_DISABLE))
Kojto 99:dbbf35b96557 702
Kojto 99:dbbf35b96557 703 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 99:dbbf35b96557 704 ((STATE) == DMA_MINC_DISABLE))
Kojto 99:dbbf35b96557 705
Kojto 99:dbbf35b96557 706 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 99:dbbf35b96557 707 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 99:dbbf35b96557 708 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 99:dbbf35b96557 709
Kojto 99:dbbf35b96557 710 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 99:dbbf35b96557 711 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 99:dbbf35b96557 712 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 99:dbbf35b96557 713
Kojto 99:dbbf35b96557 714 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 99:dbbf35b96557 715 ((MODE) == DMA_CIRCULAR) || \
Kojto 99:dbbf35b96557 716 ((MODE) == DMA_PFCTRL))
Kojto 99:dbbf35b96557 717
Kojto 99:dbbf35b96557 718 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 99:dbbf35b96557 719 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 99:dbbf35b96557 720 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 99:dbbf35b96557 721 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 99:dbbf35b96557 722
Kojto 99:dbbf35b96557 723 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
Kojto 99:dbbf35b96557 724 ((STATE) == DMA_FIFOMODE_ENABLE))
Kojto 99:dbbf35b96557 725
Kojto 99:dbbf35b96557 726 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
Kojto 99:dbbf35b96557 727 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
Kojto 99:dbbf35b96557 728 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
Kojto 99:dbbf35b96557 729 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
Kojto 99:dbbf35b96557 730
Kojto 99:dbbf35b96557 731 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
Kojto 99:dbbf35b96557 732 ((BURST) == DMA_MBURST_INC4) || \
Kojto 99:dbbf35b96557 733 ((BURST) == DMA_MBURST_INC8) || \
Kojto 99:dbbf35b96557 734 ((BURST) == DMA_MBURST_INC16))
Kojto 99:dbbf35b96557 735
Kojto 99:dbbf35b96557 736 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
Kojto 99:dbbf35b96557 737 ((BURST) == DMA_PBURST_INC4) || \
Kojto 99:dbbf35b96557 738 ((BURST) == DMA_PBURST_INC8) || \
Kojto 99:dbbf35b96557 739 ((BURST) == DMA_PBURST_INC16))
Kojto 99:dbbf35b96557 740 /**
Kojto 99:dbbf35b96557 741 * @}
Kojto 99:dbbf35b96557 742 */
Kojto 99:dbbf35b96557 743
Kojto 99:dbbf35b96557 744 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 745 /** @defgroup DMA_Private_Functions DMA Private Functions
Kojto 99:dbbf35b96557 746 * @brief DMA private functions
Kojto 99:dbbf35b96557 747 * @{
Kojto 99:dbbf35b96557 748 */
Kojto 99:dbbf35b96557 749 /**
Kojto 99:dbbf35b96557 750 * @}
Kojto 99:dbbf35b96557 751 */
emilmont 77:869cf507173a 752
emilmont 77:869cf507173a 753 /**
emilmont 77:869cf507173a 754 * @}
emilmont 77:869cf507173a 755 */
emilmont 77:869cf507173a 756
emilmont 77:869cf507173a 757 /**
emilmont 77:869cf507173a 758 * @}
emilmont 77:869cf507173a 759 */
emilmont 77:869cf507173a 760
emilmont 77:869cf507173a 761 #ifdef __cplusplus
emilmont 77:869cf507173a 762 }
emilmont 77:869cf507173a 763 #endif
emilmont 77:869cf507173a 764
emilmont 77:869cf507173a 765 #endif /* __STM32F4xx_HAL_DMA_H */
emilmont 77:869cf507173a 766
emilmont 77:869cf507173a 767 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/