Ricardo Benitez
meh
Fork of
mbed
by 
mbed official
TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h@77:869cf507173a, 2014-02-14 (annotated)
- Committer:
- emilmont
- Date:
- Fri Feb 14 14:36:43 2014 +0000
- Revision:
- 77:869cf507173a
- Child:
- 81:7d30d6019079
Release 77 of the mbed library
Main changes:
* Add target NUCLEO_F030R8
* Add target NUCLEO_F401RE
* Add target NUCLEO_F103RB
* Add target NUCLEO_L152RE
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 77:869cf507173a | 1 | /** |
| emilmont | 77:869cf507173a | 2 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 3 | * @file stm32f4xx_hal_dma.h |
| emilmont | 77:869cf507173a | 4 | * @author MCD Application Team |
| emilmont | 77:869cf507173a | 5 | * @version V1.0.0RC2 |
| emilmont | 77:869cf507173a | 6 | * @date 04-February-2014 |
| emilmont | 77:869cf507173a | 7 | * @brief Header file of DMA HAL module. |
| emilmont | 77:869cf507173a | 8 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 9 | * @attention |
| emilmont | 77:869cf507173a | 10 | * |
| emilmont | 77:869cf507173a | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| emilmont | 77:869cf507173a | 12 | * |
| emilmont | 77:869cf507173a | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| emilmont | 77:869cf507173a | 14 | * are permitted provided that the following conditions are met: |
| emilmont | 77:869cf507173a | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| emilmont | 77:869cf507173a | 16 | * this list of conditions and the following disclaimer. |
| emilmont | 77:869cf507173a | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| emilmont | 77:869cf507173a | 18 | * this list of conditions and the following disclaimer in the documentation |
| emilmont | 77:869cf507173a | 19 | * and/or other materials provided with the distribution. |
| emilmont | 77:869cf507173a | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| emilmont | 77:869cf507173a | 21 | * may be used to endorse or promote products derived from this software |
| emilmont | 77:869cf507173a | 22 | * without specific prior written permission. |
| emilmont | 77:869cf507173a | 23 | * |
| emilmont | 77:869cf507173a | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| emilmont | 77:869cf507173a | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| emilmont | 77:869cf507173a | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| emilmont | 77:869cf507173a | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| emilmont | 77:869cf507173a | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| emilmont | 77:869cf507173a | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| emilmont | 77:869cf507173a | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| emilmont | 77:869cf507173a | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| emilmont | 77:869cf507173a | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| emilmont | 77:869cf507173a | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| emilmont | 77:869cf507173a | 34 | * |
| emilmont | 77:869cf507173a | 35 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 36 | */ |
| emilmont | 77:869cf507173a | 37 | |
| emilmont | 77:869cf507173a | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| emilmont | 77:869cf507173a | 39 | #ifndef __STM32F4xx_HAL_DMA_H |
| emilmont | 77:869cf507173a | 40 | #define __STM32F4xx_HAL_DMA_H |
| emilmont | 77:869cf507173a | 41 | |
| emilmont | 77:869cf507173a | 42 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 43 | extern "C" { |
| emilmont | 77:869cf507173a | 44 | #endif |
| emilmont | 77:869cf507173a | 45 | |
| emilmont | 77:869cf507173a | 46 | /* Includes ------------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 47 | #include "stm32f4xx_hal_def.h" |
| emilmont | 77:869cf507173a | 48 | |
| emilmont | 77:869cf507173a | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| emilmont | 77:869cf507173a | 50 | * @{ |
| emilmont | 77:869cf507173a | 51 | */ |
| emilmont | 77:869cf507173a | 52 | |
| emilmont | 77:869cf507173a | 53 | /** @addtogroup DMA |
| emilmont | 77:869cf507173a | 54 | * @{ |
| emilmont | 77:869cf507173a | 55 | */ |
| emilmont | 77:869cf507173a | 56 | |
| emilmont | 77:869cf507173a | 57 | /* Exported types ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 58 | |
| emilmont | 77:869cf507173a | 59 | /** |
| emilmont | 77:869cf507173a | 60 | * @brief DMA Configuration Structure definition |
| emilmont | 77:869cf507173a | 61 | */ |
| emilmont | 77:869cf507173a | 62 | typedef struct |
| emilmont | 77:869cf507173a | 63 | { |
| emilmont | 77:869cf507173a | 64 | uint32_t Channel; /*!< Specifies the channel used for the specified stream. |
| emilmont | 77:869cf507173a | 65 | This parameter can be a value of @ref DMA_Channel_selection */ |
| emilmont | 77:869cf507173a | 66 | |
| emilmont | 77:869cf507173a | 67 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| emilmont | 77:869cf507173a | 68 | from memory to memory or from peripheral to memory. |
| emilmont | 77:869cf507173a | 69 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| emilmont | 77:869cf507173a | 70 | |
| emilmont | 77:869cf507173a | 71 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| emilmont | 77:869cf507173a | 72 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| emilmont | 77:869cf507173a | 73 | |
| emilmont | 77:869cf507173a | 74 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| emilmont | 77:869cf507173a | 75 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| emilmont | 77:869cf507173a | 76 | |
| emilmont | 77:869cf507173a | 77 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| emilmont | 77:869cf507173a | 78 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| emilmont | 77:869cf507173a | 79 | |
| emilmont | 77:869cf507173a | 80 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| emilmont | 77:869cf507173a | 81 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| emilmont | 77:869cf507173a | 82 | |
| emilmont | 77:869cf507173a | 83 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. |
| emilmont | 77:869cf507173a | 84 | This parameter can be a value of @ref DMA_mode |
| emilmont | 77:869cf507173a | 85 | @note The circular buffer mode cannot be used if the memory-to-memory |
| emilmont | 77:869cf507173a | 86 | data transfer is configured on the selected Stream */ |
| emilmont | 77:869cf507173a | 87 | |
| emilmont | 77:869cf507173a | 88 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. |
| emilmont | 77:869cf507173a | 89 | This parameter can be a value of @ref DMA_Priority_level */ |
| emilmont | 77:869cf507173a | 90 | |
| emilmont | 77:869cf507173a | 91 | uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. |
| emilmont | 77:869cf507173a | 92 | This parameter can be a value of @ref DMA_FIFO_direct_mode |
| emilmont | 77:869cf507173a | 93 | @note The Direct mode (FIFO mode disabled) cannot be used if the |
| emilmont | 77:869cf507173a | 94 | memory-to-memory data transfer is configured on the selected stream */ |
| emilmont | 77:869cf507173a | 95 | |
| emilmont | 77:869cf507173a | 96 | uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. |
| emilmont | 77:869cf507173a | 97 | This parameter can be a value of @ref DMA_FIFO_threshold_level */ |
| emilmont | 77:869cf507173a | 98 | |
| emilmont | 77:869cf507173a | 99 | uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. |
| emilmont | 77:869cf507173a | 100 | It specifies the amount of data to be transferred in a single non interruptable |
| emilmont | 77:869cf507173a | 101 | transaction. |
| emilmont | 77:869cf507173a | 102 | This parameter can be a value of @ref DMA_Memory_burst |
| emilmont | 77:869cf507173a | 103 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| emilmont | 77:869cf507173a | 104 | |
| emilmont | 77:869cf507173a | 105 | uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. |
| emilmont | 77:869cf507173a | 106 | It specifies the amount of data to be transferred in a single non interruptable |
| emilmont | 77:869cf507173a | 107 | transaction. |
| emilmont | 77:869cf507173a | 108 | This parameter can be a value of @ref DMA_Peripheral_burst |
| emilmont | 77:869cf507173a | 109 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| emilmont | 77:869cf507173a | 110 | |
| emilmont | 77:869cf507173a | 111 | }DMA_InitTypeDef; |
| emilmont | 77:869cf507173a | 112 | |
| emilmont | 77:869cf507173a | 113 | /** |
| emilmont | 77:869cf507173a | 114 | * @brief HAL DMA State structures definition |
| emilmont | 77:869cf507173a | 115 | */ |
| emilmont | 77:869cf507173a | 116 | typedef enum |
| emilmont | 77:869cf507173a | 117 | { |
| emilmont | 77:869cf507173a | 118 | HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ |
| emilmont | 77:869cf507173a | 119 | HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ |
| emilmont | 77:869cf507173a | 120 | HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */ |
| emilmont | 77:869cf507173a | 121 | HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */ |
| emilmont | 77:869cf507173a | 122 | HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */ |
| emilmont | 77:869cf507173a | 123 | HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */ |
| emilmont | 77:869cf507173a | 124 | HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ |
| emilmont | 77:869cf507173a | 125 | HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */ |
| emilmont | 77:869cf507173a | 126 | HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */ |
| emilmont | 77:869cf507173a | 127 | HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ |
| emilmont | 77:869cf507173a | 128 | HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ |
| emilmont | 77:869cf507173a | 129 | |
| emilmont | 77:869cf507173a | 130 | }HAL_DMA_StateTypeDef; |
| emilmont | 77:869cf507173a | 131 | |
| emilmont | 77:869cf507173a | 132 | /** |
| emilmont | 77:869cf507173a | 133 | * @brief HAL DMA Error Code structure definition |
| emilmont | 77:869cf507173a | 134 | */ |
| emilmont | 77:869cf507173a | 135 | typedef enum |
| emilmont | 77:869cf507173a | 136 | { |
| emilmont | 77:869cf507173a | 137 | HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ |
| emilmont | 77:869cf507173a | 138 | HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ |
| emilmont | 77:869cf507173a | 139 | |
| emilmont | 77:869cf507173a | 140 | }HAL_DMA_LevelCompleteTypeDef; |
| emilmont | 77:869cf507173a | 141 | |
| emilmont | 77:869cf507173a | 142 | |
| emilmont | 77:869cf507173a | 143 | /** |
| emilmont | 77:869cf507173a | 144 | * @brief DMA handle Structure definition |
| emilmont | 77:869cf507173a | 145 | */ |
| emilmont | 77:869cf507173a | 146 | typedef struct __DMA_HandleTypeDef |
| emilmont | 77:869cf507173a | 147 | { |
| emilmont | 77:869cf507173a | 148 | DMA_Stream_TypeDef *Instance; /*!< Register base address */ |
| emilmont | 77:869cf507173a | 149 | |
| emilmont | 77:869cf507173a | 150 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| emilmont | 77:869cf507173a | 151 | |
| emilmont | 77:869cf507173a | 152 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| emilmont | 77:869cf507173a | 153 | |
| emilmont | 77:869cf507173a | 154 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| emilmont | 77:869cf507173a | 155 | |
| emilmont | 77:869cf507173a | 156 | void *Parent; /*!< Parent object state */ |
| emilmont | 77:869cf507173a | 157 | |
| emilmont | 77:869cf507173a | 158 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| emilmont | 77:869cf507173a | 159 | |
| emilmont | 77:869cf507173a | 160 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| emilmont | 77:869cf507173a | 161 | |
| emilmont | 77:869cf507173a | 162 | void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ |
| emilmont | 77:869cf507173a | 163 | |
| emilmont | 77:869cf507173a | 164 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| emilmont | 77:869cf507173a | 165 | |
| emilmont | 77:869cf507173a | 166 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| emilmont | 77:869cf507173a | 167 | |
| emilmont | 77:869cf507173a | 168 | }DMA_HandleTypeDef; |
| emilmont | 77:869cf507173a | 169 | |
| emilmont | 77:869cf507173a | 170 | /* Exported constants --------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 171 | |
| emilmont | 77:869cf507173a | 172 | /** @defgroup DMA_Exported_Constants |
| emilmont | 77:869cf507173a | 173 | * @{ |
| emilmont | 77:869cf507173a | 174 | */ |
| emilmont | 77:869cf507173a | 175 | |
| emilmont | 77:869cf507173a | 176 | /** @defgroup DMA_Error_Code |
| emilmont | 77:869cf507173a | 177 | * @{ |
| emilmont | 77:869cf507173a | 178 | */ |
| emilmont | 77:869cf507173a | 179 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| emilmont | 77:869cf507173a | 180 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ |
| emilmont | 77:869cf507173a | 181 | #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */ |
| emilmont | 77:869cf507173a | 182 | #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */ |
| emilmont | 77:869cf507173a | 183 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ |
| emilmont | 77:869cf507173a | 184 | /** |
| emilmont | 77:869cf507173a | 185 | * @} |
| emilmont | 77:869cf507173a | 186 | */ |
| emilmont | 77:869cf507173a | 187 | |
| emilmont | 77:869cf507173a | 188 | /** @defgroup DMA_Channel_selection |
| emilmont | 77:869cf507173a | 189 | * @{ |
| emilmont | 77:869cf507173a | 190 | */ |
| emilmont | 77:869cf507173a | 191 | #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */ |
| emilmont | 77:869cf507173a | 192 | #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */ |
| emilmont | 77:869cf507173a | 193 | #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */ |
| emilmont | 77:869cf507173a | 194 | #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */ |
| emilmont | 77:869cf507173a | 195 | #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */ |
| emilmont | 77:869cf507173a | 196 | #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */ |
| emilmont | 77:869cf507173a | 197 | #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */ |
| emilmont | 77:869cf507173a | 198 | #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */ |
| emilmont | 77:869cf507173a | 199 | |
| emilmont | 77:869cf507173a | 200 | #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ |
| emilmont | 77:869cf507173a | 201 | ((CHANNEL) == DMA_CHANNEL_1) || \ |
| emilmont | 77:869cf507173a | 202 | ((CHANNEL) == DMA_CHANNEL_2) || \ |
| emilmont | 77:869cf507173a | 203 | ((CHANNEL) == DMA_CHANNEL_3) || \ |
| emilmont | 77:869cf507173a | 204 | ((CHANNEL) == DMA_CHANNEL_4) || \ |
| emilmont | 77:869cf507173a | 205 | ((CHANNEL) == DMA_CHANNEL_5) || \ |
| emilmont | 77:869cf507173a | 206 | ((CHANNEL) == DMA_CHANNEL_6) || \ |
| emilmont | 77:869cf507173a | 207 | ((CHANNEL) == DMA_CHANNEL_7)) |
| emilmont | 77:869cf507173a | 208 | /** |
| emilmont | 77:869cf507173a | 209 | * @} |
| emilmont | 77:869cf507173a | 210 | */ |
| emilmont | 77:869cf507173a | 211 | |
| emilmont | 77:869cf507173a | 212 | /** @defgroup DMA_Data_transfer_direction |
| emilmont | 77:869cf507173a | 213 | * @{ |
| emilmont | 77:869cf507173a | 214 | */ |
| emilmont | 77:869cf507173a | 215 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ |
| emilmont | 77:869cf507173a | 216 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ |
| emilmont | 77:869cf507173a | 217 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ |
| emilmont | 77:869cf507173a | 218 | |
| emilmont | 77:869cf507173a | 219 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| emilmont | 77:869cf507173a | 220 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| emilmont | 77:869cf507173a | 221 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| emilmont | 77:869cf507173a | 222 | /** |
| emilmont | 77:869cf507173a | 223 | * @} |
| emilmont | 77:869cf507173a | 224 | */ |
| emilmont | 77:869cf507173a | 225 | |
| emilmont | 77:869cf507173a | 226 | /** @defgroup DMA_Data_buffer_size |
| emilmont | 77:869cf507173a | 227 | * @{ |
| emilmont | 77:869cf507173a | 228 | */ |
| emilmont | 77:869cf507173a | 229 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| emilmont | 77:869cf507173a | 230 | /** |
| emilmont | 77:869cf507173a | 231 | * @} |
| emilmont | 77:869cf507173a | 232 | */ |
| emilmont | 77:869cf507173a | 233 | |
| emilmont | 77:869cf507173a | 234 | /** @defgroup DMA_Peripheral_incremented_mode |
| emilmont | 77:869cf507173a | 235 | * @{ |
| emilmont | 77:869cf507173a | 236 | */ |
| emilmont | 77:869cf507173a | 237 | #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ |
| emilmont | 77:869cf507173a | 238 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */ |
| emilmont | 77:869cf507173a | 239 | |
| emilmont | 77:869cf507173a | 240 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| emilmont | 77:869cf507173a | 241 | ((STATE) == DMA_PINC_DISABLE)) |
| emilmont | 77:869cf507173a | 242 | /** |
| emilmont | 77:869cf507173a | 243 | * @} |
| emilmont | 77:869cf507173a | 244 | */ |
| emilmont | 77:869cf507173a | 245 | |
| emilmont | 77:869cf507173a | 246 | /** @defgroup DMA_Memory_incremented_mode |
| emilmont | 77:869cf507173a | 247 | * @{ |
| emilmont | 77:869cf507173a | 248 | */ |
| emilmont | 77:869cf507173a | 249 | #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ |
| emilmont | 77:869cf507173a | 250 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */ |
| emilmont | 77:869cf507173a | 251 | |
| emilmont | 77:869cf507173a | 252 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| emilmont | 77:869cf507173a | 253 | ((STATE) == DMA_MINC_DISABLE)) |
| emilmont | 77:869cf507173a | 254 | /** |
| emilmont | 77:869cf507173a | 255 | * @} |
| emilmont | 77:869cf507173a | 256 | */ |
| emilmont | 77:869cf507173a | 257 | |
| emilmont | 77:869cf507173a | 258 | /** @defgroup DMA_Peripheral_data_size |
| emilmont | 77:869cf507173a | 259 | * @{ |
| emilmont | 77:869cf507173a | 260 | */ |
| emilmont | 77:869cf507173a | 261 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ |
| emilmont | 77:869cf507173a | 262 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
| emilmont | 77:869cf507173a | 263 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
| emilmont | 77:869cf507173a | 264 | |
| emilmont | 77:869cf507173a | 265 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| emilmont | 77:869cf507173a | 266 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| emilmont | 77:869cf507173a | 267 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| emilmont | 77:869cf507173a | 268 | /** |
| emilmont | 77:869cf507173a | 269 | * @} |
| emilmont | 77:869cf507173a | 270 | */ |
| emilmont | 77:869cf507173a | 271 | |
| emilmont | 77:869cf507173a | 272 | |
| emilmont | 77:869cf507173a | 273 | /** @defgroup DMA_Memory_data_size |
| emilmont | 77:869cf507173a | 274 | * @{ |
| emilmont | 77:869cf507173a | 275 | */ |
| emilmont | 77:869cf507173a | 276 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ |
| emilmont | 77:869cf507173a | 277 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
| emilmont | 77:869cf507173a | 278 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ |
| emilmont | 77:869cf507173a | 279 | |
| emilmont | 77:869cf507173a | 280 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| emilmont | 77:869cf507173a | 281 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| emilmont | 77:869cf507173a | 282 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| emilmont | 77:869cf507173a | 283 | /** |
| emilmont | 77:869cf507173a | 284 | * @} |
| emilmont | 77:869cf507173a | 285 | */ |
| emilmont | 77:869cf507173a | 286 | |
| emilmont | 77:869cf507173a | 287 | /** @defgroup DMA_mode |
| emilmont | 77:869cf507173a | 288 | * @{ |
| emilmont | 77:869cf507173a | 289 | */ |
| emilmont | 77:869cf507173a | 290 | #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ |
| emilmont | 77:869cf507173a | 291 | #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ |
| emilmont | 77:869cf507173a | 292 | #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ |
| emilmont | 77:869cf507173a | 293 | |
| emilmont | 77:869cf507173a | 294 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| emilmont | 77:869cf507173a | 295 | ((MODE) == DMA_CIRCULAR) || \ |
| emilmont | 77:869cf507173a | 296 | ((MODE) == DMA_PFCTRL)) |
| emilmont | 77:869cf507173a | 297 | /** |
| emilmont | 77:869cf507173a | 298 | * @} |
| emilmont | 77:869cf507173a | 299 | */ |
| emilmont | 77:869cf507173a | 300 | |
| emilmont | 77:869cf507173a | 301 | /** @defgroup DMA_Priority_level |
| emilmont | 77:869cf507173a | 302 | * @{ |
| emilmont | 77:869cf507173a | 303 | */ |
| emilmont | 77:869cf507173a | 304 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */ |
| emilmont | 77:869cf507173a | 305 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ |
| emilmont | 77:869cf507173a | 306 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ |
| emilmont | 77:869cf507173a | 307 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ |
| emilmont | 77:869cf507173a | 308 | |
| emilmont | 77:869cf507173a | 309 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| emilmont | 77:869cf507173a | 310 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| emilmont | 77:869cf507173a | 311 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| emilmont | 77:869cf507173a | 312 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| emilmont | 77:869cf507173a | 313 | /** |
| emilmont | 77:869cf507173a | 314 | * @} |
| emilmont | 77:869cf507173a | 315 | */ |
| emilmont | 77:869cf507173a | 316 | |
| emilmont | 77:869cf507173a | 317 | /** @defgroup DMA_FIFO_direct_mode |
| emilmont | 77:869cf507173a | 318 | * @{ |
| emilmont | 77:869cf507173a | 319 | */ |
| emilmont | 77:869cf507173a | 320 | #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */ |
| emilmont | 77:869cf507173a | 321 | #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ |
| emilmont | 77:869cf507173a | 322 | |
| emilmont | 77:869cf507173a | 323 | #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ |
| emilmont | 77:869cf507173a | 324 | ((STATE) == DMA_FIFOMODE_ENABLE)) |
| emilmont | 77:869cf507173a | 325 | /** |
| emilmont | 77:869cf507173a | 326 | * @} |
| emilmont | 77:869cf507173a | 327 | */ |
| emilmont | 77:869cf507173a | 328 | |
| emilmont | 77:869cf507173a | 329 | /** @defgroup DMA_FIFO_threshold_level |
| emilmont | 77:869cf507173a | 330 | * @{ |
| emilmont | 77:869cf507173a | 331 | */ |
| emilmont | 77:869cf507173a | 332 | #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */ |
| emilmont | 77:869cf507173a | 333 | #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ |
| emilmont | 77:869cf507173a | 334 | #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ |
| emilmont | 77:869cf507173a | 335 | #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ |
| emilmont | 77:869cf507173a | 336 | |
| emilmont | 77:869cf507173a | 337 | #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ |
| emilmont | 77:869cf507173a | 338 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ |
| emilmont | 77:869cf507173a | 339 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ |
| emilmont | 77:869cf507173a | 340 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) |
| emilmont | 77:869cf507173a | 341 | /** |
| emilmont | 77:869cf507173a | 342 | * @} |
| emilmont | 77:869cf507173a | 343 | */ |
| emilmont | 77:869cf507173a | 344 | |
| emilmont | 77:869cf507173a | 345 | /** @defgroup DMA_Memory_burst |
| emilmont | 77:869cf507173a | 346 | * @{ |
| emilmont | 77:869cf507173a | 347 | */ |
| emilmont | 77:869cf507173a | 348 | #define DMA_MBURST_SINGLE ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 349 | #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) |
| emilmont | 77:869cf507173a | 350 | #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) |
| emilmont | 77:869cf507173a | 351 | #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) |
| emilmont | 77:869cf507173a | 352 | |
| emilmont | 77:869cf507173a | 353 | #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ |
| emilmont | 77:869cf507173a | 354 | ((BURST) == DMA_MBURST_INC4) || \ |
| emilmont | 77:869cf507173a | 355 | ((BURST) == DMA_MBURST_INC8) || \ |
| emilmont | 77:869cf507173a | 356 | ((BURST) == DMA_MBURST_INC16)) |
| emilmont | 77:869cf507173a | 357 | /** |
| emilmont | 77:869cf507173a | 358 | * @} |
| emilmont | 77:869cf507173a | 359 | */ |
| emilmont | 77:869cf507173a | 360 | |
| emilmont | 77:869cf507173a | 361 | /** @defgroup DMA_Peripheral_burst |
| emilmont | 77:869cf507173a | 362 | * @{ |
| emilmont | 77:869cf507173a | 363 | */ |
| emilmont | 77:869cf507173a | 364 | #define DMA_PBURST_SINGLE ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 365 | #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) |
| emilmont | 77:869cf507173a | 366 | #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) |
| emilmont | 77:869cf507173a | 367 | #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) |
| emilmont | 77:869cf507173a | 368 | |
| emilmont | 77:869cf507173a | 369 | #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ |
| emilmont | 77:869cf507173a | 370 | ((BURST) == DMA_PBURST_INC4) || \ |
| emilmont | 77:869cf507173a | 371 | ((BURST) == DMA_PBURST_INC8) || \ |
| emilmont | 77:869cf507173a | 372 | ((BURST) == DMA_PBURST_INC16)) |
| emilmont | 77:869cf507173a | 373 | /** |
| emilmont | 77:869cf507173a | 374 | * @} |
| emilmont | 77:869cf507173a | 375 | */ |
| emilmont | 77:869cf507173a | 376 | |
| emilmont | 77:869cf507173a | 377 | /** @defgroup DMA_interrupt_enable_definitions |
| emilmont | 77:869cf507173a | 378 | * @{ |
| emilmont | 77:869cf507173a | 379 | */ |
| emilmont | 77:869cf507173a | 380 | #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) |
| emilmont | 77:869cf507173a | 381 | #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) |
| emilmont | 77:869cf507173a | 382 | #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) |
| emilmont | 77:869cf507173a | 383 | #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) |
| emilmont | 77:869cf507173a | 384 | #define DMA_IT_FE ((uint32_t)0x00000080) |
| emilmont | 77:869cf507173a | 385 | /** |
| emilmont | 77:869cf507173a | 386 | * @} |
| emilmont | 77:869cf507173a | 387 | */ |
| emilmont | 77:869cf507173a | 388 | |
| emilmont | 77:869cf507173a | 389 | /** @defgroup DMA_flag_definitions |
| emilmont | 77:869cf507173a | 390 | * @{ |
| emilmont | 77:869cf507173a | 391 | */ |
| emilmont | 77:869cf507173a | 392 | #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001) |
| emilmont | 77:869cf507173a | 393 | #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004) |
| emilmont | 77:869cf507173a | 394 | #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008) |
| emilmont | 77:869cf507173a | 395 | #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010) |
| emilmont | 77:869cf507173a | 396 | #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020) |
| emilmont | 77:869cf507173a | 397 | #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040) |
| emilmont | 77:869cf507173a | 398 | #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100) |
| emilmont | 77:869cf507173a | 399 | #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200) |
| emilmont | 77:869cf507173a | 400 | #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400) |
| emilmont | 77:869cf507173a | 401 | #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800) |
| emilmont | 77:869cf507173a | 402 | #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000) |
| emilmont | 77:869cf507173a | 403 | #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000) |
| emilmont | 77:869cf507173a | 404 | #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000) |
| emilmont | 77:869cf507173a | 405 | #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000) |
| emilmont | 77:869cf507173a | 406 | #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000) |
| emilmont | 77:869cf507173a | 407 | #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000) |
| emilmont | 77:869cf507173a | 408 | #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000) |
| emilmont | 77:869cf507173a | 409 | #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000) |
| emilmont | 77:869cf507173a | 410 | #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000) |
| emilmont | 77:869cf507173a | 411 | #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000) |
| emilmont | 77:869cf507173a | 412 | /** |
| emilmont | 77:869cf507173a | 413 | * @} |
| emilmont | 77:869cf507173a | 414 | */ |
| emilmont | 77:869cf507173a | 415 | |
| emilmont | 77:869cf507173a | 416 | /** |
| emilmont | 77:869cf507173a | 417 | * @} |
| emilmont | 77:869cf507173a | 418 | */ |
| emilmont | 77:869cf507173a | 419 | |
| emilmont | 77:869cf507173a | 420 | /* Exported macro ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 421 | /** |
| emilmont | 77:869cf507173a | 422 | * @brief Return the current DMA Stream FIFO filled level. |
| emilmont | 77:869cf507173a | 423 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 424 | * @retval The FIFO filling state. |
| emilmont | 77:869cf507173a | 425 | * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full |
| emilmont | 77:869cf507173a | 426 | * and not empty. |
| emilmont | 77:869cf507173a | 427 | * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. |
| emilmont | 77:869cf507173a | 428 | * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. |
| emilmont | 77:869cf507173a | 429 | * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. |
| emilmont | 77:869cf507173a | 430 | * - DMA_FIFOStatus_Empty: when FIFO is empty |
| emilmont | 77:869cf507173a | 431 | * - DMA_FIFOStatus_Full: when FIFO is full |
| emilmont | 77:869cf507173a | 432 | */ |
| emilmont | 77:869cf507173a | 433 | #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) |
| emilmont | 77:869cf507173a | 434 | |
| emilmont | 77:869cf507173a | 435 | /** |
| emilmont | 77:869cf507173a | 436 | * @brief Enable the specified DMA Stream. |
| emilmont | 77:869cf507173a | 437 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 438 | * @retval None |
| emilmont | 77:869cf507173a | 439 | */ |
| emilmont | 77:869cf507173a | 440 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) |
| emilmont | 77:869cf507173a | 441 | |
| emilmont | 77:869cf507173a | 442 | /** |
| emilmont | 77:869cf507173a | 443 | * @brief Disable the specified DMA Stream. |
| emilmont | 77:869cf507173a | 444 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 445 | * @retval None |
| emilmont | 77:869cf507173a | 446 | */ |
| emilmont | 77:869cf507173a | 447 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) |
| emilmont | 77:869cf507173a | 448 | |
| emilmont | 77:869cf507173a | 449 | /* Interrupt & Flag management */ |
| emilmont | 77:869cf507173a | 450 | |
| emilmont | 77:869cf507173a | 451 | /** |
| emilmont | 77:869cf507173a | 452 | * @brief Return the current DMA Stream transfer complete flag. |
| emilmont | 77:869cf507173a | 453 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 454 | * @retval The specified transfer complete flag index. |
| emilmont | 77:869cf507173a | 455 | */ |
| emilmont | 77:869cf507173a | 456 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| emilmont | 77:869cf507173a | 457 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| emilmont | 77:869cf507173a | 458 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| emilmont | 77:869cf507173a | 459 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| emilmont | 77:869cf507173a | 460 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| emilmont | 77:869cf507173a | 461 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| emilmont | 77:869cf507173a | 462 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| emilmont | 77:869cf507173a | 463 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| emilmont | 77:869cf507173a | 464 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| emilmont | 77:869cf507173a | 465 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| emilmont | 77:869cf507173a | 466 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| emilmont | 77:869cf507173a | 467 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| emilmont | 77:869cf507173a | 468 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| emilmont | 77:869cf507173a | 469 | DMA_FLAG_TCIF3_7) |
| emilmont | 77:869cf507173a | 470 | |
| emilmont | 77:869cf507173a | 471 | /** |
| emilmont | 77:869cf507173a | 472 | * @brief Return the current DMA Stream half transfer complete flag. |
| emilmont | 77:869cf507173a | 473 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 474 | * @retval The specified half transfer complete flag index. |
| emilmont | 77:869cf507173a | 475 | */ |
| emilmont | 77:869cf507173a | 476 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| emilmont | 77:869cf507173a | 477 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| emilmont | 77:869cf507173a | 478 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| emilmont | 77:869cf507173a | 479 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| emilmont | 77:869cf507173a | 480 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| emilmont | 77:869cf507173a | 481 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| emilmont | 77:869cf507173a | 482 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| emilmont | 77:869cf507173a | 483 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| emilmont | 77:869cf507173a | 484 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| emilmont | 77:869cf507173a | 485 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| emilmont | 77:869cf507173a | 486 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| emilmont | 77:869cf507173a | 487 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| emilmont | 77:869cf507173a | 488 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| emilmont | 77:869cf507173a | 489 | DMA_FLAG_HTIF3_7) |
| emilmont | 77:869cf507173a | 490 | |
| emilmont | 77:869cf507173a | 491 | /** |
| emilmont | 77:869cf507173a | 492 | * @brief Return the current DMA Stream transfer error flag. |
| emilmont | 77:869cf507173a | 493 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 494 | * @retval The specified transfer error flag index. |
| emilmont | 77:869cf507173a | 495 | */ |
| emilmont | 77:869cf507173a | 496 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| emilmont | 77:869cf507173a | 497 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| emilmont | 77:869cf507173a | 498 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| emilmont | 77:869cf507173a | 499 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| emilmont | 77:869cf507173a | 500 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| emilmont | 77:869cf507173a | 501 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| emilmont | 77:869cf507173a | 502 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| emilmont | 77:869cf507173a | 503 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| emilmont | 77:869cf507173a | 504 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| emilmont | 77:869cf507173a | 505 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| emilmont | 77:869cf507173a | 506 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| emilmont | 77:869cf507173a | 507 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| emilmont | 77:869cf507173a | 508 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| emilmont | 77:869cf507173a | 509 | DMA_FLAG_TEIF3_7) |
| emilmont | 77:869cf507173a | 510 | |
| emilmont | 77:869cf507173a | 511 | /** |
| emilmont | 77:869cf507173a | 512 | * @brief Return the current DMA Stream FIFO error flag. |
| emilmont | 77:869cf507173a | 513 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 514 | * @retval The specified FIFO error flag index. |
| emilmont | 77:869cf507173a | 515 | */ |
| emilmont | 77:869cf507173a | 516 | #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ |
| emilmont | 77:869cf507173a | 517 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| emilmont | 77:869cf507173a | 518 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| emilmont | 77:869cf507173a | 519 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| emilmont | 77:869cf507173a | 520 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| emilmont | 77:869cf507173a | 521 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| emilmont | 77:869cf507173a | 522 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| emilmont | 77:869cf507173a | 523 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| emilmont | 77:869cf507173a | 524 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| emilmont | 77:869cf507173a | 525 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| emilmont | 77:869cf507173a | 526 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| emilmont | 77:869cf507173a | 527 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| emilmont | 77:869cf507173a | 528 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| emilmont | 77:869cf507173a | 529 | DMA_FLAG_FEIF3_7) |
| emilmont | 77:869cf507173a | 530 | |
| emilmont | 77:869cf507173a | 531 | /** |
| emilmont | 77:869cf507173a | 532 | * @brief Return the current DMA Stream direct mode error flag. |
| emilmont | 77:869cf507173a | 533 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 534 | * @retval The specified direct mode error flag index. |
| emilmont | 77:869cf507173a | 535 | */ |
| emilmont | 77:869cf507173a | 536 | #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ |
| emilmont | 77:869cf507173a | 537 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| emilmont | 77:869cf507173a | 538 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| emilmont | 77:869cf507173a | 539 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| emilmont | 77:869cf507173a | 540 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| emilmont | 77:869cf507173a | 541 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| emilmont | 77:869cf507173a | 542 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| emilmont | 77:869cf507173a | 543 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| emilmont | 77:869cf507173a | 544 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| emilmont | 77:869cf507173a | 545 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| emilmont | 77:869cf507173a | 546 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| emilmont | 77:869cf507173a | 547 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| emilmont | 77:869cf507173a | 548 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| emilmont | 77:869cf507173a | 549 | DMA_FLAG_DMEIF3_7) |
| emilmont | 77:869cf507173a | 550 | |
| emilmont | 77:869cf507173a | 551 | /** |
| emilmont | 77:869cf507173a | 552 | * @brief Get the DMA Stream pending flags. |
| emilmont | 77:869cf507173a | 553 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 554 | * @param __FLAG__: Get the specified flag. |
| emilmont | 77:869cf507173a | 555 | * This parameter can be any combination of the following values: |
| emilmont | 77:869cf507173a | 556 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| emilmont | 77:869cf507173a | 557 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| emilmont | 77:869cf507173a | 558 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| emilmont | 77:869cf507173a | 559 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| emilmont | 77:869cf507173a | 560 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| emilmont | 77:869cf507173a | 561 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| emilmont | 77:869cf507173a | 562 | * @retval The state of FLAG (SET or RESET). |
| emilmont | 77:869cf507173a | 563 | */ |
| emilmont | 77:869cf507173a | 564 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
| emilmont | 77:869cf507173a | 565 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ |
| emilmont | 77:869cf507173a | 566 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ |
| emilmont | 77:869cf507173a | 567 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) |
| emilmont | 77:869cf507173a | 568 | |
| emilmont | 77:869cf507173a | 569 | /** |
| emilmont | 77:869cf507173a | 570 | * @brief Clear the DMA Stream pending flags. |
| emilmont | 77:869cf507173a | 571 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 572 | * @param __FLAG__: specifies the flag to clear. |
| emilmont | 77:869cf507173a | 573 | * This parameter can be any combination of the following values: |
| emilmont | 77:869cf507173a | 574 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| emilmont | 77:869cf507173a | 575 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| emilmont | 77:869cf507173a | 576 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| emilmont | 77:869cf507173a | 577 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| emilmont | 77:869cf507173a | 578 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| emilmont | 77:869cf507173a | 579 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| emilmont | 77:869cf507173a | 580 | * @retval None |
| emilmont | 77:869cf507173a | 581 | */ |
| emilmont | 77:869cf507173a | 582 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| emilmont | 77:869cf507173a | 583 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR |= (__FLAG__)) :\ |
| emilmont | 77:869cf507173a | 584 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR |= (__FLAG__)) :\ |
| emilmont | 77:869cf507173a | 585 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR |= (__FLAG__)) : (DMA1->LIFCR |= (__FLAG__))) |
| emilmont | 77:869cf507173a | 586 | |
| emilmont | 77:869cf507173a | 587 | /** |
| emilmont | 77:869cf507173a | 588 | * @brief Enable the specified DMA Stream interrupts. |
| emilmont | 77:869cf507173a | 589 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 590 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| emilmont | 77:869cf507173a | 591 | * This parameter can be any combination of the following values: |
| emilmont | 77:869cf507173a | 592 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| emilmont | 77:869cf507173a | 593 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| emilmont | 77:869cf507173a | 594 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| emilmont | 77:869cf507173a | 595 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| emilmont | 77:869cf507173a | 596 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| emilmont | 77:869cf507173a | 597 | * @retval None |
| emilmont | 77:869cf507173a | 598 | */ |
| emilmont | 77:869cf507173a | 599 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| emilmont | 77:869cf507173a | 600 | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) |
| emilmont | 77:869cf507173a | 601 | |
| emilmont | 77:869cf507173a | 602 | /** |
| emilmont | 77:869cf507173a | 603 | * @brief Disable the specified DMA Stream interrupts. |
| emilmont | 77:869cf507173a | 604 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 605 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| emilmont | 77:869cf507173a | 606 | * This parameter can be any combination of the following values: |
| emilmont | 77:869cf507173a | 607 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| emilmont | 77:869cf507173a | 608 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| emilmont | 77:869cf507173a | 609 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| emilmont | 77:869cf507173a | 610 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| emilmont | 77:869cf507173a | 611 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| emilmont | 77:869cf507173a | 612 | * @retval None |
| emilmont | 77:869cf507173a | 613 | */ |
| emilmont | 77:869cf507173a | 614 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| emilmont | 77:869cf507173a | 615 | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) |
| emilmont | 77:869cf507173a | 616 | |
| emilmont | 77:869cf507173a | 617 | /** |
| emilmont | 77:869cf507173a | 618 | * @brief Check whether the specified DMA Stream interrupt has occurred or not. |
| emilmont | 77:869cf507173a | 619 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 620 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| emilmont | 77:869cf507173a | 621 | * This parameter can be one of the following values: |
| emilmont | 77:869cf507173a | 622 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| emilmont | 77:869cf507173a | 623 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| emilmont | 77:869cf507173a | 624 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| emilmont | 77:869cf507173a | 625 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| emilmont | 77:869cf507173a | 626 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| emilmont | 77:869cf507173a | 627 | * @retval The state of DMA_IT. |
| emilmont | 77:869cf507173a | 628 | */ |
| emilmont | 77:869cf507173a | 629 | #define __HAL_DMA_IT_STATUS(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| emilmont | 77:869cf507173a | 630 | ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ |
| emilmont | 77:869cf507173a | 631 | ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) |
| emilmont | 77:869cf507173a | 632 | |
| emilmont | 77:869cf507173a | 633 | /** |
| emilmont | 77:869cf507173a | 634 | * @brief Writes the number of data units to be transferred on the DMA Stream. |
| emilmont | 77:869cf507173a | 635 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 636 | * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) |
| emilmont | 77:869cf507173a | 637 | * Number of data items depends only on the Peripheral data format. |
| emilmont | 77:869cf507173a | 638 | * |
| emilmont | 77:869cf507173a | 639 | * @note If Peripheral data format is Bytes: number of data units is equal |
| emilmont | 77:869cf507173a | 640 | * to total number of bytes to be transferred. |
| emilmont | 77:869cf507173a | 641 | * |
| emilmont | 77:869cf507173a | 642 | * @note If Peripheral data format is Half-Word: number of data units is |
| emilmont | 77:869cf507173a | 643 | * equal to total number of bytes to be transferred / 2. |
| emilmont | 77:869cf507173a | 644 | * |
| emilmont | 77:869cf507173a | 645 | * @note If Peripheral data format is Word: number of data units is equal |
| emilmont | 77:869cf507173a | 646 | * to total number of bytes to be transferred / 4. |
| emilmont | 77:869cf507173a | 647 | * |
| emilmont | 77:869cf507173a | 648 | * @retval The number of remaining data units in the current DMAy Streamx transfer. |
| emilmont | 77:869cf507173a | 649 | */ |
| emilmont | 77:869cf507173a | 650 | #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) |
| emilmont | 77:869cf507173a | 651 | |
| emilmont | 77:869cf507173a | 652 | /** |
| emilmont | 77:869cf507173a | 653 | * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. |
| emilmont | 77:869cf507173a | 654 | * @param __HANDLE__: DMA handle |
| emilmont | 77:869cf507173a | 655 | * |
| emilmont | 77:869cf507173a | 656 | * @retval The number of remaining data units in the current DMA Stream transfer. |
| emilmont | 77:869cf507173a | 657 | */ |
| emilmont | 77:869cf507173a | 658 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) |
| emilmont | 77:869cf507173a | 659 | |
| emilmont | 77:869cf507173a | 660 | |
| emilmont | 77:869cf507173a | 661 | /* Include DMA HAL Extension module */ |
| emilmont | 77:869cf507173a | 662 | #include "stm32f4xx_hal_dma_ex.h" |
| emilmont | 77:869cf507173a | 663 | |
| emilmont | 77:869cf507173a | 664 | /* Exported functions --------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 665 | |
| emilmont | 77:869cf507173a | 666 | /* Initialization and de-initialization functions *****************************/ |
| emilmont | 77:869cf507173a | 667 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| emilmont | 77:869cf507173a | 668 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); |
| emilmont | 77:869cf507173a | 669 | |
| emilmont | 77:869cf507173a | 670 | /* IO operation functions *****************************************************/ |
| emilmont | 77:869cf507173a | 671 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| emilmont | 77:869cf507173a | 672 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| emilmont | 77:869cf507173a | 673 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| emilmont | 77:869cf507173a | 674 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| emilmont | 77:869cf507173a | 675 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| emilmont | 77:869cf507173a | 676 | |
| emilmont | 77:869cf507173a | 677 | /* Peripheral State and Error functions ***************************************/ |
| emilmont | 77:869cf507173a | 678 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| emilmont | 77:869cf507173a | 679 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| emilmont | 77:869cf507173a | 680 | |
| emilmont | 77:869cf507173a | 681 | /** |
| emilmont | 77:869cf507173a | 682 | * @} |
| emilmont | 77:869cf507173a | 683 | */ |
| emilmont | 77:869cf507173a | 684 | |
| emilmont | 77:869cf507173a | 685 | /** |
| emilmont | 77:869cf507173a | 686 | * @} |
| emilmont | 77:869cf507173a | 687 | */ |
| emilmont | 77:869cf507173a | 688 | |
| emilmont | 77:869cf507173a | 689 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 690 | } |
| emilmont | 77:869cf507173a | 691 | #endif |
| emilmont | 77:869cf507173a | 692 | |
| emilmont | 77:869cf507173a | 693 | #endif /* __STM32F4xx_HAL_DMA_H */ |
| emilmont | 77:869cf507173a | 694 | |
| emilmont | 77:869cf507173a | 695 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |