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TARGET_WIZwiki_W7500/W7500x_i2c.h@101:7cff1c4259d7, 2015-06-09 (annotated)

Committer:
Kojto
Date:
Tue Jun 09 14:29:26 2015 +0100
Revision:
101:7cff1c4259d7
Child:
102:da0ca467f8b5
Release 101 of the mbed library



Changes:

- new platform: APPNEARME_MICRONFCBOARD, MTS_DRAGONFLY_F411RE, MAX32600MBED, WIZwiki_W7500

- Silabs memory optimization in gpio, pwm fixes

- SPI  - ssel documentation fixes and its use

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 #include "W7500x.h"
Kojto 101:7cff1c4259d7 2
Kojto 101:7cff1c4259d7 3 /**
Kojto 101:7cff1c4259d7 4 * @defgroup I2C_Public_Types I2X Public Types
Kojto 101:7cff1c4259d7 5 */
Kojto 101:7cff1c4259d7 6 typedef enum
Kojto 101:7cff1c4259d7 7 {
Kojto 101:7cff1c4259d7 8 I2C_WRITE_SA7=0,
Kojto 101:7cff1c4259d7 9 I2C_READ_SA7,
Kojto 101:7cff1c4259d7 10 //I2C_WRITE_SA10,
Kojto 101:7cff1c4259d7 11 //I2C_READ_SA10,
Kojto 101:7cff1c4259d7 12 I2C_CTRWRITE_SA7,
Kojto 101:7cff1c4259d7 13 I2C_CTRREAD_SA7,
Kojto 101:7cff1c4259d7 14 //I2C_CTRWRITE_SA10,
Kojto 101:7cff1c4259d7 15 //I2C_CTRREAD_SA10,
Kojto 101:7cff1c4259d7 16 } I2C_CTR;
Kojto 101:7cff1c4259d7 17
Kojto 101:7cff1c4259d7 18 typedef enum
Kojto 101:7cff1c4259d7 19 {
Kojto 101:7cff1c4259d7 20 I2C_ACKR=0,
Kojto 101:7cff1c4259d7 21 I2C_ACKT,
Kojto 101:7cff1c4259d7 22 I2C_OACKR,
Kojto 101:7cff1c4259d7 23 I2C_SACKR,
Kojto 101:7cff1c4259d7 24 I2C_BT,
Kojto 101:7cff1c4259d7 25 } I2C_SR;
Kojto 101:7cff1c4259d7 26
Kojto 101:7cff1c4259d7 27
Kojto 101:7cff1c4259d7 28 typedef enum
Kojto 101:7cff1c4259d7 29 {
Kojto 101:7cff1c4259d7 30 INT_ACKR=-1,
Kojto 101:7cff1c4259d7 31 INT_ACKT=-2,
Kojto 101:7cff1c4259d7 32 INT_NACKR=-3,
Kojto 101:7cff1c4259d7 33 INT_NACKT=-4,
Kojto 101:7cff1c4259d7 34 INT_BT=-5,
Kojto 101:7cff1c4259d7 35 } I2C_ERROR;
Kojto 101:7cff1c4259d7 36
Kojto 101:7cff1c4259d7 37
Kojto 101:7cff1c4259d7 38 /**
Kojto 101:7cff1c4259d7 39 *@
Kojto 101:7cff1c4259d7 40 */
Kojto 101:7cff1c4259d7 41 /** @defgroup I2C_registers
Kojto 101:7cff1c4259d7 42 * @{
Kojto 101:7cff1c4259d7 43 */
Kojto 101:7cff1c4259d7 44
Kojto 101:7cff1c4259d7 45 #define I2C_Register_PRER ((uint8_t)0x00)
Kojto 101:7cff1c4259d7 46 #define I2C_Register_CTR ((uint8_t)0x04)
Kojto 101:7cff1c4259d7 47 #define I2C_Register_CMDR ((uint8_t)0x08)
Kojto 101:7cff1c4259d7 48 #define I2C_Register_SR ((uint8_t)0x0C)
Kojto 101:7cff1c4259d7 49 #define I2C_Register_TSR ((uint8_t)0x10)
Kojto 101:7cff1c4259d7 50 #define I2C_Register_SADDR ((uint8_t)0x14)
Kojto 101:7cff1c4259d7 51 #define I2C_Register_TXR ((uint8_t)0x18)
Kojto 101:7cff1c4259d7 52 #define I2C_Register_RXR ((uint8_t)0x1C)
Kojto 101:7cff1c4259d7 53 #define I2C_Register_ISR ((uint8_t)0x20)
Kojto 101:7cff1c4259d7 54 #define I2C_Register_ISCR ((uint8_t)0x24)
Kojto 101:7cff1c4259d7 55 #define I2C_Register_ISMR ((uint8_t)0x28)
Kojto 101:7cff1c4259d7 56 #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_PRER) || \
Kojto 101:7cff1c4259d7 57 ((REGISTER) == I2C_Register_CTR) || \
Kojto 101:7cff1c4259d7 58 ((REGISTER) == I2C_Register_CMDR) || \
Kojto 101:7cff1c4259d7 59 ((REGISTER) == I2C_Register_SR) || \
Kojto 101:7cff1c4259d7 60 ((REGISTER) == I2C_Register_TSR) || \
Kojto 101:7cff1c4259d7 61 ((REGISTER) == I2C_Register_SADDR) || \
Kojto 101:7cff1c4259d7 62 ((REGISTER) == I2C_Register_TXR) || \
Kojto 101:7cff1c4259d7 63 ((REGISTER) == I2C_Register_RXR) || \
Kojto 101:7cff1c4259d7 64 ((REGISTER) == I2C_Register_ISR)|| \
Kojto 101:7cff1c4259d7 65 ((REGISTER) == I2C_Register_ISCR)| \
Kojto 101:7cff1c4259d7 66 ((REGISTER) == I2C_Register_ISMR))
Kojto 101:7cff1c4259d7 67 /**
Kojto 101:7cff1c4259d7 68 * @}
Kojto 101:7cff1c4259d7 69 */
Kojto 101:7cff1c4259d7 70 /** @addtogroup Peripheral_registers_structures
Kojto 101:7cff1c4259d7 71 * @{
Kojto 101:7cff1c4259d7 72 */
Kojto 101:7cff1c4259d7 73
Kojto 101:7cff1c4259d7 74
Kojto 101:7cff1c4259d7 75
Kojto 101:7cff1c4259d7 76
Kojto 101:7cff1c4259d7 77
Kojto 101:7cff1c4259d7 78
Kojto 101:7cff1c4259d7 79 /**
Kojto 101:7cff1c4259d7 80 * @}
Kojto 101:7cff1c4259d7 81 */
Kojto 101:7cff1c4259d7 82
Kojto 101:7cff1c4259d7 83 /**
Kojto 101:7cff1c4259d7 84 * @brief I2C Interrput Status Register Mask flags
Kojto 101:7cff1c4259d7 85 */
Kojto 101:7cff1c4259d7 86 //------------------------------------------------
Kojto 101:7cff1c4259d7 87 // I2C_ISMR_BIT
Kojto 101:7cff1c4259d7 88 //------------------------------------------------
Kojto 101:7cff1c4259d7 89
Kojto 101:7cff1c4259d7 90 /**
Kojto 101:7cff1c4259d7 91 * @}
Kojto 101:7cff1c4259d7 92 */
Kojto 101:7cff1c4259d7 93
Kojto 101:7cff1c4259d7 94 /** @defgroup I2C_Private_Defines
Kojto 101:7cff1c4259d7 95 * @{
Kojto 101:7cff1c4259d7 96 */
Kojto 101:7cff1c4259d7 97 /* I2C COREEN mask */
Kojto 101:7cff1c4259d7 98 #define I2C_CTR_COREEN_DIS ((uint16_t)0xFF7F)
Kojto 101:7cff1c4259d7 99
Kojto 101:7cff1c4259d7 100 /* I2C INTEREN mask */
Kojto 101:7cff1c4259d7 101 #define I2C_CTR_INTEREN_DIS ((uint16_t)0xFFBF)
Kojto 101:7cff1c4259d7 102
Kojto 101:7cff1c4259d7 103 /* I2C MODE(M/SN) mask */
Kojto 101:7cff1c4259d7 104 #define I2C_CTR_MODE_SLAVE ((uint16_t)0xFFDF)
Kojto 101:7cff1c4259d7 105
Kojto 101:7cff1c4259d7 106 /* I2C ADDR10(10/7N) mask */
Kojto 101:7cff1c4259d7 107 #define I2C_CTR_ADDR10_7BIT ((uint16_t)0xFFEF)
Kojto 101:7cff1c4259d7 108
Kojto 101:7cff1c4259d7 109 /* I2C CTRRWN(R/WN) mask */
Kojto 101:7cff1c4259d7 110 #define I2C_CTR_CTRRWN_DIS ((uint16_t)0xFFF7)
Kojto 101:7cff1c4259d7 111
Kojto 101:7cff1c4259d7 112 /* I2C CTREN mask */
Kojto 101:7cff1c4259d7 113 #define I2C_CTR_CTEN_DIS ((uint16_t)0xFFFB)
Kojto 101:7cff1c4259d7 114
Kojto 101:7cff1c4259d7 115
Kojto 101:7cff1c4259d7 116 /* I2C START mask */
Kojto 101:7cff1c4259d7 117 #define I2C_CMDR_START_DIS ((uint16_t)0xFF7F)
Kojto 101:7cff1c4259d7 118
Kojto 101:7cff1c4259d7 119 /* I2C STOP mask */
Kojto 101:7cff1c4259d7 120 #define I2C_CMDR_STOP_DIS ((uint16_t)0xFFBF)
Kojto 101:7cff1c4259d7 121
Kojto 101:7cff1c4259d7 122 /* I2C ACK mask */
Kojto 101:7cff1c4259d7 123 #define I2C_CMDR_ACK_NAK ((uint16_t)0xFFDF)
Kojto 101:7cff1c4259d7 124
Kojto 101:7cff1c4259d7 125 /* I2C RESTART mask */
Kojto 101:7cff1c4259d7 126 #define I2C_CMDR_RESTA_DIS ((uint16_t)0xFFEF)
Kojto 101:7cff1c4259d7 127
Kojto 101:7cff1c4259d7 128 /* I2C INTERRUPT RESET mask */
Kojto 101:7cff1c4259d7 129 #define I2C_ISCR_RST_DIS ((uint16_t)0xFFFE)
Kojto 101:7cff1c4259d7 130 /**
Kojto 101:7cff1c4259d7 131 * @}
Kojto 101:7cff1c4259d7 132 */
Kojto 101:7cff1c4259d7 133
Kojto 101:7cff1c4259d7 134
Kojto 101:7cff1c4259d7 135
Kojto 101:7cff1c4259d7 136 #define I2C_WRITE 0
Kojto 101:7cff1c4259d7 137 #define I2C_READ 1
Kojto 101:7cff1c4259d7 138 #define I2C_RWSEL(NewState) (((NewState) == I2C_WRITE)|| \
Kojto 101:7cff1c4259d7 139 ((NewState) == I2C_READ))
Kojto 101:7cff1c4259d7 140
Kojto 101:7cff1c4259d7 141
Kojto 101:7cff1c4259d7 142 #define I2C_Ack_Enable (0x01ul << 5)
Kojto 101:7cff1c4259d7 143 #define I2C_Ack_Disable (0x00ul << 5)
Kojto 101:7cff1c4259d7 144 #define IS_I2C_ACK_NewState(NewState) (((NewState) == I2C_Ack_Enable) || \
Kojto 101:7cff1c4259d7 145 ((NewState) == I2C_Ack_Disable))
Kojto 101:7cff1c4259d7 146
Kojto 101:7cff1c4259d7 147 #define I2C_MASTER_MODE (0x01ul << 5 ) // 0x20
Kojto 101:7cff1c4259d7 148 #define I2C_SLAVE_MODE (0x00ul << 5 ) // 0x20
Kojto 101:7cff1c4259d7 149 #define IS_I2C_MODE(MODE) ((MODE) == I2C_MASTER_MODE)|| \
Kojto 101:7cff1c4259d7 150 (MODE) == I2C_SLAVE_MODE))
Kojto 101:7cff1c4259d7 151
Kojto 101:7cff1c4259d7 152 #define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
Kojto 101:7cff1c4259d7 153
Kojto 101:7cff1c4259d7 154 #define SLAVE_ADDR10 0x208
Kojto 101:7cff1c4259d7 155
Kojto 101:7cff1c4259d7 156
Kojto 101:7cff1c4259d7 157 typedef enum
Kojto 101:7cff1c4259d7 158 {
Kojto 101:7cff1c4259d7 159 I2C_Master = I2C_MASTER_MODE,
Kojto 101:7cff1c4259d7 160 I2C_Slave = I2C_SLAVE_MODE
Kojto 101:7cff1c4259d7 161 }I2C_MODE;
Kojto 101:7cff1c4259d7 162
Kojto 101:7cff1c4259d7 163
Kojto 101:7cff1c4259d7 164 typedef struct
Kojto 101:7cff1c4259d7 165 {
Kojto 101:7cff1c4259d7 166 uint8_t prescale;
Kojto 101:7cff1c4259d7 167 uint16_t timeout;
Kojto 101:7cff1c4259d7 168 I2C_CTR control;
Kojto 101:7cff1c4259d7 169 }I2C_MasterConfStruct;
Kojto 101:7cff1c4259d7 170
Kojto 101:7cff1c4259d7 171
Kojto 101:7cff1c4259d7 172 typedef struct
Kojto 101:7cff1c4259d7 173 {
Kojto 101:7cff1c4259d7 174 uint32_t mode;
Kojto 101:7cff1c4259d7 175 uint16_t slave_address; // only on slave mode
Kojto 101:7cff1c4259d7 176 I2C_MasterConfStruct master;
Kojto 101:7cff1c4259d7 177 }I2C_ConfigStruct;
Kojto 101:7cff1c4259d7 178
Kojto 101:7cff1c4259d7 179
Kojto 101:7cff1c4259d7 180 /** @defgroup I2C_Exported_Functions
Kojto 101:7cff1c4259d7 181 * @{
Kojto 101:7cff1c4259d7 182 */
Kojto 101:7cff1c4259d7 183
Kojto 101:7cff1c4259d7 184 uint32_t I2C_Init (I2C_TypeDef* I2Cx, I2C_ConfigStruct conf);
Kojto 101:7cff1c4259d7 185 void setFrequency (I2C_TypeDef* I2Cx, uint8_t prescale);
Kojto 101:7cff1c4259d7 186 void I2C_DeInit (I2C_TypeDef* I2Cx);
Kojto 101:7cff1c4259d7 187
Kojto 101:7cff1c4259d7 188 ErrorStatus I2C_Start (I2C_TypeDef* I2Cx, uint16_t slave_address, I2C_CTR ctr);
Kojto 101:7cff1c4259d7 189 void I2C_Stop (I2C_TypeDef* I2Cx);
Kojto 101:7cff1c4259d7 190 void I2C_Reset (I2C_TypeDef* I2Cx);
Kojto 101:7cff1c4259d7 191
Kojto 101:7cff1c4259d7 192 void I2C_SendData (I2C_TypeDef* I2Cx,uint16_t Data);
Kojto 101:7cff1c4259d7 193 int8_t I2C_SendDataAck (I2C_TypeDef* I2Cx,uint16_t Data);
Kojto 101:7cff1c4259d7 194 int I2C_ReceiveData (I2C_TypeDef* I2Cx, int last);
Kojto 101:7cff1c4259d7 195
Kojto 101:7cff1c4259d7 196 int I2C_Burst_Read (I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop);
Kojto 101:7cff1c4259d7 197 int I2C_Burst_Write (I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop);
Kojto 101:7cff1c4259d7 198
Kojto 101:7cff1c4259d7 199 void I2C_Delay (uint32_t nCount);
Kojto 101:7cff1c4259d7 200
Kojto 101:7cff1c4259d7 201 void I2C_GenerateSTART (I2C_TypeDef* I2Cx, FunctionalState NewState);
Kojto 101:7cff1c4259d7 202 void I2C_GenerateSTOP (I2C_TypeDef* I2Cx, FunctionalState NewState);
Kojto 101:7cff1c4259d7 203
Kojto 101:7cff1c4259d7 204 void I2C_AcknowledgeConfig (I2C_TypeDef* I2Cx, FunctionalState NewState);
Kojto 101:7cff1c4259d7 205 void I2C_RESTART (I2C_TypeDef * I2Cx, FunctionalState NewState);
Kojto 101:7cff1c4259d7 206
Kojto 101:7cff1c4259d7 207 void I2C_CoreEn (I2C_TypeDef* I2Cx,FunctionalState NewState);
Kojto 101:7cff1c4259d7 208 void I2C_InterEn (I2C_TypeDef* I2Cx,FunctionalState NewState);
Kojto 101:7cff1c4259d7 209 void I2C_MasterSlave(I2C_TypeDef* I2Cx,FunctionalState NewState);
Kojto 101:7cff1c4259d7 210 void I2C_ControlRW (I2C_TypeDef* I2Cx,FunctionalState NewState);
Kojto 101:7cff1c4259d7 211 void I2C_ControlEn (I2C_TypeDef* I2Cx,FunctionalState NewState);
Kojto 101:7cff1c4259d7 212
Kojto 101:7cff1c4259d7 213 void I2C_InterRst (I2C_TypeDef* I2Cx,FunctionalState NewState);
Kojto 101:7cff1c4259d7 214 void I2C_Prescale (I2C_TypeDef* I2Cx,uint16_t Data);
Kojto 101:7cff1c4259d7 215 void I2C_TimeoutSet (I2C_TypeDef* I2Cx,uint16_t Data);
Kojto 101:7cff1c4259d7 216 void I2C_SetSlavAddress (I2C_TypeDef* I2Cx,uint16_t Data);
Kojto 101:7cff1c4259d7 217 uint8_t I2C_StatusRead (I2C_TypeDef* I2Cx);
Kojto 101:7cff1c4259d7 218
Kojto 101:7cff1c4259d7 219 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,I2C_SR sr);
Kojto 101:7cff1c4259d7 220
Kojto 101:7cff1c4259d7 221 void I2C_MasterInit (I2C_TypeDef * I2Cx,uint8_t Prescale,uint16_t Timeout,I2C_CTR Ctr);
Kojto 101:7cff1c4259d7 222 void I2C_SlaveInit (I2C_TypeDef * I2Cx,FunctionalState NewState, uint16_t data);
Kojto 101:7cff1c4259d7 223 void I2C_SendSlaveAddress (I2C_TypeDef* I2Cx, uint8_t SlaveAddress,I2C_CTR Ctr);
Kojto 101:7cff1c4259d7 224
Kojto 101:7cff1c4259d7 225 int8_t I2C_Restart_Structure(I2C_TypeDef * I2Cx,uint32_t SlaveAddress,I2C_CTR Ctr);
Kojto 101:7cff1c4259d7 226 uint16_t I2C_ReadRegister (I2C_TypeDef* I2Cx, uint8_t I2C_Register);
Kojto 101:7cff1c4259d7 227
Kojto 101:7cff1c4259d7 228 /**
Kojto 101:7cff1c4259d7 229 * @}
Kojto 101:7cff1c4259d7 230 */
Kojto 101:7cff1c4259d7 231