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TARGET_NUCLEO_L053R8/stm32l0xx_hal_pwr.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Parent:
84:0b3ab51c8877
Child:
96:487b796308b0
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_pwr.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 18-June-2014
bogdanm 84:0b3ab51c8877 7 * @brief Header file of PWR HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
bogdanm 84:0b3ab51c8877 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_PWR_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_PWR_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
bogdanm 84:0b3ab51c8877 53 /** @addtogroup PWR
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
bogdanm 84:0b3ab51c8877 57 /* Exported types ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 58 /**
bogdanm 84:0b3ab51c8877 59 * @brief PWR PVD configuration structure definition
bogdanm 84:0b3ab51c8877 60 */
bogdanm 84:0b3ab51c8877 61 typedef struct
bogdanm 84:0b3ab51c8877 62 {
bogdanm 84:0b3ab51c8877 63 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
bogdanm 84:0b3ab51c8877 64 This parameter can be a value of @ref PWR_PVD_detection_level */
bogdanm 84:0b3ab51c8877 65
bogdanm 84:0b3ab51c8877 66 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
bogdanm 84:0b3ab51c8877 67 This parameter can be a value of @ref PWR_PVD_Mode */
bogdanm 84:0b3ab51c8877 68 }PWR_PVDTypeDef;
bogdanm 84:0b3ab51c8877 69
bogdanm 84:0b3ab51c8877 70 /* Exported constants --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 71
bogdanm 84:0b3ab51c8877 72 /** @defgroup PWR_Exported_Constants
bogdanm 84:0b3ab51c8877 73 * @{
bogdanm 84:0b3ab51c8877 74 */
bogdanm 84:0b3ab51c8877 75
bogdanm 84:0b3ab51c8877 76 /** @defgroup PWR_WakeUp_Pins
bogdanm 84:0b3ab51c8877 77 * @{
bogdanm 84:0b3ab51c8877 78 */
bogdanm 84:0b3ab51c8877 79
bogdanm 84:0b3ab51c8877 80 #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1
bogdanm 84:0b3ab51c8877 81 #define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2
bogdanm 84:0b3ab51c8877 82 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
bogdanm 84:0b3ab51c8877 83 ((PIN) == PWR_WAKEUP_PIN2))
bogdanm 84:0b3ab51c8877 84 /**
bogdanm 84:0b3ab51c8877 85 * @}
bogdanm 84:0b3ab51c8877 86 */
bogdanm 84:0b3ab51c8877 87
bogdanm 84:0b3ab51c8877 88 /** @defgroup PWR_PVD_detection_level
bogdanm 84:0b3ab51c8877 89 * @{
bogdanm 84:0b3ab51c8877 90 */
bogdanm 84:0b3ab51c8877 91 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
bogdanm 84:0b3ab51c8877 92 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
bogdanm 84:0b3ab51c8877 93 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
bogdanm 84:0b3ab51c8877 94 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
bogdanm 84:0b3ab51c8877 95 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
bogdanm 84:0b3ab51c8877 96 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
bogdanm 84:0b3ab51c8877 97 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
bogdanm 84:0b3ab51c8877 98 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage
bogdanm 84:0b3ab51c8877 99 (Compare internally to VREFINT) */
bogdanm 84:0b3ab51c8877 100 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
bogdanm 84:0b3ab51c8877 101 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
bogdanm 84:0b3ab51c8877 102 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
bogdanm 84:0b3ab51c8877 103 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
bogdanm 84:0b3ab51c8877 104 /**
bogdanm 84:0b3ab51c8877 105 * @}
bogdanm 84:0b3ab51c8877 106 */
bogdanm 84:0b3ab51c8877 107
bogdanm 84:0b3ab51c8877 108 /** @defgroup PWR_PVD_Mode
bogdanm 84:0b3ab51c8877 109 * @{
bogdanm 84:0b3ab51c8877 110 */
bogdanm 84:0b3ab51c8877 111 #define PWR_MODE_EVT ((uint32_t)0x00000000) /*!< No Interrupt */
bogdanm 84:0b3ab51c8877 112 #define PWR_MODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
bogdanm 84:0b3ab51c8877 113 #define PWR_MODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
bogdanm 84:0b3ab51c8877 114 #define PWR_MODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
bogdanm 84:0b3ab51c8877 115 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \
bogdanm 84:0b3ab51c8877 116 ((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING))
bogdanm 84:0b3ab51c8877 117 /**
bogdanm 84:0b3ab51c8877 118 * @}
bogdanm 84:0b3ab51c8877 119 */
bogdanm 84:0b3ab51c8877 120
bogdanm 84:0b3ab51c8877 121 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode
bogdanm 84:0b3ab51c8877 122 * @{
bogdanm 84:0b3ab51c8877 123 */
bogdanm 84:0b3ab51c8877 124 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 125 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
bogdanm 84:0b3ab51c8877 126
bogdanm 84:0b3ab51c8877 127 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
bogdanm 84:0b3ab51c8877 128 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
bogdanm 84:0b3ab51c8877 129 /**
bogdanm 84:0b3ab51c8877 130 * @}
bogdanm 84:0b3ab51c8877 131 */
bogdanm 84:0b3ab51c8877 132
bogdanm 84:0b3ab51c8877 133 /** @defgroup PWR_SLEEP_mode_entry
bogdanm 84:0b3ab51c8877 134 * @{
bogdanm 84:0b3ab51c8877 135 */
bogdanm 84:0b3ab51c8877 136 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 137 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
bogdanm 84:0b3ab51c8877 138 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
bogdanm 84:0b3ab51c8877 139 /**
bogdanm 84:0b3ab51c8877 140 * @}
bogdanm 84:0b3ab51c8877 141 */
bogdanm 84:0b3ab51c8877 142
bogdanm 84:0b3ab51c8877 143 /** @defgroup PWR_STOP_mode_entry
bogdanm 84:0b3ab51c8877 144 * @{
bogdanm 84:0b3ab51c8877 145 */
bogdanm 84:0b3ab51c8877 146 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 147 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
bogdanm 84:0b3ab51c8877 148 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
bogdanm 84:0b3ab51c8877 149 /**
bogdanm 84:0b3ab51c8877 150 * @}
bogdanm 84:0b3ab51c8877 151 */
bogdanm 84:0b3ab51c8877 152
bogdanm 84:0b3ab51c8877 153 /** @defgroup PWR_Regulator_Voltage_Scale
bogdanm 84:0b3ab51c8877 154 * @{
bogdanm 84:0b3ab51c8877 155 */
bogdanm 84:0b3ab51c8877 156
bogdanm 84:0b3ab51c8877 157 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0
bogdanm 84:0b3ab51c8877 158 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
bogdanm 84:0b3ab51c8877 159 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS
bogdanm 84:0b3ab51c8877 160
bogdanm 84:0b3ab51c8877 161 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
bogdanm 84:0b3ab51c8877 162 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
bogdanm 84:0b3ab51c8877 163 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
bogdanm 84:0b3ab51c8877 164 /**
bogdanm 84:0b3ab51c8877 165 * @}
bogdanm 84:0b3ab51c8877 166 */
bogdanm 84:0b3ab51c8877 167
bogdanm 92:4fc01daae5a5 168 /** @defgroup PWR_Flag
bogdanm 84:0b3ab51c8877 169 * @{
bogdanm 84:0b3ab51c8877 170 */
bogdanm 84:0b3ab51c8877 171 #define PWR_FLAG_WU PWR_CSR_WUF
bogdanm 84:0b3ab51c8877 172 #define PWR_FLAG_SB PWR_CSR_SBF
bogdanm 84:0b3ab51c8877 173 #define PWR_FLAG_PVDO PWR_CSR_PVDO
bogdanm 84:0b3ab51c8877 174 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
bogdanm 84:0b3ab51c8877 175 #define PWR_FLAG_VOS PWR_CSR_VOSF
bogdanm 84:0b3ab51c8877 176 #define PWR_FLAG_REGLP PWR_CSR_REGLPF
bogdanm 84:0b3ab51c8877 177
bogdanm 84:0b3ab51c8877 178 /**
bogdanm 84:0b3ab51c8877 179 * @}
bogdanm 84:0b3ab51c8877 180 */
bogdanm 84:0b3ab51c8877 181
bogdanm 84:0b3ab51c8877 182 /**
bogdanm 84:0b3ab51c8877 183 * @}
bogdanm 84:0b3ab51c8877 184 */
bogdanm 84:0b3ab51c8877 185
bogdanm 84:0b3ab51c8877 186 /* Exported macro ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 187 /** @defgroup PWR_Exported_Macro
bogdanm 84:0b3ab51c8877 188 * @{
bogdanm 84:0b3ab51c8877 189 */
bogdanm 84:0b3ab51c8877 190
bogdanm 84:0b3ab51c8877 191 /** @brief macros configure the main internal regulator output voltage.
bogdanm 84:0b3ab51c8877 192 * @param __REGULATOR__: specifies the regulator output voltage to achieve
bogdanm 84:0b3ab51c8877 193 * a tradeoff between performance and power consumption when the device does
bogdanm 84:0b3ab51c8877 194 * not operate at the maximum frequency (refer to the datasheets for more details).
bogdanm 84:0b3ab51c8877 195 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 196 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
bogdanm 84:0b3ab51c8877 197 * System frequency up to 32 MHz.
bogdanm 84:0b3ab51c8877 198 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
bogdanm 84:0b3ab51c8877 199 * System frequency up to 16 MHz.
bogdanm 84:0b3ab51c8877 200 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
bogdanm 84:0b3ab51c8877 201 * System frequency up to 4.2 MHz
bogdanm 84:0b3ab51c8877 202 * @retval None
bogdanm 84:0b3ab51c8877 203 */
bogdanm 84:0b3ab51c8877 204 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
bogdanm 84:0b3ab51c8877 205
bogdanm 84:0b3ab51c8877 206 /** @brief Check PWR flag is set or not.
bogdanm 84:0b3ab51c8877 207 * @param __FLAG__: specifies the flag to check.
bogdanm 84:0b3ab51c8877 208 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 209 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
bogdanm 84:0b3ab51c8877 210 * was received from the WKUP pin or from the RTC alarm (Alarm B),
bogdanm 84:0b3ab51c8877 211 * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
bogdanm 84:0b3ab51c8877 212 * An additional wakeup event is detected if the WKUP pin is enabled
bogdanm 84:0b3ab51c8877 213 * (by setting the EWUP bit) when the WKUP pin level is already high.
bogdanm 84:0b3ab51c8877 214 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
bogdanm 84:0b3ab51c8877 215 * resumed from StandBy mode.
bogdanm 84:0b3ab51c8877 216 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
bogdanm 84:0b3ab51c8877 217 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
bogdanm 84:0b3ab51c8877 218 * For this reason, this bit is equal to 0 after Standby or reset
bogdanm 84:0b3ab51c8877 219 * until the PVDE bit is set.
bogdanm 84:0b3ab51c8877 220 * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
bogdanm 84:0b3ab51c8877 221 * This bit indicates the state of the internal voltage reference, VREFINT.
bogdanm 84:0b3ab51c8877 222 * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
bogdanm 84:0b3ab51c8877 223 * the internal regulator to be ready after the voltage range is changed.
bogdanm 84:0b3ab51c8877 224 * The VOSF bit indicates that the regulator has reached the voltage level
bogdanm 84:0b3ab51c8877 225 * defined with bits VOS of PWR_CR register.
bogdanm 84:0b3ab51c8877 226 * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
bogdanm 84:0b3ab51c8877 227 * mode, this bit stays at 1 until the regulator is ready in main mode.
bogdanm 84:0b3ab51c8877 228 * A polling on this bit is recommended to wait for the regulator main mode.
bogdanm 84:0b3ab51c8877 229 * This bit is reset by hardware when the regulator is ready.
bogdanm 84:0b3ab51c8877 230 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 231 */
bogdanm 84:0b3ab51c8877 232 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
bogdanm 84:0b3ab51c8877 233
bogdanm 84:0b3ab51c8877 234 /** @brief Clear the PWR's pending flags.
bogdanm 84:0b3ab51c8877 235 * @param __FLAG__: specifies the flag to clear.
bogdanm 84:0b3ab51c8877 236 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 237 * @arg PWR_FLAG_WU: Wake Up flag
bogdanm 84:0b3ab51c8877 238 * @arg PWR_FLAG_SB: StandBy flag
bogdanm 84:0b3ab51c8877 239 */
bogdanm 84:0b3ab51c8877 240 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
bogdanm 84:0b3ab51c8877 241
bogdanm 84:0b3ab51c8877 242 #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
bogdanm 84:0b3ab51c8877 243 /**
bogdanm 84:0b3ab51c8877 244 * @brief Enable the PVD Exti Line.
bogdanm 84:0b3ab51c8877 245 * @param __EXTILINE__: specifies the PVD Exti sources to be enabled.
bogdanm 84:0b3ab51c8877 246 * This parameter can be:
bogdanm 84:0b3ab51c8877 247 * @arg PWR_EXTI_LINE_PVD
bogdanm 84:0b3ab51c8877 248 * @retval None.
bogdanm 84:0b3ab51c8877 249 */
bogdanm 84:0b3ab51c8877 250 #define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
bogdanm 84:0b3ab51c8877 251
bogdanm 84:0b3ab51c8877 252 /**
bogdanm 84:0b3ab51c8877 253 * @brief Disable the PVD EXTI Line.
bogdanm 84:0b3ab51c8877 254 * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
bogdanm 84:0b3ab51c8877 255 * This parameter can be:
bogdanm 84:0b3ab51c8877 256 * @arg PWR_EXTI_LINE_PVD
bogdanm 84:0b3ab51c8877 257 * @retval None.
bogdanm 84:0b3ab51c8877 258 */
bogdanm 84:0b3ab51c8877 259 #define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
bogdanm 84:0b3ab51c8877 260
bogdanm 84:0b3ab51c8877 261 /**
bogdanm 84:0b3ab51c8877 262 * @brief Generates a Software interrupt on selected EXTI line.
bogdanm 84:0b3ab51c8877 263 * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
bogdanm 84:0b3ab51c8877 264 * This parameter can be:
bogdanm 84:0b3ab51c8877 265 * @arg PWR_EXTI_LINE_PVD
bogdanm 84:0b3ab51c8877 266 * @retval None
bogdanm 84:0b3ab51c8877 267 */
bogdanm 84:0b3ab51c8877 268 #define __HAL_PVD_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
bogdanm 84:0b3ab51c8877 269
bogdanm 84:0b3ab51c8877 270 /**
bogdanm 84:0b3ab51c8877 271 * @brief checks whether the specified PVD Exti interrupt flag is set or not.
bogdanm 84:0b3ab51c8877 272 * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
bogdanm 84:0b3ab51c8877 273 * This parameter can be:
bogdanm 84:0b3ab51c8877 274 * @arg PWR_EXTI_LINE_PVD
bogdanm 84:0b3ab51c8877 275 * @retval EXTI PVD Line Status.
bogdanm 84:0b3ab51c8877 276 */
bogdanm 84:0b3ab51c8877 277 #define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__) (EXTI->PR & (__EXTILINE__))
bogdanm 84:0b3ab51c8877 278
bogdanm 84:0b3ab51c8877 279 /**
bogdanm 84:0b3ab51c8877 280 * @brief Clear the PVD Exti flag.
bogdanm 84:0b3ab51c8877 281 * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
bogdanm 84:0b3ab51c8877 282 * This parameter can be:
bogdanm 84:0b3ab51c8877 283 * @arg PWR_EXTI_LINE_PVD
bogdanm 84:0b3ab51c8877 284 * @retval None.
bogdanm 84:0b3ab51c8877 285 */
bogdanm 84:0b3ab51c8877 286 #define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__) (EXTI->PR = (__EXTILINE__))
bogdanm 84:0b3ab51c8877 287
bogdanm 84:0b3ab51c8877 288 /**
bogdanm 84:0b3ab51c8877 289 * @}
bogdanm 84:0b3ab51c8877 290 */
bogdanm 84:0b3ab51c8877 291
bogdanm 84:0b3ab51c8877 292 /* Include PWR HAL Extension module */
bogdanm 84:0b3ab51c8877 293 #include "stm32l0xx_hal_pwr_ex.h"
bogdanm 84:0b3ab51c8877 294
bogdanm 84:0b3ab51c8877 295 /* Exported functions --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 296
bogdanm 84:0b3ab51c8877 297 /* Initialization and de-initialization functions *******************************/
bogdanm 84:0b3ab51c8877 298 void HAL_PWR_DeInit(void);
bogdanm 84:0b3ab51c8877 299 void HAL_PWR_EnableBkUpAccess(void);
bogdanm 84:0b3ab51c8877 300 void HAL_PWR_DisableBkUpAccess(void);
bogdanm 84:0b3ab51c8877 301
bogdanm 84:0b3ab51c8877 302 /* Peripheral Control functions ************************************************/
bogdanm 84:0b3ab51c8877 303 void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
bogdanm 84:0b3ab51c8877 304 void HAL_PWR_EnablePVD(void);
bogdanm 84:0b3ab51c8877 305 void HAL_PWR_DisablePVD(void);
bogdanm 84:0b3ab51c8877 306
bogdanm 84:0b3ab51c8877 307 /* WakeUp pins configuration functions ****************************************/
bogdanm 84:0b3ab51c8877 308 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 84:0b3ab51c8877 309 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 84:0b3ab51c8877 310
bogdanm 84:0b3ab51c8877 311 /* Low Power modes configuration functions ************************************/
bogdanm 84:0b3ab51c8877 312 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
bogdanm 84:0b3ab51c8877 313 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
bogdanm 84:0b3ab51c8877 314 void HAL_PWR_EnterSTANDBYMode(void);
bogdanm 84:0b3ab51c8877 315
bogdanm 84:0b3ab51c8877 316 void HAL_PWR_PVD_IRQHandler(void);
bogdanm 84:0b3ab51c8877 317 void HAL_PWR_PVDCallback(void);
bogdanm 84:0b3ab51c8877 318
bogdanm 84:0b3ab51c8877 319 /**
bogdanm 84:0b3ab51c8877 320 * @}
bogdanm 84:0b3ab51c8877 321 */
bogdanm 84:0b3ab51c8877 322
bogdanm 84:0b3ab51c8877 323 /**
bogdanm 84:0b3ab51c8877 324 * @}
bogdanm 84:0b3ab51c8877 325 */
bogdanm 84:0b3ab51c8877 326
bogdanm 84:0b3ab51c8877 327 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 328 }
bogdanm 84:0b3ab51c8877 329 #endif
bogdanm 84:0b3ab51c8877 330
bogdanm 84:0b3ab51c8877 331
bogdanm 84:0b3ab51c8877 332 #endif /* __STM32L0xx_HAL_PWR_H */
bogdanm 84:0b3ab51c8877 333
bogdanm 84:0b3ab51c8877 334 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/