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TARGET_NUCLEO_L053R8/stm32l0xx_hal_pwr.h@96:487b796308b0, 2015-03-17 (annotated)

Committer:
Kojto
Date:
Tue Mar 17 14:27:45 2015 +0000
Revision:
96:487b796308b0
Parent:
92:4fc01daae5a5 
Release 96 of the mbed library



Changes:

- IAR support for ble boards, lpc, ethernet stack

- RTC - attach function to redirect time functions

- Nucleo F103RB - cube driver

- k20xx - fixes for teensy and k20 platforms in sleep/deepsleep and usb

- STM32L0, Nucleo/Disco L053 - refactoring

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_pwr.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
Kojto 96:487b796308b0 5 * @version V1.2.0
Kojto 96:487b796308b0 6 * @date 06-February-2015
bogdanm 84:0b3ab51c8877 7 * @brief Header file of PWR HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
Kojto 96:487b796308b0 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_PWR_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_PWR_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
Kojto 96:487b796308b0 53 /** @defgroup PWR
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
Kojto 96:487b796308b0 57 /** @defgroup PWR_Exported_Types PWR Exported Types
Kojto 96:487b796308b0 58 * @{
Kojto 96:487b796308b0 59 */
Kojto 96:487b796308b0 60
bogdanm 84:0b3ab51c8877 61 /**
bogdanm 84:0b3ab51c8877 62 * @brief PWR PVD configuration structure definition
bogdanm 84:0b3ab51c8877 63 */
bogdanm 84:0b3ab51c8877 64 typedef struct
bogdanm 84:0b3ab51c8877 65 {
bogdanm 84:0b3ab51c8877 66 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
bogdanm 84:0b3ab51c8877 67 This parameter can be a value of @ref PWR_PVD_detection_level */
bogdanm 84:0b3ab51c8877 68
Kojto 96:487b796308b0 69 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
Kojto 96:487b796308b0 70 This parameter can be a value of @ref PWR_PVD_Mode */
bogdanm 84:0b3ab51c8877 71 }PWR_PVDTypeDef;
bogdanm 84:0b3ab51c8877 72
Kojto 96:487b796308b0 73 /**
Kojto 96:487b796308b0 74 * @}
bogdanm 84:0b3ab51c8877 75 */
bogdanm 84:0b3ab51c8877 76
Kojto 96:487b796308b0 77 /** @defgroup PWR_Private_Defines PWR Private Defines
bogdanm 84:0b3ab51c8877 78 * @{
Kojto 96:487b796308b0 79 */
bogdanm 84:0b3ab51c8877 80
Kojto 96:487b796308b0 81 #define PWR_EXTI_LINE_PVD EXTI_FTSR_TR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */
Kojto 96:487b796308b0 82
bogdanm 84:0b3ab51c8877 83 /**
bogdanm 84:0b3ab51c8877 84 * @}
bogdanm 84:0b3ab51c8877 85 */
bogdanm 84:0b3ab51c8877 86
Kojto 96:487b796308b0 87 /** @defgroup PWR_Exported_Constants PWR Exported Constants
Kojto 96:487b796308b0 88 * @{
Kojto 96:487b796308b0 89 */
Kojto 96:487b796308b0 90
Kojto 96:487b796308b0 91 /** @defgroup PWR_register_alias_address PWR Register alias address
bogdanm 84:0b3ab51c8877 92 * @{
bogdanm 84:0b3ab51c8877 93 */
Kojto 96:487b796308b0 94 #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1
Kojto 96:487b796308b0 95 #define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2
Kojto 96:487b796308b0 96 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
Kojto 96:487b796308b0 97 #define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3
Kojto 96:487b796308b0 98 #endif
Kojto 96:487b796308b0 99 /**
Kojto 96:487b796308b0 100 * @}
Kojto 96:487b796308b0 101 */
Kojto 96:487b796308b0 102
Kojto 96:487b796308b0 103 /** @defgroup PWR_PVD_detection_level PVD detection level
Kojto 96:487b796308b0 104 * @{
Kojto 96:487b796308b0 105 */
Kojto 96:487b796308b0 106 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
Kojto 96:487b796308b0 107 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
Kojto 96:487b796308b0 108 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
Kojto 96:487b796308b0 109 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
Kojto 96:487b796308b0 110 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
Kojto 96:487b796308b0 111 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
Kojto 96:487b796308b0 112 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
Kojto 96:487b796308b0 113 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage
Kojto 96:487b796308b0 114 (Compare internally to VREFINT) */
bogdanm 84:0b3ab51c8877 115 /**
bogdanm 84:0b3ab51c8877 116 * @}
bogdanm 84:0b3ab51c8877 117 */
bogdanm 84:0b3ab51c8877 118
Kojto 96:487b796308b0 119 /** @defgroup PWR_PVD_Mode PWR PVD Mode
bogdanm 84:0b3ab51c8877 120 * @{
bogdanm 84:0b3ab51c8877 121 */
Kojto 96:487b796308b0 122 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
Kojto 96:487b796308b0 123 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
Kojto 96:487b796308b0 124 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
Kojto 96:487b796308b0 125 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
Kojto 96:487b796308b0 126 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
Kojto 96:487b796308b0 127 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
Kojto 96:487b796308b0 128 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
Kojto 96:487b796308b0 129
bogdanm 84:0b3ab51c8877 130 /**
bogdanm 84:0b3ab51c8877 131 * @}
bogdanm 84:0b3ab51c8877 132 */
bogdanm 84:0b3ab51c8877 133
Kojto 96:487b796308b0 134 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
bogdanm 84:0b3ab51c8877 135 * @{
bogdanm 84:0b3ab51c8877 136 */
Kojto 96:487b796308b0 137 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
Kojto 96:487b796308b0 138 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
bogdanm 84:0b3ab51c8877 139
bogdanm 84:0b3ab51c8877 140 /**
bogdanm 84:0b3ab51c8877 141 * @}
bogdanm 84:0b3ab51c8877 142 */
bogdanm 84:0b3ab51c8877 143
Kojto 96:487b796308b0 144 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
bogdanm 84:0b3ab51c8877 145 * @{
bogdanm 84:0b3ab51c8877 146 */
Kojto 96:487b796308b0 147 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
Kojto 96:487b796308b0 148 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
bogdanm 84:0b3ab51c8877 149 /**
bogdanm 84:0b3ab51c8877 150 * @}
bogdanm 84:0b3ab51c8877 151 */
bogdanm 84:0b3ab51c8877 152
Kojto 96:487b796308b0 153 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
bogdanm 84:0b3ab51c8877 154 * @{
bogdanm 84:0b3ab51c8877 155 */
Kojto 96:487b796308b0 156 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
Kojto 96:487b796308b0 157 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
bogdanm 84:0b3ab51c8877 158 /**
bogdanm 84:0b3ab51c8877 159 * @}
bogdanm 84:0b3ab51c8877 160 */
bogdanm 84:0b3ab51c8877 161
Kojto 96:487b796308b0 162 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
bogdanm 84:0b3ab51c8877 163 * @{
bogdanm 84:0b3ab51c8877 164 */
bogdanm 84:0b3ab51c8877 165
Kojto 96:487b796308b0 166 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0
Kojto 96:487b796308b0 167 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
Kojto 96:487b796308b0 168 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS
bogdanm 84:0b3ab51c8877 169
bogdanm 84:0b3ab51c8877 170 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
bogdanm 84:0b3ab51c8877 171 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
bogdanm 84:0b3ab51c8877 172 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
bogdanm 84:0b3ab51c8877 173 /**
bogdanm 84:0b3ab51c8877 174 * @}
bogdanm 84:0b3ab51c8877 175 */
bogdanm 84:0b3ab51c8877 176
Kojto 96:487b796308b0 177 /** @defgroup PWR_Flag PWR Flag
bogdanm 84:0b3ab51c8877 178 * @{
bogdanm 84:0b3ab51c8877 179 */
Kojto 96:487b796308b0 180 #define PWR_FLAG_WU PWR_CSR_WUF
Kojto 96:487b796308b0 181 #define PWR_FLAG_SB PWR_CSR_SBF
Kojto 96:487b796308b0 182 #define PWR_FLAG_PVDO PWR_CSR_PVDO
Kojto 96:487b796308b0 183 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
Kojto 96:487b796308b0 184 #define PWR_FLAG_VOS PWR_CSR_VOSF
Kojto 96:487b796308b0 185 #define PWR_FLAG_REGLP PWR_CSR_REGLPF
bogdanm 84:0b3ab51c8877 186
Kojto 96:487b796308b0 187 #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
Kojto 96:487b796308b0 188 ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \
Kojto 96:487b796308b0 189 ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))
bogdanm 84:0b3ab51c8877 190 /**
bogdanm 84:0b3ab51c8877 191 * @}
bogdanm 84:0b3ab51c8877 192 */
bogdanm 84:0b3ab51c8877 193
bogdanm 84:0b3ab51c8877 194 /**
bogdanm 84:0b3ab51c8877 195 * @}
bogdanm 84:0b3ab51c8877 196 */
bogdanm 84:0b3ab51c8877 197
Kojto 96:487b796308b0 198 /** @defgroup PWR_Exported_Macro PWR Exported Macro
bogdanm 84:0b3ab51c8877 199 * @{
bogdanm 84:0b3ab51c8877 200 */
bogdanm 84:0b3ab51c8877 201 /** @brief macros configure the main internal regulator output voltage.
bogdanm 84:0b3ab51c8877 202 * @param __REGULATOR__: specifies the regulator output voltage to achieve
bogdanm 84:0b3ab51c8877 203 * a tradeoff between performance and power consumption when the device does
bogdanm 84:0b3ab51c8877 204 * not operate at the maximum frequency (refer to the datasheets for more details).
bogdanm 84:0b3ab51c8877 205 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 206 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
bogdanm 84:0b3ab51c8877 207 * System frequency up to 32 MHz.
bogdanm 84:0b3ab51c8877 208 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
bogdanm 84:0b3ab51c8877 209 * System frequency up to 16 MHz.
bogdanm 84:0b3ab51c8877 210 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
bogdanm 84:0b3ab51c8877 211 * System frequency up to 4.2 MHz
bogdanm 84:0b3ab51c8877 212 * @retval None
bogdanm 84:0b3ab51c8877 213 */
bogdanm 84:0b3ab51c8877 214 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
bogdanm 84:0b3ab51c8877 215
bogdanm 84:0b3ab51c8877 216 /** @brief Check PWR flag is set or not.
bogdanm 84:0b3ab51c8877 217 * @param __FLAG__: specifies the flag to check.
bogdanm 84:0b3ab51c8877 218 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 219 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
bogdanm 84:0b3ab51c8877 220 * was received from the WKUP pin or from the RTC alarm (Alarm B),
bogdanm 84:0b3ab51c8877 221 * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
bogdanm 84:0b3ab51c8877 222 * An additional wakeup event is detected if the WKUP pin is enabled
bogdanm 84:0b3ab51c8877 223 * (by setting the EWUP bit) when the WKUP pin level is already high.
bogdanm 84:0b3ab51c8877 224 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
bogdanm 84:0b3ab51c8877 225 * resumed from StandBy mode.
bogdanm 84:0b3ab51c8877 226 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
Kojto 96:487b796308b0 227 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
bogdanm 84:0b3ab51c8877 228 * For this reason, this bit is equal to 0 after Standby or reset
bogdanm 84:0b3ab51c8877 229 * until the PVDE bit is set.
bogdanm 84:0b3ab51c8877 230 * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
bogdanm 84:0b3ab51c8877 231 * This bit indicates the state of the internal voltage reference, VREFINT.
bogdanm 84:0b3ab51c8877 232 * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
bogdanm 84:0b3ab51c8877 233 * the internal regulator to be ready after the voltage range is changed.
bogdanm 84:0b3ab51c8877 234 * The VOSF bit indicates that the regulator has reached the voltage level
bogdanm 84:0b3ab51c8877 235 * defined with bits VOS of PWR_CR register.
bogdanm 84:0b3ab51c8877 236 * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
bogdanm 84:0b3ab51c8877 237 * mode, this bit stays at 1 until the regulator is ready in main mode.
bogdanm 84:0b3ab51c8877 238 * A polling on this bit is recommended to wait for the regulator main mode.
bogdanm 84:0b3ab51c8877 239 * This bit is reset by hardware when the regulator is ready.
bogdanm 84:0b3ab51c8877 240 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 241 */
Kojto 96:487b796308b0 242 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
bogdanm 84:0b3ab51c8877 243
bogdanm 84:0b3ab51c8877 244 /** @brief Clear the PWR's pending flags.
bogdanm 84:0b3ab51c8877 245 * @param __FLAG__: specifies the flag to clear.
bogdanm 84:0b3ab51c8877 246 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 247 * @arg PWR_FLAG_WU: Wake Up flag
bogdanm 84:0b3ab51c8877 248 * @arg PWR_FLAG_SB: StandBy flag
bogdanm 84:0b3ab51c8877 249 */
Kojto 96:487b796308b0 250 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2)
bogdanm 84:0b3ab51c8877 251
Kojto 96:487b796308b0 252 /**
Kojto 96:487b796308b0 253 * @brief Enable interrupt on PVD Exti Line 16.
Kojto 96:487b796308b0 254 * @retval None.
Kojto 96:487b796308b0 255 */
Kojto 96:487b796308b0 256 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
Kojto 96:487b796308b0 257
bogdanm 84:0b3ab51c8877 258 /**
Kojto 96:487b796308b0 259 * @brief Disable interrupt on PVD Exti Line 16.
Kojto 96:487b796308b0 260 * @retval None.
Kojto 96:487b796308b0 261 */
Kojto 96:487b796308b0 262 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
Kojto 96:487b796308b0 263
Kojto 96:487b796308b0 264 /**
Kojto 96:487b796308b0 265 * @brief Enable event on PVD Exti Line 16.
Kojto 96:487b796308b0 266 * @retval None.
Kojto 96:487b796308b0 267 */
Kojto 96:487b796308b0 268 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
Kojto 96:487b796308b0 269
Kojto 96:487b796308b0 270 /**
Kojto 96:487b796308b0 271 * @brief Disable event on PVD Exti Line 16.
bogdanm 84:0b3ab51c8877 272 * @retval None.
bogdanm 84:0b3ab51c8877 273 */
Kojto 96:487b796308b0 274 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
Kojto 96:487b796308b0 275
Kojto 96:487b796308b0 276
Kojto 96:487b796308b0 277 /**
Kojto 96:487b796308b0 278 * @brief PVD EXTI line configuration: set falling edge trigger.
Kojto 96:487b796308b0 279 * @retval None.
Kojto 96:487b796308b0 280 */
Kojto 96:487b796308b0 281 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Kojto 96:487b796308b0 282
Kojto 96:487b796308b0 283
Kojto 96:487b796308b0 284 /**
Kojto 96:487b796308b0 285 * @brief Disable the PVD Extended Interrupt Falling Trigger.
Kojto 96:487b796308b0 286 * @retval None.
Kojto 96:487b796308b0 287 */
Kojto 96:487b796308b0 288 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Kojto 96:487b796308b0 289
bogdanm 84:0b3ab51c8877 290
bogdanm 84:0b3ab51c8877 291 /**
Kojto 96:487b796308b0 292 * @brief PVD EXTI line configuration: set rising edge trigger.
bogdanm 84:0b3ab51c8877 293 * @retval None.
bogdanm 84:0b3ab51c8877 294 */
Kojto 96:487b796308b0 295 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Kojto 96:487b796308b0 296
Kojto 96:487b796308b0 297 /**
Kojto 96:487b796308b0 298 * @brief Disable the PVD Extended Interrupt Rising Trigger.
Kojto 96:487b796308b0 299 * This parameter can be:
Kojto 96:487b796308b0 300 * @retval None.
Kojto 96:487b796308b0 301 */
Kojto 96:487b796308b0 302 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Kojto 96:487b796308b0 303
Kojto 96:487b796308b0 304 /**
Kojto 96:487b796308b0 305 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
Kojto 96:487b796308b0 306 * @retval None.
Kojto 96:487b796308b0 307 */
Kojto 96:487b796308b0 308 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
bogdanm 84:0b3ab51c8877 309
bogdanm 84:0b3ab51c8877 310 /**
Kojto 96:487b796308b0 311 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
bogdanm 84:0b3ab51c8877 312 * This parameter can be:
Kojto 96:487b796308b0 313 * @retval None.
Kojto 96:487b796308b0 314 */
Kojto 96:487b796308b0 315 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()();
Kojto 96:487b796308b0 316
Kojto 96:487b796308b0 317
Kojto 96:487b796308b0 318
Kojto 96:487b796308b0 319 /**
Kojto 96:487b796308b0 320 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
Kojto 96:487b796308b0 321 * @retval EXTI PVD Line Status.
bogdanm 84:0b3ab51c8877 322 */
Kojto 96:487b796308b0 323 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
Kojto 96:487b796308b0 324
Kojto 96:487b796308b0 325 /**
Kojto 96:487b796308b0 326 * @brief Clear the PVD EXTI flag.
Kojto 96:487b796308b0 327 * @retval None.
Kojto 96:487b796308b0 328 */
Kojto 96:487b796308b0 329 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Kojto 96:487b796308b0 330
Kojto 96:487b796308b0 331 /**
Kojto 96:487b796308b0 332 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 96:487b796308b0 333 * @retval None.
Kojto 96:487b796308b0 334 */
Kojto 96:487b796308b0 335 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
Kojto 96:487b796308b0 336 /**
Kojto 96:487b796308b0 337 * @}
Kojto 96:487b796308b0 338 */
bogdanm 84:0b3ab51c8877 339
bogdanm 84:0b3ab51c8877 340 /**
Kojto 96:487b796308b0 341 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 96:487b796308b0 342 * @retval None.
bogdanm 84:0b3ab51c8877 343 */
Kojto 96:487b796308b0 344 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
bogdanm 84:0b3ab51c8877 345
bogdanm 84:0b3ab51c8877 346 /**
Kojto 96:487b796308b0 347 * @}
Kojto 96:487b796308b0 348 */
Kojto 96:487b796308b0 349
Kojto 96:487b796308b0 350 /** @defgroup PWR_Private_Macros PWR Private Macros
Kojto 96:487b796308b0 351 * @{
bogdanm 84:0b3ab51c8877 352 */
Kojto 96:487b796308b0 353 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
Kojto 96:487b796308b0 354 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
Kojto 96:487b796308b0 355 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
Kojto 96:487b796308b0 356 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
Kojto 96:487b796308b0 357
Kojto 96:487b796308b0 358 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
Kojto 96:487b796308b0 359 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
Kojto 96:487b796308b0 360 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
Kojto 96:487b796308b0 361 ((MODE) == PWR_PVD_MODE_NORMAL))
Kojto 96:487b796308b0 362
Kojto 96:487b796308b0 363 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
Kojto 96:487b796308b0 364 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
Kojto 96:487b796308b0 365 ((PIN) == PWR_WAKEUP_PIN2) || \
Kojto 96:487b796308b0 366 ((PIN) == PWR_WAKEUP_PIN3))
Kojto 96:487b796308b0 367 #else
Kojto 96:487b796308b0 368 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
Kojto 96:487b796308b0 369 ((PIN) == PWR_WAKEUP_PIN2))
Kojto 96:487b796308b0 370 #endif
Kojto 96:487b796308b0 371
Kojto 96:487b796308b0 372 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
Kojto 96:487b796308b0 373 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
Kojto 96:487b796308b0 374 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
Kojto 96:487b796308b0 375
Kojto 96:487b796308b0 376 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
bogdanm 84:0b3ab51c8877 377
bogdanm 84:0b3ab51c8877 378 /**
bogdanm 84:0b3ab51c8877 379 * @}
bogdanm 84:0b3ab51c8877 380 */
bogdanm 84:0b3ab51c8877 381
bogdanm 84:0b3ab51c8877 382 /* Include PWR HAL Extension module */
bogdanm 84:0b3ab51c8877 383 #include "stm32l0xx_hal_pwr_ex.h"
bogdanm 84:0b3ab51c8877 384
Kojto 96:487b796308b0 385 /** @defgroup PWR_Exported_Functions PWR Exported Functions
Kojto 96:487b796308b0 386 * @{
Kojto 96:487b796308b0 387 */
Kojto 96:487b796308b0 388
Kojto 96:487b796308b0 389 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 96:487b796308b0 390 * @{
Kojto 96:487b796308b0 391 */
bogdanm 84:0b3ab51c8877 392 void HAL_PWR_DeInit(void);
bogdanm 84:0b3ab51c8877 393 void HAL_PWR_EnableBkUpAccess(void);
bogdanm 84:0b3ab51c8877 394 void HAL_PWR_DisableBkUpAccess(void);
Kojto 96:487b796308b0 395 /**
Kojto 96:487b796308b0 396 * @}
Kojto 96:487b796308b0 397 */
bogdanm 84:0b3ab51c8877 398
Kojto 96:487b796308b0 399 /** @defgroup PWR_Exported_Functions_Group2 Low Power modes configuration functions
Kojto 96:487b796308b0 400 * @{
Kojto 96:487b796308b0 401 */
Kojto 96:487b796308b0 402
Kojto 96:487b796308b0 403 /* PVD control functions ************************************************/
Kojto 96:487b796308b0 404 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
bogdanm 84:0b3ab51c8877 405 void HAL_PWR_EnablePVD(void);
bogdanm 84:0b3ab51c8877 406 void HAL_PWR_DisablePVD(void);
Kojto 96:487b796308b0 407 void HAL_PWR_PVD_IRQHandler(void);
Kojto 96:487b796308b0 408 void HAL_PWR_PVDCallback(void);
bogdanm 84:0b3ab51c8877 409
bogdanm 84:0b3ab51c8877 410 /* WakeUp pins configuration functions ****************************************/
bogdanm 84:0b3ab51c8877 411 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 84:0b3ab51c8877 412 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 84:0b3ab51c8877 413
bogdanm 84:0b3ab51c8877 414 /* Low Power modes configuration functions ************************************/
bogdanm 84:0b3ab51c8877 415 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
bogdanm 84:0b3ab51c8877 416 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
bogdanm 84:0b3ab51c8877 417 void HAL_PWR_EnterSTANDBYMode(void);
bogdanm 84:0b3ab51c8877 418
Kojto 96:487b796308b0 419 void HAL_PWR_EnableSleepOnExit(void);
Kojto 96:487b796308b0 420 void HAL_PWR_DisableSleepOnExit(void);
Kojto 96:487b796308b0 421 void HAL_PWR_EnableSEVOnPend(void);
Kojto 96:487b796308b0 422 void HAL_PWR_DisableSEVOnPend(void);
Kojto 96:487b796308b0 423
Kojto 96:487b796308b0 424 /**
Kojto 96:487b796308b0 425 * @}
Kojto 96:487b796308b0 426 */
Kojto 96:487b796308b0 427
Kojto 96:487b796308b0 428 /**
Kojto 96:487b796308b0 429 * @}
Kojto 96:487b796308b0 430 */
bogdanm 84:0b3ab51c8877 431
bogdanm 84:0b3ab51c8877 432 /**
bogdanm 84:0b3ab51c8877 433 * @}
bogdanm 84:0b3ab51c8877 434 */
bogdanm 84:0b3ab51c8877 435
bogdanm 84:0b3ab51c8877 436 /**
bogdanm 84:0b3ab51c8877 437 * @}
bogdanm 84:0b3ab51c8877 438 */
bogdanm 84:0b3ab51c8877 439
bogdanm 84:0b3ab51c8877 440 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 441 }
bogdanm 84:0b3ab51c8877 442 #endif
bogdanm 84:0b3ab51c8877 443
bogdanm 84:0b3ab51c8877 444
bogdanm 84:0b3ab51c8877 445 #endif /* __STM32L0xx_HAL_PWR_H */
bogdanm 84:0b3ab51c8877 446
bogdanm 84:0b3ab51c8877 447 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 96:487b796308b0 448