Ricardo Benitez
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TARGET_NUCLEO_L053R8/stm32l0xx_hal_adc.h@92:4fc01daae5a5, 2014-11-27 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Nov 27 13:33:22 2014 +0000
- Revision:
- 92:4fc01daae5a5
- Parent:
- 84:0b3ab51c8877
- Child:
- 96:487b796308b0
Release 92 of the mbed libray
Main changes:
- nRF51822: fixed pin assignment issues
- ST targets moving to the STM32Cube driver
- LPC1439: fixed serial interrupt issue
- first Cortex-A platform supported in mbed (RZ_A1H)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 84:0b3ab51c8877 | 1 | /** |
| bogdanm | 84:0b3ab51c8877 | 2 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 3 | * @file stm32l0xx_hal_adc.h |
| bogdanm | 84:0b3ab51c8877 | 4 | * @author MCD Application Team |
| bogdanm | 92:4fc01daae5a5 | 5 | * @version V1.1.0 |
| bogdanm | 92:4fc01daae5a5 | 6 | * @date 18-June-2014 |
| bogdanm | 84:0b3ab51c8877 | 7 | * @brief This file contains all the functions prototypes for the ADC firmware |
| bogdanm | 84:0b3ab51c8877 | 8 | * library. |
| bogdanm | 84:0b3ab51c8877 | 9 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 10 | * @attention |
| bogdanm | 84:0b3ab51c8877 | 11 | * |
| bogdanm | 84:0b3ab51c8877 | 12 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 84:0b3ab51c8877 | 13 | * |
| bogdanm | 84:0b3ab51c8877 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 84:0b3ab51c8877 | 15 | * are permitted provided that the following conditions are met: |
| bogdanm | 84:0b3ab51c8877 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 84:0b3ab51c8877 | 17 | * this list of conditions and the following disclaimer. |
| bogdanm | 84:0b3ab51c8877 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 84:0b3ab51c8877 | 19 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 84:0b3ab51c8877 | 20 | * and/or other materials provided with the distribution. |
| bogdanm | 84:0b3ab51c8877 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 84:0b3ab51c8877 | 22 | * may be used to endorse or promote products derived from this software |
| bogdanm | 84:0b3ab51c8877 | 23 | * without specific prior written permission. |
| bogdanm | 84:0b3ab51c8877 | 24 | * |
| bogdanm | 84:0b3ab51c8877 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 84:0b3ab51c8877 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 84:0b3ab51c8877 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 84:0b3ab51c8877 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 84:0b3ab51c8877 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 84:0b3ab51c8877 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 84:0b3ab51c8877 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 84:0b3ab51c8877 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 84:0b3ab51c8877 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 84:0b3ab51c8877 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 84:0b3ab51c8877 | 35 | * |
| bogdanm | 84:0b3ab51c8877 | 36 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 37 | */ |
| bogdanm | 84:0b3ab51c8877 | 38 | |
| bogdanm | 84:0b3ab51c8877 | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 40 | #ifndef __STM32L0xx_ADC_H |
| bogdanm | 84:0b3ab51c8877 | 41 | #define __STM32L0xx_ADC_H |
| bogdanm | 84:0b3ab51c8877 | 42 | |
| bogdanm | 84:0b3ab51c8877 | 43 | #ifdef __cplusplus |
| bogdanm | 84:0b3ab51c8877 | 44 | extern "C" { |
| bogdanm | 84:0b3ab51c8877 | 45 | #endif |
| bogdanm | 84:0b3ab51c8877 | 46 | |
| bogdanm | 84:0b3ab51c8877 | 47 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 48 | #include "stm32l0xx_hal_def.h" |
| bogdanm | 84:0b3ab51c8877 | 49 | |
| bogdanm | 84:0b3ab51c8877 | 50 | /** @addtogroup STM32L0xx_HAL_Driver |
| bogdanm | 84:0b3ab51c8877 | 51 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 52 | */ |
| bogdanm | 84:0b3ab51c8877 | 53 | |
| bogdanm | 84:0b3ab51c8877 | 54 | /** @addtogroup ADC |
| bogdanm | 84:0b3ab51c8877 | 55 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 56 | */ |
| bogdanm | 84:0b3ab51c8877 | 57 | |
| bogdanm | 84:0b3ab51c8877 | 58 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 59 | /** |
| bogdanm | 84:0b3ab51c8877 | 60 | * @brief HAL State structures definition |
| bogdanm | 84:0b3ab51c8877 | 61 | */ |
| bogdanm | 84:0b3ab51c8877 | 62 | typedef enum |
| bogdanm | 84:0b3ab51c8877 | 63 | { |
| bogdanm | 84:0b3ab51c8877 | 64 | HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ |
| bogdanm | 84:0b3ab51c8877 | 65 | HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ |
| bogdanm | 84:0b3ab51c8877 | 66 | HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 67 | HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ |
| bogdanm | 84:0b3ab51c8877 | 68 | HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
| bogdanm | 84:0b3ab51c8877 | 69 | HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ |
| bogdanm | 84:0b3ab51c8877 | 70 | HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ |
| bogdanm | 84:0b3ab51c8877 | 71 | HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */ |
| bogdanm | 84:0b3ab51c8877 | 72 | }HAL_ADC_StateTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 73 | |
| bogdanm | 84:0b3ab51c8877 | 74 | |
| bogdanm | 84:0b3ab51c8877 | 75 | /** |
| bogdanm | 84:0b3ab51c8877 | 76 | * @brief ADC Oversampler structure definition |
| bogdanm | 84:0b3ab51c8877 | 77 | */ |
| bogdanm | 84:0b3ab51c8877 | 78 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 79 | { |
| bogdanm | 84:0b3ab51c8877 | 80 | uint32_t Ratio; /*!< Configures the oversampling ratio. |
| bogdanm | 84:0b3ab51c8877 | 81 | This parameter can be a value of @ref ADC_Oversampling_Ratio */ |
| bogdanm | 84:0b3ab51c8877 | 82 | uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. |
| bogdanm | 84:0b3ab51c8877 | 83 | This parameter can be a value of @ref ADC_Right_Bit_Shift */ |
| bogdanm | 84:0b3ab51c8877 | 84 | uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode |
| bogdanm | 84:0b3ab51c8877 | 85 | This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */ |
| bogdanm | 84:0b3ab51c8877 | 86 | |
| bogdanm | 84:0b3ab51c8877 | 87 | }ADC_OversamplingTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 88 | |
| bogdanm | 84:0b3ab51c8877 | 89 | /** |
| bogdanm | 84:0b3ab51c8877 | 90 | * @brief ADC Init structure definition |
| bogdanm | 84:0b3ab51c8877 | 91 | * @note The setting of these parameters with function HAL_ADC_Init() is conditioned by the ADC state. |
| bogdanm | 84:0b3ab51c8877 | 92 | * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed |
| bogdanm | 84:0b3ab51c8877 | 93 | * without error reporting (as it can be the expected behaviour in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly). |
| bogdanm | 84:0b3ab51c8877 | 94 | */ |
| bogdanm | 84:0b3ab51c8877 | 95 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 96 | { |
| bogdanm | 84:0b3ab51c8877 | 97 | uint32_t OversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled |
| bogdanm | 84:0b3ab51c8877 | 98 | This parameter can be set to ENABLE or DISABLE. |
| bogdanm | 84:0b3ab51c8877 | 99 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 100 | ADC_OversamplingTypeDef Oversample; /*!< Specifies the Oversampling parameters |
| bogdanm | 84:0b3ab51c8877 | 101 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 102 | uint32_t ClockPrescaler; /*!< Selects the ADC clock frequency. |
| bogdanm | 84:0b3ab51c8877 | 103 | This parameter can be a value of @ref ADC_ClockPrescaler |
| bogdanm | 84:0b3ab51c8877 | 104 | Note: This parameter can be modified only if ADC is disabled. */ |
| bogdanm | 84:0b3ab51c8877 | 105 | uint32_t Resolution; /*!< Configures the ADC resolution mode. |
| bogdanm | 84:0b3ab51c8877 | 106 | This parameter can be a value of @ref ADC_Resolution |
| bogdanm | 84:0b3ab51c8877 | 107 | Note: This parameter can be modified only if ADC is disabled. */ |
| bogdanm | 84:0b3ab51c8877 | 108 | uint32_t SamplingTime; /*!< The sample time value to be set for all channels. |
| bogdanm | 92:4fc01daae5a5 | 109 | This parameter can be a value of @ref ADC_sampling_times |
| bogdanm | 92:4fc01daae5a5 | 110 | Note: This parameter can be modified only if there is no conversion ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 111 | uint32_t ScanDirection; /*!< The scan sequence direction. |
| bogdanm | 92:4fc01daae5a5 | 112 | This parameter can be a value of @ref ADC_scan_direction |
| bogdanm | 84:0b3ab51c8877 | 113 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 114 | uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. |
| bogdanm | 92:4fc01daae5a5 | 115 | This parameter can be a value of @ref ADC_data_align |
| bogdanm | 84:0b3ab51c8877 | 116 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 117 | uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode. |
| bogdanm | 84:0b3ab51c8877 | 118 | This parameter can be set to ENABLE or DISABLE. |
| bogdanm | 84:0b3ab51c8877 | 119 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 120 | uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed |
| bogdanm | 84:0b3ab51c8877 | 121 | in Complete-sequence/Discontinuous-sequence. |
| bogdanm | 84:0b3ab51c8877 | 122 | Discontinuous mode can be enabled only if continuous mode is disabled. |
| bogdanm | 84:0b3ab51c8877 | 123 | This parameter can be set to ENABLE or DISABLE. |
| bogdanm | 84:0b3ab51c8877 | 124 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 125 | uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger. |
| bogdanm | 92:4fc01daae5a5 | 126 | This parameter can be a value of @ref ADC_External_trigger_Edge |
| bogdanm | 84:0b3ab51c8877 | 127 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 128 | uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion. |
| bogdanm | 92:4fc01daae5a5 | 129 | This parameter can be a value of @ref ADC_External_trigger_Source |
| bogdanm | 84:0b3ab51c8877 | 130 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 131 | uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) |
| bogdanm | 84:0b3ab51c8877 | 132 | or in Continuous mode (DMA transfer unlimited, whatever number of conversions). |
| bogdanm | 84:0b3ab51c8877 | 133 | Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer max pointer is reached. |
| bogdanm | 84:0b3ab51c8877 | 134 | This parameter can be set to ENABLE or DISABLE. |
| bogdanm | 84:0b3ab51c8877 | 135 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 136 | uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion polling and interruption: |
| bogdanm | 84:0b3ab51c8877 | 137 | end of single channel conversion or end of channels conversions sequence. |
| bogdanm | 92:4fc01daae5a5 | 138 | This parameter can be a value of @ref ADC_EOCSelection */ |
| bogdanm | 84:0b3ab51c8877 | 139 | uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten |
| bogdanm | 84:0b3ab51c8877 | 140 | This parameter has an effect on regular channels only, including in DMA mode. |
| bogdanm | 92:4fc01daae5a5 | 141 | This parameter can be a value of @ref ADC_Overrun |
| bogdanm | 84:0b3ab51c8877 | 142 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 143 | uint32_t LowPowerAutoWait; /*!< Specifies the usage of dynamic low power Auto Delay: new conversion start only |
| bogdanm | 84:0b3ab51c8877 | 144 | when the previous conversion (for regular channel) is completed. |
| bogdanm | 84:0b3ab51c8877 | 145 | This avoids risk of overrun for low frequency application. |
| bogdanm | 84:0b3ab51c8877 | 146 | This parameter can be set to ENABLE or DISABLE. |
| bogdanm | 84:0b3ab51c8877 | 147 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 148 | uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz, |
| bogdanm | 84:0b3ab51c8877 | 149 | it is mandatory to first enable the Low Frequency Mode. |
| bogdanm | 84:0b3ab51c8877 | 150 | This parameter can be set to ENABLE or DISABLE. |
| bogdanm | 84:0b3ab51c8877 | 151 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 152 | uint32_t LowPowerAutoOff; /*!< When setting the AutoOff feature, the ADC is always powered off when not converting and automatically |
| bogdanm | 84:0b3ab51c8877 | 153 | wakes-up when a conversion is started (by software or hardware trigger). |
| bogdanm | 84:0b3ab51c8877 | 154 | This parameter can be set to ENABLE or DISABLE. |
| bogdanm | 84:0b3ab51c8877 | 155 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
| bogdanm | 84:0b3ab51c8877 | 156 | }ADC_InitTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 157 | |
| bogdanm | 84:0b3ab51c8877 | 158 | /** |
| bogdanm | 84:0b3ab51c8877 | 159 | * @brief ADC handle Structure definition |
| bogdanm | 84:0b3ab51c8877 | 160 | */ |
| bogdanm | 84:0b3ab51c8877 | 161 | typedef struct __ADC_HandleTypeDef |
| bogdanm | 84:0b3ab51c8877 | 162 | { |
| bogdanm | 84:0b3ab51c8877 | 163 | ADC_TypeDef *Instance; /*!< Register base address */ |
| bogdanm | 84:0b3ab51c8877 | 164 | |
| bogdanm | 84:0b3ab51c8877 | 165 | ADC_InitTypeDef Init; /*!< ADC required parameters */ |
| bogdanm | 84:0b3ab51c8877 | 166 | |
| bogdanm | 84:0b3ab51c8877 | 167 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
| bogdanm | 84:0b3ab51c8877 | 168 | |
| bogdanm | 84:0b3ab51c8877 | 169 | HAL_LockTypeDef Lock; /*!< ADC locking object */ |
| bogdanm | 84:0b3ab51c8877 | 170 | |
| bogdanm | 84:0b3ab51c8877 | 171 | __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ |
| bogdanm | 84:0b3ab51c8877 | 172 | |
| bogdanm | 84:0b3ab51c8877 | 173 | __IO uint32_t ErrorCode; /*!< ADC Error code */ |
| bogdanm | 84:0b3ab51c8877 | 174 | }ADC_HandleTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 175 | |
| bogdanm | 84:0b3ab51c8877 | 176 | /** |
| bogdanm | 84:0b3ab51c8877 | 177 | * @brief ADC Configuration regular Channel structure definition |
| bogdanm | 84:0b3ab51c8877 | 178 | */ |
| bogdanm | 84:0b3ab51c8877 | 179 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 180 | { |
| bogdanm | 84:0b3ab51c8877 | 181 | uint32_t Channel; /*!< the ADC channel to configure |
| bogdanm | 84:0b3ab51c8877 | 182 | This parameter can be a value of @ref ADC_channels */ |
| bogdanm | 84:0b3ab51c8877 | 183 | }ADC_ChannelConfTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 184 | |
| bogdanm | 84:0b3ab51c8877 | 185 | |
| bogdanm | 84:0b3ab51c8877 | 186 | /** |
| bogdanm | 84:0b3ab51c8877 | 187 | * @brief ADC Configuration analog watchdog definition |
| bogdanm | 84:0b3ab51c8877 | 188 | */ |
| bogdanm | 84:0b3ab51c8877 | 189 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 190 | { |
| bogdanm | 84:0b3ab51c8877 | 191 | uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels. |
| bogdanm | 92:4fc01daae5a5 | 192 | This parameter can be a value of @ref ADC_analog_watchdog_mode */ |
| bogdanm | 84:0b3ab51c8877 | 193 | uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. |
| bogdanm | 84:0b3ab51c8877 | 194 | This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) |
| bogdanm | 92:4fc01daae5a5 | 195 | This parameter can be a value of @ref ADC_channels */ |
| bogdanm | 84:0b3ab51c8877 | 196 | uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. |
| bogdanm | 84:0b3ab51c8877 | 197 | This parameter can be set to ENABLE or DISABLE */ |
| bogdanm | 84:0b3ab51c8877 | 198 | uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| bogdanm | 84:0b3ab51c8877 | 199 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), |
| bogdanm | 84:0b3ab51c8877 | 200 | this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
| bogdanm | 84:0b3ab51c8877 | 201 | uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| bogdanm | 84:0b3ab51c8877 | 202 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), |
| bogdanm | 84:0b3ab51c8877 | 203 | this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
| bogdanm | 84:0b3ab51c8877 | 204 | }ADC_AnalogWDGConfTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 205 | |
| bogdanm | 84:0b3ab51c8877 | 206 | |
| bogdanm | 84:0b3ab51c8877 | 207 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 208 | |
| bogdanm | 84:0b3ab51c8877 | 209 | /** @defgroup ADC_Exported_Constants |
| bogdanm | 84:0b3ab51c8877 | 210 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 211 | */ |
| bogdanm | 84:0b3ab51c8877 | 212 | |
| bogdanm | 84:0b3ab51c8877 | 213 | /** @defgroup ADC_Error_Code |
| bogdanm | 84:0b3ab51c8877 | 214 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 215 | */ |
| bogdanm | 84:0b3ab51c8877 | 216 | #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ |
| bogdanm | 84:0b3ab51c8877 | 217 | #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, |
| bogdanm | 84:0b3ab51c8877 | 218 | enable/disable, erroneous state */ |
| bogdanm | 84:0b3ab51c8877 | 219 | #define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */ |
| bogdanm | 84:0b3ab51c8877 | 220 | #define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */ |
| bogdanm | 84:0b3ab51c8877 | 221 | /** |
| bogdanm | 84:0b3ab51c8877 | 222 | * @} |
| bogdanm | 84:0b3ab51c8877 | 223 | */ |
| bogdanm | 84:0b3ab51c8877 | 224 | |
| bogdanm | 84:0b3ab51c8877 | 225 | /** @defgroup ADC_TimeOut_Values |
| bogdanm | 84:0b3ab51c8877 | 226 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 227 | */ |
| bogdanm | 84:0b3ab51c8877 | 228 | |
| bogdanm | 84:0b3ab51c8877 | 229 | /* Fixed timeout values for ADC calibration, enable settling time, disable */ |
| bogdanm | 84:0b3ab51c8877 | 230 | /* settling time. */ |
| bogdanm | 84:0b3ab51c8877 | 231 | /* Values defined to be higher than worst cases: low clocks freq, */ |
| bogdanm | 84:0b3ab51c8877 | 232 | /* maximum prescalers. */ |
| bogdanm | 84:0b3ab51c8877 | 233 | /* Unit: ms */ |
| bogdanm | 84:0b3ab51c8877 | 234 | #define ADC_ENABLE_TIMEOUT 10 |
| bogdanm | 84:0b3ab51c8877 | 235 | #define ADC_DISABLE_TIMEOUT 10 |
| bogdanm | 84:0b3ab51c8877 | 236 | #define ADC_STOP_CONVERSION_TIMEOUT 10 |
| bogdanm | 84:0b3ab51c8877 | 237 | |
| bogdanm | 84:0b3ab51c8877 | 238 | /* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */ |
| bogdanm | 84:0b3ab51c8877 | 239 | /* the minimum number of CPU cycles to fulfill this delay */ |
| bogdanm | 84:0b3ab51c8877 | 240 | #define ADC_DELAY_10US_MIN_CPU_CYCLES 1800 |
| bogdanm | 84:0b3ab51c8877 | 241 | /** |
| bogdanm | 84:0b3ab51c8877 | 242 | * @} |
| bogdanm | 84:0b3ab51c8877 | 243 | */ |
| bogdanm | 84:0b3ab51c8877 | 244 | |
| bogdanm | 84:0b3ab51c8877 | 245 | /** @defgroup ADC_ClockPrescaler |
| bogdanm | 84:0b3ab51c8877 | 246 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 247 | */ |
| bogdanm | 84:0b3ab51c8877 | 248 | #define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode divided by 1 */ |
| bogdanm | 84:0b3ab51c8877 | 249 | #define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 250 | #define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 251 | #define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 252 | #define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC Asynchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 253 | #define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 254 | #define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 255 | #define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 256 | #define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC Asynchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 257 | #define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 258 | #define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 259 | #define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 260 | |
| bogdanm | 84:0b3ab51c8877 | 261 | #define ADC_CLOCKPRESCALER_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 1 */ |
| bogdanm | 84:0b3ab51c8877 | 262 | #define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 2 */ |
| bogdanm | 84:0b3ab51c8877 | 263 | #define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 4 */ |
| bogdanm | 84:0b3ab51c8877 | 264 | |
| bogdanm | 84:0b3ab51c8877 | 265 | #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\ |
| bogdanm | 84:0b3ab51c8877 | 266 | ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV1) ||\ |
| bogdanm | 84:0b3ab51c8877 | 267 | ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) ||\ |
| bogdanm | 84:0b3ab51c8877 | 268 | ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) ||\ |
| bogdanm | 84:0b3ab51c8877 | 269 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\ |
| bogdanm | 84:0b3ab51c8877 | 270 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ |
| bogdanm | 84:0b3ab51c8877 | 271 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ |
| bogdanm | 84:0b3ab51c8877 | 272 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ |
| bogdanm | 84:0b3ab51c8877 | 273 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ |
| bogdanm | 84:0b3ab51c8877 | 274 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ |
| bogdanm | 84:0b3ab51c8877 | 275 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\ |
| bogdanm | 84:0b3ab51c8877 | 276 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ |
| bogdanm | 84:0b3ab51c8877 | 277 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ |
| bogdanm | 84:0b3ab51c8877 | 278 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ |
| bogdanm | 84:0b3ab51c8877 | 279 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ |
| bogdanm | 84:0b3ab51c8877 | 280 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256)) |
| bogdanm | 84:0b3ab51c8877 | 281 | /** |
| bogdanm | 84:0b3ab51c8877 | 282 | * @} |
| bogdanm | 84:0b3ab51c8877 | 283 | */ |
| bogdanm | 84:0b3ab51c8877 | 284 | |
| bogdanm | 84:0b3ab51c8877 | 285 | /** @defgroup ADC_Resolution |
| bogdanm | 84:0b3ab51c8877 | 286 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 287 | */ |
| bogdanm | 84:0b3ab51c8877 | 288 | #define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ |
| bogdanm | 84:0b3ab51c8877 | 289 | #define ADC_RESOLUTION10b ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ |
| bogdanm | 84:0b3ab51c8877 | 290 | #define ADC_RESOLUTION8b ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ |
| bogdanm | 84:0b3ab51c8877 | 291 | #define ADC_RESOLUTION6b ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ |
| bogdanm | 84:0b3ab51c8877 | 292 | |
| bogdanm | 84:0b3ab51c8877 | 293 | #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \ |
| bogdanm | 84:0b3ab51c8877 | 294 | ((RESOLUTION) == ADC_RESOLUTION10b) || \ |
| bogdanm | 84:0b3ab51c8877 | 295 | ((RESOLUTION) == ADC_RESOLUTION8b) || \ |
| bogdanm | 84:0b3ab51c8877 | 296 | ((RESOLUTION) == ADC_RESOLUTION6b)) |
| bogdanm | 84:0b3ab51c8877 | 297 | |
| bogdanm | 84:0b3ab51c8877 | 298 | #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION8b) || \ |
| bogdanm | 84:0b3ab51c8877 | 299 | ((RESOLUTION) == ADC_RESOLUTION6b)) |
| bogdanm | 84:0b3ab51c8877 | 300 | /** |
| bogdanm | 84:0b3ab51c8877 | 301 | * @} |
| bogdanm | 84:0b3ab51c8877 | 302 | */ |
| bogdanm | 84:0b3ab51c8877 | 303 | |
| bogdanm | 84:0b3ab51c8877 | 304 | /** @defgroup ADC_data_align |
| bogdanm | 84:0b3ab51c8877 | 305 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 306 | */ |
| bogdanm | 84:0b3ab51c8877 | 307 | #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 308 | #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) |
| bogdanm | 84:0b3ab51c8877 | 309 | |
| bogdanm | 84:0b3ab51c8877 | 310 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
| bogdanm | 84:0b3ab51c8877 | 311 | ((ALIGN) == ADC_DATAALIGN_LEFT)) |
| bogdanm | 84:0b3ab51c8877 | 312 | /** |
| bogdanm | 84:0b3ab51c8877 | 313 | * @} |
| bogdanm | 84:0b3ab51c8877 | 314 | */ |
| bogdanm | 84:0b3ab51c8877 | 315 | |
| bogdanm | 84:0b3ab51c8877 | 316 | /** @defgroup ADC_External_trigger_Edge |
| bogdanm | 84:0b3ab51c8877 | 317 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 318 | */ |
| bogdanm | 84:0b3ab51c8877 | 319 | #define ADC_EXTERNALTRIG_EDGE_NONE ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 320 | #define ADC_EXTERNALTRIG_EDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) |
| bogdanm | 84:0b3ab51c8877 | 321 | #define ADC_EXTERNALTRIG_EDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) |
| bogdanm | 84:0b3ab51c8877 | 322 | #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) |
| bogdanm | 84:0b3ab51c8877 | 323 | |
| bogdanm | 84:0b3ab51c8877 | 324 | #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIG_EDGE_NONE) || \ |
| bogdanm | 84:0b3ab51c8877 | 325 | ((EDGE) == ADC_EXTERNALTRIG_EDGE_RISING) || \ |
| bogdanm | 84:0b3ab51c8877 | 326 | ((EDGE) == ADC_EXTERNALTRIG_EDGE_FALLING) || \ |
| bogdanm | 84:0b3ab51c8877 | 327 | ((EDGE) == ADC_EXTERNALTRIG_EDGE_RISINGFALLING)) |
| bogdanm | 84:0b3ab51c8877 | 328 | /** |
| bogdanm | 84:0b3ab51c8877 | 329 | * @} |
| bogdanm | 84:0b3ab51c8877 | 330 | */ |
| bogdanm | 84:0b3ab51c8877 | 331 | |
| bogdanm | 84:0b3ab51c8877 | 332 | /** @defgroup ADC_External_trigger_Source |
| bogdanm | 84:0b3ab51c8877 | 333 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 334 | */ |
| bogdanm | 84:0b3ab51c8877 | 335 | #define ADC_EXTERNALTRIG0_T6_TRGO ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 336 | #define ADC_EXTERNALTRIG1_T21_CC2 ADC_CFGR1_EXTSEL_0 |
| bogdanm | 84:0b3ab51c8877 | 337 | #define ADC_EXTERNALTRIG2_T2_TRGO ADC_CFGR1_EXTSEL_1 |
| bogdanm | 84:0b3ab51c8877 | 338 | #define ADC_EXTERNALTRIG3_T2_CC4 ((uint32_t)0x000000C0) |
| bogdanm | 84:0b3ab51c8877 | 339 | #define ADC_EXTERNALTRIG4_T22_TRGO ADC_CFGR1_EXTSEL_2 |
| bogdanm | 84:0b3ab51c8877 | 340 | #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_CFGR1_EXTSEL |
| bogdanm | 84:0b3ab51c8877 | 341 | |
| bogdanm | 84:0b3ab51c8877 | 342 | #define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_EXTERNALTRIG0_T6_TRGO ) || \ |
| bogdanm | 84:0b3ab51c8877 | 343 | ((CONV) == ADC_EXTERNALTRIG1_T21_CC2 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 344 | ((CONV) == ADC_EXTERNALTRIG2_T2_TRGO ) || \ |
| bogdanm | 84:0b3ab51c8877 | 345 | ((CONV) == ADC_EXTERNALTRIG3_T2_CC4 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 346 | ((CONV) == ADC_EXTERNALTRIG4_T22_TRGO ) || \ |
| bogdanm | 84:0b3ab51c8877 | 347 | ((CONV) == ADC_EXTERNALTRIG7_EXT_IT11 )) |
| bogdanm | 84:0b3ab51c8877 | 348 | |
| bogdanm | 84:0b3ab51c8877 | 349 | /** |
| bogdanm | 84:0b3ab51c8877 | 350 | * @} |
| bogdanm | 84:0b3ab51c8877 | 351 | */ |
| bogdanm | 84:0b3ab51c8877 | 352 | |
| bogdanm | 84:0b3ab51c8877 | 353 | /** @defgroup ADC_EOCSelection |
| bogdanm | 84:0b3ab51c8877 | 354 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 355 | */ |
| bogdanm | 84:0b3ab51c8877 | 356 | #define EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) |
| bogdanm | 84:0b3ab51c8877 | 357 | #define EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) |
| bogdanm | 84:0b3ab51c8877 | 358 | #define EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */ |
| bogdanm | 84:0b3ab51c8877 | 359 | |
| bogdanm | 84:0b3ab51c8877 | 360 | #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \ |
| bogdanm | 84:0b3ab51c8877 | 361 | ((EOC_SELECTION) == EOC_SEQ_CONV) || \ |
| bogdanm | 84:0b3ab51c8877 | 362 | ((EOC_SELECTION) == EOC_SINGLE_SEQ_CONV)) |
| bogdanm | 84:0b3ab51c8877 | 363 | /** |
| bogdanm | 84:0b3ab51c8877 | 364 | * @} |
| bogdanm | 84:0b3ab51c8877 | 365 | */ |
| bogdanm | 84:0b3ab51c8877 | 366 | |
| bogdanm | 84:0b3ab51c8877 | 367 | /** @defgroup ADC_Overrun |
| bogdanm | 84:0b3ab51c8877 | 368 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 369 | */ |
| bogdanm | 84:0b3ab51c8877 | 370 | #define OVR_DATA_PRESERVED ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 371 | #define OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD) |
| bogdanm | 84:0b3ab51c8877 | 372 | |
| bogdanm | 84:0b3ab51c8877 | 373 | #define IS_ADC_OVERRUN(OVR) (((OVR) == OVR_DATA_PRESERVED) || \ |
| bogdanm | 84:0b3ab51c8877 | 374 | ((OVR) == OVR_DATA_OVERWRITTEN)) |
| bogdanm | 84:0b3ab51c8877 | 375 | /** |
| bogdanm | 84:0b3ab51c8877 | 376 | * @} |
| bogdanm | 84:0b3ab51c8877 | 377 | */ |
| bogdanm | 84:0b3ab51c8877 | 378 | |
| bogdanm | 84:0b3ab51c8877 | 379 | /** @defgroup ADC_channels |
| bogdanm | 84:0b3ab51c8877 | 380 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 381 | */ |
| bogdanm | 84:0b3ab51c8877 | 382 | #define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0)) |
| bogdanm | 84:0b3ab51c8877 | 383 | #define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) | ADC_CFGR1_AWDCH_0) |
| bogdanm | 84:0b3ab51c8877 | 384 | #define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) | ADC_CFGR1_AWDCH_1) |
| bogdanm | 84:0b3ab51c8877 | 385 | #define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) |
| bogdanm | 84:0b3ab51c8877 | 386 | #define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)| ADC_CFGR1_AWDCH_2) |
| bogdanm | 84:0b3ab51c8877 | 387 | #define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0) |
| bogdanm | 84:0b3ab51c8877 | 388 | #define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1) |
| bogdanm | 84:0b3ab51c8877 | 389 | #define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) |
| bogdanm | 84:0b3ab51c8877 | 390 | #define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3) |
| bogdanm | 84:0b3ab51c8877 | 391 | #define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_0) |
| bogdanm | 84:0b3ab51c8877 | 392 | #define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1) |
| bogdanm | 84:0b3ab51c8877 | 393 | #define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0) |
| bogdanm | 84:0b3ab51c8877 | 394 | #define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2) |
| bogdanm | 84:0b3ab51c8877 | 395 | #define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0) |
| bogdanm | 84:0b3ab51c8877 | 396 | #define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1) |
| bogdanm | 84:0b3ab51c8877 | 397 | #define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0) |
| bogdanm | 84:0b3ab51c8877 | 398 | #define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4) |
| bogdanm | 84:0b3ab51c8877 | 399 | #define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0) |
| bogdanm | 84:0b3ab51c8877 | 400 | #define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1) |
| bogdanm | 84:0b3ab51c8877 | 401 | |
| bogdanm | 84:0b3ab51c8877 | 402 | /* Internal channels */ |
| bogdanm | 92:4fc01daae5a5 | 403 | #define ADC_CHANNEL_VLCD ADC_CHANNEL_16 |
| bogdanm | 84:0b3ab51c8877 | 404 | #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 |
| bogdanm | 92:4fc01daae5a5 | 405 | #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18 |
| bogdanm | 84:0b3ab51c8877 | 406 | |
| bogdanm | 84:0b3ab51c8877 | 407 | |
| bogdanm | 84:0b3ab51c8877 | 408 | #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ |
| bogdanm | 84:0b3ab51c8877 | 409 | ((CHANNEL) == ADC_CHANNEL_1) || \ |
| bogdanm | 84:0b3ab51c8877 | 410 | ((CHANNEL) == ADC_CHANNEL_2) || \ |
| bogdanm | 84:0b3ab51c8877 | 411 | ((CHANNEL) == ADC_CHANNEL_3) || \ |
| bogdanm | 84:0b3ab51c8877 | 412 | ((CHANNEL) == ADC_CHANNEL_4) || \ |
| bogdanm | 84:0b3ab51c8877 | 413 | ((CHANNEL) == ADC_CHANNEL_5) || \ |
| bogdanm | 84:0b3ab51c8877 | 414 | ((CHANNEL) == ADC_CHANNEL_6) || \ |
| bogdanm | 84:0b3ab51c8877 | 415 | ((CHANNEL) == ADC_CHANNEL_7) || \ |
| bogdanm | 84:0b3ab51c8877 | 416 | ((CHANNEL) == ADC_CHANNEL_8) || \ |
| bogdanm | 84:0b3ab51c8877 | 417 | ((CHANNEL) == ADC_CHANNEL_9) || \ |
| bogdanm | 84:0b3ab51c8877 | 418 | ((CHANNEL) == ADC_CHANNEL_10) || \ |
| bogdanm | 84:0b3ab51c8877 | 419 | ((CHANNEL) == ADC_CHANNEL_11) || \ |
| bogdanm | 84:0b3ab51c8877 | 420 | ((CHANNEL) == ADC_CHANNEL_12) || \ |
| bogdanm | 84:0b3ab51c8877 | 421 | ((CHANNEL) == ADC_CHANNEL_13) || \ |
| bogdanm | 84:0b3ab51c8877 | 422 | ((CHANNEL) == ADC_CHANNEL_14) || \ |
| bogdanm | 84:0b3ab51c8877 | 423 | ((CHANNEL) == ADC_CHANNEL_15) || \ |
| bogdanm | 84:0b3ab51c8877 | 424 | ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ |
| bogdanm | 84:0b3ab51c8877 | 425 | ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ |
| bogdanm | 84:0b3ab51c8877 | 426 | ((CHANNEL) == ADC_CHANNEL_VLCD)) |
| bogdanm | 84:0b3ab51c8877 | 427 | |
| bogdanm | 84:0b3ab51c8877 | 428 | /** |
| bogdanm | 84:0b3ab51c8877 | 429 | * @} |
| bogdanm | 84:0b3ab51c8877 | 430 | */ |
| bogdanm | 84:0b3ab51c8877 | 431 | |
| bogdanm | 84:0b3ab51c8877 | 432 | /** @defgroup ADC_Channel_AWD_Masks |
| bogdanm | 84:0b3ab51c8877 | 433 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 434 | */ |
| bogdanm | 84:0b3ab51c8877 | 435 | #define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFF) |
| bogdanm | 84:0b3ab51c8877 | 436 | #define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000) |
| bogdanm | 84:0b3ab51c8877 | 437 | /** |
| bogdanm | 84:0b3ab51c8877 | 438 | * @} |
| bogdanm | 84:0b3ab51c8877 | 439 | */ |
| bogdanm | 84:0b3ab51c8877 | 440 | |
| bogdanm | 84:0b3ab51c8877 | 441 | |
| bogdanm | 84:0b3ab51c8877 | 442 | /** @defgroup ADC_sampling_times |
| bogdanm | 84:0b3ab51c8877 | 443 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 444 | */ |
| bogdanm | 84:0b3ab51c8877 | 445 | |
| bogdanm | 84:0b3ab51c8877 | 446 | #define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< ADC sampling time 1.5 cycle */ |
| bogdanm | 84:0b3ab51c8877 | 447 | #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 7.5 CYCLES */ |
| bogdanm | 84:0b3ab51c8877 | 448 | #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 13.5 CYCLES */ |
| bogdanm | 84:0b3ab51c8877 | 449 | #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 28.5 CYCLES */ |
| bogdanm | 84:0b3ab51c8877 | 450 | #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /*!< ADC sampling time 41.5 CYCLES */ |
| bogdanm | 84:0b3ab51c8877 | 451 | #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 55.5 CYCLES */ |
| bogdanm | 84:0b3ab51c8877 | 452 | #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 71.5 CYCLES */ |
| bogdanm | 84:0b3ab51c8877 | 453 | #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 239.5 CYCLES */ |
| bogdanm | 84:0b3ab51c8877 | 454 | |
| bogdanm | 84:0b3ab51c8877 | 455 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 456 | ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 457 | ((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 458 | ((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 459 | ((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 460 | ((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 461 | ((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 462 | ((TIME) == ADC_SAMPLETIME_239CYCLES_5)) |
| bogdanm | 84:0b3ab51c8877 | 463 | /** |
| bogdanm | 84:0b3ab51c8877 | 464 | * @} |
| bogdanm | 84:0b3ab51c8877 | 465 | */ |
| bogdanm | 84:0b3ab51c8877 | 466 | |
| bogdanm | 84:0b3ab51c8877 | 467 | /** @defgroup ADC_scan_direction |
| bogdanm | 84:0b3ab51c8877 | 468 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 469 | */ |
| bogdanm | 84:0b3ab51c8877 | 470 | #define ADC_SCAN_DIRECTION_UPWARD ((uint32_t)0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 471 | #define ADC_SCAN_DIRECTION_BACKWARD ADC_CFGR1_SCANDIR |
| bogdanm | 84:0b3ab51c8877 | 472 | |
| bogdanm | 84:0b3ab51c8877 | 473 | |
| bogdanm | 84:0b3ab51c8877 | 474 | #define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_SCAN_DIRECTION_UPWARD) || \ |
| bogdanm | 84:0b3ab51c8877 | 475 | ((DIRECTION) == ADC_SCAN_DIRECTION_BACKWARD)) |
| bogdanm | 84:0b3ab51c8877 | 476 | /** |
| bogdanm | 84:0b3ab51c8877 | 477 | * @} |
| bogdanm | 84:0b3ab51c8877 | 478 | */ |
| bogdanm | 84:0b3ab51c8877 | 479 | |
| bogdanm | 84:0b3ab51c8877 | 480 | /** @defgroup ADC_Oversampling_Ratio |
| bogdanm | 84:0b3ab51c8877 | 481 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 482 | */ |
| bogdanm | 84:0b3ab51c8877 | 483 | |
| bogdanm | 84:0b3ab51c8877 | 484 | #define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /*!< ADC Oversampling ratio 2x */ |
| bogdanm | 84:0b3ab51c8877 | 485 | #define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004) /*!< ADC Oversampling ratio 4x */ |
| bogdanm | 84:0b3ab51c8877 | 486 | #define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008) /*!< ADC Oversampling ratio 8x */ |
| bogdanm | 84:0b3ab51c8877 | 487 | #define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000C) /*!< ADC Oversampling ratio 16x */ |
| bogdanm | 84:0b3ab51c8877 | 488 | #define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010) /*!< ADC Oversampling ratio 32x */ |
| bogdanm | 84:0b3ab51c8877 | 489 | #define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014) /*!< ADC Oversampling ratio 64x */ |
| bogdanm | 84:0b3ab51c8877 | 490 | #define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018) /*!< ADC Oversampling ratio 128x */ |
| bogdanm | 84:0b3ab51c8877 | 491 | #define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001C) /*!< ADC Oversampling ratio 256x */ |
| bogdanm | 84:0b3ab51c8877 | 492 | #define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 493 | ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 494 | ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 495 | ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 496 | ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 497 | ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 498 | ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 499 | ((RATIO) == ADC_OVERSAMPLING_RATIO_256 )) |
| bogdanm | 84:0b3ab51c8877 | 500 | /** |
| bogdanm | 84:0b3ab51c8877 | 501 | * @} |
| bogdanm | 84:0b3ab51c8877 | 502 | */ |
| bogdanm | 84:0b3ab51c8877 | 503 | |
| bogdanm | 84:0b3ab51c8877 | 504 | /** @defgroup ADC_Right_Bit_Shift |
| bogdanm | 84:0b3ab51c8877 | 505 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 506 | */ |
| bogdanm | 84:0b3ab51c8877 | 507 | #define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */ |
| bogdanm | 84:0b3ab51c8877 | 508 | #define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020) /*!< ADC 1 bit shift for oversampling */ |
| bogdanm | 84:0b3ab51c8877 | 509 | #define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040) /*!< ADC 2 bits shift for oversampling */ |
| bogdanm | 84:0b3ab51c8877 | 510 | #define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060) /*!< ADC 3 bits shift for oversampling */ |
| bogdanm | 84:0b3ab51c8877 | 511 | #define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080) /*!< ADC 4 bits shift for oversampling */ |
| bogdanm | 84:0b3ab51c8877 | 512 | #define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0) /*!< ADC 5 bits shift for oversampling */ |
| bogdanm | 84:0b3ab51c8877 | 513 | #define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0) /*!< ADC 6 bits shift for oversampling */ |
| bogdanm | 84:0b3ab51c8877 | 514 | #define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0) /*!< ADC 7 bits shift for oversampling */ |
| bogdanm | 84:0b3ab51c8877 | 515 | #define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100) /*!< ADC 8 bits shift for oversampling */ |
| bogdanm | 84:0b3ab51c8877 | 516 | #define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \ |
| bogdanm | 84:0b3ab51c8877 | 517 | ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 518 | ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 519 | ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 520 | ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 521 | ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 522 | ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 523 | ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \ |
| bogdanm | 84:0b3ab51c8877 | 524 | ((SHIFT) == ADC_RIGHTBITSHIFT_8 )) |
| bogdanm | 84:0b3ab51c8877 | 525 | /** |
| bogdanm | 84:0b3ab51c8877 | 526 | * @} |
| bogdanm | 84:0b3ab51c8877 | 527 | */ |
| bogdanm | 84:0b3ab51c8877 | 528 | |
| bogdanm | 84:0b3ab51c8877 | 529 | /** @defgroup ADC_Triggered_Oversampling_Mode |
| bogdanm | 84:0b3ab51c8877 | 530 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 531 | */ |
| bogdanm | 84:0b3ab51c8877 | 532 | #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */ |
| bogdanm | 84:0b3ab51c8877 | 533 | #define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200) /*!< ADC No bit shift for oversampling */ |
| bogdanm | 84:0b3ab51c8877 | 534 | #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ |
| bogdanm | 84:0b3ab51c8877 | 535 | ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) |
| bogdanm | 84:0b3ab51c8877 | 536 | /** |
| bogdanm | 84:0b3ab51c8877 | 537 | * @} |
| bogdanm | 84:0b3ab51c8877 | 538 | */ |
| bogdanm | 84:0b3ab51c8877 | 539 | |
| bogdanm | 84:0b3ab51c8877 | 540 | /** @defgroup ADC_analog_watchdog_mode |
| bogdanm | 84:0b3ab51c8877 | 541 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 542 | */ |
| bogdanm | 84:0b3ab51c8877 | 543 | #define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) |
| bogdanm | 84:0b3ab51c8877 | 544 | #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) |
| bogdanm | 84:0b3ab51c8877 | 545 | #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) |
| bogdanm | 84:0b3ab51c8877 | 546 | |
| bogdanm | 84:0b3ab51c8877 | 547 | |
| bogdanm | 84:0b3ab51c8877 | 548 | #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || \ |
| bogdanm | 84:0b3ab51c8877 | 549 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
| bogdanm | 84:0b3ab51c8877 | 550 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG )) |
| bogdanm | 84:0b3ab51c8877 | 551 | /** |
| bogdanm | 84:0b3ab51c8877 | 552 | * @} |
| bogdanm | 84:0b3ab51c8877 | 553 | */ |
| bogdanm | 84:0b3ab51c8877 | 554 | |
| bogdanm | 84:0b3ab51c8877 | 555 | /** @defgroup ADC_conversion_type |
| bogdanm | 84:0b3ab51c8877 | 556 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 557 | */ |
| bogdanm | 84:0b3ab51c8877 | 558 | #define REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) |
| bogdanm | 84:0b3ab51c8877 | 559 | #define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == REGULAR_GROUP) |
| bogdanm | 84:0b3ab51c8877 | 560 | /** |
| bogdanm | 84:0b3ab51c8877 | 561 | * @} |
| bogdanm | 84:0b3ab51c8877 | 562 | */ |
| bogdanm | 84:0b3ab51c8877 | 563 | |
| bogdanm | 84:0b3ab51c8877 | 564 | /** @defgroup ADC_Event_type |
| bogdanm | 84:0b3ab51c8877 | 565 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 566 | */ |
| bogdanm | 84:0b3ab51c8877 | 567 | #define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) |
| bogdanm | 84:0b3ab51c8877 | 568 | #define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) |
| bogdanm | 84:0b3ab51c8877 | 569 | |
| bogdanm | 84:0b3ab51c8877 | 570 | #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \ |
| bogdanm | 84:0b3ab51c8877 | 571 | ((EVENT) == OVR_EVENT)) |
| bogdanm | 84:0b3ab51c8877 | 572 | /** |
| bogdanm | 84:0b3ab51c8877 | 573 | * @} |
| bogdanm | 84:0b3ab51c8877 | 574 | */ |
| bogdanm | 84:0b3ab51c8877 | 575 | |
| bogdanm | 84:0b3ab51c8877 | 576 | /** @defgroup ADC_interrupts_definition |
| bogdanm | 84:0b3ab51c8877 | 577 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 578 | */ |
| bogdanm | 84:0b3ab51c8877 | 579 | #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready (ADRDY) interrupt source */ |
| bogdanm | 84:0b3ab51c8877 | 580 | #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ |
| bogdanm | 84:0b3ab51c8877 | 581 | #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ |
| bogdanm | 84:0b3ab51c8877 | 582 | #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ |
| bogdanm | 84:0b3ab51c8877 | 583 | #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ |
| bogdanm | 84:0b3ab51c8877 | 584 | #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog 1 interrupt source */ |
| bogdanm | 84:0b3ab51c8877 | 585 | #define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */ |
| bogdanm | 84:0b3ab51c8877 | 586 | |
| bogdanm | 84:0b3ab51c8877 | 587 | /* Check of single flag */ |
| bogdanm | 84:0b3ab51c8877 | 588 | #define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_RDY) || \ |
| bogdanm | 84:0b3ab51c8877 | 589 | ((IT) == ADC_IT_EOSMP) || ((IT) == ADC_IT_EOC) || \ |
| bogdanm | 84:0b3ab51c8877 | 590 | ((IT) == ADC_IT_EOS) || ((IT) == ADC_IT_OVR)) |
| bogdanm | 84:0b3ab51c8877 | 591 | /** |
| bogdanm | 84:0b3ab51c8877 | 592 | * @} |
| bogdanm | 84:0b3ab51c8877 | 593 | */ |
| bogdanm | 84:0b3ab51c8877 | 594 | |
| bogdanm | 84:0b3ab51c8877 | 595 | |
| bogdanm | 84:0b3ab51c8877 | 596 | |
| bogdanm | 84:0b3ab51c8877 | 597 | /** @defgroup ADC_flags_definition |
| bogdanm | 84:0b3ab51c8877 | 598 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 599 | */ |
| bogdanm | 84:0b3ab51c8877 | 600 | #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready (ADRDY) flag */ |
| bogdanm | 84:0b3ab51c8877 | 601 | #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ |
| bogdanm | 84:0b3ab51c8877 | 602 | #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ |
| bogdanm | 84:0b3ab51c8877 | 603 | #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ |
| bogdanm | 84:0b3ab51c8877 | 604 | #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ |
| bogdanm | 84:0b3ab51c8877 | 605 | #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ |
| bogdanm | 84:0b3ab51c8877 | 606 | #define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC Enf Of Calibration flag */ |
| bogdanm | 84:0b3ab51c8877 | 607 | |
| bogdanm | 84:0b3ab51c8877 | 608 | |
| bogdanm | 84:0b3ab51c8877 | 609 | #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ |
| bogdanm | 84:0b3ab51c8877 | 610 | ADC_FLAG_OVR | ADC_FLAG_AWD | ADC_FLAG_EOCAL) |
| bogdanm | 84:0b3ab51c8877 | 611 | |
| bogdanm | 84:0b3ab51c8877 | 612 | /* Check of single flag */ |
| bogdanm | 84:0b3ab51c8877 | 613 | #define IS_ADC_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \ |
| bogdanm | 84:0b3ab51c8877 | 614 | ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \ |
| bogdanm | 84:0b3ab51c8877 | 615 | ((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_AWD) || \ |
| bogdanm | 84:0b3ab51c8877 | 616 | ((FLAG) == ADC_FLAG_EOCAL)) |
| bogdanm | 84:0b3ab51c8877 | 617 | /** |
| bogdanm | 84:0b3ab51c8877 | 618 | * @} |
| bogdanm | 84:0b3ab51c8877 | 619 | */ |
| bogdanm | 84:0b3ab51c8877 | 620 | |
| bogdanm | 84:0b3ab51c8877 | 621 | |
| bogdanm | 84:0b3ab51c8877 | 622 | /** @defgroup ADC_range_verification |
| bogdanm | 84:0b3ab51c8877 | 623 | * in function of ADC resolution selected (12, 10, 8 or 6 bits) |
| bogdanm | 84:0b3ab51c8877 | 624 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 625 | */ |
| bogdanm | 84:0b3ab51c8877 | 626 | #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ |
| bogdanm | 84:0b3ab51c8877 | 627 | ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ |
| bogdanm | 84:0b3ab51c8877 | 628 | (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ |
| bogdanm | 84:0b3ab51c8877 | 629 | (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ |
| bogdanm | 84:0b3ab51c8877 | 630 | (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F)))) |
| bogdanm | 84:0b3ab51c8877 | 631 | /** |
| bogdanm | 84:0b3ab51c8877 | 632 | * @} |
| bogdanm | 84:0b3ab51c8877 | 633 | */ |
| bogdanm | 84:0b3ab51c8877 | 634 | |
| bogdanm | 92:4fc01daae5a5 | 635 | /** @defgroup ADC_regular_nb_conv_verification |
| bogdanm | 84:0b3ab51c8877 | 636 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 637 | */ |
| bogdanm | 84:0b3ab51c8877 | 638 | #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16))) |
| bogdanm | 84:0b3ab51c8877 | 639 | /** |
| bogdanm | 84:0b3ab51c8877 | 640 | * @} |
| bogdanm | 84:0b3ab51c8877 | 641 | */ |
| bogdanm | 84:0b3ab51c8877 | 642 | |
| bogdanm | 84:0b3ab51c8877 | 643 | /** |
| bogdanm | 84:0b3ab51c8877 | 644 | * @} |
| bogdanm | 84:0b3ab51c8877 | 645 | */ |
| bogdanm | 84:0b3ab51c8877 | 646 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 647 | |
| bogdanm | 84:0b3ab51c8877 | 648 | /** @defgroup ADC_Exported_Macro |
| bogdanm | 84:0b3ab51c8877 | 649 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 650 | */ |
| bogdanm | 84:0b3ab51c8877 | 651 | /** @brief Reset ADC handle state |
| bogdanm | 84:0b3ab51c8877 | 652 | * @param __HANDLE__: ADC handle |
| bogdanm | 84:0b3ab51c8877 | 653 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 654 | */ |
| bogdanm | 84:0b3ab51c8877 | 655 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
| bogdanm | 84:0b3ab51c8877 | 656 | |
| bogdanm | 84:0b3ab51c8877 | 657 | /** |
| bogdanm | 84:0b3ab51c8877 | 658 | * @brief Enable the ADC peripheral |
| bogdanm | 84:0b3ab51c8877 | 659 | * @param __HANDLE__: ADC handle |
| bogdanm | 84:0b3ab51c8877 | 660 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 661 | */ |
| bogdanm | 84:0b3ab51c8877 | 662 | #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) |
| bogdanm | 84:0b3ab51c8877 | 663 | |
| bogdanm | 84:0b3ab51c8877 | 664 | /** |
| bogdanm | 84:0b3ab51c8877 | 665 | * @brief Verification of hardware constraints before ADC can be enabled |
| bogdanm | 84:0b3ab51c8877 | 666 | * @param __HANDLE__: ADC handle |
| bogdanm | 84:0b3ab51c8877 | 667 | * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) |
| bogdanm | 84:0b3ab51c8877 | 668 | */ |
| bogdanm | 84:0b3ab51c8877 | 669 | #define __HAL_ADC_ENABLING_CONDITIONS(__HANDLE__) \ |
| bogdanm | 84:0b3ab51c8877 | 670 | (( ( ((__HANDLE__)->Instance->CR) & \ |
| bogdanm | 84:0b3ab51c8877 | 671 | (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | \ |
| bogdanm | 84:0b3ab51c8877 | 672 | ADC_CR_ADDIS | ADC_CR_ADEN ) \ |
| bogdanm | 84:0b3ab51c8877 | 673 | ) == RESET \ |
| bogdanm | 84:0b3ab51c8877 | 674 | ) ? SET : RESET) |
| bogdanm | 84:0b3ab51c8877 | 675 | |
| bogdanm | 84:0b3ab51c8877 | 676 | /** |
| bogdanm | 84:0b3ab51c8877 | 677 | * @brief Disable the ADC peripheral |
| bogdanm | 84:0b3ab51c8877 | 678 | * @param __HANDLE__: ADC handle |
| bogdanm | 84:0b3ab51c8877 | 679 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 680 | */ |
| bogdanm | 84:0b3ab51c8877 | 681 | #define __HAL_ADC_DISABLE(__HANDLE__) \ |
| bogdanm | 84:0b3ab51c8877 | 682 | do{ \ |
| bogdanm | 84:0b3ab51c8877 | 683 | (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ |
| bogdanm | 84:0b3ab51c8877 | 684 | __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ |
| bogdanm | 84:0b3ab51c8877 | 685 | } while(0) |
| bogdanm | 84:0b3ab51c8877 | 686 | |
| bogdanm | 84:0b3ab51c8877 | 687 | /** |
| bogdanm | 84:0b3ab51c8877 | 688 | * @brief Verification of hardware constraints before ADC can be disabled |
| bogdanm | 84:0b3ab51c8877 | 689 | * @param __HANDLE__: ADC handle |
| bogdanm | 84:0b3ab51c8877 | 690 | * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) |
| bogdanm | 84:0b3ab51c8877 | 691 | */ |
| bogdanm | 84:0b3ab51c8877 | 692 | #define __HAL_ADC_DISABLING_CONDITIONS(__HANDLE__) \ |
| bogdanm | 84:0b3ab51c8877 | 693 | (( ( ((__HANDLE__)->Instance->CR) & \ |
| bogdanm | 84:0b3ab51c8877 | 694 | (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ |
| bogdanm | 84:0b3ab51c8877 | 695 | ) ? SET : RESET) |
| bogdanm | 84:0b3ab51c8877 | 696 | |
| bogdanm | 84:0b3ab51c8877 | 697 | /** |
| bogdanm | 84:0b3ab51c8877 | 698 | * @brief Verification of ADC state: enabled or disabled |
| bogdanm | 84:0b3ab51c8877 | 699 | * @param __HANDLE__: ADC handle |
| bogdanm | 84:0b3ab51c8877 | 700 | * @retval SET (ADC enabled) or RESET (ADC disabled) |
| bogdanm | 84:0b3ab51c8877 | 701 | */ |
| bogdanm | 84:0b3ab51c8877 | 702 | #define __HAL_ADC_IS_ENABLED(__HANDLE__) \ |
| bogdanm | 84:0b3ab51c8877 | 703 | (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ |
| bogdanm | 84:0b3ab51c8877 | 704 | ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ |
| bogdanm | 84:0b3ab51c8877 | 705 | ) ? SET : RESET) |
| bogdanm | 84:0b3ab51c8877 | 706 | |
| bogdanm | 84:0b3ab51c8877 | 707 | /** |
| bogdanm | 84:0b3ab51c8877 | 708 | * @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution. |
| bogdanm | 84:0b3ab51c8877 | 709 | * @param __HANDLE__: ADC handle |
| bogdanm | 84:0b3ab51c8877 | 710 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 711 | */ |
| bogdanm | 84:0b3ab51c8877 | 712 | #define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) |
| bogdanm | 84:0b3ab51c8877 | 713 | |
| bogdanm | 84:0b3ab51c8877 | 714 | /** |
| bogdanm | 84:0b3ab51c8877 | 715 | * @brief Check if no conversion is ongoing on regular groups |
| bogdanm | 84:0b3ab51c8877 | 716 | * @param __HANDLE__: ADC handle |
| bogdanm | 84:0b3ab51c8877 | 717 | * @retval SET (conversion is on going) or RESET (no conversion is on going) |
| bogdanm | 84:0b3ab51c8877 | 718 | */ |
| bogdanm | 84:0b3ab51c8877 | 719 | #define __HAL_ADC_IS_CONVERSION_ONGOING(__HANDLE__) \ |
| bogdanm | 84:0b3ab51c8877 | 720 | (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART)) == RESET ) ? RESET : SET) |
| bogdanm | 84:0b3ab51c8877 | 721 | |
| bogdanm | 84:0b3ab51c8877 | 722 | /** |
| bogdanm | 84:0b3ab51c8877 | 723 | * @brief Enable ADC continuous conversion mode. |
| bogdanm | 84:0b3ab51c8877 | 724 | * @param _CONTINUOUS_MODE_: Continuous mode. |
| bogdanm | 84:0b3ab51c8877 | 725 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 726 | */ |
| bogdanm | 84:0b3ab51c8877 | 727 | #define __HAL_ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13) |
| bogdanm | 84:0b3ab51c8877 | 728 | |
| bogdanm | 84:0b3ab51c8877 | 729 | /** |
| bogdanm | 84:0b3ab51c8877 | 730 | * @brief Configures the number of discontinuous conversions for the regular group channels. |
| bogdanm | 84:0b3ab51c8877 | 731 | * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. |
| bogdanm | 84:0b3ab51c8877 | 732 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 733 | */ |
| bogdanm | 84:0b3ab51c8877 | 734 | #define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17) |
| bogdanm | 84:0b3ab51c8877 | 735 | |
| bogdanm | 84:0b3ab51c8877 | 736 | /** |
| bogdanm | 84:0b3ab51c8877 | 737 | * @brief Enable the ADC DMA continuous request. |
| bogdanm | 84:0b3ab51c8877 | 738 | * @param _DMAContReq_MODE_: DMA continuous request mode. |
| bogdanm | 84:0b3ab51c8877 | 739 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 740 | */ |
| bogdanm | 84:0b3ab51c8877 | 741 | #define __HAL_ADC_CFGR1_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1) |
| bogdanm | 84:0b3ab51c8877 | 742 | |
| bogdanm | 84:0b3ab51c8877 | 743 | /** |
| bogdanm | 84:0b3ab51c8877 | 744 | * @brief Enable the ADC Auto Delay. |
| bogdanm | 84:0b3ab51c8877 | 745 | * @param _AutoDelay_: Auto delay bit enable or disable. |
| bogdanm | 84:0b3ab51c8877 | 746 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 747 | */ |
| bogdanm | 84:0b3ab51c8877 | 748 | #define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14) |
| bogdanm | 84:0b3ab51c8877 | 749 | |
| bogdanm | 84:0b3ab51c8877 | 750 | /** |
| bogdanm | 84:0b3ab51c8877 | 751 | * @brief Enable the ADC LowPowerAutoOff. |
| bogdanm | 84:0b3ab51c8877 | 752 | * @param _AUTOFF_: AutoOff bit enable or disable. |
| bogdanm | 84:0b3ab51c8877 | 753 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 754 | */ |
| bogdanm | 84:0b3ab51c8877 | 755 | #define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15) |
| bogdanm | 84:0b3ab51c8877 | 756 | |
| bogdanm | 84:0b3ab51c8877 | 757 | /** |
| bogdanm | 84:0b3ab51c8877 | 758 | * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. |
| bogdanm | 84:0b3ab51c8877 | 759 | * @param _Threshold_: Threshold value |
| bogdanm | 84:0b3ab51c8877 | 760 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 761 | */ |
| bogdanm | 84:0b3ab51c8877 | 762 | #define __HAL_ADC_TRx_HighThreshold(_Threshold_) ((_Threshold_) << 16) |
| bogdanm | 84:0b3ab51c8877 | 763 | |
| bogdanm | 84:0b3ab51c8877 | 764 | /** |
| bogdanm | 84:0b3ab51c8877 | 765 | * @brief Enable the ADC Low Frequency mode. |
| bogdanm | 84:0b3ab51c8877 | 766 | * @param _LOW_FREQUENCY_MODE_: Low Frequency mode. |
| bogdanm | 84:0b3ab51c8877 | 767 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 768 | */ |
| bogdanm | 84:0b3ab51c8877 | 769 | #define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25) |
| bogdanm | 84:0b3ab51c8877 | 770 | |
| bogdanm | 84:0b3ab51c8877 | 771 | /** |
| bogdanm | 84:0b3ab51c8877 | 772 | * @brief Shift the offset in function of the selected ADC resolution. |
| bogdanm | 84:0b3ab51c8877 | 773 | * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 |
| bogdanm | 84:0b3ab51c8877 | 774 | * If resolution 12 bits, no shift. |
| bogdanm | 84:0b3ab51c8877 | 775 | * If resolution 10 bits, shift of 2 ranks on the right. |
| bogdanm | 84:0b3ab51c8877 | 776 | * If resolution 8 bits, shift of 4 ranks on the right. |
| bogdanm | 84:0b3ab51c8877 | 777 | * If resolution 6 bits, shift of 6 ranks on the right. |
| bogdanm | 84:0b3ab51c8877 | 778 | * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) |
| bogdanm | 84:0b3ab51c8877 | 779 | * @param __HANDLE__: ADC handle. |
| bogdanm | 84:0b3ab51c8877 | 780 | * @param _Offset_: Value to be shifted |
| bogdanm | 84:0b3ab51c8877 | 781 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 782 | */ |
| bogdanm | 84:0b3ab51c8877 | 783 | #define __HAL_ADC_Offset_shift_resolution(__HANDLE__, _Offset_) \ |
| bogdanm | 84:0b3ab51c8877 | 784 | ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3)*2)) |
| bogdanm | 84:0b3ab51c8877 | 785 | |
| bogdanm | 84:0b3ab51c8877 | 786 | /** |
| bogdanm | 84:0b3ab51c8877 | 787 | * @brief Shift the AWD1 threshold in function of the selected ADC resolution. |
| bogdanm | 84:0b3ab51c8877 | 788 | * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0 |
| bogdanm | 84:0b3ab51c8877 | 789 | * If resolution 12 bits, no shift. |
| bogdanm | 84:0b3ab51c8877 | 790 | * If resolution 10 bits, shift of 2 ranks on the right. |
| bogdanm | 84:0b3ab51c8877 | 791 | * If resolution 8 bits, shift of 4 ranks on the right. |
| bogdanm | 84:0b3ab51c8877 | 792 | * If resolution 6 bits, shift of 6 ranks on the right. |
| bogdanm | 84:0b3ab51c8877 | 793 | * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) |
| bogdanm | 84:0b3ab51c8877 | 794 | * @param __HANDLE__: ADC handle. |
| bogdanm | 84:0b3ab51c8877 | 795 | * @param _Threshold_: Value to be shifted |
| bogdanm | 84:0b3ab51c8877 | 796 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 797 | */ |
| bogdanm | 84:0b3ab51c8877 | 798 | #define __HAL_ADC_AWD1Threshold_shift_resolution(__HANDLE__, _Threshold_) \ |
| bogdanm | 84:0b3ab51c8877 | 799 | ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2)) |
| bogdanm | 84:0b3ab51c8877 | 800 | |
| bogdanm | 84:0b3ab51c8877 | 801 | /** |
| bogdanm | 84:0b3ab51c8877 | 802 | * @brief Shift the value on the left, less significant are set to 0. |
| bogdanm | 84:0b3ab51c8877 | 803 | * @param _Value_: Value to be shifted |
| bogdanm | 84:0b3ab51c8877 | 804 | * @param _Shift_: Number of shift to be done |
| bogdanm | 84:0b3ab51c8877 | 805 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 806 | */ |
| bogdanm | 84:0b3ab51c8877 | 807 | #define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_)) |
| bogdanm | 84:0b3ab51c8877 | 808 | |
| bogdanm | 84:0b3ab51c8877 | 809 | |
| bogdanm | 84:0b3ab51c8877 | 810 | /** |
| bogdanm | 84:0b3ab51c8877 | 811 | * @brief Enable the ADC end of conversion interrupt. |
| bogdanm | 84:0b3ab51c8877 | 812 | * @param __HANDLE__: ADC handle. |
| bogdanm | 84:0b3ab51c8877 | 813 | * @param __INTERRUPT__: ADC Interrupt. |
| bogdanm | 84:0b3ab51c8877 | 814 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 815 | */ |
| bogdanm | 84:0b3ab51c8877 | 816 | #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) |
| bogdanm | 84:0b3ab51c8877 | 817 | |
| bogdanm | 84:0b3ab51c8877 | 818 | /** |
| bogdanm | 84:0b3ab51c8877 | 819 | * @brief Disable the ADC end of conversion interrupt. |
| bogdanm | 84:0b3ab51c8877 | 820 | * @param __HANDLE__: ADC handle. |
| bogdanm | 84:0b3ab51c8877 | 821 | * @param __INTERRUPT__: ADC interrupt. |
| bogdanm | 84:0b3ab51c8877 | 822 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 823 | */ |
| bogdanm | 84:0b3ab51c8877 | 824 | #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) |
| bogdanm | 84:0b3ab51c8877 | 825 | |
| bogdanm | 84:0b3ab51c8877 | 826 | /** @brief Checks if the specified ADC interrupt source is enabled or disabled. |
| bogdanm | 84:0b3ab51c8877 | 827 | * @param __HANDLE__: specifies the ADC Handle. |
| bogdanm | 84:0b3ab51c8877 | 828 | * @param __INTERRUPT__: specifies the ADC interrupt source to check. |
| bogdanm | 84:0b3ab51c8877 | 829 | * @retval The new state of __IT__ (TRUE or FALSE). |
| bogdanm | 84:0b3ab51c8877 | 830 | */ |
| bogdanm | 84:0b3ab51c8877 | 831 | #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| bogdanm | 84:0b3ab51c8877 | 832 | |
| bogdanm | 84:0b3ab51c8877 | 833 | /** |
| bogdanm | 84:0b3ab51c8877 | 834 | * @brief Clear the ADC's pending flags |
| bogdanm | 84:0b3ab51c8877 | 835 | * @param __HANDLE__: ADC handle. |
| bogdanm | 84:0b3ab51c8877 | 836 | * @param __FLAG__: ADC flag. |
| bogdanm | 84:0b3ab51c8877 | 837 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 838 | */ |
| bogdanm | 84:0b3ab51c8877 | 839 | /* Note: bit cleared bit by writing 1 */ |
| bogdanm | 92:4fc01daae5a5 | 840 | #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__)) |
| bogdanm | 84:0b3ab51c8877 | 841 | |
| bogdanm | 84:0b3ab51c8877 | 842 | /** |
| bogdanm | 84:0b3ab51c8877 | 843 | * @brief Get the selected ADC's flag status. |
| bogdanm | 84:0b3ab51c8877 | 844 | * @param __HANDLE__: ADC handle. |
| bogdanm | 84:0b3ab51c8877 | 845 | * @param __FLAG__: ADC flag. |
| bogdanm | 84:0b3ab51c8877 | 846 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 847 | */ |
| bogdanm | 84:0b3ab51c8877 | 848 | #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) |
| bogdanm | 84:0b3ab51c8877 | 849 | |
| bogdanm | 84:0b3ab51c8877 | 850 | |
| bogdanm | 84:0b3ab51c8877 | 851 | |
| bogdanm | 84:0b3ab51c8877 | 852 | /** |
| bogdanm | 84:0b3ab51c8877 | 853 | * @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler |
| bogdanm | 84:0b3ab51c8877 | 854 | * @param __HANDLE__: ADC handle |
| bogdanm | 84:0b3ab51c8877 | 855 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 856 | */ |
| bogdanm | 84:0b3ab51c8877 | 857 | |
| bogdanm | 84:0b3ab51c8877 | 858 | #define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \ |
| bogdanm | 84:0b3ab51c8877 | 859 | do{ \ |
| bogdanm | 84:0b3ab51c8877 | 860 | if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCKPRESCALER_PCLK_DIV1) || \ |
| bogdanm | 84:0b3ab51c8877 | 861 | (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \ |
| bogdanm | 84:0b3ab51c8877 | 862 | (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCKPRESCALER_PCLK_DIV2)) \ |
| bogdanm | 84:0b3ab51c8877 | 863 | { \ |
| bogdanm | 84:0b3ab51c8877 | 864 | (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \ |
| bogdanm | 84:0b3ab51c8877 | 865 | (__HANDLE__)->Instance->CFGR2 |= (__HANDLE__)->Init.ClockPrescaler; \ |
| bogdanm | 84:0b3ab51c8877 | 866 | } \ |
| bogdanm | 84:0b3ab51c8877 | 867 | else \ |
| bogdanm | 84:0b3ab51c8877 | 868 | { \ |
| bogdanm | 84:0b3ab51c8877 | 869 | /* CKMOD bits must be reset */ \ |
| bogdanm | 84:0b3ab51c8877 | 870 | (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \ |
| bogdanm | 84:0b3ab51c8877 | 871 | ADC->CCR &= ~(ADC_CCR_PRESC); \ |
| bogdanm | 84:0b3ab51c8877 | 872 | ADC->CCR |= (__HANDLE__)->Init.ClockPrescaler; \ |
| bogdanm | 84:0b3ab51c8877 | 873 | } \ |
| bogdanm | 84:0b3ab51c8877 | 874 | } while(0) |
| bogdanm | 84:0b3ab51c8877 | 875 | |
| bogdanm | 84:0b3ab51c8877 | 876 | /** |
| bogdanm | 84:0b3ab51c8877 | 877 | * @} |
| bogdanm | 84:0b3ab51c8877 | 878 | */ |
| bogdanm | 84:0b3ab51c8877 | 879 | |
| bogdanm | 84:0b3ab51c8877 | 880 | /* Include ADC HAL Extension module */ |
| bogdanm | 84:0b3ab51c8877 | 881 | #include "stm32l0xx_hal_adc_ex.h" |
| bogdanm | 84:0b3ab51c8877 | 882 | |
| bogdanm | 84:0b3ab51c8877 | 883 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 884 | /* Initialization and de-initialization functions **********************************/ |
| bogdanm | 84:0b3ab51c8877 | 885 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 886 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
| bogdanm | 84:0b3ab51c8877 | 887 | void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 888 | void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 889 | |
| bogdanm | 84:0b3ab51c8877 | 890 | /* IO operation functions *****************************************************/ |
| bogdanm | 84:0b3ab51c8877 | 891 | /* Blocking mode: Polling */ |
| bogdanm | 84:0b3ab51c8877 | 892 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 893 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 894 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 895 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 896 | |
| bogdanm | 84:0b3ab51c8877 | 897 | /* Non-blocking mode: Interruption */ |
| bogdanm | 84:0b3ab51c8877 | 898 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 899 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 900 | |
| bogdanm | 84:0b3ab51c8877 | 901 | /* Non-blocking mode: DMA */ |
| bogdanm | 84:0b3ab51c8877 | 902 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
| bogdanm | 84:0b3ab51c8877 | 903 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 904 | |
| bogdanm | 84:0b3ab51c8877 | 905 | /* ADC retrieve conversion value intended to be used with polling or interruption */ |
| bogdanm | 84:0b3ab51c8877 | 906 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 907 | |
| bogdanm | 84:0b3ab51c8877 | 908 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ |
| bogdanm | 84:0b3ab51c8877 | 909 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 910 | void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 911 | void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 912 | void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 913 | void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
| bogdanm | 84:0b3ab51c8877 | 914 | |
| bogdanm | 84:0b3ab51c8877 | 915 | /* Peripheral Control functions ***********************************************/ |
| bogdanm | 84:0b3ab51c8877 | 916 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
| bogdanm | 84:0b3ab51c8877 | 917 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
| bogdanm | 84:0b3ab51c8877 | 918 | |
| bogdanm | 84:0b3ab51c8877 | 919 | /* Peripheral State functions *************************************************/ |
| bogdanm | 84:0b3ab51c8877 | 920 | HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
| bogdanm | 84:0b3ab51c8877 | 921 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
| bogdanm | 84:0b3ab51c8877 | 922 | |
| bogdanm | 84:0b3ab51c8877 | 923 | |
| bogdanm | 84:0b3ab51c8877 | 924 | /** |
| bogdanm | 84:0b3ab51c8877 | 925 | * @} |
| bogdanm | 84:0b3ab51c8877 | 926 | */ |
| bogdanm | 84:0b3ab51c8877 | 927 | |
| bogdanm | 84:0b3ab51c8877 | 928 | /** |
| bogdanm | 84:0b3ab51c8877 | 929 | * @} |
| bogdanm | 84:0b3ab51c8877 | 930 | */ |
| bogdanm | 84:0b3ab51c8877 | 931 | |
| bogdanm | 84:0b3ab51c8877 | 932 | #ifdef __cplusplus |
| bogdanm | 84:0b3ab51c8877 | 933 | } |
| bogdanm | 84:0b3ab51c8877 | 934 | #endif |
| bogdanm | 84:0b3ab51c8877 | 935 | |
| bogdanm | 84:0b3ab51c8877 | 936 | #endif /*__STM32L0xx_ADC_H */ |
| bogdanm | 84:0b3ab51c8877 | 937 | |
| bogdanm | 84:0b3ab51c8877 | 938 | |
| bogdanm | 84:0b3ab51c8877 | 939 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |