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TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
90:cb3d968589d8
Child:
99:dbbf35b96557
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_i2s.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 90:cb3d968589d8 5 * @version V1.1.0
Kojto 90:cb3d968589d8 6 * @date 19-June-2014
emilmont 77:869cf507173a 7 * @brief Header file of I2S HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
emilmont 77:869cf507173a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_I2S_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_I2S_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
emilmont 77:869cf507173a 52
emilmont 77:869cf507173a 53 /** @addtogroup I2S
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
emilmont 77:869cf507173a 57 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 58 /**
emilmont 77:869cf507173a 59 * @brief I2S Init structure definition
emilmont 77:869cf507173a 60 */
emilmont 77:869cf507173a 61 typedef struct
emilmont 77:869cf507173a 62 {
emilmont 77:869cf507173a 63 uint32_t Mode; /*!< Specifies the I2S operating mode.
emilmont 77:869cf507173a 64 This parameter can be a value of @ref I2S_Mode */
emilmont 77:869cf507173a 65
emilmont 77:869cf507173a 66 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
emilmont 77:869cf507173a 67 This parameter can be a value of @ref I2S_Standard */
emilmont 77:869cf507173a 68
emilmont 77:869cf507173a 69 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
emilmont 77:869cf507173a 70 This parameter can be a value of @ref I2S_Data_Format */
emilmont 77:869cf507173a 71
emilmont 77:869cf507173a 72 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
emilmont 77:869cf507173a 73 This parameter can be a value of @ref I2S_MCLK_Output */
emilmont 77:869cf507173a 74
emilmont 77:869cf507173a 75 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
emilmont 77:869cf507173a 76 This parameter can be a value of @ref I2S_Audio_Frequency */
emilmont 77:869cf507173a 77
emilmont 77:869cf507173a 78 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
emilmont 77:869cf507173a 79 This parameter can be a value of @ref I2S_Clock_Polarity */
emilmont 77:869cf507173a 80
emilmont 77:869cf507173a 81 uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
emilmont 77:869cf507173a 82 This parameter can be a value of @ref I2S_Clock_Source */
emilmont 77:869cf507173a 83
emilmont 77:869cf507173a 84 uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
emilmont 77:869cf507173a 85 This parameter can be a value of @ref I2S_FullDuplex_Mode */
emilmont 77:869cf507173a 86
emilmont 77:869cf507173a 87 }I2S_InitTypeDef;
emilmont 77:869cf507173a 88
emilmont 77:869cf507173a 89 /**
emilmont 77:869cf507173a 90 * @brief HAL State structures definition
emilmont 77:869cf507173a 91 */
emilmont 77:869cf507173a 92 typedef enum
emilmont 77:869cf507173a 93 {
emilmont 77:869cf507173a 94 HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
emilmont 77:869cf507173a 95 HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
emilmont 77:869cf507173a 96 HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
emilmont 77:869cf507173a 97 HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
emilmont 77:869cf507173a 98 HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
emilmont 77:869cf507173a 99 HAL_I2S_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
emilmont 77:869cf507173a 100 HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */
emilmont 77:869cf507173a 101 HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
emilmont 77:869cf507173a 102
emilmont 77:869cf507173a 103 }HAL_I2S_StateTypeDef;
emilmont 77:869cf507173a 104
emilmont 77:869cf507173a 105 /**
emilmont 77:869cf507173a 106 * @brief HAL I2S Error Code structure definition
emilmont 77:869cf507173a 107 */
emilmont 77:869cf507173a 108 typedef enum
emilmont 77:869cf507173a 109 {
emilmont 77:869cf507173a 110 HAL_I2S_ERROR_NONE = 0x00, /*!< No error */
emilmont 77:869cf507173a 111 HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */
emilmont 77:869cf507173a 112 HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */
emilmont 77:869cf507173a 113 HAL_I2SEX_ERROR_UDR = 0x04, /*!< I2S extended Underrun error */
emilmont 77:869cf507173a 114 HAL_I2SEX_ERROR_OVR = 0x08, /*!< I2S extended Overrun error */
emilmont 77:869cf507173a 115 HAL_I2S_ERROR_FRE = 0x10, /*!< I2S Frame format error */
emilmont 77:869cf507173a 116 HAL_I2S_ERROR_DMA = 0x20 /*!< DMA transfer error */
emilmont 77:869cf507173a 117 }HAL_I2S_ErrorTypeDef;
emilmont 77:869cf507173a 118
emilmont 77:869cf507173a 119 /**
emilmont 77:869cf507173a 120 * @brief I2S handle Structure definition
emilmont 77:869cf507173a 121 */
emilmont 77:869cf507173a 122 typedef struct
emilmont 77:869cf507173a 123 {
emilmont 77:869cf507173a 124 SPI_TypeDef *Instance; /* I2S registers base address */
emilmont 77:869cf507173a 125
emilmont 77:869cf507173a 126 I2S_InitTypeDef Init; /* I2S communication parameters */
emilmont 77:869cf507173a 127
emilmont 77:869cf507173a 128 uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
emilmont 77:869cf507173a 129
emilmont 77:869cf507173a 130 __IO uint16_t TxXferSize; /* I2S Tx transfer size */
emilmont 77:869cf507173a 131
emilmont 77:869cf507173a 132 __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
emilmont 77:869cf507173a 133
emilmont 77:869cf507173a 134 uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
emilmont 77:869cf507173a 135
emilmont 77:869cf507173a 136 __IO uint16_t RxXferSize; /* I2S Rx transfer size */
emilmont 77:869cf507173a 137
emilmont 77:869cf507173a 138 __IO uint16_t RxXferCount; /* I2S Rx transfer counter */
emilmont 77:869cf507173a 139
emilmont 77:869cf507173a 140 DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
emilmont 77:869cf507173a 141
emilmont 77:869cf507173a 142 DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
emilmont 77:869cf507173a 143
emilmont 77:869cf507173a 144 __IO HAL_LockTypeDef Lock; /* I2S locking object */
emilmont 77:869cf507173a 145
emilmont 77:869cf507173a 146 __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
emilmont 77:869cf507173a 147
emilmont 77:869cf507173a 148 __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */
emilmont 77:869cf507173a 149
emilmont 77:869cf507173a 150 }I2S_HandleTypeDef;
emilmont 77:869cf507173a 151
emilmont 77:869cf507173a 152 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 153
emilmont 77:869cf507173a 154 /** @defgroup I2S_Exported_Constants
emilmont 77:869cf507173a 155 * @{
emilmont 77:869cf507173a 156 */
emilmont 77:869cf507173a 157 #define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
emilmont 77:869cf507173a 158
emilmont 77:869cf507173a 159 /** @defgroup I2S_Clock_Source
emilmont 77:869cf507173a 160 * @{
emilmont 77:869cf507173a 161 */
emilmont 77:869cf507173a 162 #define I2S_CLOCK_PLL ((uint32_t)0x00000000)
emilmont 77:869cf507173a 163 #define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
emilmont 77:869cf507173a 164
emilmont 77:869cf507173a 165 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
emilmont 77:869cf507173a 166 ((CLOCK) == I2S_CLOCK_PLL))
emilmont 77:869cf507173a 167 /**
emilmont 77:869cf507173a 168 * @}
emilmont 77:869cf507173a 169 */
emilmont 77:869cf507173a 170
emilmont 77:869cf507173a 171 /** @defgroup I2S_Mode
emilmont 77:869cf507173a 172 * @{
emilmont 77:869cf507173a 173 */
emilmont 77:869cf507173a 174 #define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
emilmont 77:869cf507173a 175 #define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
emilmont 77:869cf507173a 176 #define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
emilmont 77:869cf507173a 177 #define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
emilmont 77:869cf507173a 178
emilmont 77:869cf507173a 179 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
emilmont 77:869cf507173a 180 ((MODE) == I2S_MODE_SLAVE_RX) || \
emilmont 77:869cf507173a 181 ((MODE) == I2S_MODE_MASTER_TX) || \
emilmont 77:869cf507173a 182 ((MODE) == I2S_MODE_MASTER_RX))
emilmont 77:869cf507173a 183 /**
emilmont 77:869cf507173a 184 * @}
emilmont 77:869cf507173a 185 */
emilmont 77:869cf507173a 186
emilmont 77:869cf507173a 187 /** @defgroup I2S_Standard
emilmont 77:869cf507173a 188 * @{
emilmont 77:869cf507173a 189 */
bogdanm 85:024bf7f99721 190 #define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
emilmont 77:869cf507173a 191 #define I2S_STANDARD_MSB ((uint32_t)0x00000010)
emilmont 77:869cf507173a 192 #define I2S_STANDARD_LSB ((uint32_t)0x00000020)
emilmont 77:869cf507173a 193 #define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
emilmont 77:869cf507173a 194 #define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
emilmont 77:869cf507173a 195
bogdanm 85:024bf7f99721 196 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
emilmont 77:869cf507173a 197 ((STANDARD) == I2S_STANDARD_MSB) || \
emilmont 77:869cf507173a 198 ((STANDARD) == I2S_STANDARD_LSB) || \
emilmont 77:869cf507173a 199 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
emilmont 77:869cf507173a 200 ((STANDARD) == I2S_STANDARD_PCM_LONG))
bogdanm 85:024bf7f99721 201 /** @defgroup I2S_Legacy
bogdanm 85:024bf7f99721 202 * @{
bogdanm 85:024bf7f99721 203 */
bogdanm 85:024bf7f99721 204 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
bogdanm 85:024bf7f99721 205 /**
bogdanm 85:024bf7f99721 206 * @}
bogdanm 85:024bf7f99721 207 */
bogdanm 85:024bf7f99721 208
emilmont 77:869cf507173a 209 /**
emilmont 77:869cf507173a 210 * @}
emilmont 77:869cf507173a 211 */
emilmont 77:869cf507173a 212
emilmont 77:869cf507173a 213 /** @defgroup I2S_Data_Format
emilmont 77:869cf507173a 214 * @{
emilmont 77:869cf507173a 215 */
emilmont 77:869cf507173a 216 #define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
emilmont 77:869cf507173a 217 #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
emilmont 77:869cf507173a 218 #define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
emilmont 77:869cf507173a 219 #define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
emilmont 77:869cf507173a 220
emilmont 77:869cf507173a 221 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
emilmont 77:869cf507173a 222 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
emilmont 77:869cf507173a 223 ((FORMAT) == I2S_DATAFORMAT_24B) || \
emilmont 77:869cf507173a 224 ((FORMAT) == I2S_DATAFORMAT_32B))
emilmont 77:869cf507173a 225 /**
emilmont 77:869cf507173a 226 * @}
emilmont 77:869cf507173a 227 */
emilmont 77:869cf507173a 228
emilmont 77:869cf507173a 229 /** @defgroup I2S_MCLK_Output
emilmont 77:869cf507173a 230 * @{
emilmont 77:869cf507173a 231 */
emilmont 77:869cf507173a 232 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
emilmont 77:869cf507173a 233 #define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
emilmont 77:869cf507173a 234
emilmont 77:869cf507173a 235 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
emilmont 77:869cf507173a 236 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
emilmont 77:869cf507173a 237 /**
emilmont 77:869cf507173a 238 * @}
emilmont 77:869cf507173a 239 */
emilmont 77:869cf507173a 240
emilmont 77:869cf507173a 241 /** @defgroup I2S_Audio_Frequency
emilmont 77:869cf507173a 242 * @{
emilmont 77:869cf507173a 243 */
emilmont 77:869cf507173a 244 #define I2S_AUDIOFREQ_192K ((uint32_t)192000)
emilmont 77:869cf507173a 245 #define I2S_AUDIOFREQ_96K ((uint32_t)96000)
emilmont 77:869cf507173a 246 #define I2S_AUDIOFREQ_48K ((uint32_t)48000)
emilmont 77:869cf507173a 247 #define I2S_AUDIOFREQ_44K ((uint32_t)44100)
emilmont 77:869cf507173a 248 #define I2S_AUDIOFREQ_32K ((uint32_t)32000)
emilmont 77:869cf507173a 249 #define I2S_AUDIOFREQ_22K ((uint32_t)22050)
emilmont 77:869cf507173a 250 #define I2S_AUDIOFREQ_16K ((uint32_t)16000)
emilmont 77:869cf507173a 251 #define I2S_AUDIOFREQ_11K ((uint32_t)11025)
emilmont 77:869cf507173a 252 #define I2S_AUDIOFREQ_8K ((uint32_t)8000)
emilmont 77:869cf507173a 253 #define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
emilmont 77:869cf507173a 254
emilmont 77:869cf507173a 255 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
emilmont 77:869cf507173a 256 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
emilmont 77:869cf507173a 257 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
emilmont 77:869cf507173a 258 /**
emilmont 77:869cf507173a 259 * @}
emilmont 77:869cf507173a 260 */
emilmont 77:869cf507173a 261
emilmont 77:869cf507173a 262 /** @defgroup I2S_FullDuplex_Mode
emilmont 77:869cf507173a 263 * @{
emilmont 77:869cf507173a 264 */
emilmont 77:869cf507173a 265 #define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000)
emilmont 77:869cf507173a 266 #define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001)
emilmont 77:869cf507173a 267
emilmont 77:869cf507173a 268 #define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
emilmont 77:869cf507173a 269 ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
emilmont 77:869cf507173a 270 /**
emilmont 77:869cf507173a 271 * @}
emilmont 77:869cf507173a 272 */
emilmont 77:869cf507173a 273
emilmont 77:869cf507173a 274 /** @defgroup I2S_Clock_Polarity
emilmont 77:869cf507173a 275 * @{
emilmont 77:869cf507173a 276 */
emilmont 77:869cf507173a 277 #define I2S_CPOL_LOW ((uint32_t)0x00000000)
emilmont 77:869cf507173a 278 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
emilmont 77:869cf507173a 279
emilmont 77:869cf507173a 280 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
emilmont 77:869cf507173a 281 ((CPOL) == I2S_CPOL_HIGH))
emilmont 77:869cf507173a 282 /**
emilmont 77:869cf507173a 283 * @}
emilmont 77:869cf507173a 284 */
emilmont 77:869cf507173a 285
emilmont 77:869cf507173a 286 /** @defgroup I2S_Interrupt_configuration_definition
emilmont 77:869cf507173a 287 * @{
emilmont 77:869cf507173a 288 */
emilmont 77:869cf507173a 289 #define I2S_IT_TXE SPI_CR2_TXEIE
emilmont 77:869cf507173a 290 #define I2S_IT_RXNE SPI_CR2_RXNEIE
emilmont 77:869cf507173a 291 #define I2S_IT_ERR SPI_CR2_ERRIE
emilmont 77:869cf507173a 292 /**
emilmont 77:869cf507173a 293 * @}
emilmont 77:869cf507173a 294 */
emilmont 77:869cf507173a 295
emilmont 77:869cf507173a 296 /** @defgroup I2S_Flag_definition
emilmont 77:869cf507173a 297 * @{
emilmont 77:869cf507173a 298 */
emilmont 77:869cf507173a 299 #define I2S_FLAG_TXE SPI_SR_TXE
emilmont 77:869cf507173a 300 #define I2S_FLAG_RXNE SPI_SR_RXNE
emilmont 77:869cf507173a 301
emilmont 77:869cf507173a 302 #define I2S_FLAG_UDR SPI_SR_UDR
emilmont 77:869cf507173a 303 #define I2S_FLAG_OVR SPI_SR_OVR
emilmont 77:869cf507173a 304 #define I2S_FLAG_FRE SPI_SR_FRE
emilmont 77:869cf507173a 305
emilmont 77:869cf507173a 306 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
emilmont 77:869cf507173a 307 #define I2S_FLAG_BSY SPI_SR_BSY
emilmont 77:869cf507173a 308 /**
emilmont 77:869cf507173a 309 * @}
emilmont 77:869cf507173a 310 */
emilmont 77:869cf507173a 311
emilmont 77:869cf507173a 312 /**
emilmont 77:869cf507173a 313 * @}
emilmont 77:869cf507173a 314 */
emilmont 77:869cf507173a 315
emilmont 77:869cf507173a 316 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 317
bogdanm 85:024bf7f99721 318
bogdanm 85:024bf7f99721 319 /** @brief Reset I2S handle state
bogdanm 85:024bf7f99721 320 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 85:024bf7f99721 321 * @retval None
bogdanm 85:024bf7f99721 322 */
bogdanm 85:024bf7f99721 323 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
bogdanm 85:024bf7f99721 324
emilmont 77:869cf507173a 325 /** @brief Enable or disable the specified SPI peripheral (in I2S mode).
emilmont 77:869cf507173a 326 * @param __HANDLE__: specifies the I2S Handle.
emilmont 77:869cf507173a 327 * @retval None
emilmont 77:869cf507173a 328 */
emilmont 77:869cf507173a 329 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
emilmont 77:869cf507173a 330 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
emilmont 77:869cf507173a 331
emilmont 77:869cf507173a 332 /** @brief Enable or disable the specified I2S interrupts.
emilmont 77:869cf507173a 333 * @param __HANDLE__: specifies the I2S Handle.
emilmont 77:869cf507173a 334 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
emilmont 77:869cf507173a 335 * This parameter can be one of the following values:
emilmont 77:869cf507173a 336 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
emilmont 77:869cf507173a 337 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
emilmont 77:869cf507173a 338 * @arg I2S_IT_ERR: Error interrupt enable
emilmont 77:869cf507173a 339 * @retval None
emilmont 77:869cf507173a 340 */
emilmont 77:869cf507173a 341 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
emilmont 77:869cf507173a 342 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
emilmont 77:869cf507173a 343
emilmont 77:869cf507173a 344 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
emilmont 77:869cf507173a 345 * @param __HANDLE__: specifies the I2S Handle.
emilmont 77:869cf507173a 346 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
emilmont 77:869cf507173a 347 * @param __INTERRUPT__: specifies the I2S interrupt source to check.
emilmont 77:869cf507173a 348 * This parameter can be one of the following values:
emilmont 77:869cf507173a 349 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
emilmont 77:869cf507173a 350 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
emilmont 77:869cf507173a 351 * @arg I2S_IT_ERR: Error interrupt enable
emilmont 77:869cf507173a 352 * @retval The new state of __IT__ (TRUE or FALSE).
emilmont 77:869cf507173a 353 */
emilmont 77:869cf507173a 354 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
emilmont 77:869cf507173a 355
emilmont 77:869cf507173a 356 /** @brief Checks whether the specified I2S flag is set or not.
emilmont 77:869cf507173a 357 * @param __HANDLE__: specifies the I2S Handle.
emilmont 77:869cf507173a 358 * @param __FLAG__: specifies the flag to check.
emilmont 77:869cf507173a 359 * This parameter can be one of the following values:
emilmont 77:869cf507173a 360 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
emilmont 77:869cf507173a 361 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
emilmont 77:869cf507173a 362 * @arg I2S_FLAG_UDR: Underrun flag
emilmont 77:869cf507173a 363 * @arg I2S_FLAG_OVR: Overrun flag
emilmont 77:869cf507173a 364 * @arg I2S_FLAG_FRE: Frame error flag
emilmont 77:869cf507173a 365 * @arg I2S_FLAG_CHSIDE: Channel Side flag
emilmont 77:869cf507173a 366 * @arg I2S_FLAG_BSY: Busy flag
emilmont 77:869cf507173a 367 * @retval The new state of __FLAG__ (TRUE or FALSE).
emilmont 77:869cf507173a 368 */
emilmont 77:869cf507173a 369 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
emilmont 77:869cf507173a 370
emilmont 77:869cf507173a 371 /** @brief Clears the I2S OVR pending flag.
emilmont 77:869cf507173a 372 * @param __HANDLE__: specifies the I2S Handle.
emilmont 77:869cf507173a 373 * @retval None
emilmont 77:869cf507173a 374 */
emilmont 77:869cf507173a 375 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
emilmont 77:869cf507173a 376 (__HANDLE__)->Instance->SR;}while(0)
emilmont 77:869cf507173a 377 /** @brief Clears the I2S UDR pending flag.
emilmont 77:869cf507173a 378 * @param __HANDLE__: specifies the I2S Handle.
emilmont 77:869cf507173a 379 * @retval None
emilmont 77:869cf507173a 380 */
emilmont 77:869cf507173a 381 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
emilmont 77:869cf507173a 382
emilmont 77:869cf507173a 383 /* Include I2S Extension module */
emilmont 77:869cf507173a 384 #include "stm32f4xx_hal_i2s_ex.h"
emilmont 77:869cf507173a 385
emilmont 77:869cf507173a 386 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 387
emilmont 77:869cf507173a 388 /* Initialization/de-initialization functions **********************************/
emilmont 77:869cf507173a 389 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
emilmont 77:869cf507173a 390 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
emilmont 77:869cf507173a 391 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
emilmont 77:869cf507173a 392 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
emilmont 77:869cf507173a 393
emilmont 77:869cf507173a 394 /* I/O operation functions *****************************************************/
emilmont 77:869cf507173a 395 /* Blocking mode: Polling */
emilmont 77:869cf507173a 396 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
emilmont 77:869cf507173a 397 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
emilmont 77:869cf507173a 398
emilmont 77:869cf507173a 399 /* Non-Blocking mode: Interrupt */
emilmont 77:869cf507173a 400 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
emilmont 77:869cf507173a 401 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
emilmont 77:869cf507173a 402 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
emilmont 77:869cf507173a 403
emilmont 77:869cf507173a 404 /* Non-Blocking mode: DMA */
emilmont 77:869cf507173a 405 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
emilmont 77:869cf507173a 406 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
emilmont 77:869cf507173a 407
emilmont 77:869cf507173a 408 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
emilmont 77:869cf507173a 409 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
emilmont 77:869cf507173a 410 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
emilmont 77:869cf507173a 411
emilmont 77:869cf507173a 412 /* Peripheral Control and State functions **************************************/
emilmont 77:869cf507173a 413 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
emilmont 77:869cf507173a 414 HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
emilmont 77:869cf507173a 415
emilmont 77:869cf507173a 416 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
bogdanm 81:7d30d6019079 417 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 81:7d30d6019079 418 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 81:7d30d6019079 419 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 81:7d30d6019079 420 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 81:7d30d6019079 421 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
emilmont 77:869cf507173a 422
emilmont 77:869cf507173a 423 void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 424 void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 425 void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 426 void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 427 void I2S_DMAError(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 428 HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
emilmont 77:869cf507173a 429
emilmont 77:869cf507173a 430 /**
emilmont 77:869cf507173a 431 * @}
emilmont 77:869cf507173a 432 */
emilmont 77:869cf507173a 433
emilmont 77:869cf507173a 434 /**
emilmont 77:869cf507173a 435 * @}
emilmont 77:869cf507173a 436 */
emilmont 77:869cf507173a 437
emilmont 77:869cf507173a 438 #ifdef __cplusplus
emilmont 77:869cf507173a 439 }
emilmont 77:869cf507173a 440 #endif
emilmont 77:869cf507173a 441
emilmont 77:869cf507173a 442
emilmont 77:869cf507173a 443 #endif /* __STM32F4xx_HAL_I2S_H */
emilmont 77:869cf507173a 444
emilmont 77:869cf507173a 445 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/