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TARGET_NUCLEO_F334R8/stm32f3xx_hal_tim_ex.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
92:4fc01daae5a5 
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f3xx_hal_tim_ex.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 12-Sept-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of TIM HAL Extended module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
bogdanm 86:04dd9b1680ae 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F3xx_HAL_TIM_EX_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F3xx_HAL_TIM_EX_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f3xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
bogdanm 86:04dd9b1680ae 49 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 86:04dd9b1680ae 50 * @{
bogdanm 86:04dd9b1680ae 51 */
bogdanm 86:04dd9b1680ae 52
bogdanm 86:04dd9b1680ae 53 /** @addtogroup TIMEx
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
bogdanm 86:04dd9b1680ae 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
bogdanm 92:4fc01daae5a5 59 * @{
bogdanm 92:4fc01daae5a5 60 */
bogdanm 86:04dd9b1680ae 61
bogdanm 86:04dd9b1680ae 62 /**
bogdanm 86:04dd9b1680ae 63 * @brief TIM Hall sensor Configuration Structure definition
bogdanm 86:04dd9b1680ae 64 */
bogdanm 86:04dd9b1680ae 65
bogdanm 86:04dd9b1680ae 66 typedef struct
bogdanm 86:04dd9b1680ae 67 {
bogdanm 86:04dd9b1680ae 68
bogdanm 86:04dd9b1680ae 69 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 86:04dd9b1680ae 70 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 86:04dd9b1680ae 71
bogdanm 86:04dd9b1680ae 72 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 86:04dd9b1680ae 73 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 86:04dd9b1680ae 74
bogdanm 86:04dd9b1680ae 75 uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm 86:04dd9b1680ae 76 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 77 uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 86:04dd9b1680ae 78 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 86:04dd9b1680ae 79 } TIM_HallSensor_InitTypeDef;
bogdanm 86:04dd9b1680ae 80
bogdanm 86:04dd9b1680ae 81 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 82 /**
bogdanm 86:04dd9b1680ae 83 * @brief TIM Master configuration Structure definition
bogdanm 86:04dd9b1680ae 84 * @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO
bogdanm 86:04dd9b1680ae 85 * output
bogdanm 86:04dd9b1680ae 86 */
bogdanm 86:04dd9b1680ae 87 typedef struct {
bogdanm 86:04dd9b1680ae 88 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
bogdanm 86:04dd9b1680ae 89 This parameter can be a value of @ref TIM_Master_Mode_Selection */
bogdanm 86:04dd9b1680ae 90 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
bogdanm 86:04dd9b1680ae 91 This parameter can be a value of @ref TIM_Master_Slave_Mode */
bogdanm 86:04dd9b1680ae 92 }TIM_MasterConfigTypeDef;
bogdanm 86:04dd9b1680ae 93
bogdanm 86:04dd9b1680ae 94 /**
bogdanm 86:04dd9b1680ae 95 * @brief TIM Break and Dead time configuration Structure definition
bogdanm 86:04dd9b1680ae 96 * @note STM32F373xC and STM32F378xx: single break input with configurable polarity.
bogdanm 86:04dd9b1680ae 97 */
bogdanm 86:04dd9b1680ae 98 typedef struct
bogdanm 86:04dd9b1680ae 99 {
bogdanm 86:04dd9b1680ae 100 uint32_t OffStateRunMode; /*!< TIM off state in run mode
bogdanm 86:04dd9b1680ae 101 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
bogdanm 86:04dd9b1680ae 102 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
bogdanm 86:04dd9b1680ae 103 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
bogdanm 86:04dd9b1680ae 104 uint32_t LockLevel; /*!< TIM Lock level
bogdanm 86:04dd9b1680ae 105 This parameter can be a value of @ref TIM_Lock_level */
bogdanm 86:04dd9b1680ae 106 uint32_t DeadTime; /*!< TIM dead Time
bogdanm 86:04dd9b1680ae 107 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm 86:04dd9b1680ae 108 uint32_t BreakState; /*!< TIM Break State
bogdanm 86:04dd9b1680ae 109 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
bogdanm 86:04dd9b1680ae 110 uint32_t BreakPolarity; /*!< TIM Break input polarity
bogdanm 86:04dd9b1680ae 111 This parameter can be a value of @ref TIM_Break_Polarity */
bogdanm 86:04dd9b1680ae 112 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
bogdanm 86:04dd9b1680ae 113 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
bogdanm 86:04dd9b1680ae 114 } TIM_BreakDeadTimeConfigTypeDef;
bogdanm 86:04dd9b1680ae 115
bogdanm 86:04dd9b1680ae 116 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 117
bogdanm 92:4fc01daae5a5 118 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 92:4fc01daae5a5 119 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 92:4fc01daae5a5 120 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 92:4fc01daae5a5 121 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 122 /**
bogdanm 86:04dd9b1680ae 123 * @brief TIM Break input(s) and Dead time configuration Structure definition
bogdanm 86:04dd9b1680ae 124 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
bogdanm 86:04dd9b1680ae 125 * filter and polarity.
bogdanm 86:04dd9b1680ae 126 */
bogdanm 86:04dd9b1680ae 127 typedef struct
bogdanm 86:04dd9b1680ae 128 {
bogdanm 86:04dd9b1680ae 129 uint32_t OffStateRunMode; /*!< TIM off state in run mode
bogdanm 86:04dd9b1680ae 130 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
bogdanm 86:04dd9b1680ae 131 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
bogdanm 86:04dd9b1680ae 132 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
bogdanm 86:04dd9b1680ae 133 uint32_t LockLevel; /*!< TIM Lock level
bogdanm 86:04dd9b1680ae 134 This parameter can be a value of @ref TIM_Lock_level */
bogdanm 86:04dd9b1680ae 135 uint32_t DeadTime; /*!< TIM dead Time
bogdanm 86:04dd9b1680ae 136 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm 86:04dd9b1680ae 137 uint32_t BreakState; /*!< TIM Break State
bogdanm 86:04dd9b1680ae 138 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
bogdanm 86:04dd9b1680ae 139 uint32_t BreakPolarity; /*!< TIM Break input polarity
bogdanm 86:04dd9b1680ae 140 This parameter can be a value of @ref TIM_Break_Polarity */
bogdanm 86:04dd9b1680ae 141 uint32_t BreakFilter; /*!< Specifies the brek input filter.
bogdanm 86:04dd9b1680ae 142 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 143 uint32_t Break2State; /*!< TIM Break2 State
bogdanm 86:04dd9b1680ae 144 This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
bogdanm 86:04dd9b1680ae 145 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
bogdanm 86:04dd9b1680ae 146 This parameter can be a value of @ref TIMEx_Break2_Polarity */
bogdanm 86:04dd9b1680ae 147 uint32_t Break2Filter; /*!< TIM break2 input filter.
bogdanm 86:04dd9b1680ae 148 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 149 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
bogdanm 86:04dd9b1680ae 150 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
bogdanm 86:04dd9b1680ae 151 } TIM_BreakDeadTimeConfigTypeDef;
bogdanm 86:04dd9b1680ae 152
bogdanm 86:04dd9b1680ae 153 /**
bogdanm 86:04dd9b1680ae 154 * @brief TIM Master configuration Structure definition
bogdanm 86:04dd9b1680ae 155 * @note Advanced timers provide TRGO2 internal line which is redirected
bogdanm 86:04dd9b1680ae 156 * to the ADC
bogdanm 86:04dd9b1680ae 157 */
bogdanm 86:04dd9b1680ae 158 typedef struct {
bogdanm 86:04dd9b1680ae 159 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
bogdanm 86:04dd9b1680ae 160 This parameter can be a value of @ref TIM_Master_Mode_Selection */
bogdanm 86:04dd9b1680ae 161 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
bogdanm 86:04dd9b1680ae 162 This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
bogdanm 86:04dd9b1680ae 163 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
bogdanm 86:04dd9b1680ae 164 This parameter can be a value of @ref TIM_Master_Slave_Mode */
bogdanm 86:04dd9b1680ae 165 }TIM_MasterConfigTypeDef;
bogdanm 92:4fc01daae5a5 166 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 86:04dd9b1680ae 167 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 92:4fc01daae5a5 168 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 169 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 92:4fc01daae5a5 170 /**
bogdanm 92:4fc01daae5a5 171 * @}
bogdanm 92:4fc01daae5a5 172 */
bogdanm 86:04dd9b1680ae 173
bogdanm 86:04dd9b1680ae 174 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 175 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
bogdanm 86:04dd9b1680ae 176 * @{
bogdanm 86:04dd9b1680ae 177 */
bogdanm 86:04dd9b1680ae 178
bogdanm 86:04dd9b1680ae 179 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 92:4fc01daae5a5 180 /** @defgroup TIMEx_Channel TIM Extended Channel
bogdanm 86:04dd9b1680ae 181 * @{
bogdanm 86:04dd9b1680ae 182 */
bogdanm 86:04dd9b1680ae 183 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 184 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm 86:04dd9b1680ae 185 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm 86:04dd9b1680ae 186 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm 86:04dd9b1680ae 187 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm 86:04dd9b1680ae 188
bogdanm 86:04dd9b1680ae 189 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 190 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 191 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 192 ((CHANNEL) == TIM_CHANNEL_4) || \
bogdanm 86:04dd9b1680ae 193 ((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm 86:04dd9b1680ae 194
bogdanm 86:04dd9b1680ae 195 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 196 ((CHANNEL) == TIM_CHANNEL_2))
bogdanm 86:04dd9b1680ae 197
bogdanm 86:04dd9b1680ae 198 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 199 ((CHANNEL) == TIM_CHANNEL_2))
bogdanm 86:04dd9b1680ae 200
bogdanm 86:04dd9b1680ae 201 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 202 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 203 ((CHANNEL) == TIM_CHANNEL_3))
bogdanm 86:04dd9b1680ae 204 /**
bogdanm 86:04dd9b1680ae 205 * @}
bogdanm 86:04dd9b1680ae 206 */
bogdanm 86:04dd9b1680ae 207
bogdanm 92:4fc01daae5a5 208 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes
bogdanm 86:04dd9b1680ae 209 * @{
bogdanm 86:04dd9b1680ae 210 */
bogdanm 86:04dd9b1680ae 211
bogdanm 86:04dd9b1680ae 212 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 213 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
bogdanm 86:04dd9b1680ae 214 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
bogdanm 86:04dd9b1680ae 215 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
bogdanm 86:04dd9b1680ae 216 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
bogdanm 86:04dd9b1680ae 217 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
bogdanm 86:04dd9b1680ae 218 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
bogdanm 86:04dd9b1680ae 219 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
bogdanm 86:04dd9b1680ae 220
bogdanm 86:04dd9b1680ae 221 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
bogdanm 86:04dd9b1680ae 222 ((MODE) == TIM_OCMODE_PWM2))
bogdanm 86:04dd9b1680ae 223
bogdanm 86:04dd9b1680ae 224 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
bogdanm 86:04dd9b1680ae 225 ((MODE) == TIM_OCMODE_ACTIVE) || \
bogdanm 86:04dd9b1680ae 226 ((MODE) == TIM_OCMODE_INACTIVE) || \
bogdanm 86:04dd9b1680ae 227 ((MODE) == TIM_OCMODE_TOGGLE) || \
bogdanm 86:04dd9b1680ae 228 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
bogdanm 86:04dd9b1680ae 229 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm 86:04dd9b1680ae 230 /**
bogdanm 86:04dd9b1680ae 231 * @}
bogdanm 86:04dd9b1680ae 232 */
bogdanm 86:04dd9b1680ae 233
bogdanm 92:4fc01daae5a5 234 /** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
bogdanm 86:04dd9b1680ae 235 * @{
bogdanm 86:04dd9b1680ae 236 */
bogdanm 86:04dd9b1680ae 237 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm 86:04dd9b1680ae 238 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 239
bogdanm 86:04dd9b1680ae 240 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
bogdanm 86:04dd9b1680ae 241 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
bogdanm 86:04dd9b1680ae 242 /**
bogdanm 86:04dd9b1680ae 243 * @}
bogdanm 86:04dd9b1680ae 244 */
bogdanm 86:04dd9b1680ae 245
bogdanm 92:4fc01daae5a5 246 /** @defgroup TIMEx_Slave_Mode TIM Extended Slave Mode
bogdanm 86:04dd9b1680ae 247 * @{
bogdanm 86:04dd9b1680ae 248 */
bogdanm 86:04dd9b1680ae 249
bogdanm 86:04dd9b1680ae 250 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 251 #define TIM_SLAVEMODE_RESET ((uint16_t)0x0004)
bogdanm 86:04dd9b1680ae 252 #define TIM_SLAVEMODE_GATED ((uint16_t)0x0005)
bogdanm 86:04dd9b1680ae 253 #define TIM_SLAVEMODE_TRIGGER ((uint16_t)0x0006)
bogdanm 86:04dd9b1680ae 254 #define TIM_SLAVEMODE_EXTERNAL1 ((uint16_t)0x0007)
bogdanm 86:04dd9b1680ae 255
bogdanm 86:04dd9b1680ae 256 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
bogdanm 86:04dd9b1680ae 257 ((MODE) == TIM_SLAVEMODE_RESET) || \
bogdanm 86:04dd9b1680ae 258 ((MODE) == TIM_SLAVEMODE_GATED) || \
bogdanm 86:04dd9b1680ae 259 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
bogdanm 86:04dd9b1680ae 260 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm 86:04dd9b1680ae 261 /**
bogdanm 86:04dd9b1680ae 262 * @}
bogdanm 86:04dd9b1680ae 263 */
bogdanm 86:04dd9b1680ae 264
bogdanm 92:4fc01daae5a5 265 /** @defgroup TIMEx_Event_Source TIM Extended Event Source
bogdanm 86:04dd9b1680ae 266 * @{
bogdanm 86:04dd9b1680ae 267 */
bogdanm 86:04dd9b1680ae 268
bogdanm 86:04dd9b1680ae 269 #define TIM_EventSource_Update TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
bogdanm 86:04dd9b1680ae 270 #define TIM_EventSource_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
bogdanm 86:04dd9b1680ae 271 #define TIM_EventSource_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
bogdanm 86:04dd9b1680ae 272 #define TIM_EventSource_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
bogdanm 86:04dd9b1680ae 273 #define TIM_EventSource_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
bogdanm 86:04dd9b1680ae 274 #define TIM_EventSource_COM TIM_EGR_COMG /*!< A commutation event is generated */
bogdanm 86:04dd9b1680ae 275 #define TIM_EventSource_Trigger TIM_EGR_TG /*!< A trigger event is generated */
bogdanm 86:04dd9b1680ae 276 #define TIM_EventSource_Break TIM_EGR_BG /*!< A break event is generated */
bogdanm 86:04dd9b1680ae 277 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm 86:04dd9b1680ae 278
bogdanm 86:04dd9b1680ae 279 /**
bogdanm 86:04dd9b1680ae 280 * @}
bogdanm 86:04dd9b1680ae 281 */
bogdanm 86:04dd9b1680ae 282
bogdanm 92:4fc01daae5a5 283 /** @defgroup TIMEx_DMA_Base_address TIM Extended DMA BAse Address
bogdanm 86:04dd9b1680ae 284 * @{
bogdanm 86:04dd9b1680ae 285 */
bogdanm 86:04dd9b1680ae 286
bogdanm 86:04dd9b1680ae 287 #define TIM_DMABase_CR1 (0x00000000)
bogdanm 86:04dd9b1680ae 288 #define TIM_DMABase_CR2 (0x00000001)
bogdanm 86:04dd9b1680ae 289 #define TIM_DMABase_SMCR (0x00000002)
bogdanm 86:04dd9b1680ae 290 #define TIM_DMABase_DIER (0x00000003)
bogdanm 86:04dd9b1680ae 291 #define TIM_DMABase_SR (0x00000004)
bogdanm 86:04dd9b1680ae 292 #define TIM_DMABase_EGR (0x00000005)
bogdanm 86:04dd9b1680ae 293 #define TIM_DMABase_CCMR1 (0x00000006)
bogdanm 86:04dd9b1680ae 294 #define TIM_DMABase_CCMR2 (0x00000007)
bogdanm 86:04dd9b1680ae 295 #define TIM_DMABase_CCER (0x00000008)
bogdanm 86:04dd9b1680ae 296 #define TIM_DMABase_CNT (0x00000009)
bogdanm 86:04dd9b1680ae 297 #define TIM_DMABase_PSC (0x0000000A)
bogdanm 86:04dd9b1680ae 298 #define TIM_DMABase_ARR (0x0000000B)
bogdanm 86:04dd9b1680ae 299 #define TIM_DMABase_RCR (0x0000000C)
bogdanm 86:04dd9b1680ae 300 #define TIM_DMABase_CCR1 (0x0000000D)
bogdanm 86:04dd9b1680ae 301 #define TIM_DMABase_CCR2 (0x0000000E)
bogdanm 86:04dd9b1680ae 302 #define TIM_DMABase_CCR3 (0x0000000F)
bogdanm 86:04dd9b1680ae 303 #define TIM_DMABase_CCR4 (0x00000010)
bogdanm 86:04dd9b1680ae 304 #define TIM_DMABase_BDTR (0x00000011)
bogdanm 86:04dd9b1680ae 305 #define TIM_DMABase_DCR (0x00000012)
bogdanm 86:04dd9b1680ae 306 #define TIM_DMABase_OR (0x00000013)
bogdanm 86:04dd9b1680ae 307 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
bogdanm 86:04dd9b1680ae 308 ((BASE) == TIM_DMABase_CR2) || \
bogdanm 86:04dd9b1680ae 309 ((BASE) == TIM_DMABase_SMCR) || \
bogdanm 86:04dd9b1680ae 310 ((BASE) == TIM_DMABase_DIER) || \
bogdanm 86:04dd9b1680ae 311 ((BASE) == TIM_DMABase_SR) || \
bogdanm 86:04dd9b1680ae 312 ((BASE) == TIM_DMABase_EGR) || \
bogdanm 86:04dd9b1680ae 313 ((BASE) == TIM_DMABase_CCMR1) || \
bogdanm 86:04dd9b1680ae 314 ((BASE) == TIM_DMABase_CCMR2) || \
bogdanm 86:04dd9b1680ae 315 ((BASE) == TIM_DMABase_CCER) || \
bogdanm 86:04dd9b1680ae 316 ((BASE) == TIM_DMABase_CNT) || \
bogdanm 86:04dd9b1680ae 317 ((BASE) == TIM_DMABase_PSC) || \
bogdanm 86:04dd9b1680ae 318 ((BASE) == TIM_DMABase_ARR) || \
bogdanm 86:04dd9b1680ae 319 ((BASE) == TIM_DMABase_RCR) || \
bogdanm 86:04dd9b1680ae 320 ((BASE) == TIM_DMABase_CCR1) || \
bogdanm 86:04dd9b1680ae 321 ((BASE) == TIM_DMABase_CCR2) || \
bogdanm 86:04dd9b1680ae 322 ((BASE) == TIM_DMABase_CCR3) || \
bogdanm 86:04dd9b1680ae 323 ((BASE) == TIM_DMABase_CCR4) || \
bogdanm 86:04dd9b1680ae 324 ((BASE) == TIM_DMABase_BDTR) || \
bogdanm 86:04dd9b1680ae 325 ((BASE) == TIM_DMABase_DCR) || \
bogdanm 86:04dd9b1680ae 326 ((BASE) == TIM_DMABase_OR))
bogdanm 86:04dd9b1680ae 327 /**
bogdanm 86:04dd9b1680ae 328 * @}
bogdanm 86:04dd9b1680ae 329 */
bogdanm 86:04dd9b1680ae 330 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 331
bogdanm 92:4fc01daae5a5 332 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 92:4fc01daae5a5 333 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 92:4fc01daae5a5 334 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 92:4fc01daae5a5 335 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 92:4fc01daae5a5 336 /** @defgroup TIMEx_Channel TIM Extended Channel
bogdanm 86:04dd9b1680ae 337 * @{
bogdanm 86:04dd9b1680ae 338 */
bogdanm 86:04dd9b1680ae 339
bogdanm 86:04dd9b1680ae 340 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 341 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm 86:04dd9b1680ae 342 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm 86:04dd9b1680ae 343 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm 86:04dd9b1680ae 344 #define TIM_CHANNEL_5 ((uint32_t)0x0010)
bogdanm 86:04dd9b1680ae 345 #define TIM_CHANNEL_6 ((uint32_t)0x0014)
bogdanm 86:04dd9b1680ae 346 #define TIM_CHANNEL_ALL ((uint32_t)0x003C)
bogdanm 86:04dd9b1680ae 347
bogdanm 86:04dd9b1680ae 348 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 349 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 350 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 351 ((CHANNEL) == TIM_CHANNEL_4) || \
bogdanm 86:04dd9b1680ae 352 ((CHANNEL) == TIM_CHANNEL_5) || \
bogdanm 86:04dd9b1680ae 353 ((CHANNEL) == TIM_CHANNEL_6) || \
bogdanm 86:04dd9b1680ae 354 ((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm 86:04dd9b1680ae 355
bogdanm 86:04dd9b1680ae 356 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 357 ((CHANNEL) == TIM_CHANNEL_2))
bogdanm 86:04dd9b1680ae 358
bogdanm 86:04dd9b1680ae 359 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 360 ((CHANNEL) == TIM_CHANNEL_2))
bogdanm 86:04dd9b1680ae 361
bogdanm 86:04dd9b1680ae 362 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 363 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 364 ((CHANNEL) == TIM_CHANNEL_3))
bogdanm 86:04dd9b1680ae 365 /**
bogdanm 86:04dd9b1680ae 366 * @}
bogdanm 86:04dd9b1680ae 367 */
bogdanm 86:04dd9b1680ae 368
bogdanm 92:4fc01daae5a5 369 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes
bogdanm 86:04dd9b1680ae 370 * @{
bogdanm 86:04dd9b1680ae 371 */
bogdanm 86:04dd9b1680ae 372 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 373 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
bogdanm 86:04dd9b1680ae 374 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
bogdanm 86:04dd9b1680ae 375 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
bogdanm 86:04dd9b1680ae 376 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
bogdanm 86:04dd9b1680ae 377 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
bogdanm 86:04dd9b1680ae 378 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
bogdanm 86:04dd9b1680ae 379 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
bogdanm 86:04dd9b1680ae 380
bogdanm 86:04dd9b1680ae 381 #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
bogdanm 86:04dd9b1680ae 382 #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
bogdanm 86:04dd9b1680ae 383 #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
bogdanm 86:04dd9b1680ae 384 #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
bogdanm 86:04dd9b1680ae 385 #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
bogdanm 86:04dd9b1680ae 386 #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
bogdanm 86:04dd9b1680ae 387
bogdanm 86:04dd9b1680ae 388 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
bogdanm 86:04dd9b1680ae 389 ((MODE) == TIM_OCMODE_PWM2) || \
bogdanm 86:04dd9b1680ae 390 ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
bogdanm 86:04dd9b1680ae 391 ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
bogdanm 86:04dd9b1680ae 392 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
bogdanm 86:04dd9b1680ae 393 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
bogdanm 86:04dd9b1680ae 394
bogdanm 86:04dd9b1680ae 395 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
bogdanm 86:04dd9b1680ae 396 ((MODE) == TIM_OCMODE_ACTIVE) || \
bogdanm 86:04dd9b1680ae 397 ((MODE) == TIM_OCMODE_INACTIVE) || \
bogdanm 86:04dd9b1680ae 398 ((MODE) == TIM_OCMODE_TOGGLE) || \
bogdanm 86:04dd9b1680ae 399 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
bogdanm 86:04dd9b1680ae 400 ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
bogdanm 86:04dd9b1680ae 401 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
bogdanm 86:04dd9b1680ae 402 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
bogdanm 86:04dd9b1680ae 403 /**
bogdanm 86:04dd9b1680ae 404 * @}
bogdanm 86:04dd9b1680ae 405 */
bogdanm 86:04dd9b1680ae 406
bogdanm 92:4fc01daae5a5 407 /** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
bogdanm 86:04dd9b1680ae 408 * @{
bogdanm 86:04dd9b1680ae 409 */
bogdanm 86:04dd9b1680ae 410 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm 86:04dd9b1680ae 411 #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
bogdanm 86:04dd9b1680ae 412 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 413
bogdanm 86:04dd9b1680ae 414 #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
bogdanm 86:04dd9b1680ae 415 ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
bogdanm 86:04dd9b1680ae 416 ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
bogdanm 86:04dd9b1680ae 417 /**
bogdanm 86:04dd9b1680ae 418 * @}
bogdanm 86:04dd9b1680ae 419 */
bogdanm 86:04dd9b1680ae 420
bogdanm 92:4fc01daae5a5 421 /** @defgroup TIMEx_BreakInput_Filter TIM Extended Break Input Filter
bogdanm 86:04dd9b1680ae 422 * @{
bogdanm 86:04dd9b1680ae 423 */
bogdanm 86:04dd9b1680ae 424
bogdanm 86:04dd9b1680ae 425 #define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xF)
bogdanm 86:04dd9b1680ae 426 /**
bogdanm 86:04dd9b1680ae 427 * @}
bogdanm 86:04dd9b1680ae 428 */
bogdanm 86:04dd9b1680ae 429
bogdanm 92:4fc01daae5a5 430 /** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
bogdanm 86:04dd9b1680ae 431 * @{
bogdanm 86:04dd9b1680ae 432 */
bogdanm 86:04dd9b1680ae 433 #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 434 #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
bogdanm 86:04dd9b1680ae 435
bogdanm 86:04dd9b1680ae 436 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
bogdanm 86:04dd9b1680ae 437 ((STATE) == TIM_BREAK2_DISABLE))
bogdanm 86:04dd9b1680ae 438 /**
bogdanm 86:04dd9b1680ae 439 * @}
bogdanm 86:04dd9b1680ae 440 */
bogdanm 92:4fc01daae5a5 441 /** @defgroup TIMEx_Break2_Polarity TIM Extended Break Input 2 Polarity
bogdanm 86:04dd9b1680ae 442 * @{
bogdanm 86:04dd9b1680ae 443 */
bogdanm 86:04dd9b1680ae 444 #define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 445 #define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
bogdanm 86:04dd9b1680ae 446
bogdanm 86:04dd9b1680ae 447 #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \
bogdanm 86:04dd9b1680ae 448 ((POLARITY) == TIM_BREAK2POLARITY_HIGH))
bogdanm 86:04dd9b1680ae 449 /**
bogdanm 86:04dd9b1680ae 450 * @}
bogdanm 86:04dd9b1680ae 451 */
bogdanm 86:04dd9b1680ae 452
bogdanm 92:4fc01daae5a5 453 /** @defgroup TIMEx_Master_Mode_Selection_2 TIM Extended Master Mode Selection 2 (TRGO2)
bogdanm 86:04dd9b1680ae 454 * @{
bogdanm 86:04dd9b1680ae 455 */
bogdanm 86:04dd9b1680ae 456 #define TIM_TRGO2_RESET ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 457 #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
bogdanm 86:04dd9b1680ae 458 #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
bogdanm 86:04dd9b1680ae 459 #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
bogdanm 86:04dd9b1680ae 460 #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
bogdanm 86:04dd9b1680ae 461 #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
bogdanm 86:04dd9b1680ae 462 #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
bogdanm 86:04dd9b1680ae 463 #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
bogdanm 86:04dd9b1680ae 464 #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
bogdanm 86:04dd9b1680ae 465 #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
bogdanm 86:04dd9b1680ae 466 #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
bogdanm 86:04dd9b1680ae 467 #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
bogdanm 86:04dd9b1680ae 468 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
bogdanm 86:04dd9b1680ae 469 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
bogdanm 86:04dd9b1680ae 470 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
bogdanm 86:04dd9b1680ae 471 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
bogdanm 86:04dd9b1680ae 472
bogdanm 86:04dd9b1680ae 473 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
bogdanm 86:04dd9b1680ae 474 ((SOURCE) == TIM_TRGO2_ENABLE) || \
bogdanm 86:04dd9b1680ae 475 ((SOURCE) == TIM_TRGO2_UPDATE) || \
bogdanm 86:04dd9b1680ae 476 ((SOURCE) == TIM_TRGO2_OC1) || \
bogdanm 86:04dd9b1680ae 477 ((SOURCE) == TIM_TRGO2_OC1REF) || \
bogdanm 86:04dd9b1680ae 478 ((SOURCE) == TIM_TRGO2_OC2REF) || \
bogdanm 86:04dd9b1680ae 479 ((SOURCE) == TIM_TRGO2_OC3REF) || \
bogdanm 86:04dd9b1680ae 480 ((SOURCE) == TIM_TRGO2_OC3REF) || \
bogdanm 86:04dd9b1680ae 481 ((SOURCE) == TIM_TRGO2_OC4REF) || \
bogdanm 86:04dd9b1680ae 482 ((SOURCE) == TIM_TRGO2_OC5REF) || \
bogdanm 86:04dd9b1680ae 483 ((SOURCE) == TIM_TRGO2_OC6REF) || \
bogdanm 86:04dd9b1680ae 484 ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
bogdanm 86:04dd9b1680ae 485 ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
bogdanm 86:04dd9b1680ae 486 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
bogdanm 86:04dd9b1680ae 487 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
bogdanm 86:04dd9b1680ae 488 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
bogdanm 86:04dd9b1680ae 489 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
bogdanm 86:04dd9b1680ae 490 /**
bogdanm 86:04dd9b1680ae 491 * @}
bogdanm 86:04dd9b1680ae 492 */
bogdanm 86:04dd9b1680ae 493
bogdanm 92:4fc01daae5a5 494 /** @defgroup TIMEx_Slave_Mode TIM Extended Slave mode
bogdanm 86:04dd9b1680ae 495 * @{
bogdanm 86:04dd9b1680ae 496 */
bogdanm 86:04dd9b1680ae 497 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 498 #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
bogdanm 86:04dd9b1680ae 499 #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
bogdanm 86:04dd9b1680ae 500 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
bogdanm 86:04dd9b1680ae 501 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
bogdanm 86:04dd9b1680ae 502 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
bogdanm 86:04dd9b1680ae 503
bogdanm 86:04dd9b1680ae 504 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
bogdanm 86:04dd9b1680ae 505 ((MODE) == TIM_SLAVEMODE_RESET) || \
bogdanm 86:04dd9b1680ae 506 ((MODE) == TIM_SLAVEMODE_GATED) || \
bogdanm 86:04dd9b1680ae 507 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
bogdanm 86:04dd9b1680ae 508 ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
bogdanm 86:04dd9b1680ae 509 ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
bogdanm 86:04dd9b1680ae 510 /**
bogdanm 86:04dd9b1680ae 511 * @}
bogdanm 86:04dd9b1680ae 512 */
bogdanm 86:04dd9b1680ae 513
bogdanm 92:4fc01daae5a5 514 /** @defgroup TIM_Event_Source TIM Extended Event Source
bogdanm 86:04dd9b1680ae 515 * @{
bogdanm 86:04dd9b1680ae 516 */
bogdanm 86:04dd9b1680ae 517
bogdanm 86:04dd9b1680ae 518 #define TIM_EventSource_Update TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
bogdanm 86:04dd9b1680ae 519 #define TIM_EventSource_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
bogdanm 86:04dd9b1680ae 520 #define TIM_EventSource_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
bogdanm 86:04dd9b1680ae 521 #define TIM_EventSource_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
bogdanm 86:04dd9b1680ae 522 #define TIM_EventSource_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
bogdanm 86:04dd9b1680ae 523 #define TIM_EventSource_COM TIM_EGR_COMG /*!< A commutation event is generated */
bogdanm 86:04dd9b1680ae 524 #define TIM_EventSource_Trigger TIM_EGR_TG /*!< A trigger event is generated */
bogdanm 86:04dd9b1680ae 525 #define TIM_EventSource_Break TIM_EGR_BG /*!< A break event is generated */
bogdanm 86:04dd9b1680ae 526 #define TIM_EventSource_Break2 TIM_EGR_B2G /*!< A break 2 event is generated */
bogdanm 86:04dd9b1680ae 527 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm 86:04dd9b1680ae 528
bogdanm 86:04dd9b1680ae 529 /**
bogdanm 86:04dd9b1680ae 530 * @}
bogdanm 86:04dd9b1680ae 531 */
bogdanm 86:04dd9b1680ae 532
bogdanm 92:4fc01daae5a5 533 /** @defgroup TIM_DMA_Base_address TIM Extended DMA Base Address
bogdanm 86:04dd9b1680ae 534 * @{
bogdanm 86:04dd9b1680ae 535 */
bogdanm 86:04dd9b1680ae 536
bogdanm 86:04dd9b1680ae 537 #define TIM_DMABase_CR1 (0x00000000)
bogdanm 86:04dd9b1680ae 538 #define TIM_DMABase_CR2 (0x00000001)
bogdanm 86:04dd9b1680ae 539 #define TIM_DMABase_SMCR (0x00000002)
bogdanm 86:04dd9b1680ae 540 #define TIM_DMABase_DIER (0x00000003)
bogdanm 86:04dd9b1680ae 541 #define TIM_DMABase_SR (0x00000004)
bogdanm 86:04dd9b1680ae 542 #define TIM_DMABase_EGR (0x00000005)
bogdanm 86:04dd9b1680ae 543 #define TIM_DMABase_CCMR1 (0x00000006)
bogdanm 86:04dd9b1680ae 544 #define TIM_DMABase_CCMR2 (0x00000007)
bogdanm 86:04dd9b1680ae 545 #define TIM_DMABase_CCER (0x00000008)
bogdanm 86:04dd9b1680ae 546 #define TIM_DMABase_CNT (0x00000009)
bogdanm 86:04dd9b1680ae 547 #define TIM_DMABase_PSC (0x0000000A)
bogdanm 86:04dd9b1680ae 548 #define TIM_DMABase_ARR (0x0000000B)
bogdanm 86:04dd9b1680ae 549 #define TIM_DMABase_RCR (0x0000000C)
bogdanm 86:04dd9b1680ae 550 #define TIM_DMABase_CCR1 (0x0000000D)
bogdanm 86:04dd9b1680ae 551 #define TIM_DMABase_CCR2 (0x0000000E)
bogdanm 86:04dd9b1680ae 552 #define TIM_DMABase_CCR3 (0x0000000F)
bogdanm 86:04dd9b1680ae 553 #define TIM_DMABase_CCR4 (0x00000010)
bogdanm 86:04dd9b1680ae 554 #define TIM_DMABase_BDTR (0x00000011)
bogdanm 86:04dd9b1680ae 555 #define TIM_DMABase_DCR (0x00000012)
bogdanm 86:04dd9b1680ae 556 #define TIM_DMABase_CCMR3 (0x00000015)
bogdanm 86:04dd9b1680ae 557 #define TIM_DMABase_CCR5 (0x00000016)
bogdanm 86:04dd9b1680ae 558 #define TIM_DMABase_CCR6 (0x00000017)
bogdanm 86:04dd9b1680ae 559 #define TIM_DMABase_OR (0x00000018)
bogdanm 86:04dd9b1680ae 560 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
bogdanm 86:04dd9b1680ae 561 ((BASE) == TIM_DMABase_CR2) || \
bogdanm 86:04dd9b1680ae 562 ((BASE) == TIM_DMABase_SMCR) || \
bogdanm 86:04dd9b1680ae 563 ((BASE) == TIM_DMABase_DIER) || \
bogdanm 86:04dd9b1680ae 564 ((BASE) == TIM_DMABase_SR) || \
bogdanm 86:04dd9b1680ae 565 ((BASE) == TIM_DMABase_EGR) || \
bogdanm 86:04dd9b1680ae 566 ((BASE) == TIM_DMABase_CCMR1) || \
bogdanm 86:04dd9b1680ae 567 ((BASE) == TIM_DMABase_CCMR2) || \
bogdanm 86:04dd9b1680ae 568 ((BASE) == TIM_DMABase_CCER) || \
bogdanm 86:04dd9b1680ae 569 ((BASE) == TIM_DMABase_CNT) || \
bogdanm 86:04dd9b1680ae 570 ((BASE) == TIM_DMABase_PSC) || \
bogdanm 86:04dd9b1680ae 571 ((BASE) == TIM_DMABase_ARR) || \
bogdanm 86:04dd9b1680ae 572 ((BASE) == TIM_DMABase_RCR) || \
bogdanm 86:04dd9b1680ae 573 ((BASE) == TIM_DMABase_CCR1) || \
bogdanm 86:04dd9b1680ae 574 ((BASE) == TIM_DMABase_CCR2) || \
bogdanm 86:04dd9b1680ae 575 ((BASE) == TIM_DMABase_CCR3) || \
bogdanm 86:04dd9b1680ae 576 ((BASE) == TIM_DMABase_CCR4) || \
bogdanm 86:04dd9b1680ae 577 ((BASE) == TIM_DMABase_BDTR) || \
bogdanm 86:04dd9b1680ae 578 ((BASE) == TIM_DMABase_CCMR3) || \
bogdanm 86:04dd9b1680ae 579 ((BASE) == TIM_DMABase_CCR5) || \
bogdanm 86:04dd9b1680ae 580 ((BASE) == TIM_DMABase_CCR6) || \
bogdanm 86:04dd9b1680ae 581 ((BASE) == TIM_DMABase_OR))
bogdanm 86:04dd9b1680ae 582 /**
bogdanm 86:04dd9b1680ae 583 * @}
bogdanm 86:04dd9b1680ae 584 */
bogdanm 92:4fc01daae5a5 585 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 86:04dd9b1680ae 586 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 92:4fc01daae5a5 587 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 588 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 589
bogdanm 92:4fc01daae5a5 590 #if defined(STM32F302xE) || \
bogdanm 92:4fc01daae5a5 591 defined(STM32F302xC) || \
bogdanm 92:4fc01daae5a5 592 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 92:4fc01daae5a5 593 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 92:4fc01daae5a5 594 /** @defgroup TIMEx_Remap TIM Extended Remapping
bogdanm 86:04dd9b1680ae 595 * @{
bogdanm 86:04dd9b1680ae 596 */
bogdanm 86:04dd9b1680ae 597 #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
bogdanm 86:04dd9b1680ae 598 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
bogdanm 86:04dd9b1680ae 599 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
bogdanm 86:04dd9b1680ae 600 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
bogdanm 86:04dd9b1680ae 601 #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
bogdanm 86:04dd9b1680ae 602 #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
bogdanm 86:04dd9b1680ae 603 #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
bogdanm 86:04dd9b1680ae 604 #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
bogdanm 86:04dd9b1680ae 605
bogdanm 86:04dd9b1680ae 606 #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
bogdanm 86:04dd9b1680ae 607 ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
bogdanm 86:04dd9b1680ae 608 ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
bogdanm 86:04dd9b1680ae 609 ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\
bogdanm 86:04dd9b1680ae 610 ((REMAP) == TIM_TIM16_GPIO) ||\
bogdanm 86:04dd9b1680ae 611 ((REMAP) == TIM_TIM16_RTC) ||\
bogdanm 86:04dd9b1680ae 612 ((REMAP) == TIM_TIM16_HSE) ||\
bogdanm 86:04dd9b1680ae 613 ((REMAP) == TIM_TIM16_MCO))
bogdanm 86:04dd9b1680ae 614 /**
bogdanm 86:04dd9b1680ae 615 * @}
bogdanm 86:04dd9b1680ae 616 */
bogdanm 92:4fc01daae5a5 617 #endif /* STM32F302xE || */
bogdanm 92:4fc01daae5a5 618 /* STM32F302xC || */
bogdanm 92:4fc01daae5a5 619 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 620 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
bogdanm 86:04dd9b1680ae 621
bogdanm 86:04dd9b1680ae 622 #if defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 92:4fc01daae5a5 623 /** @defgroup TIMEx_Remap TIM Extended Remapping 1
bogdanm 86:04dd9b1680ae 624 * @{
bogdanm 86:04dd9b1680ae 625 */
bogdanm 86:04dd9b1680ae 626 #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
bogdanm 86:04dd9b1680ae 627 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
bogdanm 86:04dd9b1680ae 628 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
bogdanm 86:04dd9b1680ae 629 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
bogdanm 86:04dd9b1680ae 630 #define TIM_TIM8_ADC2_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
bogdanm 86:04dd9b1680ae 631 #define TIM_TIM8_ADC2_AWD1 (0x00000001) /* !< TIM8_ETR is connected to ADC2 AWD1 */
bogdanm 86:04dd9b1680ae 632 #define TIM_TIM8_ADC2_AWD2 (0x00000002) /* !< TIM8_ETR is connected to ADC2 AWD2 */
bogdanm 86:04dd9b1680ae 633 #define TIM_TIM8_ADC2_AWD3 (0x00000003) /* !< TIM8_ETR is connected to ADC2 AWD3 */
bogdanm 86:04dd9b1680ae 634 #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
bogdanm 86:04dd9b1680ae 635 #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
bogdanm 86:04dd9b1680ae 636 #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
bogdanm 86:04dd9b1680ae 637 #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
bogdanm 86:04dd9b1680ae 638
bogdanm 86:04dd9b1680ae 639 #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
bogdanm 86:04dd9b1680ae 640 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
bogdanm 86:04dd9b1680ae 641 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
bogdanm 86:04dd9b1680ae 642 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
bogdanm 86:04dd9b1680ae 643 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
bogdanm 86:04dd9b1680ae 644 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
bogdanm 86:04dd9b1680ae 645 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
bogdanm 86:04dd9b1680ae 646 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
bogdanm 86:04dd9b1680ae 647 ((REMAP1) == TIM_TIM16_GPIO) ||\
bogdanm 86:04dd9b1680ae 648 ((REMAP1) == TIM_TIM16_RTC) ||\
bogdanm 86:04dd9b1680ae 649 ((REMAP1) == TIM_TIM16_HSE) ||\
bogdanm 86:04dd9b1680ae 650 ((REMAP1) == TIM_TIM16_MCO))
bogdanm 86:04dd9b1680ae 651 /**
bogdanm 86:04dd9b1680ae 652 * @}
bogdanm 86:04dd9b1680ae 653 */
bogdanm 86:04dd9b1680ae 654
bogdanm 92:4fc01daae5a5 655 /** @defgroup TIMEx_Remap2 TIM Extended Remapping 2
bogdanm 86:04dd9b1680ae 656 * @{
bogdanm 86:04dd9b1680ae 657 */
bogdanm 86:04dd9b1680ae 658 #define TIM_TIM1_ADC4_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
bogdanm 86:04dd9b1680ae 659 #define TIM_TIM1_ADC4_AWD1 (0x00000004) /* !< TIM1_ETR is connected to ADC4 AWD1 */
bogdanm 86:04dd9b1680ae 660 #define TIM_TIM1_ADC4_AWD2 (0x00000008) /* !< TIM1_ETR is connected to ADC4 AWD2 */
bogdanm 86:04dd9b1680ae 661 #define TIM_TIM1_ADC4_AWD3 (0x0000000C) /* !< TIM1_ETR is connected to ADC4 AWD3 */
bogdanm 86:04dd9b1680ae 662 #define TIM_TIM8_ADC3_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
bogdanm 86:04dd9b1680ae 663 #define TIM_TIM8_ADC3_AWD1 (0x00000004) /* !< TIM8_ETR is connected to ADC3 AWD1 */
bogdanm 86:04dd9b1680ae 664 #define TIM_TIM8_ADC3_AWD2 (0x00000008) /* !< TIM8_ETR is connected to ADC3 AWD2 */
bogdanm 86:04dd9b1680ae 665 #define TIM_TIM8_ADC3_AWD3 (0x0000000C) /* !< TIM8_ETR is connected to ADC3 AWD3 */
bogdanm 86:04dd9b1680ae 666 #define TIM_TIM16_NONE (0x00000000) /* !< Non significant value for TIM16 */
bogdanm 86:04dd9b1680ae 667
bogdanm 86:04dd9b1680ae 668 #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
bogdanm 86:04dd9b1680ae 669 ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
bogdanm 86:04dd9b1680ae 670 ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
bogdanm 86:04dd9b1680ae 671 ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
bogdanm 86:04dd9b1680ae 672 ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
bogdanm 86:04dd9b1680ae 673 ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
bogdanm 86:04dd9b1680ae 674 ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
bogdanm 86:04dd9b1680ae 675 ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
bogdanm 86:04dd9b1680ae 676 ((REMAP2) == TIM_TIM16_NONE))
bogdanm 86:04dd9b1680ae 677 /**
bogdanm 86:04dd9b1680ae 678 * @}
bogdanm 86:04dd9b1680ae 679 */
bogdanm 86:04dd9b1680ae 680 #endif /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 681
bogdanm 92:4fc01daae5a5 682 #if defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 92:4fc01daae5a5 683 /** @defgroup TIMEx_Remap TIM Extended Remapping 1
bogdanm 92:4fc01daae5a5 684 * @{
bogdanm 92:4fc01daae5a5 685 */
bogdanm 92:4fc01daae5a5 686 #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
bogdanm 92:4fc01daae5a5 687 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
bogdanm 92:4fc01daae5a5 688 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
bogdanm 92:4fc01daae5a5 689 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
bogdanm 92:4fc01daae5a5 690 #define TIM_TIM8_ADC2_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
bogdanm 92:4fc01daae5a5 691 #define TIM_TIM8_ADC2_AWD1 (0x00000001) /* !< TIM8_ETR is connected to ADC2 AWD1 */
bogdanm 92:4fc01daae5a5 692 #define TIM_TIM8_ADC2_AWD2 (0x00000002) /* !< TIM8_ETR is connected to ADC2 AWD2 */
bogdanm 92:4fc01daae5a5 693 #define TIM_TIM8_ADC2_AWD3 (0x00000003) /* !< TIM8_ETR is connected to ADC2 AWD3 */
bogdanm 92:4fc01daae5a5 694 #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
bogdanm 92:4fc01daae5a5 695 #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
bogdanm 92:4fc01daae5a5 696 #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
bogdanm 92:4fc01daae5a5 697 #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
bogdanm 92:4fc01daae5a5 698 #define TIM_TIM20_ADC3_NONE (0x00000000) /* !< TIM20_ETR is not connected to any AWD (analog watchdog) */
bogdanm 92:4fc01daae5a5 699 #define TIM_TIM20_ADC3_AWD1 (0x00000001) /* !< TIM20_ETR is connected to ADC3 AWD1 */
bogdanm 92:4fc01daae5a5 700 #define TIM_TIM20_ADC3_AWD2 (0x00000002) /* !< TIM20_ETR is connected to ADC3 AWD2 */
bogdanm 92:4fc01daae5a5 701 #define TIM_TIM20_ADC3_AWD3 (0x00000003) /* !< TIM20_ETR is connected to ADC3 AWD3 */
bogdanm 92:4fc01daae5a5 702
bogdanm 92:4fc01daae5a5 703 #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
bogdanm 92:4fc01daae5a5 704 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
bogdanm 92:4fc01daae5a5 705 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
bogdanm 92:4fc01daae5a5 706 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
bogdanm 92:4fc01daae5a5 707 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
bogdanm 92:4fc01daae5a5 708 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
bogdanm 92:4fc01daae5a5 709 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
bogdanm 92:4fc01daae5a5 710 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
bogdanm 92:4fc01daae5a5 711 ((REMAP1) == TIM_TIM16_GPIO) ||\
bogdanm 92:4fc01daae5a5 712 ((REMAP1) == TIM_TIM16_RTC) ||\
bogdanm 92:4fc01daae5a5 713 ((REMAP1) == TIM_TIM16_HSE) ||\
bogdanm 92:4fc01daae5a5 714 ((REMAP1) == TIM_TIM16_MCO) ||\
bogdanm 92:4fc01daae5a5 715 ((REMAP1) == TIM_TIM20_ADC3_NONE) ||\
bogdanm 92:4fc01daae5a5 716 ((REMAP1) == TIM_TIM20_ADC3_AWD1) ||\
bogdanm 92:4fc01daae5a5 717 ((REMAP1) == TIM_TIM20_ADC3_AWD2) ||\
bogdanm 92:4fc01daae5a5 718 ((REMAP1) == TIM_TIM20_ADC3_AWD3))
bogdanm 92:4fc01daae5a5 719 /**
bogdanm 92:4fc01daae5a5 720 * @}
bogdanm 92:4fc01daae5a5 721 */
bogdanm 92:4fc01daae5a5 722
bogdanm 92:4fc01daae5a5 723 /** @defgroup TIMEx_Remap2 TIM Extended Remapping 2
bogdanm 92:4fc01daae5a5 724 * @{
bogdanm 92:4fc01daae5a5 725 */
bogdanm 92:4fc01daae5a5 726 #define TIM_TIM1_ADC4_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
bogdanm 92:4fc01daae5a5 727 #define TIM_TIM1_ADC4_AWD1 (0x00000004) /* !< TIM1_ETR is connected to ADC4 AWD1 */
bogdanm 92:4fc01daae5a5 728 #define TIM_TIM1_ADC4_AWD2 (0x00000008) /* !< TIM1_ETR is connected to ADC4 AWD2 */
bogdanm 92:4fc01daae5a5 729 #define TIM_TIM1_ADC4_AWD3 (0x0000000C) /* !< TIM1_ETR is connected to ADC4 AWD3 */
bogdanm 92:4fc01daae5a5 730 #define TIM_TIM8_ADC3_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
bogdanm 92:4fc01daae5a5 731 #define TIM_TIM8_ADC3_AWD1 (0x00000004) /* !< TIM8_ETR is connected to ADC3 AWD1 */
bogdanm 92:4fc01daae5a5 732 #define TIM_TIM8_ADC3_AWD2 (0x00000008) /* !< TIM8_ETR is connected to ADC3 AWD2 */
bogdanm 92:4fc01daae5a5 733 #define TIM_TIM8_ADC3_AWD3 (0x0000000C) /* !< TIM8_ETR is connected to ADC3 AWD3 */
bogdanm 92:4fc01daae5a5 734 #define TIM_TIM16_NONE (0x00000000) /* !< Non significant value for TIM16 */
bogdanm 92:4fc01daae5a5 735 #define TIM_TIM20_ADC4_NONE (0x00000000) /* !< TIM20_ETR is not connected to any AWD (analog watchdog) */
bogdanm 92:4fc01daae5a5 736 #define TIM_TIM20_ADC4_AWD1 (0x00000004) /* !< TIM20_ETR is connected to ADC4 AWD1 */
bogdanm 92:4fc01daae5a5 737 #define TIM_TIM20_ADC4_AWD2 (0x00000008) /* !< TIM20_ETR is connected to ADC4 AWD2 */
bogdanm 92:4fc01daae5a5 738 #define TIM_TIM20_ADC4_AWD3 (0x0000000C) /* !< TIM20_ETR is connected to ADC4 AWD3 */
bogdanm 92:4fc01daae5a5 739
bogdanm 92:4fc01daae5a5 740 #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
bogdanm 92:4fc01daae5a5 741 ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
bogdanm 92:4fc01daae5a5 742 ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
bogdanm 92:4fc01daae5a5 743 ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
bogdanm 92:4fc01daae5a5 744 ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
bogdanm 92:4fc01daae5a5 745 ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
bogdanm 92:4fc01daae5a5 746 ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
bogdanm 92:4fc01daae5a5 747 ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
bogdanm 92:4fc01daae5a5 748 ((REMAP2) == TIM_TIM16_NONE) ||\
bogdanm 92:4fc01daae5a5 749 ((REMAP2) == TIM_TIM20_ADC4_NONE) ||\
bogdanm 92:4fc01daae5a5 750 ((REMAP2) == TIM_TIM20_ADC4_AWD1) ||\
bogdanm 92:4fc01daae5a5 751 ((REMAP2) == TIM_TIM20_ADC4_AWD2) ||\
bogdanm 92:4fc01daae5a5 752 ((REMAP2) == TIM_TIM20_ADC4_AWD3))
bogdanm 92:4fc01daae5a5 753 /**
bogdanm 92:4fc01daae5a5 754 * @}
bogdanm 92:4fc01daae5a5 755 */
bogdanm 92:4fc01daae5a5 756 #endif /* STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 757
bogdanm 92:4fc01daae5a5 758
bogdanm 86:04dd9b1680ae 759 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 92:4fc01daae5a5 760 /** @defgroup TIMEx_Remap TIM Extended remapping
bogdanm 86:04dd9b1680ae 761 * @{
bogdanm 86:04dd9b1680ae 762 */
bogdanm 86:04dd9b1680ae 763
bogdanm 86:04dd9b1680ae 764 #define TIM_TIM2_TIM8_TRGO (0x00000000) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
bogdanm 86:04dd9b1680ae 765 #define TIM_TIM2_ETH_PTP (0x00000400) /*!< PTP trigger output is connected to TIM2_ITR1 */
bogdanm 86:04dd9b1680ae 766 #define TIM_TIM2_USBFS_SOF (0x00000800) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
bogdanm 86:04dd9b1680ae 767 #define TIM_TIM2_USBHS_SOF (0x00000C00) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
bogdanm 86:04dd9b1680ae 768 #define TIM_TIM14_GPIO (0x00000000) /* !< TIM14 TI1 is connected to GPIO */
bogdanm 86:04dd9b1680ae 769 #define TIM_TIM14_RTC (0x00000001) /* !< TIM14 TI1 is connected to RTC_clock */
bogdanm 86:04dd9b1680ae 770 #define TIM_TIM14_HSE (0x00000002) /* !< TIM14 TI1 is connected to HSE/32 */
bogdanm 86:04dd9b1680ae 771 #define TIM_TIM14_MCO (0x00000003) /* !< TIM14 TI1 is connected to MCO */
bogdanm 86:04dd9b1680ae 772
bogdanm 86:04dd9b1680ae 773 #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) ||\
bogdanm 86:04dd9b1680ae 774 ((REMAP) == TIM_TIM2_ETH_PTP) ||\
bogdanm 86:04dd9b1680ae 775 ((REMAP) == TIM_TIM2_USBFS_SOF) ||\
bogdanm 86:04dd9b1680ae 776 ((REMAP) == TIM_TIM2_USBHS_SOF) ||\
bogdanm 86:04dd9b1680ae 777 ((REMAP) == TIM_TIM14_GPIO) ||\
bogdanm 86:04dd9b1680ae 778 ((REMAP) == TIM_TIM14_RTC) ||\
bogdanm 86:04dd9b1680ae 779 ((REMAP) == TIM_TIM14_HSE) ||\
bogdanm 86:04dd9b1680ae 780 ((REMAP) == TIM_TIM14_MCO))
bogdanm 86:04dd9b1680ae 781
bogdanm 86:04dd9b1680ae 782 /**
bogdanm 86:04dd9b1680ae 783 * @}
bogdanm 86:04dd9b1680ae 784 */
bogdanm 86:04dd9b1680ae 785 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 786
bogdanm 92:4fc01daae5a5 787 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 92:4fc01daae5a5 788 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 92:4fc01daae5a5 789 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 92:4fc01daae5a5 790 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 92:4fc01daae5a5 791 /** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
bogdanm 86:04dd9b1680ae 792 * @{
bogdanm 86:04dd9b1680ae 793 */
bogdanm 86:04dd9b1680ae 794 #define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
bogdanm 86:04dd9b1680ae 795 #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
bogdanm 86:04dd9b1680ae 796 #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
bogdanm 86:04dd9b1680ae 797 #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
bogdanm 86:04dd9b1680ae 798
bogdanm 86:04dd9b1680ae 799 #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
bogdanm 86:04dd9b1680ae 800 /**
bogdanm 86:04dd9b1680ae 801 * @}
bogdanm 86:04dd9b1680ae 802 */
bogdanm 92:4fc01daae5a5 803 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 86:04dd9b1680ae 804 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 92:4fc01daae5a5 805 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 806 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 92:4fc01daae5a5 807
bogdanm 92:4fc01daae5a5 808 /** @defgroup TIM_Clock_Filter TIM Clock Filter
bogdanm 92:4fc01daae5a5 809 * @{
bogdanm 92:4fc01daae5a5 810 */
bogdanm 92:4fc01daae5a5 811 #define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
bogdanm 92:4fc01daae5a5 812 /**
bogdanm 92:4fc01daae5a5 813 * @}
bogdanm 92:4fc01daae5a5 814 */
bogdanm 92:4fc01daae5a5 815
bogdanm 86:04dd9b1680ae 816 /**
bogdanm 86:04dd9b1680ae 817 * @}
bogdanm 86:04dd9b1680ae 818 */
bogdanm 86:04dd9b1680ae 819
bogdanm 86:04dd9b1680ae 820 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 821 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
bogdanm 92:4fc01daae5a5 822 * @{
bogdanm 92:4fc01daae5a5 823 */
bogdanm 92:4fc01daae5a5 824
bogdanm 86:04dd9b1680ae 825 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 826 /**
bogdanm 86:04dd9b1680ae 827 * @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm 86:04dd9b1680ae 828 * calling another time ConfigChannel function.
bogdanm 86:04dd9b1680ae 829 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 830 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 86:04dd9b1680ae 831 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 832 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 86:04dd9b1680ae 833 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 86:04dd9b1680ae 834 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 86:04dd9b1680ae 835 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 86:04dd9b1680ae 836 * @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm 86:04dd9b1680ae 837 * @retval None
bogdanm 86:04dd9b1680ae 838 */
bogdanm 86:04dd9b1680ae 839 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm 86:04dd9b1680ae 840 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm 86:04dd9b1680ae 841
bogdanm 86:04dd9b1680ae 842 /**
bogdanm 86:04dd9b1680ae 843 * @brief Gets the TIM Capture Compare Register value on runtime
bogdanm 86:04dd9b1680ae 844 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 845 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm 86:04dd9b1680ae 846 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 847 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm 86:04dd9b1680ae 848 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm 86:04dd9b1680ae 849 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm 86:04dd9b1680ae 850 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm 86:04dd9b1680ae 851 * @retval None
bogdanm 86:04dd9b1680ae 852 */
bogdanm 86:04dd9b1680ae 853 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
bogdanm 86:04dd9b1680ae 854 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm 86:04dd9b1680ae 855 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 856
bogdanm 92:4fc01daae5a5 857 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 92:4fc01daae5a5 858 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 92:4fc01daae5a5 859 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 92:4fc01daae5a5 860 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 861 /**
bogdanm 86:04dd9b1680ae 862 * @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm 86:04dd9b1680ae 863 * calling another time ConfigChannel function.
bogdanm 86:04dd9b1680ae 864 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 865 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 86:04dd9b1680ae 866 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 867 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 86:04dd9b1680ae 868 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 86:04dd9b1680ae 869 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 86:04dd9b1680ae 870 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 86:04dd9b1680ae 871 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm 86:04dd9b1680ae 872 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm 86:04dd9b1680ae 873 * @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm 86:04dd9b1680ae 874 * @retval None
bogdanm 86:04dd9b1680ae 875 */
bogdanm 86:04dd9b1680ae 876 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm 86:04dd9b1680ae 877 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
bogdanm 86:04dd9b1680ae 878 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
bogdanm 86:04dd9b1680ae 879 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
bogdanm 86:04dd9b1680ae 880 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
bogdanm 86:04dd9b1680ae 881 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
bogdanm 86:04dd9b1680ae 882 ((__HANDLE__)->Instance->CCR6 |= (__COMPARE__)))
bogdanm 86:04dd9b1680ae 883
bogdanm 86:04dd9b1680ae 884 /**
bogdanm 86:04dd9b1680ae 885 * @brief Gets the TIM Capture Compare Register value on runtime
bogdanm 86:04dd9b1680ae 886 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 887 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm 86:04dd9b1680ae 888 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 889 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm 86:04dd9b1680ae 890 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm 86:04dd9b1680ae 891 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm 86:04dd9b1680ae 892 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm 86:04dd9b1680ae 893 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
bogdanm 86:04dd9b1680ae 894 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
bogdanm 86:04dd9b1680ae 895 * @retval None
bogdanm 86:04dd9b1680ae 896 */
bogdanm 86:04dd9b1680ae 897 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
bogdanm 86:04dd9b1680ae 898 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
bogdanm 86:04dd9b1680ae 899 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
bogdanm 86:04dd9b1680ae 900 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
bogdanm 86:04dd9b1680ae 901 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
bogdanm 86:04dd9b1680ae 902 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
bogdanm 86:04dd9b1680ae 903 ((__HANDLE__)->Instance->CCR6))
bogdanm 92:4fc01daae5a5 904 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 86:04dd9b1680ae 905 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 92:4fc01daae5a5 906 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 907 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 92:4fc01daae5a5 908 /**
bogdanm 92:4fc01daae5a5 909 * @}
bogdanm 92:4fc01daae5a5 910 */
bogdanm 86:04dd9b1680ae 911
bogdanm 86:04dd9b1680ae 912 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 913 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
bogdanm 92:4fc01daae5a5 914 * @{
bogdanm 92:4fc01daae5a5 915 */
bogdanm 86:04dd9b1680ae 916
bogdanm 92:4fc01daae5a5 917 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
bogdanm 92:4fc01daae5a5 918 * @brief Timer Hall Sensor functions
bogdanm 92:4fc01daae5a5 919 * @{
bogdanm 92:4fc01daae5a5 920 */
bogdanm 86:04dd9b1680ae 921 /* Timer Hall Sensor functions **********************************************/
bogdanm 86:04dd9b1680ae 922 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
bogdanm 86:04dd9b1680ae 923 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 924
bogdanm 86:04dd9b1680ae 925 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 926 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 927
bogdanm 86:04dd9b1680ae 928 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 929 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 930 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 931 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 932 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 933 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 934 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 935 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
bogdanm 86:04dd9b1680ae 936 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 937 /**
bogdanm 92:4fc01daae5a5 938 * @}
bogdanm 92:4fc01daae5a5 939 */
bogdanm 86:04dd9b1680ae 940
bogdanm 92:4fc01daae5a5 941 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
bogdanm 92:4fc01daae5a5 942 * @brief Timer Complementary Output Compare functions
bogdanm 92:4fc01daae5a5 943 * @{
bogdanm 92:4fc01daae5a5 944 */
bogdanm 86:04dd9b1680ae 945 /* Timer Complementary Output Compare functions *****************************/
bogdanm 86:04dd9b1680ae 946 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 947 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 948 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 949
bogdanm 86:04dd9b1680ae 950 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 951 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 952 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 953
bogdanm 86:04dd9b1680ae 954 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 955 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 86:04dd9b1680ae 956 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 957 /**
bogdanm 92:4fc01daae5a5 958 * @}
bogdanm 92:4fc01daae5a5 959 */
bogdanm 86:04dd9b1680ae 960
bogdanm 92:4fc01daae5a5 961 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
bogdanm 92:4fc01daae5a5 962 * @brief Timer Complementary PWM functions
bogdanm 92:4fc01daae5a5 963 * @{
bogdanm 92:4fc01daae5a5 964 */
bogdanm 86:04dd9b1680ae 965 /* Timer Complementary PWM functions ****************************************/
bogdanm 86:04dd9b1680ae 966 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 967 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 968 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 969
bogdanm 86:04dd9b1680ae 970 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 971 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 972 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 973 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 974 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 86:04dd9b1680ae 975 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 976 /**
bogdanm 92:4fc01daae5a5 977 * @}
bogdanm 92:4fc01daae5a5 978 */
bogdanm 86:04dd9b1680ae 979
bogdanm 92:4fc01daae5a5 980 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
bogdanm 92:4fc01daae5a5 981 * @brief Timer Complementary One Pulse functions
bogdanm 92:4fc01daae5a5 982 * @{
bogdanm 92:4fc01daae5a5 983 */
bogdanm 86:04dd9b1680ae 984 /* Timer Complementary One Pulse functions **********************************/
bogdanm 86:04dd9b1680ae 985 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 986 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 86:04dd9b1680ae 987 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 86:04dd9b1680ae 988
bogdanm 86:04dd9b1680ae 989 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 990 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 86:04dd9b1680ae 991 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 92:4fc01daae5a5 992 /**
bogdanm 92:4fc01daae5a5 993 * @}
bogdanm 92:4fc01daae5a5 994 */
bogdanm 86:04dd9b1680ae 995
bogdanm 92:4fc01daae5a5 996 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
bogdanm 92:4fc01daae5a5 997 * @brief Peripheral Control functions
bogdanm 92:4fc01daae5a5 998 * @{
bogdanm 92:4fc01daae5a5 999 */
bogdanm 92:4fc01daae5a5 1000 /* Extended Control functions ************************************************/
bogdanm 86:04dd9b1680ae 1001 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
bogdanm 86:04dd9b1680ae 1002 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
bogdanm 86:04dd9b1680ae 1003 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
bogdanm 86:04dd9b1680ae 1004 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
bogdanm 86:04dd9b1680ae 1005 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
bogdanm 86:04dd9b1680ae 1006
bogdanm 92:4fc01daae5a5 1007 #if defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 92:4fc01daae5a5 1008 defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1009 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
bogdanm 92:4fc01daae5a5 1010 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 1011 /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1012
bogdanm 92:4fc01daae5a5 1013 #if defined(STM32F302xE) || \
bogdanm 92:4fc01daae5a5 1014 defined(STM32F302xC) || \
bogdanm 86:04dd9b1680ae 1015 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 92:4fc01daae5a5 1016 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 86:04dd9b1680ae 1017 defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1018 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
bogdanm 92:4fc01daae5a5 1019 #endif /* STM32F302xE || */
bogdanm 92:4fc01daae5a5 1020 /* STM32F302xC || */
bogdanm 86:04dd9b1680ae 1021 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 1022 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
bogdanm 92:4fc01daae5a5 1023 /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1024
bogdanm 92:4fc01daae5a5 1025 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 92:4fc01daae5a5 1026 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 92:4fc01daae5a5 1027 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 92:4fc01daae5a5 1028 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 1029 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
bogdanm 92:4fc01daae5a5 1030 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 86:04dd9b1680ae 1031 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 92:4fc01daae5a5 1032 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 1033 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 92:4fc01daae5a5 1034 /**
bogdanm 92:4fc01daae5a5 1035 * @}
bogdanm 92:4fc01daae5a5 1036 */
bogdanm 86:04dd9b1680ae 1037
bogdanm 92:4fc01daae5a5 1038 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
bogdanm 92:4fc01daae5a5 1039 * @brief Extended Callbacks functions
bogdanm 92:4fc01daae5a5 1040 * @{
bogdanm 92:4fc01daae5a5 1041 */
bogdanm 92:4fc01daae5a5 1042 /* Extended Callback *********************************************************/
bogdanm 86:04dd9b1680ae 1043 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1044 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1045 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 1046 /**
bogdanm 92:4fc01daae5a5 1047 * @}
bogdanm 92:4fc01daae5a5 1048 */
bogdanm 86:04dd9b1680ae 1049
bogdanm 92:4fc01daae5a5 1050 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
bogdanm 92:4fc01daae5a5 1051 * @brief Extended Peripheral State functions
bogdanm 92:4fc01daae5a5 1052 * @{
bogdanm 92:4fc01daae5a5 1053 */
bogdanm 92:4fc01daae5a5 1054 /* Extended Peripheral State functions **************************************/
bogdanm 86:04dd9b1680ae 1055 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1056 /**
bogdanm 92:4fc01daae5a5 1057 * @}
bogdanm 92:4fc01daae5a5 1058 */
bogdanm 92:4fc01daae5a5 1059
bogdanm 92:4fc01daae5a5 1060 /**
bogdanm 92:4fc01daae5a5 1061 * @}
bogdanm 92:4fc01daae5a5 1062 */
bogdanm 86:04dd9b1680ae 1063
bogdanm 86:04dd9b1680ae 1064 /**
bogdanm 86:04dd9b1680ae 1065 * @}
bogdanm 86:04dd9b1680ae 1066 */
bogdanm 86:04dd9b1680ae 1067
bogdanm 86:04dd9b1680ae 1068 /**
bogdanm 86:04dd9b1680ae 1069 * @}
bogdanm 86:04dd9b1680ae 1070 */
bogdanm 86:04dd9b1680ae 1071
bogdanm 86:04dd9b1680ae 1072 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 1073 }
bogdanm 86:04dd9b1680ae 1074 #endif
bogdanm 86:04dd9b1680ae 1075
bogdanm 86:04dd9b1680ae 1076
bogdanm 86:04dd9b1680ae 1077 #endif /* __STM32F3xx_HAL_TIM_EX_H */
bogdanm 86:04dd9b1680ae 1078
bogdanm 86:04dd9b1680ae 1079 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/