Ricardo Benitez
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TARGET_NUCLEO_F334R8/stm32f3xx_hal_tim_ex.h@86:04dd9b1680ae, 2014-07-02 (annotated)
- Committer:
- bogdanm
- Date:
- Wed Jul 02 13:22:23 2014 +0100
- Revision:
- 86:04dd9b1680ae
- Child:
- 92:4fc01daae5a5
Release 86 of the mbed library
Main changes:
- bug fixes in various backends
- mbed "error" replaced by assert logic (mbed_assert)
- new ST Nucleo targets
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 86:04dd9b1680ae | 1 | /** |
| bogdanm | 86:04dd9b1680ae | 2 | ****************************************************************************** |
| bogdanm | 86:04dd9b1680ae | 3 | * @file stm32f3xx_hal_tim_ex.h |
| bogdanm | 86:04dd9b1680ae | 4 | * @author MCD Application Team |
| bogdanm | 86:04dd9b1680ae | 5 | * @version V1.0.1 |
| bogdanm | 86:04dd9b1680ae | 6 | * @date 18-June-2014 |
| bogdanm | 86:04dd9b1680ae | 7 | * @brief Header file of TIM HAL Extension module. |
| bogdanm | 86:04dd9b1680ae | 8 | ****************************************************************************** |
| bogdanm | 86:04dd9b1680ae | 9 | * @attention |
| bogdanm | 86:04dd9b1680ae | 10 | * |
| bogdanm | 86:04dd9b1680ae | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 86:04dd9b1680ae | 12 | * |
| bogdanm | 86:04dd9b1680ae | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 86:04dd9b1680ae | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 86:04dd9b1680ae | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 86:04dd9b1680ae | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 86:04dd9b1680ae | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 86:04dd9b1680ae | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 86:04dd9b1680ae | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 86:04dd9b1680ae | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 86:04dd9b1680ae | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 86:04dd9b1680ae | 22 | * without specific prior written permission. |
| bogdanm | 86:04dd9b1680ae | 23 | * |
| bogdanm | 86:04dd9b1680ae | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 86:04dd9b1680ae | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 86:04dd9b1680ae | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 86:04dd9b1680ae | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 86:04dd9b1680ae | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 86:04dd9b1680ae | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 86:04dd9b1680ae | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 86:04dd9b1680ae | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 86:04dd9b1680ae | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 86:04dd9b1680ae | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 86:04dd9b1680ae | 34 | * |
| bogdanm | 86:04dd9b1680ae | 35 | ****************************************************************************** |
| bogdanm | 86:04dd9b1680ae | 36 | */ |
| bogdanm | 86:04dd9b1680ae | 37 | |
| bogdanm | 86:04dd9b1680ae | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 86:04dd9b1680ae | 39 | #ifndef __STM32F3xx_HAL_TIM_EX_H |
| bogdanm | 86:04dd9b1680ae | 40 | #define __STM32F3xx_HAL_TIM_EX_H |
| bogdanm | 86:04dd9b1680ae | 41 | |
| bogdanm | 86:04dd9b1680ae | 42 | #ifdef __cplusplus |
| bogdanm | 86:04dd9b1680ae | 43 | extern "C" { |
| bogdanm | 86:04dd9b1680ae | 44 | #endif |
| bogdanm | 86:04dd9b1680ae | 45 | |
| bogdanm | 86:04dd9b1680ae | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 86:04dd9b1680ae | 47 | #include "stm32f3xx_hal_def.h" |
| bogdanm | 86:04dd9b1680ae | 48 | |
| bogdanm | 86:04dd9b1680ae | 49 | /** @addtogroup STM32F3xx_HAL_Driver |
| bogdanm | 86:04dd9b1680ae | 50 | * @{ |
| bogdanm | 86:04dd9b1680ae | 51 | */ |
| bogdanm | 86:04dd9b1680ae | 52 | |
| bogdanm | 86:04dd9b1680ae | 53 | /** @addtogroup TIMEx |
| bogdanm | 86:04dd9b1680ae | 54 | * @{ |
| bogdanm | 86:04dd9b1680ae | 55 | */ |
| bogdanm | 86:04dd9b1680ae | 56 | |
| bogdanm | 86:04dd9b1680ae | 57 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 86:04dd9b1680ae | 58 | |
| bogdanm | 86:04dd9b1680ae | 59 | /** |
| bogdanm | 86:04dd9b1680ae | 60 | * @brief TIM Hall sensor Configuration Structure definition |
| bogdanm | 86:04dd9b1680ae | 61 | */ |
| bogdanm | 86:04dd9b1680ae | 62 | |
| bogdanm | 86:04dd9b1680ae | 63 | typedef struct |
| bogdanm | 86:04dd9b1680ae | 64 | { |
| bogdanm | 86:04dd9b1680ae | 65 | |
| bogdanm | 86:04dd9b1680ae | 66 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
| bogdanm | 86:04dd9b1680ae | 67 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
| bogdanm | 86:04dd9b1680ae | 68 | |
| bogdanm | 86:04dd9b1680ae | 69 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
| bogdanm | 86:04dd9b1680ae | 70 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
| bogdanm | 86:04dd9b1680ae | 71 | |
| bogdanm | 86:04dd9b1680ae | 72 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
| bogdanm | 86:04dd9b1680ae | 73 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| bogdanm | 86:04dd9b1680ae | 74 | uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
| bogdanm | 86:04dd9b1680ae | 75 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
| bogdanm | 86:04dd9b1680ae | 76 | } TIM_HallSensor_InitTypeDef; |
| bogdanm | 86:04dd9b1680ae | 77 | |
| bogdanm | 86:04dd9b1680ae | 78 | #if defined(STM32F373xC) || defined(STM32F378xx) |
| bogdanm | 86:04dd9b1680ae | 79 | /** |
| bogdanm | 86:04dd9b1680ae | 80 | * @brief TIM Master configuration Structure definition |
| bogdanm | 86:04dd9b1680ae | 81 | * @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO |
| bogdanm | 86:04dd9b1680ae | 82 | * output |
| bogdanm | 86:04dd9b1680ae | 83 | */ |
| bogdanm | 86:04dd9b1680ae | 84 | typedef struct { |
| bogdanm | 86:04dd9b1680ae | 85 | uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection |
| bogdanm | 86:04dd9b1680ae | 86 | This parameter can be a value of @ref TIM_Master_Mode_Selection */ |
| bogdanm | 86:04dd9b1680ae | 87 | uint32_t MasterSlaveMode; /*!< Master/slave mode selection |
| bogdanm | 86:04dd9b1680ae | 88 | This parameter can be a value of @ref TIM_Master_Slave_Mode */ |
| bogdanm | 86:04dd9b1680ae | 89 | }TIM_MasterConfigTypeDef; |
| bogdanm | 86:04dd9b1680ae | 90 | |
| bogdanm | 86:04dd9b1680ae | 91 | /** |
| bogdanm | 86:04dd9b1680ae | 92 | * @brief TIM Break and Dead time configuration Structure definition |
| bogdanm | 86:04dd9b1680ae | 93 | * @note STM32F373xC and STM32F378xx: single break input with configurable polarity. |
| bogdanm | 86:04dd9b1680ae | 94 | */ |
| bogdanm | 86:04dd9b1680ae | 95 | typedef struct |
| bogdanm | 86:04dd9b1680ae | 96 | { |
| bogdanm | 86:04dd9b1680ae | 97 | uint32_t OffStateRunMode; /*!< TIM off state in run mode |
| bogdanm | 86:04dd9b1680ae | 98 | This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ |
| bogdanm | 86:04dd9b1680ae | 99 | uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode |
| bogdanm | 86:04dd9b1680ae | 100 | This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ |
| bogdanm | 86:04dd9b1680ae | 101 | uint32_t LockLevel; /*!< TIM Lock level |
| bogdanm | 86:04dd9b1680ae | 102 | This parameter can be a value of @ref TIM_Lock_level */ |
| bogdanm | 86:04dd9b1680ae | 103 | uint32_t DeadTime; /*!< TIM dead Time |
| bogdanm | 86:04dd9b1680ae | 104 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
| bogdanm | 86:04dd9b1680ae | 105 | uint32_t BreakState; /*!< TIM Break State |
| bogdanm | 86:04dd9b1680ae | 106 | This parameter can be a value of @ref TIM_Break_Input_enable_disable */ |
| bogdanm | 86:04dd9b1680ae | 107 | uint32_t BreakPolarity; /*!< TIM Break input polarity |
| bogdanm | 86:04dd9b1680ae | 108 | This parameter can be a value of @ref TIM_Break_Polarity */ |
| bogdanm | 86:04dd9b1680ae | 109 | uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state |
| bogdanm | 86:04dd9b1680ae | 110 | This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
| bogdanm | 86:04dd9b1680ae | 111 | } TIM_BreakDeadTimeConfigTypeDef; |
| bogdanm | 86:04dd9b1680ae | 112 | |
| bogdanm | 86:04dd9b1680ae | 113 | #endif /* STM32F373xC || STM32F378xx */ |
| bogdanm | 86:04dd9b1680ae | 114 | |
| bogdanm | 86:04dd9b1680ae | 115 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
| bogdanm | 86:04dd9b1680ae | 116 | defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) || \ |
| bogdanm | 86:04dd9b1680ae | 117 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
| bogdanm | 86:04dd9b1680ae | 118 | /** |
| bogdanm | 86:04dd9b1680ae | 119 | * @brief TIM Break input(s) and Dead time configuration Structure definition |
| bogdanm | 86:04dd9b1680ae | 120 | * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable |
| bogdanm | 86:04dd9b1680ae | 121 | * filter and polarity. |
| bogdanm | 86:04dd9b1680ae | 122 | */ |
| bogdanm | 86:04dd9b1680ae | 123 | typedef struct |
| bogdanm | 86:04dd9b1680ae | 124 | { |
| bogdanm | 86:04dd9b1680ae | 125 | uint32_t OffStateRunMode; /*!< TIM off state in run mode |
| bogdanm | 86:04dd9b1680ae | 126 | This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ |
| bogdanm | 86:04dd9b1680ae | 127 | uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode |
| bogdanm | 86:04dd9b1680ae | 128 | This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ |
| bogdanm | 86:04dd9b1680ae | 129 | uint32_t LockLevel; /*!< TIM Lock level |
| bogdanm | 86:04dd9b1680ae | 130 | This parameter can be a value of @ref TIM_Lock_level */ |
| bogdanm | 86:04dd9b1680ae | 131 | uint32_t DeadTime; /*!< TIM dead Time |
| bogdanm | 86:04dd9b1680ae | 132 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
| bogdanm | 86:04dd9b1680ae | 133 | uint32_t BreakState; /*!< TIM Break State |
| bogdanm | 86:04dd9b1680ae | 134 | This parameter can be a value of @ref TIM_Break_Input_enable_disable */ |
| bogdanm | 86:04dd9b1680ae | 135 | uint32_t BreakPolarity; /*!< TIM Break input polarity |
| bogdanm | 86:04dd9b1680ae | 136 | This parameter can be a value of @ref TIM_Break_Polarity */ |
| bogdanm | 86:04dd9b1680ae | 137 | uint32_t BreakFilter; /*!< Specifies the brek input filter. |
| bogdanm | 86:04dd9b1680ae | 138 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| bogdanm | 86:04dd9b1680ae | 139 | uint32_t Break2State; /*!< TIM Break2 State |
| bogdanm | 86:04dd9b1680ae | 140 | This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */ |
| bogdanm | 86:04dd9b1680ae | 141 | uint32_t Break2Polarity; /*!< TIM Break2 input polarity |
| bogdanm | 86:04dd9b1680ae | 142 | This parameter can be a value of @ref TIMEx_Break2_Polarity */ |
| bogdanm | 86:04dd9b1680ae | 143 | uint32_t Break2Filter; /*!< TIM break2 input filter. |
| bogdanm | 86:04dd9b1680ae | 144 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| bogdanm | 86:04dd9b1680ae | 145 | uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state |
| bogdanm | 86:04dd9b1680ae | 146 | This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
| bogdanm | 86:04dd9b1680ae | 147 | } TIM_BreakDeadTimeConfigTypeDef; |
| bogdanm | 86:04dd9b1680ae | 148 | |
| bogdanm | 86:04dd9b1680ae | 149 | /** |
| bogdanm | 86:04dd9b1680ae | 150 | * @brief TIM Master configuration Structure definition |
| bogdanm | 86:04dd9b1680ae | 151 | * @note Advanced timers provide TRGO2 internal line which is redirected |
| bogdanm | 86:04dd9b1680ae | 152 | * to the ADC |
| bogdanm | 86:04dd9b1680ae | 153 | */ |
| bogdanm | 86:04dd9b1680ae | 154 | typedef struct { |
| bogdanm | 86:04dd9b1680ae | 155 | uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection |
| bogdanm | 86:04dd9b1680ae | 156 | This parameter can be a value of @ref TIM_Master_Mode_Selection */ |
| bogdanm | 86:04dd9b1680ae | 157 | uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection |
| bogdanm | 86:04dd9b1680ae | 158 | This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */ |
| bogdanm | 86:04dd9b1680ae | 159 | uint32_t MasterSlaveMode; /*!< Master/slave mode selection |
| bogdanm | 86:04dd9b1680ae | 160 | This parameter can be a value of @ref TIM_Master_Slave_Mode */ |
| bogdanm | 86:04dd9b1680ae | 161 | }TIM_MasterConfigTypeDef; |
| bogdanm | 86:04dd9b1680ae | 162 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ |
| bogdanm | 86:04dd9b1680ae | 163 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
| bogdanm | 86:04dd9b1680ae | 164 | /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
| bogdanm | 86:04dd9b1680ae | 165 | |
| bogdanm | 86:04dd9b1680ae | 166 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 86:04dd9b1680ae | 167 | /** @defgroup TIMEx_Exported_Constants |
| bogdanm | 86:04dd9b1680ae | 168 | * @{ |
| bogdanm | 86:04dd9b1680ae | 169 | */ |
| bogdanm | 86:04dd9b1680ae | 170 | |
| bogdanm | 86:04dd9b1680ae | 171 | #if defined(STM32F373xC) || defined(STM32F378xx) |
| bogdanm | 86:04dd9b1680ae | 172 | /** @defgroup TIMEx_Channel |
| bogdanm | 86:04dd9b1680ae | 173 | * @{ |
| bogdanm | 86:04dd9b1680ae | 174 | */ |
| bogdanm | 86:04dd9b1680ae | 175 | #define TIM_CHANNEL_1 ((uint32_t)0x0000) |
| bogdanm | 86:04dd9b1680ae | 176 | #define TIM_CHANNEL_2 ((uint32_t)0x0004) |
| bogdanm | 86:04dd9b1680ae | 177 | #define TIM_CHANNEL_3 ((uint32_t)0x0008) |
| bogdanm | 86:04dd9b1680ae | 178 | #define TIM_CHANNEL_4 ((uint32_t)0x000C) |
| bogdanm | 86:04dd9b1680ae | 179 | #define TIM_CHANNEL_ALL ((uint32_t)0x0018) |
| bogdanm | 86:04dd9b1680ae | 180 | |
| bogdanm | 86:04dd9b1680ae | 181 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| bogdanm | 86:04dd9b1680ae | 182 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| bogdanm | 86:04dd9b1680ae | 183 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| bogdanm | 86:04dd9b1680ae | 184 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
| bogdanm | 86:04dd9b1680ae | 185 | ((CHANNEL) == TIM_CHANNEL_ALL)) |
| bogdanm | 86:04dd9b1680ae | 186 | |
| bogdanm | 86:04dd9b1680ae | 187 | #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| bogdanm | 86:04dd9b1680ae | 188 | ((CHANNEL) == TIM_CHANNEL_2)) |
| bogdanm | 86:04dd9b1680ae | 189 | |
| bogdanm | 86:04dd9b1680ae | 190 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| bogdanm | 86:04dd9b1680ae | 191 | ((CHANNEL) == TIM_CHANNEL_2)) |
| bogdanm | 86:04dd9b1680ae | 192 | |
| bogdanm | 86:04dd9b1680ae | 193 | #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| bogdanm | 86:04dd9b1680ae | 194 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| bogdanm | 86:04dd9b1680ae | 195 | ((CHANNEL) == TIM_CHANNEL_3)) |
| bogdanm | 86:04dd9b1680ae | 196 | /** |
| bogdanm | 86:04dd9b1680ae | 197 | * @} |
| bogdanm | 86:04dd9b1680ae | 198 | */ |
| bogdanm | 86:04dd9b1680ae | 199 | |
| bogdanm | 86:04dd9b1680ae | 200 | /** @defgroup TIMEx_Output_Compare_and_PWM_modes |
| bogdanm | 86:04dd9b1680ae | 201 | * @{ |
| bogdanm | 86:04dd9b1680ae | 202 | */ |
| bogdanm | 86:04dd9b1680ae | 203 | |
| bogdanm | 86:04dd9b1680ae | 204 | #define TIM_OCMODE_TIMING ((uint32_t)0x0000) |
| bogdanm | 86:04dd9b1680ae | 205 | #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) |
| bogdanm | 86:04dd9b1680ae | 206 | #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) |
| bogdanm | 86:04dd9b1680ae | 207 | #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) |
| bogdanm | 86:04dd9b1680ae | 208 | #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
| bogdanm | 86:04dd9b1680ae | 209 | #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M) |
| bogdanm | 86:04dd9b1680ae | 210 | #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
| bogdanm | 86:04dd9b1680ae | 211 | #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) |
| bogdanm | 86:04dd9b1680ae | 212 | |
| bogdanm | 86:04dd9b1680ae | 213 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ |
| bogdanm | 86:04dd9b1680ae | 214 | ((MODE) == TIM_OCMODE_PWM2)) |
| bogdanm | 86:04dd9b1680ae | 215 | |
| bogdanm | 86:04dd9b1680ae | 216 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ |
| bogdanm | 86:04dd9b1680ae | 217 | ((MODE) == TIM_OCMODE_ACTIVE) || \ |
| bogdanm | 86:04dd9b1680ae | 218 | ((MODE) == TIM_OCMODE_INACTIVE) || \ |
| bogdanm | 86:04dd9b1680ae | 219 | ((MODE) == TIM_OCMODE_TOGGLE) || \ |
| bogdanm | 86:04dd9b1680ae | 220 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ |
| bogdanm | 86:04dd9b1680ae | 221 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) |
| bogdanm | 86:04dd9b1680ae | 222 | /** |
| bogdanm | 86:04dd9b1680ae | 223 | * @} |
| bogdanm | 86:04dd9b1680ae | 224 | */ |
| bogdanm | 86:04dd9b1680ae | 225 | |
| bogdanm | 86:04dd9b1680ae | 226 | /** @defgroup TIMEx_ClearInput_Source |
| bogdanm | 86:04dd9b1680ae | 227 | * @{ |
| bogdanm | 86:04dd9b1680ae | 228 | */ |
| bogdanm | 86:04dd9b1680ae | 229 | #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) |
| bogdanm | 86:04dd9b1680ae | 230 | #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) |
| bogdanm | 86:04dd9b1680ae | 231 | |
| bogdanm | 86:04dd9b1680ae | 232 | #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ |
| bogdanm | 86:04dd9b1680ae | 233 | ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) |
| bogdanm | 86:04dd9b1680ae | 234 | /** |
| bogdanm | 86:04dd9b1680ae | 235 | * @} |
| bogdanm | 86:04dd9b1680ae | 236 | */ |
| bogdanm | 86:04dd9b1680ae | 237 | |
| bogdanm | 86:04dd9b1680ae | 238 | /** @defgroup TIMEx_Slave_Mode |
| bogdanm | 86:04dd9b1680ae | 239 | * @{ |
| bogdanm | 86:04dd9b1680ae | 240 | */ |
| bogdanm | 86:04dd9b1680ae | 241 | |
| bogdanm | 86:04dd9b1680ae | 242 | #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) |
| bogdanm | 86:04dd9b1680ae | 243 | #define TIM_SLAVEMODE_RESET ((uint16_t)0x0004) |
| bogdanm | 86:04dd9b1680ae | 244 | #define TIM_SLAVEMODE_GATED ((uint16_t)0x0005) |
| bogdanm | 86:04dd9b1680ae | 245 | #define TIM_SLAVEMODE_TRIGGER ((uint16_t)0x0006) |
| bogdanm | 86:04dd9b1680ae | 246 | #define TIM_SLAVEMODE_EXTERNAL1 ((uint16_t)0x0007) |
| bogdanm | 86:04dd9b1680ae | 247 | |
| bogdanm | 86:04dd9b1680ae | 248 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ |
| bogdanm | 86:04dd9b1680ae | 249 | ((MODE) == TIM_SLAVEMODE_RESET) || \ |
| bogdanm | 86:04dd9b1680ae | 250 | ((MODE) == TIM_SLAVEMODE_GATED) || \ |
| bogdanm | 86:04dd9b1680ae | 251 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ |
| bogdanm | 86:04dd9b1680ae | 252 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) |
| bogdanm | 86:04dd9b1680ae | 253 | /** |
| bogdanm | 86:04dd9b1680ae | 254 | * @} |
| bogdanm | 86:04dd9b1680ae | 255 | */ |
| bogdanm | 86:04dd9b1680ae | 256 | |
| bogdanm | 86:04dd9b1680ae | 257 | /** @defgroup TIMEx_Event_Source |
| bogdanm | 86:04dd9b1680ae | 258 | * @{ |
| bogdanm | 86:04dd9b1680ae | 259 | */ |
| bogdanm | 86:04dd9b1680ae | 260 | |
| bogdanm | 86:04dd9b1680ae | 261 | #define TIM_EventSource_Update TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ |
| bogdanm | 86:04dd9b1680ae | 262 | #define TIM_EventSource_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ |
| bogdanm | 86:04dd9b1680ae | 263 | #define TIM_EventSource_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ |
| bogdanm | 86:04dd9b1680ae | 264 | #define TIM_EventSource_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ |
| bogdanm | 86:04dd9b1680ae | 265 | #define TIM_EventSource_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ |
| bogdanm | 86:04dd9b1680ae | 266 | #define TIM_EventSource_COM TIM_EGR_COMG /*!< A commutation event is generated */ |
| bogdanm | 86:04dd9b1680ae | 267 | #define TIM_EventSource_Trigger TIM_EGR_TG /*!< A trigger event is generated */ |
| bogdanm | 86:04dd9b1680ae | 268 | #define TIM_EventSource_Break TIM_EGR_BG /*!< A break event is generated */ |
| bogdanm | 86:04dd9b1680ae | 269 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) |
| bogdanm | 86:04dd9b1680ae | 270 | |
| bogdanm | 86:04dd9b1680ae | 271 | /** |
| bogdanm | 86:04dd9b1680ae | 272 | * @} |
| bogdanm | 86:04dd9b1680ae | 273 | */ |
| bogdanm | 86:04dd9b1680ae | 274 | |
| bogdanm | 86:04dd9b1680ae | 275 | /** @defgroup TIMEx_DMA_Base_address |
| bogdanm | 86:04dd9b1680ae | 276 | * @{ |
| bogdanm | 86:04dd9b1680ae | 277 | */ |
| bogdanm | 86:04dd9b1680ae | 278 | |
| bogdanm | 86:04dd9b1680ae | 279 | #define TIM_DMABase_CR1 (0x00000000) |
| bogdanm | 86:04dd9b1680ae | 280 | #define TIM_DMABase_CR2 (0x00000001) |
| bogdanm | 86:04dd9b1680ae | 281 | #define TIM_DMABase_SMCR (0x00000002) |
| bogdanm | 86:04dd9b1680ae | 282 | #define TIM_DMABase_DIER (0x00000003) |
| bogdanm | 86:04dd9b1680ae | 283 | #define TIM_DMABase_SR (0x00000004) |
| bogdanm | 86:04dd9b1680ae | 284 | #define TIM_DMABase_EGR (0x00000005) |
| bogdanm | 86:04dd9b1680ae | 285 | #define TIM_DMABase_CCMR1 (0x00000006) |
| bogdanm | 86:04dd9b1680ae | 286 | #define TIM_DMABase_CCMR2 (0x00000007) |
| bogdanm | 86:04dd9b1680ae | 287 | #define TIM_DMABase_CCER (0x00000008) |
| bogdanm | 86:04dd9b1680ae | 288 | #define TIM_DMABase_CNT (0x00000009) |
| bogdanm | 86:04dd9b1680ae | 289 | #define TIM_DMABase_PSC (0x0000000A) |
| bogdanm | 86:04dd9b1680ae | 290 | #define TIM_DMABase_ARR (0x0000000B) |
| bogdanm | 86:04dd9b1680ae | 291 | #define TIM_DMABase_RCR (0x0000000C) |
| bogdanm | 86:04dd9b1680ae | 292 | #define TIM_DMABase_CCR1 (0x0000000D) |
| bogdanm | 86:04dd9b1680ae | 293 | #define TIM_DMABase_CCR2 (0x0000000E) |
| bogdanm | 86:04dd9b1680ae | 294 | #define TIM_DMABase_CCR3 (0x0000000F) |
| bogdanm | 86:04dd9b1680ae | 295 | #define TIM_DMABase_CCR4 (0x00000010) |
| bogdanm | 86:04dd9b1680ae | 296 | #define TIM_DMABase_BDTR (0x00000011) |
| bogdanm | 86:04dd9b1680ae | 297 | #define TIM_DMABase_DCR (0x00000012) |
| bogdanm | 86:04dd9b1680ae | 298 | #define TIM_DMABase_OR (0x00000013) |
| bogdanm | 86:04dd9b1680ae | 299 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ |
| bogdanm | 86:04dd9b1680ae | 300 | ((BASE) == TIM_DMABase_CR2) || \ |
| bogdanm | 86:04dd9b1680ae | 301 | ((BASE) == TIM_DMABase_SMCR) || \ |
| bogdanm | 86:04dd9b1680ae | 302 | ((BASE) == TIM_DMABase_DIER) || \ |
| bogdanm | 86:04dd9b1680ae | 303 | ((BASE) == TIM_DMABase_SR) || \ |
| bogdanm | 86:04dd9b1680ae | 304 | ((BASE) == TIM_DMABase_EGR) || \ |
| bogdanm | 86:04dd9b1680ae | 305 | ((BASE) == TIM_DMABase_CCMR1) || \ |
| bogdanm | 86:04dd9b1680ae | 306 | ((BASE) == TIM_DMABase_CCMR2) || \ |
| bogdanm | 86:04dd9b1680ae | 307 | ((BASE) == TIM_DMABase_CCER) || \ |
| bogdanm | 86:04dd9b1680ae | 308 | ((BASE) == TIM_DMABase_CNT) || \ |
| bogdanm | 86:04dd9b1680ae | 309 | ((BASE) == TIM_DMABase_PSC) || \ |
| bogdanm | 86:04dd9b1680ae | 310 | ((BASE) == TIM_DMABase_ARR) || \ |
| bogdanm | 86:04dd9b1680ae | 311 | ((BASE) == TIM_DMABase_RCR) || \ |
| bogdanm | 86:04dd9b1680ae | 312 | ((BASE) == TIM_DMABase_CCR1) || \ |
| bogdanm | 86:04dd9b1680ae | 313 | ((BASE) == TIM_DMABase_CCR2) || \ |
| bogdanm | 86:04dd9b1680ae | 314 | ((BASE) == TIM_DMABase_CCR3) || \ |
| bogdanm | 86:04dd9b1680ae | 315 | ((BASE) == TIM_DMABase_CCR4) || \ |
| bogdanm | 86:04dd9b1680ae | 316 | ((BASE) == TIM_DMABase_BDTR) || \ |
| bogdanm | 86:04dd9b1680ae | 317 | ((BASE) == TIM_DMABase_DCR) || \ |
| bogdanm | 86:04dd9b1680ae | 318 | ((BASE) == TIM_DMABase_OR)) |
| bogdanm | 86:04dd9b1680ae | 319 | /** |
| bogdanm | 86:04dd9b1680ae | 320 | * @} |
| bogdanm | 86:04dd9b1680ae | 321 | */ |
| bogdanm | 86:04dd9b1680ae | 322 | #endif /* STM32F373xC || STM32F378xx */ |
| bogdanm | 86:04dd9b1680ae | 323 | |
| bogdanm | 86:04dd9b1680ae | 324 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
| bogdanm | 86:04dd9b1680ae | 325 | defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) || \ |
| bogdanm | 86:04dd9b1680ae | 326 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
| bogdanm | 86:04dd9b1680ae | 327 | /** @defgroup TIMEx_Channel |
| bogdanm | 86:04dd9b1680ae | 328 | * @{ |
| bogdanm | 86:04dd9b1680ae | 329 | */ |
| bogdanm | 86:04dd9b1680ae | 330 | |
| bogdanm | 86:04dd9b1680ae | 331 | #define TIM_CHANNEL_1 ((uint32_t)0x0000) |
| bogdanm | 86:04dd9b1680ae | 332 | #define TIM_CHANNEL_2 ((uint32_t)0x0004) |
| bogdanm | 86:04dd9b1680ae | 333 | #define TIM_CHANNEL_3 ((uint32_t)0x0008) |
| bogdanm | 86:04dd9b1680ae | 334 | #define TIM_CHANNEL_4 ((uint32_t)0x000C) |
| bogdanm | 86:04dd9b1680ae | 335 | #define TIM_CHANNEL_5 ((uint32_t)0x0010) |
| bogdanm | 86:04dd9b1680ae | 336 | #define TIM_CHANNEL_6 ((uint32_t)0x0014) |
| bogdanm | 86:04dd9b1680ae | 337 | #define TIM_CHANNEL_ALL ((uint32_t)0x003C) |
| bogdanm | 86:04dd9b1680ae | 338 | |
| bogdanm | 86:04dd9b1680ae | 339 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| bogdanm | 86:04dd9b1680ae | 340 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| bogdanm | 86:04dd9b1680ae | 341 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| bogdanm | 86:04dd9b1680ae | 342 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
| bogdanm | 86:04dd9b1680ae | 343 | ((CHANNEL) == TIM_CHANNEL_5) || \ |
| bogdanm | 86:04dd9b1680ae | 344 | ((CHANNEL) == TIM_CHANNEL_6) || \ |
| bogdanm | 86:04dd9b1680ae | 345 | ((CHANNEL) == TIM_CHANNEL_ALL)) |
| bogdanm | 86:04dd9b1680ae | 346 | |
| bogdanm | 86:04dd9b1680ae | 347 | #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| bogdanm | 86:04dd9b1680ae | 348 | ((CHANNEL) == TIM_CHANNEL_2)) |
| bogdanm | 86:04dd9b1680ae | 349 | |
| bogdanm | 86:04dd9b1680ae | 350 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| bogdanm | 86:04dd9b1680ae | 351 | ((CHANNEL) == TIM_CHANNEL_2)) |
| bogdanm | 86:04dd9b1680ae | 352 | |
| bogdanm | 86:04dd9b1680ae | 353 | #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| bogdanm | 86:04dd9b1680ae | 354 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| bogdanm | 86:04dd9b1680ae | 355 | ((CHANNEL) == TIM_CHANNEL_3)) |
| bogdanm | 86:04dd9b1680ae | 356 | /** |
| bogdanm | 86:04dd9b1680ae | 357 | * @} |
| bogdanm | 86:04dd9b1680ae | 358 | */ |
| bogdanm | 86:04dd9b1680ae | 359 | |
| bogdanm | 86:04dd9b1680ae | 360 | /** @defgroup TIMEx_Output_Compare_and_PWM_modes |
| bogdanm | 86:04dd9b1680ae | 361 | * @{ |
| bogdanm | 86:04dd9b1680ae | 362 | */ |
| bogdanm | 86:04dd9b1680ae | 363 | #define TIM_OCMODE_TIMING ((uint32_t)0x0000) |
| bogdanm | 86:04dd9b1680ae | 364 | #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) |
| bogdanm | 86:04dd9b1680ae | 365 | #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) |
| bogdanm | 86:04dd9b1680ae | 366 | #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
| bogdanm | 86:04dd9b1680ae | 367 | #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) |
| bogdanm | 86:04dd9b1680ae | 368 | #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
| bogdanm | 86:04dd9b1680ae | 369 | #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) |
| bogdanm | 86:04dd9b1680ae | 370 | #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) |
| bogdanm | 86:04dd9b1680ae | 371 | |
| bogdanm | 86:04dd9b1680ae | 372 | #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) |
| bogdanm | 86:04dd9b1680ae | 373 | #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) |
| bogdanm | 86:04dd9b1680ae | 374 | #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) |
| bogdanm | 86:04dd9b1680ae | 375 | #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
| bogdanm | 86:04dd9b1680ae | 376 | #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
| bogdanm | 86:04dd9b1680ae | 377 | #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) |
| bogdanm | 86:04dd9b1680ae | 378 | |
| bogdanm | 86:04dd9b1680ae | 379 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ |
| bogdanm | 86:04dd9b1680ae | 380 | ((MODE) == TIM_OCMODE_PWM2) || \ |
| bogdanm | 86:04dd9b1680ae | 381 | ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \ |
| bogdanm | 86:04dd9b1680ae | 382 | ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \ |
| bogdanm | 86:04dd9b1680ae | 383 | ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ |
| bogdanm | 86:04dd9b1680ae | 384 | ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2)) |
| bogdanm | 86:04dd9b1680ae | 385 | |
| bogdanm | 86:04dd9b1680ae | 386 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ |
| bogdanm | 86:04dd9b1680ae | 387 | ((MODE) == TIM_OCMODE_ACTIVE) || \ |
| bogdanm | 86:04dd9b1680ae | 388 | ((MODE) == TIM_OCMODE_INACTIVE) || \ |
| bogdanm | 86:04dd9b1680ae | 389 | ((MODE) == TIM_OCMODE_TOGGLE) || \ |
| bogdanm | 86:04dd9b1680ae | 390 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ |
| bogdanm | 86:04dd9b1680ae | 391 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \ |
| bogdanm | 86:04dd9b1680ae | 392 | ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ |
| bogdanm | 86:04dd9b1680ae | 393 | ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2)) |
| bogdanm | 86:04dd9b1680ae | 394 | /** |
| bogdanm | 86:04dd9b1680ae | 395 | * @} |
| bogdanm | 86:04dd9b1680ae | 396 | */ |
| bogdanm | 86:04dd9b1680ae | 397 | |
| bogdanm | 86:04dd9b1680ae | 398 | /** @defgroup TIMEx_ClearInput_Source |
| bogdanm | 86:04dd9b1680ae | 399 | * @{ |
| bogdanm | 86:04dd9b1680ae | 400 | */ |
| bogdanm | 86:04dd9b1680ae | 401 | #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) |
| bogdanm | 86:04dd9b1680ae | 402 | #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) |
| bogdanm | 86:04dd9b1680ae | 403 | #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) |
| bogdanm | 86:04dd9b1680ae | 404 | |
| bogdanm | 86:04dd9b1680ae | 405 | #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \ |
| bogdanm | 86:04dd9b1680ae | 406 | ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ |
| bogdanm | 86:04dd9b1680ae | 407 | ((MODE) == TIM_CLEARINPUTSOURCE_NONE)) |
| bogdanm | 86:04dd9b1680ae | 408 | /** |
| bogdanm | 86:04dd9b1680ae | 409 | * @} |
| bogdanm | 86:04dd9b1680ae | 410 | */ |
| bogdanm | 86:04dd9b1680ae | 411 | |
| bogdanm | 86:04dd9b1680ae | 412 | /** @defgroup TIMEx_BreakInput_Filter |
| bogdanm | 86:04dd9b1680ae | 413 | * @{ |
| bogdanm | 86:04dd9b1680ae | 414 | */ |
| bogdanm | 86:04dd9b1680ae | 415 | |
| bogdanm | 86:04dd9b1680ae | 416 | #define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xF) |
| bogdanm | 86:04dd9b1680ae | 417 | /** |
| bogdanm | 86:04dd9b1680ae | 418 | * @} |
| bogdanm | 86:04dd9b1680ae | 419 | */ |
| bogdanm | 86:04dd9b1680ae | 420 | |
| bogdanm | 86:04dd9b1680ae | 421 | /** @defgroup TIMEx_Break2_Input_enable_disable |
| bogdanm | 86:04dd9b1680ae | 422 | * @{ |
| bogdanm | 86:04dd9b1680ae | 423 | */ |
| bogdanm | 86:04dd9b1680ae | 424 | #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 86:04dd9b1680ae | 425 | #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) |
| bogdanm | 86:04dd9b1680ae | 426 | |
| bogdanm | 86:04dd9b1680ae | 427 | #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \ |
| bogdanm | 86:04dd9b1680ae | 428 | ((STATE) == TIM_BREAK2_DISABLE)) |
| bogdanm | 86:04dd9b1680ae | 429 | /** |
| bogdanm | 86:04dd9b1680ae | 430 | * @} |
| bogdanm | 86:04dd9b1680ae | 431 | */ |
| bogdanm | 86:04dd9b1680ae | 432 | /** @defgroup TIMEx_Break2_Polarity |
| bogdanm | 86:04dd9b1680ae | 433 | * @{ |
| bogdanm | 86:04dd9b1680ae | 434 | */ |
| bogdanm | 86:04dd9b1680ae | 435 | #define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000) |
| bogdanm | 86:04dd9b1680ae | 436 | #define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P) |
| bogdanm | 86:04dd9b1680ae | 437 | |
| bogdanm | 86:04dd9b1680ae | 438 | #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \ |
| bogdanm | 86:04dd9b1680ae | 439 | ((POLARITY) == TIM_BREAK2POLARITY_HIGH)) |
| bogdanm | 86:04dd9b1680ae | 440 | /** |
| bogdanm | 86:04dd9b1680ae | 441 | * @} |
| bogdanm | 86:04dd9b1680ae | 442 | */ |
| bogdanm | 86:04dd9b1680ae | 443 | |
| bogdanm | 86:04dd9b1680ae | 444 | /** @defgroup TIMEx_Master_Mode_Selection_2 |
| bogdanm | 86:04dd9b1680ae | 445 | * @{ |
| bogdanm | 86:04dd9b1680ae | 446 | */ |
| bogdanm | 86:04dd9b1680ae | 447 | #define TIM_TRGO2_RESET ((uint32_t)0x00000000) |
| bogdanm | 86:04dd9b1680ae | 448 | #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) |
| bogdanm | 86:04dd9b1680ae | 449 | #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) |
| bogdanm | 86:04dd9b1680ae | 450 | #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
| bogdanm | 86:04dd9b1680ae | 451 | #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) |
| bogdanm | 86:04dd9b1680ae | 452 | #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) |
| bogdanm | 86:04dd9b1680ae | 453 | #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) |
| bogdanm | 86:04dd9b1680ae | 454 | #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
| bogdanm | 86:04dd9b1680ae | 455 | #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) |
| bogdanm | 86:04dd9b1680ae | 456 | #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) |
| bogdanm | 86:04dd9b1680ae | 457 | #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) |
| bogdanm | 86:04dd9b1680ae | 458 | #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
| bogdanm | 86:04dd9b1680ae | 459 | #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) |
| bogdanm | 86:04dd9b1680ae | 460 | #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) |
| bogdanm | 86:04dd9b1680ae | 461 | #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) |
| bogdanm | 86:04dd9b1680ae | 462 | #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
| bogdanm | 86:04dd9b1680ae | 463 | |
| bogdanm | 86:04dd9b1680ae | 464 | #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \ |
| bogdanm | 86:04dd9b1680ae | 465 | ((SOURCE) == TIM_TRGO2_ENABLE) || \ |
| bogdanm | 86:04dd9b1680ae | 466 | ((SOURCE) == TIM_TRGO2_UPDATE) || \ |
| bogdanm | 86:04dd9b1680ae | 467 | ((SOURCE) == TIM_TRGO2_OC1) || \ |
| bogdanm | 86:04dd9b1680ae | 468 | ((SOURCE) == TIM_TRGO2_OC1REF) || \ |
| bogdanm | 86:04dd9b1680ae | 469 | ((SOURCE) == TIM_TRGO2_OC2REF) || \ |
| bogdanm | 86:04dd9b1680ae | 470 | ((SOURCE) == TIM_TRGO2_OC3REF) || \ |
| bogdanm | 86:04dd9b1680ae | 471 | ((SOURCE) == TIM_TRGO2_OC3REF) || \ |
| bogdanm | 86:04dd9b1680ae | 472 | ((SOURCE) == TIM_TRGO2_OC4REF) || \ |
| bogdanm | 86:04dd9b1680ae | 473 | ((SOURCE) == TIM_TRGO2_OC5REF) || \ |
| bogdanm | 86:04dd9b1680ae | 474 | ((SOURCE) == TIM_TRGO2_OC6REF) || \ |
| bogdanm | 86:04dd9b1680ae | 475 | ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ |
| bogdanm | 86:04dd9b1680ae | 476 | ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ |
| bogdanm | 86:04dd9b1680ae | 477 | ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ |
| bogdanm | 86:04dd9b1680ae | 478 | ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ |
| bogdanm | 86:04dd9b1680ae | 479 | ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ |
| bogdanm | 86:04dd9b1680ae | 480 | ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) |
| bogdanm | 86:04dd9b1680ae | 481 | /** |
| bogdanm | 86:04dd9b1680ae | 482 | * @} |
| bogdanm | 86:04dd9b1680ae | 483 | */ |
| bogdanm | 86:04dd9b1680ae | 484 | |
| bogdanm | 86:04dd9b1680ae | 485 | /** @defgroup TIMEx_Slave_Mode |
| bogdanm | 86:04dd9b1680ae | 486 | * @{ |
| bogdanm | 86:04dd9b1680ae | 487 | */ |
| bogdanm | 86:04dd9b1680ae | 488 | #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) |
| bogdanm | 86:04dd9b1680ae | 489 | #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) |
| bogdanm | 86:04dd9b1680ae | 490 | #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) |
| bogdanm | 86:04dd9b1680ae | 491 | #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) |
| bogdanm | 86:04dd9b1680ae | 492 | #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)) |
| bogdanm | 86:04dd9b1680ae | 493 | #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3)) |
| bogdanm | 86:04dd9b1680ae | 494 | |
| bogdanm | 86:04dd9b1680ae | 495 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ |
| bogdanm | 86:04dd9b1680ae | 496 | ((MODE) == TIM_SLAVEMODE_RESET) || \ |
| bogdanm | 86:04dd9b1680ae | 497 | ((MODE) == TIM_SLAVEMODE_GATED) || \ |
| bogdanm | 86:04dd9b1680ae | 498 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ |
| bogdanm | 86:04dd9b1680ae | 499 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \ |
| bogdanm | 86:04dd9b1680ae | 500 | ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) |
| bogdanm | 86:04dd9b1680ae | 501 | /** |
| bogdanm | 86:04dd9b1680ae | 502 | * @} |
| bogdanm | 86:04dd9b1680ae | 503 | */ |
| bogdanm | 86:04dd9b1680ae | 504 | |
| bogdanm | 86:04dd9b1680ae | 505 | /** @defgroup TIM_Event_Source |
| bogdanm | 86:04dd9b1680ae | 506 | * @{ |
| bogdanm | 86:04dd9b1680ae | 507 | */ |
| bogdanm | 86:04dd9b1680ae | 508 | |
| bogdanm | 86:04dd9b1680ae | 509 | #define TIM_EventSource_Update TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ |
| bogdanm | 86:04dd9b1680ae | 510 | #define TIM_EventSource_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ |
| bogdanm | 86:04dd9b1680ae | 511 | #define TIM_EventSource_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ |
| bogdanm | 86:04dd9b1680ae | 512 | #define TIM_EventSource_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ |
| bogdanm | 86:04dd9b1680ae | 513 | #define TIM_EventSource_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ |
| bogdanm | 86:04dd9b1680ae | 514 | #define TIM_EventSource_COM TIM_EGR_COMG /*!< A commutation event is generated */ |
| bogdanm | 86:04dd9b1680ae | 515 | #define TIM_EventSource_Trigger TIM_EGR_TG /*!< A trigger event is generated */ |
| bogdanm | 86:04dd9b1680ae | 516 | #define TIM_EventSource_Break TIM_EGR_BG /*!< A break event is generated */ |
| bogdanm | 86:04dd9b1680ae | 517 | #define TIM_EventSource_Break2 TIM_EGR_B2G /*!< A break 2 event is generated */ |
| bogdanm | 86:04dd9b1680ae | 518 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00) == 0x00000000) && ((SOURCE) != 0x00000000)) |
| bogdanm | 86:04dd9b1680ae | 519 | |
| bogdanm | 86:04dd9b1680ae | 520 | /** |
| bogdanm | 86:04dd9b1680ae | 521 | * @} |
| bogdanm | 86:04dd9b1680ae | 522 | */ |
| bogdanm | 86:04dd9b1680ae | 523 | |
| bogdanm | 86:04dd9b1680ae | 524 | /** @defgroup TIM_DMA_Base_address |
| bogdanm | 86:04dd9b1680ae | 525 | * @{ |
| bogdanm | 86:04dd9b1680ae | 526 | */ |
| bogdanm | 86:04dd9b1680ae | 527 | |
| bogdanm | 86:04dd9b1680ae | 528 | #define TIM_DMABase_CR1 (0x00000000) |
| bogdanm | 86:04dd9b1680ae | 529 | #define TIM_DMABase_CR2 (0x00000001) |
| bogdanm | 86:04dd9b1680ae | 530 | #define TIM_DMABase_SMCR (0x00000002) |
| bogdanm | 86:04dd9b1680ae | 531 | #define TIM_DMABase_DIER (0x00000003) |
| bogdanm | 86:04dd9b1680ae | 532 | #define TIM_DMABase_SR (0x00000004) |
| bogdanm | 86:04dd9b1680ae | 533 | #define TIM_DMABase_EGR (0x00000005) |
| bogdanm | 86:04dd9b1680ae | 534 | #define TIM_DMABase_CCMR1 (0x00000006) |
| bogdanm | 86:04dd9b1680ae | 535 | #define TIM_DMABase_CCMR2 (0x00000007) |
| bogdanm | 86:04dd9b1680ae | 536 | #define TIM_DMABase_CCER (0x00000008) |
| bogdanm | 86:04dd9b1680ae | 537 | #define TIM_DMABase_CNT (0x00000009) |
| bogdanm | 86:04dd9b1680ae | 538 | #define TIM_DMABase_PSC (0x0000000A) |
| bogdanm | 86:04dd9b1680ae | 539 | #define TIM_DMABase_ARR (0x0000000B) |
| bogdanm | 86:04dd9b1680ae | 540 | #define TIM_DMABase_RCR (0x0000000C) |
| bogdanm | 86:04dd9b1680ae | 541 | #define TIM_DMABase_CCR1 (0x0000000D) |
| bogdanm | 86:04dd9b1680ae | 542 | #define TIM_DMABase_CCR2 (0x0000000E) |
| bogdanm | 86:04dd9b1680ae | 543 | #define TIM_DMABase_CCR3 (0x0000000F) |
| bogdanm | 86:04dd9b1680ae | 544 | #define TIM_DMABase_CCR4 (0x00000010) |
| bogdanm | 86:04dd9b1680ae | 545 | #define TIM_DMABase_BDTR (0x00000011) |
| bogdanm | 86:04dd9b1680ae | 546 | #define TIM_DMABase_DCR (0x00000012) |
| bogdanm | 86:04dd9b1680ae | 547 | #define TIM_DMABase_CCMR3 (0x00000015) |
| bogdanm | 86:04dd9b1680ae | 548 | #define TIM_DMABase_CCR5 (0x00000016) |
| bogdanm | 86:04dd9b1680ae | 549 | #define TIM_DMABase_CCR6 (0x00000017) |
| bogdanm | 86:04dd9b1680ae | 550 | #define TIM_DMABase_OR (0x00000018) |
| bogdanm | 86:04dd9b1680ae | 551 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ |
| bogdanm | 86:04dd9b1680ae | 552 | ((BASE) == TIM_DMABase_CR2) || \ |
| bogdanm | 86:04dd9b1680ae | 553 | ((BASE) == TIM_DMABase_SMCR) || \ |
| bogdanm | 86:04dd9b1680ae | 554 | ((BASE) == TIM_DMABase_DIER) || \ |
| bogdanm | 86:04dd9b1680ae | 555 | ((BASE) == TIM_DMABase_SR) || \ |
| bogdanm | 86:04dd9b1680ae | 556 | ((BASE) == TIM_DMABase_EGR) || \ |
| bogdanm | 86:04dd9b1680ae | 557 | ((BASE) == TIM_DMABase_CCMR1) || \ |
| bogdanm | 86:04dd9b1680ae | 558 | ((BASE) == TIM_DMABase_CCMR2) || \ |
| bogdanm | 86:04dd9b1680ae | 559 | ((BASE) == TIM_DMABase_CCER) || \ |
| bogdanm | 86:04dd9b1680ae | 560 | ((BASE) == TIM_DMABase_CNT) || \ |
| bogdanm | 86:04dd9b1680ae | 561 | ((BASE) == TIM_DMABase_PSC) || \ |
| bogdanm | 86:04dd9b1680ae | 562 | ((BASE) == TIM_DMABase_ARR) || \ |
| bogdanm | 86:04dd9b1680ae | 563 | ((BASE) == TIM_DMABase_RCR) || \ |
| bogdanm | 86:04dd9b1680ae | 564 | ((BASE) == TIM_DMABase_CCR1) || \ |
| bogdanm | 86:04dd9b1680ae | 565 | ((BASE) == TIM_DMABase_CCR2) || \ |
| bogdanm | 86:04dd9b1680ae | 566 | ((BASE) == TIM_DMABase_CCR3) || \ |
| bogdanm | 86:04dd9b1680ae | 567 | ((BASE) == TIM_DMABase_CCR4) || \ |
| bogdanm | 86:04dd9b1680ae | 568 | ((BASE) == TIM_DMABase_BDTR) || \ |
| bogdanm | 86:04dd9b1680ae | 569 | ((BASE) == TIM_DMABase_CCMR3) || \ |
| bogdanm | 86:04dd9b1680ae | 570 | ((BASE) == TIM_DMABase_CCR5) || \ |
| bogdanm | 86:04dd9b1680ae | 571 | ((BASE) == TIM_DMABase_CCR6) || \ |
| bogdanm | 86:04dd9b1680ae | 572 | ((BASE) == TIM_DMABase_OR)) |
| bogdanm | 86:04dd9b1680ae | 573 | /** |
| bogdanm | 86:04dd9b1680ae | 574 | * @} |
| bogdanm | 86:04dd9b1680ae | 575 | */ |
| bogdanm | 86:04dd9b1680ae | 576 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ |
| bogdanm | 86:04dd9b1680ae | 577 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
| bogdanm | 86:04dd9b1680ae | 578 | /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
| bogdanm | 86:04dd9b1680ae | 579 | |
| bogdanm | 86:04dd9b1680ae | 580 | #if defined(STM32F302xC) |
| bogdanm | 86:04dd9b1680ae | 581 | /** @defgroup TIMEx_Remap |
| bogdanm | 86:04dd9b1680ae | 582 | * @{ |
| bogdanm | 86:04dd9b1680ae | 583 | */ |
| bogdanm | 86:04dd9b1680ae | 584 | #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
| bogdanm | 86:04dd9b1680ae | 585 | #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */ |
| bogdanm | 86:04dd9b1680ae | 586 | #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */ |
| bogdanm | 86:04dd9b1680ae | 587 | #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */ |
| bogdanm | 86:04dd9b1680ae | 588 | #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */ |
| bogdanm | 86:04dd9b1680ae | 589 | #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */ |
| bogdanm | 86:04dd9b1680ae | 590 | #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */ |
| bogdanm | 86:04dd9b1680ae | 591 | #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */ |
| bogdanm | 86:04dd9b1680ae | 592 | |
| bogdanm | 86:04dd9b1680ae | 593 | #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\ |
| bogdanm | 86:04dd9b1680ae | 594 | ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\ |
| bogdanm | 86:04dd9b1680ae | 595 | ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\ |
| bogdanm | 86:04dd9b1680ae | 596 | ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\ |
| bogdanm | 86:04dd9b1680ae | 597 | ((REMAP) == TIM_TIM16_GPIO) ||\ |
| bogdanm | 86:04dd9b1680ae | 598 | ((REMAP) == TIM_TIM16_RTC) ||\ |
| bogdanm | 86:04dd9b1680ae | 599 | ((REMAP) == TIM_TIM16_HSE) ||\ |
| bogdanm | 86:04dd9b1680ae | 600 | ((REMAP) == TIM_TIM16_MCO)) |
| bogdanm | 86:04dd9b1680ae | 601 | /** |
| bogdanm | 86:04dd9b1680ae | 602 | * @} |
| bogdanm | 86:04dd9b1680ae | 603 | */ |
| bogdanm | 86:04dd9b1680ae | 604 | #endif /* STM32F302xC */ |
| bogdanm | 86:04dd9b1680ae | 605 | |
| bogdanm | 86:04dd9b1680ae | 606 | #if defined(STM32F303xC) || defined(STM32F358xx) |
| bogdanm | 86:04dd9b1680ae | 607 | /** @defgroup TIMEx_Remap |
| bogdanm | 86:04dd9b1680ae | 608 | * @{ |
| bogdanm | 86:04dd9b1680ae | 609 | */ |
| bogdanm | 86:04dd9b1680ae | 610 | #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
| bogdanm | 86:04dd9b1680ae | 611 | #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */ |
| bogdanm | 86:04dd9b1680ae | 612 | #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */ |
| bogdanm | 86:04dd9b1680ae | 613 | #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */ |
| bogdanm | 86:04dd9b1680ae | 614 | #define TIM_TIM8_ADC2_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */ |
| bogdanm | 86:04dd9b1680ae | 615 | #define TIM_TIM8_ADC2_AWD1 (0x00000001) /* !< TIM8_ETR is connected to ADC2 AWD1 */ |
| bogdanm | 86:04dd9b1680ae | 616 | #define TIM_TIM8_ADC2_AWD2 (0x00000002) /* !< TIM8_ETR is connected to ADC2 AWD2 */ |
| bogdanm | 86:04dd9b1680ae | 617 | #define TIM_TIM8_ADC2_AWD3 (0x00000003) /* !< TIM8_ETR is connected to ADC2 AWD3 */ |
| bogdanm | 86:04dd9b1680ae | 618 | #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */ |
| bogdanm | 86:04dd9b1680ae | 619 | #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */ |
| bogdanm | 86:04dd9b1680ae | 620 | #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */ |
| bogdanm | 86:04dd9b1680ae | 621 | #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */ |
| bogdanm | 86:04dd9b1680ae | 622 | |
| bogdanm | 86:04dd9b1680ae | 623 | #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\ |
| bogdanm | 86:04dd9b1680ae | 624 | ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\ |
| bogdanm | 86:04dd9b1680ae | 625 | ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\ |
| bogdanm | 86:04dd9b1680ae | 626 | ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\ |
| bogdanm | 86:04dd9b1680ae | 627 | ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\ |
| bogdanm | 86:04dd9b1680ae | 628 | ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\ |
| bogdanm | 86:04dd9b1680ae | 629 | ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\ |
| bogdanm | 86:04dd9b1680ae | 630 | ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\ |
| bogdanm | 86:04dd9b1680ae | 631 | ((REMAP1) == TIM_TIM16_GPIO) ||\ |
| bogdanm | 86:04dd9b1680ae | 632 | ((REMAP1) == TIM_TIM16_RTC) ||\ |
| bogdanm | 86:04dd9b1680ae | 633 | ((REMAP1) == TIM_TIM16_HSE) ||\ |
| bogdanm | 86:04dd9b1680ae | 634 | ((REMAP1) == TIM_TIM16_MCO)) |
| bogdanm | 86:04dd9b1680ae | 635 | /** |
| bogdanm | 86:04dd9b1680ae | 636 | * @} |
| bogdanm | 86:04dd9b1680ae | 637 | */ |
| bogdanm | 86:04dd9b1680ae | 638 | |
| bogdanm | 86:04dd9b1680ae | 639 | /** @defgroup TIMEx_Remap2 |
| bogdanm | 86:04dd9b1680ae | 640 | * @{ |
| bogdanm | 86:04dd9b1680ae | 641 | */ |
| bogdanm | 86:04dd9b1680ae | 642 | #define TIM_TIM1_ADC4_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
| bogdanm | 86:04dd9b1680ae | 643 | #define TIM_TIM1_ADC4_AWD1 (0x00000004) /* !< TIM1_ETR is connected to ADC4 AWD1 */ |
| bogdanm | 86:04dd9b1680ae | 644 | #define TIM_TIM1_ADC4_AWD2 (0x00000008) /* !< TIM1_ETR is connected to ADC4 AWD2 */ |
| bogdanm | 86:04dd9b1680ae | 645 | #define TIM_TIM1_ADC4_AWD3 (0x0000000C) /* !< TIM1_ETR is connected to ADC4 AWD3 */ |
| bogdanm | 86:04dd9b1680ae | 646 | #define TIM_TIM8_ADC3_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */ |
| bogdanm | 86:04dd9b1680ae | 647 | #define TIM_TIM8_ADC3_AWD1 (0x00000004) /* !< TIM8_ETR is connected to ADC3 AWD1 */ |
| bogdanm | 86:04dd9b1680ae | 648 | #define TIM_TIM8_ADC3_AWD2 (0x00000008) /* !< TIM8_ETR is connected to ADC3 AWD2 */ |
| bogdanm | 86:04dd9b1680ae | 649 | #define TIM_TIM8_ADC3_AWD3 (0x0000000C) /* !< TIM8_ETR is connected to ADC3 AWD3 */ |
| bogdanm | 86:04dd9b1680ae | 650 | #define TIM_TIM16_NONE (0x00000000) /* !< Non significant value for TIM16 */ |
| bogdanm | 86:04dd9b1680ae | 651 | |
| bogdanm | 86:04dd9b1680ae | 652 | #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\ |
| bogdanm | 86:04dd9b1680ae | 653 | ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\ |
| bogdanm | 86:04dd9b1680ae | 654 | ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\ |
| bogdanm | 86:04dd9b1680ae | 655 | ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\ |
| bogdanm | 86:04dd9b1680ae | 656 | ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\ |
| bogdanm | 86:04dd9b1680ae | 657 | ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\ |
| bogdanm | 86:04dd9b1680ae | 658 | ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\ |
| bogdanm | 86:04dd9b1680ae | 659 | ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\ |
| bogdanm | 86:04dd9b1680ae | 660 | ((REMAP2) == TIM_TIM16_NONE)) |
| bogdanm | 86:04dd9b1680ae | 661 | /** |
| bogdanm | 86:04dd9b1680ae | 662 | * @} |
| bogdanm | 86:04dd9b1680ae | 663 | */ |
| bogdanm | 86:04dd9b1680ae | 664 | #endif /* STM32F303xC || STM32F358xx */ |
| bogdanm | 86:04dd9b1680ae | 665 | |
| bogdanm | 86:04dd9b1680ae | 666 | #if defined(STM32F373xC) || defined(STM32F378xx) |
| bogdanm | 86:04dd9b1680ae | 667 | /** @defgroup TIMEx_Remap |
| bogdanm | 86:04dd9b1680ae | 668 | * @{ |
| bogdanm | 86:04dd9b1680ae | 669 | */ |
| bogdanm | 86:04dd9b1680ae | 670 | |
| bogdanm | 86:04dd9b1680ae | 671 | #define TIM_TIM2_TIM8_TRGO (0x00000000) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */ |
| bogdanm | 86:04dd9b1680ae | 672 | #define TIM_TIM2_ETH_PTP (0x00000400) /*!< PTP trigger output is connected to TIM2_ITR1 */ |
| bogdanm | 86:04dd9b1680ae | 673 | #define TIM_TIM2_USBFS_SOF (0x00000800) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */ |
| bogdanm | 86:04dd9b1680ae | 674 | #define TIM_TIM2_USBHS_SOF (0x00000C00) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */ |
| bogdanm | 86:04dd9b1680ae | 675 | #define TIM_TIM14_GPIO (0x00000000) /* !< TIM14 TI1 is connected to GPIO */ |
| bogdanm | 86:04dd9b1680ae | 676 | #define TIM_TIM14_RTC (0x00000001) /* !< TIM14 TI1 is connected to RTC_clock */ |
| bogdanm | 86:04dd9b1680ae | 677 | #define TIM_TIM14_HSE (0x00000002) /* !< TIM14 TI1 is connected to HSE/32 */ |
| bogdanm | 86:04dd9b1680ae | 678 | #define TIM_TIM14_MCO (0x00000003) /* !< TIM14 TI1 is connected to MCO */ |
| bogdanm | 86:04dd9b1680ae | 679 | |
| bogdanm | 86:04dd9b1680ae | 680 | #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) ||\ |
| bogdanm | 86:04dd9b1680ae | 681 | ((REMAP) == TIM_TIM2_ETH_PTP) ||\ |
| bogdanm | 86:04dd9b1680ae | 682 | ((REMAP) == TIM_TIM2_USBFS_SOF) ||\ |
| bogdanm | 86:04dd9b1680ae | 683 | ((REMAP) == TIM_TIM2_USBHS_SOF) ||\ |
| bogdanm | 86:04dd9b1680ae | 684 | ((REMAP) == TIM_TIM14_GPIO) ||\ |
| bogdanm | 86:04dd9b1680ae | 685 | ((REMAP) == TIM_TIM14_RTC) ||\ |
| bogdanm | 86:04dd9b1680ae | 686 | ((REMAP) == TIM_TIM14_HSE) ||\ |
| bogdanm | 86:04dd9b1680ae | 687 | ((REMAP) == TIM_TIM14_MCO)) |
| bogdanm | 86:04dd9b1680ae | 688 | |
| bogdanm | 86:04dd9b1680ae | 689 | /** |
| bogdanm | 86:04dd9b1680ae | 690 | * @} |
| bogdanm | 86:04dd9b1680ae | 691 | */ |
| bogdanm | 86:04dd9b1680ae | 692 | #endif /* STM32F373xC || STM32F378xx */ |
| bogdanm | 86:04dd9b1680ae | 693 | |
| bogdanm | 86:04dd9b1680ae | 694 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
| bogdanm | 86:04dd9b1680ae | 695 | /** @defgroup TIMEx_Remap |
| bogdanm | 86:04dd9b1680ae | 696 | * @{ |
| bogdanm | 86:04dd9b1680ae | 697 | */ |
| bogdanm | 86:04dd9b1680ae | 698 | #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
| bogdanm | 86:04dd9b1680ae | 699 | #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */ |
| bogdanm | 86:04dd9b1680ae | 700 | #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */ |
| bogdanm | 86:04dd9b1680ae | 701 | #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */ |
| bogdanm | 86:04dd9b1680ae | 702 | #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */ |
| bogdanm | 86:04dd9b1680ae | 703 | #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */ |
| bogdanm | 86:04dd9b1680ae | 704 | #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */ |
| bogdanm | 86:04dd9b1680ae | 705 | #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */ |
| bogdanm | 86:04dd9b1680ae | 706 | |
| bogdanm | 86:04dd9b1680ae | 707 | #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\ |
| bogdanm | 86:04dd9b1680ae | 708 | ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\ |
| bogdanm | 86:04dd9b1680ae | 709 | ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\ |
| bogdanm | 86:04dd9b1680ae | 710 | ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\ |
| bogdanm | 86:04dd9b1680ae | 711 | ((REMAP) == TIM_TIM16_GPIO) ||\ |
| bogdanm | 86:04dd9b1680ae | 712 | ((REMAP) == TIM_TIM16_RTC) ||\ |
| bogdanm | 86:04dd9b1680ae | 713 | ((REMAP) == TIM_TIM16_HSE) ||\ |
| bogdanm | 86:04dd9b1680ae | 714 | ((REMAP) == TIM_TIM16_MCO)) |
| bogdanm | 86:04dd9b1680ae | 715 | /** |
| bogdanm | 86:04dd9b1680ae | 716 | * @} |
| bogdanm | 86:04dd9b1680ae | 717 | */ |
| bogdanm | 86:04dd9b1680ae | 718 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
| bogdanm | 86:04dd9b1680ae | 719 | |
| bogdanm | 86:04dd9b1680ae | 720 | #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
| bogdanm | 86:04dd9b1680ae | 721 | /** @defgroup TIMEx_Remap |
| bogdanm | 86:04dd9b1680ae | 722 | * @{ |
| bogdanm | 86:04dd9b1680ae | 723 | */ |
| bogdanm | 86:04dd9b1680ae | 724 | #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
| bogdanm | 86:04dd9b1680ae | 725 | #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */ |
| bogdanm | 86:04dd9b1680ae | 726 | #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */ |
| bogdanm | 86:04dd9b1680ae | 727 | #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */ |
| bogdanm | 86:04dd9b1680ae | 728 | |
| bogdanm | 86:04dd9b1680ae | 729 | #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\ |
| bogdanm | 86:04dd9b1680ae | 730 | ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\ |
| bogdanm | 86:04dd9b1680ae | 731 | ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\ |
| bogdanm | 86:04dd9b1680ae | 732 | ((REMAP) == TIM_TIM1_ADC1_AWD3)) |
| bogdanm | 86:04dd9b1680ae | 733 | /** |
| bogdanm | 86:04dd9b1680ae | 734 | * @} |
| bogdanm | 86:04dd9b1680ae | 735 | */ |
| bogdanm | 86:04dd9b1680ae | 736 | #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
| bogdanm | 86:04dd9b1680ae | 737 | |
| bogdanm | 86:04dd9b1680ae | 738 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
| bogdanm | 86:04dd9b1680ae | 739 | defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) || \ |
| bogdanm | 86:04dd9b1680ae | 740 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
| bogdanm | 86:04dd9b1680ae | 741 | /** @defgroup TIMEx_Group_Channel5 |
| bogdanm | 86:04dd9b1680ae | 742 | * @{ |
| bogdanm | 86:04dd9b1680ae | 743 | */ |
| bogdanm | 86:04dd9b1680ae | 744 | #define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ |
| bogdanm | 86:04dd9b1680ae | 745 | #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ |
| bogdanm | 86:04dd9b1680ae | 746 | #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ |
| bogdanm | 86:04dd9b1680ae | 747 | #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ |
| bogdanm | 86:04dd9b1680ae | 748 | |
| bogdanm | 86:04dd9b1680ae | 749 | #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000)) |
| bogdanm | 86:04dd9b1680ae | 750 | /** |
| bogdanm | 86:04dd9b1680ae | 751 | * @} |
| bogdanm | 86:04dd9b1680ae | 752 | */ |
| bogdanm | 86:04dd9b1680ae | 753 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ |
| bogdanm | 86:04dd9b1680ae | 754 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
| bogdanm | 86:04dd9b1680ae | 755 | /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
| bogdanm | 86:04dd9b1680ae | 756 | /** |
| bogdanm | 86:04dd9b1680ae | 757 | * @} |
| bogdanm | 86:04dd9b1680ae | 758 | */ |
| bogdanm | 86:04dd9b1680ae | 759 | |
| bogdanm | 86:04dd9b1680ae | 760 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 86:04dd9b1680ae | 761 | #if defined(STM32F373xC) || defined(STM32F378xx) |
| bogdanm | 86:04dd9b1680ae | 762 | /** |
| bogdanm | 86:04dd9b1680ae | 763 | * @brief Sets the TIM Capture Compare Register value on runtime without |
| bogdanm | 86:04dd9b1680ae | 764 | * calling another time ConfigChannel function. |
| bogdanm | 86:04dd9b1680ae | 765 | * @param __HANDLE__: TIM handle. |
| bogdanm | 86:04dd9b1680ae | 766 | * @param __CHANNEL__ : TIM Channels to be configured. |
| bogdanm | 86:04dd9b1680ae | 767 | * This parameter can be one of the following values: |
| bogdanm | 86:04dd9b1680ae | 768 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| bogdanm | 86:04dd9b1680ae | 769 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| bogdanm | 86:04dd9b1680ae | 770 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| bogdanm | 86:04dd9b1680ae | 771 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| bogdanm | 86:04dd9b1680ae | 772 | * @param __COMPARE__: specifies the Capture Compare register new value. |
| bogdanm | 86:04dd9b1680ae | 773 | * @retval None |
| bogdanm | 86:04dd9b1680ae | 774 | */ |
| bogdanm | 86:04dd9b1680ae | 775 | #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
| bogdanm | 86:04dd9b1680ae | 776 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) |
| bogdanm | 86:04dd9b1680ae | 777 | |
| bogdanm | 86:04dd9b1680ae | 778 | /** |
| bogdanm | 86:04dd9b1680ae | 779 | * @brief Gets the TIM Capture Compare Register value on runtime |
| bogdanm | 86:04dd9b1680ae | 780 | * @param __HANDLE__: TIM handle. |
| bogdanm | 86:04dd9b1680ae | 781 | * @param __CHANNEL__ : TIM Channel associated with the capture compare register |
| bogdanm | 86:04dd9b1680ae | 782 | * This parameter can be one of the following values: |
| bogdanm | 86:04dd9b1680ae | 783 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
| bogdanm | 86:04dd9b1680ae | 784 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
| bogdanm | 86:04dd9b1680ae | 785 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
| bogdanm | 86:04dd9b1680ae | 786 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
| bogdanm | 86:04dd9b1680ae | 787 | * @retval None |
| bogdanm | 86:04dd9b1680ae | 788 | */ |
| bogdanm | 86:04dd9b1680ae | 789 | #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ |
| bogdanm | 86:04dd9b1680ae | 790 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) |
| bogdanm | 86:04dd9b1680ae | 791 | #endif /* STM32F373xC || STM32F378xx */ |
| bogdanm | 86:04dd9b1680ae | 792 | |
| bogdanm | 86:04dd9b1680ae | 793 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
| bogdanm | 86:04dd9b1680ae | 794 | defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) || \ |
| bogdanm | 86:04dd9b1680ae | 795 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
| bogdanm | 86:04dd9b1680ae | 796 | /** |
| bogdanm | 86:04dd9b1680ae | 797 | * @brief Sets the TIM Capture Compare Register value on runtime without |
| bogdanm | 86:04dd9b1680ae | 798 | * calling another time ConfigChannel function. |
| bogdanm | 86:04dd9b1680ae | 799 | * @param __HANDLE__: TIM handle. |
| bogdanm | 86:04dd9b1680ae | 800 | * @param __CHANNEL__ : TIM Channels to be configured. |
| bogdanm | 86:04dd9b1680ae | 801 | * This parameter can be one of the following values: |
| bogdanm | 86:04dd9b1680ae | 802 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| bogdanm | 86:04dd9b1680ae | 803 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| bogdanm | 86:04dd9b1680ae | 804 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| bogdanm | 86:04dd9b1680ae | 805 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| bogdanm | 86:04dd9b1680ae | 806 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
| bogdanm | 86:04dd9b1680ae | 807 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
| bogdanm | 86:04dd9b1680ae | 808 | * @param __COMPARE__: specifies the Capture Compare register new value. |
| bogdanm | 86:04dd9b1680ae | 809 | * @retval None |
| bogdanm | 86:04dd9b1680ae | 810 | */ |
| bogdanm | 86:04dd9b1680ae | 811 | #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
| bogdanm | 86:04dd9b1680ae | 812 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ |
| bogdanm | 86:04dd9b1680ae | 813 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ |
| bogdanm | 86:04dd9b1680ae | 814 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ |
| bogdanm | 86:04dd9b1680ae | 815 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ |
| bogdanm | 86:04dd9b1680ae | 816 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ |
| bogdanm | 86:04dd9b1680ae | 817 | ((__HANDLE__)->Instance->CCR6 |= (__COMPARE__))) |
| bogdanm | 86:04dd9b1680ae | 818 | |
| bogdanm | 86:04dd9b1680ae | 819 | /** |
| bogdanm | 86:04dd9b1680ae | 820 | * @brief Gets the TIM Capture Compare Register value on runtime |
| bogdanm | 86:04dd9b1680ae | 821 | * @param __HANDLE__: TIM handle. |
| bogdanm | 86:04dd9b1680ae | 822 | * @param __CHANNEL__ : TIM Channel associated with the capture compare register |
| bogdanm | 86:04dd9b1680ae | 823 | * This parameter can be one of the following values: |
| bogdanm | 86:04dd9b1680ae | 824 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
| bogdanm | 86:04dd9b1680ae | 825 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
| bogdanm | 86:04dd9b1680ae | 826 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
| bogdanm | 86:04dd9b1680ae | 827 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
| bogdanm | 86:04dd9b1680ae | 828 | * @arg TIM_CHANNEL_5: get capture/compare 5 register value |
| bogdanm | 86:04dd9b1680ae | 829 | * @arg TIM_CHANNEL_6: get capture/compare 6 register value |
| bogdanm | 86:04dd9b1680ae | 830 | * @retval None |
| bogdanm | 86:04dd9b1680ae | 831 | */ |
| bogdanm | 86:04dd9b1680ae | 832 | #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ |
| bogdanm | 86:04dd9b1680ae | 833 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ |
| bogdanm | 86:04dd9b1680ae | 834 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ |
| bogdanm | 86:04dd9b1680ae | 835 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ |
| bogdanm | 86:04dd9b1680ae | 836 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ |
| bogdanm | 86:04dd9b1680ae | 837 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ |
| bogdanm | 86:04dd9b1680ae | 838 | ((__HANDLE__)->Instance->CCR6)) |
| bogdanm | 86:04dd9b1680ae | 839 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ |
| bogdanm | 86:04dd9b1680ae | 840 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
| bogdanm | 86:04dd9b1680ae | 841 | /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
| bogdanm | 86:04dd9b1680ae | 842 | |
| bogdanm | 86:04dd9b1680ae | 843 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 86:04dd9b1680ae | 844 | |
| bogdanm | 86:04dd9b1680ae | 845 | /* Timer Hall Sensor functions **********************************************/ |
| bogdanm | 86:04dd9b1680ae | 846 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); |
| bogdanm | 86:04dd9b1680ae | 847 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); |
| bogdanm | 86:04dd9b1680ae | 848 | |
| bogdanm | 86:04dd9b1680ae | 849 | void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); |
| bogdanm | 86:04dd9b1680ae | 850 | void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); |
| bogdanm | 86:04dd9b1680ae | 851 | |
| bogdanm | 86:04dd9b1680ae | 852 | /* Blocking mode: Polling */ |
| bogdanm | 86:04dd9b1680ae | 853 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); |
| bogdanm | 86:04dd9b1680ae | 854 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); |
| bogdanm | 86:04dd9b1680ae | 855 | /* Non-Blocking mode: Interrupt */ |
| bogdanm | 86:04dd9b1680ae | 856 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); |
| bogdanm | 86:04dd9b1680ae | 857 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); |
| bogdanm | 86:04dd9b1680ae | 858 | /* Non-Blocking mode: DMA */ |
| bogdanm | 86:04dd9b1680ae | 859 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
| bogdanm | 86:04dd9b1680ae | 860 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); |
| bogdanm | 86:04dd9b1680ae | 861 | |
| bogdanm | 86:04dd9b1680ae | 862 | /* Timer Complementary Output Compare functions *****************************/ |
| bogdanm | 86:04dd9b1680ae | 863 | /* Blocking mode: Polling */ |
| bogdanm | 86:04dd9b1680ae | 864 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| bogdanm | 86:04dd9b1680ae | 865 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| bogdanm | 86:04dd9b1680ae | 866 | |
| bogdanm | 86:04dd9b1680ae | 867 | /* Non-Blocking mode: Interrupt */ |
| bogdanm | 86:04dd9b1680ae | 868 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| bogdanm | 86:04dd9b1680ae | 869 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| bogdanm | 86:04dd9b1680ae | 870 | |
| bogdanm | 86:04dd9b1680ae | 871 | /* Non-Blocking mode: DMA */ |
| bogdanm | 86:04dd9b1680ae | 872 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
| bogdanm | 86:04dd9b1680ae | 873 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| bogdanm | 86:04dd9b1680ae | 874 | |
| bogdanm | 86:04dd9b1680ae | 875 | /* Timer Complementary PWM functions ****************************************/ |
| bogdanm | 86:04dd9b1680ae | 876 | /* Blocking mode: Polling */ |
| bogdanm | 86:04dd9b1680ae | 877 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| bogdanm | 86:04dd9b1680ae | 878 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| bogdanm | 86:04dd9b1680ae | 879 | |
| bogdanm | 86:04dd9b1680ae | 880 | /* Non-Blocking mode: Interrupt */ |
| bogdanm | 86:04dd9b1680ae | 881 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| bogdanm | 86:04dd9b1680ae | 882 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| bogdanm | 86:04dd9b1680ae | 883 | /* Non-Blocking mode: DMA */ |
| bogdanm | 86:04dd9b1680ae | 884 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
| bogdanm | 86:04dd9b1680ae | 885 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| bogdanm | 86:04dd9b1680ae | 886 | |
| bogdanm | 86:04dd9b1680ae | 887 | /* Timer Complementary One Pulse functions **********************************/ |
| bogdanm | 86:04dd9b1680ae | 888 | /* Blocking mode: Polling */ |
| bogdanm | 86:04dd9b1680ae | 889 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| bogdanm | 86:04dd9b1680ae | 890 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| bogdanm | 86:04dd9b1680ae | 891 | |
| bogdanm | 86:04dd9b1680ae | 892 | /* Non-Blocking mode: Interrupt */ |
| bogdanm | 86:04dd9b1680ae | 893 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| bogdanm | 86:04dd9b1680ae | 894 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| bogdanm | 86:04dd9b1680ae | 895 | |
| bogdanm | 86:04dd9b1680ae | 896 | /* Extnsion Control functions ************************************************/ |
| bogdanm | 86:04dd9b1680ae | 897 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| bogdanm | 86:04dd9b1680ae | 898 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| bogdanm | 86:04dd9b1680ae | 899 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| bogdanm | 86:04dd9b1680ae | 900 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); |
| bogdanm | 86:04dd9b1680ae | 901 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); |
| bogdanm | 86:04dd9b1680ae | 902 | |
| bogdanm | 86:04dd9b1680ae | 903 | #if defined(STM32F303xC) || defined(STM32F358xx) |
| bogdanm | 86:04dd9b1680ae | 904 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2); |
| bogdanm | 86:04dd9b1680ae | 905 | #endif /* STM32F303xC || STM32F358xx */ |
| bogdanm | 86:04dd9b1680ae | 906 | |
| bogdanm | 86:04dd9b1680ae | 907 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
| bogdanm | 86:04dd9b1680ae | 908 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
| bogdanm | 86:04dd9b1680ae | 909 | defined(STM32F373xC) || defined(STM32F378xx) |
| bogdanm | 86:04dd9b1680ae | 910 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); |
| bogdanm | 86:04dd9b1680ae | 911 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ |
| bogdanm | 86:04dd9b1680ae | 912 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
| bogdanm | 86:04dd9b1680ae | 913 | /* STM32F373xC || STM32F378xx */ |
| bogdanm | 86:04dd9b1680ae | 914 | |
| bogdanm | 86:04dd9b1680ae | 915 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
| bogdanm | 86:04dd9b1680ae | 916 | defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) || \ |
| bogdanm | 86:04dd9b1680ae | 917 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
| bogdanm | 86:04dd9b1680ae | 918 | HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); |
| bogdanm | 86:04dd9b1680ae | 919 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ |
| bogdanm | 86:04dd9b1680ae | 920 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
| bogdanm | 86:04dd9b1680ae | 921 | /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
| bogdanm | 86:04dd9b1680ae | 922 | |
| bogdanm | 86:04dd9b1680ae | 923 | |
| bogdanm | 86:04dd9b1680ae | 924 | /* Extension Callback *********************************************************/ |
| bogdanm | 86:04dd9b1680ae | 925 | void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); |
| bogdanm | 86:04dd9b1680ae | 926 | void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); |
| bogdanm | 86:04dd9b1680ae | 927 | void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); |
| bogdanm | 86:04dd9b1680ae | 928 | |
| bogdanm | 86:04dd9b1680ae | 929 | /* Extension Peripheral State functions **************************************/ |
| bogdanm | 86:04dd9b1680ae | 930 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); |
| bogdanm | 86:04dd9b1680ae | 931 | |
| bogdanm | 86:04dd9b1680ae | 932 | /** |
| bogdanm | 86:04dd9b1680ae | 933 | * @} |
| bogdanm | 86:04dd9b1680ae | 934 | */ |
| bogdanm | 86:04dd9b1680ae | 935 | |
| bogdanm | 86:04dd9b1680ae | 936 | /** |
| bogdanm | 86:04dd9b1680ae | 937 | * @} |
| bogdanm | 86:04dd9b1680ae | 938 | */ |
| bogdanm | 86:04dd9b1680ae | 939 | |
| bogdanm | 86:04dd9b1680ae | 940 | #ifdef __cplusplus |
| bogdanm | 86:04dd9b1680ae | 941 | } |
| bogdanm | 86:04dd9b1680ae | 942 | #endif |
| bogdanm | 86:04dd9b1680ae | 943 | |
| bogdanm | 86:04dd9b1680ae | 944 | |
| bogdanm | 86:04dd9b1680ae | 945 | #endif /* __STM32F3xx_HAL_TIM_EX_H */ |
| bogdanm | 86:04dd9b1680ae | 946 | |
| bogdanm | 86:04dd9b1680ae | 947 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |