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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_uart.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
92:4fc01daae5a5
Child:
99:dbbf35b96557
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_uart.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of UART HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_UART_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_UART_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup UART
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 /**
bogdanm 92:4fc01daae5a5 60 * @brief UART Init Structure definition
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62 typedef struct
bogdanm 92:4fc01daae5a5 63 {
bogdanm 92:4fc01daae5a5 64 uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
bogdanm 92:4fc01daae5a5 65 The baud rate is computed using the following formula:
bogdanm 92:4fc01daae5a5 66 - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
bogdanm 92:4fc01daae5a5 67 - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
bogdanm 92:4fc01daae5a5 68 Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
bogdanm 92:4fc01daae5a5 71 This parameter can be a value of @ref UART_Word_Length */
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
bogdanm 92:4fc01daae5a5 74 This parameter can be a value of @ref UART_Stop_Bits */
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76 uint32_t Parity; /*!< Specifies the parity mode.
bogdanm 92:4fc01daae5a5 77 This parameter can be a value of @ref UART_Parity
bogdanm 92:4fc01daae5a5 78 @note When parity is enabled, the computed parity is inserted
bogdanm 92:4fc01daae5a5 79 at the MSB position of the transmitted data (9th bit when
bogdanm 92:4fc01daae5a5 80 the word length is set to 9 data bits; 8th bit when the
bogdanm 92:4fc01daae5a5 81 word length is set to 8 data bits). */
bogdanm 92:4fc01daae5a5 82
bogdanm 92:4fc01daae5a5 83 uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
bogdanm 92:4fc01daae5a5 84 This parameter can be a value of @ref UART_Mode */
bogdanm 92:4fc01daae5a5 85
bogdanm 92:4fc01daae5a5 86 uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled
bogdanm 92:4fc01daae5a5 87 or disabled.
bogdanm 92:4fc01daae5a5 88 This parameter can be a value of @ref UART_Hardware_Flow_Control */
bogdanm 92:4fc01daae5a5 89
bogdanm 92:4fc01daae5a5 90 uint32_t OverSampling; /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
bogdanm 92:4fc01daae5a5 91 This parameter can be a value of @ref UART_Over_Sampling */
bogdanm 92:4fc01daae5a5 92 }UART_InitTypeDef;
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 /**
bogdanm 92:4fc01daae5a5 95 * @brief HAL UART State structures definition
bogdanm 92:4fc01daae5a5 96 */
bogdanm 92:4fc01daae5a5 97 typedef enum
bogdanm 92:4fc01daae5a5 98 {
bogdanm 92:4fc01daae5a5 99 HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
bogdanm 92:4fc01daae5a5 100 HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 92:4fc01daae5a5 101 HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
bogdanm 92:4fc01daae5a5 102 HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 92:4fc01daae5a5 103 HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 92:4fc01daae5a5 104 HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
bogdanm 92:4fc01daae5a5 105 HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 92:4fc01daae5a5 106 HAL_UART_STATE_ERROR = 0x04 /*!< Error */
bogdanm 92:4fc01daae5a5 107 }HAL_UART_StateTypeDef;
bogdanm 92:4fc01daae5a5 108
bogdanm 92:4fc01daae5a5 109 /**
bogdanm 92:4fc01daae5a5 110 * @brief HAL UART Error Code structure definition
bogdanm 92:4fc01daae5a5 111 */
bogdanm 92:4fc01daae5a5 112 typedef enum
bogdanm 92:4fc01daae5a5 113 {
bogdanm 92:4fc01daae5a5 114 HAL_UART_ERROR_NONE = 0x00, /*!< No error */
bogdanm 92:4fc01daae5a5 115 HAL_UART_ERROR_PE = 0x01, /*!< Parity error */
bogdanm 92:4fc01daae5a5 116 HAL_UART_ERROR_NE = 0x02, /*!< Noise error */
bogdanm 92:4fc01daae5a5 117 HAL_UART_ERROR_FE = 0x04, /*!< frame error */
bogdanm 92:4fc01daae5a5 118 HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */
bogdanm 92:4fc01daae5a5 119 HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */
bogdanm 92:4fc01daae5a5 120 }HAL_UART_ErrorTypeDef;
bogdanm 92:4fc01daae5a5 121
bogdanm 92:4fc01daae5a5 122 /**
bogdanm 92:4fc01daae5a5 123 * @brief UART handle Structure definition
bogdanm 92:4fc01daae5a5 124 */
bogdanm 92:4fc01daae5a5 125 typedef struct
bogdanm 92:4fc01daae5a5 126 {
bogdanm 92:4fc01daae5a5 127 USART_TypeDef *Instance; /* UART registers base address */
bogdanm 92:4fc01daae5a5 128
bogdanm 92:4fc01daae5a5 129 UART_InitTypeDef Init; /* UART communication parameters */
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */
bogdanm 92:4fc01daae5a5 132
bogdanm 92:4fc01daae5a5 133 uint16_t TxXferSize; /* UART Tx Transfer size */
bogdanm 92:4fc01daae5a5 134
bogdanm 92:4fc01daae5a5 135 uint16_t TxXferCount; /* UART Tx Transfer Counter */
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */
bogdanm 92:4fc01daae5a5 138
bogdanm 92:4fc01daae5a5 139 uint16_t RxXferSize; /* UART Rx Transfer size */
bogdanm 92:4fc01daae5a5 140
bogdanm 92:4fc01daae5a5 141 uint16_t RxXferCount; /* UART Rx Transfer Counter */
bogdanm 92:4fc01daae5a5 142
bogdanm 92:4fc01daae5a5 143 DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */
bogdanm 92:4fc01daae5a5 144
bogdanm 92:4fc01daae5a5 145 DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147 HAL_LockTypeDef Lock; /* Locking object */
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 __IO HAL_UART_StateTypeDef State; /* UART communication state */
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151 __IO HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */
bogdanm 92:4fc01daae5a5 152
bogdanm 92:4fc01daae5a5 153 }UART_HandleTypeDef;
bogdanm 92:4fc01daae5a5 154
bogdanm 92:4fc01daae5a5 155 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 156 /** @defgroup UART_Exported_Constants
bogdanm 92:4fc01daae5a5 157 * @{
bogdanm 92:4fc01daae5a5 158 */
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 /** @defgroup UART_Word_Length
bogdanm 92:4fc01daae5a5 161 * @{
bogdanm 92:4fc01daae5a5 162 */
bogdanm 92:4fc01daae5a5 163 #define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 164 #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
bogdanm 92:4fc01daae5a5 165 #define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
bogdanm 92:4fc01daae5a5 166 ((LENGTH) == UART_WORDLENGTH_9B))
bogdanm 92:4fc01daae5a5 167 /**
bogdanm 92:4fc01daae5a5 168 * @}
bogdanm 92:4fc01daae5a5 169 */
bogdanm 92:4fc01daae5a5 170
bogdanm 92:4fc01daae5a5 171 /** @defgroup UART_Stop_Bits
bogdanm 92:4fc01daae5a5 172 * @{
bogdanm 92:4fc01daae5a5 173 */
bogdanm 92:4fc01daae5a5 174 #define UART_STOPBITS_1 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 175 #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
bogdanm 92:4fc01daae5a5 176 #define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
bogdanm 92:4fc01daae5a5 177 ((STOPBITS) == UART_STOPBITS_2))
bogdanm 92:4fc01daae5a5 178 /**
bogdanm 92:4fc01daae5a5 179 * @}
bogdanm 92:4fc01daae5a5 180 */
bogdanm 92:4fc01daae5a5 181
bogdanm 92:4fc01daae5a5 182 /** @defgroup UART_Parity
bogdanm 92:4fc01daae5a5 183 * @{
bogdanm 92:4fc01daae5a5 184 */
bogdanm 92:4fc01daae5a5 185 #define UART_PARITY_NONE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 186 #define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
bogdanm 92:4fc01daae5a5 187 #define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
bogdanm 92:4fc01daae5a5 188 #define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
bogdanm 92:4fc01daae5a5 189 ((PARITY) == UART_PARITY_EVEN) || \
bogdanm 92:4fc01daae5a5 190 ((PARITY) == UART_PARITY_ODD))
bogdanm 92:4fc01daae5a5 191 /**
bogdanm 92:4fc01daae5a5 192 * @}
bogdanm 92:4fc01daae5a5 193 */
bogdanm 92:4fc01daae5a5 194
bogdanm 92:4fc01daae5a5 195 /** @defgroup UART_Hardware_Flow_Control
bogdanm 92:4fc01daae5a5 196 * @{
bogdanm 92:4fc01daae5a5 197 */
bogdanm 92:4fc01daae5a5 198 #define UART_HWCONTROL_NONE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 199 #define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
bogdanm 92:4fc01daae5a5 200 #define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
bogdanm 92:4fc01daae5a5 201 #define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
bogdanm 92:4fc01daae5a5 202 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
bogdanm 92:4fc01daae5a5 203 (((CONTROL) == UART_HWCONTROL_NONE) || \
bogdanm 92:4fc01daae5a5 204 ((CONTROL) == UART_HWCONTROL_RTS) || \
bogdanm 92:4fc01daae5a5 205 ((CONTROL) == UART_HWCONTROL_CTS) || \
bogdanm 92:4fc01daae5a5 206 ((CONTROL) == UART_HWCONTROL_RTS_CTS))
bogdanm 92:4fc01daae5a5 207 /**
bogdanm 92:4fc01daae5a5 208 * @}
bogdanm 92:4fc01daae5a5 209 */
bogdanm 92:4fc01daae5a5 210
bogdanm 92:4fc01daae5a5 211 /** @defgroup UART_Mode
bogdanm 92:4fc01daae5a5 212 * @{
bogdanm 92:4fc01daae5a5 213 */
bogdanm 92:4fc01daae5a5 214 #define UART_MODE_RX ((uint32_t)USART_CR1_RE)
bogdanm 92:4fc01daae5a5 215 #define UART_MODE_TX ((uint32_t)USART_CR1_TE)
bogdanm 92:4fc01daae5a5 216 #define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
bogdanm 92:4fc01daae5a5 217 #define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
bogdanm 92:4fc01daae5a5 218 /**
bogdanm 92:4fc01daae5a5 219 * @}
bogdanm 92:4fc01daae5a5 220 */
bogdanm 92:4fc01daae5a5 221
bogdanm 92:4fc01daae5a5 222 /** @defgroup UART_State
bogdanm 92:4fc01daae5a5 223 * @{
bogdanm 92:4fc01daae5a5 224 */
bogdanm 92:4fc01daae5a5 225 #define UART_STATE_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 226 #define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
bogdanm 92:4fc01daae5a5 227 #define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
bogdanm 92:4fc01daae5a5 228 ((STATE) == UART_STATE_ENABLE))
bogdanm 92:4fc01daae5a5 229 /**
bogdanm 92:4fc01daae5a5 230 * @}
bogdanm 92:4fc01daae5a5 231 */
bogdanm 92:4fc01daae5a5 232
bogdanm 92:4fc01daae5a5 233 /** @defgroup UART_Over_Sampling
bogdanm 92:4fc01daae5a5 234 * @{
bogdanm 92:4fc01daae5a5 235 */
bogdanm 92:4fc01daae5a5 236 #define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 237 #define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
bogdanm 92:4fc01daae5a5 238 #define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
bogdanm 92:4fc01daae5a5 239 ((SAMPLING) == UART_OVERSAMPLING_8))
bogdanm 92:4fc01daae5a5 240 /**
bogdanm 92:4fc01daae5a5 241 * @}
bogdanm 92:4fc01daae5a5 242 */
bogdanm 92:4fc01daae5a5 243
bogdanm 92:4fc01daae5a5 244 /** @defgroup UART_LIN_Break_Detection_Length
bogdanm 92:4fc01daae5a5 245 * @{
bogdanm 92:4fc01daae5a5 246 */
bogdanm 92:4fc01daae5a5 247 #define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 248 #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 249 #define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
bogdanm 92:4fc01daae5a5 250 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
bogdanm 92:4fc01daae5a5 251 /**
bogdanm 92:4fc01daae5a5 252 * @}
bogdanm 92:4fc01daae5a5 253 */
bogdanm 92:4fc01daae5a5 254
bogdanm 92:4fc01daae5a5 255 /** @defgroup UART_WakeUp_functions
bogdanm 92:4fc01daae5a5 256 * @{
bogdanm 92:4fc01daae5a5 257 */
bogdanm 92:4fc01daae5a5 258 #define UART_WAKEUPMETHODE_IDLELINE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 259 #define UART_WAKEUPMETHODE_ADDRESSMARK ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 260 #define IS_UART_WAKEUPMETHODE(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHODE_IDLELINE) || \
bogdanm 92:4fc01daae5a5 261 ((WAKEUP) == UART_WAKEUPMETHODE_ADDRESSMARK))
bogdanm 92:4fc01daae5a5 262 /**
bogdanm 92:4fc01daae5a5 263 * @}
bogdanm 92:4fc01daae5a5 264 */
bogdanm 92:4fc01daae5a5 265
bogdanm 92:4fc01daae5a5 266 /** @defgroup UART_Flags
bogdanm 92:4fc01daae5a5 267 * Elements values convention: 0xXXXX
bogdanm 92:4fc01daae5a5 268 * - 0xXXXX : Flag mask in the SR register
bogdanm 92:4fc01daae5a5 269 * @{
bogdanm 92:4fc01daae5a5 270 */
bogdanm 92:4fc01daae5a5 271 #define UART_FLAG_CTS ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 272 #define UART_FLAG_LBD ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 273 #define UART_FLAG_TXE ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 274 #define UART_FLAG_TC ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 275 #define UART_FLAG_RXNE ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 276 #define UART_FLAG_IDLE ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 277 #define UART_FLAG_ORE ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 278 #define UART_FLAG_NE ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 279 #define UART_FLAG_FE ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 280 #define UART_FLAG_PE ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 281 /**
bogdanm 92:4fc01daae5a5 282 * @}
bogdanm 92:4fc01daae5a5 283 */
bogdanm 92:4fc01daae5a5 284
bogdanm 92:4fc01daae5a5 285 /** @defgroup UART_Interrupt_definition
bogdanm 92:4fc01daae5a5 286 * Elements values convention: 0xY000XXXX
bogdanm 92:4fc01daae5a5 287 * - XXXX : Interrupt mask in the XX register
bogdanm 92:4fc01daae5a5 288 * - Y : Interrupt source register (2bits)
bogdanm 92:4fc01daae5a5 289 * - 01: CR1 register
bogdanm 92:4fc01daae5a5 290 * - 10: CR2 register
bogdanm 92:4fc01daae5a5 291 * - 11: CR3 register
bogdanm 92:4fc01daae5a5 292 *
bogdanm 92:4fc01daae5a5 293 * @{
bogdanm 92:4fc01daae5a5 294 */
bogdanm 92:4fc01daae5a5 295 #define UART_IT_PE ((uint32_t)0x10000100)
bogdanm 92:4fc01daae5a5 296 #define UART_IT_TXE ((uint32_t)0x10000080)
bogdanm 92:4fc01daae5a5 297 #define UART_IT_TC ((uint32_t)0x10000040)
bogdanm 92:4fc01daae5a5 298 #define UART_IT_RXNE ((uint32_t)0x10000020)
bogdanm 92:4fc01daae5a5 299 #define UART_IT_IDLE ((uint32_t)0x10000010)
bogdanm 92:4fc01daae5a5 300
bogdanm 92:4fc01daae5a5 301 #define UART_IT_LBD ((uint32_t)0x20000040)
bogdanm 92:4fc01daae5a5 302 #define UART_IT_CTS ((uint32_t)0x30000400)
bogdanm 92:4fc01daae5a5 303
bogdanm 92:4fc01daae5a5 304 #define UART_IT_ERR ((uint32_t)0x30000001)
bogdanm 92:4fc01daae5a5 305
bogdanm 92:4fc01daae5a5 306 /**
bogdanm 92:4fc01daae5a5 307 * @}
bogdanm 92:4fc01daae5a5 308 */
bogdanm 92:4fc01daae5a5 309
bogdanm 92:4fc01daae5a5 310 /**
bogdanm 92:4fc01daae5a5 311 * @}
bogdanm 92:4fc01daae5a5 312 */
bogdanm 92:4fc01daae5a5 313
bogdanm 92:4fc01daae5a5 314 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 315
bogdanm 92:4fc01daae5a5 316 /** @brief Reset UART handle state
bogdanm 92:4fc01daae5a5 317 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 318 * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
bogdanm 92:4fc01daae5a5 319 * UART peripheral.
bogdanm 92:4fc01daae5a5 320 * @retval None
bogdanm 92:4fc01daae5a5 321 */
bogdanm 92:4fc01daae5a5 322 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
bogdanm 92:4fc01daae5a5 323
bogdanm 92:4fc01daae5a5 324 /** @brief Flushs the UART DR register
bogdanm 92:4fc01daae5a5 325 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 326 */
bogdanm 92:4fc01daae5a5 327 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
bogdanm 92:4fc01daae5a5 328
bogdanm 92:4fc01daae5a5 329 /** @brief Checks whether the specified UART flag is set or not.
bogdanm 92:4fc01daae5a5 330 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 331 * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
bogdanm 92:4fc01daae5a5 332 * UART peripheral.
bogdanm 92:4fc01daae5a5 333 * @param __FLAG__: specifies the flag to check.
bogdanm 92:4fc01daae5a5 334 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 335 * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
bogdanm 92:4fc01daae5a5 336 * @arg UART_FLAG_LBD: LIN Break detection flag
bogdanm 92:4fc01daae5a5 337 * @arg UART_FLAG_TXE: Transmit data register empty flag
bogdanm 92:4fc01daae5a5 338 * @arg UART_FLAG_TC: Transmission Complete flag
bogdanm 92:4fc01daae5a5 339 * @arg UART_FLAG_RXNE: Receive data register not empty flag
bogdanm 92:4fc01daae5a5 340 * @arg UART_FLAG_IDLE: Idle Line detection flag
bogdanm 92:4fc01daae5a5 341 * @arg UART_FLAG_ORE: OverRun Error flag
bogdanm 92:4fc01daae5a5 342 * @arg UART_FLAG_NE: Noise Error flag
bogdanm 92:4fc01daae5a5 343 * @arg UART_FLAG_FE: Framing Error flag
bogdanm 92:4fc01daae5a5 344 * @arg UART_FLAG_PE: Parity Error flag
bogdanm 92:4fc01daae5a5 345 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 346 */
bogdanm 92:4fc01daae5a5 347
bogdanm 92:4fc01daae5a5 348 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 349
bogdanm 92:4fc01daae5a5 350 /** @brief Clears the specified UART pending flag.
bogdanm 92:4fc01daae5a5 351 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 352 * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
bogdanm 92:4fc01daae5a5 353 * UART peripheral.
bogdanm 92:4fc01daae5a5 354 * @param __FLAG__: specifies the flag to check.
bogdanm 92:4fc01daae5a5 355 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 356 * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
bogdanm 92:4fc01daae5a5 357 * @arg UART_FLAG_LBD: LIN Break detection flag.
bogdanm 92:4fc01daae5a5 358 * @arg UART_FLAG_TC: Transmission Complete flag.
bogdanm 92:4fc01daae5a5 359 * @arg UART_FLAG_RXNE: Receive data register not empty flag.
bogdanm 92:4fc01daae5a5 360 *
bogdanm 92:4fc01daae5a5 361 * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
bogdanm 92:4fc01daae5a5 362 * error) and IDLE (Idle line detected) flags are cleared by software
bogdanm 92:4fc01daae5a5 363 * sequence: a read operation to USART_SR register followed by a read
bogdanm 92:4fc01daae5a5 364 * operation to USART_DR register.
bogdanm 92:4fc01daae5a5 365 * @note RXNE flag can be also cleared by a read to the USART_DR register.
bogdanm 92:4fc01daae5a5 366 * @note TC flag can be also cleared by software sequence: a read operation to
bogdanm 92:4fc01daae5a5 367 * USART_SR register followed by a write operation to USART_DR register.
bogdanm 92:4fc01daae5a5 368 * @note TXE flag is cleared only by a write to the USART_DR register.
bogdanm 92:4fc01daae5a5 369 *
bogdanm 92:4fc01daae5a5 370 * @retval None
bogdanm 92:4fc01daae5a5 371 */
bogdanm 92:4fc01daae5a5 372 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm 92:4fc01daae5a5 373
bogdanm 92:4fc01daae5a5 374 /** @brief Clear the UART PE pending flag.
bogdanm 92:4fc01daae5a5 375 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 376 * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
bogdanm 92:4fc01daae5a5 377 * UART peripheral.
bogdanm 92:4fc01daae5a5 378 * @retval None
bogdanm 92:4fc01daae5a5 379 */
bogdanm 92:4fc01daae5a5 380 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
bogdanm 92:4fc01daae5a5 381 (__HANDLE__)->Instance->DR;}while(0)
bogdanm 92:4fc01daae5a5 382 /** @brief Clear the UART FE pending flag.
bogdanm 92:4fc01daae5a5 383 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 384 * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
bogdanm 92:4fc01daae5a5 385 * UART peripheral.
bogdanm 92:4fc01daae5a5 386 * @retval None
bogdanm 92:4fc01daae5a5 387 */
bogdanm 92:4fc01daae5a5 388 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
bogdanm 92:4fc01daae5a5 389
bogdanm 92:4fc01daae5a5 390 /** @brief Clear the UART NE pending flag.
bogdanm 92:4fc01daae5a5 391 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 392 * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
bogdanm 92:4fc01daae5a5 393 * UART peripheral.
bogdanm 92:4fc01daae5a5 394 * @retval None
bogdanm 92:4fc01daae5a5 395 */
bogdanm 92:4fc01daae5a5 396 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
bogdanm 92:4fc01daae5a5 397
bogdanm 92:4fc01daae5a5 398 /** @brief Clear the UART ORE pending flag.
bogdanm 92:4fc01daae5a5 399 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 400 * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
bogdanm 92:4fc01daae5a5 401 * UART peripheral.
bogdanm 92:4fc01daae5a5 402 * @retval None
bogdanm 92:4fc01daae5a5 403 */
bogdanm 92:4fc01daae5a5 404 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
bogdanm 92:4fc01daae5a5 405
bogdanm 92:4fc01daae5a5 406 /** @brief Clear the UART IDLE pending flag.
bogdanm 92:4fc01daae5a5 407 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 408 * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
bogdanm 92:4fc01daae5a5 409 * UART peripheral.
bogdanm 92:4fc01daae5a5 410 * @retval None
bogdanm 92:4fc01daae5a5 411 */
bogdanm 92:4fc01daae5a5 412 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
bogdanm 92:4fc01daae5a5 413
bogdanm 92:4fc01daae5a5 414 /** @brief Enables or disables the specified UART interrupt.
bogdanm 92:4fc01daae5a5 415 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 416 * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
bogdanm 92:4fc01daae5a5 417 * UART peripheral.
bogdanm 92:4fc01daae5a5 418 * @param __INTERRUPT__: specifies the UART interrupt source to check.
bogdanm 92:4fc01daae5a5 419 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 420 * @arg UART_IT_CTS: CTS change interrupt
bogdanm 92:4fc01daae5a5 421 * @arg UART_IT_LBD: LIN Break detection interrupt
bogdanm 92:4fc01daae5a5 422 * @arg UART_IT_TXE: Transmit Data Register empty interrupt
bogdanm 92:4fc01daae5a5 423 * @arg UART_IT_TC: Transmission complete interrupt
bogdanm 92:4fc01daae5a5 424 * @arg UART_IT_RXNE: Receive Data register not empty interrupt
bogdanm 92:4fc01daae5a5 425 * @arg UART_IT_IDLE: Idle line detection interrupt
bogdanm 92:4fc01daae5a5 426 * @arg UART_IT_PE: Parity Error interrupt
bogdanm 92:4fc01daae5a5 427 * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
bogdanm 92:4fc01daae5a5 428 * @param NewState: new state of the specified UART interrupt.
bogdanm 92:4fc01daae5a5 429 * This parameter can be: ENABLE or DISABLE.
bogdanm 92:4fc01daae5a5 430 * @retval None
bogdanm 92:4fc01daae5a5 431 */
bogdanm 92:4fc01daae5a5 432 #define UART_IT_MASK ((uint32_t)0x0000FFFF)
bogdanm 92:4fc01daae5a5 433 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
bogdanm 92:4fc01daae5a5 434 (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
bogdanm 92:4fc01daae5a5 435 ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
bogdanm 92:4fc01daae5a5 436 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
bogdanm 92:4fc01daae5a5 437 (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
bogdanm 92:4fc01daae5a5 438 ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
bogdanm 92:4fc01daae5a5 439
bogdanm 92:4fc01daae5a5 440 /** @brief Checks whether the specified UART interrupt has occurred or not.
bogdanm 92:4fc01daae5a5 441 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 442 * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
bogdanm 92:4fc01daae5a5 443 * UART peripheral.
bogdanm 92:4fc01daae5a5 444 * @param __IT__: specifies the UART interrupt source to check.
bogdanm 92:4fc01daae5a5 445 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 446 * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
bogdanm 92:4fc01daae5a5 447 * @arg UART_IT_LBD: LIN Break detection interrupt
bogdanm 92:4fc01daae5a5 448 * @arg UART_IT_TXE: Transmit Data Register empty interrupt
bogdanm 92:4fc01daae5a5 449 * @arg UART_IT_TC: Transmission complete interrupt
bogdanm 92:4fc01daae5a5 450 * @arg UART_IT_RXNE: Receive Data register not empty interrupt
bogdanm 92:4fc01daae5a5 451 * @arg UART_IT_IDLE: Idle line detection interrupt
bogdanm 92:4fc01daae5a5 452 * @arg USART_IT_ERR: Error interrupt
bogdanm 92:4fc01daae5a5 453 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 454 */
bogdanm 92:4fc01daae5a5 455 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
bogdanm 92:4fc01daae5a5 456 (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
bogdanm 92:4fc01daae5a5 457
bogdanm 92:4fc01daae5a5 458 /** @brief Enable CTS flow control
bogdanm 92:4fc01daae5a5 459 * This macro allows to enable CTS hardware flow control for a given UART instance,
bogdanm 92:4fc01daae5a5 460 * without need to call HAL_UART_Init() function.
bogdanm 92:4fc01daae5a5 461 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
bogdanm 92:4fc01daae5a5 462 * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
bogdanm 92:4fc01daae5a5 463 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
bogdanm 92:4fc01daae5a5 464 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
bogdanm 92:4fc01daae5a5 465 * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
bogdanm 92:4fc01daae5a5 466 * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
bogdanm 92:4fc01daae5a5 467 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 468 * The Handle Instance can be USART1, USART2 or LPUART.
bogdanm 92:4fc01daae5a5 469 * @retval None
bogdanm 92:4fc01daae5a5 470 */
bogdanm 92:4fc01daae5a5 471 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
bogdanm 92:4fc01daae5a5 472 do{ \
bogdanm 92:4fc01daae5a5 473 SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
bogdanm 92:4fc01daae5a5 474 (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
bogdanm 92:4fc01daae5a5 475 } while(0)
bogdanm 92:4fc01daae5a5 476
bogdanm 92:4fc01daae5a5 477 /** @brief Disable CTS flow control
bogdanm 92:4fc01daae5a5 478 * This macro allows to disable CTS hardware flow control for a given UART instance,
bogdanm 92:4fc01daae5a5 479 * without need to call HAL_UART_Init() function.
bogdanm 92:4fc01daae5a5 480 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
bogdanm 92:4fc01daae5a5 481 * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
bogdanm 92:4fc01daae5a5 482 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
bogdanm 92:4fc01daae5a5 483 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
bogdanm 92:4fc01daae5a5 484 * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
bogdanm 92:4fc01daae5a5 485 * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
bogdanm 92:4fc01daae5a5 486 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 487 * The Handle Instance can be USART1, USART2 or LPUART.
bogdanm 92:4fc01daae5a5 488 * @retval None
bogdanm 92:4fc01daae5a5 489 */
bogdanm 92:4fc01daae5a5 490 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
bogdanm 92:4fc01daae5a5 491 do{ \
bogdanm 92:4fc01daae5a5 492 CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
bogdanm 92:4fc01daae5a5 493 (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
bogdanm 92:4fc01daae5a5 494 } while(0)
bogdanm 92:4fc01daae5a5 495
bogdanm 92:4fc01daae5a5 496 /** @brief Enable RTS flow control
bogdanm 92:4fc01daae5a5 497 * This macro allows to enable RTS hardware flow control for a given UART instance,
bogdanm 92:4fc01daae5a5 498 * without need to call HAL_UART_Init() function.
bogdanm 92:4fc01daae5a5 499 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
bogdanm 92:4fc01daae5a5 500 * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
bogdanm 92:4fc01daae5a5 501 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
bogdanm 92:4fc01daae5a5 502 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
bogdanm 92:4fc01daae5a5 503 * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
bogdanm 92:4fc01daae5a5 504 * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
bogdanm 92:4fc01daae5a5 505 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 506 * The Handle Instance can be USART1, USART2 or LPUART.
bogdanm 92:4fc01daae5a5 507 * @retval None
bogdanm 92:4fc01daae5a5 508 */
bogdanm 92:4fc01daae5a5 509 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
bogdanm 92:4fc01daae5a5 510 do{ \
bogdanm 92:4fc01daae5a5 511 SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
bogdanm 92:4fc01daae5a5 512 (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
bogdanm 92:4fc01daae5a5 513 } while(0)
bogdanm 92:4fc01daae5a5 514
bogdanm 92:4fc01daae5a5 515 /** @brief Disable RTS flow control
bogdanm 92:4fc01daae5a5 516 * This macro allows to disable RTS hardware flow control for a given UART instance,
bogdanm 92:4fc01daae5a5 517 * without need to call HAL_UART_Init() function.
bogdanm 92:4fc01daae5a5 518 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
bogdanm 92:4fc01daae5a5 519 * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
bogdanm 92:4fc01daae5a5 520 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
bogdanm 92:4fc01daae5a5 521 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
bogdanm 92:4fc01daae5a5 522 * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
bogdanm 92:4fc01daae5a5 523 * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
bogdanm 92:4fc01daae5a5 524 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 525 * The Handle Instance can be USART1, USART2 or LPUART.
bogdanm 92:4fc01daae5a5 526 * @retval None
bogdanm 92:4fc01daae5a5 527 */
bogdanm 92:4fc01daae5a5 528 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
bogdanm 92:4fc01daae5a5 529 do{ \
bogdanm 92:4fc01daae5a5 530 CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
bogdanm 92:4fc01daae5a5 531 (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
bogdanm 92:4fc01daae5a5 532 } while(0)
bogdanm 92:4fc01daae5a5 533
bogdanm 92:4fc01daae5a5 534 /** @brief macros to enables or disables the UART's one bit sampling method
bogdanm 92:4fc01daae5a5 535 * @param __HANDLE__: specifies the UART Handle.
bogdanm 92:4fc01daae5a5 536 * @retval None
bogdanm 92:4fc01daae5a5 537 */
bogdanm 92:4fc01daae5a5 538 #define __HAL_UART_ONEBIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
bogdanm 92:4fc01daae5a5 539 #define __HAL_UART_ONEBIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
bogdanm 92:4fc01daae5a5 540
bogdanm 92:4fc01daae5a5 541 #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
bogdanm 92:4fc01daae5a5 542 #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
bogdanm 92:4fc01daae5a5 543
bogdanm 92:4fc01daae5a5 544 #define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
bogdanm 92:4fc01daae5a5 545 #define __DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (__DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
bogdanm 92:4fc01daae5a5 546 #define __DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((__DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
bogdanm 92:4fc01daae5a5 547 #define __UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
bogdanm 92:4fc01daae5a5 548
bogdanm 92:4fc01daae5a5 549 #define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
bogdanm 92:4fc01daae5a5 550 #define __DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (__DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
bogdanm 92:4fc01daae5a5 551 #define __DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((__DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
bogdanm 92:4fc01daae5a5 552 #define __UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
bogdanm 92:4fc01daae5a5 553
bogdanm 92:4fc01daae5a5 554 #define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
bogdanm 92:4fc01daae5a5 555 #define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
bogdanm 92:4fc01daae5a5 556
bogdanm 92:4fc01daae5a5 557 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 558 /* Initialization/de-initialization functions **********************************/
bogdanm 92:4fc01daae5a5 559 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 560 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 561 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
bogdanm 92:4fc01daae5a5 562 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode);
bogdanm 92:4fc01daae5a5 563 HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 564 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 565 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 566
bogdanm 92:4fc01daae5a5 567 /* IO operation functions *******************************************************/
bogdanm 92:4fc01daae5a5 568 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 569 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 570 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 571 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 572 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 573 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 574 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 575 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 576 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 577 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 578 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 579 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 580 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 581 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 582 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 583
bogdanm 92:4fc01daae5a5 584 /* Peripheral Control functions ************************************************/
bogdanm 92:4fc01daae5a5 585 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 586 HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 587 HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 588 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 589 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 590
bogdanm 92:4fc01daae5a5 591 /* Peripheral State functions **************************************************/
bogdanm 92:4fc01daae5a5 592 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 593 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
bogdanm 92:4fc01daae5a5 594
bogdanm 92:4fc01daae5a5 595 /**
bogdanm 92:4fc01daae5a5 596 * @}
bogdanm 92:4fc01daae5a5 597 */
bogdanm 92:4fc01daae5a5 598
bogdanm 92:4fc01daae5a5 599 /**
bogdanm 92:4fc01daae5a5 600 * @}
bogdanm 92:4fc01daae5a5 601 */
bogdanm 92:4fc01daae5a5 602
bogdanm 92:4fc01daae5a5 603 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 604 }
bogdanm 92:4fc01daae5a5 605 #endif
bogdanm 92:4fc01daae5a5 606
bogdanm 92:4fc01daae5a5 607 #endif /* __STM32F4xx_HAL_UART_H */
bogdanm 92:4fc01daae5a5 608
bogdanm 92:4fc01daae5a5 609 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/