mbed - meh | Mbed

Users » ricardobtez » Code » mbed

meh

TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_tim.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:: ricardobtez
Date:: Tue Apr 05 23:51:21 2016 +0000
Revision:: 118:16969dd821af
Parent:: 92:4fc01daae5a5
Child:: 99:dbbf35b96557

dgdgr

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	92:4fc01daae5a5	1	/**
bogdanm	92:4fc01daae5a5	2	******************************************************************************
bogdanm	92:4fc01daae5a5	3	* @file stm32f4xx_hal_tim.h
bogdanm	92:4fc01daae5a5	4	* @author MCD Application Team
bogdanm	92:4fc01daae5a5	5	* @version V1.1.0
bogdanm	92:4fc01daae5a5	6	* @date 19-June-2014
bogdanm	92:4fc01daae5a5	7	* @brief Header file of TIM HAL module.
bogdanm	92:4fc01daae5a5	8	******************************************************************************
bogdanm	92:4fc01daae5a5	9	* @attention
bogdanm	92:4fc01daae5a5	10	*
bogdanm	92:4fc01daae5a5	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	92:4fc01daae5a5	12	*
bogdanm	92:4fc01daae5a5	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	92:4fc01daae5a5	14	* are permitted provided that the following conditions are met:
bogdanm	92:4fc01daae5a5	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	92:4fc01daae5a5	16	* this list of conditions and the following disclaimer.
bogdanm	92:4fc01daae5a5	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	92:4fc01daae5a5	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	92:4fc01daae5a5	19	* and/or other materials provided with the distribution.
bogdanm	92:4fc01daae5a5	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	92:4fc01daae5a5	21	* may be used to endorse or promote products derived from this software
bogdanm	92:4fc01daae5a5	22	* without specific prior written permission.
bogdanm	92:4fc01daae5a5	23	*
bogdanm	92:4fc01daae5a5	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	92:4fc01daae5a5	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	92:4fc01daae5a5	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	92:4fc01daae5a5	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	92:4fc01daae5a5	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	92:4fc01daae5a5	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	92:4fc01daae5a5	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	92:4fc01daae5a5	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	92:4fc01daae5a5	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	92:4fc01daae5a5	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	92:4fc01daae5a5	34	*
bogdanm	92:4fc01daae5a5	35	******************************************************************************
bogdanm	92:4fc01daae5a5	36	*/
bogdanm	92:4fc01daae5a5	37
bogdanm	92:4fc01daae5a5	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	92:4fc01daae5a5	39	#ifndef __STM32F4xx_HAL_TIM_H
bogdanm	92:4fc01daae5a5	40	#define __STM32F4xx_HAL_TIM_H
bogdanm	92:4fc01daae5a5	41
bogdanm	92:4fc01daae5a5	42	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	43	extern "C" {
bogdanm	92:4fc01daae5a5	44	#endif
bogdanm	92:4fc01daae5a5	45
bogdanm	92:4fc01daae5a5	46	/* Includes ------------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	47	#include "stm32f4xx_hal_def.h"
bogdanm	92:4fc01daae5a5	48
bogdanm	92:4fc01daae5a5	49	/** @addtogroup STM32F4xx_HAL
bogdanm	92:4fc01daae5a5	50	* @{
bogdanm	92:4fc01daae5a5	51	*/
bogdanm	92:4fc01daae5a5	52
bogdanm	92:4fc01daae5a5	53	/** @addtogroup TIM
bogdanm	92:4fc01daae5a5	54	* @{
bogdanm	92:4fc01daae5a5	55	*/
bogdanm	92:4fc01daae5a5	56
bogdanm	92:4fc01daae5a5	57	/* Exported types ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	58
bogdanm	92:4fc01daae5a5	59	/**
bogdanm	92:4fc01daae5a5	60	* @brief TIM Time base Configuration Structure definition
bogdanm	92:4fc01daae5a5	61	*/
bogdanm	92:4fc01daae5a5	62	typedef struct
bogdanm	92:4fc01daae5a5	63	{
bogdanm	92:4fc01daae5a5	64	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	92:4fc01daae5a5	65	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	92:4fc01daae5a5	66
bogdanm	92:4fc01daae5a5	67	uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm	92:4fc01daae5a5	68	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	92:4fc01daae5a5	69
bogdanm	92:4fc01daae5a5	70	uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm	92:4fc01daae5a5	71	Auto-Reload Register at the next update event.
bogdanm	92:4fc01daae5a5	72	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm	92:4fc01daae5a5	73
bogdanm	92:4fc01daae5a5	74	uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm	92:4fc01daae5a5	75	This parameter can be a value of @ref TIM_ClockDivision */
bogdanm	92:4fc01daae5a5	76
bogdanm	92:4fc01daae5a5	77	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm	92:4fc01daae5a5	78	reaches zero, an update event is generated and counting restarts
bogdanm	92:4fc01daae5a5	79	from the RCR value (N).
bogdanm	92:4fc01daae5a5	80	This means in PWM mode that (N+1) corresponds to:
bogdanm	92:4fc01daae5a5	81	- the number of PWM periods in edge-aligned mode
bogdanm	92:4fc01daae5a5	82	- the number of half PWM period in center-aligned mode
bogdanm	92:4fc01daae5a5	83	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm	92:4fc01daae5a5	84	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	92:4fc01daae5a5	85	} TIM_Base_InitTypeDef;
bogdanm	92:4fc01daae5a5	86
bogdanm	92:4fc01daae5a5	87	/**
bogdanm	92:4fc01daae5a5	88	* @brief TIM Output Compare Configuration Structure definition
bogdanm	92:4fc01daae5a5	89	*/
bogdanm	92:4fc01daae5a5	90
bogdanm	92:4fc01daae5a5	91	typedef struct
bogdanm	92:4fc01daae5a5	92	{
bogdanm	92:4fc01daae5a5	93	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	92:4fc01daae5a5	94	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	92:4fc01daae5a5	95
bogdanm	92:4fc01daae5a5	96	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	92:4fc01daae5a5	97	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	92:4fc01daae5a5	98
bogdanm	92:4fc01daae5a5	99	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	92:4fc01daae5a5	100	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	92:4fc01daae5a5	101
bogdanm	92:4fc01daae5a5	102	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	92:4fc01daae5a5	103	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	92:4fc01daae5a5	104	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	92:4fc01daae5a5	105
bogdanm	92:4fc01daae5a5	106	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm	92:4fc01daae5a5	107	This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm	92:4fc01daae5a5	108	@note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm	92:4fc01daae5a5	109
bogdanm	92:4fc01daae5a5	110
bogdanm	92:4fc01daae5a5	111	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	92:4fc01daae5a5	112	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	92:4fc01daae5a5	113	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	92:4fc01daae5a5	114
bogdanm	92:4fc01daae5a5	115	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	92:4fc01daae5a5	116	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	92:4fc01daae5a5	117	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	92:4fc01daae5a5	118	} TIM_OC_InitTypeDef;
bogdanm	92:4fc01daae5a5	119
bogdanm	92:4fc01daae5a5	120	/**
bogdanm	92:4fc01daae5a5	121	* @brief TIM One Pulse Mode Configuration Structure definition
bogdanm	92:4fc01daae5a5	122	*/
bogdanm	92:4fc01daae5a5	123	typedef struct
bogdanm	92:4fc01daae5a5	124	{
bogdanm	92:4fc01daae5a5	125	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	92:4fc01daae5a5	126	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	92:4fc01daae5a5	127
bogdanm	92:4fc01daae5a5	128	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	92:4fc01daae5a5	129	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	92:4fc01daae5a5	130
bogdanm	92:4fc01daae5a5	131	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	92:4fc01daae5a5	132	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	92:4fc01daae5a5	133
bogdanm	92:4fc01daae5a5	134	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	92:4fc01daae5a5	135	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	92:4fc01daae5a5	136	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	92:4fc01daae5a5	137
bogdanm	92:4fc01daae5a5	138	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	92:4fc01daae5a5	139	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	92:4fc01daae5a5	140	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	92:4fc01daae5a5	141
bogdanm	92:4fc01daae5a5	142	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	92:4fc01daae5a5	143	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	92:4fc01daae5a5	144	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	92:4fc01daae5a5	145
bogdanm	92:4fc01daae5a5	146	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	92:4fc01daae5a5	147	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	92:4fc01daae5a5	148
bogdanm	92:4fc01daae5a5	149	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	92:4fc01daae5a5	150	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	92:4fc01daae5a5	151
bogdanm	92:4fc01daae5a5	152	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	92:4fc01daae5a5	153	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	92:4fc01daae5a5	154	} TIM_OnePulse_InitTypeDef;
bogdanm	92:4fc01daae5a5	155
bogdanm	92:4fc01daae5a5	156
bogdanm	92:4fc01daae5a5	157	/**
bogdanm	92:4fc01daae5a5	158	* @brief TIM Input Capture Configuration Structure definition
bogdanm	92:4fc01daae5a5	159	*/
bogdanm	92:4fc01daae5a5	160
bogdanm	92:4fc01daae5a5	161	typedef struct
bogdanm	92:4fc01daae5a5	162	{
bogdanm	92:4fc01daae5a5	163	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	92:4fc01daae5a5	164	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	92:4fc01daae5a5	165
bogdanm	92:4fc01daae5a5	166	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	92:4fc01daae5a5	167	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	92:4fc01daae5a5	168
bogdanm	92:4fc01daae5a5	169	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	92:4fc01daae5a5	170	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	92:4fc01daae5a5	171
bogdanm	92:4fc01daae5a5	172	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	92:4fc01daae5a5	173	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	92:4fc01daae5a5	174	} TIM_IC_InitTypeDef;
bogdanm	92:4fc01daae5a5	175
bogdanm	92:4fc01daae5a5	176	/**
bogdanm	92:4fc01daae5a5	177	* @brief TIM Encoder Configuration Structure definition
bogdanm	92:4fc01daae5a5	178	*/
bogdanm	92:4fc01daae5a5	179
bogdanm	92:4fc01daae5a5	180	typedef struct
bogdanm	92:4fc01daae5a5	181	{
bogdanm	92:4fc01daae5a5	182	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm	92:4fc01daae5a5	183	This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm	92:4fc01daae5a5	184
bogdanm	92:4fc01daae5a5	185	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	92:4fc01daae5a5	186	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	92:4fc01daae5a5	187
bogdanm	92:4fc01daae5a5	188	uint32_t IC1Selection; /*!< Specifies the input.
bogdanm	92:4fc01daae5a5	189	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	92:4fc01daae5a5	190
bogdanm	92:4fc01daae5a5	191	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	92:4fc01daae5a5	192	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	92:4fc01daae5a5	193
bogdanm	92:4fc01daae5a5	194	uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm	92:4fc01daae5a5	195	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	92:4fc01daae5a5	196
bogdanm	92:4fc01daae5a5	197	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	92:4fc01daae5a5	198	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	92:4fc01daae5a5	199
bogdanm	92:4fc01daae5a5	200	uint32_t IC2Selection; /*!< Specifies the input.
bogdanm	92:4fc01daae5a5	201	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	92:4fc01daae5a5	202
bogdanm	92:4fc01daae5a5	203	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	92:4fc01daae5a5	204	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	92:4fc01daae5a5	205
bogdanm	92:4fc01daae5a5	206	uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm	92:4fc01daae5a5	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	92:4fc01daae5a5	208	} TIM_Encoder_InitTypeDef;
bogdanm	92:4fc01daae5a5	209
bogdanm	92:4fc01daae5a5	210	/**
bogdanm	92:4fc01daae5a5	211	* @brief Clock Configuration Handle Structure definition
bogdanm	92:4fc01daae5a5	212	*/
bogdanm	92:4fc01daae5a5	213	typedef struct
bogdanm	92:4fc01daae5a5	214	{
bogdanm	92:4fc01daae5a5	215	uint32_t ClockSource; /*!< TIM clock sources.
bogdanm	92:4fc01daae5a5	216	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	92:4fc01daae5a5	217	uint32_t ClockPolarity; /*!< TIM clock polarity.
bogdanm	92:4fc01daae5a5	218	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	92:4fc01daae5a5	219	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
bogdanm	92:4fc01daae5a5	220	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	92:4fc01daae5a5	221	uint32_t ClockFilter; /*!< TIM clock filter.
bogdanm	92:4fc01daae5a5	222	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	92:4fc01daae5a5	223	}TIM_ClockConfigTypeDef;
bogdanm	92:4fc01daae5a5	224
bogdanm	92:4fc01daae5a5	225	/**
bogdanm	92:4fc01daae5a5	226	* @brief Clear Input Configuration Handle Structure definition
bogdanm	92:4fc01daae5a5	227	*/
bogdanm	92:4fc01daae5a5	228	typedef struct
bogdanm	92:4fc01daae5a5	229	{
bogdanm	92:4fc01daae5a5	230	uint32_t ClearInputState; /*!< TIM clear Input state.
bogdanm	92:4fc01daae5a5	231	This parameter can be ENABLE or DISABLE */
bogdanm	92:4fc01daae5a5	232	uint32_t ClearInputSource; /*!< TIM clear Input sources.
bogdanm	92:4fc01daae5a5	233	This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm	92:4fc01daae5a5	234	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
bogdanm	92:4fc01daae5a5	235	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	92:4fc01daae5a5	236	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
bogdanm	92:4fc01daae5a5	237	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	92:4fc01daae5a5	238	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
bogdanm	92:4fc01daae5a5	239	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	92:4fc01daae5a5	240	}TIM_ClearInputConfigTypeDef;
bogdanm	92:4fc01daae5a5	241
bogdanm	92:4fc01daae5a5	242	/**
bogdanm	92:4fc01daae5a5	243	* @brief TIM Slave configuration Structure definition
bogdanm	92:4fc01daae5a5	244	*/
bogdanm	92:4fc01daae5a5	245	typedef struct {
bogdanm	92:4fc01daae5a5	246	uint32_t SlaveMode; /*!< Slave mode selection
bogdanm	92:4fc01daae5a5	247	This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm	92:4fc01daae5a5	248	uint32_t InputTrigger; /*!< Input Trigger source
bogdanm	92:4fc01daae5a5	249	This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm	92:4fc01daae5a5	250	uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm	92:4fc01daae5a5	251	This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm	92:4fc01daae5a5	252	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm	92:4fc01daae5a5	253	This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm	92:4fc01daae5a5	254	uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm	92:4fc01daae5a5	255	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	92:4fc01daae5a5	256
bogdanm	92:4fc01daae5a5	257	}TIM_SlaveConfigTypeDef;
bogdanm	92:4fc01daae5a5	258
bogdanm	92:4fc01daae5a5	259	/**
bogdanm	92:4fc01daae5a5	260	* @brief HAL State structures definition
bogdanm	92:4fc01daae5a5	261	*/
bogdanm	92:4fc01daae5a5	262	typedef enum
bogdanm	92:4fc01daae5a5	263	{
bogdanm	92:4fc01daae5a5	264	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
bogdanm	92:4fc01daae5a5	265	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	92:4fc01daae5a5	266	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	92:4fc01daae5a5	267	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	92:4fc01daae5a5	268	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	92:4fc01daae5a5	269	}HAL_TIM_StateTypeDef;
bogdanm	92:4fc01daae5a5	270
bogdanm	92:4fc01daae5a5	271	/**
bogdanm	92:4fc01daae5a5	272	* @brief HAL Active channel structures definition
bogdanm	92:4fc01daae5a5	273	*/
bogdanm	92:4fc01daae5a5	274	typedef enum
bogdanm	92:4fc01daae5a5	275	{
bogdanm	92:4fc01daae5a5	276	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
bogdanm	92:4fc01daae5a5	277	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
bogdanm	92:4fc01daae5a5	278	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
bogdanm	92:4fc01daae5a5	279	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
bogdanm	92:4fc01daae5a5	280	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
bogdanm	92:4fc01daae5a5	281	}HAL_TIM_ActiveChannel;
bogdanm	92:4fc01daae5a5	282
bogdanm	92:4fc01daae5a5	283	/**
bogdanm	92:4fc01daae5a5	284	* @brief TIM Time Base Handle Structure definition
bogdanm	92:4fc01daae5a5	285	*/
bogdanm	92:4fc01daae5a5	286	typedef struct
bogdanm	92:4fc01daae5a5	287	{
bogdanm	92:4fc01daae5a5	288	TIM_TypeDef Instance; /!< Register base address */
bogdanm	92:4fc01daae5a5	289	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
bogdanm	92:4fc01daae5a5	290	HAL_TIM_ActiveChannel Channel; /!< Active channel /
bogdanm	92:4fc01daae5a5	291	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
bogdanm	92:4fc01daae5a5	292	This array is accessed by a @ref DMA_Handle_index */
bogdanm	92:4fc01daae5a5	293	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	92:4fc01daae5a5	294	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
bogdanm	92:4fc01daae5a5	295	}TIM_HandleTypeDef;
bogdanm	92:4fc01daae5a5	296
bogdanm	92:4fc01daae5a5	297	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	298	/** @defgroup TIM_Exported_Constants
bogdanm	92:4fc01daae5a5	299	* @{
bogdanm	92:4fc01daae5a5	300	*/
bogdanm	92:4fc01daae5a5	301
bogdanm	92:4fc01daae5a5	302	/** @defgroup TIM_Input_Channel_Polarity
bogdanm	92:4fc01daae5a5	303	* @{
bogdanm	92:4fc01daae5a5	304	*/
bogdanm	92:4fc01daae5a5	305	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
bogdanm	92:4fc01daae5a5	306	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
bogdanm	92:4fc01daae5a5	307	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
bogdanm	92:4fc01daae5a5	308	/**
bogdanm	92:4fc01daae5a5	309	* @}
bogdanm	92:4fc01daae5a5	310	*/
bogdanm	92:4fc01daae5a5	311
bogdanm	92:4fc01daae5a5	312	/** @defgroup TIM_ETR_Polarity
bogdanm	92:4fc01daae5a5	313	* @{
bogdanm	92:4fc01daae5a5	314	*/
bogdanm	92:4fc01daae5a5	315	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
bogdanm	92:4fc01daae5a5	316	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
bogdanm	92:4fc01daae5a5	317	/**
bogdanm	92:4fc01daae5a5	318	* @}
bogdanm	92:4fc01daae5a5	319	*/
bogdanm	92:4fc01daae5a5	320
bogdanm	92:4fc01daae5a5	321	/** @defgroup TIM_ETR_Prescaler
bogdanm	92:4fc01daae5a5	322	* @{
bogdanm	92:4fc01daae5a5	323	*/
bogdanm	92:4fc01daae5a5	324	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
bogdanm	92:4fc01daae5a5	325	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
bogdanm	92:4fc01daae5a5	326	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
bogdanm	92:4fc01daae5a5	327	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
bogdanm	92:4fc01daae5a5	328	/**
bogdanm	92:4fc01daae5a5	329	* @}
bogdanm	92:4fc01daae5a5	330	*/
bogdanm	92:4fc01daae5a5	331
bogdanm	92:4fc01daae5a5	332	/** @defgroup TIM_Counter_Mode
bogdanm	92:4fc01daae5a5	333	* @{
bogdanm	92:4fc01daae5a5	334	*/
bogdanm	92:4fc01daae5a5	335	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	336	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm	92:4fc01daae5a5	337	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm	92:4fc01daae5a5	338	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm	92:4fc01daae5a5	339	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm	92:4fc01daae5a5	340
bogdanm	92:4fc01daae5a5	341	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
bogdanm	92:4fc01daae5a5	342	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
bogdanm	92:4fc01daae5a5	343	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
bogdanm	92:4fc01daae5a5	344	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
bogdanm	92:4fc01daae5a5	345	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm	92:4fc01daae5a5	346	/**
bogdanm	92:4fc01daae5a5	347	* @}
bogdanm	92:4fc01daae5a5	348	*/
bogdanm	92:4fc01daae5a5	349
bogdanm	92:4fc01daae5a5	350	/** @defgroup TIM_ClockDivision
bogdanm	92:4fc01daae5a5	351	* @{
bogdanm	92:4fc01daae5a5	352	*/
bogdanm	92:4fc01daae5a5	353	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	354	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm	92:4fc01daae5a5	355	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm	92:4fc01daae5a5	356
bogdanm	92:4fc01daae5a5	357	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
bogdanm	92:4fc01daae5a5	358	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
bogdanm	92:4fc01daae5a5	359	((DIV) == TIM_CLOCKDIVISION_DIV4))
bogdanm	92:4fc01daae5a5	360	/**
bogdanm	92:4fc01daae5a5	361	* @}
bogdanm	92:4fc01daae5a5	362	*/
bogdanm	92:4fc01daae5a5	363
bogdanm	92:4fc01daae5a5	364	/** @defgroup TIM_Output_Compare_and_PWM_modes
bogdanm	92:4fc01daae5a5	365	* @{
bogdanm	92:4fc01daae5a5	366	*/
bogdanm	92:4fc01daae5a5	367	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	368	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm	92:4fc01daae5a5	369	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm	92:4fc01daae5a5	370	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
bogdanm	92:4fc01daae5a5	371	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
bogdanm	92:4fc01daae5a5	372	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm	92:4fc01daae5a5	373	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
bogdanm	92:4fc01daae5a5	374	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm	92:4fc01daae5a5	375
bogdanm	92:4fc01daae5a5	376	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
bogdanm	92:4fc01daae5a5	377	((MODE) == TIM_OCMODE_PWM2))
bogdanm	92:4fc01daae5a5	378
bogdanm	92:4fc01daae5a5	379	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
bogdanm	92:4fc01daae5a5	380	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
bogdanm	92:4fc01daae5a5	381	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
bogdanm	92:4fc01daae5a5	382	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
bogdanm	92:4fc01daae5a5	383	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
bogdanm	92:4fc01daae5a5	384	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm	92:4fc01daae5a5	385	/**
bogdanm	92:4fc01daae5a5	386	* @}
bogdanm	92:4fc01daae5a5	387	*/
bogdanm	92:4fc01daae5a5	388
bogdanm	92:4fc01daae5a5	389	/** @defgroup TIM_Output_Compare_State
bogdanm	92:4fc01daae5a5	390	* @{
bogdanm	92:4fc01daae5a5	391	*/
bogdanm	92:4fc01daae5a5	392	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	393	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm	92:4fc01daae5a5	394
bogdanm	92:4fc01daae5a5	395	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	396	((STATE) == TIM_OUTPUTSTATE_ENABLE))
bogdanm	92:4fc01daae5a5	397	/**
bogdanm	92:4fc01daae5a5	398	* @}
bogdanm	92:4fc01daae5a5	399	*/
bogdanm	92:4fc01daae5a5	400
bogdanm	92:4fc01daae5a5	401	/** @defgroup TIM_Output_Fast_State
bogdanm	92:4fc01daae5a5	402	* @{
bogdanm	92:4fc01daae5a5	403	*/
bogdanm	92:4fc01daae5a5	404	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	405	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm	92:4fc01daae5a5	406
bogdanm	92:4fc01daae5a5	407	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	408	((STATE) == TIM_OCFAST_ENABLE))
bogdanm	92:4fc01daae5a5	409	/**
bogdanm	92:4fc01daae5a5	410	* @}
bogdanm	92:4fc01daae5a5	411	*/
bogdanm	92:4fc01daae5a5	412
bogdanm	92:4fc01daae5a5	413	/** @defgroup TIM_Output_Compare_N_State
bogdanm	92:4fc01daae5a5	414	* @{
bogdanm	92:4fc01daae5a5	415	*/
bogdanm	92:4fc01daae5a5	416	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	417	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm	92:4fc01daae5a5	418
bogdanm	92:4fc01daae5a5	419	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	420	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
bogdanm	92:4fc01daae5a5	421	/**
bogdanm	92:4fc01daae5a5	422	* @}
bogdanm	92:4fc01daae5a5	423	*/
bogdanm	92:4fc01daae5a5	424
bogdanm	92:4fc01daae5a5	425	/** @defgroup TIM_Output_Compare_Polarity
bogdanm	92:4fc01daae5a5	426	* @{
bogdanm	92:4fc01daae5a5	427	*/
bogdanm	92:4fc01daae5a5	428	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	429	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm	92:4fc01daae5a5	430
bogdanm	92:4fc01daae5a5	431	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
bogdanm	92:4fc01daae5a5	432	((POLARITY) == TIM_OCPOLARITY_LOW))
bogdanm	92:4fc01daae5a5	433	/**
bogdanm	92:4fc01daae5a5	434	* @}
bogdanm	92:4fc01daae5a5	435	*/
bogdanm	92:4fc01daae5a5	436
bogdanm	92:4fc01daae5a5	437	/** @defgroup TIM_Output_Compare_N_Polarity
bogdanm	92:4fc01daae5a5	438	* @{
bogdanm	92:4fc01daae5a5	439	*/
bogdanm	92:4fc01daae5a5	440	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	441	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm	92:4fc01daae5a5	442
bogdanm	92:4fc01daae5a5	443	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
bogdanm	92:4fc01daae5a5	444	((POLARITY) == TIM_OCNPOLARITY_LOW))
bogdanm	92:4fc01daae5a5	445	/**
bogdanm	92:4fc01daae5a5	446	* @}
bogdanm	92:4fc01daae5a5	447	*/
bogdanm	92:4fc01daae5a5	448
bogdanm	92:4fc01daae5a5	449	/** @defgroup TIM_Output_Compare_Idle_State
bogdanm	92:4fc01daae5a5	450	* @{
bogdanm	92:4fc01daae5a5	451	*/
bogdanm	92:4fc01daae5a5	452	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm	92:4fc01daae5a5	453	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	454	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
bogdanm	92:4fc01daae5a5	455	((STATE) == TIM_OCIDLESTATE_RESET))
bogdanm	92:4fc01daae5a5	456	/**
bogdanm	92:4fc01daae5a5	457	* @}
bogdanm	92:4fc01daae5a5	458	*/
bogdanm	92:4fc01daae5a5	459
bogdanm	92:4fc01daae5a5	460	/** @defgroup TIM_Output_Compare_N_Idle_State
bogdanm	92:4fc01daae5a5	461	* @{
bogdanm	92:4fc01daae5a5	462	*/
bogdanm	92:4fc01daae5a5	463	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
bogdanm	92:4fc01daae5a5	464	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	465	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
bogdanm	92:4fc01daae5a5	466	((STATE) == TIM_OCNIDLESTATE_RESET))
bogdanm	92:4fc01daae5a5	467	/**
bogdanm	92:4fc01daae5a5	468	* @}
bogdanm	92:4fc01daae5a5	469	*/
bogdanm	92:4fc01daae5a5	470
bogdanm	92:4fc01daae5a5	471	/** @defgroup TIM_Channel
bogdanm	92:4fc01daae5a5	472	* @{
bogdanm	92:4fc01daae5a5	473	*/
bogdanm	92:4fc01daae5a5	474	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	475	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	92:4fc01daae5a5	476	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm	92:4fc01daae5a5	477	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm	92:4fc01daae5a5	478	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm	92:4fc01daae5a5	479
bogdanm	92:4fc01daae5a5	480	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	92:4fc01daae5a5	481	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	92:4fc01daae5a5	482	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	92:4fc01daae5a5	483	((CHANNEL) == TIM_CHANNEL_4) \|\| \
bogdanm	92:4fc01daae5a5	484	((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm	92:4fc01daae5a5	485
bogdanm	92:4fc01daae5a5	486	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	92:4fc01daae5a5	487	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	92:4fc01daae5a5	488
bogdanm	92:4fc01daae5a5	489	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	92:4fc01daae5a5	490	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	92:4fc01daae5a5	491
bogdanm	92:4fc01daae5a5	492	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	92:4fc01daae5a5	493	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	92:4fc01daae5a5	494	((CHANNEL) == TIM_CHANNEL_3))
bogdanm	92:4fc01daae5a5	495	/**
bogdanm	92:4fc01daae5a5	496	* @}
bogdanm	92:4fc01daae5a5	497	*/
bogdanm	92:4fc01daae5a5	498
bogdanm	92:4fc01daae5a5	499	/** @defgroup TIM_Input_Capture_Polarity
bogdanm	92:4fc01daae5a5	500	* @{
bogdanm	92:4fc01daae5a5	501	*/
bogdanm	92:4fc01daae5a5	502	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm	92:4fc01daae5a5	503	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm	92:4fc01daae5a5	504	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm	92:4fc01daae5a5	505
bogdanm	92:4fc01daae5a5	506	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
bogdanm	92:4fc01daae5a5	507	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
bogdanm	92:4fc01daae5a5	508	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm	92:4fc01daae5a5	509	/**
bogdanm	92:4fc01daae5a5	510	* @}
bogdanm	92:4fc01daae5a5	511	*/
bogdanm	92:4fc01daae5a5	512
bogdanm	92:4fc01daae5a5	513	/** @defgroup TIM_Input_Capture_Selection
bogdanm	92:4fc01daae5a5	514	* @{
bogdanm	92:4fc01daae5a5	515	*/
bogdanm	92:4fc01daae5a5	516	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	92:4fc01daae5a5	517	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	92:4fc01daae5a5	518	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	92:4fc01daae5a5	519	connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm	92:4fc01daae5a5	520	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
bogdanm	92:4fc01daae5a5	521
bogdanm	92:4fc01daae5a5	522	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
bogdanm	92:4fc01daae5a5	523	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
bogdanm	92:4fc01daae5a5	524	((SELECTION) == TIM_ICSELECTION_TRC))
bogdanm	92:4fc01daae5a5	525	/**
bogdanm	92:4fc01daae5a5	526	* @}
bogdanm	92:4fc01daae5a5	527	*/
bogdanm	92:4fc01daae5a5	528
bogdanm	92:4fc01daae5a5	529	/** @defgroup TIM_Input_Capture_Prescaler
bogdanm	92:4fc01daae5a5	530	* @{
bogdanm	92:4fc01daae5a5	531	*/
bogdanm	92:4fc01daae5a5	532	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
bogdanm	92:4fc01daae5a5	533	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
bogdanm	92:4fc01daae5a5	534	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
bogdanm	92:4fc01daae5a5	535	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
bogdanm	92:4fc01daae5a5	536
bogdanm	92:4fc01daae5a5	537	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
bogdanm	92:4fc01daae5a5	538	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
bogdanm	92:4fc01daae5a5	539	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
bogdanm	92:4fc01daae5a5	540	((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm	92:4fc01daae5a5	541	/**
bogdanm	92:4fc01daae5a5	542	* @}
bogdanm	92:4fc01daae5a5	543	*/
bogdanm	92:4fc01daae5a5	544
bogdanm	92:4fc01daae5a5	545	/** @defgroup TIM_One_Pulse_Mode
bogdanm	92:4fc01daae5a5	546	* @{
bogdanm	92:4fc01daae5a5	547	*/
bogdanm	92:4fc01daae5a5	548	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm	92:4fc01daae5a5	549	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	550	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
bogdanm	92:4fc01daae5a5	551	((MODE) == TIM_OPMODE_REPETITIVE))
bogdanm	92:4fc01daae5a5	552	/**
bogdanm	92:4fc01daae5a5	553	* @}
bogdanm	92:4fc01daae5a5	554	*/
bogdanm	92:4fc01daae5a5	555
bogdanm	92:4fc01daae5a5	556	/** @defgroup TIM_Encoder_Mode
bogdanm	92:4fc01daae5a5	557	* @{
bogdanm	92:4fc01daae5a5	558	*/
bogdanm	92:4fc01daae5a5	559	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm	92:4fc01daae5a5	560	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm	92:4fc01daae5a5	561	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
bogdanm	92:4fc01daae5a5	562	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
bogdanm	92:4fc01daae5a5	563	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
bogdanm	92:4fc01daae5a5	564	((MODE) == TIM_ENCODERMODE_TI12))
bogdanm	92:4fc01daae5a5	565	/**
bogdanm	92:4fc01daae5a5	566	* @}
bogdanm	92:4fc01daae5a5	567	*/
bogdanm	92:4fc01daae5a5	568
bogdanm	92:4fc01daae5a5	569	/** @defgroup TIM_Interrupt_definition
bogdanm	92:4fc01daae5a5	570	* @{
bogdanm	92:4fc01daae5a5	571	*/
bogdanm	92:4fc01daae5a5	572	#define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm	92:4fc01daae5a5	573	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm	92:4fc01daae5a5	574	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm	92:4fc01daae5a5	575	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm	92:4fc01daae5a5	576	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm	92:4fc01daae5a5	577	#define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm	92:4fc01daae5a5	578	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm	92:4fc01daae5a5	579	#define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm	92:4fc01daae5a5	580
bogdanm	92:4fc01daae5a5	581	#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
bogdanm	92:4fc01daae5a5	582
bogdanm	92:4fc01daae5a5	583	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) \|\| \
bogdanm	92:4fc01daae5a5	584	((IT) == TIM_IT_CC1) \|\| \
bogdanm	92:4fc01daae5a5	585	((IT) == TIM_IT_CC2) \|\| \
bogdanm	92:4fc01daae5a5	586	((IT) == TIM_IT_CC3) \|\| \
bogdanm	92:4fc01daae5a5	587	((IT) == TIM_IT_CC4) \|\| \
bogdanm	92:4fc01daae5a5	588	((IT) == TIM_IT_COM) \|\| \
bogdanm	92:4fc01daae5a5	589	((IT) == TIM_IT_TRIGGER) \|\| \
bogdanm	92:4fc01daae5a5	590	((IT) == TIM_IT_BREAK))
bogdanm	92:4fc01daae5a5	591	/**
bogdanm	92:4fc01daae5a5	592	* @}
bogdanm	92:4fc01daae5a5	593	*/
bogdanm	92:4fc01daae5a5	594	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm	92:4fc01daae5a5	595	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	596
bogdanm	92:4fc01daae5a5	597	/** @defgroup TIM_DMA_sources
bogdanm	92:4fc01daae5a5	598	* @{
bogdanm	92:4fc01daae5a5	599	*/
bogdanm	92:4fc01daae5a5	600	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm	92:4fc01daae5a5	601	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm	92:4fc01daae5a5	602	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm	92:4fc01daae5a5	603	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm	92:4fc01daae5a5	604	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm	92:4fc01daae5a5	605	#define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm	92:4fc01daae5a5	606	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm	92:4fc01daae5a5	607	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	92:4fc01daae5a5	608	/**
bogdanm	92:4fc01daae5a5	609	* @}
bogdanm	92:4fc01daae5a5	610	*/
bogdanm	92:4fc01daae5a5	611
bogdanm	92:4fc01daae5a5	612	/** @defgroup TIM_Event_Source
bogdanm	92:4fc01daae5a5	613	* @{
bogdanm	92:4fc01daae5a5	614	*/
bogdanm	92:4fc01daae5a5	615	#define TIM_EventSource_Update TIM_EGR_UG
bogdanm	92:4fc01daae5a5	616	#define TIM_EventSource_CC1 TIM_EGR_CC1G
bogdanm	92:4fc01daae5a5	617	#define TIM_EventSource_CC2 TIM_EGR_CC2G
bogdanm	92:4fc01daae5a5	618	#define TIM_EventSource_CC3 TIM_EGR_CC3G
bogdanm	92:4fc01daae5a5	619	#define TIM_EventSource_CC4 TIM_EGR_CC4G
bogdanm	92:4fc01daae5a5	620	#define TIM_EventSource_COM TIM_EGR_COMG
bogdanm	92:4fc01daae5a5	621	#define TIM_EventSource_Trigger TIM_EGR_TG
bogdanm	92:4fc01daae5a5	622	#define TIM_EventSource_Break TIM_EGR_BG
bogdanm	92:4fc01daae5a5	623	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	92:4fc01daae5a5	624	/**
bogdanm	92:4fc01daae5a5	625	* @}
bogdanm	92:4fc01daae5a5	626	*/
bogdanm	92:4fc01daae5a5	627
bogdanm	92:4fc01daae5a5	628	/** @defgroup TIM_Flag_definition
bogdanm	92:4fc01daae5a5	629	* @{
bogdanm	92:4fc01daae5a5	630	*/
bogdanm	92:4fc01daae5a5	631	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm	92:4fc01daae5a5	632	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm	92:4fc01daae5a5	633	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm	92:4fc01daae5a5	634	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm	92:4fc01daae5a5	635	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm	92:4fc01daae5a5	636	#define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm	92:4fc01daae5a5	637	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm	92:4fc01daae5a5	638	#define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm	92:4fc01daae5a5	639	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm	92:4fc01daae5a5	640	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm	92:4fc01daae5a5	641	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm	92:4fc01daae5a5	642	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm	92:4fc01daae5a5	643
bogdanm	92:4fc01daae5a5	644	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
bogdanm	92:4fc01daae5a5	645	((FLAG) == TIM_FLAG_CC1) \|\| \
bogdanm	92:4fc01daae5a5	646	((FLAG) == TIM_FLAG_CC2) \|\| \
bogdanm	92:4fc01daae5a5	647	((FLAG) == TIM_FLAG_CC3) \|\| \
bogdanm	92:4fc01daae5a5	648	((FLAG) == TIM_FLAG_CC4) \|\| \
bogdanm	92:4fc01daae5a5	649	((FLAG) == TIM_FLAG_COM) \|\| \
bogdanm	92:4fc01daae5a5	650	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
bogdanm	92:4fc01daae5a5	651	((FLAG) == TIM_FLAG_BREAK) \|\| \
bogdanm	92:4fc01daae5a5	652	((FLAG) == TIM_FLAG_CC1OF) \|\| \
bogdanm	92:4fc01daae5a5	653	((FLAG) == TIM_FLAG_CC2OF) \|\| \
bogdanm	92:4fc01daae5a5	654	((FLAG) == TIM_FLAG_CC3OF) \|\| \
bogdanm	92:4fc01daae5a5	655	((FLAG) == TIM_FLAG_CC4OF))
bogdanm	92:4fc01daae5a5	656	/**
bogdanm	92:4fc01daae5a5	657	* @}
bogdanm	92:4fc01daae5a5	658	*/
bogdanm	92:4fc01daae5a5	659
bogdanm	92:4fc01daae5a5	660	/** @defgroup TIM_Clock_Source
bogdanm	92:4fc01daae5a5	661	* @{
bogdanm	92:4fc01daae5a5	662	*/
bogdanm	92:4fc01daae5a5	663	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm	92:4fc01daae5a5	664	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm	92:4fc01daae5a5	665	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	666	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm	92:4fc01daae5a5	667	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm	92:4fc01daae5a5	668	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
bogdanm	92:4fc01daae5a5	669	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm	92:4fc01daae5a5	670	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
bogdanm	92:4fc01daae5a5	671	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
bogdanm	92:4fc01daae5a5	672	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm	92:4fc01daae5a5	673
bogdanm	92:4fc01daae5a5	674	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
bogdanm	92:4fc01daae5a5	675	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
bogdanm	92:4fc01daae5a5	676	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
bogdanm	92:4fc01daae5a5	677	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
bogdanm	92:4fc01daae5a5	678	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
bogdanm	92:4fc01daae5a5	679	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
bogdanm	92:4fc01daae5a5	680	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
bogdanm	92:4fc01daae5a5	681	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
bogdanm	92:4fc01daae5a5	682	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
bogdanm	92:4fc01daae5a5	683	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm	92:4fc01daae5a5	684	/**
bogdanm	92:4fc01daae5a5	685	* @}
bogdanm	92:4fc01daae5a5	686	*/
bogdanm	92:4fc01daae5a5	687
bogdanm	92:4fc01daae5a5	688	/** @defgroup TIM_Clock_Polarity
bogdanm	92:4fc01daae5a5	689	* @{
bogdanm	92:4fc01daae5a5	690	*/
bogdanm	92:4fc01daae5a5	691	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
bogdanm	92:4fc01daae5a5	692	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
bogdanm	92:4fc01daae5a5	693	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
bogdanm	92:4fc01daae5a5	694	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
bogdanm	92:4fc01daae5a5	695	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
bogdanm	92:4fc01daae5a5	696
bogdanm	92:4fc01daae5a5	697	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
bogdanm	92:4fc01daae5a5	698	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
bogdanm	92:4fc01daae5a5	699	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
bogdanm	92:4fc01daae5a5	700	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
bogdanm	92:4fc01daae5a5	701	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm	92:4fc01daae5a5	702	/**
bogdanm	92:4fc01daae5a5	703	* @}
bogdanm	92:4fc01daae5a5	704	*/
bogdanm	92:4fc01daae5a5	705
bogdanm	92:4fc01daae5a5	706	/** @defgroup TIM_Clock_Prescaler
bogdanm	92:4fc01daae5a5	707	* @{
bogdanm	92:4fc01daae5a5	708	*/
bogdanm	92:4fc01daae5a5	709	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	92:4fc01daae5a5	710	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
bogdanm	92:4fc01daae5a5	711	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
bogdanm	92:4fc01daae5a5	712	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
bogdanm	92:4fc01daae5a5	713
bogdanm	92:4fc01daae5a5	714	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
bogdanm	92:4fc01daae5a5	715	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
bogdanm	92:4fc01daae5a5	716	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
bogdanm	92:4fc01daae5a5	717	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
bogdanm	92:4fc01daae5a5	718	/**
bogdanm	92:4fc01daae5a5	719	* @}
bogdanm	92:4fc01daae5a5	720	*/
bogdanm	92:4fc01daae5a5	721
bogdanm	92:4fc01daae5a5	722	/** @defgroup TIM_Clock_Filter
bogdanm	92:4fc01daae5a5	723	* @{
bogdanm	92:4fc01daae5a5	724	*/
bogdanm	92:4fc01daae5a5	725	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	92:4fc01daae5a5	726	/**
bogdanm	92:4fc01daae5a5	727	* @}
bogdanm	92:4fc01daae5a5	728	*/
bogdanm	92:4fc01daae5a5	729
bogdanm	92:4fc01daae5a5	730	/** @defgroup TIM_ClearInput_Source
bogdanm	92:4fc01daae5a5	731	* @{
bogdanm	92:4fc01daae5a5	732	*/
bogdanm	92:4fc01daae5a5	733	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm	92:4fc01daae5a5	734	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	735
bogdanm	92:4fc01daae5a5	736	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
bogdanm	92:4fc01daae5a5	737	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
bogdanm	92:4fc01daae5a5	738	/**
bogdanm	92:4fc01daae5a5	739	* @}
bogdanm	92:4fc01daae5a5	740	*/
bogdanm	92:4fc01daae5a5	741
bogdanm	92:4fc01daae5a5	742	/** @defgroup TIM_ClearInput_Polarity
bogdanm	92:4fc01daae5a5	743	* @{
bogdanm	92:4fc01daae5a5	744	*/
bogdanm	92:4fc01daae5a5	745	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
bogdanm	92:4fc01daae5a5	746	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
bogdanm	92:4fc01daae5a5	747	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
bogdanm	92:4fc01daae5a5	748	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm	92:4fc01daae5a5	749	/**
bogdanm	92:4fc01daae5a5	750	* @}
bogdanm	92:4fc01daae5a5	751	*/
bogdanm	92:4fc01daae5a5	752
bogdanm	92:4fc01daae5a5	753	/** @defgroup TIM_ClearInput_Prescaler
bogdanm	92:4fc01daae5a5	754	* @{
bogdanm	92:4fc01daae5a5	755	*/
bogdanm	92:4fc01daae5a5	756	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	92:4fc01daae5a5	757	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
bogdanm	92:4fc01daae5a5	758	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
bogdanm	92:4fc01daae5a5	759	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
bogdanm	92:4fc01daae5a5	760	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
bogdanm	92:4fc01daae5a5	761	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
bogdanm	92:4fc01daae5a5	762	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
bogdanm	92:4fc01daae5a5	763	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm	92:4fc01daae5a5	764	/**
bogdanm	92:4fc01daae5a5	765	* @}
bogdanm	92:4fc01daae5a5	766	*/
bogdanm	92:4fc01daae5a5	767
bogdanm	92:4fc01daae5a5	768	/** @defgroup TIM_ClearInput_Filter
bogdanm	92:4fc01daae5a5	769	* @{
bogdanm	92:4fc01daae5a5	770	*/
bogdanm	92:4fc01daae5a5	771	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	92:4fc01daae5a5	772	/**
bogdanm	92:4fc01daae5a5	773	* @}
bogdanm	92:4fc01daae5a5	774	*/
bogdanm	92:4fc01daae5a5	775
bogdanm	92:4fc01daae5a5	776	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
bogdanm	92:4fc01daae5a5	777	* @{
bogdanm	92:4fc01daae5a5	778	*/
bogdanm	92:4fc01daae5a5	779	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm	92:4fc01daae5a5	780	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	781
bogdanm	92:4fc01daae5a5	782	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	783	((STATE) == TIM_OSSR_DISABLE))
bogdanm	92:4fc01daae5a5	784	/**
bogdanm	92:4fc01daae5a5	785	* @}
bogdanm	92:4fc01daae5a5	786	*/
bogdanm	92:4fc01daae5a5	787
bogdanm	92:4fc01daae5a5	788	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
bogdanm	92:4fc01daae5a5	789	* @{
bogdanm	92:4fc01daae5a5	790	*/
bogdanm	92:4fc01daae5a5	791	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm	92:4fc01daae5a5	792	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	793
bogdanm	92:4fc01daae5a5	794	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	795	((STATE) == TIM_OSSI_DISABLE))
bogdanm	92:4fc01daae5a5	796	/**
bogdanm	92:4fc01daae5a5	797	* @}
bogdanm	92:4fc01daae5a5	798	*/
bogdanm	92:4fc01daae5a5	799	/** @defgroup TIM_Lock_level
bogdanm	92:4fc01daae5a5	800	* @{
bogdanm	92:4fc01daae5a5	801	*/
bogdanm	92:4fc01daae5a5	802	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	803	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm	92:4fc01daae5a5	804	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm	92:4fc01daae5a5	805	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm	92:4fc01daae5a5	806
bogdanm	92:4fc01daae5a5	807	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
bogdanm	92:4fc01daae5a5	808	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
bogdanm	92:4fc01daae5a5	809	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
bogdanm	92:4fc01daae5a5	810	((LEVEL) == TIM_LOCKLEVEL_3))
bogdanm	92:4fc01daae5a5	811	/**
bogdanm	92:4fc01daae5a5	812	* @}
bogdanm	92:4fc01daae5a5	813	*/
bogdanm	92:4fc01daae5a5	814	/** @defgroup TIM_Break_Input_enable_disable
bogdanm	92:4fc01daae5a5	815	* @{
bogdanm	92:4fc01daae5a5	816	*/
bogdanm	92:4fc01daae5a5	817	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm	92:4fc01daae5a5	818	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	819
bogdanm	92:4fc01daae5a5	820	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	821	((STATE) == TIM_BREAK_DISABLE))
bogdanm	92:4fc01daae5a5	822	/**
bogdanm	92:4fc01daae5a5	823	* @}
bogdanm	92:4fc01daae5a5	824	*/
bogdanm	92:4fc01daae5a5	825	/** @defgroup TIM_Break_Polarity
bogdanm	92:4fc01daae5a5	826	* @{
bogdanm	92:4fc01daae5a5	827	*/
bogdanm	92:4fc01daae5a5	828	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	829	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm	92:4fc01daae5a5	830
bogdanm	92:4fc01daae5a5	831	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
bogdanm	92:4fc01daae5a5	832	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
bogdanm	92:4fc01daae5a5	833	/**
bogdanm	92:4fc01daae5a5	834	* @}
bogdanm	92:4fc01daae5a5	835	*/
bogdanm	92:4fc01daae5a5	836	/** @defgroup TIM_AOE_Bit_Set_Reset
bogdanm	92:4fc01daae5a5	837	* @{
bogdanm	92:4fc01daae5a5	838	*/
bogdanm	92:4fc01daae5a5	839	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm	92:4fc01daae5a5	840	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	841
bogdanm	92:4fc01daae5a5	842	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	843	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm	92:4fc01daae5a5	844	/**
bogdanm	92:4fc01daae5a5	845	* @}
bogdanm	92:4fc01daae5a5	846	*/
bogdanm	92:4fc01daae5a5	847
bogdanm	92:4fc01daae5a5	848	/** @defgroup TIM_Master_Mode_Selection
bogdanm	92:4fc01daae5a5	849	* @{
bogdanm	92:4fc01daae5a5	850	*/
bogdanm	92:4fc01daae5a5	851	#define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	852	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm	92:4fc01daae5a5	853	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm	92:4fc01daae5a5	854	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	92:4fc01daae5a5	855	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm	92:4fc01daae5a5	856	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
bogdanm	92:4fc01daae5a5	857	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
bogdanm	92:4fc01daae5a5	858	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	92:4fc01daae5a5	859
bogdanm	92:4fc01daae5a5	860	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
bogdanm	92:4fc01daae5a5	861	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	862	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
bogdanm	92:4fc01daae5a5	863	((SOURCE) == TIM_TRGO_OC1) \|\| \
bogdanm	92:4fc01daae5a5	864	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
bogdanm	92:4fc01daae5a5	865	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
bogdanm	92:4fc01daae5a5	866	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
bogdanm	92:4fc01daae5a5	867	((SOURCE) == TIM_TRGO_OC4REF))
bogdanm	92:4fc01daae5a5	868
bogdanm	92:4fc01daae5a5	869
bogdanm	92:4fc01daae5a5	870	/**
bogdanm	92:4fc01daae5a5	871	* @}
bogdanm	92:4fc01daae5a5	872	*/
bogdanm	92:4fc01daae5a5	873	/** @defgroup TIM_Slave_Mode
bogdanm	92:4fc01daae5a5	874	* @{
bogdanm	92:4fc01daae5a5	875	*/
bogdanm	92:4fc01daae5a5	876	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	877	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm	92:4fc01daae5a5	878	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm	92:4fc01daae5a5	879	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm	92:4fc01daae5a5	880	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm	92:4fc01daae5a5	881
bogdanm	92:4fc01daae5a5	882	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
bogdanm	92:4fc01daae5a5	883	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
bogdanm	92:4fc01daae5a5	884	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
bogdanm	92:4fc01daae5a5	885	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
bogdanm	92:4fc01daae5a5	886	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm	92:4fc01daae5a5	887	/**
bogdanm	92:4fc01daae5a5	888	* @}
bogdanm	92:4fc01daae5a5	889	*/
bogdanm	92:4fc01daae5a5	890
bogdanm	92:4fc01daae5a5	891	/** @defgroup TIM_Master_Slave_Mode
bogdanm	92:4fc01daae5a5	892	* @{
bogdanm	92:4fc01daae5a5	893	*/
bogdanm	92:4fc01daae5a5	894
bogdanm	92:4fc01daae5a5	895	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm	92:4fc01daae5a5	896	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	897	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	898	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm	92:4fc01daae5a5	899	/**
bogdanm	92:4fc01daae5a5	900	* @}
bogdanm	92:4fc01daae5a5	901	*/
bogdanm	92:4fc01daae5a5	902	/** @defgroup TIM_Trigger_Selection
bogdanm	92:4fc01daae5a5	903	* @{
bogdanm	92:4fc01daae5a5	904	*/
bogdanm	92:4fc01daae5a5	905	#define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	906	#define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm	92:4fc01daae5a5	907	#define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm	92:4fc01daae5a5	908	#define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm	92:4fc01daae5a5	909	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm	92:4fc01daae5a5	910	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm	92:4fc01daae5a5	911	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm	92:4fc01daae5a5	912	#define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm	92:4fc01daae5a5	913	#define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm	92:4fc01daae5a5	914	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	92:4fc01daae5a5	915	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	92:4fc01daae5a5	916	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	92:4fc01daae5a5	917	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	92:4fc01daae5a5	918	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
bogdanm	92:4fc01daae5a5	919	((SELECTION) == TIM_TS_TI1FP1) \|\| \
bogdanm	92:4fc01daae5a5	920	((SELECTION) == TIM_TS_TI2FP2) \|\| \
bogdanm	92:4fc01daae5a5	921	((SELECTION) == TIM_TS_ETRF))
bogdanm	92:4fc01daae5a5	922	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	92:4fc01daae5a5	923	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	92:4fc01daae5a5	924	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	92:4fc01daae5a5	925	((SELECTION) == TIM_TS_ITR3))
bogdanm	92:4fc01daae5a5	926	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	92:4fc01daae5a5	927	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	92:4fc01daae5a5	928	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	92:4fc01daae5a5	929	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	92:4fc01daae5a5	930	((SELECTION) == TIM_TS_NONE))
bogdanm	92:4fc01daae5a5	931	/**
bogdanm	92:4fc01daae5a5	932	* @}
bogdanm	92:4fc01daae5a5	933	*/
bogdanm	92:4fc01daae5a5	934
bogdanm	92:4fc01daae5a5	935	/** @defgroup TIM_Trigger_Polarity
bogdanm	92:4fc01daae5a5	936	* @{
bogdanm	92:4fc01daae5a5	937	*/
bogdanm	92:4fc01daae5a5	938	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
bogdanm	92:4fc01daae5a5	939	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
bogdanm	92:4fc01daae5a5	940	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	92:4fc01daae5a5	941	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	92:4fc01daae5a5	942	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	92:4fc01daae5a5	943
bogdanm	92:4fc01daae5a5	944	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
bogdanm	92:4fc01daae5a5	945	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
bogdanm	92:4fc01daae5a5	946	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
bogdanm	92:4fc01daae5a5	947	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
bogdanm	92:4fc01daae5a5	948	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm	92:4fc01daae5a5	949	/**
bogdanm	92:4fc01daae5a5	950	* @}
bogdanm	92:4fc01daae5a5	951	*/
bogdanm	92:4fc01daae5a5	952
bogdanm	92:4fc01daae5a5	953	/** @defgroup TIM_Trigger_Prescaler
bogdanm	92:4fc01daae5a5	954	* @{
bogdanm	92:4fc01daae5a5	955	*/
bogdanm	92:4fc01daae5a5	956	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	92:4fc01daae5a5	957	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
bogdanm	92:4fc01daae5a5	958	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
bogdanm	92:4fc01daae5a5	959	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
bogdanm	92:4fc01daae5a5	960
bogdanm	92:4fc01daae5a5	961	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
bogdanm	92:4fc01daae5a5	962	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
bogdanm	92:4fc01daae5a5	963	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
bogdanm	92:4fc01daae5a5	964	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm	92:4fc01daae5a5	965	/**
bogdanm	92:4fc01daae5a5	966	* @}
bogdanm	92:4fc01daae5a5	967	*/
bogdanm	92:4fc01daae5a5	968
bogdanm	92:4fc01daae5a5	969	/** @defgroup TIM_Trigger_Filter
bogdanm	92:4fc01daae5a5	970	* @{
bogdanm	92:4fc01daae5a5	971	*/
bogdanm	92:4fc01daae5a5	972	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	92:4fc01daae5a5	973	/**
bogdanm	92:4fc01daae5a5	974	* @}
bogdanm	92:4fc01daae5a5	975	*/
bogdanm	92:4fc01daae5a5	976
bogdanm	92:4fc01daae5a5	977	/** @defgroup TIM_TI1_Selection
bogdanm	92:4fc01daae5a5	978	* @{
bogdanm	92:4fc01daae5a5	979	*/
bogdanm	92:4fc01daae5a5	980	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	981	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm	92:4fc01daae5a5	982
bogdanm	92:4fc01daae5a5	983	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
bogdanm	92:4fc01daae5a5	984	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm	92:4fc01daae5a5	985	/**
bogdanm	92:4fc01daae5a5	986	* @}
bogdanm	92:4fc01daae5a5	987	*/
bogdanm	92:4fc01daae5a5	988
bogdanm	92:4fc01daae5a5	989	/** @defgroup TIM_DMA_Base_address
bogdanm	92:4fc01daae5a5	990	* @{
bogdanm	92:4fc01daae5a5	991	*/
bogdanm	92:4fc01daae5a5	992	#define TIM_DMABase_CR1 (0x00000000)
bogdanm	92:4fc01daae5a5	993	#define TIM_DMABase_CR2 (0x00000001)
bogdanm	92:4fc01daae5a5	994	#define TIM_DMABase_SMCR (0x00000002)
bogdanm	92:4fc01daae5a5	995	#define TIM_DMABase_DIER (0x00000003)
bogdanm	92:4fc01daae5a5	996	#define TIM_DMABase_SR (0x00000004)
bogdanm	92:4fc01daae5a5	997	#define TIM_DMABase_EGR (0x00000005)
bogdanm	92:4fc01daae5a5	998	#define TIM_DMABase_CCMR1 (0x00000006)
bogdanm	92:4fc01daae5a5	999	#define TIM_DMABase_CCMR2 (0x00000007)
bogdanm	92:4fc01daae5a5	1000	#define TIM_DMABase_CCER (0x00000008)
bogdanm	92:4fc01daae5a5	1001	#define TIM_DMABase_CNT (0x00000009)
bogdanm	92:4fc01daae5a5	1002	#define TIM_DMABase_PSC (0x0000000A)
bogdanm	92:4fc01daae5a5	1003	#define TIM_DMABase_ARR (0x0000000B)
bogdanm	92:4fc01daae5a5	1004	#define TIM_DMABase_RCR (0x0000000C)
bogdanm	92:4fc01daae5a5	1005	#define TIM_DMABase_CCR1 (0x0000000D)
bogdanm	92:4fc01daae5a5	1006	#define TIM_DMABase_CCR2 (0x0000000E)
bogdanm	92:4fc01daae5a5	1007	#define TIM_DMABase_CCR3 (0x0000000F)
bogdanm	92:4fc01daae5a5	1008	#define TIM_DMABase_CCR4 (0x00000010)
bogdanm	92:4fc01daae5a5	1009	#define TIM_DMABase_BDTR (0x00000011)
bogdanm	92:4fc01daae5a5	1010	#define TIM_DMABase_DCR (0x00000012)
bogdanm	92:4fc01daae5a5	1011	#define TIM_DMABase_OR (0x00000013)
bogdanm	92:4fc01daae5a5	1012	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
bogdanm	92:4fc01daae5a5	1013	((BASE) == TIM_DMABase_CR2) \|\| \
bogdanm	92:4fc01daae5a5	1014	((BASE) == TIM_DMABase_SMCR) \|\| \
bogdanm	92:4fc01daae5a5	1015	((BASE) == TIM_DMABase_DIER) \|\| \
bogdanm	92:4fc01daae5a5	1016	((BASE) == TIM_DMABase_SR) \|\| \
bogdanm	92:4fc01daae5a5	1017	((BASE) == TIM_DMABase_EGR) \|\| \
bogdanm	92:4fc01daae5a5	1018	((BASE) == TIM_DMABase_CCMR1) \|\| \
bogdanm	92:4fc01daae5a5	1019	((BASE) == TIM_DMABase_CCMR2) \|\| \
bogdanm	92:4fc01daae5a5	1020	((BASE) == TIM_DMABase_CCER) \|\| \
bogdanm	92:4fc01daae5a5	1021	((BASE) == TIM_DMABase_CNT) \|\| \
bogdanm	92:4fc01daae5a5	1022	((BASE) == TIM_DMABase_PSC) \|\| \
bogdanm	92:4fc01daae5a5	1023	((BASE) == TIM_DMABase_ARR) \|\| \
bogdanm	92:4fc01daae5a5	1024	((BASE) == TIM_DMABase_RCR) \|\| \
bogdanm	92:4fc01daae5a5	1025	((BASE) == TIM_DMABase_CCR1) \|\| \
bogdanm	92:4fc01daae5a5	1026	((BASE) == TIM_DMABase_CCR2) \|\| \
bogdanm	92:4fc01daae5a5	1027	((BASE) == TIM_DMABase_CCR3) \|\| \
bogdanm	92:4fc01daae5a5	1028	((BASE) == TIM_DMABase_CCR4) \|\| \
bogdanm	92:4fc01daae5a5	1029	((BASE) == TIM_DMABase_BDTR) \|\| \
bogdanm	92:4fc01daae5a5	1030	((BASE) == TIM_DMABase_DCR) \|\| \
bogdanm	92:4fc01daae5a5	1031	((BASE) == TIM_DMABase_OR))
bogdanm	92:4fc01daae5a5	1032	/**
bogdanm	92:4fc01daae5a5	1033	* @}
bogdanm	92:4fc01daae5a5	1034	*/
bogdanm	92:4fc01daae5a5	1035
bogdanm	92:4fc01daae5a5	1036	/** @defgroup TIM_DMA_Burst_Length
bogdanm	92:4fc01daae5a5	1037	* @{
bogdanm	92:4fc01daae5a5	1038	*/
bogdanm	92:4fc01daae5a5	1039	#define TIM_DMABurstLength_1Transfer (0x00000000)
bogdanm	92:4fc01daae5a5	1040	#define TIM_DMABurstLength_2Transfers (0x00000100)
bogdanm	92:4fc01daae5a5	1041	#define TIM_DMABurstLength_3Transfers (0x00000200)
bogdanm	92:4fc01daae5a5	1042	#define TIM_DMABurstLength_4Transfers (0x00000300)
bogdanm	92:4fc01daae5a5	1043	#define TIM_DMABurstLength_5Transfers (0x00000400)
bogdanm	92:4fc01daae5a5	1044	#define TIM_DMABurstLength_6Transfers (0x00000500)
bogdanm	92:4fc01daae5a5	1045	#define TIM_DMABurstLength_7Transfers (0x00000600)
bogdanm	92:4fc01daae5a5	1046	#define TIM_DMABurstLength_8Transfers (0x00000700)
bogdanm	92:4fc01daae5a5	1047	#define TIM_DMABurstLength_9Transfers (0x00000800)
bogdanm	92:4fc01daae5a5	1048	#define TIM_DMABurstLength_10Transfers (0x00000900)
bogdanm	92:4fc01daae5a5	1049	#define TIM_DMABurstLength_11Transfers (0x00000A00)
bogdanm	92:4fc01daae5a5	1050	#define TIM_DMABurstLength_12Transfers (0x00000B00)
bogdanm	92:4fc01daae5a5	1051	#define TIM_DMABurstLength_13Transfers (0x00000C00)
bogdanm	92:4fc01daae5a5	1052	#define TIM_DMABurstLength_14Transfers (0x00000D00)
bogdanm	92:4fc01daae5a5	1053	#define TIM_DMABurstLength_15Transfers (0x00000E00)
bogdanm	92:4fc01daae5a5	1054	#define TIM_DMABurstLength_16Transfers (0x00000F00)
bogdanm	92:4fc01daae5a5	1055	#define TIM_DMABurstLength_17Transfers (0x00001000)
bogdanm	92:4fc01daae5a5	1056	#define TIM_DMABurstLength_18Transfers (0x00001100)
bogdanm	92:4fc01daae5a5	1057	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
bogdanm	92:4fc01daae5a5	1058	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1059	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1060	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1061	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1062	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1063	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1064	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1065	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1066	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1067	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1068	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1069	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1070	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1071	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1072	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1073	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
bogdanm	92:4fc01daae5a5	1074	((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm	92:4fc01daae5a5	1075	/**
bogdanm	92:4fc01daae5a5	1076	* @}
bogdanm	92:4fc01daae5a5	1077	*/
bogdanm	92:4fc01daae5a5	1078
bogdanm	92:4fc01daae5a5	1079	/** @defgroup TIM_Input_Capture_Filer_Value
bogdanm	92:4fc01daae5a5	1080	* @{
bogdanm	92:4fc01daae5a5	1081	*/
bogdanm	92:4fc01daae5a5	1082	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	92:4fc01daae5a5	1083	/**
bogdanm	92:4fc01daae5a5	1084	* @}
bogdanm	92:4fc01daae5a5	1085	*/
bogdanm	92:4fc01daae5a5	1086
bogdanm	92:4fc01daae5a5	1087	/** @defgroup DMA_Handle_index
bogdanm	92:4fc01daae5a5	1088	* @{
bogdanm	92:4fc01daae5a5	1089	*/
bogdanm	92:4fc01daae5a5	1090	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
bogdanm	92:4fc01daae5a5	1091	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
bogdanm	92:4fc01daae5a5	1092	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
bogdanm	92:4fc01daae5a5	1093	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
bogdanm	92:4fc01daae5a5	1094	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
bogdanm	92:4fc01daae5a5	1095	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
bogdanm	92:4fc01daae5a5	1096	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
bogdanm	92:4fc01daae5a5	1097	/**
bogdanm	92:4fc01daae5a5	1098	* @}
bogdanm	92:4fc01daae5a5	1099	*/
bogdanm	92:4fc01daae5a5	1100
bogdanm	92:4fc01daae5a5	1101	/** @defgroup Channel_CC_State
bogdanm	92:4fc01daae5a5	1102	* @{
bogdanm	92:4fc01daae5a5	1103	*/
bogdanm	92:4fc01daae5a5	1104	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm	92:4fc01daae5a5	1105	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	1106	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
bogdanm	92:4fc01daae5a5	1107	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
bogdanm	92:4fc01daae5a5	1108	/**
bogdanm	92:4fc01daae5a5	1109	* @}
bogdanm	92:4fc01daae5a5	1110	*/
bogdanm	92:4fc01daae5a5	1111
bogdanm	92:4fc01daae5a5	1112	/**
bogdanm	92:4fc01daae5a5	1113	* @}
bogdanm	92:4fc01daae5a5	1114	*/
bogdanm	92:4fc01daae5a5	1115
bogdanm	92:4fc01daae5a5	1116	/* Exported macro ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1117
bogdanm	92:4fc01daae5a5	1118	/** @brief Reset TIM handle state
bogdanm	92:4fc01daae5a5	1119	* @param __HANDLE__: TIM handle
bogdanm	92:4fc01daae5a5	1120	* @retval None
bogdanm	92:4fc01daae5a5	1121	*/
bogdanm	92:4fc01daae5a5	1122	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	92:4fc01daae5a5	1123
bogdanm	92:4fc01daae5a5	1124	/**
bogdanm	92:4fc01daae5a5	1125	* @brief Enable the TIM peripheral.
bogdanm	92:4fc01daae5a5	1126	* @param __HANDLE__: TIM handle
bogdanm	92:4fc01daae5a5	1127	* @retval None
bogdanm	92:4fc01daae5a5	1128	*/
bogdanm	92:4fc01daae5a5	1129	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
bogdanm	92:4fc01daae5a5	1130
bogdanm	92:4fc01daae5a5	1131	/**
bogdanm	92:4fc01daae5a5	1132	* @brief Enable the TIM main Output.
bogdanm	92:4fc01daae5a5	1133	* @param __HANDLE__: TIM handle
bogdanm	92:4fc01daae5a5	1134	* @retval None
bogdanm	92:4fc01daae5a5	1135	*/
bogdanm	92:4fc01daae5a5	1136	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
bogdanm	92:4fc01daae5a5	1137
bogdanm	92:4fc01daae5a5	1138
bogdanm	92:4fc01daae5a5	1139	/* The counter of a timer instance is disabled only if all the CCx and CCxN
bogdanm	92:4fc01daae5a5	1140	channels have been disabled */
bogdanm	92:4fc01daae5a5	1141	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
bogdanm	92:4fc01daae5a5	1142	#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
bogdanm	92:4fc01daae5a5	1143
bogdanm	92:4fc01daae5a5	1144	/**
bogdanm	92:4fc01daae5a5	1145	* @brief Disable the TIM peripheral.
bogdanm	92:4fc01daae5a5	1146	* @param __HANDLE__: TIM handle
bogdanm	92:4fc01daae5a5	1147	* @retval None
bogdanm	92:4fc01daae5a5	1148	*/
bogdanm	92:4fc01daae5a5	1149	#define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm	92:4fc01daae5a5	1150	do { \
bogdanm	92:4fc01daae5a5	1151	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm	92:4fc01daae5a5	1152	{ \
bogdanm	92:4fc01daae5a5	1153	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm	92:4fc01daae5a5	1154	{ \
bogdanm	92:4fc01daae5a5	1155	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm	92:4fc01daae5a5	1156	} \
bogdanm	92:4fc01daae5a5	1157	} \
bogdanm	92:4fc01daae5a5	1158	} while(0)
bogdanm	92:4fc01daae5a5	1159
bogdanm	92:4fc01daae5a5	1160	/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
bogdanm	92:4fc01daae5a5	1161	channels have been disabled */
bogdanm	92:4fc01daae5a5	1162	/**
bogdanm	92:4fc01daae5a5	1163	* @brief Disable the TIM main Output.
bogdanm	92:4fc01daae5a5	1164	* @param __HANDLE__: TIM handle
bogdanm	92:4fc01daae5a5	1165	* @retval None
bogdanm	92:4fc01daae5a5	1166	*/
bogdanm	92:4fc01daae5a5	1167	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm	92:4fc01daae5a5	1168	do { \
bogdanm	92:4fc01daae5a5	1169	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm	92:4fc01daae5a5	1170	{ \
bogdanm	92:4fc01daae5a5	1171	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm	92:4fc01daae5a5	1172	{ \
bogdanm	92:4fc01daae5a5	1173	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm	92:4fc01daae5a5	1174	} \
bogdanm	92:4fc01daae5a5	1175	} \
bogdanm	92:4fc01daae5a5	1176	} while(0)
bogdanm	92:4fc01daae5a5	1177
bogdanm	92:4fc01daae5a5	1178	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1179	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
bogdanm	92:4fc01daae5a5	1180	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1181	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm	92:4fc01daae5a5	1182	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm	92:4fc01daae5a5	1183	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm	92:4fc01daae5a5	1184
bogdanm	92:4fc01daae5a5	1185	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	92:4fc01daae5a5	1186	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1187
bogdanm	92:4fc01daae5a5	1188	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm	92:4fc01daae5a5	1189	#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm	92:4fc01daae5a5	1190
bogdanm	92:4fc01daae5a5	1191	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	92:4fc01daae5a5	1192	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
bogdanm	92:4fc01daae5a5	1193	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
bogdanm	92:4fc01daae5a5	1194	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
bogdanm	92:4fc01daae5a5	1195	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
bogdanm	92:4fc01daae5a5	1196
bogdanm	92:4fc01daae5a5	1197	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
bogdanm	92:4fc01daae5a5	1198	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm	92:4fc01daae5a5	1199	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm	92:4fc01daae5a5	1200	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm	92:4fc01daae5a5	1201	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm	92:4fc01daae5a5	1202
bogdanm	92:4fc01daae5a5	1203	/**
bogdanm	92:4fc01daae5a5	1204	* @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm	92:4fc01daae5a5	1205	* calling another time ConfigChannel function.
bogdanm	92:4fc01daae5a5	1206	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1207	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	92:4fc01daae5a5	1208	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1209	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	92:4fc01daae5a5	1210	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	92:4fc01daae5a5	1211	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	92:4fc01daae5a5	1212	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	92:4fc01daae5a5	1213	* @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm	92:4fc01daae5a5	1214	* @retval None
bogdanm	92:4fc01daae5a5	1215	*/
bogdanm	92:4fc01daae5a5	1216	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm	92:4fc01daae5a5	1217	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm	92:4fc01daae5a5	1218
bogdanm	92:4fc01daae5a5	1219	/**
bogdanm	92:4fc01daae5a5	1220	* @brief Gets the TIM Capture Compare Register value on runtime
bogdanm	92:4fc01daae5a5	1221	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1222	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm	92:4fc01daae5a5	1223	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1224	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	92:4fc01daae5a5	1225	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	92:4fc01daae5a5	1226	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	92:4fc01daae5a5	1227	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	92:4fc01daae5a5	1228	* @retval None
bogdanm	92:4fc01daae5a5	1229	*/
bogdanm	92:4fc01daae5a5	1230	#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
bogdanm	92:4fc01daae5a5	1231	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm	92:4fc01daae5a5	1232
bogdanm	92:4fc01daae5a5	1233	/**
bogdanm	92:4fc01daae5a5	1234	* @brief Sets the TIM Counter Register value on runtime.
bogdanm	92:4fc01daae5a5	1235	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1236	* @param __COUNTER__: specifies the Counter register new value.
bogdanm	92:4fc01daae5a5	1237	* @retval None
bogdanm	92:4fc01daae5a5	1238	*/
bogdanm	92:4fc01daae5a5	1239	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	92:4fc01daae5a5	1240
bogdanm	92:4fc01daae5a5	1241	/**
bogdanm	92:4fc01daae5a5	1242	* @brief Gets the TIM Counter Register value on runtime.
bogdanm	92:4fc01daae5a5	1243	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1244	* @retval None
bogdanm	92:4fc01daae5a5	1245	*/
bogdanm	92:4fc01daae5a5	1246	#define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT)
bogdanm	92:4fc01daae5a5	1247
bogdanm	92:4fc01daae5a5	1248	/**
bogdanm	92:4fc01daae5a5	1249	* @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm	92:4fc01daae5a5	1250	* another time any Init function.
bogdanm	92:4fc01daae5a5	1251	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1252	* @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm	92:4fc01daae5a5	1253	* @retval None
bogdanm	92:4fc01daae5a5	1254	*/
bogdanm	92:4fc01daae5a5	1255	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
bogdanm	92:4fc01daae5a5	1256	do{ \
bogdanm	92:4fc01daae5a5	1257	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	92:4fc01daae5a5	1258	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm	92:4fc01daae5a5	1259	} while(0)
bogdanm	92:4fc01daae5a5	1260	/**
bogdanm	92:4fc01daae5a5	1261	* @brief Gets the TIM Autoreload Register value on runtime
bogdanm	92:4fc01daae5a5	1262	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1263	* @retval None
bogdanm	92:4fc01daae5a5	1264	*/
bogdanm	92:4fc01daae5a5	1265	#define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR)
bogdanm	92:4fc01daae5a5	1266
bogdanm	92:4fc01daae5a5	1267	/**
bogdanm	92:4fc01daae5a5	1268	* @brief Sets the TIM Clock Division value on runtime without calling
bogdanm	92:4fc01daae5a5	1269	* another time any Init function.
bogdanm	92:4fc01daae5a5	1270	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1271	* @param __CKD__: specifies the clock division value.
bogdanm	92:4fc01daae5a5	1272	* This parameter can be one of the following value:
bogdanm	92:4fc01daae5a5	1273	* @arg TIM_CLOCKDIVISION_DIV1
bogdanm	92:4fc01daae5a5	1274	* @arg TIM_CLOCKDIVISION_DIV2
bogdanm	92:4fc01daae5a5	1275	* @arg TIM_CLOCKDIVISION_DIV4
bogdanm	92:4fc01daae5a5	1276	* @retval None
bogdanm	92:4fc01daae5a5	1277	*/
bogdanm	92:4fc01daae5a5	1278	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
bogdanm	92:4fc01daae5a5	1279	do{ \
bogdanm	92:4fc01daae5a5	1280	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm	92:4fc01daae5a5	1281	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
bogdanm	92:4fc01daae5a5	1282	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm	92:4fc01daae5a5	1283	} while(0)
bogdanm	92:4fc01daae5a5	1284	/**
bogdanm	92:4fc01daae5a5	1285	* @brief Gets the TIM Clock Division value on runtime
bogdanm	92:4fc01daae5a5	1286	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1287	* @retval None
bogdanm	92:4fc01daae5a5	1288	*/
bogdanm	92:4fc01daae5a5	1289	#define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm	92:4fc01daae5a5	1290
bogdanm	92:4fc01daae5a5	1291	/**
bogdanm	92:4fc01daae5a5	1292	* @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm	92:4fc01daae5a5	1293	* another time HAL_TIM_IC_ConfigChannel() function.
bogdanm	92:4fc01daae5a5	1294	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1295	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	92:4fc01daae5a5	1296	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1297	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	92:4fc01daae5a5	1298	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	92:4fc01daae5a5	1299	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	92:4fc01daae5a5	1300	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	92:4fc01daae5a5	1301	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm	92:4fc01daae5a5	1302	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1303	* @arg TIM_ICPSC_DIV1: no prescaler
bogdanm	92:4fc01daae5a5	1304	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm	92:4fc01daae5a5	1305	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm	92:4fc01daae5a5	1306	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm	92:4fc01daae5a5	1307	* @retval None
bogdanm	92:4fc01daae5a5	1308	*/
bogdanm	92:4fc01daae5a5	1309	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	92:4fc01daae5a5	1310	do{ \
bogdanm	92:4fc01daae5a5	1311	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
bogdanm	92:4fc01daae5a5	1312	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm	92:4fc01daae5a5	1313	} while(0)
bogdanm	92:4fc01daae5a5	1314
bogdanm	92:4fc01daae5a5	1315	/**
bogdanm	92:4fc01daae5a5	1316	* @brief Gets the TIM Input Capture prescaler on runtime
bogdanm	92:4fc01daae5a5	1317	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1318	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	92:4fc01daae5a5	1319	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1320	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	92:4fc01daae5a5	1321	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	92:4fc01daae5a5	1322	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	92:4fc01daae5a5	1323	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	92:4fc01daae5a5	1324	* @retval None
bogdanm	92:4fc01daae5a5	1325	*/
bogdanm	92:4fc01daae5a5	1326	#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
bogdanm	92:4fc01daae5a5	1327	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm	92:4fc01daae5a5	1328	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm	92:4fc01daae5a5	1329	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm	92:4fc01daae5a5	1330	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm	92:4fc01daae5a5	1331	/**
bogdanm	92:4fc01daae5a5	1332	* @}
bogdanm	92:4fc01daae5a5	1333	*/
bogdanm	92:4fc01daae5a5	1334
bogdanm	92:4fc01daae5a5	1335	/* Include TIM HAL Extension module */
bogdanm	92:4fc01daae5a5	1336	#include "stm32f4xx_hal_tim_ex.h"
bogdanm	92:4fc01daae5a5	1337
bogdanm	92:4fc01daae5a5	1338	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1339
bogdanm	92:4fc01daae5a5	1340	/* Time Base functions ********************************************************/
bogdanm	92:4fc01daae5a5	1341	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1342	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1343	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1344	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1345	/* Blocking mode: Polling */
bogdanm	92:4fc01daae5a5	1346	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1347	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1348	/* Non-Blocking mode: Interrupt */
bogdanm	92:4fc01daae5a5	1349	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1350	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1351	/* Non-Blocking mode: DMA */
bogdanm	92:4fc01daae5a5	1352	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	92:4fc01daae5a5	1353	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1354
bogdanm	92:4fc01daae5a5	1355	/* Timer Output Compare functions **********************************************/
bogdanm	92:4fc01daae5a5	1356	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1357	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1358	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1359	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1360	/* Blocking mode: Polling */
bogdanm	92:4fc01daae5a5	1361	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1362	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1363	/* Non-Blocking mode: Interrupt */
bogdanm	92:4fc01daae5a5	1364	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1365	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1366	/* Non-Blocking mode: DMA */
bogdanm	92:4fc01daae5a5	1367	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	92:4fc01daae5a5	1368	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1369
bogdanm	92:4fc01daae5a5	1370	/* Timer PWM functions *********************************************************/
bogdanm	92:4fc01daae5a5	1371	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1372	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1373	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1374	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1375	/* Blocking mode: Polling */
bogdanm	92:4fc01daae5a5	1376	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1377	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1378	/* Non-Blocking mode: Interrupt */
bogdanm	92:4fc01daae5a5	1379	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1380	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1381	/* Non-Blocking mode: DMA */
bogdanm	92:4fc01daae5a5	1382	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	92:4fc01daae5a5	1383	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1384
bogdanm	92:4fc01daae5a5	1385	/* Timer Input Capture functions ***********************************************/
bogdanm	92:4fc01daae5a5	1386	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1387	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1388	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1389	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1390	/* Blocking mode: Polling */
bogdanm	92:4fc01daae5a5	1391	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1392	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1393	/* Non-Blocking mode: Interrupt */
bogdanm	92:4fc01daae5a5	1394	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1395	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1396	/* Non-Blocking mode: DMA */
bogdanm	92:4fc01daae5a5	1397	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	92:4fc01daae5a5	1398	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1399
bogdanm	92:4fc01daae5a5	1400	/* Timer One Pulse functions ***************************************************/
bogdanm	92:4fc01daae5a5	1401	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm	92:4fc01daae5a5	1402	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1403	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1404	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1405	/* Blocking mode: Polling */
bogdanm	92:4fc01daae5a5	1406	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	92:4fc01daae5a5	1407	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	92:4fc01daae5a5	1408
bogdanm	92:4fc01daae5a5	1409	/* Non-Blocking mode: Interrupt */
bogdanm	92:4fc01daae5a5	1410	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	92:4fc01daae5a5	1411	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	92:4fc01daae5a5	1412
bogdanm	92:4fc01daae5a5	1413	/* Timer Encoder functions *****************************************************/
bogdanm	92:4fc01daae5a5	1414	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
bogdanm	92:4fc01daae5a5	1415	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1416	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1417	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1418	/* Blocking mode: Polling */
bogdanm	92:4fc01daae5a5	1419	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1420	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1421	/* Non-Blocking mode: Interrupt */
bogdanm	92:4fc01daae5a5	1422	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1423	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1424	/* Non-Blocking mode: DMA */
bogdanm	92:4fc01daae5a5	1425	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
bogdanm	92:4fc01daae5a5	1426	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1427
bogdanm	92:4fc01daae5a5	1428	/* Interrupt Handler functions **********************************************/
bogdanm	92:4fc01daae5a5	1429	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1430
bogdanm	92:4fc01daae5a5	1431	/* Control functions *********************************************************/
bogdanm	92:4fc01daae5a5	1432	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1433	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1434	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1435	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm	92:4fc01daae5a5	1436	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1437	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
bogdanm	92:4fc01daae5a5	1438	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm	92:4fc01daae5a5	1439	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	92:4fc01daae5a5	1440	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	92:4fc01daae5a5	1441	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	92:4fc01daae5a5	1442	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	92:4fc01daae5a5	1443	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	92:4fc01daae5a5	1444	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	92:4fc01daae5a5	1445	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	92:4fc01daae5a5	1446	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm	92:4fc01daae5a5	1447	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1448
bogdanm	92:4fc01daae5a5	1449	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	92:4fc01daae5a5	1450	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1451	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1452	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1453	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1454	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1455	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1456
bogdanm	92:4fc01daae5a5	1457	/* Peripheral State functions **************************************************/
bogdanm	92:4fc01daae5a5	1458	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1459	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1460	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1461	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1462	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1463	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1464
bogdanm	92:4fc01daae5a5	1465	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
bogdanm	92:4fc01daae5a5	1466	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm	92:4fc01daae5a5	1467	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	92:4fc01daae5a5	1468	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm	92:4fc01daae5a5	1469	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	92:4fc01daae5a5	1470	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm	92:4fc01daae5a5	1471	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
bogdanm	92:4fc01daae5a5	1472
bogdanm	92:4fc01daae5a5	1473	/**
bogdanm	92:4fc01daae5a5	1474	* @}
bogdanm	92:4fc01daae5a5	1475	*/
bogdanm	92:4fc01daae5a5	1476
bogdanm	92:4fc01daae5a5	1477	/**
bogdanm	92:4fc01daae5a5	1478	* @}
bogdanm	92:4fc01daae5a5	1479	*/
bogdanm	92:4fc01daae5a5	1480
bogdanm	92:4fc01daae5a5	1481	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	1482	}
bogdanm	92:4fc01daae5a5	1483	#endif
bogdanm	92:4fc01daae5a5	1484
bogdanm	92:4fc01daae5a5	1485	#endif /* __STM32F4xx_HAL_TIM_H */
bogdanm	92:4fc01daae5a5	1486
bogdanm	92:4fc01daae5a5	1487	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	05 Apr 2016
Imports:	0
Forks:	0
Commits:	119
Dependents:	0
Dependencies:	0
Followers:	1

TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_tim.h@118:16969dd821af, 2016-04-05 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning