Ricardo Benitez / mbed

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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_tim.h@99:dbbf35b96557, 2015-05-13 (annotated)

Committer:
Kojto
Date:
Wed May 13 08:08:21 2015 +0200
Revision:
99:dbbf35b96557
Parent:
92:4fc01daae5a5
Child:
106:ba1f97679dad
Release 99 of the mbed library



Changes:

 - new targets - MAXWSNENV, DISCO_L053C8

 - STM32F4xx - ST Cube driver

 - KSDK mcu - SPI timing fix

 - Nordic - update to softdevice s130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_tim.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
Kojto 99:dbbf35b96557 5 * @version V1.3.0
Kojto 99:dbbf35b96557 6 * @date 09-March-2015
bogdanm 92:4fc01daae5a5 7 * @brief Header file of TIM HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_TIM_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_TIM_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
Kojto 99:dbbf35b96557 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup TIM
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 58 /** @defgroup TIM_Exported_Types TIM Exported Types
Kojto 99:dbbf35b96557 59 * @{
Kojto 99:dbbf35b96557 60 */
Kojto 99:dbbf35b96557 61
bogdanm 92:4fc01daae5a5 62 /**
bogdanm 92:4fc01daae5a5 63 * @brief TIM Time base Configuration Structure definition
bogdanm 92:4fc01daae5a5 64 */
bogdanm 92:4fc01daae5a5 65 typedef struct
bogdanm 92:4fc01daae5a5 66 {
bogdanm 92:4fc01daae5a5 67 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm 92:4fc01daae5a5 68 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm 92:4fc01daae5a5 71 This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm 92:4fc01daae5a5 74 Auto-Reload Register at the next update event.
bogdanm 92:4fc01daae5a5 75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm 92:4fc01daae5a5 76
bogdanm 92:4fc01daae5a5 77 uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm 92:4fc01daae5a5 78 This parameter can be a value of @ref TIM_ClockDivision */
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm 92:4fc01daae5a5 81 reaches zero, an update event is generated and counting restarts
bogdanm 92:4fc01daae5a5 82 from the RCR value (N).
bogdanm 92:4fc01daae5a5 83 This means in PWM mode that (N+1) corresponds to:
bogdanm 92:4fc01daae5a5 84 - the number of PWM periods in edge-aligned mode
bogdanm 92:4fc01daae5a5 85 - the number of half PWM period in center-aligned mode
bogdanm 92:4fc01daae5a5 86 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm 92:4fc01daae5a5 87 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 92:4fc01daae5a5 88 } TIM_Base_InitTypeDef;
bogdanm 92:4fc01daae5a5 89
bogdanm 92:4fc01daae5a5 90 /**
bogdanm 92:4fc01daae5a5 91 * @brief TIM Output Compare Configuration Structure definition
bogdanm 92:4fc01daae5a5 92 */
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 typedef struct
bogdanm 92:4fc01daae5a5 95 {
bogdanm 92:4fc01daae5a5 96 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 92:4fc01daae5a5 97 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm 92:4fc01daae5a5 98
bogdanm 92:4fc01daae5a5 99 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 92:4fc01daae5a5 100 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 92:4fc01daae5a5 101
bogdanm 92:4fc01daae5a5 102 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 92:4fc01daae5a5 103 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm 92:4fc01daae5a5 106 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm 92:4fc01daae5a5 107 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 92:4fc01daae5a5 108
bogdanm 92:4fc01daae5a5 109 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm 92:4fc01daae5a5 110 This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm 92:4fc01daae5a5 111 @note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm 92:4fc01daae5a5 112
bogdanm 92:4fc01daae5a5 113
bogdanm 92:4fc01daae5a5 114 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 92:4fc01daae5a5 115 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm 92:4fc01daae5a5 116 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 92:4fc01daae5a5 117
bogdanm 92:4fc01daae5a5 118 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 92:4fc01daae5a5 119 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm 92:4fc01daae5a5 120 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 92:4fc01daae5a5 121 } TIM_OC_InitTypeDef;
bogdanm 92:4fc01daae5a5 122
bogdanm 92:4fc01daae5a5 123 /**
bogdanm 92:4fc01daae5a5 124 * @brief TIM One Pulse Mode Configuration Structure definition
bogdanm 92:4fc01daae5a5 125 */
bogdanm 92:4fc01daae5a5 126 typedef struct
bogdanm 92:4fc01daae5a5 127 {
bogdanm 92:4fc01daae5a5 128 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 92:4fc01daae5a5 129 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 92:4fc01daae5a5 132 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 92:4fc01daae5a5 133
bogdanm 92:4fc01daae5a5 134 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 92:4fc01daae5a5 135 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm 92:4fc01daae5a5 138 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm 92:4fc01daae5a5 139 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 92:4fc01daae5a5 140
bogdanm 92:4fc01daae5a5 141 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 92:4fc01daae5a5 142 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm 92:4fc01daae5a5 143 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 92:4fc01daae5a5 144
bogdanm 92:4fc01daae5a5 145 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 92:4fc01daae5a5 146 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm 92:4fc01daae5a5 147 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 92:4fc01daae5a5 150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 92:4fc01daae5a5 151
bogdanm 92:4fc01daae5a5 152 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 92:4fc01daae5a5 153 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 92:4fc01daae5a5 154
bogdanm 92:4fc01daae5a5 155 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 92:4fc01daae5a5 156 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 92:4fc01daae5a5 157 } TIM_OnePulse_InitTypeDef;
bogdanm 92:4fc01daae5a5 158
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 /**
bogdanm 92:4fc01daae5a5 161 * @brief TIM Input Capture Configuration Structure definition
bogdanm 92:4fc01daae5a5 162 */
bogdanm 92:4fc01daae5a5 163
bogdanm 92:4fc01daae5a5 164 typedef struct
bogdanm 92:4fc01daae5a5 165 {
bogdanm 92:4fc01daae5a5 166 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 92:4fc01daae5a5 167 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 92:4fc01daae5a5 168
bogdanm 92:4fc01daae5a5 169 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 92:4fc01daae5a5 170 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 92:4fc01daae5a5 171
bogdanm 92:4fc01daae5a5 172 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 92:4fc01daae5a5 173 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 92:4fc01daae5a5 174
bogdanm 92:4fc01daae5a5 175 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 92:4fc01daae5a5 176 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 92:4fc01daae5a5 177 } TIM_IC_InitTypeDef;
bogdanm 92:4fc01daae5a5 178
bogdanm 92:4fc01daae5a5 179 /**
bogdanm 92:4fc01daae5a5 180 * @brief TIM Encoder Configuration Structure definition
bogdanm 92:4fc01daae5a5 181 */
bogdanm 92:4fc01daae5a5 182
bogdanm 92:4fc01daae5a5 183 typedef struct
bogdanm 92:4fc01daae5a5 184 {
bogdanm 92:4fc01daae5a5 185 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm 92:4fc01daae5a5 186 This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm 92:4fc01daae5a5 187
bogdanm 92:4fc01daae5a5 188 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 92:4fc01daae5a5 189 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 92:4fc01daae5a5 190
bogdanm 92:4fc01daae5a5 191 uint32_t IC1Selection; /*!< Specifies the input.
bogdanm 92:4fc01daae5a5 192 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 92:4fc01daae5a5 193
bogdanm 92:4fc01daae5a5 194 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 92:4fc01daae5a5 195 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 92:4fc01daae5a5 196
bogdanm 92:4fc01daae5a5 197 uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm 92:4fc01daae5a5 198 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 92:4fc01daae5a5 199
bogdanm 92:4fc01daae5a5 200 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 92:4fc01daae5a5 201 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 92:4fc01daae5a5 202
bogdanm 92:4fc01daae5a5 203 uint32_t IC2Selection; /*!< Specifies the input.
bogdanm 92:4fc01daae5a5 204 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 92:4fc01daae5a5 205
bogdanm 92:4fc01daae5a5 206 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 92:4fc01daae5a5 207 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 92:4fc01daae5a5 208
bogdanm 92:4fc01daae5a5 209 uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm 92:4fc01daae5a5 210 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 92:4fc01daae5a5 211 } TIM_Encoder_InitTypeDef;
bogdanm 92:4fc01daae5a5 212
bogdanm 92:4fc01daae5a5 213 /**
bogdanm 92:4fc01daae5a5 214 * @brief Clock Configuration Handle Structure definition
bogdanm 92:4fc01daae5a5 215 */
bogdanm 92:4fc01daae5a5 216 typedef struct
bogdanm 92:4fc01daae5a5 217 {
bogdanm 92:4fc01daae5a5 218 uint32_t ClockSource; /*!< TIM clock sources.
bogdanm 92:4fc01daae5a5 219 This parameter can be a value of @ref TIM_Clock_Source */
bogdanm 92:4fc01daae5a5 220 uint32_t ClockPolarity; /*!< TIM clock polarity.
bogdanm 92:4fc01daae5a5 221 This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm 92:4fc01daae5a5 222 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
bogdanm 92:4fc01daae5a5 223 This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm 92:4fc01daae5a5 224 uint32_t ClockFilter; /*!< TIM clock filter.
bogdanm 92:4fc01daae5a5 225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 92:4fc01daae5a5 226 }TIM_ClockConfigTypeDef;
bogdanm 92:4fc01daae5a5 227
bogdanm 92:4fc01daae5a5 228 /**
bogdanm 92:4fc01daae5a5 229 * @brief Clear Input Configuration Handle Structure definition
bogdanm 92:4fc01daae5a5 230 */
bogdanm 92:4fc01daae5a5 231 typedef struct
bogdanm 92:4fc01daae5a5 232 {
bogdanm 92:4fc01daae5a5 233 uint32_t ClearInputState; /*!< TIM clear Input state.
bogdanm 92:4fc01daae5a5 234 This parameter can be ENABLE or DISABLE */
bogdanm 92:4fc01daae5a5 235 uint32_t ClearInputSource; /*!< TIM clear Input sources.
bogdanm 92:4fc01daae5a5 236 This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm 92:4fc01daae5a5 237 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
bogdanm 92:4fc01daae5a5 238 This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm 92:4fc01daae5a5 239 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
bogdanm 92:4fc01daae5a5 240 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm 92:4fc01daae5a5 241 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
bogdanm 92:4fc01daae5a5 242 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 92:4fc01daae5a5 243 }TIM_ClearInputConfigTypeDef;
bogdanm 92:4fc01daae5a5 244
bogdanm 92:4fc01daae5a5 245 /**
bogdanm 92:4fc01daae5a5 246 * @brief TIM Slave configuration Structure definition
bogdanm 92:4fc01daae5a5 247 */
bogdanm 92:4fc01daae5a5 248 typedef struct {
bogdanm 92:4fc01daae5a5 249 uint32_t SlaveMode; /*!< Slave mode selection
bogdanm 92:4fc01daae5a5 250 This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm 92:4fc01daae5a5 251 uint32_t InputTrigger; /*!< Input Trigger source
bogdanm 92:4fc01daae5a5 252 This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm 92:4fc01daae5a5 253 uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm 92:4fc01daae5a5 254 This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm 92:4fc01daae5a5 255 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm 92:4fc01daae5a5 256 This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm 92:4fc01daae5a5 257 uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm 92:4fc01daae5a5 258 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 92:4fc01daae5a5 259
bogdanm 92:4fc01daae5a5 260 }TIM_SlaveConfigTypeDef;
bogdanm 92:4fc01daae5a5 261
bogdanm 92:4fc01daae5a5 262 /**
bogdanm 92:4fc01daae5a5 263 * @brief HAL State structures definition
bogdanm 92:4fc01daae5a5 264 */
bogdanm 92:4fc01daae5a5 265 typedef enum
bogdanm 92:4fc01daae5a5 266 {
bogdanm 92:4fc01daae5a5 267 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 268 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 92:4fc01daae5a5 269 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
bogdanm 92:4fc01daae5a5 270 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 92:4fc01daae5a5 271 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
bogdanm 92:4fc01daae5a5 272 }HAL_TIM_StateTypeDef;
bogdanm 92:4fc01daae5a5 273
bogdanm 92:4fc01daae5a5 274 /**
bogdanm 92:4fc01daae5a5 275 * @brief HAL Active channel structures definition
bogdanm 92:4fc01daae5a5 276 */
bogdanm 92:4fc01daae5a5 277 typedef enum
bogdanm 92:4fc01daae5a5 278 {
bogdanm 92:4fc01daae5a5 279 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
bogdanm 92:4fc01daae5a5 280 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
bogdanm 92:4fc01daae5a5 281 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
bogdanm 92:4fc01daae5a5 282 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
bogdanm 92:4fc01daae5a5 283 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
bogdanm 92:4fc01daae5a5 284 }HAL_TIM_ActiveChannel;
bogdanm 92:4fc01daae5a5 285
bogdanm 92:4fc01daae5a5 286 /**
bogdanm 92:4fc01daae5a5 287 * @brief TIM Time Base Handle Structure definition
bogdanm 92:4fc01daae5a5 288 */
bogdanm 92:4fc01daae5a5 289 typedef struct
bogdanm 92:4fc01daae5a5 290 {
bogdanm 92:4fc01daae5a5 291 TIM_TypeDef *Instance; /*!< Register base address */
bogdanm 92:4fc01daae5a5 292 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
bogdanm 92:4fc01daae5a5 293 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
bogdanm 92:4fc01daae5a5 294 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
bogdanm 92:4fc01daae5a5 295 This array is accessed by a @ref DMA_Handle_index */
bogdanm 92:4fc01daae5a5 296 HAL_LockTypeDef Lock; /*!< Locking object */
bogdanm 92:4fc01daae5a5 297 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
bogdanm 92:4fc01daae5a5 298 }TIM_HandleTypeDef;
Kojto 99:dbbf35b96557 299 /**
Kojto 99:dbbf35b96557 300 * @}
Kojto 99:dbbf35b96557 301 */
bogdanm 92:4fc01daae5a5 302
bogdanm 92:4fc01daae5a5 303 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 304 /** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm 92:4fc01daae5a5 305 * @{
bogdanm 92:4fc01daae5a5 306 */
bogdanm 92:4fc01daae5a5 307
Kojto 99:dbbf35b96557 308 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
bogdanm 92:4fc01daae5a5 309 * @{
bogdanm 92:4fc01daae5a5 310 */
bogdanm 92:4fc01daae5a5 311 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
bogdanm 92:4fc01daae5a5 312 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
bogdanm 92:4fc01daae5a5 313 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
bogdanm 92:4fc01daae5a5 314 /**
bogdanm 92:4fc01daae5a5 315 * @}
bogdanm 92:4fc01daae5a5 316 */
bogdanm 92:4fc01daae5a5 317
Kojto 99:dbbf35b96557 318 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
bogdanm 92:4fc01daae5a5 319 * @{
bogdanm 92:4fc01daae5a5 320 */
bogdanm 92:4fc01daae5a5 321 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
bogdanm 92:4fc01daae5a5 322 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
bogdanm 92:4fc01daae5a5 323 /**
bogdanm 92:4fc01daae5a5 324 * @}
bogdanm 92:4fc01daae5a5 325 */
bogdanm 92:4fc01daae5a5 326
Kojto 99:dbbf35b96557 327 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
bogdanm 92:4fc01daae5a5 328 * @{
bogdanm 92:4fc01daae5a5 329 */
bogdanm 92:4fc01daae5a5 330 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
bogdanm 92:4fc01daae5a5 331 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
bogdanm 92:4fc01daae5a5 332 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
bogdanm 92:4fc01daae5a5 333 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
bogdanm 92:4fc01daae5a5 334 /**
bogdanm 92:4fc01daae5a5 335 * @}
bogdanm 92:4fc01daae5a5 336 */
bogdanm 92:4fc01daae5a5 337
Kojto 99:dbbf35b96557 338 /** @defgroup TIM_Counter_Mode TIM Counter Mode
bogdanm 92:4fc01daae5a5 339 * @{
bogdanm 92:4fc01daae5a5 340 */
bogdanm 92:4fc01daae5a5 341 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 342 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm 92:4fc01daae5a5 343 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm 92:4fc01daae5a5 344 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm 92:4fc01daae5a5 345 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm 92:4fc01daae5a5 346 /**
bogdanm 92:4fc01daae5a5 347 * @}
bogdanm 92:4fc01daae5a5 348 */
bogdanm 92:4fc01daae5a5 349
Kojto 99:dbbf35b96557 350 /** @defgroup TIM_ClockDivision TIM Clock Division
bogdanm 92:4fc01daae5a5 351 * @{
bogdanm 92:4fc01daae5a5 352 */
bogdanm 92:4fc01daae5a5 353 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 354 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm 92:4fc01daae5a5 355 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm 92:4fc01daae5a5 356 /**
bogdanm 92:4fc01daae5a5 357 * @}
bogdanm 92:4fc01daae5a5 358 */
bogdanm 92:4fc01daae5a5 359
Kojto 99:dbbf35b96557 360 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
bogdanm 92:4fc01daae5a5 361 * @{
bogdanm 92:4fc01daae5a5 362 */
bogdanm 92:4fc01daae5a5 363 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 364 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm 92:4fc01daae5a5 365 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm 92:4fc01daae5a5 366 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
bogdanm 92:4fc01daae5a5 367 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
bogdanm 92:4fc01daae5a5 368 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm 92:4fc01daae5a5 369 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
bogdanm 92:4fc01daae5a5 370 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm 92:4fc01daae5a5 371
bogdanm 92:4fc01daae5a5 372 /**
bogdanm 92:4fc01daae5a5 373 * @}
bogdanm 92:4fc01daae5a5 374 */
bogdanm 92:4fc01daae5a5 375
Kojto 99:dbbf35b96557 376 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
bogdanm 92:4fc01daae5a5 377 * @{
bogdanm 92:4fc01daae5a5 378 */
Kojto 99:dbbf35b96557 379 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
Kojto 99:dbbf35b96557 380 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm 92:4fc01daae5a5 381 /**
bogdanm 92:4fc01daae5a5 382 * @}
bogdanm 92:4fc01daae5a5 383 */
bogdanm 92:4fc01daae5a5 384
Kojto 99:dbbf35b96557 385 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
bogdanm 92:4fc01daae5a5 386 * @{
bogdanm 92:4fc01daae5a5 387 */
Kojto 99:dbbf35b96557 388 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
Kojto 99:dbbf35b96557 389 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm 92:4fc01daae5a5 390 /**
bogdanm 92:4fc01daae5a5 391 * @}
bogdanm 92:4fc01daae5a5 392 */
bogdanm 92:4fc01daae5a5 393
Kojto 99:dbbf35b96557 394 /** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
bogdanm 92:4fc01daae5a5 395 * @{
bogdanm 92:4fc01daae5a5 396 */
bogdanm 92:4fc01daae5a5 397 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 398 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm 92:4fc01daae5a5 399 /**
bogdanm 92:4fc01daae5a5 400 * @}
bogdanm 92:4fc01daae5a5 401 */
bogdanm 92:4fc01daae5a5 402
Kojto 99:dbbf35b96557 403 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
bogdanm 92:4fc01daae5a5 404 * @{
bogdanm 92:4fc01daae5a5 405 */
bogdanm 92:4fc01daae5a5 406 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm 92:4fc01daae5a5 407 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 408 /**
bogdanm 92:4fc01daae5a5 409 * @}
bogdanm 92:4fc01daae5a5 410 */
bogdanm 92:4fc01daae5a5 411
Kojto 99:dbbf35b96557 412 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
bogdanm 92:4fc01daae5a5 413 * @{
bogdanm 92:4fc01daae5a5 414 */
bogdanm 92:4fc01daae5a5 415 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
bogdanm 92:4fc01daae5a5 416 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 417 /**
bogdanm 92:4fc01daae5a5 418 * @}
bogdanm 92:4fc01daae5a5 419 */
bogdanm 92:4fc01daae5a5 420
Kojto 99:dbbf35b96557 421 /** @defgroup TIM_Channel TIM Channel
bogdanm 92:4fc01daae5a5 422 * @{
bogdanm 92:4fc01daae5a5 423 */
bogdanm 92:4fc01daae5a5 424 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 425 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm 92:4fc01daae5a5 426 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm 92:4fc01daae5a5 427 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm 92:4fc01daae5a5 428 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm 92:4fc01daae5a5 429
bogdanm 92:4fc01daae5a5 430 /**
bogdanm 92:4fc01daae5a5 431 * @}
bogdanm 92:4fc01daae5a5 432 */
bogdanm 92:4fc01daae5a5 433
Kojto 99:dbbf35b96557 434 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
bogdanm 92:4fc01daae5a5 435 * @{
bogdanm 92:4fc01daae5a5 436 */
bogdanm 92:4fc01daae5a5 437 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm 92:4fc01daae5a5 438 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm 92:4fc01daae5a5 439 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm 92:4fc01daae5a5 440 /**
bogdanm 92:4fc01daae5a5 441 * @}
bogdanm 92:4fc01daae5a5 442 */
bogdanm 92:4fc01daae5a5 443
Kojto 99:dbbf35b96557 444 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
bogdanm 92:4fc01daae5a5 445 * @{
bogdanm 92:4fc01daae5a5 446 */
bogdanm 92:4fc01daae5a5 447 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 92:4fc01daae5a5 448 connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm 92:4fc01daae5a5 449 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 92:4fc01daae5a5 450 connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm 92:4fc01daae5a5 451 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
bogdanm 92:4fc01daae5a5 452
bogdanm 92:4fc01daae5a5 453 /**
bogdanm 92:4fc01daae5a5 454 * @}
bogdanm 92:4fc01daae5a5 455 */
bogdanm 92:4fc01daae5a5 456
Kojto 99:dbbf35b96557 457 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
bogdanm 92:4fc01daae5a5 458 * @{
bogdanm 92:4fc01daae5a5 459 */
bogdanm 92:4fc01daae5a5 460 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
bogdanm 92:4fc01daae5a5 461 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
bogdanm 92:4fc01daae5a5 462 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
bogdanm 92:4fc01daae5a5 463 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
bogdanm 92:4fc01daae5a5 464 /**
bogdanm 92:4fc01daae5a5 465 * @}
bogdanm 92:4fc01daae5a5 466 */
bogdanm 92:4fc01daae5a5 467
Kojto 99:dbbf35b96557 468 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
bogdanm 92:4fc01daae5a5 469 * @{
bogdanm 92:4fc01daae5a5 470 */
bogdanm 92:4fc01daae5a5 471 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm 92:4fc01daae5a5 472 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 473 /**
bogdanm 92:4fc01daae5a5 474 * @}
bogdanm 92:4fc01daae5a5 475 */
bogdanm 92:4fc01daae5a5 476
Kojto 99:dbbf35b96557 477 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
bogdanm 92:4fc01daae5a5 478 * @{
bogdanm 92:4fc01daae5a5 479 */
bogdanm 92:4fc01daae5a5 480 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm 92:4fc01daae5a5 481 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm 92:4fc01daae5a5 482 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
Kojto 99:dbbf35b96557 483
bogdanm 92:4fc01daae5a5 484 /**
bogdanm 92:4fc01daae5a5 485 * @}
bogdanm 92:4fc01daae5a5 486 */
bogdanm 92:4fc01daae5a5 487
Kojto 99:dbbf35b96557 488 /** @defgroup TIM_Interrupt_definition TIM Interrupt definition
bogdanm 92:4fc01daae5a5 489 * @{
bogdanm 92:4fc01daae5a5 490 */
bogdanm 92:4fc01daae5a5 491 #define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm 92:4fc01daae5a5 492 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm 92:4fc01daae5a5 493 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm 92:4fc01daae5a5 494 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm 92:4fc01daae5a5 495 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm 92:4fc01daae5a5 496 #define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm 92:4fc01daae5a5 497 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm 92:4fc01daae5a5 498 #define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm 92:4fc01daae5a5 499 /**
bogdanm 92:4fc01daae5a5 500 * @}
bogdanm 92:4fc01daae5a5 501 */
Kojto 99:dbbf35b96557 502
Kojto 99:dbbf35b96557 503 /** @defgroup TIM_Commutation_Source TIM Commutation Source
Kojto 99:dbbf35b96557 504 * @{
Kojto 99:dbbf35b96557 505 */
bogdanm 92:4fc01daae5a5 506 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm 92:4fc01daae5a5 507 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
Kojto 99:dbbf35b96557 508 /**
Kojto 99:dbbf35b96557 509 * @}
Kojto 99:dbbf35b96557 510 */
bogdanm 92:4fc01daae5a5 511
Kojto 99:dbbf35b96557 512 /** @defgroup TIM_DMA_sources TIM DMA sources
bogdanm 92:4fc01daae5a5 513 * @{
bogdanm 92:4fc01daae5a5 514 */
bogdanm 92:4fc01daae5a5 515 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm 92:4fc01daae5a5 516 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm 92:4fc01daae5a5 517 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm 92:4fc01daae5a5 518 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm 92:4fc01daae5a5 519 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm 92:4fc01daae5a5 520 #define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm 92:4fc01daae5a5 521 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm 92:4fc01daae5a5 522 /**
bogdanm 92:4fc01daae5a5 523 * @}
bogdanm 92:4fc01daae5a5 524 */
bogdanm 92:4fc01daae5a5 525
Kojto 99:dbbf35b96557 526 /** @defgroup TIM_Event_Source TIM Event Source
bogdanm 92:4fc01daae5a5 527 * @{
bogdanm 92:4fc01daae5a5 528 */
Kojto 99:dbbf35b96557 529 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
Kojto 99:dbbf35b96557 530 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
Kojto 99:dbbf35b96557 531 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
Kojto 99:dbbf35b96557 532 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
Kojto 99:dbbf35b96557 533 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
Kojto 99:dbbf35b96557 534 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
Kojto 99:dbbf35b96557 535 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
Kojto 99:dbbf35b96557 536 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
Kojto 99:dbbf35b96557 537
bogdanm 92:4fc01daae5a5 538 /**
bogdanm 92:4fc01daae5a5 539 * @}
bogdanm 92:4fc01daae5a5 540 */
bogdanm 92:4fc01daae5a5 541
Kojto 99:dbbf35b96557 542 /** @defgroup TIM_Flag_definition TIM Flag definition
bogdanm 92:4fc01daae5a5 543 * @{
bogdanm 92:4fc01daae5a5 544 */
bogdanm 92:4fc01daae5a5 545 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm 92:4fc01daae5a5 546 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm 92:4fc01daae5a5 547 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm 92:4fc01daae5a5 548 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm 92:4fc01daae5a5 549 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm 92:4fc01daae5a5 550 #define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm 92:4fc01daae5a5 551 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm 92:4fc01daae5a5 552 #define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm 92:4fc01daae5a5 553 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm 92:4fc01daae5a5 554 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm 92:4fc01daae5a5 555 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm 92:4fc01daae5a5 556 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm 92:4fc01daae5a5 557 /**
bogdanm 92:4fc01daae5a5 558 * @}
bogdanm 92:4fc01daae5a5 559 */
bogdanm 92:4fc01daae5a5 560
Kojto 99:dbbf35b96557 561 /** @defgroup TIM_Clock_Source TIM Clock Source
bogdanm 92:4fc01daae5a5 562 * @{
bogdanm 92:4fc01daae5a5 563 */
bogdanm 92:4fc01daae5a5 564 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm 92:4fc01daae5a5 565 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm 92:4fc01daae5a5 566 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 567 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm 92:4fc01daae5a5 568 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm 92:4fc01daae5a5 569 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
bogdanm 92:4fc01daae5a5 570 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm 92:4fc01daae5a5 571 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
bogdanm 92:4fc01daae5a5 572 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
bogdanm 92:4fc01daae5a5 573 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm 92:4fc01daae5a5 574 /**
bogdanm 92:4fc01daae5a5 575 * @}
bogdanm 92:4fc01daae5a5 576 */
bogdanm 92:4fc01daae5a5 577
Kojto 99:dbbf35b96557 578 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
bogdanm 92:4fc01daae5a5 579 * @{
bogdanm 92:4fc01daae5a5 580 */
bogdanm 92:4fc01daae5a5 581 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
bogdanm 92:4fc01daae5a5 582 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
bogdanm 92:4fc01daae5a5 583 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
bogdanm 92:4fc01daae5a5 584 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
bogdanm 92:4fc01daae5a5 585 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
bogdanm 92:4fc01daae5a5 586 /**
bogdanm 92:4fc01daae5a5 587 * @}
bogdanm 92:4fc01daae5a5 588 */
bogdanm 92:4fc01daae5a5 589
Kojto 99:dbbf35b96557 590 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
bogdanm 92:4fc01daae5a5 591 * @{
bogdanm 92:4fc01daae5a5 592 */
Kojto 99:dbbf35b96557 593 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
Kojto 99:dbbf35b96557 594 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
Kojto 99:dbbf35b96557 595 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
Kojto 99:dbbf35b96557 596 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
bogdanm 92:4fc01daae5a5 597 /**
bogdanm 92:4fc01daae5a5 598 * @}
bogdanm 92:4fc01daae5a5 599 */
bogdanm 92:4fc01daae5a5 600
Kojto 99:dbbf35b96557 601 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
bogdanm 92:4fc01daae5a5 602 * @{
bogdanm 92:4fc01daae5a5 603 */
bogdanm 92:4fc01daae5a5 604 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm 92:4fc01daae5a5 605 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 606 /**
bogdanm 92:4fc01daae5a5 607 * @}
bogdanm 92:4fc01daae5a5 608 */
bogdanm 92:4fc01daae5a5 609
Kojto 99:dbbf35b96557 610 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
bogdanm 92:4fc01daae5a5 611 * @{
bogdanm 92:4fc01daae5a5 612 */
bogdanm 92:4fc01daae5a5 613 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
bogdanm 92:4fc01daae5a5 614 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
bogdanm 92:4fc01daae5a5 615 /**
bogdanm 92:4fc01daae5a5 616 * @}
bogdanm 92:4fc01daae5a5 617 */
bogdanm 92:4fc01daae5a5 618
Kojto 99:dbbf35b96557 619 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
bogdanm 92:4fc01daae5a5 620 * @{
bogdanm 92:4fc01daae5a5 621 */
bogdanm 92:4fc01daae5a5 622 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 92:4fc01daae5a5 623 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
bogdanm 92:4fc01daae5a5 624 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
bogdanm 92:4fc01daae5a5 625 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
bogdanm 92:4fc01daae5a5 626 /**
bogdanm 92:4fc01daae5a5 627 * @}
bogdanm 92:4fc01daae5a5 628 */
bogdanm 92:4fc01daae5a5 629
Kojto 99:dbbf35b96557 630 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
bogdanm 92:4fc01daae5a5 631 * @{
bogdanm 92:4fc01daae5a5 632 */
bogdanm 92:4fc01daae5a5 633 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
Kojto 99:dbbf35b96557 634 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 635 /**
bogdanm 92:4fc01daae5a5 636 * @}
bogdanm 92:4fc01daae5a5 637 */
bogdanm 92:4fc01daae5a5 638
Kojto 99:dbbf35b96557 639 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
bogdanm 92:4fc01daae5a5 640 * @{
bogdanm 92:4fc01daae5a5 641 */
bogdanm 92:4fc01daae5a5 642 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm 92:4fc01daae5a5 643 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 644 /**
bogdanm 92:4fc01daae5a5 645 * @}
bogdanm 92:4fc01daae5a5 646 */
Kojto 99:dbbf35b96557 647
Kojto 99:dbbf35b96557 648 /** @defgroup TIM_Lock_level TIM Lock level
bogdanm 92:4fc01daae5a5 649 * @{
bogdanm 92:4fc01daae5a5 650 */
bogdanm 92:4fc01daae5a5 651 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 652 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm 92:4fc01daae5a5 653 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm 92:4fc01daae5a5 654 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm 92:4fc01daae5a5 655 /**
bogdanm 92:4fc01daae5a5 656 * @}
bogdanm 92:4fc01daae5a5 657 */
Kojto 99:dbbf35b96557 658 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
bogdanm 92:4fc01daae5a5 659 * @{
bogdanm 92:4fc01daae5a5 660 */
bogdanm 92:4fc01daae5a5 661 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm 92:4fc01daae5a5 662 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 663 /**
bogdanm 92:4fc01daae5a5 664 * @}
bogdanm 92:4fc01daae5a5 665 */
Kojto 99:dbbf35b96557 666
Kojto 99:dbbf35b96557 667 /** @defgroup TIM_Break_Polarity TIM Break Polarity
bogdanm 92:4fc01daae5a5 668 * @{
bogdanm 92:4fc01daae5a5 669 */
bogdanm 92:4fc01daae5a5 670 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 671 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm 92:4fc01daae5a5 672 /**
bogdanm 92:4fc01daae5a5 673 * @}
bogdanm 92:4fc01daae5a5 674 */
Kojto 99:dbbf35b96557 675
Kojto 99:dbbf35b96557 676 /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
bogdanm 92:4fc01daae5a5 677 * @{
bogdanm 92:4fc01daae5a5 678 */
bogdanm 92:4fc01daae5a5 679 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm 92:4fc01daae5a5 680 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 681 /**
bogdanm 92:4fc01daae5a5 682 * @}
bogdanm 92:4fc01daae5a5 683 */
bogdanm 92:4fc01daae5a5 684
Kojto 99:dbbf35b96557 685 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
bogdanm 92:4fc01daae5a5 686 * @{
bogdanm 92:4fc01daae5a5 687 */
bogdanm 92:4fc01daae5a5 688 #define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 689 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm 92:4fc01daae5a5 690 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm 92:4fc01daae5a5 691 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 92:4fc01daae5a5 692 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm 92:4fc01daae5a5 693 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
bogdanm 92:4fc01daae5a5 694 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
Kojto 99:dbbf35b96557 695 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 92:4fc01daae5a5 696 /**
bogdanm 92:4fc01daae5a5 697 * @}
bogdanm 92:4fc01daae5a5 698 */
Kojto 99:dbbf35b96557 699
Kojto 99:dbbf35b96557 700 /** @defgroup TIM_Slave_Mode TIM Slave Mode
bogdanm 92:4fc01daae5a5 701 * @{
bogdanm 92:4fc01daae5a5 702 */
bogdanm 92:4fc01daae5a5 703 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 704 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm 92:4fc01daae5a5 705 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm 92:4fc01daae5a5 706 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm 92:4fc01daae5a5 707 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm 92:4fc01daae5a5 708 /**
bogdanm 92:4fc01daae5a5 709 * @}
bogdanm 92:4fc01daae5a5 710 */
bogdanm 92:4fc01daae5a5 711
Kojto 99:dbbf35b96557 712 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
bogdanm 92:4fc01daae5a5 713 * @{
bogdanm 92:4fc01daae5a5 714 */
bogdanm 92:4fc01daae5a5 715 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm 92:4fc01daae5a5 716 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 717 /**
bogdanm 92:4fc01daae5a5 718 * @}
bogdanm 92:4fc01daae5a5 719 */
Kojto 99:dbbf35b96557 720
Kojto 99:dbbf35b96557 721 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
bogdanm 92:4fc01daae5a5 722 * @{
bogdanm 92:4fc01daae5a5 723 */
bogdanm 92:4fc01daae5a5 724 #define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 725 #define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm 92:4fc01daae5a5 726 #define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm 92:4fc01daae5a5 727 #define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm 92:4fc01daae5a5 728 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm 92:4fc01daae5a5 729 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm 92:4fc01daae5a5 730 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm 92:4fc01daae5a5 731 #define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm 92:4fc01daae5a5 732 #define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm 92:4fc01daae5a5 733 /**
bogdanm 92:4fc01daae5a5 734 * @}
bogdanm 92:4fc01daae5a5 735 */
bogdanm 92:4fc01daae5a5 736
Kojto 99:dbbf35b96557 737 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
bogdanm 92:4fc01daae5a5 738 * @{
bogdanm 92:4fc01daae5a5 739 */
bogdanm 92:4fc01daae5a5 740 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 92:4fc01daae5a5 741 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 92:4fc01daae5a5 742 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 92:4fc01daae5a5 743 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 92:4fc01daae5a5 744 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 92:4fc01daae5a5 745 /**
bogdanm 92:4fc01daae5a5 746 * @}
bogdanm 92:4fc01daae5a5 747 */
bogdanm 92:4fc01daae5a5 748
Kojto 99:dbbf35b96557 749 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
bogdanm 92:4fc01daae5a5 750 * @{
bogdanm 92:4fc01daae5a5 751 */
bogdanm 92:4fc01daae5a5 752 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 92:4fc01daae5a5 753 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
bogdanm 92:4fc01daae5a5 754 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
bogdanm 92:4fc01daae5a5 755 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
bogdanm 92:4fc01daae5a5 756 /**
bogdanm 92:4fc01daae5a5 757 * @}
bogdanm 92:4fc01daae5a5 758 */
bogdanm 92:4fc01daae5a5 759
bogdanm 92:4fc01daae5a5 760
Kojto 99:dbbf35b96557 761 /** @defgroup TIM_TI1_Selection TIM TI1 Selection
bogdanm 92:4fc01daae5a5 762 * @{
bogdanm 92:4fc01daae5a5 763 */
bogdanm 92:4fc01daae5a5 764 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 765 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm 92:4fc01daae5a5 766 /**
bogdanm 92:4fc01daae5a5 767 * @}
bogdanm 92:4fc01daae5a5 768 */
bogdanm 92:4fc01daae5a5 769
Kojto 99:dbbf35b96557 770 /** @defgroup TIM_DMA_Base_address TIM DMA Base address
bogdanm 92:4fc01daae5a5 771 * @{
bogdanm 92:4fc01daae5a5 772 */
Kojto 99:dbbf35b96557 773 #define TIM_DMABASE_CR1 (0x00000000)
Kojto 99:dbbf35b96557 774 #define TIM_DMABASE_CR2 (0x00000001)
Kojto 99:dbbf35b96557 775 #define TIM_DMABASE_SMCR (0x00000002)
Kojto 99:dbbf35b96557 776 #define TIM_DMABASE_DIER (0x00000003)
Kojto 99:dbbf35b96557 777 #define TIM_DMABASE_SR (0x00000004)
Kojto 99:dbbf35b96557 778 #define TIM_DMABASE_EGR (0x00000005)
Kojto 99:dbbf35b96557 779 #define TIM_DMABASE_CCMR1 (0x00000006)
Kojto 99:dbbf35b96557 780 #define TIM_DMABASE_CCMR2 (0x00000007)
Kojto 99:dbbf35b96557 781 #define TIM_DMABASE_CCER (0x00000008)
Kojto 99:dbbf35b96557 782 #define TIM_DMABASE_CNT (0x00000009)
Kojto 99:dbbf35b96557 783 #define TIM_DMABASE_PSC (0x0000000A)
Kojto 99:dbbf35b96557 784 #define TIM_DMABASE_ARR (0x0000000B)
Kojto 99:dbbf35b96557 785 #define TIM_DMABASE_RCR (0x0000000C)
Kojto 99:dbbf35b96557 786 #define TIM_DMABASE_CCR1 (0x0000000D)
Kojto 99:dbbf35b96557 787 #define TIM_DMABASE_CCR2 (0x0000000E)
Kojto 99:dbbf35b96557 788 #define TIM_DMABASE_CCR3 (0x0000000F)
Kojto 99:dbbf35b96557 789 #define TIM_DMABASE_CCR4 (0x00000010)
Kojto 99:dbbf35b96557 790 #define TIM_DMABASE_BDTR (0x00000011)
Kojto 99:dbbf35b96557 791 #define TIM_DMABASE_DCR (0x00000012)
Kojto 99:dbbf35b96557 792 #define TIM_DMABASE_OR (0x00000013)
bogdanm 92:4fc01daae5a5 793 /**
bogdanm 92:4fc01daae5a5 794 * @}
bogdanm 92:4fc01daae5a5 795 */
bogdanm 92:4fc01daae5a5 796
Kojto 99:dbbf35b96557 797 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
bogdanm 92:4fc01daae5a5 798 * @{
bogdanm 92:4fc01daae5a5 799 */
Kojto 99:dbbf35b96557 800 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
Kojto 99:dbbf35b96557 801 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
Kojto 99:dbbf35b96557 802 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
Kojto 99:dbbf35b96557 803 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
Kojto 99:dbbf35b96557 804 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
Kojto 99:dbbf35b96557 805 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
Kojto 99:dbbf35b96557 806 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
Kojto 99:dbbf35b96557 807 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
Kojto 99:dbbf35b96557 808 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
Kojto 99:dbbf35b96557 809 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
Kojto 99:dbbf35b96557 810 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
Kojto 99:dbbf35b96557 811 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
Kojto 99:dbbf35b96557 812 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
Kojto 99:dbbf35b96557 813 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
Kojto 99:dbbf35b96557 814 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
Kojto 99:dbbf35b96557 815 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
Kojto 99:dbbf35b96557 816 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
Kojto 99:dbbf35b96557 817 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
bogdanm 92:4fc01daae5a5 818 /**
bogdanm 92:4fc01daae5a5 819 * @}
bogdanm 92:4fc01daae5a5 820 */
bogdanm 92:4fc01daae5a5 821
Kojto 99:dbbf35b96557 822 /** @defgroup DMA_Handle_index DMA Handle index
bogdanm 92:4fc01daae5a5 823 * @{
bogdanm 92:4fc01daae5a5 824 */
bogdanm 92:4fc01daae5a5 825 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
bogdanm 92:4fc01daae5a5 826 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
bogdanm 92:4fc01daae5a5 827 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
bogdanm 92:4fc01daae5a5 828 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
bogdanm 92:4fc01daae5a5 829 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
bogdanm 92:4fc01daae5a5 830 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
bogdanm 92:4fc01daae5a5 831 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
bogdanm 92:4fc01daae5a5 832 /**
bogdanm 92:4fc01daae5a5 833 * @}
bogdanm 92:4fc01daae5a5 834 */
bogdanm 92:4fc01daae5a5 835
Kojto 99:dbbf35b96557 836 /** @defgroup Channel_CC_State Channel CC State
bogdanm 92:4fc01daae5a5 837 * @{
bogdanm 92:4fc01daae5a5 838 */
bogdanm 92:4fc01daae5a5 839 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm 92:4fc01daae5a5 840 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 841 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
bogdanm 92:4fc01daae5a5 842 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 843 /**
bogdanm 92:4fc01daae5a5 844 * @}
bogdanm 92:4fc01daae5a5 845 */
bogdanm 92:4fc01daae5a5 846
bogdanm 92:4fc01daae5a5 847 /**
bogdanm 92:4fc01daae5a5 848 * @}
bogdanm 92:4fc01daae5a5 849 */
bogdanm 92:4fc01daae5a5 850
bogdanm 92:4fc01daae5a5 851 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 852 /** @defgroup TIM_Exported_Macros TIM Exported Macros
Kojto 99:dbbf35b96557 853 * @{
Kojto 99:dbbf35b96557 854 */
bogdanm 92:4fc01daae5a5 855 /** @brief Reset TIM handle state
bogdanm 92:4fc01daae5a5 856 * @param __HANDLE__: TIM handle
bogdanm 92:4fc01daae5a5 857 * @retval None
bogdanm 92:4fc01daae5a5 858 */
bogdanm 92:4fc01daae5a5 859 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm 92:4fc01daae5a5 860
bogdanm 92:4fc01daae5a5 861 /**
bogdanm 92:4fc01daae5a5 862 * @brief Enable the TIM peripheral.
bogdanm 92:4fc01daae5a5 863 * @param __HANDLE__: TIM handle
bogdanm 92:4fc01daae5a5 864 * @retval None
bogdanm 92:4fc01daae5a5 865 */
bogdanm 92:4fc01daae5a5 866 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
bogdanm 92:4fc01daae5a5 867
bogdanm 92:4fc01daae5a5 868 /**
bogdanm 92:4fc01daae5a5 869 * @brief Enable the TIM main Output.
bogdanm 92:4fc01daae5a5 870 * @param __HANDLE__: TIM handle
bogdanm 92:4fc01daae5a5 871 * @retval None
bogdanm 92:4fc01daae5a5 872 */
bogdanm 92:4fc01daae5a5 873 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
bogdanm 92:4fc01daae5a5 874
bogdanm 92:4fc01daae5a5 875
bogdanm 92:4fc01daae5a5 876 /**
bogdanm 92:4fc01daae5a5 877 * @brief Disable the TIM peripheral.
bogdanm 92:4fc01daae5a5 878 * @param __HANDLE__: TIM handle
bogdanm 92:4fc01daae5a5 879 * @retval None
bogdanm 92:4fc01daae5a5 880 */
bogdanm 92:4fc01daae5a5 881 #define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm 92:4fc01daae5a5 882 do { \
Kojto 99:dbbf35b96557 883 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm 92:4fc01daae5a5 884 { \
Kojto 99:dbbf35b96557 885 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
bogdanm 92:4fc01daae5a5 886 { \
bogdanm 92:4fc01daae5a5 887 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm 92:4fc01daae5a5 888 } \
bogdanm 92:4fc01daae5a5 889 } \
bogdanm 92:4fc01daae5a5 890 } while(0)
bogdanm 92:4fc01daae5a5 891
bogdanm 92:4fc01daae5a5 892 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
bogdanm 92:4fc01daae5a5 893 channels have been disabled */
bogdanm 92:4fc01daae5a5 894 /**
bogdanm 92:4fc01daae5a5 895 * @brief Disable the TIM main Output.
bogdanm 92:4fc01daae5a5 896 * @param __HANDLE__: TIM handle
bogdanm 92:4fc01daae5a5 897 * @retval None
bogdanm 92:4fc01daae5a5 898 */
bogdanm 92:4fc01daae5a5 899 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm 92:4fc01daae5a5 900 do { \
Kojto 99:dbbf35b96557 901 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm 92:4fc01daae5a5 902 { \
Kojto 99:dbbf35b96557 903 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
bogdanm 92:4fc01daae5a5 904 { \
bogdanm 92:4fc01daae5a5 905 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm 92:4fc01daae5a5 906 } \
bogdanm 92:4fc01daae5a5 907 } \
bogdanm 92:4fc01daae5a5 908 } while(0)
bogdanm 92:4fc01daae5a5 909
bogdanm 92:4fc01daae5a5 910 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 911 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
bogdanm 92:4fc01daae5a5 912 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm 92:4fc01daae5a5 913 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm 92:4fc01daae5a5 914 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 915 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm 92:4fc01daae5a5 916
Kojto 99:dbbf35b96557 917 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 92:4fc01daae5a5 918 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm 92:4fc01daae5a5 919
Kojto 99:dbbf35b96557 920 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Kojto 99:dbbf35b96557 921 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm 92:4fc01daae5a5 922
Kojto 99:dbbf35b96557 923 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 92:4fc01daae5a5 924 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
bogdanm 92:4fc01daae5a5 925 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
bogdanm 92:4fc01daae5a5 926 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
bogdanm 92:4fc01daae5a5 927 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
bogdanm 92:4fc01daae5a5 928
Kojto 99:dbbf35b96557 929 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
bogdanm 92:4fc01daae5a5 930 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm 92:4fc01daae5a5 931 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm 92:4fc01daae5a5 932 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm 92:4fc01daae5a5 933 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm 92:4fc01daae5a5 934
Kojto 99:dbbf35b96557 935 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
Kojto 99:dbbf35b96557 936 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
Kojto 99:dbbf35b96557 937 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
Kojto 99:dbbf35b96557 938 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
Kojto 99:dbbf35b96557 939 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
Kojto 99:dbbf35b96557 940
Kojto 99:dbbf35b96557 941 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
Kojto 99:dbbf35b96557 942 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
Kojto 99:dbbf35b96557 943 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
Kojto 99:dbbf35b96557 944 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
Kojto 99:dbbf35b96557 945 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
Kojto 99:dbbf35b96557 946
bogdanm 92:4fc01daae5a5 947 /**
bogdanm 92:4fc01daae5a5 948 * @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm 92:4fc01daae5a5 949 * calling another time ConfigChannel function.
bogdanm 92:4fc01daae5a5 950 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 951 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 92:4fc01daae5a5 952 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 953 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 92:4fc01daae5a5 954 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 92:4fc01daae5a5 955 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 92:4fc01daae5a5 956 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 92:4fc01daae5a5 957 * @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm 92:4fc01daae5a5 958 * @retval None
bogdanm 92:4fc01daae5a5 959 */
Kojto 99:dbbf35b96557 960 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm 92:4fc01daae5a5 961 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm 92:4fc01daae5a5 962
bogdanm 92:4fc01daae5a5 963 /**
bogdanm 92:4fc01daae5a5 964 * @brief Gets the TIM Capture Compare Register value on runtime
bogdanm 92:4fc01daae5a5 965 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 966 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm 92:4fc01daae5a5 967 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 968 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm 92:4fc01daae5a5 969 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm 92:4fc01daae5a5 970 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm 92:4fc01daae5a5 971 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm 92:4fc01daae5a5 972 * @retval None
bogdanm 92:4fc01daae5a5 973 */
Kojto 99:dbbf35b96557 974 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
bogdanm 92:4fc01daae5a5 975 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm 92:4fc01daae5a5 976
bogdanm 92:4fc01daae5a5 977 /**
bogdanm 92:4fc01daae5a5 978 * @brief Sets the TIM Counter Register value on runtime.
bogdanm 92:4fc01daae5a5 979 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 980 * @param __COUNTER__: specifies the Counter register new value.
bogdanm 92:4fc01daae5a5 981 * @retval None
bogdanm 92:4fc01daae5a5 982 */
Kojto 99:dbbf35b96557 983 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm 92:4fc01daae5a5 984
bogdanm 92:4fc01daae5a5 985 /**
bogdanm 92:4fc01daae5a5 986 * @brief Gets the TIM Counter Register value on runtime.
bogdanm 92:4fc01daae5a5 987 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 988 * @retval None
bogdanm 92:4fc01daae5a5 989 */
Kojto 99:dbbf35b96557 990 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
bogdanm 92:4fc01daae5a5 991
bogdanm 92:4fc01daae5a5 992 /**
bogdanm 92:4fc01daae5a5 993 * @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm 92:4fc01daae5a5 994 * another time any Init function.
bogdanm 92:4fc01daae5a5 995 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 996 * @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm 92:4fc01daae5a5 997 * @retval None
bogdanm 92:4fc01daae5a5 998 */
Kojto 99:dbbf35b96557 999 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
bogdanm 92:4fc01daae5a5 1000 do{ \
bogdanm 92:4fc01daae5a5 1001 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm 92:4fc01daae5a5 1002 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm 92:4fc01daae5a5 1003 } while(0)
bogdanm 92:4fc01daae5a5 1004 /**
bogdanm 92:4fc01daae5a5 1005 * @brief Gets the TIM Autoreload Register value on runtime
bogdanm 92:4fc01daae5a5 1006 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 1007 * @retval None
bogdanm 92:4fc01daae5a5 1008 */
Kojto 99:dbbf35b96557 1009 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
bogdanm 92:4fc01daae5a5 1010
bogdanm 92:4fc01daae5a5 1011 /**
bogdanm 92:4fc01daae5a5 1012 * @brief Sets the TIM Clock Division value on runtime without calling
bogdanm 92:4fc01daae5a5 1013 * another time any Init function.
bogdanm 92:4fc01daae5a5 1014 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 1015 * @param __CKD__: specifies the clock division value.
bogdanm 92:4fc01daae5a5 1016 * This parameter can be one of the following value:
bogdanm 92:4fc01daae5a5 1017 * @arg TIM_CLOCKDIVISION_DIV1
bogdanm 92:4fc01daae5a5 1018 * @arg TIM_CLOCKDIVISION_DIV2
bogdanm 92:4fc01daae5a5 1019 * @arg TIM_CLOCKDIVISION_DIV4
bogdanm 92:4fc01daae5a5 1020 * @retval None
bogdanm 92:4fc01daae5a5 1021 */
Kojto 99:dbbf35b96557 1022 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
bogdanm 92:4fc01daae5a5 1023 do{ \
bogdanm 92:4fc01daae5a5 1024 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm 92:4fc01daae5a5 1025 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
bogdanm 92:4fc01daae5a5 1026 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm 92:4fc01daae5a5 1027 } while(0)
bogdanm 92:4fc01daae5a5 1028 /**
bogdanm 92:4fc01daae5a5 1029 * @brief Gets the TIM Clock Division value on runtime
bogdanm 92:4fc01daae5a5 1030 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 1031 * @retval None
bogdanm 92:4fc01daae5a5 1032 */
Kojto 99:dbbf35b96557 1033 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm 92:4fc01daae5a5 1034
bogdanm 92:4fc01daae5a5 1035 /**
bogdanm 92:4fc01daae5a5 1036 * @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm 92:4fc01daae5a5 1037 * another time HAL_TIM_IC_ConfigChannel() function.
bogdanm 92:4fc01daae5a5 1038 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 1039 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 92:4fc01daae5a5 1040 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 1041 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 92:4fc01daae5a5 1042 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 92:4fc01daae5a5 1043 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 92:4fc01daae5a5 1044 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 92:4fc01daae5a5 1045 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm 92:4fc01daae5a5 1046 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 1047 * @arg TIM_ICPSC_DIV1: no prescaler
bogdanm 92:4fc01daae5a5 1048 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm 92:4fc01daae5a5 1049 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm 92:4fc01daae5a5 1050 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm 92:4fc01daae5a5 1051 * @retval None
bogdanm 92:4fc01daae5a5 1052 */
Kojto 99:dbbf35b96557 1053 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 92:4fc01daae5a5 1054 do{ \
Kojto 99:dbbf35b96557 1055 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
Kojto 99:dbbf35b96557 1056 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm 92:4fc01daae5a5 1057 } while(0)
bogdanm 92:4fc01daae5a5 1058
bogdanm 92:4fc01daae5a5 1059 /**
bogdanm 92:4fc01daae5a5 1060 * @brief Gets the TIM Input Capture prescaler on runtime
bogdanm 92:4fc01daae5a5 1061 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 1062 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 92:4fc01daae5a5 1063 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 1064 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm 92:4fc01daae5a5 1065 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm 92:4fc01daae5a5 1066 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm 92:4fc01daae5a5 1067 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm 92:4fc01daae5a5 1068 * @retval None
bogdanm 92:4fc01daae5a5 1069 */
Kojto 99:dbbf35b96557 1070 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
bogdanm 92:4fc01daae5a5 1071 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm 92:4fc01daae5a5 1072 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm 92:4fc01daae5a5 1073 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm 92:4fc01daae5a5 1074 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
Kojto 99:dbbf35b96557 1075
Kojto 99:dbbf35b96557 1076 /**
Kojto 99:dbbf35b96557 1077 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
Kojto 99:dbbf35b96557 1078 * @param __HANDLE__: TIM handle.
Kojto 99:dbbf35b96557 1079 * @note When the USR bit of the TIMx_CR1 register is set, only counter
Kojto 99:dbbf35b96557 1080 * overflow/underflow generates an update interrupt or DMA request (if
Kojto 99:dbbf35b96557 1081 * enabled)
Kojto 99:dbbf35b96557 1082 * @retval None
Kojto 99:dbbf35b96557 1083 */
Kojto 99:dbbf35b96557 1084 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
Kojto 99:dbbf35b96557 1085 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Kojto 99:dbbf35b96557 1086
Kojto 99:dbbf35b96557 1087 /**
Kojto 99:dbbf35b96557 1088 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
Kojto 99:dbbf35b96557 1089 * @param __HANDLE__: TIM handle.
Kojto 99:dbbf35b96557 1090 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
Kojto 99:dbbf35b96557 1091 * following events generate an update interrupt or DMA request (if
Kojto 99:dbbf35b96557 1092 * enabled):
Kojto 99:dbbf35b96557 1093 * – Counter overflow/underflow
Kojto 99:dbbf35b96557 1094 * – Setting the UG bit
Kojto 99:dbbf35b96557 1095 * – Update generation through the slave mode controller
Kojto 99:dbbf35b96557 1096 * @retval None
Kojto 99:dbbf35b96557 1097 */
Kojto 99:dbbf35b96557 1098 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
Kojto 99:dbbf35b96557 1099 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Kojto 99:dbbf35b96557 1100
Kojto 99:dbbf35b96557 1101 /**
Kojto 99:dbbf35b96557 1102 * @brief Sets the TIM Capture x input polarity on runtime.
Kojto 99:dbbf35b96557 1103 * @param __HANDLE__: TIM handle.
Kojto 99:dbbf35b96557 1104 * @param __CHANNEL__: TIM Channels to be configured.
Kojto 99:dbbf35b96557 1105 * This parameter can be one of the following values:
Kojto 99:dbbf35b96557 1106 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
Kojto 99:dbbf35b96557 1107 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
Kojto 99:dbbf35b96557 1108 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
Kojto 99:dbbf35b96557 1109 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
Kojto 99:dbbf35b96557 1110 * @param __POLARITY__: Polarity for TIx source
Kojto 99:dbbf35b96557 1111 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
Kojto 99:dbbf35b96557 1112 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
Kojto 99:dbbf35b96557 1113 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Kojto 99:dbbf35b96557 1114 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
Kojto 99:dbbf35b96557 1115 * @retval None
Kojto 99:dbbf35b96557 1116 */
Kojto 99:dbbf35b96557 1117 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
Kojto 99:dbbf35b96557 1118 do{ \
Kojto 99:dbbf35b96557 1119 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
Kojto 99:dbbf35b96557 1120 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
Kojto 99:dbbf35b96557 1121 }while(0)
bogdanm 92:4fc01daae5a5 1122 /**
bogdanm 92:4fc01daae5a5 1123 * @}
bogdanm 92:4fc01daae5a5 1124 */
bogdanm 92:4fc01daae5a5 1125
bogdanm 92:4fc01daae5a5 1126 /* Include TIM HAL Extension module */
bogdanm 92:4fc01daae5a5 1127 #include "stm32f4xx_hal_tim_ex.h"
bogdanm 92:4fc01daae5a5 1128
bogdanm 92:4fc01daae5a5 1129 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 1130 /** @addtogroup TIM_Exported_Functions
Kojto 99:dbbf35b96557 1131 * @{
Kojto 99:dbbf35b96557 1132 */
Kojto 99:dbbf35b96557 1133
Kojto 99:dbbf35b96557 1134 /** @addtogroup TIM_Exported_Functions_Group1
Kojto 99:dbbf35b96557 1135 * @{
Kojto 99:dbbf35b96557 1136 */
bogdanm 92:4fc01daae5a5 1137
bogdanm 92:4fc01daae5a5 1138 /* Time Base functions ********************************************************/
bogdanm 92:4fc01daae5a5 1139 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1140 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1141 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1142 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1143 /* Blocking mode: Polling */
bogdanm 92:4fc01daae5a5 1144 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1145 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1146 /* Non-Blocking mode: Interrupt */
bogdanm 92:4fc01daae5a5 1147 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1148 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1149 /* Non-Blocking mode: DMA */
bogdanm 92:4fc01daae5a5 1150 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
bogdanm 92:4fc01daae5a5 1151 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
Kojto 99:dbbf35b96557 1152 /**
Kojto 99:dbbf35b96557 1153 * @}
Kojto 99:dbbf35b96557 1154 */
bogdanm 92:4fc01daae5a5 1155
Kojto 99:dbbf35b96557 1156 /** @addtogroup TIM_Exported_Functions_Group2
Kojto 99:dbbf35b96557 1157 * @{
Kojto 99:dbbf35b96557 1158 */
bogdanm 92:4fc01daae5a5 1159 /* Timer Output Compare functions **********************************************/
bogdanm 92:4fc01daae5a5 1160 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1161 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1162 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1163 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1164 /* Blocking mode: Polling */
bogdanm 92:4fc01daae5a5 1165 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1166 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1167 /* Non-Blocking mode: Interrupt */
bogdanm 92:4fc01daae5a5 1168 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1169 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1170 /* Non-Blocking mode: DMA */
bogdanm 92:4fc01daae5a5 1171 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 92:4fc01daae5a5 1172 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1173
Kojto 99:dbbf35b96557 1174 /**
Kojto 99:dbbf35b96557 1175 * @}
Kojto 99:dbbf35b96557 1176 */
Kojto 99:dbbf35b96557 1177
Kojto 99:dbbf35b96557 1178 /** @addtogroup TIM_Exported_Functions_Group3
Kojto 99:dbbf35b96557 1179 * @{
Kojto 99:dbbf35b96557 1180 */
bogdanm 92:4fc01daae5a5 1181 /* Timer PWM functions *********************************************************/
bogdanm 92:4fc01daae5a5 1182 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1183 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1184 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1185 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1186 /* Blocking mode: Polling */
bogdanm 92:4fc01daae5a5 1187 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1188 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1189 /* Non-Blocking mode: Interrupt */
bogdanm 92:4fc01daae5a5 1190 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1191 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1192 /* Non-Blocking mode: DMA */
bogdanm 92:4fc01daae5a5 1193 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 92:4fc01daae5a5 1194 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1195
Kojto 99:dbbf35b96557 1196 /**
Kojto 99:dbbf35b96557 1197 * @}
Kojto 99:dbbf35b96557 1198 */
Kojto 99:dbbf35b96557 1199
Kojto 99:dbbf35b96557 1200 /** @addtogroup TIM_Exported_Functions_Group4
Kojto 99:dbbf35b96557 1201 * @{
Kojto 99:dbbf35b96557 1202 */
bogdanm 92:4fc01daae5a5 1203 /* Timer Input Capture functions ***********************************************/
bogdanm 92:4fc01daae5a5 1204 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1205 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1206 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1207 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1208 /* Blocking mode: Polling */
bogdanm 92:4fc01daae5a5 1209 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1210 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1211 /* Non-Blocking mode: Interrupt */
bogdanm 92:4fc01daae5a5 1212 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1213 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1214 /* Non-Blocking mode: DMA */
bogdanm 92:4fc01daae5a5 1215 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 92:4fc01daae5a5 1216 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1217
Kojto 99:dbbf35b96557 1218 /**
Kojto 99:dbbf35b96557 1219 * @}
Kojto 99:dbbf35b96557 1220 */
Kojto 99:dbbf35b96557 1221
Kojto 99:dbbf35b96557 1222 /** @addtogroup TIM_Exported_Functions_Group5
Kojto 99:dbbf35b96557 1223 * @{
Kojto 99:dbbf35b96557 1224 */
bogdanm 92:4fc01daae5a5 1225 /* Timer One Pulse functions ***************************************************/
bogdanm 92:4fc01daae5a5 1226 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm 92:4fc01daae5a5 1227 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1228 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1229 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1230 /* Blocking mode: Polling */
bogdanm 92:4fc01daae5a5 1231 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 92:4fc01daae5a5 1232 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 92:4fc01daae5a5 1233
bogdanm 92:4fc01daae5a5 1234 /* Non-Blocking mode: Interrupt */
bogdanm 92:4fc01daae5a5 1235 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 92:4fc01daae5a5 1236 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 92:4fc01daae5a5 1237
Kojto 99:dbbf35b96557 1238 /**
Kojto 99:dbbf35b96557 1239 * @}
Kojto 99:dbbf35b96557 1240 */
Kojto 99:dbbf35b96557 1241
Kojto 99:dbbf35b96557 1242 /** @addtogroup TIM_Exported_Functions_Group6
Kojto 99:dbbf35b96557 1243 * @{
Kojto 99:dbbf35b96557 1244 */
bogdanm 92:4fc01daae5a5 1245 /* Timer Encoder functions *****************************************************/
bogdanm 92:4fc01daae5a5 1246 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
bogdanm 92:4fc01daae5a5 1247 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1248 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1249 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1250 /* Blocking mode: Polling */
bogdanm 92:4fc01daae5a5 1251 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1252 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1253 /* Non-Blocking mode: Interrupt */
bogdanm 92:4fc01daae5a5 1254 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1255 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1256 /* Non-Blocking mode: DMA */
bogdanm 92:4fc01daae5a5 1257 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
bogdanm 92:4fc01daae5a5 1258 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1259
Kojto 99:dbbf35b96557 1260 /**
Kojto 99:dbbf35b96557 1261 * @}
Kojto 99:dbbf35b96557 1262 */
Kojto 99:dbbf35b96557 1263
Kojto 99:dbbf35b96557 1264 /** @addtogroup TIM_Exported_Functions_Group7
Kojto 99:dbbf35b96557 1265 * @{
Kojto 99:dbbf35b96557 1266 */
bogdanm 92:4fc01daae5a5 1267 /* Interrupt Handler functions **********************************************/
bogdanm 92:4fc01daae5a5 1268 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1269
Kojto 99:dbbf35b96557 1270 /**
Kojto 99:dbbf35b96557 1271 * @}
Kojto 99:dbbf35b96557 1272 */
Kojto 99:dbbf35b96557 1273
Kojto 99:dbbf35b96557 1274 /** @addtogroup TIM_Exported_Functions_Group8
Kojto 99:dbbf35b96557 1275 * @{
Kojto 99:dbbf35b96557 1276 */
bogdanm 92:4fc01daae5a5 1277 /* Control functions *********************************************************/
bogdanm 92:4fc01daae5a5 1278 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1279 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1280 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1281 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm 92:4fc01daae5a5 1282 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1283 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
bogdanm 92:4fc01daae5a5 1284 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm 92:4fc01daae5a5 1285 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
Kojto 99:dbbf35b96557 1286 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
bogdanm 92:4fc01daae5a5 1287 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 92:4fc01daae5a5 1288 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 92:4fc01daae5a5 1289 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 92:4fc01daae5a5 1290 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 92:4fc01daae5a5 1291 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 92:4fc01daae5a5 1292 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 92:4fc01daae5a5 1293 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm 92:4fc01daae5a5 1294 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1295
Kojto 99:dbbf35b96557 1296 /**
Kojto 99:dbbf35b96557 1297 * @}
Kojto 99:dbbf35b96557 1298 */
Kojto 99:dbbf35b96557 1299
Kojto 99:dbbf35b96557 1300 /** @addtogroup TIM_Exported_Functions_Group9
Kojto 99:dbbf35b96557 1301 * @{
Kojto 99:dbbf35b96557 1302 */
bogdanm 92:4fc01daae5a5 1303 /* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm 92:4fc01daae5a5 1304 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1305 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1306 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1307 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1308 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1309 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1310
Kojto 99:dbbf35b96557 1311 /**
Kojto 99:dbbf35b96557 1312 * @}
Kojto 99:dbbf35b96557 1313 */
Kojto 99:dbbf35b96557 1314
Kojto 99:dbbf35b96557 1315 /** @addtogroup TIM_Exported_Functions_Group10
Kojto 99:dbbf35b96557 1316 * @{
Kojto 99:dbbf35b96557 1317 */
bogdanm 92:4fc01daae5a5 1318 /* Peripheral State functions **************************************************/
bogdanm 92:4fc01daae5a5 1319 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1320 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1321 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1322 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1323 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1324 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1325
Kojto 99:dbbf35b96557 1326 /**
Kojto 99:dbbf35b96557 1327 * @}
Kojto 99:dbbf35b96557 1328 */
Kojto 99:dbbf35b96557 1329
Kojto 99:dbbf35b96557 1330 /**
Kojto 99:dbbf35b96557 1331 * @}
Kojto 99:dbbf35b96557 1332 */
Kojto 99:dbbf35b96557 1333
Kojto 99:dbbf35b96557 1334 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 1335 /** @defgroup TIM_Private_Macros TIM Private Macros
Kojto 99:dbbf35b96557 1336 * @{
Kojto 99:dbbf35b96557 1337 */
Kojto 99:dbbf35b96557 1338
Kojto 99:dbbf35b96557 1339 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
Kojto 99:dbbf35b96557 1340 * @{
Kojto 99:dbbf35b96557 1341 */
Kojto 99:dbbf35b96557 1342 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
Kojto 99:dbbf35b96557 1343 ((MODE) == TIM_COUNTERMODE_DOWN) || \
Kojto 99:dbbf35b96557 1344 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
Kojto 99:dbbf35b96557 1345 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
Kojto 99:dbbf35b96557 1346 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
Kojto 99:dbbf35b96557 1347
Kojto 99:dbbf35b96557 1348 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
Kojto 99:dbbf35b96557 1349 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
Kojto 99:dbbf35b96557 1350 ((DIV) == TIM_CLOCKDIVISION_DIV4))
Kojto 99:dbbf35b96557 1351
Kojto 99:dbbf35b96557 1352 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
Kojto 99:dbbf35b96557 1353 ((MODE) == TIM_OCMODE_PWM2))
Kojto 99:dbbf35b96557 1354
Kojto 99:dbbf35b96557 1355 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
Kojto 99:dbbf35b96557 1356 ((MODE) == TIM_OCMODE_ACTIVE) || \
Kojto 99:dbbf35b96557 1357 ((MODE) == TIM_OCMODE_INACTIVE) || \
Kojto 99:dbbf35b96557 1358 ((MODE) == TIM_OCMODE_TOGGLE) || \
Kojto 99:dbbf35b96557 1359 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
Kojto 99:dbbf35b96557 1360 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
Kojto 99:dbbf35b96557 1361
Kojto 99:dbbf35b96557 1362 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
Kojto 99:dbbf35b96557 1363 ((STATE) == TIM_OCFAST_ENABLE))
Kojto 99:dbbf35b96557 1364
Kojto 99:dbbf35b96557 1365 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
Kojto 99:dbbf35b96557 1366 ((POLARITY) == TIM_OCPOLARITY_LOW))
Kojto 99:dbbf35b96557 1367
Kojto 99:dbbf35b96557 1368 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
Kojto 99:dbbf35b96557 1369 ((POLARITY) == TIM_OCNPOLARITY_LOW))
Kojto 99:dbbf35b96557 1370
Kojto 99:dbbf35b96557 1371 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
Kojto 99:dbbf35b96557 1372 ((STATE) == TIM_OCIDLESTATE_RESET))
Kojto 99:dbbf35b96557 1373
Kojto 99:dbbf35b96557 1374 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
Kojto 99:dbbf35b96557 1375 ((STATE) == TIM_OCNIDLESTATE_RESET))
Kojto 99:dbbf35b96557 1376
Kojto 99:dbbf35b96557 1377 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 99:dbbf35b96557 1378 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 99:dbbf35b96557 1379 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 99:dbbf35b96557 1380 ((CHANNEL) == TIM_CHANNEL_4) || \
Kojto 99:dbbf35b96557 1381 ((CHANNEL) == TIM_CHANNEL_ALL))
Kojto 99:dbbf35b96557 1382
Kojto 99:dbbf35b96557 1383 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 99:dbbf35b96557 1384 ((CHANNEL) == TIM_CHANNEL_2))
Kojto 99:dbbf35b96557 1385
Kojto 99:dbbf35b96557 1386 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 99:dbbf35b96557 1387 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 99:dbbf35b96557 1388 ((CHANNEL) == TIM_CHANNEL_3))
Kojto 99:dbbf35b96557 1389
Kojto 99:dbbf35b96557 1390 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
Kojto 99:dbbf35b96557 1391 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
Kojto 99:dbbf35b96557 1392 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
Kojto 99:dbbf35b96557 1393
Kojto 99:dbbf35b96557 1394 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
Kojto 99:dbbf35b96557 1395 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
Kojto 99:dbbf35b96557 1396 ((SELECTION) == TIM_ICSELECTION_TRC))
Kojto 99:dbbf35b96557 1397
Kojto 99:dbbf35b96557 1398 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
Kojto 99:dbbf35b96557 1399 ((PRESCALER) == TIM_ICPSC_DIV2) || \
Kojto 99:dbbf35b96557 1400 ((PRESCALER) == TIM_ICPSC_DIV4) || \
Kojto 99:dbbf35b96557 1401 ((PRESCALER) == TIM_ICPSC_DIV8))
Kojto 99:dbbf35b96557 1402
Kojto 99:dbbf35b96557 1403 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
Kojto 99:dbbf35b96557 1404 ((MODE) == TIM_OPMODE_REPETITIVE))
Kojto 99:dbbf35b96557 1405
Kojto 99:dbbf35b96557 1406 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
Kojto 99:dbbf35b96557 1407
Kojto 99:dbbf35b96557 1408 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
Kojto 99:dbbf35b96557 1409 ((MODE) == TIM_ENCODERMODE_TI2) || \
Kojto 99:dbbf35b96557 1410 ((MODE) == TIM_ENCODERMODE_TI12))
Kojto 99:dbbf35b96557 1411
Kojto 99:dbbf35b96557 1412 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
Kojto 99:dbbf35b96557 1413
Kojto 99:dbbf35b96557 1414 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
Kojto 99:dbbf35b96557 1415 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
Kojto 99:dbbf35b96557 1416 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
Kojto 99:dbbf35b96557 1417 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
Kojto 99:dbbf35b96557 1418 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
Kojto 99:dbbf35b96557 1419 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
Kojto 99:dbbf35b96557 1420 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
Kojto 99:dbbf35b96557 1421 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
Kojto 99:dbbf35b96557 1422 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
Kojto 99:dbbf35b96557 1423 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
Kojto 99:dbbf35b96557 1424
Kojto 99:dbbf35b96557 1425 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
Kojto 99:dbbf35b96557 1426 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
Kojto 99:dbbf35b96557 1427 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
Kojto 99:dbbf35b96557 1428 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
Kojto 99:dbbf35b96557 1429 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
Kojto 99:dbbf35b96557 1430
Kojto 99:dbbf35b96557 1431 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
Kojto 99:dbbf35b96557 1432 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
Kojto 99:dbbf35b96557 1433 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
Kojto 99:dbbf35b96557 1434 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
Kojto 99:dbbf35b96557 1435
Kojto 99:dbbf35b96557 1436 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
Kojto 99:dbbf35b96557 1437
Kojto 99:dbbf35b96557 1438 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
Kojto 99:dbbf35b96557 1439 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
Kojto 99:dbbf35b96557 1440
Kojto 99:dbbf35b96557 1441 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
Kojto 99:dbbf35b96557 1442 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
Kojto 99:dbbf35b96557 1443
Kojto 99:dbbf35b96557 1444 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
Kojto 99:dbbf35b96557 1445 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
Kojto 99:dbbf35b96557 1446 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
Kojto 99:dbbf35b96557 1447 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
Kojto 99:dbbf35b96557 1448
Kojto 99:dbbf35b96557 1449 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
Kojto 99:dbbf35b96557 1450
Kojto 99:dbbf35b96557 1451 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
Kojto 99:dbbf35b96557 1452 ((STATE) == TIM_OSSR_DISABLE))
Kojto 99:dbbf35b96557 1453
Kojto 99:dbbf35b96557 1454 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
Kojto 99:dbbf35b96557 1455 ((STATE) == TIM_OSSI_DISABLE))
Kojto 99:dbbf35b96557 1456
Kojto 99:dbbf35b96557 1457 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
Kojto 99:dbbf35b96557 1458 ((LEVEL) == TIM_LOCKLEVEL_1) || \
Kojto 99:dbbf35b96557 1459 ((LEVEL) == TIM_LOCKLEVEL_2) || \
Kojto 99:dbbf35b96557 1460 ((LEVEL) == TIM_LOCKLEVEL_3))
Kojto 99:dbbf35b96557 1461
Kojto 99:dbbf35b96557 1462 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
Kojto 99:dbbf35b96557 1463 ((STATE) == TIM_BREAK_DISABLE))
Kojto 99:dbbf35b96557 1464
Kojto 99:dbbf35b96557 1465 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
Kojto 99:dbbf35b96557 1466 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
Kojto 99:dbbf35b96557 1467
Kojto 99:dbbf35b96557 1468 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
Kojto 99:dbbf35b96557 1469 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
Kojto 99:dbbf35b96557 1470
Kojto 99:dbbf35b96557 1471 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
Kojto 99:dbbf35b96557 1472 ((SOURCE) == TIM_TRGO_ENABLE) || \
Kojto 99:dbbf35b96557 1473 ((SOURCE) == TIM_TRGO_UPDATE) || \
Kojto 99:dbbf35b96557 1474 ((SOURCE) == TIM_TRGO_OC1) || \
Kojto 99:dbbf35b96557 1475 ((SOURCE) == TIM_TRGO_OC1REF) || \
Kojto 99:dbbf35b96557 1476 ((SOURCE) == TIM_TRGO_OC2REF) || \
Kojto 99:dbbf35b96557 1477 ((SOURCE) == TIM_TRGO_OC3REF) || \
Kojto 99:dbbf35b96557 1478 ((SOURCE) == TIM_TRGO_OC4REF))
Kojto 99:dbbf35b96557 1479
Kojto 99:dbbf35b96557 1480 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
Kojto 99:dbbf35b96557 1481 ((MODE) == TIM_SLAVEMODE_GATED) || \
Kojto 99:dbbf35b96557 1482 ((MODE) == TIM_SLAVEMODE_RESET) || \
Kojto 99:dbbf35b96557 1483 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
Kojto 99:dbbf35b96557 1484 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
Kojto 99:dbbf35b96557 1485
Kojto 99:dbbf35b96557 1486 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
Kojto 99:dbbf35b96557 1487 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
Kojto 99:dbbf35b96557 1488
Kojto 99:dbbf35b96557 1489 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
Kojto 99:dbbf35b96557 1490 ((SELECTION) == TIM_TS_ITR1) || \
Kojto 99:dbbf35b96557 1491 ((SELECTION) == TIM_TS_ITR2) || \
Kojto 99:dbbf35b96557 1492 ((SELECTION) == TIM_TS_ITR3) || \
Kojto 99:dbbf35b96557 1493 ((SELECTION) == TIM_TS_TI1F_ED) || \
Kojto 99:dbbf35b96557 1494 ((SELECTION) == TIM_TS_TI1FP1) || \
Kojto 99:dbbf35b96557 1495 ((SELECTION) == TIM_TS_TI2FP2) || \
Kojto 99:dbbf35b96557 1496 ((SELECTION) == TIM_TS_ETRF))
Kojto 99:dbbf35b96557 1497
Kojto 99:dbbf35b96557 1498 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
Kojto 99:dbbf35b96557 1499 ((SELECTION) == TIM_TS_ITR1) || \
Kojto 99:dbbf35b96557 1500 ((SELECTION) == TIM_TS_ITR2) || \
Kojto 99:dbbf35b96557 1501 ((SELECTION) == TIM_TS_ITR3) || \
Kojto 99:dbbf35b96557 1502 ((SELECTION) == TIM_TS_NONE))
Kojto 99:dbbf35b96557 1503 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
Kojto 99:dbbf35b96557 1504 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
Kojto 99:dbbf35b96557 1505 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
Kojto 99:dbbf35b96557 1506 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
Kojto 99:dbbf35b96557 1507 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
Kojto 99:dbbf35b96557 1508
Kojto 99:dbbf35b96557 1509 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
Kojto 99:dbbf35b96557 1510 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
Kojto 99:dbbf35b96557 1511 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
Kojto 99:dbbf35b96557 1512 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
Kojto 99:dbbf35b96557 1513
Kojto 99:dbbf35b96557 1514 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
Kojto 99:dbbf35b96557 1515
Kojto 99:dbbf35b96557 1516 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
Kojto 99:dbbf35b96557 1517 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
Kojto 99:dbbf35b96557 1518
Kojto 99:dbbf35b96557 1519 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
Kojto 99:dbbf35b96557 1520 ((BASE) == TIM_DMABASE_CR2) || \
Kojto 99:dbbf35b96557 1521 ((BASE) == TIM_DMABASE_SMCR) || \
Kojto 99:dbbf35b96557 1522 ((BASE) == TIM_DMABASE_DIER) || \
Kojto 99:dbbf35b96557 1523 ((BASE) == TIM_DMABASE_SR) || \
Kojto 99:dbbf35b96557 1524 ((BASE) == TIM_DMABASE_EGR) || \
Kojto 99:dbbf35b96557 1525 ((BASE) == TIM_DMABASE_CCMR1) || \
Kojto 99:dbbf35b96557 1526 ((BASE) == TIM_DMABASE_CCMR2) || \
Kojto 99:dbbf35b96557 1527 ((BASE) == TIM_DMABASE_CCER) || \
Kojto 99:dbbf35b96557 1528 ((BASE) == TIM_DMABASE_CNT) || \
Kojto 99:dbbf35b96557 1529 ((BASE) == TIM_DMABASE_PSC) || \
Kojto 99:dbbf35b96557 1530 ((BASE) == TIM_DMABASE_ARR) || \
Kojto 99:dbbf35b96557 1531 ((BASE) == TIM_DMABASE_RCR) || \
Kojto 99:dbbf35b96557 1532 ((BASE) == TIM_DMABASE_CCR1) || \
Kojto 99:dbbf35b96557 1533 ((BASE) == TIM_DMABASE_CCR2) || \
Kojto 99:dbbf35b96557 1534 ((BASE) == TIM_DMABASE_CCR3) || \
Kojto 99:dbbf35b96557 1535 ((BASE) == TIM_DMABASE_CCR4) || \
Kojto 99:dbbf35b96557 1536 ((BASE) == TIM_DMABASE_BDTR) || \
Kojto 99:dbbf35b96557 1537 ((BASE) == TIM_DMABASE_DCR) || \
Kojto 99:dbbf35b96557 1538 ((BASE) == TIM_DMABASE_OR))
Kojto 99:dbbf35b96557 1539
Kojto 99:dbbf35b96557 1540 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
Kojto 99:dbbf35b96557 1541 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
Kojto 99:dbbf35b96557 1542 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
Kojto 99:dbbf35b96557 1543 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
Kojto 99:dbbf35b96557 1544 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
Kojto 99:dbbf35b96557 1545 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
Kojto 99:dbbf35b96557 1546 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
Kojto 99:dbbf35b96557 1547 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
Kojto 99:dbbf35b96557 1548 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
Kojto 99:dbbf35b96557 1549 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
Kojto 99:dbbf35b96557 1550 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
Kojto 99:dbbf35b96557 1551 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
Kojto 99:dbbf35b96557 1552 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
Kojto 99:dbbf35b96557 1553 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
Kojto 99:dbbf35b96557 1554 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
Kojto 99:dbbf35b96557 1555 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
Kojto 99:dbbf35b96557 1556 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
Kojto 99:dbbf35b96557 1557 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
Kojto 99:dbbf35b96557 1558
Kojto 99:dbbf35b96557 1559 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
Kojto 99:dbbf35b96557 1560 /**
Kojto 99:dbbf35b96557 1561 * @}
Kojto 99:dbbf35b96557 1562 */
Kojto 99:dbbf35b96557 1563
Kojto 99:dbbf35b96557 1564 /** @defgroup TIM_Mask_Definitions TIM Mask Definition
Kojto 99:dbbf35b96557 1565 * @{
Kojto 99:dbbf35b96557 1566 */
Kojto 99:dbbf35b96557 1567 /* The counter of a timer instance is disabled only if all the CCx and CCxN
Kojto 99:dbbf35b96557 1568 channels have been disabled */
Kojto 99:dbbf35b96557 1569 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
Kojto 99:dbbf35b96557 1570 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
Kojto 99:dbbf35b96557 1571 /**
Kojto 99:dbbf35b96557 1572 * @}
Kojto 99:dbbf35b96557 1573 */
Kojto 99:dbbf35b96557 1574
Kojto 99:dbbf35b96557 1575 /**
Kojto 99:dbbf35b96557 1576 * @}
Kojto 99:dbbf35b96557 1577 */
Kojto 99:dbbf35b96557 1578
Kojto 99:dbbf35b96557 1579 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 1580 /** @defgroup TIM_Private_Functions TIM Private Functions
Kojto 99:dbbf35b96557 1581 * @{
Kojto 99:dbbf35b96557 1582 */
bogdanm 92:4fc01daae5a5 1583 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
bogdanm 92:4fc01daae5a5 1584 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm 92:4fc01daae5a5 1585 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
Kojto 99:dbbf35b96557 1586 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 1587 void TIM_DMAError(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 1588 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 1589 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
Kojto 99:dbbf35b96557 1590 /**
Kojto 99:dbbf35b96557 1591 * @}
Kojto 99:dbbf35b96557 1592 */
Kojto 99:dbbf35b96557 1593
bogdanm 92:4fc01daae5a5 1594 /**
bogdanm 92:4fc01daae5a5 1595 * @}
bogdanm 92:4fc01daae5a5 1596 */
bogdanm 92:4fc01daae5a5 1597
bogdanm 92:4fc01daae5a5 1598 /**
bogdanm 92:4fc01daae5a5 1599 * @}
bogdanm 92:4fc01daae5a5 1600 */
bogdanm 92:4fc01daae5a5 1601
bogdanm 92:4fc01daae5a5 1602 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 1603 }
bogdanm 92:4fc01daae5a5 1604 #endif
bogdanm 92:4fc01daae5a5 1605
bogdanm 92:4fc01daae5a5 1606 #endif /* __STM32F4xx_HAL_TIM_H */
bogdanm 92:4fc01daae5a5 1607
bogdanm 92:4fc01daae5a5 1608 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/