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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_adc.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
92:4fc01daae5a5
Child:
99:dbbf35b96557
dgdgr

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bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_adc.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of ADC HAL extension module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_ADC_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_ADC_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup ADC
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 /**
bogdanm 92:4fc01daae5a5 60 * @brief HAL State structures definition
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62 typedef enum
bogdanm 92:4fc01daae5a5 63 {
bogdanm 92:4fc01daae5a5 64 HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 65 HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
bogdanm 92:4fc01daae5a5 66 HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
bogdanm 92:4fc01daae5a5 67 HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
bogdanm 92:4fc01daae5a5 68 HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
bogdanm 92:4fc01daae5a5 69 HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
bogdanm 92:4fc01daae5a5 70 HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 92:4fc01daae5a5 71 HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
bogdanm 92:4fc01daae5a5 72 HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
bogdanm 92:4fc01daae5a5 73 HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
bogdanm 92:4fc01daae5a5 74 HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
bogdanm 92:4fc01daae5a5 75 HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
bogdanm 92:4fc01daae5a5 76 HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78 }HAL_ADC_StateTypeDef;
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 /**
bogdanm 92:4fc01daae5a5 81 * @brief ADC Init structure definition
bogdanm 92:4fc01daae5a5 82 */
bogdanm 92:4fc01daae5a5 83 typedef struct
bogdanm 92:4fc01daae5a5 84 {
bogdanm 92:4fc01daae5a5 85 uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for
bogdanm 92:4fc01daae5a5 86 all the ADCs.
bogdanm 92:4fc01daae5a5 87 This parameter can be a value of @ref ADC_ClockPrescaler */
bogdanm 92:4fc01daae5a5 88 uint32_t Resolution; /*!< Configures the ADC resolution dual mode.
bogdanm 92:4fc01daae5a5 89 This parameter can be a value of @ref ADC_Resolution */
bogdanm 92:4fc01daae5a5 90 uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
bogdanm 92:4fc01daae5a5 91 This parameter can be a value of @ref ADC_data_align */
bogdanm 92:4fc01daae5a5 92 uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or
bogdanm 92:4fc01daae5a5 93 Single (one channel) mode.
bogdanm 92:4fc01daae5a5 94 This parameter can be set to ENABLE or DISABLE */
bogdanm 92:4fc01daae5a5 95 uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set
bogdanm 92:4fc01daae5a5 96 at the end of single channel conversion or at the end of all conversions.
bogdanm 92:4fc01daae5a5 97 This parameter can be a value of @ref ADC_EOCSelection */
bogdanm 92:4fc01daae5a5 98 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
bogdanm 92:4fc01daae5a5 99 This parameter can be set to ENABLE or DISABLE. */
bogdanm 92:4fc01daae5a5 100 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
bogdanm 92:4fc01daae5a5 101 This parameter can be set to ENABLE or DISABLE. */
bogdanm 92:4fc01daae5a5 102 uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
bogdanm 92:4fc01daae5a5 103 regular channel group.
bogdanm 92:4fc01daae5a5 104 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
bogdanm 92:4fc01daae5a5 105 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not
bogdanm 92:4fc01daae5a5 106 for regular channels.
bogdanm 92:4fc01daae5a5 107 This parameter can be set to ENABLE or DISABLE. */
bogdanm 92:4fc01daae5a5 108 uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
bogdanm 92:4fc01daae5a5 109 using the sequencer for regular channel group.
bogdanm 92:4fc01daae5a5 110 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
bogdanm 92:4fc01daae5a5 111 uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
bogdanm 92:4fc01daae5a5 112 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
bogdanm 92:4fc01daae5a5 113 uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group.
bogdanm 92:4fc01daae5a5 114 This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
bogdanm 92:4fc01daae5a5 115 }ADC_InitTypeDef;
bogdanm 92:4fc01daae5a5 116
bogdanm 92:4fc01daae5a5 117 /**
bogdanm 92:4fc01daae5a5 118 * @brief ADC handle Structure definition
bogdanm 92:4fc01daae5a5 119 */
bogdanm 92:4fc01daae5a5 120 typedef struct
bogdanm 92:4fc01daae5a5 121 {
bogdanm 92:4fc01daae5a5 122 ADC_TypeDef *Instance; /*!< Register base address */
bogdanm 92:4fc01daae5a5 123
bogdanm 92:4fc01daae5a5 124 ADC_InitTypeDef Init; /*!< ADC required parameters */
bogdanm 92:4fc01daae5a5 125
bogdanm 92:4fc01daae5a5 126 __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
bogdanm 92:4fc01daae5a5 127
bogdanm 92:4fc01daae5a5 128 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
bogdanm 92:4fc01daae5a5 129
bogdanm 92:4fc01daae5a5 130 HAL_LockTypeDef Lock; /*!< ADC locking object */
bogdanm 92:4fc01daae5a5 131
bogdanm 92:4fc01daae5a5 132 __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
bogdanm 92:4fc01daae5a5 133
bogdanm 92:4fc01daae5a5 134 __IO uint32_t ErrorCode; /*!< ADC Error code */
bogdanm 92:4fc01daae5a5 135 }ADC_HandleTypeDef;
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 /**
bogdanm 92:4fc01daae5a5 138 * @brief ADC Configuration regular Channel structure definition
bogdanm 92:4fc01daae5a5 139 */
bogdanm 92:4fc01daae5a5 140 typedef struct
bogdanm 92:4fc01daae5a5 141 {
bogdanm 92:4fc01daae5a5 142 uint32_t Channel; /*!< The ADC channel to configure.
bogdanm 92:4fc01daae5a5 143 This parameter can be a value of @ref ADC_channels */
bogdanm 92:4fc01daae5a5 144 uint32_t Rank; /*!< The rank in the regular group sequencer.
bogdanm 92:4fc01daae5a5 145 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
bogdanm 92:4fc01daae5a5 146 uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
bogdanm 92:4fc01daae5a5 147 This parameter can be a value of @ref ADC_sampling_times */
bogdanm 92:4fc01daae5a5 148 uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
bogdanm 92:4fc01daae5a5 149 }ADC_ChannelConfTypeDef;
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151 /**
bogdanm 92:4fc01daae5a5 152 * @brief ADC Configuration multi-mode structure definition
bogdanm 92:4fc01daae5a5 153 */
bogdanm 92:4fc01daae5a5 154 typedef struct
bogdanm 92:4fc01daae5a5 155 {
bogdanm 92:4fc01daae5a5 156 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
bogdanm 92:4fc01daae5a5 157 This parameter can be a value of @ref ADC_analog_watchdog_selection */
bogdanm 92:4fc01daae5a5 158 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm 92:4fc01daae5a5 159 This parameter must be a 12-bit value. */
bogdanm 92:4fc01daae5a5 160 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm 92:4fc01daae5a5 161 This parameter must be a 12-bit value. */
bogdanm 92:4fc01daae5a5 162 uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
bogdanm 92:4fc01daae5a5 163 This parameter has an effect only if watchdog mode is configured on single channel
bogdanm 92:4fc01daae5a5 164 This parameter can be a value of @ref ADC_channels */
bogdanm 92:4fc01daae5a5 165 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
bogdanm 92:4fc01daae5a5 166 is interrupt mode or in polling mode.
bogdanm 92:4fc01daae5a5 167 This parameter can be set to ENABLE or DISABLE */
bogdanm 92:4fc01daae5a5 168 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
bogdanm 92:4fc01daae5a5 169 }ADC_AnalogWDGConfTypeDef;
bogdanm 92:4fc01daae5a5 170
bogdanm 92:4fc01daae5a5 171 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 172
bogdanm 92:4fc01daae5a5 173 /** @defgroup ADC_Exported_Constants
bogdanm 92:4fc01daae5a5 174 * @{
bogdanm 92:4fc01daae5a5 175 */
bogdanm 92:4fc01daae5a5 176
bogdanm 92:4fc01daae5a5 177
bogdanm 92:4fc01daae5a5 178 /** @defgroup ADC_Error_Code
bogdanm 92:4fc01daae5a5 179 * @{
bogdanm 92:4fc01daae5a5 180 */
bogdanm 92:4fc01daae5a5 181
bogdanm 92:4fc01daae5a5 182 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
bogdanm 92:4fc01daae5a5 183 #define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */
bogdanm 92:4fc01daae5a5 184 #define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */
bogdanm 92:4fc01daae5a5 185 /**
bogdanm 92:4fc01daae5a5 186 * @}
bogdanm 92:4fc01daae5a5 187 */
bogdanm 92:4fc01daae5a5 188
bogdanm 92:4fc01daae5a5 189
bogdanm 92:4fc01daae5a5 190 /** @defgroup ADC_ClockPrescaler
bogdanm 92:4fc01daae5a5 191 * @{
bogdanm 92:4fc01daae5a5 192 */
bogdanm 92:4fc01daae5a5 193 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 194 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
bogdanm 92:4fc01daae5a5 195 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
bogdanm 92:4fc01daae5a5 196 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
bogdanm 92:4fc01daae5a5 197 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \
bogdanm 92:4fc01daae5a5 198 ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \
bogdanm 92:4fc01daae5a5 199 ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \
bogdanm 92:4fc01daae5a5 200 ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8))
bogdanm 92:4fc01daae5a5 201 /**
bogdanm 92:4fc01daae5a5 202 * @}
bogdanm 92:4fc01daae5a5 203 */
bogdanm 92:4fc01daae5a5 204
bogdanm 92:4fc01daae5a5 205 /** @defgroup ADC_delay_between_2_sampling_phases
bogdanm 92:4fc01daae5a5 206 * @{
bogdanm 92:4fc01daae5a5 207 */
bogdanm 92:4fc01daae5a5 208 #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 209 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
bogdanm 92:4fc01daae5a5 210 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
bogdanm 92:4fc01daae5a5 211 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 212 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
bogdanm 92:4fc01daae5a5 213 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 214 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
bogdanm 92:4fc01daae5a5 215 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 216 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
bogdanm 92:4fc01daae5a5 217 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 218 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
bogdanm 92:4fc01daae5a5 219 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 220 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
bogdanm 92:4fc01daae5a5 221 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
bogdanm 92:4fc01daae5a5 222 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
bogdanm 92:4fc01daae5a5 223 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
bogdanm 92:4fc01daae5a5 224
bogdanm 92:4fc01daae5a5 225 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
bogdanm 92:4fc01daae5a5 226 ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
bogdanm 92:4fc01daae5a5 227 ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
bogdanm 92:4fc01daae5a5 228 ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
bogdanm 92:4fc01daae5a5 229 ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
bogdanm 92:4fc01daae5a5 230 ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
bogdanm 92:4fc01daae5a5 231 ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
bogdanm 92:4fc01daae5a5 232 ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
bogdanm 92:4fc01daae5a5 233 ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
bogdanm 92:4fc01daae5a5 234 ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
bogdanm 92:4fc01daae5a5 235 ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
bogdanm 92:4fc01daae5a5 236 ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
bogdanm 92:4fc01daae5a5 237 ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
bogdanm 92:4fc01daae5a5 238 ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
bogdanm 92:4fc01daae5a5 239 ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
bogdanm 92:4fc01daae5a5 240 ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
bogdanm 92:4fc01daae5a5 241 /**
bogdanm 92:4fc01daae5a5 242 * @}
bogdanm 92:4fc01daae5a5 243 */
bogdanm 92:4fc01daae5a5 244
bogdanm 92:4fc01daae5a5 245 /** @defgroup ADC_Resolution
bogdanm 92:4fc01daae5a5 246 * @{
bogdanm 92:4fc01daae5a5 247 */
bogdanm 92:4fc01daae5a5 248 #define ADC_RESOLUTION12b ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 249 #define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0)
bogdanm 92:4fc01daae5a5 250 #define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1)
bogdanm 92:4fc01daae5a5 251 #define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES)
bogdanm 92:4fc01daae5a5 252
bogdanm 92:4fc01daae5a5 253 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
bogdanm 92:4fc01daae5a5 254 ((RESOLUTION) == ADC_RESOLUTION10b) || \
bogdanm 92:4fc01daae5a5 255 ((RESOLUTION) == ADC_RESOLUTION8b) || \
bogdanm 92:4fc01daae5a5 256 ((RESOLUTION) == ADC_RESOLUTION6b))
bogdanm 92:4fc01daae5a5 257 /**
bogdanm 92:4fc01daae5a5 258 * @}
bogdanm 92:4fc01daae5a5 259 */
bogdanm 92:4fc01daae5a5 260
bogdanm 92:4fc01daae5a5 261 /** @defgroup ADC_External_trigger_edge_Regular
bogdanm 92:4fc01daae5a5 262 * @{
bogdanm 92:4fc01daae5a5 263 */
bogdanm 92:4fc01daae5a5 264 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 265 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
bogdanm 92:4fc01daae5a5 266 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
bogdanm 92:4fc01daae5a5 267 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
bogdanm 92:4fc01daae5a5 268
bogdanm 92:4fc01daae5a5 269 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
bogdanm 92:4fc01daae5a5 270 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
bogdanm 92:4fc01daae5a5 271 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
bogdanm 92:4fc01daae5a5 272 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
bogdanm 92:4fc01daae5a5 273 /**
bogdanm 92:4fc01daae5a5 274 * @}
bogdanm 92:4fc01daae5a5 275 */
bogdanm 92:4fc01daae5a5 276
bogdanm 92:4fc01daae5a5 277 /** @defgroup ADC_External_trigger_Source_Regular
bogdanm 92:4fc01daae5a5 278 * @{
bogdanm 92:4fc01daae5a5 279 */
bogdanm 92:4fc01daae5a5 280 #define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 281 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
bogdanm 92:4fc01daae5a5 282 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
bogdanm 92:4fc01daae5a5 283 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
bogdanm 92:4fc01daae5a5 284 #define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
bogdanm 92:4fc01daae5a5 285 #define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
bogdanm 92:4fc01daae5a5 286 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
bogdanm 92:4fc01daae5a5 287 #define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
bogdanm 92:4fc01daae5a5 288 #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
bogdanm 92:4fc01daae5a5 289 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
bogdanm 92:4fc01daae5a5 290 #define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
bogdanm 92:4fc01daae5a5 291 #define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
bogdanm 92:4fc01daae5a5 292 #define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
bogdanm 92:4fc01daae5a5 293 #define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
bogdanm 92:4fc01daae5a5 294 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
bogdanm 92:4fc01daae5a5 295 #define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
bogdanm 92:4fc01daae5a5 296
bogdanm 92:4fc01daae5a5 297 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
bogdanm 92:4fc01daae5a5 298 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
bogdanm 92:4fc01daae5a5 299 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
bogdanm 92:4fc01daae5a5 300 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
bogdanm 92:4fc01daae5a5 301 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
bogdanm 92:4fc01daae5a5 302 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
bogdanm 92:4fc01daae5a5 303 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
bogdanm 92:4fc01daae5a5 304 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
bogdanm 92:4fc01daae5a5 305 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
bogdanm 92:4fc01daae5a5 306 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
bogdanm 92:4fc01daae5a5 307 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
bogdanm 92:4fc01daae5a5 308 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
bogdanm 92:4fc01daae5a5 309 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
bogdanm 92:4fc01daae5a5 310 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
bogdanm 92:4fc01daae5a5 311 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
bogdanm 92:4fc01daae5a5 312 ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11))
bogdanm 92:4fc01daae5a5 313 /**
bogdanm 92:4fc01daae5a5 314 * @}
bogdanm 92:4fc01daae5a5 315 */
bogdanm 92:4fc01daae5a5 316
bogdanm 92:4fc01daae5a5 317 /** @defgroup ADC_data_align
bogdanm 92:4fc01daae5a5 318 * @{
bogdanm 92:4fc01daae5a5 319 */
bogdanm 92:4fc01daae5a5 320 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 321 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
bogdanm 92:4fc01daae5a5 322
bogdanm 92:4fc01daae5a5 323 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
bogdanm 92:4fc01daae5a5 324 ((ALIGN) == ADC_DATAALIGN_LEFT))
bogdanm 92:4fc01daae5a5 325 /**
bogdanm 92:4fc01daae5a5 326 * @}
bogdanm 92:4fc01daae5a5 327 */
bogdanm 92:4fc01daae5a5 328
bogdanm 92:4fc01daae5a5 329 /** @defgroup ADC_channels
bogdanm 92:4fc01daae5a5 330 * @{
bogdanm 92:4fc01daae5a5 331 */
bogdanm 92:4fc01daae5a5 332 #define ADC_CHANNEL_0 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 333 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
bogdanm 92:4fc01daae5a5 334 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
bogdanm 92:4fc01daae5a5 335 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
bogdanm 92:4fc01daae5a5 336 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
bogdanm 92:4fc01daae5a5 337 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
bogdanm 92:4fc01daae5a5 338 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
bogdanm 92:4fc01daae5a5 339 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
bogdanm 92:4fc01daae5a5 340 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
bogdanm 92:4fc01daae5a5 341 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
bogdanm 92:4fc01daae5a5 342 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
bogdanm 92:4fc01daae5a5 343 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
bogdanm 92:4fc01daae5a5 344 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
bogdanm 92:4fc01daae5a5 345 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
bogdanm 92:4fc01daae5a5 346 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
bogdanm 92:4fc01daae5a5 347 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
bogdanm 92:4fc01daae5a5 348 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
bogdanm 92:4fc01daae5a5 349 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
bogdanm 92:4fc01daae5a5 350 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
bogdanm 92:4fc01daae5a5 351
bogdanm 92:4fc01daae5a5 352 #define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
bogdanm 92:4fc01daae5a5 353 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
bogdanm 92:4fc01daae5a5 354 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
bogdanm 92:4fc01daae5a5 355
bogdanm 92:4fc01daae5a5 356 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
bogdanm 92:4fc01daae5a5 357 ((CHANNEL) == ADC_CHANNEL_1) || \
bogdanm 92:4fc01daae5a5 358 ((CHANNEL) == ADC_CHANNEL_2) || \
bogdanm 92:4fc01daae5a5 359 ((CHANNEL) == ADC_CHANNEL_3) || \
bogdanm 92:4fc01daae5a5 360 ((CHANNEL) == ADC_CHANNEL_4) || \
bogdanm 92:4fc01daae5a5 361 ((CHANNEL) == ADC_CHANNEL_5) || \
bogdanm 92:4fc01daae5a5 362 ((CHANNEL) == ADC_CHANNEL_6) || \
bogdanm 92:4fc01daae5a5 363 ((CHANNEL) == ADC_CHANNEL_7) || \
bogdanm 92:4fc01daae5a5 364 ((CHANNEL) == ADC_CHANNEL_8) || \
bogdanm 92:4fc01daae5a5 365 ((CHANNEL) == ADC_CHANNEL_9) || \
bogdanm 92:4fc01daae5a5 366 ((CHANNEL) == ADC_CHANNEL_10) || \
bogdanm 92:4fc01daae5a5 367 ((CHANNEL) == ADC_CHANNEL_11) || \
bogdanm 92:4fc01daae5a5 368 ((CHANNEL) == ADC_CHANNEL_12) || \
bogdanm 92:4fc01daae5a5 369 ((CHANNEL) == ADC_CHANNEL_13) || \
bogdanm 92:4fc01daae5a5 370 ((CHANNEL) == ADC_CHANNEL_14) || \
bogdanm 92:4fc01daae5a5 371 ((CHANNEL) == ADC_CHANNEL_15) || \
bogdanm 92:4fc01daae5a5 372 ((CHANNEL) == ADC_CHANNEL_16) || \
bogdanm 92:4fc01daae5a5 373 ((CHANNEL) == ADC_CHANNEL_17) || \
bogdanm 92:4fc01daae5a5 374 ((CHANNEL) == ADC_CHANNEL_18))
bogdanm 92:4fc01daae5a5 375 /**
bogdanm 92:4fc01daae5a5 376 * @}
bogdanm 92:4fc01daae5a5 377 */
bogdanm 92:4fc01daae5a5 378
bogdanm 92:4fc01daae5a5 379 /** @defgroup ADC_sampling_times
bogdanm 92:4fc01daae5a5 380 * @{
bogdanm 92:4fc01daae5a5 381 */
bogdanm 92:4fc01daae5a5 382 #define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 383 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
bogdanm 92:4fc01daae5a5 384 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
bogdanm 92:4fc01daae5a5 385 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
bogdanm 92:4fc01daae5a5 386 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
bogdanm 92:4fc01daae5a5 387 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
bogdanm 92:4fc01daae5a5 388 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
bogdanm 92:4fc01daae5a5 389 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
bogdanm 92:4fc01daae5a5 390
bogdanm 92:4fc01daae5a5 391 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
bogdanm 92:4fc01daae5a5 392 ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
bogdanm 92:4fc01daae5a5 393 ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
bogdanm 92:4fc01daae5a5 394 ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
bogdanm 92:4fc01daae5a5 395 ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
bogdanm 92:4fc01daae5a5 396 ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
bogdanm 92:4fc01daae5a5 397 ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
bogdanm 92:4fc01daae5a5 398 ((TIME) == ADC_SAMPLETIME_480CYCLES))
bogdanm 92:4fc01daae5a5 399 /**
bogdanm 92:4fc01daae5a5 400 * @}
bogdanm 92:4fc01daae5a5 401 */
bogdanm 92:4fc01daae5a5 402
bogdanm 92:4fc01daae5a5 403 /** @defgroup ADC_EOCSelection
bogdanm 92:4fc01daae5a5 404 * @{
bogdanm 92:4fc01daae5a5 405 */
bogdanm 92:4fc01daae5a5 406 #define EOC_SEQ_CONV ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 407 #define EOC_SINGLE_CONV ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 408 #define EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */
bogdanm 92:4fc01daae5a5 409
bogdanm 92:4fc01daae5a5 410 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == EOC_SINGLE_CONV) || \
bogdanm 92:4fc01daae5a5 411 ((EOCSelection) == EOC_SEQ_CONV) || \
bogdanm 92:4fc01daae5a5 412 ((EOCSelection) == EOC_SINGLE_SEQ_CONV))
bogdanm 92:4fc01daae5a5 413 /**
bogdanm 92:4fc01daae5a5 414 * @}
bogdanm 92:4fc01daae5a5 415 */
bogdanm 92:4fc01daae5a5 416
bogdanm 92:4fc01daae5a5 417 /** @defgroup ADC_Event_type
bogdanm 92:4fc01daae5a5 418 * @{
bogdanm 92:4fc01daae5a5 419 */
bogdanm 92:4fc01daae5a5 420 #define AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
bogdanm 92:4fc01daae5a5 421 #define OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
bogdanm 92:4fc01daae5a5 422
bogdanm 92:4fc01daae5a5 423 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
bogdanm 92:4fc01daae5a5 424 ((EVENT) == OVR_EVENT))
bogdanm 92:4fc01daae5a5 425 /**
bogdanm 92:4fc01daae5a5 426 * @}
bogdanm 92:4fc01daae5a5 427 */
bogdanm 92:4fc01daae5a5 428
bogdanm 92:4fc01daae5a5 429 /** @defgroup ADC_analog_watchdog_selection
bogdanm 92:4fc01daae5a5 430 * @{
bogdanm 92:4fc01daae5a5 431 */
bogdanm 92:4fc01daae5a5 432 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
bogdanm 92:4fc01daae5a5 433 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
bogdanm 92:4fc01daae5a5 434 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
bogdanm 92:4fc01daae5a5 435 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
bogdanm 92:4fc01daae5a5 436 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
bogdanm 92:4fc01daae5a5 437 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
bogdanm 92:4fc01daae5a5 438 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 439
bogdanm 92:4fc01daae5a5 440 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
bogdanm 92:4fc01daae5a5 441 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
bogdanm 92:4fc01daae5a5 442 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
bogdanm 92:4fc01daae5a5 443 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
bogdanm 92:4fc01daae5a5 444 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
bogdanm 92:4fc01daae5a5 445 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
bogdanm 92:4fc01daae5a5 446 ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
bogdanm 92:4fc01daae5a5 447 /**
bogdanm 92:4fc01daae5a5 448 * @}
bogdanm 92:4fc01daae5a5 449 */
bogdanm 92:4fc01daae5a5 450
bogdanm 92:4fc01daae5a5 451 /** @defgroup ADC_interrupts_definition
bogdanm 92:4fc01daae5a5 452 * @{
bogdanm 92:4fc01daae5a5 453 */
bogdanm 92:4fc01daae5a5 454 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
bogdanm 92:4fc01daae5a5 455 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
bogdanm 92:4fc01daae5a5 456 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
bogdanm 92:4fc01daae5a5 457 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
bogdanm 92:4fc01daae5a5 458
bogdanm 92:4fc01daae5a5 459 #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
bogdanm 92:4fc01daae5a5 460 ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
bogdanm 92:4fc01daae5a5 461 /**
bogdanm 92:4fc01daae5a5 462 * @}
bogdanm 92:4fc01daae5a5 463 */
bogdanm 92:4fc01daae5a5 464
bogdanm 92:4fc01daae5a5 465 /** @defgroup ADC_flags_definition
bogdanm 92:4fc01daae5a5 466 * @{
bogdanm 92:4fc01daae5a5 467 */
bogdanm 92:4fc01daae5a5 468 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
bogdanm 92:4fc01daae5a5 469 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
bogdanm 92:4fc01daae5a5 470 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
bogdanm 92:4fc01daae5a5 471 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
bogdanm 92:4fc01daae5a5 472 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
bogdanm 92:4fc01daae5a5 473 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
bogdanm 92:4fc01daae5a5 474 /**
bogdanm 92:4fc01daae5a5 475 * @}
bogdanm 92:4fc01daae5a5 476 */
bogdanm 92:4fc01daae5a5 477
bogdanm 92:4fc01daae5a5 478 /** @defgroup ADC_channels_type
bogdanm 92:4fc01daae5a5 479 * @{
bogdanm 92:4fc01daae5a5 480 */
bogdanm 92:4fc01daae5a5 481 #define ALL_CHANNELS ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 482 #define REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */
bogdanm 92:4fc01daae5a5 483 #define INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
bogdanm 92:4fc01daae5a5 484
bogdanm 92:4fc01daae5a5 485 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ALL_CHANNELS) || \
bogdanm 92:4fc01daae5a5 486 ((CHANNEL_TYPE) == REGULAR_CHANNELS) || \
bogdanm 92:4fc01daae5a5 487 ((CHANNEL_TYPE) == INJECTED_CHANNELS))
bogdanm 92:4fc01daae5a5 488 /**
bogdanm 92:4fc01daae5a5 489 * @}
bogdanm 92:4fc01daae5a5 490 */
bogdanm 92:4fc01daae5a5 491
bogdanm 92:4fc01daae5a5 492 /** @defgroup ADC_thresholds
bogdanm 92:4fc01daae5a5 493 * @{
bogdanm 92:4fc01daae5a5 494 */
bogdanm 92:4fc01daae5a5 495 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
bogdanm 92:4fc01daae5a5 496 /**
bogdanm 92:4fc01daae5a5 497 * @}
bogdanm 92:4fc01daae5a5 498 */
bogdanm 92:4fc01daae5a5 499
bogdanm 92:4fc01daae5a5 500 /** @defgroup ADC_regular_length
bogdanm 92:4fc01daae5a5 501 * @{
bogdanm 92:4fc01daae5a5 502 */
bogdanm 92:4fc01daae5a5 503 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
bogdanm 92:4fc01daae5a5 504 /**
bogdanm 92:4fc01daae5a5 505 * @}
bogdanm 92:4fc01daae5a5 506 */
bogdanm 92:4fc01daae5a5 507
bogdanm 92:4fc01daae5a5 508 /** @defgroup ADC_regular_rank
bogdanm 92:4fc01daae5a5 509 * @{
bogdanm 92:4fc01daae5a5 510 */
bogdanm 92:4fc01daae5a5 511 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
bogdanm 92:4fc01daae5a5 512 /**
bogdanm 92:4fc01daae5a5 513 * @}
bogdanm 92:4fc01daae5a5 514 */
bogdanm 92:4fc01daae5a5 515
bogdanm 92:4fc01daae5a5 516 /** @defgroup ADC_regular_discontinuous_mode_number
bogdanm 92:4fc01daae5a5 517 * @{
bogdanm 92:4fc01daae5a5 518 */
bogdanm 92:4fc01daae5a5 519 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
bogdanm 92:4fc01daae5a5 520 /**
bogdanm 92:4fc01daae5a5 521 * @}
bogdanm 92:4fc01daae5a5 522 */
bogdanm 92:4fc01daae5a5 523
bogdanm 92:4fc01daae5a5 524 /** @defgroup ADC_range_verification
bogdanm 92:4fc01daae5a5 525 * @{
bogdanm 92:4fc01daae5a5 526 */
bogdanm 92:4fc01daae5a5 527 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
bogdanm 92:4fc01daae5a5 528 ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
bogdanm 92:4fc01daae5a5 529 (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
bogdanm 92:4fc01daae5a5 530 (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
bogdanm 92:4fc01daae5a5 531 (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
bogdanm 92:4fc01daae5a5 532 /**
bogdanm 92:4fc01daae5a5 533 * @}
bogdanm 92:4fc01daae5a5 534 */
bogdanm 92:4fc01daae5a5 535
bogdanm 92:4fc01daae5a5 536 /**
bogdanm 92:4fc01daae5a5 537 * @}
bogdanm 92:4fc01daae5a5 538 */
bogdanm 92:4fc01daae5a5 539
bogdanm 92:4fc01daae5a5 540 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 541
bogdanm 92:4fc01daae5a5 542 /** @brief Reset ADC handle state
bogdanm 92:4fc01daae5a5 543 * @param __HANDLE__: ADC handle
bogdanm 92:4fc01daae5a5 544 * @retval None
bogdanm 92:4fc01daae5a5 545 */
bogdanm 92:4fc01daae5a5 546 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
bogdanm 92:4fc01daae5a5 547
bogdanm 92:4fc01daae5a5 548 /**
bogdanm 92:4fc01daae5a5 549 * @brief Enable the ADC peripheral.
bogdanm 92:4fc01daae5a5 550 * @param __HANDLE__: ADC handle
bogdanm 92:4fc01daae5a5 551 * @retval None
bogdanm 92:4fc01daae5a5 552 */
bogdanm 92:4fc01daae5a5 553 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
bogdanm 92:4fc01daae5a5 554
bogdanm 92:4fc01daae5a5 555 /**
bogdanm 92:4fc01daae5a5 556 * @brief Disable the ADC peripheral.
bogdanm 92:4fc01daae5a5 557 * @param __HANDLE__: ADC handle
bogdanm 92:4fc01daae5a5 558 * @retval None
bogdanm 92:4fc01daae5a5 559 */
bogdanm 92:4fc01daae5a5 560 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
bogdanm 92:4fc01daae5a5 561
bogdanm 92:4fc01daae5a5 562 /**
bogdanm 92:4fc01daae5a5 563 * @brief Set ADC Regular channel sequence length.
bogdanm 92:4fc01daae5a5 564 * @param _NbrOfConversion_: Regular channel sequence length.
bogdanm 92:4fc01daae5a5 565 * @retval None
bogdanm 92:4fc01daae5a5 566 */
bogdanm 92:4fc01daae5a5 567 #define __HAL_ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
bogdanm 92:4fc01daae5a5 568
bogdanm 92:4fc01daae5a5 569 /**
bogdanm 92:4fc01daae5a5 570 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
bogdanm 92:4fc01daae5a5 571 * @param _SAMPLETIME_: Sample time parameter.
bogdanm 92:4fc01daae5a5 572 * @param _CHANNELNB_: Channel number.
bogdanm 92:4fc01daae5a5 573 * @retval None
bogdanm 92:4fc01daae5a5 574 */
bogdanm 92:4fc01daae5a5 575 #define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
bogdanm 92:4fc01daae5a5 576
bogdanm 92:4fc01daae5a5 577 /**
bogdanm 92:4fc01daae5a5 578 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
bogdanm 92:4fc01daae5a5 579 * @param _SAMPLETIME_: Sample time parameter.
bogdanm 92:4fc01daae5a5 580 * @param _CHANNELNB_: Channel number.
bogdanm 92:4fc01daae5a5 581 * @retval None
bogdanm 92:4fc01daae5a5 582 */
bogdanm 92:4fc01daae5a5 583 #define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
bogdanm 92:4fc01daae5a5 584
bogdanm 92:4fc01daae5a5 585 /**
bogdanm 92:4fc01daae5a5 586 * @brief Set the selected regular channel rank for rank between 1 and 6.
bogdanm 92:4fc01daae5a5 587 * @param _CHANNELNB_: Channel number.
bogdanm 92:4fc01daae5a5 588 * @param _RANKNB_: Rank number.
bogdanm 92:4fc01daae5a5 589 * @retval None
bogdanm 92:4fc01daae5a5 590 */
bogdanm 92:4fc01daae5a5 591 #define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
bogdanm 92:4fc01daae5a5 592
bogdanm 92:4fc01daae5a5 593 /**
bogdanm 92:4fc01daae5a5 594 * @brief Set the selected regular channel rank for rank between 7 and 12.
bogdanm 92:4fc01daae5a5 595 * @param _CHANNELNB_: Channel number.
bogdanm 92:4fc01daae5a5 596 * @param _RANKNB_: Rank number.
bogdanm 92:4fc01daae5a5 597 * @retval None
bogdanm 92:4fc01daae5a5 598 */
bogdanm 92:4fc01daae5a5 599 #define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
bogdanm 92:4fc01daae5a5 600
bogdanm 92:4fc01daae5a5 601 /**
bogdanm 92:4fc01daae5a5 602 * @brief Set the selected regular channel rank for rank between 13 and 16.
bogdanm 92:4fc01daae5a5 603 * @param _CHANNELNB_: Channel number.
bogdanm 92:4fc01daae5a5 604 * @param _RANKNB_: Rank number.
bogdanm 92:4fc01daae5a5 605 * @retval None
bogdanm 92:4fc01daae5a5 606 */
bogdanm 92:4fc01daae5a5 607 #define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
bogdanm 92:4fc01daae5a5 608
bogdanm 92:4fc01daae5a5 609 /**
bogdanm 92:4fc01daae5a5 610 * @brief Enable ADC continuous conversion mode.
bogdanm 92:4fc01daae5a5 611 * @param _CONTINUOUS_MODE_: Continuous mode.
bogdanm 92:4fc01daae5a5 612 * @retval None
bogdanm 92:4fc01daae5a5 613 */
bogdanm 92:4fc01daae5a5 614 #define __HAL_ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
bogdanm 92:4fc01daae5a5 615
bogdanm 92:4fc01daae5a5 616 /**
bogdanm 92:4fc01daae5a5 617 * @brief Configures the number of discontinuous conversions for the regular group channels.
bogdanm 92:4fc01daae5a5 618 * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
bogdanm 92:4fc01daae5a5 619 * @retval None
bogdanm 92:4fc01daae5a5 620 */
bogdanm 92:4fc01daae5a5 621 #define __HAL_ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13)
bogdanm 92:4fc01daae5a5 622
bogdanm 92:4fc01daae5a5 623 /**
bogdanm 92:4fc01daae5a5 624 * @brief Enable ADC scan mode.
bogdanm 92:4fc01daae5a5 625 * @param _SCANCONV_MODE_: Scan conversion mode.
bogdanm 92:4fc01daae5a5 626 * @retval None
bogdanm 92:4fc01daae5a5 627 */
bogdanm 92:4fc01daae5a5 628 #define __HAL_ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
bogdanm 92:4fc01daae5a5 629
bogdanm 92:4fc01daae5a5 630 /**
bogdanm 92:4fc01daae5a5 631 * @brief Enable the ADC end of conversion selection.
bogdanm 92:4fc01daae5a5 632 * @param _EOCSelection_MODE_: End of conversion selection mode.
bogdanm 92:4fc01daae5a5 633 * @retval None
bogdanm 92:4fc01daae5a5 634 */
bogdanm 92:4fc01daae5a5 635 #define __HAL_ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
bogdanm 92:4fc01daae5a5 636
bogdanm 92:4fc01daae5a5 637 /**
bogdanm 92:4fc01daae5a5 638 * @brief Enable the ADC DMA continuous request.
bogdanm 92:4fc01daae5a5 639 * @param _DMAContReq_MODE_: DMA continuous request mode.
bogdanm 92:4fc01daae5a5 640 * @retval None
bogdanm 92:4fc01daae5a5 641 */
bogdanm 92:4fc01daae5a5 642 #define __HAL_ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
bogdanm 92:4fc01daae5a5 643
bogdanm 92:4fc01daae5a5 644 /**
bogdanm 92:4fc01daae5a5 645 * @brief Enable the ADC end of conversion interrupt.
bogdanm 92:4fc01daae5a5 646 * @param __HANDLE__: specifies the ADC Handle.
bogdanm 92:4fc01daae5a5 647 * @param __INTERRUPT__: ADC Interrupt.
bogdanm 92:4fc01daae5a5 648 * @retval None
bogdanm 92:4fc01daae5a5 649 */
bogdanm 92:4fc01daae5a5 650 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 651
bogdanm 92:4fc01daae5a5 652 /**
bogdanm 92:4fc01daae5a5 653 * @brief Disable the ADC end of conversion interrupt.
bogdanm 92:4fc01daae5a5 654 * @param __HANDLE__: specifies the ADC Handle.
bogdanm 92:4fc01daae5a5 655 * @param __INTERRUPT__: ADC interrupt.
bogdanm 92:4fc01daae5a5 656 * @retval None
bogdanm 92:4fc01daae5a5 657 */
bogdanm 92:4fc01daae5a5 658 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
bogdanm 92:4fc01daae5a5 659
bogdanm 92:4fc01daae5a5 660 /** @brief Check if the specified ADC interrupt source is enabled or disabled.
bogdanm 92:4fc01daae5a5 661 * @param __HANDLE__: specifies the ADC Handle.
bogdanm 92:4fc01daae5a5 662 * @param __INTERRUPT__: specifies the ADC interrupt source to check.
bogdanm 92:4fc01daae5a5 663 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 664 */
bogdanm 92:4fc01daae5a5 665 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 92:4fc01daae5a5 666
bogdanm 92:4fc01daae5a5 667 /**
bogdanm 92:4fc01daae5a5 668 * @brief Clear the ADC's pending flags.
bogdanm 92:4fc01daae5a5 669 * @param __HANDLE__: specifies the ADC Handle.
bogdanm 92:4fc01daae5a5 670 * @param __FLAG__: ADC flag.
bogdanm 92:4fc01daae5a5 671 * @retval None
bogdanm 92:4fc01daae5a5 672 */
bogdanm 92:4fc01daae5a5 673 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
bogdanm 92:4fc01daae5a5 674
bogdanm 92:4fc01daae5a5 675 /**
bogdanm 92:4fc01daae5a5 676 * @brief Get the selected ADC's flag status.
bogdanm 92:4fc01daae5a5 677 * @param __HANDLE__: specifies the ADC Handle.
bogdanm 92:4fc01daae5a5 678 * @param __FLAG__: ADC flag.
bogdanm 92:4fc01daae5a5 679 * @retval None
bogdanm 92:4fc01daae5a5 680 */
bogdanm 92:4fc01daae5a5 681 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 682
bogdanm 92:4fc01daae5a5 683 /**
bogdanm 92:4fc01daae5a5 684 * @brief Return resolution bits in CR1 register.
bogdanm 92:4fc01daae5a5 685 * @param __HANDLE__: ADC handle
bogdanm 92:4fc01daae5a5 686 * @retval None
bogdanm 92:4fc01daae5a5 687 */
bogdanm 92:4fc01daae5a5 688 #define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
bogdanm 92:4fc01daae5a5 689
bogdanm 92:4fc01daae5a5 690 /* Include ADC HAL Extension module */
bogdanm 92:4fc01daae5a5 691 #include "stm32f4xx_hal_adc_ex.h"
bogdanm 92:4fc01daae5a5 692
bogdanm 92:4fc01daae5a5 693 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 694 /* Initialization/de-initialization functions ***********************************/
bogdanm 92:4fc01daae5a5 695 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 696 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
bogdanm 92:4fc01daae5a5 697 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 698 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 699
bogdanm 92:4fc01daae5a5 700 /* I/O operation functions ******************************************************/
bogdanm 92:4fc01daae5a5 701 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 702 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 703 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 704
bogdanm 92:4fc01daae5a5 705 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 706
bogdanm 92:4fc01daae5a5 707 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 708 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 709
bogdanm 92:4fc01daae5a5 710 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 711
bogdanm 92:4fc01daae5a5 712 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
bogdanm 92:4fc01daae5a5 713 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 714
bogdanm 92:4fc01daae5a5 715 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 716
bogdanm 92:4fc01daae5a5 717 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 718 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 719 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 720 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
bogdanm 92:4fc01daae5a5 721
bogdanm 92:4fc01daae5a5 722 /* Peripheral Control functions *************************************************/
bogdanm 92:4fc01daae5a5 723 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
bogdanm 92:4fc01daae5a5 724 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
bogdanm 92:4fc01daae5a5 725
bogdanm 92:4fc01daae5a5 726 /* Peripheral State functions ***************************************************/
bogdanm 92:4fc01daae5a5 727 HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 728 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
bogdanm 92:4fc01daae5a5 729
bogdanm 92:4fc01daae5a5 730 /**
bogdanm 92:4fc01daae5a5 731 * @}
bogdanm 92:4fc01daae5a5 732 */
bogdanm 92:4fc01daae5a5 733
bogdanm 92:4fc01daae5a5 734 /**
bogdanm 92:4fc01daae5a5 735 * @}
bogdanm 92:4fc01daae5a5 736 */
bogdanm 92:4fc01daae5a5 737
bogdanm 92:4fc01daae5a5 738 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 739 }
bogdanm 92:4fc01daae5a5 740 #endif
bogdanm 92:4fc01daae5a5 741
bogdanm 92:4fc01daae5a5 742 #endif /*__STM32F4xx_ADC_H */
bogdanm 92:4fc01daae5a5 743
bogdanm 92:4fc01daae5a5 744
bogdanm 92:4fc01daae5a5 745 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/