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TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:: Kojto
Date:: Wed Nov 25 13:21:40 2015 +0000
Revision:: 110:165afa46840b
Parent:: 106:ba1f97679dad

Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_hal_rcc_ex.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
Kojto	110:165afa46840b	5	* @version V1.4.1
Kojto	110:165afa46840b	6	* @date 09-October-2015
emilmont	77:869cf507173a	7	* @brief Header file of RCC HAL Extension module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
Kojto	99:dbbf35b96557	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_HAL_RCC_EX_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	47	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	48
emilmont	77:869cf507173a	49	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	50	* @{
emilmont	77:869cf507173a	51	*/
emilmont	77:869cf507173a	52
emilmont	77:869cf507173a	53	/** @addtogroup RCCEx
emilmont	77:869cf507173a	54	* @{
emilmont	77:869cf507173a	55	*/
emilmont	77:869cf507173a	56
Kojto	99:dbbf35b96557	57	/* Exported types ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto	99:dbbf35b96557	59	* @{
Kojto	99:dbbf35b96557	60	*/
Kojto	99:dbbf35b96557	61
Kojto	99:dbbf35b96557	62	/**
Kojto	99:dbbf35b96557	63	* @brief RCC PLL configuration structure definition
Kojto	99:dbbf35b96557	64	*/
Kojto	99:dbbf35b96557	65	typedef struct
Kojto	99:dbbf35b96557	66	{
Kojto	99:dbbf35b96557	67	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	99:dbbf35b96557	68	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	99:dbbf35b96557	69
Kojto	99:dbbf35b96557	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto	110:165afa46840b	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	99:dbbf35b96557	72
Kojto	99:dbbf35b96557	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto	110:165afa46840b	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
Kojto	99:dbbf35b96557	75
Kojto	99:dbbf35b96557	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto	99:dbbf35b96557	77	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	99:dbbf35b96557	78
Kojto	99:dbbf35b96557	79	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
Kojto	99:dbbf35b96557	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto	99:dbbf35b96557	81
Kojto	99:dbbf35b96557	82	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	83	This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
Kojto	110:165afa46840b	84	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
Kojto	110:165afa46840b	85	defined(STM32F479xx)
Kojto	99:dbbf35b96557	86	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	110:165afa46840b	87	This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx and STM32F479xx
Kojto	110:165afa46840b	88	devices.
Kojto	99:dbbf35b96557	89	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
Kojto	110:165afa46840b	90	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	91	}RCC_PLLInitTypeDef;
Kojto	99:dbbf35b96557	92
Kojto	99:dbbf35b96557	93	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	94	/**
Kojto	99:dbbf35b96557	95	* @brief PLLI2S Clock structure definition
Kojto	99:dbbf35b96557	96	*/
Kojto	99:dbbf35b96557	97	typedef struct
Kojto	99:dbbf35b96557	98	{
Kojto	99:dbbf35b96557	99	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
Kojto	110:165afa46840b	100	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	99:dbbf35b96557	101
Kojto	99:dbbf35b96557	102	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	99:dbbf35b96557	103	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	99:dbbf35b96557	104
Kojto	99:dbbf35b96557	105	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
Kojto	99:dbbf35b96557	106	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
Kojto	99:dbbf35b96557	107
Kojto	99:dbbf35b96557	108	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
Kojto	99:dbbf35b96557	109	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	110	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	111
Kojto	99:dbbf35b96557	112	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	99:dbbf35b96557	113	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	114	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
Kojto	99:dbbf35b96557	115	}RCC_PLLI2SInitTypeDef;
Kojto	99:dbbf35b96557	116
Kojto	99:dbbf35b96557	117	/**
Kojto	99:dbbf35b96557	118	* @brief PLLSAI Clock structure definition
Kojto	99:dbbf35b96557	119	*/
Kojto	99:dbbf35b96557	120	typedef struct
Kojto	99:dbbf35b96557	121	{
Kojto	99:dbbf35b96557	122	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
Kojto	110:165afa46840b	123	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	99:dbbf35b96557	124
Kojto	99:dbbf35b96557	125	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	110:165afa46840b	126	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	99:dbbf35b96557	127
Kojto	99:dbbf35b96557	128	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	129	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
Kojto	99:dbbf35b96557	130
Kojto	99:dbbf35b96557	131	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
Kojto	99:dbbf35b96557	132	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	133	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	134	}RCC_PLLSAIInitTypeDef;
Kojto	99:dbbf35b96557	135	/**
Kojto	99:dbbf35b96557	136	* @brief RCC extended clocks structure definition
Kojto	99:dbbf35b96557	137	*/
Kojto	99:dbbf35b96557	138	typedef struct
Kojto	99:dbbf35b96557	139	{
Kojto	99:dbbf35b96557	140	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	99:dbbf35b96557	141	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	99:dbbf35b96557	142
Kojto	99:dbbf35b96557	143	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	99:dbbf35b96557	144	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	99:dbbf35b96557	145
Kojto	99:dbbf35b96557	146	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto	99:dbbf35b96557	147	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto	99:dbbf35b96557	148
Kojto	99:dbbf35b96557	149	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	99:dbbf35b96557	150	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	99:dbbf35b96557	151	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	152
Kojto	99:dbbf35b96557	153	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	99:dbbf35b96557	154	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	99:dbbf35b96557	155	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	156
Kojto	99:dbbf35b96557	157	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
Kojto	99:dbbf35b96557	158	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto	99:dbbf35b96557	159
Kojto	99:dbbf35b96557	160	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
Kojto	99:dbbf35b96557	161	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto	99:dbbf35b96557	162
Kojto	99:dbbf35b96557	163	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
Kojto	99:dbbf35b96557	164	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
Kojto	99:dbbf35b96557	165
Kojto	99:dbbf35b96557	166	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
Kojto	99:dbbf35b96557	167	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
Kojto	99:dbbf35b96557	168
Kojto	99:dbbf35b96557	169	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	99:dbbf35b96557	170	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	99:dbbf35b96557	171
Kojto	99:dbbf35b96557	172	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	99:dbbf35b96557	173	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	99:dbbf35b96557	174
Kojto	99:dbbf35b96557	175	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
Kojto	99:dbbf35b96557	176	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	99:dbbf35b96557	177
Kojto	99:dbbf35b96557	178	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	99:dbbf35b96557	179	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	99:dbbf35b96557	180
Kojto	99:dbbf35b96557	181	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
Kojto	99:dbbf35b96557	182	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
Kojto	99:dbbf35b96557	183
Kojto	99:dbbf35b96557	184	uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	185	This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
Kojto	99:dbbf35b96557	186
Kojto	99:dbbf35b96557	187	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	99:dbbf35b96557	188	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	99:dbbf35b96557	189	}RCC_PeriphCLKInitTypeDef;
Kojto	99:dbbf35b96557	190	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	191
Kojto	110:165afa46840b	192	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	193	/**
Kojto	110:165afa46840b	194	* @brief RCC extended clocks structure definition
Kojto	110:165afa46840b	195	*/
Kojto	110:165afa46840b	196	typedef struct
Kojto	110:165afa46840b	197	{
Kojto	110:165afa46840b	198	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	110:165afa46840b	199	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	110:165afa46840b	200
Kojto	110:165afa46840b	201	uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	110:165afa46840b	202	This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
Kojto	110:165afa46840b	203
Kojto	110:165afa46840b	204	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	110:165afa46840b	205	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	110:165afa46840b	206
Kojto	110:165afa46840b	207	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
Kojto	110:165afa46840b	208	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto	110:165afa46840b	209
Kojto	110:165afa46840b	210	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	110:165afa46840b	211	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	110:165afa46840b	212	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	110:165afa46840b	213	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	110:165afa46840b	214	}RCC_PeriphCLKInitTypeDef;
Kojto	110:165afa46840b	215	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	216
Kojto	110:165afa46840b	217	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	218
emilmont	77:869cf507173a	219	/**
emilmont	77:869cf507173a	220	* @brief PLLI2S Clock structure definition
emilmont	77:869cf507173a	221	*/
emilmont	77:869cf507173a	222	typedef struct
emilmont	77:869cf507173a	223	{
bogdanm	85:024bf7f99721	224	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	85:024bf7f99721	225	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont	77:869cf507173a	226	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	227
bogdanm	85:024bf7f99721	228	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	85:024bf7f99721	229	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont	77:869cf507173a	230	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	231
emilmont	77:869cf507173a	232	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	85:024bf7f99721	233	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
emilmont	77:869cf507173a	234	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
emilmont	77:869cf507173a	235	}RCC_PLLI2SInitTypeDef;
emilmont	77:869cf507173a	236
emilmont	77:869cf507173a	237	/**
emilmont	77:869cf507173a	238	* @brief PLLSAI Clock structure definition
emilmont	77:869cf507173a	239	*/
emilmont	77:869cf507173a	240	typedef struct
emilmont	77:869cf507173a	241	{
emilmont	77:869cf507173a	242	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	85:024bf7f99721	243	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont	77:869cf507173a	244	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto	110:165afa46840b	245	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	246	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
Kojto	110:165afa46840b	247	This parameter is only available in STM32F469xx/STM32F479xx devices.
Kojto	110:165afa46840b	248	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
Kojto	110:165afa46840b	249	#endif /* STM32F469xx \|\| STM32F479xx */
emilmont	77:869cf507173a	250
emilmont	77:869cf507173a	251	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	85:024bf7f99721	252	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
emilmont	77:869cf507173a	253	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
emilmont	77:869cf507173a	254
emilmont	77:869cf507173a	255	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
bogdanm	85:024bf7f99721	256	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont	77:869cf507173a	257	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
emilmont	77:869cf507173a	258
emilmont	77:869cf507173a	259	}RCC_PLLSAIInitTypeDef;
emilmont	77:869cf507173a	260	/**
emilmont	77:869cf507173a	261	* @brief RCC extended clocks structure definition
emilmont	77:869cf507173a	262	*/
emilmont	77:869cf507173a	263	typedef struct
emilmont	77:869cf507173a	264	{
emilmont	77:869cf507173a	265	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
emilmont	77:869cf507173a	266	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
emilmont	77:869cf507173a	267
bogdanm	85:024bf7f99721	268	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
emilmont	77:869cf507173a	269	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	270
bogdanm	85:024bf7f99721	271	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
emilmont	77:869cf507173a	272	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
emilmont	77:869cf507173a	273
bogdanm	85:024bf7f99721	274	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
emilmont	77:869cf507173a	275	This parameter must be a number between Min_Data = 1 and Max_Data = 32
emilmont	77:869cf507173a	276	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
emilmont	77:869cf507173a	277
emilmont	77:869cf507173a	278	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
emilmont	77:869cf507173a	279	This parameter must be a number between Min_Data = 1 and Max_Data = 32
emilmont	77:869cf507173a	280	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
emilmont	77:869cf507173a	281
emilmont	77:869cf507173a	282	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
emilmont	77:869cf507173a	283	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
emilmont	77:869cf507173a	284
bogdanm	85:024bf7f99721	285	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
emilmont	77:869cf507173a	286	This parameter can be a value of @ref RCC_RTC_Clock_Source */
emilmont	77:869cf507173a	287
bogdanm	85:024bf7f99721	288	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
emilmont	77:869cf507173a	289	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	110:165afa46840b	290	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	291	uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	110:165afa46840b	292	This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
Kojto	110:165afa46840b	293
Kojto	110:165afa46840b	294	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	110:165afa46840b	295	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	110:165afa46840b	296	#endif /* STM32F469xx \|\| STM32F479xx */
emilmont	77:869cf507173a	297	}RCC_PeriphCLKInitTypeDef;
Kojto	110:165afa46840b	298	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	299
Kojto	110:165afa46840b	300	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
Kojto	90:cb3d968589d8	301	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
emilmont	77:869cf507173a	302	/**
emilmont	77:869cf507173a	303	* @brief PLLI2S Clock structure definition
emilmont	77:869cf507173a	304	*/
emilmont	77:869cf507173a	305	typedef struct
emilmont	77:869cf507173a	306	{
Kojto	110:165afa46840b	307	#if defined(STM32F411xE)
Kojto	90:cb3d968589d8	308	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
Kojto	90:cb3d968589d8	309	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
Kojto	90:cb3d968589d8	310	#endif /* STM32F411xE */
Kojto	90:cb3d968589d8	311
bogdanm	85:024bf7f99721	312	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
emilmont	77:869cf507173a	313	This parameter must be a number between Min_Data = 192 and Max_Data = 432
emilmont	77:869cf507173a	314	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	315
bogdanm	85:024bf7f99721	316	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	85:024bf7f99721	317	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont	77:869cf507173a	318	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	319
emilmont	77:869cf507173a	320	}RCC_PLLI2SInitTypeDef;
emilmont	77:869cf507173a	321
emilmont	77:869cf507173a	322
emilmont	77:869cf507173a	323	/**
emilmont	77:869cf507173a	324	* @brief RCC extended clocks structure definition
emilmont	77:869cf507173a	325	*/
emilmont	77:869cf507173a	326	typedef struct
emilmont	77:869cf507173a	327	{
emilmont	77:869cf507173a	328	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
emilmont	77:869cf507173a	329	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
emilmont	77:869cf507173a	330
bogdanm	85:024bf7f99721	331	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
emilmont	77:869cf507173a	332	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont	77:869cf507173a	333
bogdanm	85:024bf7f99721	334	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto	110:165afa46840b	335	This parameter can be a value of @ref RCC_RTC_Clock_Source */
emilmont	77:869cf507173a	336
emilmont	77:869cf507173a	337	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	338	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	99:dbbf35b96557	339	/**
Kojto	99:dbbf35b96557	340	* @}
Kojto	99:dbbf35b96557	341	*/
Kojto	99:dbbf35b96557	342
emilmont	77:869cf507173a	343	/* Exported constants --------------------------------------------------------*/
Kojto	99:dbbf35b96557	344	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
emilmont	77:869cf507173a	345	* @{
emilmont	77:869cf507173a	346	*/
emilmont	77:869cf507173a	347
Kojto	99:dbbf35b96557	348	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
emilmont	77:869cf507173a	349	* @{
emilmont	77:869cf507173a	350	*/
Kojto	110:165afa46840b	351	/------------------- Peripheral Clock source for STM32F410xx ----------------/
Kojto	110:165afa46840b	352	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	353	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto	110:165afa46840b	354	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002)
Kojto	110:165afa46840b	355	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004)
Kojto	110:165afa46840b	356	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000008)
Kojto	110:165afa46840b	357	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000010)
Kojto	110:165afa46840b	358	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	359	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	360
Kojto	110:165afa46840b	361	/------------------- Peripheral Clock source for STM32F446xx ----------------/
Kojto	99:dbbf35b96557	362	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	363	#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001)
Kojto	99:dbbf35b96557	364	#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002)
Kojto	99:dbbf35b96557	365	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004)
Kojto	99:dbbf35b96557	366	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008)
Kojto	99:dbbf35b96557	367	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto	99:dbbf35b96557	368	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto	99:dbbf35b96557	369	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040)
Kojto	99:dbbf35b96557	370	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080)
Kojto	99:dbbf35b96557	371	#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000100)
Kojto	99:dbbf35b96557	372	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200)
Kojto	99:dbbf35b96557	373	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400)
Kojto	99:dbbf35b96557	374	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800)
Kojto	99:dbbf35b96557	375	#endif /* STM32F446xx */
Kojto	110:165afa46840b	376	/-----------------------------------------------------------------------------/
Kojto	110:165afa46840b	377
Kojto	110:165afa46840b	378	/----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------/
Kojto	110:165afa46840b	379	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	380	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto	110:165afa46840b	381	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
Kojto	110:165afa46840b	382	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
Kojto	110:165afa46840b	383	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
Kojto	110:165afa46840b	384	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto	110:165afa46840b	385	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto	110:165afa46840b	386	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
Kojto	110:165afa46840b	387	#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000080)
Kojto	110:165afa46840b	388	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000100)
Kojto	110:165afa46840b	389	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	390	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	391
Kojto	110:165afa46840b	392	/-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------/
Kojto	99:dbbf35b96557	393	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
emilmont	77:869cf507173a	394	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
emilmont	77:869cf507173a	395	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
emilmont	77:869cf507173a	396	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
emilmont	77:869cf507173a	397	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
emilmont	77:869cf507173a	398	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
emilmont	77:869cf507173a	399	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto	99:dbbf35b96557	400	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
emilmont	77:869cf507173a	401	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	110:165afa46840b	402	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	403
Kojto	110:165afa46840b	404	/-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------/
Kojto	90:cb3d968589d8	405	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
Kojto	90:cb3d968589d8	406	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
emilmont	77:869cf507173a	407	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
emilmont	77:869cf507173a	408	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
Kojto	99:dbbf35b96557	409	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	410	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	110:165afa46840b	411	/----------------------------------------------------------------------------/
emilmont	77:869cf507173a	412	/**
emilmont	77:869cf507173a	413	* @}
emilmont	77:869cf507173a	414	*/
Kojto	110:165afa46840b	415	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	416	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	417	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	110:165afa46840b	418	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	419	/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
Kojto	110:165afa46840b	420	* @{
Kojto	110:165afa46840b	421	*/
Kojto	110:165afa46840b	422	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto	110:165afa46840b	423	#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
Kojto	110:165afa46840b	424	/**
Kojto	110:165afa46840b	425	* @}
Kojto	110:165afa46840b	426	*/
Kojto	110:165afa46840b	427	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	110:165afa46840b	428	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
emilmont	77:869cf507173a	429
Kojto	99:dbbf35b96557	430	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
emilmont	77:869cf507173a	431	* @{
Kojto	99:dbbf35b96557	432	*/
Kojto	110:165afa46840b	433	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
Kojto	110:165afa46840b	434	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	435	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	436	#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
Kojto	99:dbbf35b96557	437	#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
Kojto	99:dbbf35b96557	438	#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
Kojto	110:165afa46840b	439	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
emilmont	77:869cf507173a	440	/**
emilmont	77:869cf507173a	441	* @}
emilmont	77:869cf507173a	442	*/
emilmont	77:869cf507173a	443
Kojto	99:dbbf35b96557	444	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
emilmont	77:869cf507173a	445	* @{
emilmont	77:869cf507173a	446	*/
Kojto	110:165afa46840b	447	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	448	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002)
Kojto	99:dbbf35b96557	449	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004)
Kojto	99:dbbf35b96557	450	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006)
Kojto	99:dbbf35b96557	451	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008)
Kojto	110:165afa46840b	452	#endif /* STM32F446xx */
emilmont	77:869cf507173a	453	/**
emilmont	77:869cf507173a	454	* @}
emilmont	77:869cf507173a	455	*/
emilmont	77:869cf507173a	456
Kojto	99:dbbf35b96557	457	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
emilmont	77:869cf507173a	458	* @{
Kojto	99:dbbf35b96557	459	*/
Kojto	110:165afa46840b	460	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	461	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002)
Kojto	99:dbbf35b96557	462	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004)
Kojto	99:dbbf35b96557	463	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006)
Kojto	99:dbbf35b96557	464	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008)
Kojto	110:165afa46840b	465	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
emilmont	77:869cf507173a	466	/**
emilmont	77:869cf507173a	467	* @}
emilmont	77:869cf507173a	468	*/
emilmont	77:869cf507173a	469
Kojto	110:165afa46840b	470	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	471	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
emilmont	77:869cf507173a	472	* @{
emilmont	77:869cf507173a	473	*/
emilmont	77:869cf507173a	474	#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
emilmont	77:869cf507173a	475	#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
emilmont	77:869cf507173a	476	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
emilmont	77:869cf507173a	477	/**
emilmont	77:869cf507173a	478	* @}
emilmont	77:869cf507173a	479	*/
emilmont	77:869cf507173a	480
Kojto	99:dbbf35b96557	481	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
emilmont	77:869cf507173a	482	* @{
emilmont	77:869cf507173a	483	*/
emilmont	77:869cf507173a	484	#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
emilmont	77:869cf507173a	485	#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
emilmont	77:869cf507173a	486	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
emilmont	77:869cf507173a	487	/**
emilmont	77:869cf507173a	488	* @}
emilmont	77:869cf507173a	489	*/
Kojto	110:165afa46840b	490	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	491
Kojto	110:165afa46840b	492	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	493	/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
Kojto	110:165afa46840b	494	* @{
Kojto	110:165afa46840b	495	*/
Kojto	110:165afa46840b	496	#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
Kojto	110:165afa46840b	497	#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
Kojto	110:165afa46840b	498	/**
Kojto	110:165afa46840b	499	* @}
Kojto	110:165afa46840b	500	*/
Kojto	110:165afa46840b	501
Kojto	110:165afa46840b	502	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	110:165afa46840b	503	* @{
Kojto	110:165afa46840b	504	*/
Kojto	110:165afa46840b	505	#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
Kojto	110:165afa46840b	506	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
Kojto	110:165afa46840b	507	/**
Kojto	110:165afa46840b	508	* @}
Kojto	110:165afa46840b	509	*/
Kojto	110:165afa46840b	510
Kojto	110:165afa46840b	511	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
Kojto	110:165afa46840b	512	* @{
Kojto	110:165afa46840b	513	*/
Kojto	110:165afa46840b	514	#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000)
Kojto	110:165afa46840b	515	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
Kojto	110:165afa46840b	516	/**
Kojto	110:165afa46840b	517	* @}
Kojto	110:165afa46840b	518	*/
Kojto	110:165afa46840b	519	#endif /* STM32F469xx \|\| STM32F479xx */
emilmont	77:869cf507173a	520
Kojto	99:dbbf35b96557	521	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	522	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
Kojto	99:dbbf35b96557	523	* @{
Kojto	99:dbbf35b96557	524	*/
Kojto	99:dbbf35b96557	525	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	526	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
Kojto	99:dbbf35b96557	527	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
Kojto	99:dbbf35b96557	528	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
Kojto	99:dbbf35b96557	529	/**
Kojto	99:dbbf35b96557	530	* @}
Kojto	99:dbbf35b96557	531	*/
Kojto	99:dbbf35b96557	532
Kojto	99:dbbf35b96557	533	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
Kojto	99:dbbf35b96557	534	* @{
Kojto	99:dbbf35b96557	535	*/
Kojto	99:dbbf35b96557	536	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	537	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
Kojto	99:dbbf35b96557	538	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
Kojto	99:dbbf35b96557	539	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
Kojto	99:dbbf35b96557	540	/**
Kojto	99:dbbf35b96557	541	* @}
Kojto	99:dbbf35b96557	542	*/
Kojto	99:dbbf35b96557	543
Kojto	99:dbbf35b96557	544	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
Kojto	99:dbbf35b96557	545	* @{
Kojto	99:dbbf35b96557	546	*/
Kojto	99:dbbf35b96557	547	#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	548	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
Kojto	99:dbbf35b96557	549	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
Kojto	99:dbbf35b96557	550	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
Kojto	99:dbbf35b96557	551	/**
Kojto	99:dbbf35b96557	552	* @}
Kojto	99:dbbf35b96557	553	*/
Kojto	99:dbbf35b96557	554
Kojto	99:dbbf35b96557	555	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
Kojto	99:dbbf35b96557	556	* @{
Kojto	99:dbbf35b96557	557	*/
Kojto	99:dbbf35b96557	558	#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	559	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
Kojto	99:dbbf35b96557	560	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
Kojto	99:dbbf35b96557	561	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
Kojto	99:dbbf35b96557	562	/**
Kojto	99:dbbf35b96557	563	* @}
Kojto	99:dbbf35b96557	564	*/
Kojto	99:dbbf35b96557	565
Kojto	99:dbbf35b96557	566	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	99:dbbf35b96557	567	* @{
Kojto	99:dbbf35b96557	568	*/
Kojto	99:dbbf35b96557	569	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	570	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
Kojto	99:dbbf35b96557	571	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	99:dbbf35b96557	572	/**
Kojto	99:dbbf35b96557	573	* @}
Kojto	99:dbbf35b96557	574	*/
Kojto	99:dbbf35b96557	575
Kojto	99:dbbf35b96557	576	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
Kojto	99:dbbf35b96557	577	* @{
Kojto	99:dbbf35b96557	578	*/
Kojto	99:dbbf35b96557	579	#define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	580	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
Kojto	99:dbbf35b96557	581	/**
Kojto	99:dbbf35b96557	582	* @}
Kojto	99:dbbf35b96557	583	*/
Kojto	99:dbbf35b96557	584
Kojto	99:dbbf35b96557	585	/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
Kojto	99:dbbf35b96557	586	* @{
Kojto	99:dbbf35b96557	587	*/
Kojto	99:dbbf35b96557	588	#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	589	#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
Kojto	99:dbbf35b96557	590	/**
Kojto	99:dbbf35b96557	591	* @}
Kojto	99:dbbf35b96557	592	*/
Kojto	99:dbbf35b96557	593
Kojto	99:dbbf35b96557	594	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	99:dbbf35b96557	595	* @{
Kojto	99:dbbf35b96557	596	*/
Kojto	99:dbbf35b96557	597	#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	598	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
Kojto	99:dbbf35b96557	599	/**
Kojto	99:dbbf35b96557	600	* @}
Kojto	99:dbbf35b96557	601	*/
Kojto	99:dbbf35b96557	602
Kojto	99:dbbf35b96557	603	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
Kojto	99:dbbf35b96557	604	* @{
Kojto	99:dbbf35b96557	605	*/
Kojto	99:dbbf35b96557	606	#define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	607	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
Kojto	99:dbbf35b96557	608	/**
Kojto	99:dbbf35b96557	609	* @}
Kojto	99:dbbf35b96557	610	*/
Kojto	110:165afa46840b	611
Kojto	99:dbbf35b96557	612	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	613
Kojto	110:165afa46840b	614	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	615
Kojto	110:165afa46840b	616	/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
Kojto	110:165afa46840b	617	* @{
Kojto	110:165afa46840b	618	*/
Kojto	110:165afa46840b	619	#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
Kojto	110:165afa46840b	620	#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
Kojto	110:165afa46840b	621	#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
Kojto	110:165afa46840b	622	/**
Kojto	110:165afa46840b	623	* @}
Kojto	110:165afa46840b	624	*/
Kojto	110:165afa46840b	625
Kojto	110:165afa46840b	626	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	110:165afa46840b	627	* @{
Kojto	110:165afa46840b	628	*/
Kojto	110:165afa46840b	629	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
Kojto	110:165afa46840b	630	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
Kojto	110:165afa46840b	631	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	110:165afa46840b	632	/**
Kojto	110:165afa46840b	633	* @}
Kojto	110:165afa46840b	634	*/
Kojto	110:165afa46840b	635
Kojto	110:165afa46840b	636	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
Kojto	110:165afa46840b	637	* @{
Kojto	110:165afa46840b	638	*/
Kojto	110:165afa46840b	639	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
Kojto	110:165afa46840b	640	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
Kojto	110:165afa46840b	641	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
Kojto	110:165afa46840b	642	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
Kojto	110:165afa46840b	643	/**
Kojto	110:165afa46840b	644	* @}
Kojto	110:165afa46840b	645	*/
Kojto	110:165afa46840b	646
Kojto	99:dbbf35b96557	647	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
emilmont	77:869cf507173a	648	* @{
emilmont	77:869cf507173a	649	*/
emilmont	77:869cf507173a	650	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
emilmont	77:869cf507173a	651	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
emilmont	77:869cf507173a	652	/**
emilmont	77:869cf507173a	653	* @}
emilmont	77:869cf507173a	654	*/
Kojto	110:165afa46840b	655	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	656
Kojto	110:165afa46840b	657	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	658	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\|\
Kojto	110:165afa46840b	659	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	660	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
Kojto	110:165afa46840b	661	* @{
Kojto	110:165afa46840b	662	*/
Kojto	110:165afa46840b	663	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
Kojto	110:165afa46840b	664	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
Kojto	110:165afa46840b	665	/**
Kojto	110:165afa46840b	666	* @}
Kojto	110:165afa46840b	667	*/
Kojto	110:165afa46840b	668	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
Kojto	110:165afa46840b	669	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	670
Kojto	110:165afa46840b	671	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
Kojto	110:165afa46840b	672	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	673	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
Kojto	90:cb3d968589d8	674	* @{
Kojto	90:cb3d968589d8	675	*/
Kojto	90:cb3d968589d8	676	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
Kojto	90:cb3d968589d8	677	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
Kojto	90:cb3d968589d8	678	/**
Kojto	90:cb3d968589d8	679	* @}
Kojto	90:cb3d968589d8	680	*/
Kojto	110:165afa46840b	681	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	682
Kojto	110:165afa46840b	683
Kojto	110:165afa46840b	684	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	685	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	686	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	110:165afa46840b	687	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	688	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
Kojto	110:165afa46840b	689	* @{
Kojto	110:165afa46840b	690	*/
Kojto	110:165afa46840b	691	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
Kojto	110:165afa46840b	692	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
Kojto	110:165afa46840b	693	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto	110:165afa46840b	694	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto	110:165afa46840b	695	/**
Kojto	110:165afa46840b	696	* @}
Kojto	110:165afa46840b	697	*/
Kojto	110:165afa46840b	698	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	110:165afa46840b	699	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	700
Kojto	110:165afa46840b	701	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	702	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
Kojto	110:165afa46840b	703	* @{
Kojto	110:165afa46840b	704	*/
Kojto	110:165afa46840b	705	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
Kojto	110:165afa46840b	706	#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
Kojto	110:165afa46840b	707	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto	110:165afa46840b	708	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto	110:165afa46840b	709	/**
Kojto	110:165afa46840b	710	* @}
Kojto	110:165afa46840b	711	*/
Kojto	110:165afa46840b	712	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	713
emilmont	77:869cf507173a	714	/**
emilmont	77:869cf507173a	715	* @}
emilmont	77:869cf507173a	716	*/
emilmont	77:869cf507173a	717
emilmont	77:869cf507173a	718	/* Exported macro ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	719	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto	99:dbbf35b96557	720	* @{
Kojto	99:dbbf35b96557	721	*/
Kojto	110:165afa46840b	722	/------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------/
Kojto	110:165afa46840b	723	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	724	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	725	* @brief Enables or disables the AHB1 peripheral clock.
emilmont	77:869cf507173a	726	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	727	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	728	* using it.
emilmont	77:869cf507173a	729	*/
Kojto	110:165afa46840b	730	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	110:165afa46840b	731	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	732	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	733	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	734	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	735	UNUSED(tmpreg); \
Kojto	110:165afa46840b	736	} while(0)
Kojto	110:165afa46840b	737	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	110:165afa46840b	738	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	739	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	740	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	741	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	742	UNUSED(tmpreg); \
Kojto	110:165afa46840b	743	} while(0)
Kojto	110:165afa46840b	744	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	110:165afa46840b	745	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	746	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	747	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	748	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	749	UNUSED(tmpreg); \
Kojto	110:165afa46840b	750	} while(0)
Kojto	110:165afa46840b	751	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	110:165afa46840b	752	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	753	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	754	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	755	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	756	UNUSED(tmpreg); \
Kojto	110:165afa46840b	757	} while(0)
Kojto	110:165afa46840b	758	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	110:165afa46840b	759	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	760	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	761	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	762	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	763	UNUSED(tmpreg); \
Kojto	110:165afa46840b	764	} while(0)
Kojto	99:dbbf35b96557	765	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	766	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	767	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	768	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	769	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	770	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	771	} while(0)
Kojto	99:dbbf35b96557	772	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	773	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	774	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	775	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	776	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	777	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	778	} while(0)
Kojto	99:dbbf35b96557	779	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	780	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	781	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	782	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	783	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	784	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	785	} while(0)
Kojto	99:dbbf35b96557	786	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	787	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	788	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	99:dbbf35b96557	789	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	790	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	99:dbbf35b96557	791	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	792	} while(0)
Kojto	99:dbbf35b96557	793	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	794	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	795	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	99:dbbf35b96557	796	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	797	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	99:dbbf35b96557	798	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	799	} while(0)
Kojto	99:dbbf35b96557	800	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	801	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	802	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	99:dbbf35b96557	803	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	804	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	99:dbbf35b96557	805	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	806	} while(0)
Kojto	99:dbbf35b96557	807	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	808	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	809	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	810	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	811	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	812	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	813	} while(0)
Kojto	99:dbbf35b96557	814	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	815	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	816	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	817	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	818	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	819	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	820	} while(0)
Kojto	99:dbbf35b96557	821	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	822	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	823	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	824	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	825	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	826	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	827	} while(0)
Kojto	99:dbbf35b96557	828	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	829	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	830	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	831	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	832	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	833	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	834	} while(0)
Kojto	99:dbbf35b96557	835	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	836	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	837	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	838	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	839	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	840	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	841	} while(0)
Kojto	99:dbbf35b96557	842	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	843	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	844	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	845	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	846	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	847	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	848	} while(0)
Kojto	110:165afa46840b	849	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	850	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	99:dbbf35b96557	851	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	852	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	853	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	99:dbbf35b96557	854	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto	99:dbbf35b96557	855	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto	99:dbbf35b96557	856	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto	99:dbbf35b96557	857	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	99:dbbf35b96557	858	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	99:dbbf35b96557	859	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	99:dbbf35b96557	860	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	99:dbbf35b96557	861	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	862	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	110:165afa46840b	863	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	864	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	865	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	90:cb3d968589d8	866
Kojto	90:cb3d968589d8	867	/**
Kojto	90:cb3d968589d8	868	* @brief Enable ETHERNET clock.
Kojto	90:cb3d968589d8	869	*/
Kojto	99:dbbf35b96557	870	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	871	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	872	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	873	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	874	} while(0)
Kojto	90:cb3d968589d8	875	/**
Kojto	90:cb3d968589d8	876	* @brief Disable ETHERNET clock.
Kojto	90:cb3d968589d8	877	*/
Kojto	99:dbbf35b96557	878	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	99:dbbf35b96557	879	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	880	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	881	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	882	} while(0)
Kojto	110:165afa46840b	883	/**
Kojto	110:165afa46840b	884	* @}
Kojto	110:165afa46840b	885	*/
Kojto	110:165afa46840b	886
Kojto	110:165afa46840b	887	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	888	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	90:cb3d968589d8	889	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	890	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	891	* using it.
Kojto	90:cb3d968589d8	892	*/
Kojto	110:165afa46840b	893	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	894	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	895	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	896	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	897	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	898	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	899	} while(0)
Kojto	99:dbbf35b96557	900	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	90:cb3d968589d8	901
Kojto	110:165afa46840b	902	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	903	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	904	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	905	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	906	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	907	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	908	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	909	} while(0)
Kojto	99:dbbf35b96557	910	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	911	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	912	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	913	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	914	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	915	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	916	} while(0)
Kojto	90:cb3d968589d8	917
Kojto	99:dbbf35b96557	918	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	99:dbbf35b96557	919	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto	110:165afa46840b	920	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	110:165afa46840b	921	/**
Kojto	110:165afa46840b	922	* @}
Kojto	110:165afa46840b	923	*/
Kojto	110:165afa46840b	924
Kojto	110:165afa46840b	925	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	926	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	110:165afa46840b	927	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	928	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	929	* using it.
Kojto	110:165afa46840b	930	* @{
Kojto	110:165afa46840b	931	*/
Kojto	110:165afa46840b	932	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	933	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	110:165afa46840b	934	}while(0)
Kojto	110:165afa46840b	935
Kojto	110:165afa46840b	936	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	937	__HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto	110:165afa46840b	938	}while(0)
Kojto	110:165afa46840b	939
Kojto	110:165afa46840b	940	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	110:165afa46840b	941	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	942	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	943	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	944	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	945	UNUSED(tmpreg); \
Kojto	110:165afa46840b	946	} while(0)
Kojto	110:165afa46840b	947	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	110:165afa46840b	948	/**
Kojto	110:165afa46840b	949	* @}
Kojto	110:165afa46840b	950	*/
Kojto	110:165afa46840b	951
Kojto	110:165afa46840b	952	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	953	* @brief Enables or disables the AHB3 peripheral clock.
Kojto	90:cb3d968589d8	954	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	955	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	956	* using it.
Kojto	90:cb3d968589d8	957	*/
Kojto	99:dbbf35b96557	958	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	959	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	960	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	961	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	962	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	963	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	964	} while(0)
Kojto	99:dbbf35b96557	965	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	110:165afa46840b	966	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	967	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	110:165afa46840b	968	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	969	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	110:165afa46840b	970	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	971	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	110:165afa46840b	972	UNUSED(tmpreg); \
Kojto	110:165afa46840b	973	} while(0)
Kojto	110:165afa46840b	974	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	110:165afa46840b	975	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	976	/**
Kojto	110:165afa46840b	977	* @}
Kojto	110:165afa46840b	978	*/
Kojto	110:165afa46840b	979
Kojto	110:165afa46840b	980	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	981	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	90:cb3d968589d8	982	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	983	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	984	* using it.
Kojto	90:cb3d968589d8	985	*/
Kojto	99:dbbf35b96557	986	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	987	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	988	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	989	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	990	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	991	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	992	} while(0)
Kojto	99:dbbf35b96557	993	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	994	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	995	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	996	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	997	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	998	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	999	} while(0)
Kojto	99:dbbf35b96557	1000	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1001	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1002	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1003	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1004	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1005	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1006	} while(0)
Kojto	99:dbbf35b96557	1007	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1008	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1009	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1010	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1011	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1012	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1013	} while(0)
Kojto	99:dbbf35b96557	1014	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1015	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1016	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1017	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1018	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1019	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1020	} while(0)
Kojto	99:dbbf35b96557	1021	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1022	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1023	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1024	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1025	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1026	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1027	} while(0)
Kojto	99:dbbf35b96557	1028	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1029	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1030	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1031	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1032	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1033	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1034	} while(0)
Kojto	99:dbbf35b96557	1035	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1036	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1037	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1038	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1039	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1040	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1041	} while(0)
Kojto	99:dbbf35b96557	1042	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1043	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1044	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1045	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1046	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1047	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1048	} while(0)
Kojto	99:dbbf35b96557	1049	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1050	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1051	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1052	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1053	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1054	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1055	} while(0)
Kojto	99:dbbf35b96557	1056	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1057	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1058	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1059	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1060	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1061	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1062	} while(0)
Kojto	99:dbbf35b96557	1063	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1064	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1065	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1066	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1067	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1068	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1069	} while(0)
Kojto	99:dbbf35b96557	1070	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1071	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1072	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	99:dbbf35b96557	1073	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1074	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	99:dbbf35b96557	1075	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1076	} while(0)
Kojto	99:dbbf35b96557	1077	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1078	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1079	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	99:dbbf35b96557	1080	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1081	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	99:dbbf35b96557	1082	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1083	} while(0)
Kojto	110:165afa46840b	1084	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1085	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1086	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	1087	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1088	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	1089	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1090	} while(0)
Kojto	110:165afa46840b	1091	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1092	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1093	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	1094	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1095	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	1096	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1097	} while(0)
Kojto	110:165afa46840b	1098	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1099	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1100	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	1101	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1102	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	1103	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1104	} while(0)
Kojto	110:165afa46840b	1105	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1106	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1107	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	1108	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1109	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	1110	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1111	} while(0)
Kojto	110:165afa46840b	1112	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1113	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1114	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	1115	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1116	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	1117	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1118	} while(0)
Kojto	110:165afa46840b	1119	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	1120	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	1121	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	1122	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	1123	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	99:dbbf35b96557	1124	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	1125	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	1126	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	1127	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	1128	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	1129	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	1130	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	1131	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	1132	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	1133	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	1134	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	99:dbbf35b96557	1135	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto	99:dbbf35b96557	1136	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto	110:165afa46840b	1137	/**
Kojto	110:165afa46840b	1138	* @}
Kojto	110:165afa46840b	1139	*/
Kojto	110:165afa46840b	1140
Kojto	110:165afa46840b	1141	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1142	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	90:cb3d968589d8	1143	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	1144	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	1145	* using it.
Kojto	90:cb3d968589d8	1146	*/
Kojto	99:dbbf35b96557	1147	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1148	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1149	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1150	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1151	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1152	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1153	} while(0)
Kojto	99:dbbf35b96557	1154	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1155	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1156	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1157	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1158	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1159	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1160	} while(0)
Kojto	99:dbbf35b96557	1161	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1162	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1163	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1164	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1165	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1166	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1167	} while(0)
Kojto	99:dbbf35b96557	1168	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1169	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1170	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	1171	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1172	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	1173	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1174	} while(0)
Kojto	99:dbbf35b96557	1175	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1176	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1177	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	99:dbbf35b96557	1178	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1179	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	99:dbbf35b96557	1180	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1181	} while(0)
Kojto	99:dbbf35b96557	1182	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1183	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1184	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	1185	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1186	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	1187	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1188	} while(0)
Kojto	110:165afa46840b	1189	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1190	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1191	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	1192	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1193	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	1194	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1195	} while(0)
Kojto	110:165afa46840b	1196	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1197	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1198	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	1199	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1200	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	1201	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1202	} while(0)
Kojto	110:165afa46840b	1203	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1204	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1205	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	1206	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1207	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	1208	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1209	} while(0)
Kojto	110:165afa46840b	1210	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	1211	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	1212	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	1213	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	110:165afa46840b	1214	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	110:165afa46840b	1215	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	110:165afa46840b	1216	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	110:165afa46840b	1217	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto	110:165afa46840b	1218	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	110:165afa46840b	1219
Kojto	110:165afa46840b	1220	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1221	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1222	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1223	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto	110:165afa46840b	1224	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1225	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto	110:165afa46840b	1226	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1227	} while(0)
Kojto	90:cb3d968589d8	1228
Kojto	99:dbbf35b96557	1229	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto	110:165afa46840b	1230	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1231
Kojto	110:165afa46840b	1232	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1233	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1234	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1235	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
Kojto	110:165afa46840b	1236	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1237	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
Kojto	110:165afa46840b	1238	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1239	} while(0)
Kojto	110:165afa46840b	1240
Kojto	110:165afa46840b	1241	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
Kojto	110:165afa46840b	1242	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1243	/**
Kojto	110:165afa46840b	1244	* @}
Kojto	110:165afa46840b	1245	*/
Kojto	110:165afa46840b	1246
Kojto	110:165afa46840b	1247	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	1248	* @brief Force or release AHB1 peripheral reset.
Kojto	110:165afa46840b	1249	*/
Kojto	110:165afa46840b	1250	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	1251	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	1252	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	1253	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	1254	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	1255	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	1256	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	99:dbbf35b96557	1257	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
Kojto	99:dbbf35b96557	1258	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
Kojto	99:dbbf35b96557	1259	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
Kojto	110:165afa46840b	1260	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	1261
Kojto	110:165afa46840b	1262	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	1263	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	1264	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	1265	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	1266	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	1267	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	1268	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	99:dbbf35b96557	1269	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto	99:dbbf35b96557	1270	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto	99:dbbf35b96557	1271	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto	110:165afa46840b	1272	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	1273	/**
Kojto	110:165afa46840b	1274	* @}
Kojto	110:165afa46840b	1275	*/
Kojto	110:165afa46840b	1276
Kojto	110:165afa46840b	1277	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	1278	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	1279	* @{
Kojto	110:165afa46840b	1280	*/
Kojto	110:165afa46840b	1281	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	1282	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	1283	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	1284	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	110:165afa46840b	1285
Kojto	110:165afa46840b	1286	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto	110:165afa46840b	1287	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	1288	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	1289	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	90:cb3d968589d8	1290
Kojto	110:165afa46840b	1291	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1292	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	1293	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
Kojto	90:cb3d968589d8	1294
Kojto	99:dbbf35b96557	1295	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	1296	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto	110:165afa46840b	1297	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1298	/**
Kojto	110:165afa46840b	1299	* @}
Kojto	110:165afa46840b	1300	*/
Kojto	110:165afa46840b	1301
Kojto	110:165afa46840b	1302	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	1303	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	1304	* @{
Kojto	90:cb3d968589d8	1305	*/
Kojto	110:165afa46840b	1306	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	1307	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto	99:dbbf35b96557	1308	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	1309	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	110:165afa46840b	1310
Kojto	110:165afa46840b	1311	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1312	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	110:165afa46840b	1313	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	110:165afa46840b	1314	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1315	/**
Kojto	110:165afa46840b	1316	* @}
Kojto	110:165afa46840b	1317	*/
Kojto	110:165afa46840b	1318
Kojto	110:165afa46840b	1319	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	1320	* @brief Force or release APB1 peripheral reset.
Kojto	90:cb3d968589d8	1321	*/
Kojto	99:dbbf35b96557	1322	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	1323	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	1324	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	1325	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	1326	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	1327	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	1328	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	1329	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	1330	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	1331	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	1332	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	99:dbbf35b96557	1333	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
Kojto	99:dbbf35b96557	1334	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
Kojto	110:165afa46840b	1335	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	1336	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	1337	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	1338	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	1339	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	1340
Kojto	110:165afa46840b	1341	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	1342	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	1343	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	1344	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	1345	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	99:dbbf35b96557	1346	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	1347	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	1348	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	1349	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	1350	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	1351	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	1352	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	1353	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	1354	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	1355	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	1356	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	99:dbbf35b96557	1357	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto	99:dbbf35b96557	1358	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto	110:165afa46840b	1359	/**
Kojto	110:165afa46840b	1360	* @}
Kojto	110:165afa46840b	1361	*/
Kojto	110:165afa46840b	1362
Kojto	110:165afa46840b	1363	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	1364	* @brief Force or release APB2 peripheral reset.
Kojto	90:cb3d968589d8	1365	*/
Kojto	99:dbbf35b96557	1366	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	99:dbbf35b96557	1367	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	99:dbbf35b96557	1368	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
Kojto	99:dbbf35b96557	1369	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	110:165afa46840b	1370	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	1371	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	1372	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	1373
Kojto	110:165afa46840b	1374	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	1375	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	1376	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	99:dbbf35b96557	1377	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	99:dbbf35b96557	1378	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	99:dbbf35b96557	1379	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto	99:dbbf35b96557	1380	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto	90:cb3d968589d8	1381
Kojto	110:165afa46840b	1382	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1383	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
Kojto	99:dbbf35b96557	1384	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto	110:165afa46840b	1385	#endif /* STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1386
Kojto	110:165afa46840b	1387	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1388	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
Kojto	110:165afa46840b	1389	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
Kojto	110:165afa46840b	1390	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1391	/**
Kojto	110:165afa46840b	1392	* @}
Kojto	110:165afa46840b	1393	*/
Kojto	110:165afa46840b	1394
Kojto	110:165afa46840b	1395	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1396	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	1397	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	1398	* power consumption.
Kojto	90:cb3d968589d8	1399	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	1400	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	1401	*/
Kojto	110:165afa46840b	1402	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	1403	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	1404	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	1405	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	1406	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	1407	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	1408	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	1409	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	1410	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	1411	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	1412	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	1413	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	99:dbbf35b96557	1414	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto	99:dbbf35b96557	1415	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto	99:dbbf35b96557	1416	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
Kojto	99:dbbf35b96557	1417	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto	110:165afa46840b	1418	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	1419	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	1420	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	1421	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	1422
Kojto	110:165afa46840b	1423	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	1424	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	1425	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	1426	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	1427	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	1428	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	1429	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	1430	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	1431	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	1432	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	1433	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	1434	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	99:dbbf35b96557	1435	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto	99:dbbf35b96557	1436	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto	99:dbbf35b96557	1437	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto	110:165afa46840b	1438	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	1439	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	1440	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	1441	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	1442	/**
Kojto	110:165afa46840b	1443	* @}
Kojto	110:165afa46840b	1444	*/
Kojto	110:165afa46840b	1445
Kojto	110:165afa46840b	1446	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1447	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	1448	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	1449	* power consumption.
Kojto	110:165afa46840b	1450	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	1451	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	1452	* @{
Kojto	110:165afa46840b	1453	*/
Kojto	110:165afa46840b	1454	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	1455	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	1456
Kojto	110:165afa46840b	1457	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	1458	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	1459
Kojto	99:dbbf35b96557	1460	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	1461	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	90:cb3d968589d8	1462
Kojto	110:165afa46840b	1463	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1464	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	1465	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
Kojto	90:cb3d968589d8	1466
Kojto	99:dbbf35b96557	1467	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	1468	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto	110:165afa46840b	1469	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1470	/**
Kojto	110:165afa46840b	1471	* @}
Kojto	110:165afa46840b	1472	*/
Kojto	110:165afa46840b	1473
Kojto	110:165afa46840b	1474	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1475	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	1476	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	1477	* power consumption.
Kojto	90:cb3d968589d8	1478	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	1479	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	1480	*/
Kojto	99:dbbf35b96557	1481	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	1482	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto	90:cb3d968589d8	1483
Kojto	110:165afa46840b	1484	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1485	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	110:165afa46840b	1486	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	110:165afa46840b	1487	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1488	/**
Kojto	110:165afa46840b	1489	* @}
Kojto	110:165afa46840b	1490	*/
Kojto	110:165afa46840b	1491
Kojto	110:165afa46840b	1492	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1493	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	1494	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	1495	* power consumption.
Kojto	90:cb3d968589d8	1496	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	1497	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	1498	*/
Kojto	99:dbbf35b96557	1499	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1500	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1501	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1502	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1503	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1504	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1505	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1506	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1507	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1508	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1509	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	99:dbbf35b96557	1510	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
Kojto	99:dbbf35b96557	1511	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
Kojto	110:165afa46840b	1512	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	1513	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	1514	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	1515	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	1516	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	1517
Kojto	110:165afa46840b	1518	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	1519	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	1520	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	1521	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	1522	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	99:dbbf35b96557	1523	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1524	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1525	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1526	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1527	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1528	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1529	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1530	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1531	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1532	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1533	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	99:dbbf35b96557	1534	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto	99:dbbf35b96557	1535	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto	110:165afa46840b	1536	/**
Kojto	110:165afa46840b	1537	* @}
Kojto	110:165afa46840b	1538	*/
Kojto	110:165afa46840b	1539
Kojto	110:165afa46840b	1540	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1541	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	1542	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	1543	* power consumption.
Kojto	90:cb3d968589d8	1544	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	1545	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	1546	*/
Kojto	99:dbbf35b96557	1547	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	1548	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	1549	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	1550	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	99:dbbf35b96557	1551	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
Kojto	99:dbbf35b96557	1552	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	110:165afa46840b	1553	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	1554	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	1555	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	1556
Kojto	110:165afa46840b	1557	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	1558	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	1559	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	99:dbbf35b96557	1560	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	1561	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	1562	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	1563	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	99:dbbf35b96557	1564	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto	99:dbbf35b96557	1565	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto	90:cb3d968589d8	1566
Kojto	110:165afa46840b	1567	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1568	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
Kojto	90:cb3d968589d8	1569
Kojto	99:dbbf35b96557	1570	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto	110:165afa46840b	1571	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1572
Kojto	110:165afa46840b	1573	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1574	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
Kojto	110:165afa46840b	1575	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
Kojto	110:165afa46840b	1576	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1577	/**
Kojto	110:165afa46840b	1578	* @}
Kojto	110:165afa46840b	1579	*/
Kojto	110:165afa46840b	1580	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1581	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	1582
Kojto	110:165afa46840b	1583	/----------------------------------- STM32F40xxx/STM32F41xxx-----------------/
Kojto	90:cb3d968589d8	1584	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	110:165afa46840b	1585	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1586	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	90:cb3d968589d8	1587	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	1588	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	1589	* using it.
Kojto	90:cb3d968589d8	1590	*/
Kojto	110:165afa46840b	1591	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1592	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1593	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	1594	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1595	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	1596	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1597	} while(0)
Kojto	110:165afa46840b	1598	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1599	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1600	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	1601	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1602	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	1603	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1604	} while(0)
Kojto	110:165afa46840b	1605	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1606	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1607	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	1608	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1609	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	1610	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1611	} while(0)
Kojto	110:165afa46840b	1612	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1613	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1614	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	1615	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1616	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	1617	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1618	} while(0)
Kojto	110:165afa46840b	1619	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1620	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1621	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	1622	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1623	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	1624	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1625	} while(0)
Kojto	99:dbbf35b96557	1626	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1627	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1628	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	1629	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1630	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	1631	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1632	} while(0)
Kojto	99:dbbf35b96557	1633	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1634	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1635	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	1636	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1637	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	1638	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1639	} while(0)
Kojto	99:dbbf35b96557	1640	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1641	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1642	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	1643	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1644	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	1645	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1646	} while(0)
Kojto	99:dbbf35b96557	1647	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1648	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1649	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	1650	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1651	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	1652	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1653	} while(0)
Kojto	99:dbbf35b96557	1654	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1655	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1656	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	1657	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1658	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	1659	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1660	} while(0)
Kojto	110:165afa46840b	1661	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	1662	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	99:dbbf35b96557	1663	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	1664	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	1665	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	99:dbbf35b96557	1666	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	1667	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	110:165afa46840b	1668	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	1669	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	1670	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	90:cb3d968589d8	1671	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	90:cb3d968589d8	1672	/**
Kojto	90:cb3d968589d8	1673	* @brief Enable ETHERNET clock.
Kojto	90:cb3d968589d8	1674	*/
Kojto	99:dbbf35b96557	1675	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1676	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1677	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	1678	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1679	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	1680	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1681	} while(0)
Kojto	99:dbbf35b96557	1682	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1683	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1684	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	1685	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1686	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	1687	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1688	} while(0)
Kojto	99:dbbf35b96557	1689	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1690	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1691	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	1692	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1693	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	1694	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1695	} while(0)
Kojto	99:dbbf35b96557	1696	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1697	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1698	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	1699	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1700	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	1701	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1702	} while(0)
Kojto	99:dbbf35b96557	1703	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1704	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	1705	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	1706	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	1707	} while(0)
emilmont	77:869cf507173a	1708
emilmont	77:869cf507173a	1709	/**
emilmont	77:869cf507173a	1710	* @brief Disable ETHERNET clock.
emilmont	77:869cf507173a	1711	*/
Kojto	99:dbbf35b96557	1712	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	99:dbbf35b96557	1713	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	99:dbbf35b96557	1714	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	99:dbbf35b96557	1715	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	99:dbbf35b96557	1716	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	99:dbbf35b96557	1717	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	1718	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	1719	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
emilmont	77:869cf507173a	1720	} while(0)
Kojto	90:cb3d968589d8	1721	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	110:165afa46840b	1722	/**
Kojto	110:165afa46840b	1723	* @}
Kojto	110:165afa46840b	1724	*/
Kojto	110:165afa46840b	1725
Kojto	110:165afa46840b	1726	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1727	* @brief Enable or disable the AHB2 peripheral clock.
emilmont	77:869cf507173a	1728	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	1729	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	1730	* using it.
emilmont	77:869cf507173a	1731	*/
Kojto	110:165afa46840b	1732	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	1733	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	110:165afa46840b	1734	}while(0)
Kojto	110:165afa46840b	1735
Kojto	110:165afa46840b	1736	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	1737	__HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto	110:165afa46840b	1738	}while(0)
Kojto	110:165afa46840b	1739
Kojto	110:165afa46840b	1740	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1741	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1742	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	1743	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1744	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	1745	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1746	} while(0)
Kojto	110:165afa46840b	1747	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	110:165afa46840b	1748
Kojto	90:cb3d968589d8	1749	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	1750	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1751	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1752	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	1753	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1754	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	1755	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1756	} while(0)
Kojto	99:dbbf35b96557	1757	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	90:cb3d968589d8	1758	#endif /* STM32F407xx \|\| STM32F417xx */
emilmont	77:869cf507173a	1759
Kojto	90:cb3d968589d8	1760	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	1761	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1762	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1763	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	1764	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1765	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	1766	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1767	} while(0)
Kojto	99:dbbf35b96557	1768	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1769	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1770	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	1771	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1772	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	1773	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1774	} while(0)
Kojto	99:dbbf35b96557	1775	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	99:dbbf35b96557	1776	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto	90:cb3d968589d8	1777	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	110:165afa46840b	1778	/**
Kojto	110:165afa46840b	1779	* @}
Kojto	110:165afa46840b	1780	*/
Kojto	110:165afa46840b	1781
Kojto	110:165afa46840b	1782	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1783	* @brief Enables or disables the AHB3 peripheral clock.
emilmont	77:869cf507173a	1784	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	1785	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	1786	* using it.
emilmont	77:869cf507173a	1787	*/
Kojto	99:dbbf35b96557	1788	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1789	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1790	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	99:dbbf35b96557	1791	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1792	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	99:dbbf35b96557	1793	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1794	} while(0)
Kojto	99:dbbf35b96557	1795	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
Kojto	110:165afa46840b	1796	/**
Kojto	110:165afa46840b	1797	* @}
Kojto	110:165afa46840b	1798	*/
Kojto	110:165afa46840b	1799
Kojto	110:165afa46840b	1800	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1801	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
emilmont	77:869cf507173a	1802	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	1803	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	1804	* using it.
emilmont	77:869cf507173a	1805	*/
Kojto	99:dbbf35b96557	1806	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1807	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1808	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	1809	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1810	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	1811	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1812	} while(0)
Kojto	99:dbbf35b96557	1813	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1814	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1815	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	1816	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1817	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	1818	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1819	} while(0)
Kojto	99:dbbf35b96557	1820	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1821	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1822	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1823	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1824	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1825	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1826	} while(0)
Kojto	99:dbbf35b96557	1827	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1828	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1829	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1830	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1831	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1832	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1833	} while(0)
Kojto	99:dbbf35b96557	1834	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1835	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1836	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1837	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1838	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1839	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1840	} while(0)
Kojto	99:dbbf35b96557	1841	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1842	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1843	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1844	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1845	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1846	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1847	} while(0)
Kojto	99:dbbf35b96557	1848	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1849	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1850	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1851	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1852	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1853	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1854	} while(0)
Kojto	99:dbbf35b96557	1855	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1856	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1857	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1858	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1859	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1860	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1861	} while(0)
Kojto	99:dbbf35b96557	1862	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1863	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1864	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1865	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1866	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1867	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1868	} while(0)
Kojto	99:dbbf35b96557	1869	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1870	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1871	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1872	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1873	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1874	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1875	} while(0)
Kojto	99:dbbf35b96557	1876	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1877	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1878	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1879	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1880	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1881	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1882	} while(0)
Kojto	110:165afa46840b	1883	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1884	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1885	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	1886	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1887	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	1888	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1889	} while(0)
Kojto	110:165afa46840b	1890	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1891	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1892	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	1893	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1894	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	1895	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1896	} while(0)
Kojto	110:165afa46840b	1897	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1898	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1899	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	1900	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1901	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	1902	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1903	} while(0)
Kojto	110:165afa46840b	1904	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1905	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1906	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	1907	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1908	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	1909	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1910	} while(0)
Kojto	110:165afa46840b	1911	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1912	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1913	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	1914	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1915	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	1916	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1917	} while(0)
Kojto	110:165afa46840b	1918	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	1919	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	1920	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	1921	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	1922	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	99:dbbf35b96557	1923	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	1924	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	1925	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	1926	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	1927	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	1928	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	1929	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	1930	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	1931	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	1932	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	1933	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	110:165afa46840b	1934	/**
Kojto	110:165afa46840b	1935	* @}
Kojto	110:165afa46840b	1936	*/
Kojto	110:165afa46840b	1937
Kojto	110:165afa46840b	1938	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1939	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
emilmont	77:869cf507173a	1940	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	1941	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	1942	* using it.
emilmont	77:869cf507173a	1943	*/
Kojto	99:dbbf35b96557	1944	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1945	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1946	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1947	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1948	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1949	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1950	} while(0)
Kojto	99:dbbf35b96557	1951	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1952	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1953	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1954	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1955	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1956	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1957	} while(0)
Kojto	99:dbbf35b96557	1958	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1959	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	1960	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1961	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1962	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1963	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1964	} while(0)
Kojto	110:165afa46840b	1965	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1966	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1967	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	1968	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1969	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	1970	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1971	} while(0)
Kojto	110:165afa46840b	1972	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1973	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1974	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	1975	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1976	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	1977	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1978	} while(0)
Kojto	110:165afa46840b	1979	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	110:165afa46840b	1980	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	1981	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	1982	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1983	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	1984	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1985	} while(0)
Kojto	110:165afa46840b	1986
Kojto	110:165afa46840b	1987	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	1988	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	1989	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	1990	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	110:165afa46840b	1991	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	110:165afa46840b	1992	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	110:165afa46840b	1993	/**
Kojto	110:165afa46840b	1994	* @}
Kojto	110:165afa46840b	1995	*/
Kojto	110:165afa46840b	1996
Kojto	110:165afa46840b	1997	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	1998	* @brief Force or release AHB1 peripheral reset.
Kojto	110:165afa46840b	1999	*/
Kojto	110:165afa46840b	2000	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	2001	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	2002	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	2003	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	2004	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	2005	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	2006	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	2007	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2008
Kojto	110:165afa46840b	2009	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	2010	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	2011	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	2012	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	2013	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	2014	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	2015	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	2016	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2017	/**
Kojto	110:165afa46840b	2018	* @}
Kojto	110:165afa46840b	2019	*/
Kojto	110:165afa46840b	2020
Kojto	110:165afa46840b	2021	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	2022	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	2023	*/
Kojto	110:165afa46840b	2024	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	2025	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto	110:165afa46840b	2026
Kojto	90:cb3d968589d8	2027	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2028	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	99:dbbf35b96557	2029	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	90:cb3d968589d8	2030	#endif /* STM32F407xx \|\| STM32F417xx */
emilmont	77:869cf507173a	2031
Kojto	90:cb3d968589d8	2032	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2033	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	2034	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
emilmont	77:869cf507173a	2035
Kojto	99:dbbf35b96557	2036	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	2037	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto	90:cb3d968589d8	2038	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2039
Kojto	110:165afa46840b	2040	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	2041	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	2042
Kojto	110:165afa46840b	2043	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	110:165afa46840b	2044	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	110:165afa46840b	2045	/**
Kojto	110:165afa46840b	2046	* @}
Kojto	110:165afa46840b	2047	*/
Kojto	110:165afa46840b	2048
Kojto	110:165afa46840b	2049	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	2050	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	2051	* @{
Kojto	110:165afa46840b	2052	*/
Kojto	110:165afa46840b	2053	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	2054	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto	110:165afa46840b	2055
Kojto	99:dbbf35b96557	2056	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
Kojto	99:dbbf35b96557	2057	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
Kojto	110:165afa46840b	2058	/**
Kojto	110:165afa46840b	2059	* @}
Kojto	110:165afa46840b	2060	*/
Kojto	110:165afa46840b	2061
Kojto	110:165afa46840b	2062	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	2063	* @brief Force or release APB1 peripheral reset.
Kojto	90:cb3d968589d8	2064	*/
Kojto	99:dbbf35b96557	2065	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	2066	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	2067	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	2068	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	2069	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	2070	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	2071	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	2072	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	2073	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	2074	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	2075	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	2076	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	2077	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	2078	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	2079	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	2080	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	2081
Kojto	110:165afa46840b	2082	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	2083	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	2084	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	2085	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	2086	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	99:dbbf35b96557	2087	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	2088	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	2089	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	2090	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	2091	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	2092	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	2093	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	2094	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	2095	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	2096	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	2097	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	2098	/**
Kojto	110:165afa46840b	2099	* @}
Kojto	110:165afa46840b	2100	*/
Kojto	110:165afa46840b	2101
Kojto	110:165afa46840b	2102	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	2103	* @brief Force or release APB2 peripheral reset.
emilmont	77:869cf507173a	2104	*/
Kojto	99:dbbf35b96557	2105	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	2106	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	2107	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	2108	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	2109
Kojto	110:165afa46840b	2110	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	2111	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	2112	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	99:dbbf35b96557	2113	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	2114	/**
Kojto	110:165afa46840b	2115	* @}
Kojto	110:165afa46840b	2116	*/
Kojto	110:165afa46840b	2117
Kojto	110:165afa46840b	2118	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2119	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	2120	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	2121	* power consumption.
emilmont	77:869cf507173a	2122	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	2123	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	2124	*/
Kojto	110:165afa46840b	2125	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	2126	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	2127	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	2128	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	2129	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	2130	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	2131	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	2132	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	2133	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	2134	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	2135	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	2136	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	2137	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	2138	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	2139	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	2140	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	2141
Kojto	110:165afa46840b	2142	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	2143	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	2144	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	2145	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	2146	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	2147	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	2148	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	2149	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	2150	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	2151	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	2152	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	2153	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	2154	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	2155	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	2156	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	2157	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	2158	/**
Kojto	110:165afa46840b	2159	* @}
Kojto	110:165afa46840b	2160	*/
Kojto	110:165afa46840b	2161
Kojto	110:165afa46840b	2162	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2163	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	2164	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	2165	* power consumption.
Kojto	110:165afa46840b	2166	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	2167	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	2168	* @{
Kojto	110:165afa46840b	2169	*/
Kojto	110:165afa46840b	2170	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	2171	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	2172
Kojto	110:165afa46840b	2173	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	2174	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	2175
Kojto	90:cb3d968589d8	2176	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2177	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	2178	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	90:cb3d968589d8	2179	#endif /* STM32F407xx \|\| STM32F417xx */
emilmont	77:869cf507173a	2180
Kojto	90:cb3d968589d8	2181	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2182	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	2183	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
emilmont	77:869cf507173a	2184
Kojto	99:dbbf35b96557	2185	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	2186	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto	90:cb3d968589d8	2187	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2188	/**
Kojto	110:165afa46840b	2189	* @}
Kojto	110:165afa46840b	2190	*/
Kojto	110:165afa46840b	2191
Kojto	110:165afa46840b	2192	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2193	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	2194	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	2195	* power consumption.
emilmont	77:869cf507173a	2196	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	2197	* @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont	77:869cf507173a	2198	*/
Kojto	99:dbbf35b96557	2199	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
Kojto	99:dbbf35b96557	2200	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
Kojto	110:165afa46840b	2201	/**
Kojto	110:165afa46840b	2202	* @}
Kojto	110:165afa46840b	2203	*/
Kojto	110:165afa46840b	2204
Kojto	110:165afa46840b	2205	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2206	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	2207	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	2208	* power consumption.
emilmont	77:869cf507173a	2209	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	2210	* @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont	77:869cf507173a	2211	*/
Kojto	99:dbbf35b96557	2212	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	2213	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	2214	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	2215	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	2216	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	2217	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	2218	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	2219	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	2220	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	2221	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	2222	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	2223	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	2224	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	2225	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	2226	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	2227	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	2228
Kojto	110:165afa46840b	2229	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	2230	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	2231	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	2232	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	2233	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	99:dbbf35b96557	2234	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	2235	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	2236	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	2237	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	2238	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	2239	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	2240	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	2241	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	2242	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	2243	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	2244	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	2245	/**
Kojto	110:165afa46840b	2246	* @}
Kojto	110:165afa46840b	2247	*/
Kojto	110:165afa46840b	2248
Kojto	110:165afa46840b	2249	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2250	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	2251	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	2252	* power consumption.
Kojto	99:dbbf35b96557	2253	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	2254	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	99:dbbf35b96557	2255	*/
Kojto	99:dbbf35b96557	2256	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	2257	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	2258	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	110:165afa46840b	2259	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	2260	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	2261	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	2262
Kojto	110:165afa46840b	2263	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	2264	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	2265	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	99:dbbf35b96557	2266	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	2267	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	2268	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	110:165afa46840b	2269	/**
Kojto	110:165afa46840b	2270	* @}
Kojto	110:165afa46840b	2271	*/
Kojto	99:dbbf35b96557	2272	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2273	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	2274
Kojto	110:165afa46840b	2275	/------------------------- STM32F401xE/STM32F401xC --------------------------/
Kojto	110:165afa46840b	2276	#if defined(STM32F401xC) \|\| defined(STM32F401xE)
Kojto	110:165afa46840b	2277	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2278	* @brief Enable or disable the AHB1 peripheral clock.
Kojto	110:165afa46840b	2279	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2280	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2281	* using it.
Kojto	110:165afa46840b	2282	* @{
Kojto	110:165afa46840b	2283	*/
Kojto	110:165afa46840b	2284	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2285	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2286	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	2287	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2288	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	2289	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2290	} while(0)
Kojto	110:165afa46840b	2291	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2292	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2293	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	2294	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2295	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	2296	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2297	} while(0)
Kojto	110:165afa46840b	2298	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2299	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2300	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2301	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2302	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2303	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2304	} while(0)
Kojto	110:165afa46840b	2305	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2306	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2307	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	2308	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2309	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	2310	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2311	} while(0)
Kojto	110:165afa46840b	2312	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2313	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2314	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	2315	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2316	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	2317	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2318	} while(0)
Kojto	110:165afa46840b	2319
Kojto	110:165afa46840b	2320	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	2321	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	110:165afa46840b	2322	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	2323	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	2324	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	2325	/**
Kojto	110:165afa46840b	2326	* @}
Kojto	110:165afa46840b	2327	*/
Kojto	110:165afa46840b	2328
Kojto	110:165afa46840b	2329	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2330	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	110:165afa46840b	2331	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2332	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2333	* using it.
Kojto	110:165afa46840b	2334	* @{
Kojto	110:165afa46840b	2335	*/
Kojto	110:165afa46840b	2336	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	2337	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	110:165afa46840b	2338	}while(0)
Kojto	110:165afa46840b	2339
Kojto	110:165afa46840b	2340	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	2341	__HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto	110:165afa46840b	2342	}while(0)
Kojto	110:165afa46840b	2343	/**
Kojto	110:165afa46840b	2344	* @}
Kojto	110:165afa46840b	2345	*/
Kojto	110:165afa46840b	2346
Kojto	110:165afa46840b	2347	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2348	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	110:165afa46840b	2349	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2350	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2351	* using it.
Kojto	110:165afa46840b	2352	* @{
Kojto	110:165afa46840b	2353	*/
Kojto	110:165afa46840b	2354	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2355	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2356	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2357	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2358	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2359	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2360	} while(0)
Kojto	110:165afa46840b	2361	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2362	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2363	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	2364	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2365	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	2366	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2367	} while(0)
Kojto	110:165afa46840b	2368	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2369	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2370	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	2371	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2372	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	2373	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2374	} while(0)
Kojto	110:165afa46840b	2375	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2376	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2377	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	2378	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2379	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	2380	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2381	} while(0)
Kojto	110:165afa46840b	2382	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2383	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2384	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	2385	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2386	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	2387	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2388	} while(0)
Kojto	110:165afa46840b	2389	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	2390	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	2391	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	2392	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	2393	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	110:165afa46840b	2394	/**
Kojto	110:165afa46840b	2395	* @}
Kojto	110:165afa46840b	2396	*/
Kojto	110:165afa46840b	2397
Kojto	110:165afa46840b	2398	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2399	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	110:165afa46840b	2400	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2401	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2402	* using it.
Kojto	110:165afa46840b	2403	* @{
Kojto	110:165afa46840b	2404	*/
Kojto	110:165afa46840b	2405	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2406	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2407	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	2408	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2409	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	2410	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2411	} while(0)
Kojto	110:165afa46840b	2412	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2413	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2414	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	2415	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2416	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	2417	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2418	} while(0)
Kojto	110:165afa46840b	2419	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2420	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2421	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	2422	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2423	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	2424	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2425	} while(0)
Kojto	110:165afa46840b	2426
Kojto	110:165afa46840b	2427	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	2428	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	2429	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	2430	/**
Kojto	110:165afa46840b	2431	* @}
Kojto	110:165afa46840b	2432	*/
Kojto	110:165afa46840b	2433
Kojto	110:165afa46840b	2434	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	2435	* @brief Force or release AHB1 peripheral reset.
Kojto	110:165afa46840b	2436	* @{
Kojto	110:165afa46840b	2437	*/
Kojto	110:165afa46840b	2438	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	2439	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	2440	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	2441	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2442
Kojto	110:165afa46840b	2443	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
Kojto	110:165afa46840b	2444	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	2445	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	2446	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2447	/**
Kojto	110:165afa46840b	2448	* @}
Kojto	110:165afa46840b	2449	*/
Kojto	110:165afa46840b	2450
Kojto	110:165afa46840b	2451	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	2452	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	2453	* @{
Kojto	110:165afa46840b	2454	*/
Kojto	110:165afa46840b	2455	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	2456	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	2457
Kojto	110:165afa46840b	2458	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto	110:165afa46840b	2459	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	2460	/**
Kojto	110:165afa46840b	2461	* @}
Kojto	110:165afa46840b	2462	*/
Kojto	110:165afa46840b	2463
Kojto	110:165afa46840b	2464	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	2465	* @brief Force or release APB1 peripheral reset.
Kojto	110:165afa46840b	2466	* @{
Kojto	110:165afa46840b	2467	*/
Kojto	110:165afa46840b	2468	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	2469	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	2470	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	2471	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	2472	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	2473	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	2474
Kojto	110:165afa46840b	2475	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	110:165afa46840b	2476	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	2477	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	2478	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	2479	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	2480	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	2481	/**
Kojto	110:165afa46840b	2482	* @}
Kojto	110:165afa46840b	2483	*/
Kojto	110:165afa46840b	2484
Kojto	110:165afa46840b	2485	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	2486	* @brief Force or release APB2 peripheral reset.
Kojto	110:165afa46840b	2487	* @{
Kojto	110:165afa46840b	2488	*/
Kojto	110:165afa46840b	2489	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	2490	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	2491	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	2492	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	2493
Kojto	110:165afa46840b	2494	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	110:165afa46840b	2495	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	2496	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	2497	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	2498	/**
Kojto	110:165afa46840b	2499	* @}
Kojto	110:165afa46840b	2500	*/
Kojto	110:165afa46840b	2501
Kojto	110:165afa46840b	2502	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	2503	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	2504	* @{
Kojto	110:165afa46840b	2505	*/
Kojto	110:165afa46840b	2506	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	2507	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto	110:165afa46840b	2508	/**
Kojto	110:165afa46840b	2509	* @}
Kojto	110:165afa46840b	2510	*/
Kojto	110:165afa46840b	2511
Kojto	110:165afa46840b	2512	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2513	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	2514	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	2515	* power consumption.
Kojto	110:165afa46840b	2516	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	2517	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	2518	* @{
Kojto	110:165afa46840b	2519	*/
Kojto	110:165afa46840b	2520	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	2521	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	2522	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	2523	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	2524	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	2525	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	2526
Kojto	110:165afa46840b	2527	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	2528	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	2529	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	2530	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	2531	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	2532	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	2533	/**
Kojto	110:165afa46840b	2534	* @}
Kojto	110:165afa46840b	2535	*/
Kojto	110:165afa46840b	2536
Kojto	110:165afa46840b	2537	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2538	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	2539	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	2540	* power consumption.
Kojto	110:165afa46840b	2541	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	2542	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	2543	* @{
Kojto	110:165afa46840b	2544	*/
Kojto	110:165afa46840b	2545	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	2546
Kojto	110:165afa46840b	2547	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	2548	/**
Kojto	110:165afa46840b	2549	* @}
Kojto	110:165afa46840b	2550	*/
Kojto	110:165afa46840b	2551
Kojto	110:165afa46840b	2552	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2553	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	2554	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	2555	* power consumption.
Kojto	110:165afa46840b	2556	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	2557	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	2558	* @{
Kojto	110:165afa46840b	2559	*/
Kojto	110:165afa46840b	2560	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	2561	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	2562	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	2563	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	2564	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	2565
Kojto	110:165afa46840b	2566	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	2567	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	2568	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	2569	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	2570	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	2571	/**
Kojto	110:165afa46840b	2572	* @}
Kojto	110:165afa46840b	2573	*/
Kojto	110:165afa46840b	2574
Kojto	110:165afa46840b	2575	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2576	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	2577	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	2578	* power consumption.
Kojto	110:165afa46840b	2579	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	2580	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	2581	* @{
Kojto	110:165afa46840b	2582	*/
Kojto	110:165afa46840b	2583	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	2584	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	2585	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	2586
Kojto	110:165afa46840b	2587	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	2588	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	2589	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	2590	/**
Kojto	110:165afa46840b	2591	* @}
Kojto	110:165afa46840b	2592	*/
Kojto	110:165afa46840b	2593	#endif /* STM32F401xC \|\| STM32F401xE*/
Kojto	110:165afa46840b	2594	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	2595
Kojto	110:165afa46840b	2596	/-------------------------------- STM32F410xx -------------------------------/
Kojto	110:165afa46840b	2597	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	2598	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2599	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	110:165afa46840b	2600	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2601	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2602	* using it.
Kojto	110:165afa46840b	2603	*/
Kojto	110:165afa46840b	2604	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2605	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2606	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2607	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2608	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2609	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2610	} while(0)
Kojto	110:165afa46840b	2611	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2612	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2613	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
Kojto	110:165afa46840b	2614	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2615	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
Kojto	110:165afa46840b	2616	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2617	} while(0)
Kojto	110:165afa46840b	2618	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	2619	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
Kojto	110:165afa46840b	2620	/**
Kojto	110:165afa46840b	2621	* @}
Kojto	110:165afa46840b	2622	*/
Kojto	110:165afa46840b	2623
Kojto	110:165afa46840b	2624	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2625	* @brief Enable or disable the High Speed APB (APB1) peripheral clock.
Kojto	110:165afa46840b	2626	*/
Kojto	110:165afa46840b	2627	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2628	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2629	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	110:165afa46840b	2630	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2631	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	110:165afa46840b	2632	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2633	} while(0)
Kojto	110:165afa46840b	2634	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2635	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2636	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto	110:165afa46840b	2637	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2638	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto	110:165afa46840b	2639	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2640	} while(0)
Kojto	110:165afa46840b	2641	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2642	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2643	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	110:165afa46840b	2644	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2645	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	110:165afa46840b	2646	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2647	} while(0)
Kojto	110:165afa46840b	2648	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2649	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2650	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	110:165afa46840b	2651	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2652	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	110:165afa46840b	2653	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2654	} while(0)
Kojto	110:165afa46840b	2655	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2656	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2657	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	110:165afa46840b	2658	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2659	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	110:165afa46840b	2660	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2661	} while(0)
Kojto	110:165afa46840b	2662
Kojto	110:165afa46840b	2663	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	110:165afa46840b	2664	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
Kojto	110:165afa46840b	2665	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
Kojto	110:165afa46840b	2666	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	110:165afa46840b	2667	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	110:165afa46840b	2668	/**
Kojto	110:165afa46840b	2669	* @}
Kojto	110:165afa46840b	2670	*/
Kojto	110:165afa46840b	2671
Kojto	110:165afa46840b	2672	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2673	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	99:dbbf35b96557	2674	*/
Kojto	99:dbbf35b96557	2675	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	2676	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	2677	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	2678	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2679	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	2680	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2681	} while(0)
Kojto	110:165afa46840b	2682	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2683	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2684	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
Kojto	110:165afa46840b	2685	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2686	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
Kojto	110:165afa46840b	2687	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2688	} while(0)
Kojto	110:165afa46840b	2689	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	110:165afa46840b	2690	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
Kojto	110:165afa46840b	2691	/**
Kojto	110:165afa46840b	2692	* @}
Kojto	110:165afa46840b	2693	*/
Kojto	110:165afa46840b	2694
Kojto	110:165afa46840b	2695	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	2696	* @brief Force or release AHB1 peripheral reset.
Kojto	110:165afa46840b	2697	*/
Kojto	110:165afa46840b	2698	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2699	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_RNGRST))
Kojto	110:165afa46840b	2700	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2701	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
Kojto	110:165afa46840b	2702	/**
Kojto	110:165afa46840b	2703	* @}
Kojto	110:165afa46840b	2704	*/
Kojto	110:165afa46840b	2705
Kojto	110:165afa46840b	2706	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	2707	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	2708	* @{
Kojto	110:165afa46840b	2709	*/
Kojto	110:165afa46840b	2710	#define __HAL_RCC_AHB2_FORCE_RESET()
Kojto	110:165afa46840b	2711	#define __HAL_RCC_AHB2_RELEASE_RESET()
Kojto	110:165afa46840b	2712	/**
Kojto	110:165afa46840b	2713	* @}
Kojto	110:165afa46840b	2714	*/
Kojto	110:165afa46840b	2715
Kojto	110:165afa46840b	2716	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	2717	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	2718	* @{
Kojto	99:dbbf35b96557	2719	*/
Kojto	110:165afa46840b	2720	#define __HAL_RCC_AHB3_FORCE_RESET()
Kojto	110:165afa46840b	2721	#define __HAL_RCC_AHB3_RELEASE_RESET()
Kojto	110:165afa46840b	2722	/**
Kojto	110:165afa46840b	2723	* @}
Kojto	110:165afa46840b	2724	*/
Kojto	110:165afa46840b	2725
Kojto	110:165afa46840b	2726	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	2727	* @brief Force or release APB1 peripheral reset.
Kojto	110:165afa46840b	2728	*/
Kojto	110:165afa46840b	2729	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	110:165afa46840b	2730	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
Kojto	110:165afa46840b	2731	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	110:165afa46840b	2732	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	2733
Kojto	110:165afa46840b	2734	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	110:165afa46840b	2735	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
Kojto	110:165afa46840b	2736	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto	110:165afa46840b	2737	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	2738	/**
Kojto	110:165afa46840b	2739	* @}
Kojto	110:165afa46840b	2740	*/
Kojto	110:165afa46840b	2741
Kojto	110:165afa46840b	2742	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	2743	* @brief Force or release APB2 peripheral reset.
Kojto	110:165afa46840b	2744	*/
Kojto	110:165afa46840b	2745	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	2746	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	2747	/**
Kojto	110:165afa46840b	2748	* @}
Kojto	110:165afa46840b	2749	*/
Kojto	110:165afa46840b	2750
Kojto	110:165afa46840b	2751	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2752	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	2753	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	2754	* power consumption.
Kojto	110:165afa46840b	2755	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	2756	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	2757	*/
Kojto	110:165afa46840b	2758	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_RNGLPEN))
Kojto	110:165afa46840b	2759	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	2760	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	2761	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	2762
Kojto	110:165afa46840b	2763	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
Kojto	110:165afa46840b	2764	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	2765	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	2766	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	2767	/**
Kojto	110:165afa46840b	2768	* @}
Kojto	110:165afa46840b	2769	*/
Kojto	110:165afa46840b	2770
Kojto	110:165afa46840b	2771	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2772	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	2773	*/
Kojto	110:165afa46840b	2774	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	110:165afa46840b	2775	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
Kojto	110:165afa46840b	2776	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
Kojto	110:165afa46840b	2777	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	110:165afa46840b	2778	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	2779
Kojto	110:165afa46840b	2780	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	110:165afa46840b	2781	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
Kojto	110:165afa46840b	2782	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
Kojto	110:165afa46840b	2783	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	110:165afa46840b	2784	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	2785	/**
Kojto	110:165afa46840b	2786	* @}
Kojto	110:165afa46840b	2787	*/
Kojto	110:165afa46840b	2788
Kojto	110:165afa46840b	2789	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2790	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	2791	*/
Kojto	110:165afa46840b	2792	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	2793	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
Kojto	110:165afa46840b	2794	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	2795	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
Kojto	110:165afa46840b	2796	/**
Kojto	110:165afa46840b	2797	* @}
Kojto	110:165afa46840b	2798	*/
Kojto	110:165afa46840b	2799
Kojto	110:165afa46840b	2800	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	2801	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	2802
Kojto	110:165afa46840b	2803	/-------------------------------- STM32F411xx -------------------------------/
Kojto	110:165afa46840b	2804	#if defined(STM32F411xE)
Kojto	110:165afa46840b	2805	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2806	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	110:165afa46840b	2807	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2808	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2809	* using it.
Kojto	110:165afa46840b	2810	*/
Kojto	110:165afa46840b	2811	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2812	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2813	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	2814	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2815	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	2816	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2817	} while(0)
Kojto	110:165afa46840b	2818	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2819	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2820	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	2821	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2822	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	2823	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2824	} while(0)
Kojto	110:165afa46840b	2825	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2826	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2827	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	2828	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2829	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	2830	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2831	} while(0)
Kojto	110:165afa46840b	2832	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2833	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2834	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	2835	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2836	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	2837	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2838	} while(0)
Kojto	110:165afa46840b	2839	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2840	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2841	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2842	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2843	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2844	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2845	} while(0)
Kojto	110:165afa46840b	2846	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	2847	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	110:165afa46840b	2848	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	2849	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	2850	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	2851	/**
Kojto	110:165afa46840b	2852	* @}
Kojto	110:165afa46840b	2853	*/
Kojto	110:165afa46840b	2854
Kojto	110:165afa46840b	2855	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2856	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	99:dbbf35b96557	2857	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	2858	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	2859	* using it.
Kojto	110:165afa46840b	2860	* @{
Kojto	110:165afa46840b	2861	*/
Kojto	110:165afa46840b	2862	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	2863	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	110:165afa46840b	2864	}while(0)
Kojto	110:165afa46840b	2865
Kojto	110:165afa46840b	2866	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	2867	__HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto	110:165afa46840b	2868	}while(0)
Kojto	110:165afa46840b	2869	/**
Kojto	110:165afa46840b	2870	* @}
Kojto	110:165afa46840b	2871	*/
Kojto	110:165afa46840b	2872
Kojto	110:165afa46840b	2873	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2874	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	110:165afa46840b	2875	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2876	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2877	* using it.
Kojto	110:165afa46840b	2878	*/
Kojto	110:165afa46840b	2879	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2880	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2881	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2882	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2883	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2884	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2885	} while(0)
Kojto	110:165afa46840b	2886	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2887	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2888	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	2889	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2890	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	2891	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2892	} while(0)
Kojto	110:165afa46840b	2893	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2894	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2895	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	2896	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2897	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	2898	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2899	} while(0)
Kojto	110:165afa46840b	2900	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2901	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2902	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	2903	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2904	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	2905	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2906	} while(0)
Kojto	110:165afa46840b	2907	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2908	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2909	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	2910	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2911	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	2912	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2913	} while(0)
Kojto	110:165afa46840b	2914	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	2915	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	2916	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	2917	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	2918	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	110:165afa46840b	2919	/**
Kojto	110:165afa46840b	2920	* @}
Kojto	110:165afa46840b	2921	*/
Kojto	110:165afa46840b	2922	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2923	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	110:165afa46840b	2924	*/
Kojto	110:165afa46840b	2925	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2926	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2927	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	110:165afa46840b	2928	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2929	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	110:165afa46840b	2930	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2931	} while(0)
Kojto	110:165afa46840b	2932	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2933	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2934	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	2935	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2936	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	2937	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2938	} while(0)
Kojto	110:165afa46840b	2939	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2940	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2941	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	2942	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2943	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	2944	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2945	} while(0)
Kojto	110:165afa46840b	2946	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	110:165afa46840b	2947	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	2948	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	2949	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2950	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	2951	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2952	} while(0)
Kojto	110:165afa46840b	2953	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	2954	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	2955	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	2956	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	110:165afa46840b	2957	/**
Kojto	110:165afa46840b	2958	* @}
Kojto	110:165afa46840b	2959	*/
Kojto	110:165afa46840b	2960
Kojto	110:165afa46840b	2961	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	2962	* @brief Force or release AHB1 peripheral reset.
Kojto	110:165afa46840b	2963	*/
Kojto	110:165afa46840b	2964	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	2965	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	2966	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2967
Kojto	110:165afa46840b	2968	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	2969	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	2970	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2971	/**
Kojto	110:165afa46840b	2972	* @}
Kojto	110:165afa46840b	2973	*/
Kojto	110:165afa46840b	2974
Kojto	110:165afa46840b	2975	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	2976	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	2977	* @{
Kojto	110:165afa46840b	2978	*/
Kojto	110:165afa46840b	2979	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	2980	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	2981
Kojto	110:165afa46840b	2982	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto	110:165afa46840b	2983	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	2984	/**
Kojto	110:165afa46840b	2985	* @}
Kojto	110:165afa46840b	2986	*/
Kojto	110:165afa46840b	2987
Kojto	110:165afa46840b	2988	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	2989	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	2990	* @{
Kojto	110:165afa46840b	2991	*/
Kojto	110:165afa46840b	2992	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	2993	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto	110:165afa46840b	2994	/**
Kojto	110:165afa46840b	2995	* @}
Kojto	110:165afa46840b	2996	*/
Kojto	110:165afa46840b	2997
Kojto	110:165afa46840b	2998	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	2999	* @brief Force or release APB1 peripheral reset.
Kojto	110:165afa46840b	3000	*/
Kojto	110:165afa46840b	3001	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3002	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3003	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3004	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3005	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	3006
Kojto	110:165afa46840b	3007	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3008	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3009	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3010	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3011	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	3012	/**
Kojto	110:165afa46840b	3013	* @}
Kojto	110:165afa46840b	3014	*/
Kojto	110:165afa46840b	3015
Kojto	110:165afa46840b	3016	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	3017	* @brief Force or release APB2 peripheral reset.
Kojto	110:165afa46840b	3018	*/
Kojto	110:165afa46840b	3019	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	3020	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3021	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3022	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3023
Kojto	110:165afa46840b	3024	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3025	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3026	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3027	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	3028	/**
Kojto	110:165afa46840b	3029	* @}
Kojto	110:165afa46840b	3030	*/
Kojto	110:165afa46840b	3031
Kojto	110:165afa46840b	3032	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3033	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3034	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3035	* power consumption.
Kojto	110:165afa46840b	3036	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3037	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3038	*/
Kojto	110:165afa46840b	3039	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3040	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	3041	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3042	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3043	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3044
Kojto	110:165afa46840b	3045	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3046	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	3047	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3048	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3049	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3050	/**
Kojto	110:165afa46840b	3051	* @}
Kojto	110:165afa46840b	3052	*/
Kojto	110:165afa46840b	3053
Kojto	110:165afa46840b	3054	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3055	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3056	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3057	* power consumption.
Kojto	110:165afa46840b	3058	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3059	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3060	* @{
Kojto	110:165afa46840b	3061	*/
Kojto	110:165afa46840b	3062	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3063	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3064	/**
Kojto	110:165afa46840b	3065	* @}
Kojto	110:165afa46840b	3066	*/
Kojto	110:165afa46840b	3067
Kojto	110:165afa46840b	3068	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3069	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3070	*/
Kojto	110:165afa46840b	3071	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3072	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3073	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3074	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3075	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	3076
Kojto	110:165afa46840b	3077	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3078	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3079	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3080	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3081	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	3082	/**
Kojto	110:165afa46840b	3083	* @}
Kojto	110:165afa46840b	3084	*/
Kojto	110:165afa46840b	3085
Kojto	110:165afa46840b	3086	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3087	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3088	*/
Kojto	110:165afa46840b	3089	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	3090	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3091	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3092	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	3093
Kojto	110:165afa46840b	3094	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3095	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3096	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	3097	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	3098	/**
Kojto	110:165afa46840b	3099	* @}
Kojto	110:165afa46840b	3100	*/
Kojto	110:165afa46840b	3101	#endif /* STM32F411xE */
Kojto	110:165afa46840b	3102	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	3103
Kojto	110:165afa46840b	3104	/---------------------------------- STM32F446xx -----------------------------/
Kojto	110:165afa46840b	3105	#if defined(STM32F446xx)
Kojto	110:165afa46840b	3106	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3107	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	110:165afa46840b	3108	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	3109	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	3110	* using it.
Kojto	110:165afa46840b	3111	*/
Kojto	110:165afa46840b	3112	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3113	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3114	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	3115	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3116	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	3117	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3118	} while(0)
Kojto	110:165afa46840b	3119	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3120	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3121	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	3122	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3123	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	3124	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3125	} while(0)
Kojto	110:165afa46840b	3126	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3127	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3128	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3129	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3130	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3131	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3132	} while(0)
Kojto	110:165afa46840b	3133	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3134	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3135	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	3136	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3137	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	3138	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3139	} while(0)
Kojto	110:165afa46840b	3140	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3141	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3142	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	3143	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3144	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	3145	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3146	} while(0)
Kojto	99:dbbf35b96557	3147	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3148	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3149	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	3150	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3151	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	3152	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3153	} while(0)
Kojto	99:dbbf35b96557	3154	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3155	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3156	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	3157	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3158	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	3159	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3160	} while(0)
Kojto	99:dbbf35b96557	3161	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3162	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3163	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	3164	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3165	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	3166	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3167	} while(0)
Kojto	99:dbbf35b96557	3168	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3169	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3170	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	3171	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3172	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	3173	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3174	} while(0)
Kojto	110:165afa46840b	3175	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	3176	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	99:dbbf35b96557	3177	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	3178	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	3179	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	3180	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	110:165afa46840b	3181	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	3182	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	3183	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	3184	/**
Kojto	110:165afa46840b	3185	* @}
Kojto	110:165afa46840b	3186	*/
Kojto	110:165afa46840b	3187
Kojto	110:165afa46840b	3188	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3189	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	99:dbbf35b96557	3190	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	3191	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	3192	* using it.
Kojto	99:dbbf35b96557	3193	*/
Kojto	99:dbbf35b96557	3194	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3195	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3196	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	3197	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3198	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	3199	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3200	} while(0)
Kojto	99:dbbf35b96557	3201	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	110:165afa46840b	3202	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	3203	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	110:165afa46840b	3204	}while(0)
Kojto	110:165afa46840b	3205
Kojto	110:165afa46840b	3206	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	3207	__HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto	110:165afa46840b	3208	}while(0)
Kojto	110:165afa46840b	3209
Kojto	110:165afa46840b	3210	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3211	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3212	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	3213	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3214	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	3215	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3216	} while(0)
Kojto	110:165afa46840b	3217	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	110:165afa46840b	3218	/**
Kojto	110:165afa46840b	3219	* @}
Kojto	110:165afa46840b	3220	*/
Kojto	110:165afa46840b	3221
Kojto	110:165afa46840b	3222	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3223	* @brief Enables or disables the AHB3 peripheral clock.
Kojto	99:dbbf35b96557	3224	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	3225	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	3226	* using it.
Kojto	99:dbbf35b96557	3227	*/
Kojto	99:dbbf35b96557	3228	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3229	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3230	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	3231	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3232	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	3233	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3234	} while(0)
Kojto	99:dbbf35b96557	3235	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3236	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3237	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	99:dbbf35b96557	3238	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3239	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	99:dbbf35b96557	3240	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3241	} while(0)
Kojto	99:dbbf35b96557	3242
Kojto	99:dbbf35b96557	3243	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	99:dbbf35b96557	3244	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	110:165afa46840b	3245	/**
Kojto	110:165afa46840b	3246	* @}
Kojto	110:165afa46840b	3247	*/
Kojto	110:165afa46840b	3248
Kojto	110:165afa46840b	3249	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3250	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	99:dbbf35b96557	3251	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	3252	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	3253	* using it.
Kojto	99:dbbf35b96557	3254	*/
Kojto	99:dbbf35b96557	3255	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3256	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3257	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	3258	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3259	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	3260	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3261	} while(0)
Kojto	99:dbbf35b96557	3262	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3263	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3264	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	3265	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3266	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	3267	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3268	} while(0)
Kojto	99:dbbf35b96557	3269	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3270	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3271	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	3272	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3273	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	3274	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3275	} while(0)
Kojto	99:dbbf35b96557	3276	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3277	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3278	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	3279	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3280	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	3281	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3282	} while(0)
Kojto	99:dbbf35b96557	3283	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3284	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3285	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	3286	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3287	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	3288	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3289	} while(0)
Kojto	99:dbbf35b96557	3290	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3291	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3292	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	99:dbbf35b96557	3293	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3294	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	99:dbbf35b96557	3295	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3296	} while(0)
Kojto	99:dbbf35b96557	3297	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3298	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3299	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	3300	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3301	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	3302	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3303	} while(0)
Kojto	99:dbbf35b96557	3304	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3305	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3306	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	3307	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3308	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	3309	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3310	} while(0)
Kojto	99:dbbf35b96557	3311	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3312	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3313	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	3314	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3315	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	3316	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3317	} while(0)
Kojto	99:dbbf35b96557	3318	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3319	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3320	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	99:dbbf35b96557	3321	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3322	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	99:dbbf35b96557	3323	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3324	} while(0)
Kojto	99:dbbf35b96557	3325	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3326	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3327	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	3328	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3329	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	3330	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3331	} while(0)
Kojto	99:dbbf35b96557	3332	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3333	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3334	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	3335	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3336	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	3337	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3338	} while(0)
Kojto	99:dbbf35b96557	3339	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3340	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3341	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	99:dbbf35b96557	3342	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3343	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	99:dbbf35b96557	3344	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3345	} while(0)
Kojto	99:dbbf35b96557	3346	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3347	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3348	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	3349	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3350	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	3351	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3352	} while(0)
Kojto	110:165afa46840b	3353	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3354	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3355	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	3356	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3357	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	3358	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3359	} while(0)
Kojto	110:165afa46840b	3360	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3361	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3362	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	3363	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3364	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	3365	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3366	} while(0)
Kojto	110:165afa46840b	3367	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3368	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3369	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	3370	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3371	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	3372	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3373	} while(0)
Kojto	110:165afa46840b	3374	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3375	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3376	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	3377	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3378	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	3379	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3380	} while(0)
Kojto	110:165afa46840b	3381	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3382	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3383	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	3384	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3385	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	3386	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3387	} while(0)
Kojto	110:165afa46840b	3388	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	3389	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	3390	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	3391	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	3392	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	99:dbbf35b96557	3393	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	3394	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	3395	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	3396	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	3397	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	3398	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
Kojto	99:dbbf35b96557	3399	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	3400	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	3401	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	3402	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	99:dbbf35b96557	3403	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	3404	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	3405	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto	99:dbbf35b96557	3406	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	110:165afa46840b	3407	/**
Kojto	110:165afa46840b	3408	* @}
Kojto	110:165afa46840b	3409	*/
Kojto	110:165afa46840b	3410
Kojto	110:165afa46840b	3411	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3412	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	99:dbbf35b96557	3413	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	3414	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	3415	* using it.
Kojto	99:dbbf35b96557	3416	*/
Kojto	99:dbbf35b96557	3417	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3418	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3419	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	3420	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3421	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	3422	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3423	} while(0)
Kojto	99:dbbf35b96557	3424	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3425	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3426	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	3427	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3428	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	3429	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3430	} while(0)
Kojto	99:dbbf35b96557	3431	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3432	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3433	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	3434	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3435	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	3436	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3437	} while(0)
Kojto	99:dbbf35b96557	3438	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3439	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3440	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	3441	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3442	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	3443	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3444	} while(0)
Kojto	99:dbbf35b96557	3445	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	3446	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	3447	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	99:dbbf35b96557	3448	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3449	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	99:dbbf35b96557	3450	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3451	} while(0)
Kojto	110:165afa46840b	3452	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3453	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3454	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	3455	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3456	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	3457	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3458	} while(0)
Kojto	110:165afa46840b	3459	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3460	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3461	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	3462	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3463	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	3464	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3465	} while(0)
Kojto	110:165afa46840b	3466	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	110:165afa46840b	3467	__IO uint32_t tmpreg; \
Kojto	110:165afa46840b	3468	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	3469	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3470	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	3471	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3472	} while(0)
Kojto	110:165afa46840b	3473	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	3474	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	3475	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	3476	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	110:165afa46840b	3477	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	110:165afa46840b	3478	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	110:165afa46840b	3479	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	110:165afa46840b	3480	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
Kojto	110:165afa46840b	3481	/**
Kojto	110:165afa46840b	3482	* @}
Kojto	110:165afa46840b	3483	*/
Kojto	110:165afa46840b	3484
Kojto	110:165afa46840b	3485	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	3486	* @brief Force or release AHB1 peripheral reset.
Kojto	110:165afa46840b	3487	*/
Kojto	110:165afa46840b	3488	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	3489	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	3490	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	3491	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	3492	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	3493	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3494
Kojto	110:165afa46840b	3495	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	3496	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	3497	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	3498	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	3499	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	3500	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3501	/**
Kojto	110:165afa46840b	3502	* @}
Kojto	110:165afa46840b	3503	*/
Kojto	110:165afa46840b	3504
Kojto	110:165afa46840b	3505	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	3506	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	3507	* @{
Kojto	110:165afa46840b	3508	*/
Kojto	110:165afa46840b	3509	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	3510	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	3511	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	3512	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	110:165afa46840b	3513
Kojto	110:165afa46840b	3514	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto	110:165afa46840b	3515	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	3516	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	3517	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	110:165afa46840b	3518	/**
Kojto	110:165afa46840b	3519	* @}
Kojto	110:165afa46840b	3520	*/
Kojto	110:165afa46840b	3521
Kojto	110:165afa46840b	3522	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	3523	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	3524	* @{
Kojto	99:dbbf35b96557	3525	*/
Kojto	110:165afa46840b	3526	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto	110:165afa46840b	3527	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto	110:165afa46840b	3528
Kojto	99:dbbf35b96557	3529	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	3530	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	99:dbbf35b96557	3531
Kojto	99:dbbf35b96557	3532	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	3533	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	110:165afa46840b	3534	/**
Kojto	110:165afa46840b	3535	* @}
Kojto	110:165afa46840b	3536	*/
Kojto	110:165afa46840b	3537
Kojto	110:165afa46840b	3538	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	3539	* @brief Force or release APB1 peripheral reset.
Kojto	99:dbbf35b96557	3540	*/
Kojto	99:dbbf35b96557	3541	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	3542	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	3543	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	3544	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	3545	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	110:165afa46840b	3546	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
Kojto	99:dbbf35b96557	3547	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	3548	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	3549	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	3550	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	99:dbbf35b96557	3551	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	3552	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	3553	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
Kojto	99:dbbf35b96557	3554	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	3555	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3556	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3557	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3558	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3559	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	3560
Kojto	110:165afa46840b	3561	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3562	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3563	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3564	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3565	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	99:dbbf35b96557	3566	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	3567	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	3568	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	3569	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	3570	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	3571	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
Kojto	99:dbbf35b96557	3572	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	3573	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	3574	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	3575	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto	99:dbbf35b96557	3576	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	3577	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	3578	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto	99:dbbf35b96557	3579	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	3580	/**
Kojto	110:165afa46840b	3581	* @}
Kojto	110:165afa46840b	3582	*/
Kojto	110:165afa46840b	3583
Kojto	110:165afa46840b	3584	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	3585	* @brief Force or release APB2 peripheral reset.
Kojto	110:165afa46840b	3586	*/
Kojto	110:165afa46840b	3587	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	3588	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	110:165afa46840b	3589	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
Kojto	110:165afa46840b	3590	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3591	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3592	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3593
Kojto	110:165afa46840b	3594	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3595	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3596	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3597	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	3598	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto	110:165afa46840b	3599	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
Kojto	110:165afa46840b	3600	/**
Kojto	110:165afa46840b	3601	* @}
Kojto	110:165afa46840b	3602	*/
Kojto	110:165afa46840b	3603
Kojto	110:165afa46840b	3604	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3605	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	3606	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	3607	* power consumption.
Kojto	99:dbbf35b96557	3608	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	3609	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3610	*/
Kojto	110:165afa46840b	3611	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3612	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	3613	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	3614	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	3615	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	3616	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	3617	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	3618	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3619	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3620	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3621	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	3622
Kojto	110:165afa46840b	3623	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3624	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	3625	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	3626	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	3627	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	3628	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	3629	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	3630	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3631	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3632	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3633	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	3634	/**
Kojto	110:165afa46840b	3635	* @}
Kojto	110:165afa46840b	3636	*/
Kojto	110:165afa46840b	3637
Kojto	110:165afa46840b	3638	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3639	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	3640	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	3641	* power consumption.
Kojto	110:165afa46840b	3642	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	3643	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3644	* @{
Kojto	110:165afa46840b	3645	*/
Kojto	110:165afa46840b	3646	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3647	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3648
Kojto	110:165afa46840b	3649	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	3650	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	3651
Kojto	99:dbbf35b96557	3652	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	3653	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	110:165afa46840b	3654	/**
Kojto	110:165afa46840b	3655	* @}
Kojto	110:165afa46840b	3656	*/
Kojto	110:165afa46840b	3657
Kojto	110:165afa46840b	3658	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3659	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	3660	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	3661	* power consumption.
Kojto	99:dbbf35b96557	3662	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	3663	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	99:dbbf35b96557	3664	*/
Kojto	99:dbbf35b96557	3665	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	3666	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	99:dbbf35b96557	3667
Kojto	99:dbbf35b96557	3668	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	3669	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	110:165afa46840b	3670	/**
Kojto	110:165afa46840b	3671	* @}
Kojto	110:165afa46840b	3672	*/
Kojto	110:165afa46840b	3673
Kojto	110:165afa46840b	3674	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3675	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	3676	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	3677	* power consumption.
Kojto	99:dbbf35b96557	3678	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	3679	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	99:dbbf35b96557	3680	*/
Kojto	99:dbbf35b96557	3681	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	3682	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	3683	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	3684	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	3685	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	110:165afa46840b	3686	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	99:dbbf35b96557	3687	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	3688	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	3689	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	3690	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	99:dbbf35b96557	3691	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	3692	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	3693	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
Kojto	99:dbbf35b96557	3694	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	3695	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3696	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3697	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3698	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3699	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	3700
Kojto	110:165afa46840b	3701	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3702	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3703	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3704	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3705	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	99:dbbf35b96557	3706	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	3707	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	3708	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	3709	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	3710	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	110:165afa46840b	3711	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	99:dbbf35b96557	3712	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	3713	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	3714	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	110:165afa46840b	3715	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	99:dbbf35b96557	3716	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	3717	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	3718	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
Kojto	99:dbbf35b96557	3719	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	3720	/**
Kojto	110:165afa46840b	3721	* @}
Kojto	110:165afa46840b	3722	*/
Kojto	110:165afa46840b	3723
Kojto	110:165afa46840b	3724	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3725	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	3726	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	3727	* power consumption.
emilmont	77:869cf507173a	3728	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	3729	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	3730	*/
Kojto	99:dbbf35b96557	3731	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	3732	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	3733	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	3734	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	99:dbbf35b96557	3735	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
Kojto	110:165afa46840b	3736	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3737	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3738	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	3739
Kojto	110:165afa46840b	3740	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3741	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3742	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	99:dbbf35b96557	3743	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	3744	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	3745	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	3746	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto	99:dbbf35b96557	3747	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
Kojto	110:165afa46840b	3748	/**
Kojto	110:165afa46840b	3749	* @}
Kojto	110:165afa46840b	3750	*/
Kojto	99:dbbf35b96557	3751
Kojto	99:dbbf35b96557	3752	#endif /* STM32F446xx */
Kojto	110:165afa46840b	3753	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	3754	/------------------------------- PLL Configuration --------------------------/
Kojto	110:165afa46840b	3755	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
Kojto	110:165afa46840b	3756	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	3757	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	99:dbbf35b96557	3758	* @note This function must be used only when the main PLL is disabled.
Kojto	99:dbbf35b96557	3759	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	99:dbbf35b96557	3760	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	3761	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	3762	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	3763	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	99:dbbf35b96557	3764	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	99:dbbf35b96557	3765	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	3766	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	3767	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	3768	* of 2 MHz to limit PLL jitter.
Kojto	99:dbbf35b96557	3769	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	99:dbbf35b96557	3770	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	3771	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	3772	* output frequency is between 192 and 432 MHz.
Kojto	99:dbbf35b96557	3773	*
Kojto	99:dbbf35b96557	3774	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	99:dbbf35b96557	3775	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	3776	*
Kojto	99:dbbf35b96557	3777	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	110:165afa46840b	3778	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	3779	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	99:dbbf35b96557	3780	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	99:dbbf35b96557	3781	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	99:dbbf35b96557	3782	* correctly.
Kojto	99:dbbf35b96557	3783	*
Kojto	99:dbbf35b96557	3784	* @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	99:dbbf35b96557	3785	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	110:165afa46840b	3786	* @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx devices.
Kojto	99:dbbf35b96557	3787	*
Kojto	99:dbbf35b96557	3788	*/
Kojto	99:dbbf35b96557	3789	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
Kojto	99:dbbf35b96557	3790	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
Kojto	99:dbbf35b96557	3791	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
Kojto	99:dbbf35b96557	3792	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	99:dbbf35b96557	3793	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
Kojto	99:dbbf35b96557	3794	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
Kojto	99:dbbf35b96557	3795	#else
Kojto	99:dbbf35b96557	3796	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	99:dbbf35b96557	3797	* @note This function must be used only when the main PLL is disabled.
Kojto	99:dbbf35b96557	3798	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	99:dbbf35b96557	3799	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	3800	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	3801	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	3802	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	99:dbbf35b96557	3803	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	99:dbbf35b96557	3804	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	3805	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	3806	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	3807	* of 2 MHz to limit PLL jitter.
Kojto	99:dbbf35b96557	3808	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	99:dbbf35b96557	3809	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	3810	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	3811	* output frequency is between 192 and 432 MHz.
Kojto	99:dbbf35b96557	3812	*
Kojto	99:dbbf35b96557	3813	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	99:dbbf35b96557	3814	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	3815	*
Kojto	99:dbbf35b96557	3816	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	110:165afa46840b	3817	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	3818	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	99:dbbf35b96557	3819	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	99:dbbf35b96557	3820	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	99:dbbf35b96557	3821	* correctly.
Kojto	99:dbbf35b96557	3822	*
Kojto	99:dbbf35b96557	3823	*/
Kojto	99:dbbf35b96557	3824	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
Kojto	99:dbbf35b96557	3825	(RCC->PLLCFGR = (0x20000000 \| (__RCC_PLLSource__) \| (__PLLM__)\| \
Kojto	99:dbbf35b96557	3826	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
Kojto	99:dbbf35b96557	3827	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	99:dbbf35b96557	3828	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
Kojto	110:165afa46840b	3829	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	3830	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	3831
Kojto	110:165afa46840b	3832	/----------------------------PLLI2S Configuration ---------------------------/
Kojto	110:165afa46840b	3833	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	3834	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	3835	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	110:165afa46840b	3836	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	3837
Kojto	110:165afa46840b	3838	/** @brief Macros to enable or disable the PLLI2S.
Kojto	110:165afa46840b	3839	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
Kojto	110:165afa46840b	3840	*/
Kojto	110:165afa46840b	3841	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
Kojto	110:165afa46840b	3842	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
Kojto	110:165afa46840b	3843
Kojto	110:165afa46840b	3844	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	110:165afa46840b	3845	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	3846	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	3847	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	3848	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	3849	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	3850	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	3851	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	99:dbbf35b96557	3852	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	3853	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	3854	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	3855	* of 1 MHz to limit PLLI2S jitter.
Kojto	110:165afa46840b	3856	*
Kojto	99:dbbf35b96557	3857	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	99:dbbf35b96557	3858	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	3859	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	3860	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	3861	*
Kojto	99:dbbf35b96557	3862	* @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
Kojto	99:dbbf35b96557	3863	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	3864	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
Kojto	99:dbbf35b96557	3865	*
Kojto	99:dbbf35b96557	3866	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	3867	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	3868	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	3869	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	3870	*
Kojto	99:dbbf35b96557	3871	* @param __PLLI2SQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	3872	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	3873	*/
Kojto	110:165afa46840b	3874	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
Kojto	110:165afa46840b	3875	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	110:165afa46840b	3876	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	110:165afa46840b	3877	((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
Kojto	110:165afa46840b	3878	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
Kojto	110:165afa46840b	3879	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	3880	#else
Kojto	99:dbbf35b96557	3881	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	3882	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	3883	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	3884	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	3885	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	99:dbbf35b96557	3886	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	3887	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	3888	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	110:165afa46840b	3889	*
Kojto	99:dbbf35b96557	3890	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	3891	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	3892	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	3893	* on the I2S clock frequency.
Kojto	110:165afa46840b	3894	*
Kojto	110:165afa46840b	3895	*/
Kojto	110:165afa46840b	3896	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
Kojto	110:165afa46840b	3897	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	99:dbbf35b96557	3898	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	3899	#endif /* STM32F446xx */
emilmont	77:869cf507173a	3900
Kojto	90:cb3d968589d8	3901	#if defined(STM32F411xE)
Kojto	99:dbbf35b96557	3902	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	3903	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	3904	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	3905	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	3906	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	3907	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	99:dbbf35b96557	3908	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	110:165afa46840b	3909	* @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
Kojto	99:dbbf35b96557	3910	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	3911	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	3912	* of 2 MHz to limit PLLI2S jitter.
Kojto	99:dbbf35b96557	3913	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	99:dbbf35b96557	3914	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	3915	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	3916	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	3917	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	3918	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	3919	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	3920	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	3921	*/
Kojto	99:dbbf35b96557	3922	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	99:dbbf35b96557	3923	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	99:dbbf35b96557	3924	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	3925	#endif /* STM32F411xE */
Kojto	99:dbbf35b96557	3926
Kojto	110:165afa46840b	3927	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	3928	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
Kojto	99:dbbf35b96557	3929	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	3930	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	3931	* HAL_RCC_ClockConfig() API)
Kojto	99:dbbf35b96557	3932	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	99:dbbf35b96557	3933	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	3934	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	3935	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	3936	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
Kojto	99:dbbf35b96557	3937	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	3938	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
Kojto	110:165afa46840b	3939	* Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
Kojto	99:dbbf35b96557	3940	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	3941	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	3942	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	3943	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	3944	*/
Kojto	99:dbbf35b96557	3945	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) \|\
Kojto	99:dbbf35b96557	3946	((__PLLI2SQ__) << 24) \|\
Kojto	99:dbbf35b96557	3947	((__PLLI2SR__) << 28))
Kojto	110:165afa46840b	3948	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	3949	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	3950
Kojto	110:165afa46840b	3951	/------------------------------ PLLSAI Configuration ------------------------/
Kojto	110:165afa46840b	3952	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	3953	/** @brief Macros to Enable or Disable the PLLISAI.
Kojto	110:165afa46840b	3954	* @note The PLLSAI is only available with STM32F429x/439x Devices.
Kojto	99:dbbf35b96557	3955	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Kojto	99:dbbf35b96557	3956	*/
Kojto	99:dbbf35b96557	3957	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
Kojto	99:dbbf35b96557	3958	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
Kojto	99:dbbf35b96557	3959
Kojto	99:dbbf35b96557	3960	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	3961	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	99:dbbf35b96557	3962	*
Kojto	99:dbbf35b96557	3963	* @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
Kojto	99:dbbf35b96557	3964	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	3965	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	3966	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	3967	* of 1 MHz to limit PLLI2S jitter.
Kojto	99:dbbf35b96557	3968	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
Kojto	99:dbbf35b96557	3969	*
Kojto	99:dbbf35b96557	3970	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	99:dbbf35b96557	3971	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	3972	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	3973	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	3974	*
Kojto	99:dbbf35b96557	3975	* @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	3976	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	3977	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
Kojto	99:dbbf35b96557	3978	*
Kojto	99:dbbf35b96557	3979	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	3980	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	3981	*
Kojto	99:dbbf35b96557	3982	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	99:dbbf35b96557	3983	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	3984	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto	99:dbbf35b96557	3985	*/
Kojto	99:dbbf35b96557	3986	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	99:dbbf35b96557	3987	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
Kojto	99:dbbf35b96557	3988	((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
Kojto	99:dbbf35b96557	3989	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \| \
Kojto	99:dbbf35b96557	3990	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
Kojto	99:dbbf35b96557	3991	#endif /* STM32F446xx */
Kojto	110:165afa46840b	3992
Kojto	110:165afa46840b	3993	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	3994	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	110:165afa46840b	3995	*
Kojto	110:165afa46840b	3996	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	110:165afa46840b	3997	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	110:165afa46840b	3998	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	110:165afa46840b	3999	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	110:165afa46840b	4000	*
Kojto	110:165afa46840b	4001	* @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks.
Kojto	110:165afa46840b	4002	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	110:165afa46840b	4003	*
Kojto	110:165afa46840b	4004	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	110:165afa46840b	4005	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	4006	*
Kojto	110:165afa46840b	4007	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	110:165afa46840b	4008	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	110:165afa46840b	4009	*/
Kojto	110:165afa46840b	4010	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	110:165afa46840b	4011	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \|\
Kojto	110:165afa46840b	4012	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \|\
Kojto	110:165afa46840b	4013	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \|\
Kojto	110:165afa46840b	4014	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
Kojto	110:165afa46840b	4015	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	4016
Kojto	99:dbbf35b96557	4017	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	4018	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	99:dbbf35b96557	4019	*
Kojto	99:dbbf35b96557	4020	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	99:dbbf35b96557	4021	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	4022	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	4023	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	4024	*
Kojto	99:dbbf35b96557	4025	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	4026	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	4027	*
Kojto	99:dbbf35b96557	4028	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	99:dbbf35b96557	4029	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	4030	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto	90:cb3d968589d8	4031	*/
Kojto	99:dbbf35b96557	4032	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	99:dbbf35b96557	4033	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
Kojto	99:dbbf35b96557	4034	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \| \
Kojto	99:dbbf35b96557	4035	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
Kojto	99:dbbf35b96557	4036	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	4037
Kojto	110:165afa46840b	4038	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4039	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	4040
Kojto	110:165afa46840b	4041	/------------------- PLLSAI/PLLI2S Dividers Configuration -------------------/
Kojto	110:165afa46840b	4042	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
Kojto	110:165afa46840b	4043	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	4044	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
Kojto	110:165afa46840b	4045	* @note This function must be called before enabling the PLLI2S.
Kojto	110:165afa46840b	4046	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock.
Kojto	99:dbbf35b96557	4047	* This parameter must be a number between 1 and 32.
Kojto	99:dbbf35b96557	4048	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
Kojto	99:dbbf35b96557	4049	*/
Kojto	99:dbbf35b96557	4050	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Kojto	99:dbbf35b96557	4051
Kojto	99:dbbf35b96557	4052	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
Kojto	99:dbbf35b96557	4053	* @note This function must be called before enabling the PLLSAI.
Kojto	99:dbbf35b96557	4054	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
Kojto	99:dbbf35b96557	4055	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
Kojto	99:dbbf35b96557	4056	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
Kojto	99:dbbf35b96557	4057	*/
Kojto	99:dbbf35b96557	4058	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Kojto	110:165afa46840b	4059	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4060
Kojto	110:165afa46840b	4061	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	4062	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
Kojto	99:dbbf35b96557	4063	*
Kojto	110:165afa46840b	4064	* @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	99:dbbf35b96557	4065	* @note This function must be called before enabling the PLLSAI.
Kojto	99:dbbf35b96557	4066	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
Kojto	99:dbbf35b96557	4067	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
Kojto	99:dbbf35b96557	4068	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
Kojto	110:165afa46840b	4069	*/
Kojto	99:dbbf35b96557	4070	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
Kojto	110:165afa46840b	4071	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4072	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	4073
Kojto	110:165afa46840b	4074	/------------------------- Peripheral Clock selection -----------------------/
Kojto	99:dbbf35b96557	4075	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
Kojto	99:dbbf35b96557	4076	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	4077	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\|\
Kojto	110:165afa46840b	4078	defined(STM32F479xx)
Kojto	99:dbbf35b96557	4079	/** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto	99:dbbf35b96557	4080	* @note This function must be called before enabling the I2S APB clock.
Kojto	99:dbbf35b96557	4081	* @param __SOURCE__: specifies the I2S clock source.
Kojto	99:dbbf35b96557	4082	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	4083	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
Kojto	99:dbbf35b96557	4084	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	4085	* used as I2S clock source.
Kojto	90:cb3d968589d8	4086	*/
Kojto	99:dbbf35b96557	4087	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
Kojto	110:165afa46840b	4088	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	4089
Kojto	110:165afa46840b	4090	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	4091
Kojto	99:dbbf35b96557	4092	/** @brief Macro to configure SAI1BlockA clock source selection.
Kojto	110:165afa46840b	4093	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	99:dbbf35b96557	4094	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	4095	* the SAI clock.
Kojto	99:dbbf35b96557	4096	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	99:dbbf35b96557	4097	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	4098	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	99:dbbf35b96557	4099	* as SAI1 Block A clock.
Kojto	99:dbbf35b96557	4100	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	99:dbbf35b96557	4101	* as SAI1 Block A clock.
Kojto	99:dbbf35b96557	4102	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	4103	* used as SAI1 Block A clock.
Kojto	99:dbbf35b96557	4104	*/
Kojto	99:dbbf35b96557	4105	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	4106
Kojto	99:dbbf35b96557	4107	/** @brief Macro to configure SAI1BlockB clock source selection.
Kojto	110:165afa46840b	4108	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	99:dbbf35b96557	4109	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	4110	* the SAI clock.
Kojto	99:dbbf35b96557	4111	* @param __SOURCE__: specifies the SAI Block B clock source.
Kojto	99:dbbf35b96557	4112	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	4113	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	99:dbbf35b96557	4114	* as SAI1 Block B clock.
Kojto	99:dbbf35b96557	4115	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	99:dbbf35b96557	4116	* as SAI1 Block B clock.
Kojto	99:dbbf35b96557	4117	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	4118	* used as SAI1 Block B clock.
Kojto	99:dbbf35b96557	4119	*/
Kojto	99:dbbf35b96557	4120	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
Kojto	110:165afa46840b	4121	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	4122
Kojto	99:dbbf35b96557	4123	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	4124	/** @brief Macro to configure SAI1 clock source selection.
Kojto	110:165afa46840b	4125	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	4126	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	4127	* the SAI clock.
Kojto	99:dbbf35b96557	4128	* @param __SOURCE__: specifies the SAI1 clock source.
Kojto	99:dbbf35b96557	4129	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	4130	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	4131	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	4132	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	4133	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	4134	*/
Kojto	99:dbbf35b96557	4135	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	4136
Kojto	99:dbbf35b96557	4137	/** @brief Macro to Get SAI1 clock source selection.
Kojto	99:dbbf35b96557	4138	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	4139	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	4140	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	4141	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	4142	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	4143	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	4144	*/
Kojto	99:dbbf35b96557	4145	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
Kojto	99:dbbf35b96557	4146
Kojto	99:dbbf35b96557	4147	/** @brief Macro to configure SAI2 clock source selection.
Kojto	99:dbbf35b96557	4148	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	4149	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	4150	* the SAI clock.
Kojto	99:dbbf35b96557	4151	* @param __SOURCE__: specifies the SAI2 clock source.
Kojto	99:dbbf35b96557	4152	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	4153	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	4154	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	4155	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	99:dbbf35b96557	4156	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	99:dbbf35b96557	4157	*/
Kojto	99:dbbf35b96557	4158	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
Kojto	90:cb3d968589d8	4159
Kojto	99:dbbf35b96557	4160	/** @brief Macro to Get SAI2 clock source selection.
Kojto	99:dbbf35b96557	4161	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	4162	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	4163	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	4164	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	4165	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	99:dbbf35b96557	4166	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	99:dbbf35b96557	4167	*/
Kojto	99:dbbf35b96557	4168	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
Kojto	99:dbbf35b96557	4169
Kojto	99:dbbf35b96557	4170	/** @brief Macro to configure I2S APB1 clock source selection.
Kojto	99:dbbf35b96557	4171	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	99:dbbf35b96557	4172	* @param __SOURCE__: specifies the I2S APB1 clock source.
Kojto	99:dbbf35b96557	4173	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	4174	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	4175	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	4176	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	4177	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	4178	*/
Kojto	99:dbbf35b96557	4179	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	4180
Kojto	99:dbbf35b96557	4181	/** @brief Macro to Get I2S APB1 clock source selection.
Kojto	99:dbbf35b96557	4182	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	4183	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	4184	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	4185	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	4186	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	4187	*/
Kojto	99:dbbf35b96557	4188	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
Kojto	99:dbbf35b96557	4189
Kojto	99:dbbf35b96557	4190	/** @brief Macro to configure I2S APB2 clock source selection.
Kojto	99:dbbf35b96557	4191	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	99:dbbf35b96557	4192	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	99:dbbf35b96557	4193	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	4194	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	4195	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	4196	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	4197	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	4198	*/
Kojto	99:dbbf35b96557	4199	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	4200
Kojto	99:dbbf35b96557	4201	/** @brief Macro to Get I2S APB2 clock source selection.
Kojto	99:dbbf35b96557	4202	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	4203	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	4204	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	4205	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	4206	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	4207	*/
Kojto	99:dbbf35b96557	4208	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
Kojto	99:dbbf35b96557	4209
Kojto	99:dbbf35b96557	4210	/** @brief Macro to configure the CEC clock.
Kojto	99:dbbf35b96557	4211	* @param __SOURCE__: specifies the CEC clock source.
Kojto	99:dbbf35b96557	4212	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	4213	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	99:dbbf35b96557	4214	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	99:dbbf35b96557	4215	*/
Kojto	99:dbbf35b96557	4216	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
emilmont	77:869cf507173a	4217
Kojto	99:dbbf35b96557	4218	/** @brief Macro to Get the CEC clock.
Kojto	99:dbbf35b96557	4219	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	4220	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
Kojto	99:dbbf35b96557	4221	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	99:dbbf35b96557	4222	*/
Kojto	99:dbbf35b96557	4223	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
Kojto	110:165afa46840b	4224
Kojto	99:dbbf35b96557	4225	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	99:dbbf35b96557	4226	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	99:dbbf35b96557	4227	* This parameter can be one of the following values:
Kojto	110:165afa46840b	4228	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	110:165afa46840b	4229	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	4230	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	99:dbbf35b96557	4231	*/
Kojto	99:dbbf35b96557	4232	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	4233
Kojto	99:dbbf35b96557	4234	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	99:dbbf35b96557	4235	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	4236	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	110:165afa46840b	4237	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	4238	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	99:dbbf35b96557	4239	*/
Kojto	99:dbbf35b96557	4240	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	99:dbbf35b96557	4241
Kojto	99:dbbf35b96557	4242	/** @brief Macro to configure the CLK48 clock.
Kojto	99:dbbf35b96557	4243	* @param __SOURCE__: specifies the CK48 clock source.
Kojto	99:dbbf35b96557	4244	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	4245	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	99:dbbf35b96557	4246	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	99:dbbf35b96557	4247	*/
Kojto	99:dbbf35b96557	4248	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	4249
Kojto	99:dbbf35b96557	4250	/** @brief Macro to Get the CLK48 clock.
Kojto	99:dbbf35b96557	4251	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	4252	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	99:dbbf35b96557	4253	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	99:dbbf35b96557	4254	*/
Kojto	99:dbbf35b96557	4255	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
Kojto	99:dbbf35b96557	4256
Kojto	99:dbbf35b96557	4257	/** @brief Macro to configure the SDIO clock.
Kojto	99:dbbf35b96557	4258	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	99:dbbf35b96557	4259	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	4260	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	99:dbbf35b96557	4261	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	99:dbbf35b96557	4262	*/
Kojto	99:dbbf35b96557	4263	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	4264
Kojto	99:dbbf35b96557	4265	/** @brief Macro to Get the SDIO clock.
Kojto	99:dbbf35b96557	4266	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	4267	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	99:dbbf35b96557	4268	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	99:dbbf35b96557	4269	*/
Kojto	99:dbbf35b96557	4270	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
Kojto	99:dbbf35b96557	4271
Kojto	99:dbbf35b96557	4272	/** @brief Macro to configure the SPDIFRX clock.
Kojto	99:dbbf35b96557	4273	* @param __SOURCE__: specifies the SPDIFRX clock source.
Kojto	99:dbbf35b96557	4274	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	4275	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	99:dbbf35b96557	4276	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	99:dbbf35b96557	4277	*/
Kojto	99:dbbf35b96557	4278	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	4279
Kojto	99:dbbf35b96557	4280	/** @brief Macro to Get the SPDIFRX clock.
Kojto	99:dbbf35b96557	4281	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	4282	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	99:dbbf35b96557	4283	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	99:dbbf35b96557	4284	*/
Kojto	99:dbbf35b96557	4285	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
Kojto	99:dbbf35b96557	4286	#endif /* STM32F446xx */
Kojto	110:165afa46840b	4287
Kojto	110:165afa46840b	4288	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	4289
Kojto	110:165afa46840b	4290	/** @brief Macro to configure the CLK48 clock.
Kojto	110:165afa46840b	4291	* @param __SOURCE__: specifies the CK48 clock source.
Kojto	110:165afa46840b	4292	* This parameter can be one of the following values:
Kojto	110:165afa46840b	4293	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	110:165afa46840b	4294	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	110:165afa46840b	4295	*/
Kojto	110:165afa46840b	4296	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	4297
Kojto	110:165afa46840b	4298	/** @brief Macro to Get the CLK48 clock.
Kojto	110:165afa46840b	4299	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	4300	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	110:165afa46840b	4301	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	110:165afa46840b	4302	*/
Kojto	110:165afa46840b	4303	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
Kojto	110:165afa46840b	4304
Kojto	110:165afa46840b	4305	/** @brief Macro to configure the SDIO clock.
Kojto	110:165afa46840b	4306	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	110:165afa46840b	4307	* This parameter can be one of the following values:
Kojto	110:165afa46840b	4308	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	110:165afa46840b	4309	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	110:165afa46840b	4310	*/
Kojto	110:165afa46840b	4311	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	4312
Kojto	110:165afa46840b	4313	/** @brief Macro to Get the SDIO clock.
Kojto	110:165afa46840b	4314	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	4315	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	110:165afa46840b	4316	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	110:165afa46840b	4317	*/
Kojto	110:165afa46840b	4318	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
Kojto	110:165afa46840b	4319
Kojto	110:165afa46840b	4320	/** @brief Macro to configure the DSI clock.
Kojto	110:165afa46840b	4321	* @param __SOURCE__: specifies the DSI clock source.
Kojto	110:165afa46840b	4322	* This parameter can be one of the following values:
Kojto	110:165afa46840b	4323	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
Kojto	110:165afa46840b	4324	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
Kojto	110:165afa46840b	4325	*/
Kojto	110:165afa46840b	4326	#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	4327
Kojto	110:165afa46840b	4328	/** @brief Macro to Get the DSI clock.
Kojto	110:165afa46840b	4329	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	4330	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
Kojto	110:165afa46840b	4331	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
Kojto	110:165afa46840b	4332	*/
Kojto	110:165afa46840b	4333	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
Kojto	110:165afa46840b	4334
Kojto	110:165afa46840b	4335	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4336
Kojto	110:165afa46840b	4337	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	4338	/** @brief Macro to configure I2S clock source selection.
Kojto	110:165afa46840b	4339	* @param __SOURCE__: specifies the I2S clock source.
Kojto	110:165afa46840b	4340	* This parameter can be one of the following values:
Kojto	110:165afa46840b	4341	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
Kojto	110:165afa46840b	4342	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	110:165afa46840b	4343	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
Kojto	110:165afa46840b	4344	*/
Kojto	110:165afa46840b	4345	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
Kojto	110:165afa46840b	4346
Kojto	110:165afa46840b	4347	/** @brief Macro to Get I2S clock source selection.
Kojto	110:165afa46840b	4348	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	4349	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
Kojto	110:165afa46840b	4350	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	110:165afa46840b	4351	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
Kojto	110:165afa46840b	4352	*/
Kojto	110:165afa46840b	4353	#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
Kojto	110:165afa46840b	4354
Kojto	110:165afa46840b	4355	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	110:165afa46840b	4356	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	110:165afa46840b	4357	* This parameter can be one of the following values:
Kojto	110:165afa46840b	4358	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	110:165afa46840b	4359	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	4360	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	110:165afa46840b	4361	*/
Kojto	110:165afa46840b	4362	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	4363
Kojto	110:165afa46840b	4364	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	110:165afa46840b	4365	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	4366	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	110:165afa46840b	4367	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	4368	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	110:165afa46840b	4369	*/
Kojto	110:165afa46840b	4370	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	110:165afa46840b	4371
Kojto	110:165afa46840b	4372	/** @brief Macro to configure the LPTIM1 clock.
Kojto	110:165afa46840b	4373	* @param __SOURCE__: specifies the LPTIM1 clock source.
Kojto	110:165afa46840b	4374	* This parameter can be one of the following values:
Kojto	110:165afa46840b	4375	* @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
Kojto	110:165afa46840b	4376	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
Kojto	110:165afa46840b	4377	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto	110:165afa46840b	4378	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto	110:165afa46840b	4379	*/
Kojto	110:165afa46840b	4380	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	4381
Kojto	110:165afa46840b	4382	/** @brief Macro to Get the LPTIM1 clock.
Kojto	110:165afa46840b	4383	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	4384	* @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
Kojto	110:165afa46840b	4385	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
Kojto	110:165afa46840b	4386	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto	110:165afa46840b	4387	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto	110:165afa46840b	4388	*/
Kojto	110:165afa46840b	4389	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
Kojto	110:165afa46840b	4390	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	4391
Kojto	110:165afa46840b	4392	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	4393	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
Kojto	110:165afa46840b	4394	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
Kojto	110:165afa46840b	4395	defined(STM32F479xx)
emilmont	77:869cf507173a	4396	/** @brief Macro to configure the Timers clocks prescalers
emilmont	77:869cf507173a	4397	* @note This feature is only available with STM32F429x/439x Devices.
emilmont	77:869cf507173a	4398	* @param __PRESC__ : specifies the Timers clocks prescalers selection
emilmont	77:869cf507173a	4399	* This parameter can be one of the following values:
emilmont	77:869cf507173a	4400	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
emilmont	77:869cf507173a	4401	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
emilmont	77:869cf507173a	4402	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
emilmont	77:869cf507173a	4403	* division by 4 or more.
emilmont	77:869cf507173a	4404	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
emilmont	77:869cf507173a	4405	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
emilmont	77:869cf507173a	4406	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
emilmont	77:869cf507173a	4407	* to division by 8 or more.
emilmont	77:869cf507173a	4408	*/
Kojto	99:dbbf35b96557	4409	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
Kojto	90:cb3d968589d8	4410
Kojto	110:165afa46840b	4411	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\|\
Kojto	110:165afa46840b	4412	STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4413
Kojto	110:165afa46840b	4414	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	4415
Kojto	110:165afa46840b	4416	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
emilmont	77:869cf507173a	4417	/** @brief Enable PLLSAI_RDY interrupt.
emilmont	77:869cf507173a	4418	*/
emilmont	77:869cf507173a	4419	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
emilmont	77:869cf507173a	4420
emilmont	77:869cf507173a	4421	/** @brief Disable PLLSAI_RDY interrupt.
emilmont	77:869cf507173a	4422	*/
emilmont	77:869cf507173a	4423	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
emilmont	77:869cf507173a	4424
emilmont	77:869cf507173a	4425	/** @brief Clear the PLLSAI RDY interrupt pending bits.
emilmont	77:869cf507173a	4426	*/
emilmont	77:869cf507173a	4427	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
emilmont	77:869cf507173a	4428
emilmont	77:869cf507173a	4429	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
emilmont	77:869cf507173a	4430	* @retval The new state (TRUE or FALSE).
emilmont	77:869cf507173a	4431	*/
emilmont	77:869cf507173a	4432	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
emilmont	77:869cf507173a	4433
emilmont	77:869cf507173a	4434	/** @brief Check PLLSAI RDY flag is set or not.
emilmont	77:869cf507173a	4435	* @retval The new state (TRUE or FALSE).
emilmont	77:869cf507173a	4436	*/
emilmont	77:869cf507173a	4437	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
emilmont	77:869cf507173a	4438
Kojto	110:165afa46840b	4439	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4440
Kojto	110:165afa46840b	4441	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	4442	/** @defgroup RCCEx_MCO1_Enable MCO1 Enable
Kojto	110:165afa46840b	4443	* @brief Macros to enable or disable the RCC MCO1 feature.
Kojto	110:165afa46840b	4444	*/
Kojto	110:165afa46840b	4445	#define __HAL_RCC_MCO1_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = ENABLE)
Kojto	110:165afa46840b	4446	#define __HAL_RCC_MCO1_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = DISABLE)
Kojto	110:165afa46840b	4447	/**
Kojto	110:165afa46840b	4448	* @}
Kojto	110:165afa46840b	4449	*/
Kojto	110:165afa46840b	4450
Kojto	110:165afa46840b	4451	/** @defgroup RCCEx_MCO2_Enable MCO2 Enable
Kojto	110:165afa46840b	4452	* @brief Macros to enable or disable the RCC MCO2 feature.
Kojto	110:165afa46840b	4453	*/
Kojto	110:165afa46840b	4454	#define __HAL_RCC_MCO2_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = ENABLE)
Kojto	110:165afa46840b	4455	#define __HAL_RCC_MCO2_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = DISABLE)
Kojto	110:165afa46840b	4456	/**
Kojto	110:165afa46840b	4457	* @}
Kojto	110:165afa46840b	4458	*/
Kojto	110:165afa46840b	4459	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	4460
Kojto	99:dbbf35b96557	4461	/**
Kojto	99:dbbf35b96557	4462	* @}
Kojto	99:dbbf35b96557	4463	*/
emilmont	77:869cf507173a	4464
emilmont	77:869cf507173a	4465	/* Exported functions --------------------------------------------------------*/
Kojto	99:dbbf35b96557	4466	/** @addtogroup RCCEx_Exported_Functions
Kojto	99:dbbf35b96557	4467	* @{
Kojto	99:dbbf35b96557	4468	*/
Kojto	99:dbbf35b96557	4469
Kojto	99:dbbf35b96557	4470	/** @addtogroup RCCEx_Exported_Functions_Group1
Kojto	99:dbbf35b96557	4471	* @{
Kojto	99:dbbf35b96557	4472	*/
emilmont	77:869cf507173a	4473	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
emilmont	77:869cf507173a	4474	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
emilmont	77:869cf507173a	4475
Kojto	99:dbbf35b96557	4476	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	4477	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto	99:dbbf35b96557	4478	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	4479
Kojto	110:165afa46840b	4480	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
Kojto	110:165afa46840b	4481	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	90:cb3d968589d8	4482	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
Kojto	110:165afa46840b	4483	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
emilmont	77:869cf507173a	4484	/**
emilmont	77:869cf507173a	4485	* @}
emilmont	77:869cf507173a	4486	*/
emilmont	77:869cf507173a	4487
emilmont	77:869cf507173a	4488	/**
emilmont	77:869cf507173a	4489	* @}
emilmont	77:869cf507173a	4490	*/
Kojto	99:dbbf35b96557	4491	/* Private types -------------------------------------------------------------*/
Kojto	99:dbbf35b96557	4492	/* Private variables ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	4493	/* Private constants ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	4494	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
Kojto	99:dbbf35b96557	4495	* @{
Kojto	99:dbbf35b96557	4496	*/
Kojto	99:dbbf35b96557	4497
Kojto	99:dbbf35b96557	4498	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	99:dbbf35b96557	4499	* @brief RCC registers bit address in the alias region
Kojto	99:dbbf35b96557	4500	* @{
Kojto	99:dbbf35b96557	4501	*/
Kojto	99:dbbf35b96557	4502	/* --- CR Register ---*/
Kojto	110:165afa46840b	4503	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	4504	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	4505	/* Alias word address of PLLSAION bit */
Kojto	99:dbbf35b96557	4506	#define RCC_PLLSAION_BIT_NUMBER 0x1C
Kojto	99:dbbf35b96557	4507	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
Kojto	99:dbbf35b96557	4508
Kojto	110:165afa46840b	4509	#define PLLSAI_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
Kojto	110:165afa46840b	4510	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4511
Kojto	110:165afa46840b	4512	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	4513	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	4514	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	110:165afa46840b	4515	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	4516	/* Alias word address of PLLI2SON bit */
Kojto	110:165afa46840b	4517	#define RCC_PLLI2SON_BIT_NUMBER 0x1A
Kojto	110:165afa46840b	4518	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
Kojto	110:165afa46840b	4519	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	110:165afa46840b	4520	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4521
Kojto	99:dbbf35b96557	4522	/* --- DCKCFGR Register ---*/
Kojto	110:165afa46840b	4523	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	4524	defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
Kojto	110:165afa46840b	4525	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	4526	/* Alias word address of TIMPRE bit */
Kojto	99:dbbf35b96557	4527	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
Kojto	99:dbbf35b96557	4528	#define RCC_TIMPRE_BIT_NUMBER 0x18
Kojto	99:dbbf35b96557	4529	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
Kojto	110:165afa46840b	4530	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4531
Kojto	110:165afa46840b	4532	/* --- CFGR Register ---*/
Kojto	110:165afa46840b	4533	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
Kojto	110:165afa46840b	4534	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	4535	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	4536	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	110:165afa46840b	4537	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	4538	/* Alias word address of I2SSRC bit */
Kojto	110:165afa46840b	4539	#define RCC_I2SSRC_BIT_NUMBER 0x17
Kojto	110:165afa46840b	4540	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
Kojto	110:165afa46840b	4541
Kojto	110:165afa46840b	4542	#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
Kojto	110:165afa46840b	4543	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	110:165afa46840b	4544	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4545
Kojto	110:165afa46840b	4546	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	4547	/* Alias word address of MCO1EN bit */
Kojto	110:165afa46840b	4548	#define RCC_MCO1EN_BIT_NUMBER 0x8
Kojto	110:165afa46840b	4549	#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
Kojto	110:165afa46840b	4550
Kojto	110:165afa46840b	4551	/* Alias word address of MCO2EN bit */
Kojto	110:165afa46840b	4552	#define RCC_MCO2EN_BIT_NUMBER 0x9
Kojto	110:165afa46840b	4553	#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
Kojto	110:165afa46840b	4554	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	4555
Kojto	99:dbbf35b96557	4556	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	99:dbbf35b96557	4557	/**
Kojto	99:dbbf35b96557	4558	* @}
Kojto	99:dbbf35b96557	4559	*/
Kojto	99:dbbf35b96557	4560
Kojto	99:dbbf35b96557	4561	/**
Kojto	99:dbbf35b96557	4562	* @}
Kojto	99:dbbf35b96557	4563	*/
Kojto	99:dbbf35b96557	4564
Kojto	99:dbbf35b96557	4565	/* Private macros ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	4566	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
Kojto	99:dbbf35b96557	4567	* @{
Kojto	99:dbbf35b96557	4568	*/
Kojto	99:dbbf35b96557	4569	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto	99:dbbf35b96557	4570	* @{
Kojto	99:dbbf35b96557	4571	*/
Kojto	99:dbbf35b96557	4572
Kojto	99:dbbf35b96557	4573	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	110:165afa46840b	4574	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000007F))
Kojto	99:dbbf35b96557	4575	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	4576
Kojto	99:dbbf35b96557	4577	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
Kojto	99:dbbf35b96557	4578	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	110:165afa46840b	4579	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000007))
Kojto	99:dbbf35b96557	4580	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	99:dbbf35b96557	4581
Kojto	110:165afa46840b	4582	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	4583	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001F))
Kojto	110:165afa46840b	4584	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	4585
Kojto	99:dbbf35b96557	4586	#if defined(STM32F446xx)
Kojto	110:165afa46840b	4587	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000FFF))
Kojto	99:dbbf35b96557	4588	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	4589
Kojto	110:165afa46840b	4590	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	4591	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000001FF))
Kojto	110:165afa46840b	4592	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4593
Kojto	99:dbbf35b96557	4594	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto	99:dbbf35b96557	4595	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	99:dbbf35b96557	4596
Kojto	99:dbbf35b96557	4597
Kojto	110:165afa46840b	4598	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	4599	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	4600	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto	99:dbbf35b96557	4601
Kojto	99:dbbf35b96557	4602	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
Kojto	99:dbbf35b96557	4603
Kojto	99:dbbf35b96557	4604	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto	99:dbbf35b96557	4605
Kojto	99:dbbf35b96557	4606	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	99:dbbf35b96557	4607
Kojto	99:dbbf35b96557	4608	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto	99:dbbf35b96557	4609
Kojto	99:dbbf35b96557	4610	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto	99:dbbf35b96557	4611
Kojto	99:dbbf35b96557	4612	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
Kojto	99:dbbf35b96557	4613	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
Kojto	99:dbbf35b96557	4614	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
Kojto	99:dbbf35b96557	4615	((VALUE) == RCC_PLLSAIDIVR_16))
Kojto	110:165afa46840b	4616	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4617
Kojto	110:165afa46840b	4618	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
Kojto	99:dbbf35b96557	4619	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
Kojto	99:dbbf35b96557	4620
Kojto	99:dbbf35b96557	4621	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	99:dbbf35b96557	4622	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	110:165afa46840b	4623	#endif /* STM32F411xE \|\| STM32F446xx */
Kojto	110:165afa46840b	4624
Kojto	110:165afa46840b	4625	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	4626	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	110:165afa46840b	4627
Kojto	110:165afa46840b	4628	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	110:165afa46840b	4629	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	110:165afa46840b	4630
Kojto	110:165afa46840b	4631	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
Kojto	110:165afa46840b	4632	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	110:165afa46840b	4633	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	110:165afa46840b	4634
Kojto	110:165afa46840b	4635	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) \|\|\
Kojto	110:165afa46840b	4636	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
Kojto	110:165afa46840b	4637	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
Kojto	110:165afa46840b	4638	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
Kojto	110:165afa46840b	4639
Kojto	110:165afa46840b	4640	#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) \|\|\
Kojto	110:165afa46840b	4641	((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) \|\|\
Kojto	110:165afa46840b	4642	((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
Kojto	110:165afa46840b	4643	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	4644
Kojto	99:dbbf35b96557	4645	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	4646	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
emilmont	77:869cf507173a	4647
Kojto	99:dbbf35b96557	4648	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
Kojto	99:dbbf35b96557	4649	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
Kojto	99:dbbf35b96557	4650	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
Kojto	99:dbbf35b96557	4651	((VALUE) == RCC_PLLI2SP_DIV8))
Kojto	99:dbbf35b96557	4652
Kojto	99:dbbf35b96557	4653	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
Kojto	99:dbbf35b96557	4654
Kojto	99:dbbf35b96557	4655	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
Kojto	99:dbbf35b96557	4656	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
Kojto	99:dbbf35b96557	4657	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
Kojto	99:dbbf35b96557	4658	((VALUE) == RCC_PLLSAIP_DIV8))
Kojto	99:dbbf35b96557	4659
Kojto	99:dbbf35b96557	4660	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
Kojto	99:dbbf35b96557	4661	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	4662	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	4663	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
Kojto	99:dbbf35b96557	4664
Kojto	99:dbbf35b96557	4665	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
Kojto	99:dbbf35b96557	4666	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	4667	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	4668	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	4669
Kojto	99:dbbf35b96557	4670	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	4671	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
Kojto	99:dbbf35b96557	4672	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	4673	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	4674
Kojto	99:dbbf35b96557	4675	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	4676	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
Kojto	99:dbbf35b96557	4677	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	4678	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	4679
Kojto	99:dbbf35b96557	4680	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
Kojto	99:dbbf35b96557	4681	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	99:dbbf35b96557	4682	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	99:dbbf35b96557	4683
Kojto	99:dbbf35b96557	4684	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
Kojto	99:dbbf35b96557	4685	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	99:dbbf35b96557	4686
Kojto	99:dbbf35b96557	4687	#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) \|\|\
Kojto	99:dbbf35b96557	4688	((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
Kojto	99:dbbf35b96557	4689
Kojto	99:dbbf35b96557	4690	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) \|\|\
Kojto	99:dbbf35b96557	4691	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	99:dbbf35b96557	4692
Kojto	110:165afa46840b	4693	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	4694	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
Kojto	110:165afa46840b	4695	#endif /* STM32F446xx */
Kojto	110:165afa46840b	4696
Kojto	110:165afa46840b	4697	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	4698	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	110:165afa46840b	4699
Kojto	110:165afa46840b	4700	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
Kojto	110:165afa46840b	4701	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
Kojto	110:165afa46840b	4702	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
Kojto	110:165afa46840b	4703	((VALUE) == RCC_PLLSAIP_DIV8))
Kojto	110:165afa46840b	4704
Kojto	110:165afa46840b	4705	#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) \|\|\
Kojto	110:165afa46840b	4706	((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
Kojto	110:165afa46840b	4707
Kojto	110:165afa46840b	4708	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) \|\|\
Kojto	110:165afa46840b	4709	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	110:165afa46840b	4710
Kojto	110:165afa46840b	4711	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
Kojto	110:165afa46840b	4712	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
Kojto	110:165afa46840b	4713
Kojto	110:165afa46840b	4714	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	110:165afa46840b	4715	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	110:165afa46840b	4716	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4717
Kojto	110:165afa46840b	4718	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	4719	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	4720	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	110:165afa46840b	4721	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	4722
Kojto	110:165afa46840b	4723	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
Kojto	110:165afa46840b	4724	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto	110:165afa46840b	4725
Kojto	110:165afa46840b	4726	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	110:165afa46840b	4727	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	4728
Kojto	110:165afa46840b	4729	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	4730	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)\|\| \
Kojto	110:165afa46840b	4731	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto	110:165afa46840b	4732	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	4733	/**
Kojto	99:dbbf35b96557	4734	* @}
Kojto	99:dbbf35b96557	4735	*/
Kojto	99:dbbf35b96557	4736
Kojto	99:dbbf35b96557	4737	/**
Kojto	99:dbbf35b96557	4738	* @}
Kojto	99:dbbf35b96557	4739	*/
Kojto	99:dbbf35b96557	4740
Kojto	99:dbbf35b96557	4741	/**
Kojto	99:dbbf35b96557	4742	* @}
Kojto	99:dbbf35b96557	4743	*/
Kojto	99:dbbf35b96557	4744
Kojto	99:dbbf35b96557	4745	/**
Kojto	99:dbbf35b96557	4746	* @}
Kojto	99:dbbf35b96557	4747	*/
emilmont	77:869cf507173a	4748	#ifdef __cplusplus
emilmont	77:869cf507173a	4749	}
emilmont	77:869cf507173a	4750	#endif
emilmont	77:869cf507173a	4751
emilmont	77:869cf507173a	4752	#endif /* __STM32F4xx_HAL_RCC_EX_H */
emilmont	77:869cf507173a	4753
emilmont	77:869cf507173a	4754	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Apr 2016
Imports:	0
Forks:	0
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TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h@110:165afa46840b, 2015-11-25 (annotated)

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