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Fork of FRDM_MMA8451Q by
MMA8451Q.cpp@6:c52175d13e0a, 2013-05-28 (annotated)
- Committer:
- clemente
- Date:
- Tue May 28 07:29:58 2013 +0000
- Revision:
- 6:c52175d13e0a
- Parent:
- 5:695063448f2a
- Child:
- 7:ba0016258d5d
Added Orientation. To be completed and tested.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
samux | 1:d2630136d51e | 1 | /* Copyright (c) 2010-2011 mbed.org, MIT License |
samux | 1:d2630136d51e | 2 | * |
samux | 1:d2630136d51e | 3 | * Permission is hereby granted, free of charge, to any person obtaining a copy of this software |
samux | 1:d2630136d51e | 4 | * and associated documentation files (the "Software"), to deal in the Software without |
samux | 1:d2630136d51e | 5 | * restriction, including without limitation the rights to use, copy, modify, merge, publish, |
samux | 1:d2630136d51e | 6 | * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the |
samux | 1:d2630136d51e | 7 | * Software is furnished to do so, subject to the following conditions: |
samux | 1:d2630136d51e | 8 | * |
samux | 1:d2630136d51e | 9 | * The above copyright notice and this permission notice shall be included in all copies or |
samux | 1:d2630136d51e | 10 | * substantial portions of the Software. |
samux | 1:d2630136d51e | 11 | * |
samux | 1:d2630136d51e | 12 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING |
samux | 1:d2630136d51e | 13 | * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
samux | 1:d2630136d51e | 14 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, |
samux | 1:d2630136d51e | 15 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
samux | 1:d2630136d51e | 16 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
samux | 1:d2630136d51e | 17 | */ |
samux | 1:d2630136d51e | 18 | |
emilmont | 0:6149091f755d | 19 | #include "MMA8451Q.h" |
emilmont | 0:6149091f755d | 20 | |
samux | 1:d2630136d51e | 21 | #define REG_WHO_AM_I 0x0D |
samux | 1:d2630136d51e | 22 | #define REG_CTRL_REG_1 0x2A |
clemente | 5:695063448f2a | 23 | #define REG_CTRL_REG_4 0x2D |
clemente | 5:695063448f2a | 24 | #define REG_CTRL_REG_5 0x2E |
clemente | 5:695063448f2a | 25 | #define REG_INT_SRC 0x0C |
clemente | 5:695063448f2a | 26 | #define REG_FF_MT_CFG 0x15 |
clemente | 5:695063448f2a | 27 | #define REG_FF_MT_SRC 0x16 |
clemente | 5:695063448f2a | 28 | #define REG_FF_MT_THS 0x17 |
clemente | 5:695063448f2a | 29 | #define REG_FF_MT_CNT 0x18 |
clemente | 6:c52175d13e0a | 30 | #define REG_DBCNTM 0x11 |
clemente | 6:c52175d13e0a | 31 | #define REG_DBNCE 0x12 |
clemente | 6:c52175d13e0a | 32 | #define REG_BKFR 0x13 |
clemente | 6:c52175d13e0a | 33 | #define REG_P_L_THS 0x14 |
clemente | 5:695063448f2a | 34 | // |
emilmont | 0:6149091f755d | 35 | #define REG_OUT_X_MSB 0x01 |
emilmont | 0:6149091f755d | 36 | #define REG_OUT_Y_MSB 0x03 |
emilmont | 0:6149091f755d | 37 | #define REG_OUT_Z_MSB 0x05 |
emilmont | 0:6149091f755d | 38 | |
samux | 1:d2630136d51e | 39 | #define UINT14_MAX 16383 |
emilmont | 0:6149091f755d | 40 | |
clemente | 5:695063448f2a | 41 | void (*fall_fptr)(void); |
clemente | 5:695063448f2a | 42 | void (*motion_fptr)(void); |
clemente | 5:695063448f2a | 43 | |
clemente | 5:695063448f2a | 44 | // |
clemente | 5:695063448f2a | 45 | InterruptIn MMA8451Q_Int1( PTA14); |
clemente | 5:695063448f2a | 46 | InterruptIn MMA8451Q_Int2( PTA15); |
clemente | 5:695063448f2a | 47 | |
emilmont | 0:6149091f755d | 48 | MMA8451Q::MMA8451Q(PinName sda, PinName scl, int addr) : m_i2c(sda, scl), m_addr(addr) { |
emilmont | 0:6149091f755d | 49 | // activate the peripheral |
emilmont | 0:6149091f755d | 50 | uint8_t data[2] = {REG_CTRL_REG_1, 0x01}; |
samux | 1:d2630136d51e | 51 | writeRegs(data, 2); |
emilmont | 0:6149091f755d | 52 | } |
emilmont | 0:6149091f755d | 53 | |
clemente | 5:695063448f2a | 54 | MMA8451Q::~MMA8451Q() |
clemente | 5:695063448f2a | 55 | { |
clemente | 5:695063448f2a | 56 | MMA8451Q_Int1.fall( NULL); |
clemente | 5:695063448f2a | 57 | MMA8451Q_Int2.fall( NULL); |
clemente | 5:695063448f2a | 58 | fall_fptr = NULL; |
clemente | 5:695063448f2a | 59 | motion_fptr = NULL; |
clemente | 5:695063448f2a | 60 | } |
clemente | 5:695063448f2a | 61 | |
clemente | 5:695063448f2a | 62 | void MMA8451Q::FreFallDetection( void(*fptr)(void)) |
clemente | 5:695063448f2a | 63 | { |
clemente | 5:695063448f2a | 64 | // Example Steps for Configuring Linear Freefall Detection |
clemente | 5:695063448f2a | 65 | // X AND Y AND Z < 0.2g using MFF Function, 50 Hz ODR |
clemente | 5:695063448f2a | 66 | // Step 1: Put the device in Standby Mode: Register 0x2A CTRL_REG1 |
clemente | 5:695063448f2a | 67 | unsigned char data[2] = {REG_CTRL_REG_1, 0x20}; |
clemente | 5:695063448f2a | 68 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 69 | |
clemente | 5:695063448f2a | 70 | // Step 2: Configuration Register set for Freefall Detection enabling “AND” condition, OAE = 0, Enabling X, |
clemente | 5:695063448f2a | 71 | // Y, Z and the Latch |
clemente | 5:695063448f2a | 72 | data[0] = REG_FF_MT_CFG; |
clemente | 5:695063448f2a | 73 | data[1] = 0x01; |
clemente | 5:695063448f2a | 74 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 75 | |
clemente | 5:695063448f2a | 76 | // Step 3: Threshold Setting Value for the resulting acceleration < 0.2g |
clemente | 5:695063448f2a | 77 | // Note: The step count is 0.063g/count |
clemente | 5:695063448f2a | 78 | // • 0.2g/0.063g = 3.17 counts //Round to 3 counts |
clemente | 5:695063448f2a | 79 | data[0] = REG_FF_MT_THS; |
clemente | 5:695063448f2a | 80 | data[1] = 0x03; |
clemente | 5:695063448f2a | 81 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 82 | |
clemente | 5:695063448f2a | 83 | // Step 4: Set the debounce counter to eliminate false positive readings for 50Hz sample rate with a |
clemente | 5:695063448f2a | 84 | // requirement of 120 ms timer, assuming Normal Mode. |
clemente | 5:695063448f2a | 85 | // Note: 120 ms/20 ms (steps) = 6 counts |
clemente | 5:695063448f2a | 86 | data[0] = REG_FF_MT_CNT; |
clemente | 5:695063448f2a | 87 | data[1] = 0x06; |
clemente | 5:695063448f2a | 88 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 89 | |
clemente | 5:695063448f2a | 90 | // Step 5: Enable Motion/Freefall Interrupt Function in the System (CTRL_REG4) |
clemente | 5:695063448f2a | 91 | data[0] = REG_CTRL_REG_4; |
clemente | 5:695063448f2a | 92 | data[1] = 0x04; |
clemente | 5:695063448f2a | 93 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 94 | |
clemente | 5:695063448f2a | 95 | // Step 6: Route the Motion/Freefall Interrupt Function to INT2 hardware pin (CTRL_REG5) |
clemente | 5:695063448f2a | 96 | data[0] = REG_CTRL_REG_5; |
clemente | 5:695063448f2a | 97 | data[1] = 0x00; |
clemente | 5:695063448f2a | 98 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 99 | |
clemente | 5:695063448f2a | 100 | // Step 7: Put the device in Active Mode, 50 Hz |
clemente | 5:695063448f2a | 101 | data[0] = REG_CTRL_REG_1; |
clemente | 5:695063448f2a | 102 | data[1] = 0x21; |
clemente | 5:695063448f2a | 103 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 104 | |
clemente | 5:695063448f2a | 105 | fall_fptr = fptr; |
clemente | 5:695063448f2a | 106 | MMA8451Q_Int2.fall( this, &MMA8451Q::Fall_IRQ); |
clemente | 5:695063448f2a | 107 | } |
clemente | 5:695063448f2a | 108 | |
clemente | 5:695063448f2a | 109 | void MMA8451Q::Fall_IRQ( void) |
clemente | 5:695063448f2a | 110 | { |
clemente | 5:695063448f2a | 111 | unsigned char t; |
clemente | 5:695063448f2a | 112 | |
clemente | 5:695063448f2a | 113 | // Determine source of the interrupt by first reading the system interrupt |
clemente | 5:695063448f2a | 114 | readRegs( REG_INT_SRC, &t, 1); |
clemente | 5:695063448f2a | 115 | // |
clemente | 5:695063448f2a | 116 | if ( (t & 0x04) == 0x04) { |
clemente | 5:695063448f2a | 117 | // Read the Motion/Freefall Function to clear the interrupt |
clemente | 5:695063448f2a | 118 | readRegs( REG_FF_MT_SRC, &t, 1); |
clemente | 5:695063448f2a | 119 | // Run the user supplied function |
clemente | 5:695063448f2a | 120 | fall_fptr(); |
clemente | 5:695063448f2a | 121 | } |
clemente | 5:695063448f2a | 122 | } |
clemente | 5:695063448f2a | 123 | |
clemente | 5:695063448f2a | 124 | void MMA8451Q::MotionDetection( void(*fptr)(void)) |
clemente | 5:695063448f2a | 125 | { |
clemente | 5:695063448f2a | 126 | |
clemente | 5:695063448f2a | 127 | // 6.1 Example Steps for Configuring Motion Detection |
clemente | 5:695063448f2a | 128 | // X or Y > 3g using MFF Function 4g, 100 Hz ODR, Normal Mode |
clemente | 5:695063448f2a | 129 | // Step 1: Put the device into Standby Mode: Register 0x2A CTRL_REG1 |
clemente | 5:695063448f2a | 130 | unsigned char data[2] = {REG_CTRL_REG_1, 0x18}; // Set the device in 100 Hz ODR, Standby |
clemente | 5:695063448f2a | 131 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 132 | |
clemente | 5:695063448f2a | 133 | |
clemente | 5:695063448f2a | 134 | // Step 2: Set Configuration Register for Motion Detection by setting the “OR” condition OAE = 1, enabling |
clemente | 5:695063448f2a | 135 | // X, Y, and the latch |
clemente | 5:695063448f2a | 136 | data[0] = REG_FF_MT_CFG; |
clemente | 5:695063448f2a | 137 | data[1] = 0xD8; |
clemente | 5:695063448f2a | 138 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 139 | |
clemente | 5:695063448f2a | 140 | // Step 3: Threshold Setting Value for the Motion detection of > 2g |
clemente | 5:695063448f2a | 141 | // Note: The step count is 0.063g/ count |
clemente | 5:695063448f2a | 142 | // • 2g/0.063g = 31.7; //Round up to 32 |
clemente | 5:695063448f2a | 143 | data[0] = REG_FF_MT_THS; |
clemente | 5:695063448f2a | 144 | data[1] = 0x20; |
clemente | 5:695063448f2a | 145 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 146 | |
clemente | 5:695063448f2a | 147 | // Step 4: Set the debounce counter to eliminate false readings for 100 Hz sample rate with a requirement |
clemente | 5:695063448f2a | 148 | // of 100 ms timer. |
clemente | 5:695063448f2a | 149 | // Note: 100 ms/10 ms (steps) = 10 counts |
clemente | 5:695063448f2a | 150 | data[0] = REG_FF_MT_CNT; |
clemente | 5:695063448f2a | 151 | data[1] = 0x0A; |
clemente | 5:695063448f2a | 152 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 153 | |
clemente | 5:695063448f2a | 154 | // Step 5: Enable Motion/Freefall Interrupt Function in the System (CTRL_REG4) |
clemente | 5:695063448f2a | 155 | data[0] = REG_CTRL_REG_4; |
clemente | 5:695063448f2a | 156 | data[1] = 0x04; |
clemente | 5:695063448f2a | 157 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 158 | |
clemente | 5:695063448f2a | 159 | // Step 6: Route the Motion/Freefall Interrupt Function to INT1 hardware pin (CTRL_REG5) |
clemente | 5:695063448f2a | 160 | data[0] = REG_CTRL_REG_5; |
clemente | 5:695063448f2a | 161 | data[1] = 0x04; |
clemente | 5:695063448f2a | 162 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 163 | |
clemente | 5:695063448f2a | 164 | // Step 7: Put the device in Active Mode |
clemente | 5:695063448f2a | 165 | data[0] = REG_CTRL_REG_1; |
clemente | 5:695063448f2a | 166 | data[1] = 0x19; |
clemente | 5:695063448f2a | 167 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 168 | |
clemente | 5:695063448f2a | 169 | motion_fptr = fptr; |
clemente | 5:695063448f2a | 170 | MMA8451Q_Int1.fall( this, &MMA8451Q::Motion_IRQ); |
clemente | 5:695063448f2a | 171 | |
clemente | 5:695063448f2a | 172 | } |
clemente | 5:695063448f2a | 173 | |
clemente | 5:695063448f2a | 174 | void MMA8451Q::Motion_IRQ( void) |
clemente | 5:695063448f2a | 175 | { |
clemente | 5:695063448f2a | 176 | unsigned char t; |
clemente | 5:695063448f2a | 177 | |
clemente | 5:695063448f2a | 178 | // Determine source of the interrupt by first reading the system interrupt |
clemente | 5:695063448f2a | 179 | readRegs( REG_INT_SRC, &t, 1); |
clemente | 5:695063448f2a | 180 | // |
clemente | 5:695063448f2a | 181 | if ( (t & 0x04) == 0x04) { |
clemente | 5:695063448f2a | 182 | // Read the Motion/Freefall Function to clear the interrupt |
clemente | 5:695063448f2a | 183 | readRegs( REG_FF_MT_SRC, &t, 1); |
clemente | 5:695063448f2a | 184 | // Run the user supplied function |
clemente | 5:695063448f2a | 185 | motion_fptr(); |
clemente | 5:695063448f2a | 186 | } |
clemente | 5:695063448f2a | 187 | } |
clemente | 5:695063448f2a | 188 | |
clemente | 6:c52175d13e0a | 189 | void MMA8451Q::OrientationDetect( void) |
clemente | 6:c52175d13e0a | 190 | { |
clemente | 6:c52175d13e0a | 191 | OrientationDetect( Z_LOCKOUT_14, Z_BKFR_80, PL_THS_15, PL_HYS_0); |
clemente | 6:c52175d13e0a | 192 | } |
clemente | 6:c52175d13e0a | 193 | |
clemente | 6:c52175d13e0a | 194 | void MMA8451Q::OrientationDetect( unsigned int Z_LockOut, unsigned int Z_BkFr, unsigned int PL_Thsld, unsigned int PL_Hyst) |
clemente | 6:c52175d13e0a | 195 | { |
clemente | 6:c52175d13e0a | 196 | unsigned char t; |
clemente | 6:c52175d13e0a | 197 | |
clemente | 6:c52175d13e0a | 198 | // Step 1: Put the part into Standby Mode |
clemente | 6:c52175d13e0a | 199 | Standby(); |
clemente | 6:c52175d13e0a | 200 | |
clemente | 6:c52175d13e0a | 201 | // Step 2: Set the data rate to 50 Hz (for example, but can choose any sample rate). |
clemente | 6:c52175d13e0a | 202 | readRegs( REG_CTRL_REG_1, &t, 1); // Note: Can combine this step with above |
clemente | 6:c52175d13e0a | 203 | t &= 0xC7; // Clear the sample rate bits |
clemente | 6:c52175d13e0a | 204 | t |= 0x20; // Set the sample rate bits to 50 Hz |
clemente | 6:c52175d13e0a | 205 | unsigned char data[2] = {REG_CTRL_REG_1, t}; |
clemente | 6:c52175d13e0a | 206 | writeRegs(data, 2); // Write updated value into the register. |
clemente | 6:c52175d13e0a | 207 | |
clemente | 6:c52175d13e0a | 208 | |
clemente | 6:c52175d13e0a | 209 | // Step 3: Set the PL_EN bit in Register 0x11 PL_CFG. This will enable the orientation detection. |
clemente | 6:c52175d13e0a | 210 | readRegs( REG_DBCNTM, &t, 1); |
clemente | 6:c52175d13e0a | 211 | data[0] = REG_DBCNTM; |
clemente | 6:c52175d13e0a | 212 | data[1] = t | 0x40; |
clemente | 6:c52175d13e0a | 213 | writeRegs(data, 2); |
clemente | 6:c52175d13e0a | 214 | |
clemente | 6:c52175d13e0a | 215 | // Step 4: Set the Back/Front Angle trip points in register 0x13 following the table in the data sheet. |
clemente | 6:c52175d13e0a | 216 | // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the |
clemente | 6:c52175d13e0a | 217 | // MMA8451Q. |
clemente | 6:c52175d13e0a | 218 | readRegs( REG_BKFR, &t, 1); |
clemente | 6:c52175d13e0a | 219 | t &= 0x3F; // Clear bit 7 and 6 |
clemente | 6:c52175d13e0a | 220 | data[0] = REG_BKFR; |
clemente | 6:c52175d13e0a | 221 | data[1] = t | Z_BkFr; |
clemente | 6:c52175d13e0a | 222 | writeRegs(data, 2); // Write in the updated Back/Front Angle |
clemente | 6:c52175d13e0a | 223 | |
clemente | 6:c52175d13e0a | 224 | // Step 5: Set the Z-Lockout angle trip point in register 0x13 following the table in the data sheet. |
clemente | 6:c52175d13e0a | 225 | // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the |
clemente | 6:c52175d13e0a | 226 | // MMA8451Q. |
clemente | 6:c52175d13e0a | 227 | readRegs( REG_BKFR, &t, 1); |
clemente | 6:c52175d13e0a | 228 | t &= 0xF8; // Clear the last three bits of the register |
clemente | 6:c52175d13e0a | 229 | data[0] = REG_BKFR; |
clemente | 6:c52175d13e0a | 230 | data[1] = t | Z_LockOut; |
clemente | 6:c52175d13e0a | 231 | writeRegs(data, 2); // Write in the updated Z-lockout angle |
clemente | 6:c52175d13e0a | 232 | |
clemente | 6:c52175d13e0a | 233 | // Step 6: Set the Trip Threshold Angle |
clemente | 6:c52175d13e0a | 234 | // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the |
clemente | 6:c52175d13e0a | 235 | // MMA8451Q. |
clemente | 6:c52175d13e0a | 236 | // Select the angle desired in the table, and, |
clemente | 6:c52175d13e0a | 237 | // Enter in the values given in the table for the corresponding angle. |
clemente | 6:c52175d13e0a | 238 | // Refer to Figure 7 for the reference frame of the trip angles. |
clemente | 6:c52175d13e0a | 239 | readRegs( REG_P_L_THS, &t, 1); |
clemente | 6:c52175d13e0a | 240 | t &= 0x07; // Clear the Threshold values |
clemente | 6:c52175d13e0a | 241 | data[0] = REG_P_L_THS; |
clemente | 6:c52175d13e0a | 242 | data[1] = t | (PL_Thsld<<3); |
clemente | 6:c52175d13e0a | 243 | writeRegs(data, 2); |
clemente | 6:c52175d13e0a | 244 | |
clemente | 6:c52175d13e0a | 245 | // Step 7: Set the Hysteresis Angle |
clemente | 6:c52175d13e0a | 246 | // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the |
clemente | 6:c52175d13e0a | 247 | // MMA8451Q. |
clemente | 6:c52175d13e0a | 248 | // Select the hysteresis value based on the desired final trip points (threshold + hysteresis) |
clemente | 6:c52175d13e0a | 249 | // Enter in the values given in the table for that corresponding angle. |
clemente | 6:c52175d13e0a | 250 | // Note: Care must be taken. Review the final resulting angles. Make sure there isn’t a resulting trip value |
clemente | 6:c52175d13e0a | 251 | // greater than 90 or less than 0. |
clemente | 6:c52175d13e0a | 252 | // The following are the options for setting the hysteresis. |
clemente | 6:c52175d13e0a | 253 | readRegs( REG_P_L_THS, &t, 1); |
clemente | 6:c52175d13e0a | 254 | t &= 0xF8; // Clear the Hysteresis values |
clemente | 6:c52175d13e0a | 255 | data[0] = REG_P_L_THS; |
clemente | 6:c52175d13e0a | 256 | data[1] = t | PL_Hyst; |
clemente | 6:c52175d13e0a | 257 | writeRegs(data, 2); |
clemente | 6:c52175d13e0a | 258 | |
clemente | 6:c52175d13e0a | 259 | // Step 8: Register 0x2D, Control Register 4 configures all embedded features for interrupt |
clemente | 6:c52175d13e0a | 260 | // detection. |
clemente | 6:c52175d13e0a | 261 | // To set this device up to run an interrupt service routine: |
clemente | 6:c52175d13e0a | 262 | // Program the Orientation Detection bit in Control Register 4. |
clemente | 6:c52175d13e0a | 263 | // Set bit 4 to enable the orientation detection “INT_EN_LNDPRT”. |
clemente | 6:c52175d13e0a | 264 | readRegs( REG_CTRL_REG_4, &t, 1); |
clemente | 6:c52175d13e0a | 265 | data[0] = REG_CTRL_REG_4; |
clemente | 6:c52175d13e0a | 266 | data[1] = t | 0x10; // Set bit 4 |
clemente | 6:c52175d13e0a | 267 | writeRegs(data, 2); |
clemente | 6:c52175d13e0a | 268 | |
clemente | 6:c52175d13e0a | 269 | // Step 9: Register 0x2E is Control Register 5 which gives the option of routing the interrupt to |
clemente | 6:c52175d13e0a | 270 | // either INT1 or INT2 |
clemente | 6:c52175d13e0a | 271 | // Depending on which interrupt pin is enabled and configured to the processor: |
clemente | 6:c52175d13e0a | 272 | // Set bit 4 “INT_CFG_LNDPRT” to configure INT1, or, |
clemente | 6:c52175d13e0a | 273 | // Leave the bit clear to configure INT2. |
clemente | 6:c52175d13e0a | 274 | readRegs( REG_CTRL_REG_5, &t, 1); |
clemente | 6:c52175d13e0a | 275 | data[0] = REG_CTRL_REG_5; |
clemente | 6:c52175d13e0a | 276 | data[1] = t | 0x10; // Set bit 4 to choose the interrupt to route to INT1 |
clemente | 6:c52175d13e0a | 277 | data[1] = t & 0xEF; // Clear bit 4 to choose the interrupt to route to INT2 |
clemente | 6:c52175d13e0a | 278 | writeRegs(data, 2); |
clemente | 6:c52175d13e0a | 279 | |
clemente | 6:c52175d13e0a | 280 | // Step 10: Set the debounce counter in register 0x12 |
clemente | 6:c52175d13e0a | 281 | // This value will scale depending on the application-specific required ODR. |
clemente | 6:c52175d13e0a | 282 | // If the device is set to go to sleep, reset the debounce counter before the device goes to sleep. This setting |
clemente | 6:c52175d13e0a | 283 | // helps avoid long delays since the debounce will always scale with the current sample rate. The debounce |
clemente | 6:c52175d13e0a | 284 | // can be set between 50 ms - 100 ms to avoid long delays. |
clemente | 6:c52175d13e0a | 285 | data[0] = REG_DBNCE; |
clemente | 6:c52175d13e0a | 286 | data[1] = 0x05; // This sets the debounce counter to 100 ms at 50 Hz |
clemente | 6:c52175d13e0a | 287 | writeRegs(data, 2); |
clemente | 6:c52175d13e0a | 288 | |
clemente | 6:c52175d13e0a | 289 | // Step 11: Put the device in Active Mode |
clemente | 6:c52175d13e0a | 290 | Active(); |
clemente | 6:c52175d13e0a | 291 | |
clemente | 6:c52175d13e0a | 292 | } |
clemente | 6:c52175d13e0a | 293 | |
clemente | 5:695063448f2a | 294 | void MMA8451Q::Active( void) |
clemente | 5:695063448f2a | 295 | { |
clemente | 5:695063448f2a | 296 | unsigned char t; |
clemente | 5:695063448f2a | 297 | |
clemente | 5:695063448f2a | 298 | // Activate the peripheral |
clemente | 5:695063448f2a | 299 | readRegs(REG_CTRL_REG_1, &t, 1); |
clemente | 5:695063448f2a | 300 | unsigned char data[2] = {REG_CTRL_REG_1, t|0x01}; |
clemente | 5:695063448f2a | 301 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 302 | } |
clemente | 5:695063448f2a | 303 | |
clemente | 5:695063448f2a | 304 | void MMA8451Q::Standby( void) |
clemente | 5:695063448f2a | 305 | { |
clemente | 5:695063448f2a | 306 | unsigned char t; |
clemente | 5:695063448f2a | 307 | |
clemente | 5:695063448f2a | 308 | // Standby |
clemente | 5:695063448f2a | 309 | readRegs(REG_CTRL_REG_1, &t, 1); |
clemente | 5:695063448f2a | 310 | unsigned char data[2] = {REG_CTRL_REG_1, t&0xFE}; |
clemente | 5:695063448f2a | 311 | writeRegs(data, 2); |
clemente | 5:695063448f2a | 312 | } |
emilmont | 0:6149091f755d | 313 | |
emilmont | 0:6149091f755d | 314 | uint8_t MMA8451Q::getWhoAmI() { |
emilmont | 0:6149091f755d | 315 | uint8_t who_am_i = 0; |
samux | 1:d2630136d51e | 316 | readRegs(REG_WHO_AM_I, &who_am_i, 1); |
emilmont | 0:6149091f755d | 317 | return who_am_i; |
emilmont | 0:6149091f755d | 318 | } |
emilmont | 0:6149091f755d | 319 | |
chris | 3:db7126dbd63f | 320 | float MMA8451Q::getAccX() { |
chris | 3:db7126dbd63f | 321 | return (float(getAccAxis(REG_OUT_X_MSB))/4096.0); |
emilmont | 0:6149091f755d | 322 | } |
emilmont | 0:6149091f755d | 323 | |
chris | 3:db7126dbd63f | 324 | float MMA8451Q::getAccY() { |
chris | 3:db7126dbd63f | 325 | return (float(getAccAxis(REG_OUT_Y_MSB))/4096.0); |
emilmont | 0:6149091f755d | 326 | } |
emilmont | 0:6149091f755d | 327 | |
chris | 3:db7126dbd63f | 328 | float MMA8451Q::getAccZ() { |
chris | 3:db7126dbd63f | 329 | return (float(getAccAxis(REG_OUT_Z_MSB))/4096.0); |
emilmont | 0:6149091f755d | 330 | } |
emilmont | 0:6149091f755d | 331 | |
chris | 3:db7126dbd63f | 332 | void MMA8451Q::getAccAllAxis(float * res) { |
emilmont | 0:6149091f755d | 333 | res[0] = getAccX(); |
emilmont | 0:6149091f755d | 334 | res[1] = getAccY(); |
emilmont | 0:6149091f755d | 335 | res[2] = getAccZ(); |
emilmont | 0:6149091f755d | 336 | } |
emilmont | 0:6149091f755d | 337 | |
emilmont | 0:6149091f755d | 338 | int16_t MMA8451Q::getAccAxis(uint8_t addr) { |
emilmont | 0:6149091f755d | 339 | int16_t acc; |
emilmont | 0:6149091f755d | 340 | uint8_t res[2]; |
samux | 1:d2630136d51e | 341 | readRegs(addr, res, 2); |
emilmont | 0:6149091f755d | 342 | |
emilmont | 0:6149091f755d | 343 | acc = (res[0] << 6) | (res[1] >> 2); |
emilmont | 0:6149091f755d | 344 | if (acc > UINT14_MAX/2) |
emilmont | 0:6149091f755d | 345 | acc -= UINT14_MAX; |
emilmont | 0:6149091f755d | 346 | |
emilmont | 0:6149091f755d | 347 | return acc; |
emilmont | 0:6149091f755d | 348 | } |
emilmont | 0:6149091f755d | 349 | |
samux | 1:d2630136d51e | 350 | void MMA8451Q::readRegs(int addr, uint8_t * data, int len) { |
emilmont | 0:6149091f755d | 351 | char t[1] = {addr}; |
emilmont | 0:6149091f755d | 352 | m_i2c.write(m_addr, t, 1, true); |
emilmont | 0:6149091f755d | 353 | m_i2c.read(m_addr, (char *)data, len); |
emilmont | 0:6149091f755d | 354 | } |
emilmont | 0:6149091f755d | 355 | |
samux | 1:d2630136d51e | 356 | void MMA8451Q::writeRegs(uint8_t * data, int len) { |
emilmont | 0:6149091f755d | 357 | m_i2c.write(m_addr, (char *)data, len); |
emilmont | 0:6149091f755d | 358 | } |