Internal and external clocks, PLL, CSS and MCO configuration functions. More...

Functions
void	RCC_DeInit (void)
	Resets the RCC clock configuration to the default reset state.
void	RCC_HSEConfig (uint8_t RCC_HSE)
	Configures the External High Speed oscillator (HSE).
ErrorStatus	RCC_WaitForHSEStartUp (void)
	Waits for HSE start-up.
void	RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
	Adjusts the Internal High Speed oscillator (HSI) calibration value.
void	RCC_HSICmd (FunctionalState NewState)
	Enables or disables the Internal High Speed oscillator (HSI).
void	RCC_LSEConfig (uint8_t RCC_LSE)
	Configures the External Low Speed oscillator (LSE).
void	RCC_LSICmd (FunctionalState NewState)
	Enables or disables the Internal Low Speed oscillator (LSI).
void	RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR)
	Configures the main PLL clock source, multiplication and division factors.
void	RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
	Configures the main PLL clock source, multiplication and division factors.
void	RCC_PLLCmd (FunctionalState NewState)
	Enables or disables the main PLL.
void	RCC_PLLI2SConfig (uint32_t PLLI2SN, uint32_t PLLI2SR)
	Configures the PLLI2S clock multiplication and division factors.
void	RCC_PLLI2SConfig (uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM)
	Configures the PLLI2S clock multiplication and division factors.
void	RCC_PLLI2SConfig (uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR)
	Configures the PLLI2S clock multiplication and division factors.
void	RCC_PLLI2SCmd (FunctionalState NewState)
	Enables or disables the PLLI2S.
void	RCC_PLLSAIConfig (uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR)
	Configures the PLLSAI clock multiplication and division factors.
void	RCC_PLLSAIConfig (uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
	Configures the PLLSAI clock multiplication and division factors.
void	RCC_PLLSAICmd (FunctionalState NewState)
	Enables or disables the PLLSAI.
void	RCC_ClockSecuritySystemCmd (FunctionalState NewState)
	Enables or disables the Clock Security System.
void	RCC_MCO1Config (uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
	Selects the clock source to output on MCO1 pin(PA8).
void	RCC_MCO2Config (uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
	Selects the clock source to output on MCO2 pin(PC9).

Detailed Description

Internal and external clocks, PLL, CSS and MCO configuration functions.

 ===================================================================================
 ##### Internal and  external clocks, PLL, CSS and MCO configuration functions #####
 ===================================================================================
    [..]
      This section provide functions allowing to configure the internal/external clocks,
      PLLs, CSS and MCO pins.
  
      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
          the PLL as System clock source.

      (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
          clock source.

      (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
          through the PLL as System clock source. Can be used also as RTC clock source.

      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   

      (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
        (++) The first output is used to generate the high speed system clock (up to 168 MHz)
        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
             the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).

      (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve 
          high-quality audio performance on the I2S interface or SAI interface in case 
          of STM32F429x/439x devices.
     
      (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI 
          interface and LCD TFT controller available only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
  
      (#) CSS (Clock security system), once enable and if a HSE clock failure occurs 
         (HSE used directly or through PLL as System clock source), the System clock
         is automatically switched to HSI and an interrupt is generated if enabled. 
         The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) 
         exception vector.   

      (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
          clock (through a configurable prescaler) on PA8 pin.

      (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
          clock (through a configurable prescaler) on PC9 pin.

Function Documentation

void RCC_AdjustHSICalibrationValue ( uint8_t HSICalibrationValue )

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Note:: The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.

Parameters:

HSICalibrationValue,: specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.

Return values:

None

Definition at line 339 of file stm32f4xx_rcc_mort.c.

void RCC_ClockSecuritySystemCmd ( FunctionalState NewState )

Enables or disables the Clock Security System.

Note:: If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.

Parameters:

NewState,: new state of the Clock Security System. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 879 of file stm32f4xx_rcc_mort.c.

void RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note:

The default reset state of the clock configuration is given below:

HSI ON and used as system clock source
HSE, PLL and PLLI2S OFF
AHB, APB1 and APB2 prescaler set to 1.
CSS, MCO1 and MCO2 OFF
All interrupts disabled

This function doesn't modify the configuration of the

Peripheral clocks
LSI, LSE and RTC clocks

Parameters:

None

Return values:

None

Definition at line 225 of file stm32f4xx_rcc_mort.c.

void RCC_HSEConfig ( uint8_t RCC_HSE )

Configures the External High Speed oscillator (HSE).

Note:: After enabling the HSE (RCC_HSE_ON_MORT or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.; HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).; The HSE is stopped by hardware when entering STOP and STANDBY modes.; This function reset the CSSON bit, so if the Clock security system(CSS) was previously enabled you have to enable it again after calling this function.

Parameters:

RCC_HSE,:

specifies the new state of the HSE. This parameter can be one of the following values:

RCC_HSE_OFF_MORT: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
RCC_HSE_ON_MORT: turn ON the HSE oscillator
RCC_HSE_Bypass: HSE oscillator bypassed with external clock

Return values:

None

Definition at line 284 of file stm32f4xx_rcc_mort.c.

void RCC_HSICmd ( FunctionalState NewState )

Enables or disables the Internal High Speed oscillator (HSI).

Note:: The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).; HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.; After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source.

Parameters:

NewState,: new state of the HSI. This parameter can be: ENABLE or DISABLE.

Note:: When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Return values:

None

Definition at line 375 of file stm32f4xx_rcc_mort.c.

void RCC_LSEConfig ( uint8_t RCC_LSE )

Configures the External Low Speed oscillator (LSE).

Note:: As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the LSE (to be done once after reset).; After enabling the LSE (RCC_LSE_ON_MORT or RCC_LSE_Bypass), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.

Parameters:

RCC_LSE,:

specifies the new state of the LSE. This parameter can be one of the following values:

RCC_LSE_OFF_MORT: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
RCC_LSE_ON_MORT: turn ON the LSE oscillator
RCC_LSE_Bypass: LSE oscillator bypassed with external clock

Return values:

None

Definition at line 400 of file stm32f4xx_rcc_mort.c.

void RCC_LSICmd ( FunctionalState NewState )

Enables or disables the Internal Low Speed oscillator (LSI).

Note:: After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.; LSI can not be disabled if the IWDG is running.

Parameters:

NewState,: new state of the LSI. This parameter can be: ENABLE or DISABLE.

Note:: When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

Return values:

None

Definition at line 440 of file stm32f4xx_rcc_mort.c.

void RCC_MCO1Config	(	uint32_t	RCC_MCO1Source,
		uint32_t	RCC_MCO1Div
	)

Selects the clock source to output on MCO1 pin(PA8).

Note:: PA8 should be configured in alternate function mode.

Parameters:

RCC_MCO1Source,:

specifies the clock source to output. This parameter can be one of the following values:

RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source

RCC_MCO1Div,:

specifies the MCO1 prescaler. This parameter can be one of the following values:

RCC_MCO1Div_1: no division applied to MCO1 clock
RCC_MCO1Div_2: division by 2 applied to MCO1 clock
RCC_MCO1Div_3: division by 3 applied to MCO1 clock
RCC_MCO1Div_4: division by 4 applied to MCO1 clock
RCC_MCO1Div_5: division by 5 applied to MCO1 clock

Return values:

None

Definition at line 904 of file stm32f4xx_rcc_mort.c.

void RCC_MCO2Config	(	uint32_t	RCC_MCO2Source,
		uint32_t	RCC_MCO2Div
	)

Selects the clock source to output on MCO2 pin(PC9).

Note:: PC9 should be configured in alternate function mode.

Parameters:

RCC_MCO2Source,:

specifies the clock source to output. This parameter can be one of the following values:

RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410xx devices
RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source

RCC_MCO2Div,:

specifies the MCO2 prescaler. This parameter can be one of the following values:

RCC_MCO2Div_1: no division applied to MCO2 clock
RCC_MCO2Div_2: division by 2 applied to MCO2 clock
RCC_MCO2Div_3: division by 3 applied to MCO2 clock
RCC_MCO2Div_4: division by 4 applied to MCO2 clock
RCC_MCO2Div_5: division by 5 applied to MCO2 clock

Note:: For STM32F410xx devices to output I2SCLK clock on MCO2 you should have at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).

Return values:

None

Definition at line 949 of file stm32f4xx_rcc_mort.c.

void RCC_PLLCmd ( FunctionalState NewState )

Enables or disables the main PLL.

Note:: After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.; The main PLL can not be disabled if it is used as system clock source; The main PLL is disabled by hardware when entering STOP and STANDBY modes.

Parameters:

NewState,: new state of the main PLL. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 563 of file stm32f4xx_rcc_mort.c.

void RCC_PLLConfig	(	uint32_t	RCC_PLLSource,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLP,
		uint32_t	PLLQ,
		uint32_t	PLLR
	)

Configures the main PLL clock source, multiplication and division factors.

Note:: This function must be used only when the main PLL is disabled.

Parameters:

RCC_PLLSource,:

specifies the PLL entry clock source. This parameter can be one of the following values:

RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry

Note:: This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.

Parameters:

PLLM,: specifies the division factor for PLL VCO input clock This parameter must be a number between 0 and 63.

Note:: You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

Parameters:

PLLN,: specifies the multiplication factor for PLL VCO output clock This parameter must be a number between 50 and 432.

Note:: You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

Parameters:

PLLP,: specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.

Note:: You have to set the PLLP parameter correctly to not exceed 168 MHz on the System clock frequency.

Parameters:

PLLQ,:	specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between 4 and 15.
PLLR,:	specifies the division factor for I2S, SAI, SYSTEM, SPDIF in STM32F446xx devices This parameter must be a number between 2 and 7.

Note:: If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.

Return values:

None

Definition at line 488 of file stm32f4xx_rcc_mort.c.

void RCC_PLLConfig	(	uint32_t	RCC_PLLSource,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLP,
		uint32_t	PLLQ
	)

Configures the main PLL clock source, multiplication and division factors.

Note:: This function must be used only when the main PLL is disabled.

Parameters:

RCC_PLLSource,:

specifies the PLL entry clock source. This parameter can be one of the following values:

RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry

Note:: This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.

Parameters:

PLLM,: specifies the division factor for PLL VCO input clock This parameter must be a number between 0 and 63.

Note:: You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

Parameters:

PLLN,: specifies the multiplication factor for PLL VCO output clock This parameter must be a number between 50 and 432.

Note:: You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

Parameters:

PLLP,: specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.

Note:: You have to set the PLLP parameter correctly to not exceed 168 MHz on the System clock frequency.

Parameters:

PLLQ,: specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between 4 and 15.

Note:: If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.

Return values:

None

Definition at line 539 of file stm32f4xx_rcc_mort.c.

void RCC_PLLI2SCmd ( FunctionalState NewState )

Enables or disables the PLLI2S.

Note:: The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.

Parameters:

NewState,: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 732 of file stm32f4xx_rcc_mort.c.

void RCC_PLLI2SConfig	(	uint32_t	PLLI2SM,
		uint32_t	PLLI2SN,
		uint32_t	PLLI2SP,
		uint32_t	PLLI2SQ,
		uint32_t	PLLI2SR
	)

Configures the PLLI2S clock multiplication and division factors.

Note:: This function can be used only for STM32F446xx devices; This function must be used only when the PLLI2S is disabled.; PLLI2S clock source is common with the main PLL (configured in RCC_PLLConfig function )

Parameters:

PLLI2SM,: specifies the division factor for PLLI2S VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note:: You have to set the PLLI2SM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLLI2S jitter.

Parameters:

PLLI2SN,: specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between 50 and 432.

Note:: You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

Parameters:

PLLI2SP,:	specifies the division factor for PLL 48Mhz clock output This parameter must be a number in the range {2, 4, 6, or 8}.
PLLI2SQ,:	specifies the division factor for SAI1 clock This parameter must be a number between 2 and 15.
PLLI2SR,:	specifies the division factor for I2S clock This parameter must be a number between 2 and 7.

Note:: You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.; the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices.

Return values:

None

Definition at line 713 of file stm32f4xx_rcc_mort.c.

void RCC_PLLI2SConfig	(	uint32_t	PLLI2SN,
		uint32_t	PLLI2SR
	)

Configures the PLLI2S clock multiplication and division factors.

Note:: This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx or STM32F401xx devices.; This function must be used only when the PLLI2S is disabled.; PLLI2S clock source is common with the main PLL (configured in RCC_PLLConfig function )

Parameters:

PLLI2SN,: specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between 50 and 432.

Note:: You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

Parameters:

PLLI2SR,: specifies the division factor for I2S clock This parameter must be a number between 2 and 7.

Note:: You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.

Return values:

None

Definition at line 593 of file stm32f4xx_rcc_mort.c.

void RCC_PLLI2SConfig	(	uint32_t	PLLI2SN,
		uint32_t	PLLI2SQ,
		uint32_t	PLLI2SR
	)

Configures the PLLI2S clock multiplication and division factors.

Note:: This function can be used only for STM32F411xE devices.; This function must be used only when the PLLI2S is disabled.; PLLI2S clock source is common with the main PLL (configured in RCC_PLLConfig function )

Parameters:

PLLI2SM,: specifies the division factor for PLLI2S VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note:: You have to set the PLLI2SM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLLI2S jitter.

Parameters:

PLLI2SN,: specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between 50 and 432.

Note:: You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

Parameters:

PLLI2SR,: specifies the division factor for I2S clock This parameter must be a number between 2 and 7.

Note:: You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.

Return values:

None

Note:: This function can be used only for STM32F42xxx/43xxx devices; This function must be used only when the PLLI2S is disabled.; PLLI2S clock source is common with the main PLL (configured in RCC_PLLConfig function )

Parameters:

PLLI2SN,: specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between 50 and 432.

Note:: You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

Parameters:

PLLI2SQ,:	specifies the division factor for SAI1 clock This parameter must be a number between 2 and 15.
PLLI2SR,:	specifies the division factor for I2S clock This parameter must be a number between 2 and 7.

Note:: You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.

Return values:

None

Definition at line 631 of file stm32f4xx_rcc_mort.c.

void RCC_PLLSAICmd ( FunctionalState NewState )

Enables or disables the PLLSAI.

Note:: This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices; The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.

Parameters:

NewState,: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 861 of file stm32f4xx_rcc_mort.c.

void RCC_PLLSAIConfig	(	uint32_t	PLLSAIM,
		uint32_t	PLLSAIN,
		uint32_t	PLLSAIP,
		uint32_t	PLLSAIQ
	)

Configures the PLLSAI clock multiplication and division factors.

Note:: This function can be used only for STM32F469_479xx devices; This function must be used only when the PLLSAI is disabled.; PLLSAI clock source is common with the main PLL (configured in RCC_PLLConfig function )

Parameters:

PLLSAIN,: specifies the multiplication factor for PLLSAI VCO output clock This parameter must be a number between 50 and 432.

Note:: You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

Parameters:

PLLSAIP,:	specifies the division factor for PLL 48Mhz clock output This parameter must be a number in the range {2, 4, 6, or 8}..
PLLSAIQ,:	specifies the division factor for SAI1 clock This parameter must be a number between 2 and 15.
PLLSAIR,:	specifies the division factor for LTDC clock This parameter must be a number between 2 and 7.

Return values:

None

Note:: This function can be used only for STM32F446xx devices; This function must be used only when the PLLSAI is disabled.; PLLSAI clock source is common with the main PLL (configured in RCC_PLLConfig function )

Parameters:

PLLSAIM,: specifies the division factor for PLLSAI VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note:: You have to set the PLLSAIM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLLSAI jitter.

Parameters:

PLLSAIN,: specifies the multiplication factor for PLLSAI VCO output clock This parameter must be a number between 50 and 432.

Note:: You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

Parameters:

PLLSAIP,:	specifies the division factor for PLL 48Mhz clock output This parameter must be a number in the range {2, 4, 6, or 8}.
PLLSAIQ,:	specifies the division factor for SAI1 clock This parameter must be a number between 2 and 15.

Return values:

None

Definition at line 765 of file stm32f4xx_rcc_mort.c.

void RCC_PLLSAIConfig	(	uint32_t	PLLSAIN,
		uint32_t	PLLSAIQ,
		uint32_t	PLLSAIR
	)

Configures the PLLSAI clock multiplication and division factors.

Note:: This function can be used only for STM32F42xxx/43xxx devices; This function must be used only when the PLLSAI is disabled.; PLLSAI clock source is common with the main PLL (configured in RCC_PLLConfig function )

Parameters:

PLLSAIN,: specifies the multiplication factor for PLLSAI VCO output clock This parameter must be a number between 50 and 432.

Note:: You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

Parameters:

PLLSAIQ,:	specifies the division factor for SAI1 clock This parameter must be a number between 2 and 15.
PLLSAIR,:	specifies the division factor for LTDC clock This parameter must be a number between 2 and 7.

Return values:

None

Definition at line 841 of file stm32f4xx_rcc_mort.c.

ErrorStatus RCC_WaitForHSEStartUp ( void )

Waits for HSE start-up.

Note:: This functions waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending on the HSE crystal used in your application.

Parameters:

None

Return values:

An	ErrorStatus enumeration value: SUCCESS: HSE oscillator is stable and ready to use ERROR: HSE oscillator not yet ready

Definition at line 308 of file stm32f4xx_rcc_mort.c.

Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	23 Oct 2021
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

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