stm32f4xx_rcc_mort.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_rcc.c
00004   * @author  MCD Application Team
00005   * @version V1.8.0
00006   * @date    04-November-2016
00007   * @brief   This file provides firmware functions to manage the following 
00008   *          functionalities of the Reset and clock control (RCC) peripheral:
00009   *           + Internal/external clocks, PLL, CSS and MCO configuration
00010   *           + System, AHB and APB busses clocks configuration
00011   *           + Peripheral clocks configuration
00012   *           + Interrupts and flags management
00013   *
00014  @verbatim
00015  ===============================================================================
00016                       ##### RCC specific features #####
00017  ===============================================================================
00018     [..]  
00019       After reset the device is running from Internal High Speed oscillator 
00020       (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache 
00021       and I-Cache are disabled, and all peripherals are off except internal
00022       SRAM, Flash and JTAG.
00023       (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
00024           all peripherals mapped on these busses are running at HSI speed.
00025       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00026       (+) All GPIOs are in input floating state, except the JTAG pins which
00027           are assigned to be used for debug purpose.
00028     [..]          
00029       Once the device started from reset, the user application has to:
00030       (+) Configure the clock source to be used to drive the System clock
00031           (if the application needs higher frequency/performance)
00032       (+) Configure the System clock frequency and Flash settings  
00033       (+) Configure the AHB and APB busses prescalers
00034       (+) Enable the clock for the peripheral(s) to be used
00035       (+) Configure the clock source(s) for peripherals which clocks are not
00036           derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
00037  @endverbatim    
00038   ******************************************************************************
00039   * @attention
00040   *
00041   * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
00042   *
00043   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00044   * You may not use this file except in compliance with the License.
00045   * You may obtain a copy of the License at:
00046   *
00047   *        http://www.st.com/software_license_agreement_liberty_v2
00048   *
00049   * Unless required by applicable law or agreed to in writing, software 
00050   * distributed under the License is distributed on an "AS IS" BASIS, 
00051   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00052   * See the License for the specific language governing permissions and
00053   * limitations under the License.
00054   *
00055   ******************************************************************************
00056   */
00057 
00058 /* Includes ------------------------------------------------------------------*/
00059 #include "stm32f4xx_rcc_mort.h"
00060 
00061 /** @addtogroup STM32F4xx_StdPeriph_Driver
00062   * @{
00063   */
00064 
00065 /** @defgroup RCC 
00066   * @brief RCC driver modules
00067   * @{
00068   */ 
00069 
00070 /* Private typedef -----------------------------------------------------------*/
00071 /* Private define ------------------------------------------------------------*/
00072 /* ------------ RCC registers bit address in the alias region ----------- */
00073 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
00074 /* --- CR Register ---*/
00075 /* Alias word address of HSION bit */
00076 #define CR_OFFSET                 (RCC_OFFSET + 0x00)
00077 #define HSION_BitNumber_MORT           0x00
00078 #define CR_HSION_BB_MORT               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
00079 /* Alias word address of CSSON bit */
00080 #define CSSON_BitNumber_MORT           0x13
00081 #define CR_CSSON_BB_MORT               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
00082 /* Alias word address of PLLON bit */
00083 #define PLLON_BitNumber_MORT           0x18
00084 #define CR_PLLON_BB_MORT               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
00085 /* Alias word address of PLLI2SON bit */
00086 #define PLLI2SON_BitNumber_MORT        0x1A
00087 #define CR_PLLI2SON_BB_MORT            (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
00088 
00089 /* Alias word address of PLLSAION bit */
00090 #define PLLSAION_BitNumber_MORT        0x1C
00091 #define CR_PLLSAION_BB_MORT            (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
00092 
00093 /* --- CFGR Register ---*/
00094 /* Alias word address of I2SSRC bit */
00095 #define CFGR_OFFSET               (RCC_OFFSET + 0x08)
00096 #define I2SSRC_BitNumber_MORT          0x17
00097 #define CFGR_I2SSRC_BB_MORT            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
00098 
00099 /* --- BDCR Register ---*/
00100 /* Alias word address of RTCEN bit */
00101 #define BDCR_OFFSET               (RCC_OFFSET + 0x70)
00102 #define RTCEN_BitNumber_MORT           0x0F
00103 #define BDCR_RTCEN_BB_MORT             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
00104 /* Alias word address of BDRST bit */
00105 #define BDRST_BitNumber_MORT           0x10
00106 #define BDCR_BDRST_BB_MORT             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
00107 
00108 /* --- CSR Register ---*/
00109 /* Alias word address of LSION bit */
00110 #define CSR_OFFSET                (RCC_OFFSET + 0x74)
00111 #define LSION_BitNumber_MORT           0x00
00112 #define CSR_LSION_BB_MORT              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
00113 
00114 /* --- DCKCFGR Register ---*/
00115 /* Alias word address of TIMPRE bit */
00116 #define DCKCFGR_OFFSET            (RCC_OFFSET + 0x8C)
00117 #define TIMPRE_BitNumber_MORT          0x18
00118 #define DCKCFGR_TIMPRE_BB_MORT         (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
00119     
00120 /* --- CFGR Register ---*/
00121 #define RCC_CFGR_OFFSET_MORT            (RCC_OFFSET + 0x08)
00122  #if defined(STM32F410xx)
00123 /* Alias word address of MCO1EN bit */
00124 #define RCC_MCO1EN_BIT_NUMBER      0x8
00125 #define RCC_CFGR_MCO1EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
00126 
00127 /* Alias word address of MCO2EN bit */
00128 #define RCC_MCO2EN_BIT_NUMBER      0x9
00129 #define RCC_CFGR_MCO2EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
00130 #endif /* STM32F410xx */
00131 /* ---------------------- RCC registers bit mask ------------------------ */
00132 /* CFGR register bit mask */
00133 #define CFGR_MCO2_RESET_MASK      ((uint32_t)0x07FFFFFF)
00134 #define CFGR_MCO1_RESET_MASK      ((uint32_t)0xF89FFFFF)
00135 
00136 /* RCC Flag Mask */
00137 #define FLAG_MASK                 ((uint8_t)0x1F)
00138 
00139 /* CR register byte 3 (Bits[23:16]) base address */
00140 #define CR_BYTE3_ADDRESS          ((uint32_t)0x40023802)
00141 
00142 /* CIR register byte 2 (Bits[15:8]) base address */
00143 #define CIR_BYTE2_ADDRESS_MORT         ((uint32_t)(RCC_BASE + 0x0C + 0x01))
00144 
00145 /* CIR register byte 3 (Bits[23:16]) base address */
00146 #define CIR_BYTE3_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x02))
00147 
00148 /* BDCR register base address */
00149 #define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
00150 
00151 /* Private macro -------------------------------------------------------------*/
00152 /* Private variables ---------------------------------------------------------*/
00153 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
00154 
00155 /* Private function prototypes -----------------------------------------------*/
00156 /* Private functions ---------------------------------------------------------*/
00157 
00158 /** @defgroup RCC_Private_Functions
00159   * @{
00160   */ 
00161 
00162 /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
00163  *  @brief   Internal and external clocks, PLL, CSS and MCO configuration functions 
00164  *
00165 @verbatim   
00166  ===================================================================================
00167  ##### Internal and  external clocks, PLL, CSS and MCO configuration functions #####
00168  ===================================================================================
00169     [..]
00170       This section provide functions allowing to configure the internal/external clocks,
00171       PLLs, CSS and MCO pins.
00172   
00173       (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
00174           the PLL as System clock source.
00175 
00176       (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
00177           clock source.
00178 
00179       (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
00180           through the PLL as System clock source. Can be used also as RTC clock source.
00181 
00182       (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   
00183 
00184       (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
00185         (++) The first output is used to generate the high speed system clock (up to 168 MHz)
00186         (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
00187              the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
00188 
00189       (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve 
00190           high-quality audio performance on the I2S interface or SAI interface in case 
00191           of STM32F429x/439x devices.
00192      
00193       (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI 
00194           interface and LCD TFT controller available only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
00195   
00196       (#) CSS (Clock security system), once enable and if a HSE clock failure occurs 
00197          (HSE used directly or through PLL as System clock source), the System clock
00198          is automatically switched to HSI and an interrupt is generated if enabled. 
00199          The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) 
00200          exception vector.   
00201 
00202       (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
00203           clock (through a configurable prescaler) on PA8 pin.
00204 
00205       (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
00206           clock (through a configurable prescaler) on PC9 pin.
00207  @endverbatim
00208   * @{
00209   */
00210 
00211 /**
00212   * @brief  Resets the RCC clock configuration to the default reset state.
00213   * @note   The default reset state of the clock configuration is given below:
00214   *            - HSI ON and used as system clock source
00215   *            - HSE, PLL and PLLI2S OFF
00216   *            - AHB, APB1 and APB2 prescaler set to 1.
00217   *            - CSS, MCO1 and MCO2 OFF
00218   *            - All interrupts disabled
00219   * @note   This function doesn't modify the configuration of the
00220   *            - Peripheral clocks  
00221   *            - LSI, LSE and RTC clocks 
00222   * @param  None
00223   * @retval None
00224   */
00225 void RCC_DeInit(void)
00226 {
00227   /* Set HSION bit */
00228   RCC->CR |= (uint32_t)0x00000001;
00229 
00230   /* Reset CFGR register */
00231   RCC->CFGR = 0x00000000;
00232 
00233   /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42xxx/43xxx/446xx/469xx/479xx devices) bits */
00234   RCC->CR &= (uint32_t)0xEAF6FFFF;
00235   
00236   /* Reset PLLCFGR register */
00237   RCC->PLLCFGR = 0x24003010;
00238 
00239 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F413_423xx) || defined(STM32F469_479xx)  
00240   /* Reset PLLI2SCFGR register */
00241   RCC->PLLI2SCFGR = 0x20003000;
00242 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F413_423xx || STM32F469_479xx */
00243 
00244 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 
00245   /* Reset PLLSAICFGR register, only available for STM32F42xxx/43xxx/446xx/469xx/479xx devices */
00246   RCC->PLLSAICFGR = 0x24003000;
00247 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
00248   
00249   /* Reset HSEBYP bit */
00250   RCC->CR &= (uint32_t)0xFFFBFFFF;
00251 
00252   /* Disable all interrupts */
00253   RCC->CIR = 0x00000000;
00254 
00255   /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx and STM32F413_423xx devices */
00256   RCC->DCKCFGR = 0x00000000;
00257   
00258 #if defined(STM32F410xx) || defined(STM32F413_423xx)
00259   /* Disable LPTIM and FMPI2C clock prescalers selection, only available for STM32F410xx and STM32F413_423xx devices */
00260   RCC->DCKCFGR2 = 0x00000000;
00261 #endif /* STM32F410xx || STM32F413_423xx */  
00262 }
00263 
00264 /**
00265   * @brief  Configures the External High Speed oscillator (HSE).
00266   * @note   After enabling the HSE (RCC_HSE_ON_MORT or RCC_HSE_Bypass), the application
00267   *         software should wait on HSERDY flag to be set indicating that HSE clock
00268   *         is stable and can be used to clock the PLL and/or system clock.
00269   * @note   HSE state can not be changed if it is used directly or through the
00270   *         PLL as system clock. In this case, you have to select another source
00271   *         of the system clock then change the HSE state (ex. disable it).
00272   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.  
00273   * @note   This function reset the CSSON bit, so if the Clock security system(CSS)
00274   *         was previously enabled you have to enable it again after calling this
00275   *         function.    
00276   * @param  RCC_HSE: specifies the new state of the HSE.
00277   *          This parameter can be one of the following values:
00278   *            @arg RCC_HSE_OFF_MORT: turn OFF the HSE oscillator, HSERDY flag goes low after
00279   *                              6 HSE oscillator clock cycles.
00280   *            @arg RCC_HSE_ON_MORT: turn ON the HSE oscillator
00281   *            @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
00282   * @retval None
00283   */
00284 void RCC_HSEConfig(uint8_t RCC_HSE)
00285 {
00286   /* Check the parameters */
00287   assert_param(IS_RCC_HSE_MORT(RCC_HSE));
00288 
00289   /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
00290   *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF_MORT;
00291 
00292   /* Set the new HSE configuration -------------------------------------------*/
00293   *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
00294 }
00295 
00296 /**
00297   * @brief  Waits for HSE start-up.
00298   * @note   This functions waits on HSERDY flag to be set and return SUCCESS if 
00299   *         this flag is set, otherwise returns ERROR if the timeout is reached 
00300   *         and this flag is not set. The timeout value is defined by the constant
00301   *         HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
00302   *         on the HSE crystal used in your application. 
00303   * @param  None
00304   * @retval An ErrorStatus enumeration value:
00305   *          - SUCCESS: HSE oscillator is stable and ready to use
00306   *          - ERROR: HSE oscillator not yet ready
00307   */
00308 ErrorStatus RCC_WaitForHSEStartUp(void)
00309 {
00310   __IO uint32_t startupcounter = 0;
00311   ErrorStatus status = ERROR;
00312   FlagStatus hsestatus = RESET;
00313   /* Wait till HSE is ready and if Time out is reached exit */
00314   do
00315   {
00316     hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
00317     startupcounter++;
00318   } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
00319 
00320   if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
00321   {
00322     status = SUCCESS;
00323   }
00324   else
00325   {
00326     status = ERROR;
00327   }
00328   return (status);
00329 }
00330 
00331 /**
00332   * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
00333   * @note   The calibration is used to compensate for the variations in voltage
00334   *         and temperature that influence the frequency of the internal HSI RC.
00335   * @param  HSICalibrationValue: specifies the calibration trimming value.
00336   *         This parameter must be a number between 0 and 0x1F.
00337   * @retval None
00338   */
00339 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
00340 {
00341   uint32_t tmpreg = 0;
00342   /* Check the parameters */
00343   assert_param(IS_RCC_CALIBRATION_VALUE_MORT(HSICalibrationValue));
00344 
00345   tmpreg = RCC->CR;
00346 
00347   /* Clear HSITRIM[4:0] bits */
00348   tmpreg &= ~RCC_CR_HSITRIM_MORT;
00349 
00350   /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
00351   tmpreg |= (uint32_t)HSICalibrationValue << 3;
00352 
00353   /* Store the new value */
00354   RCC->CR = tmpreg;
00355 }
00356 
00357 /**
00358   * @brief  Enables or disables the Internal High Speed oscillator (HSI).
00359   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
00360   *         It is used (enabled by hardware) as system clock source after startup
00361   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
00362   *         of the HSE used directly or indirectly as system clock (if the Clock
00363   *         Security System CSS is enabled).             
00364   * @note   HSI can not be stopped if it is used as system clock source. In this case,
00365   *         you have to select another source of the system clock then stop the HSI.  
00366   * @note   After enabling the HSI, the application software should wait on HSIRDY
00367   *         flag to be set indicating that HSI clock is stable and can be used as
00368   *         system clock source.  
00369   * @param  NewState: new state of the HSI.
00370   *          This parameter can be: ENABLE or DISABLE.
00371   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
00372   *         clock cycles.  
00373   * @retval None
00374   */
00375 void RCC_HSICmd(FunctionalState NewState)
00376 {
00377   /* Check the parameters */
00378   assert_param(IS_FUNCTIONAL_STATE(NewState));
00379 
00380   *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
00381 }
00382 
00383 /**
00384   * @brief  Configures the External Low Speed oscillator (LSE).
00385   * @note   As the LSE is in the Backup domain and write access is denied to
00386   *         this domain after reset, you have to enable write access using 
00387   *         PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
00388   *         (to be done once after reset).  
00389   * @note   After enabling the LSE (RCC_LSE_ON_MORT or RCC_LSE_Bypass), the application
00390   *         software should wait on LSERDY flag to be set indicating that LSE clock
00391   *         is stable and can be used to clock the RTC.
00392   * @param  RCC_LSE: specifies the new state of the LSE.
00393   *          This parameter can be one of the following values:
00394   *            @arg RCC_LSE_OFF_MORT: turn OFF the LSE oscillator, LSERDY flag goes low after
00395   *                              6 LSE oscillator clock cycles.
00396   *            @arg RCC_LSE_ON_MORT: turn ON the LSE oscillator
00397   *            @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
00398   * @retval None
00399   */
00400 void RCC_LSEConfig(uint8_t RCC_LSE)
00401 {
00402   /* Check the parameters */
00403   assert_param(IS_RCC_LSE_MORT(RCC_LSE));
00404 
00405   /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
00406   /* Reset LSEON bit */
00407   *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF_MORT;
00408 
00409   /* Reset LSEBYP bit */
00410   *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF_MORT;
00411 
00412   /* Configure LSE (RCC_LSE_OFF_MORT is already covered by the code section above) */
00413   switch (RCC_LSE)
00414   {
00415     case RCC_LSE_ON_MORT:
00416       /* Set LSEON bit */
00417       *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON_MORT;
00418       break;
00419     case RCC_LSE_Bypass:
00420       /* Set LSEBYP and LSEON bits */
00421       *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON_MORT;
00422       break;
00423     default:
00424       break;
00425   }
00426 }
00427 
00428 /**
00429   * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
00430   * @note   After enabling the LSI, the application software should wait on 
00431   *         LSIRDY flag to be set indicating that LSI clock is stable and can
00432   *         be used to clock the IWDG and/or the RTC.
00433   * @note   LSI can not be disabled if the IWDG is running.  
00434   * @param  NewState: new state of the LSI.
00435   *          This parameter can be: ENABLE or DISABLE.
00436   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
00437   *         clock cycles. 
00438   * @retval None
00439   */
00440 void RCC_LSICmd(FunctionalState NewState)
00441 {
00442   /* Check the parameters */
00443   assert_param(IS_FUNCTIONAL_STATE(NewState));
00444 
00445   *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
00446 }
00447 
00448 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
00449 /**
00450   * @brief  Configures the main PLL clock source, multiplication and division factors.
00451   * @note   This function must be used only when the main PLL is disabled.
00452   *  
00453   * @param  RCC_PLLSource: specifies the PLL entry clock source.
00454   *          This parameter can be one of the following values:
00455   *            @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
00456   *            @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
00457   * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
00458   *  
00459   * @param  PLLM: specifies the division factor for PLL VCO input clock
00460   *          This parameter must be a number between 0 and 63.
00461   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
00462   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
00463   *         of 2 MHz to limit PLL jitter.
00464   *  
00465   * @param  PLLN: specifies the multiplication factor for PLL VCO output clock
00466   *          This parameter must be a number between 50 and 432.
00467   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
00468   *         output frequency is between 100 and 432 MHz.
00469   *   
00470   * @param  PLLP: specifies the division factor for main system clock (SYSCLK)
00471   *          This parameter must be a number in the range {2, 4, 6, or 8}.
00472   * @note   You have to set the PLLP parameter correctly to not exceed 168 MHz on
00473   *         the System clock frequency.
00474   *  
00475   * @param  PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
00476   *          This parameter must be a number between 4 and 15.
00477   *
00478   * @param  PLLR: specifies the division factor for I2S, SAI, SYSTEM, SPDIF in STM32F446xx devices
00479   *          This parameter must be a number between 2 and 7.
00480   *
00481   * @note   If the USB OTG FS is used in your application, you have to set the
00482   *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
00483   *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
00484   *         correctly.
00485   *   
00486   * @retval None
00487   */
00488 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR)
00489 {
00490   /* Check the parameters */
00491   assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
00492   assert_param(IS_RCC_PLLM_VALUE_MORT(PLLM));
00493   assert_param(IS_RCC_PLLN_VALUE(PLLN));
00494   assert_param(IS_RCC_PLLP_VALUE_MORT(PLLP));
00495   assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
00496   assert_param(IS_RCC_PLLR_VALUE_MORT(PLLR));
00497   
00498   RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
00499                  (PLLQ << 24) | (PLLR << 28);
00500 }
00501 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
00502 
00503 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
00504 /**
00505   * @brief  Configures the main PLL clock source, multiplication and division factors.
00506   * @note   This function must be used only when the main PLL is disabled.
00507   *  
00508   * @param  RCC_PLLSource: specifies the PLL entry clock source.
00509   *          This parameter can be one of the following values:
00510   *            @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
00511   *            @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
00512   * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
00513   *  
00514   * @param  PLLM: specifies the division factor for PLL VCO input clock
00515   *          This parameter must be a number between 0 and 63.
00516   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
00517   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
00518   *         of 2 MHz to limit PLL jitter.
00519   *  
00520   * @param  PLLN: specifies the multiplication factor for PLL VCO output clock
00521   *          This parameter must be a number between 50 and 432.
00522   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
00523   *         output frequency is between 100 and 432 MHz.
00524   *   
00525   * @param  PLLP: specifies the division factor for main system clock (SYSCLK)
00526   *          This parameter must be a number in the range {2, 4, 6, or 8}.
00527   * @note   You have to set the PLLP parameter correctly to not exceed 168 MHz on
00528   *         the System clock frequency.
00529   *  
00530   * @param  PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
00531   *          This parameter must be a number between 4 and 15.
00532   * @note   If the USB OTG FS is used in your application, you have to set the
00533   *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
00534   *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
00535   *         correctly.
00536   *   
00537   * @retval None
00538   */
00539 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
00540 {
00541   /* Check the parameters */
00542   assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
00543   assert_param(IS_RCC_PLLM_VALUE_MORT(PLLM));
00544   assert_param(IS_RCC_PLLN_VALUE(PLLN));
00545   assert_param(IS_RCC_PLLP_VALUE_MORT(PLLP));
00546   assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
00547 
00548   RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
00549                  (PLLQ << 24);
00550 }
00551 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
00552 
00553 /**
00554   * @brief  Enables or disables the main PLL.
00555   * @note   After enabling the main PLL, the application software should wait on 
00556   *         PLLRDY flag to be set indicating that PLL clock is stable and can
00557   *         be used as system clock source.
00558   * @note   The main PLL can not be disabled if it is used as system clock source
00559   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
00560   * @param  NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
00561   * @retval None
00562   */
00563 void RCC_PLLCmd(FunctionalState NewState)
00564 {
00565   /* Check the parameters */
00566   assert_param(IS_FUNCTIONAL_STATE(NewState));
00567   *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
00568 }
00569 
00570 #if defined(STM32F40_41xxx) || defined(STM32F401xx)
00571 /**
00572   * @brief  Configures the PLLI2S clock multiplication and division factors.
00573   *  
00574   * @note   This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx 
00575   *         or STM32F401xx devices. 
00576   *    
00577   * @note   This function must be used only when the PLLI2S is disabled.
00578   * @note   PLLI2S clock source is common with the main PLL (configured in 
00579   *         RCC_PLLConfig function )  
00580   *             
00581   * @param  PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
00582   *          This parameter must be a number between 50 and 432.
00583   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
00584   *         output frequency is between 100 and 432 MHz.
00585   *    
00586   * @param  PLLI2SR: specifies the division factor for I2S clock
00587   *          This parameter must be a number between 2 and 7.
00588   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
00589   *         on the I2S clock frequency.
00590   *   
00591   * @retval None
00592   */
00593 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
00594 {
00595   /* Check the parameters */
00596   assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
00597   assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
00598 
00599   RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
00600 }
00601 #endif /* STM32F40_41xxx || STM32F401xx */
00602 
00603 #if defined(STM32F411xE)
00604 /**
00605   * @brief  Configures the PLLI2S clock multiplication and division factors.
00606   *  
00607   * @note   This function can be used only for STM32F411xE devices. 
00608   *    
00609   * @note   This function must be used only when the PLLI2S is disabled.
00610   * @note   PLLI2S clock source is common with the main PLL (configured in 
00611   *         RCC_PLLConfig function )  
00612   *
00613   * @param  PLLI2SM: specifies the division factor for PLLI2S VCO input clock
00614   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
00615   * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
00616   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
00617   *         of 2 MHz to limit PLLI2S jitter.
00618   *
00619   * @param  PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
00620   *          This parameter must be a number between 50 and 432.
00621   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
00622   *         output frequency is between 100 and 432 MHz.
00623   *    
00624   * @param  PLLI2SR: specifies the division factor for I2S clock
00625   *          This parameter must be a number between 2 and 7.
00626   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
00627   *         on the I2S clock frequency.
00628   *   
00629   * @retval None
00630   */
00631 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM)
00632 {
00633   /* Check the parameters */
00634   assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
00635   assert_param(IS_RCC_PLLI2SM_VALUE_MORT(PLLI2SM));
00636   assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
00637 
00638   RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM;
00639 }
00640 #endif /* STM32F411xE */
00641 
00642 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
00643 /**
00644   * @brief  Configures the PLLI2S clock multiplication and division factors.
00645   * 
00646   * @note   This function can be used only for STM32F42xxx/43xxx devices 
00647   *         
00648   * @note   This function must be used only when the PLLI2S is disabled.
00649   * @note   PLLI2S clock source is common with the main PLL (configured in 
00650   *         RCC_PLLConfig function )  
00651   *             
00652   * @param  PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
00653   *          This parameter must be a number between 50 and 432.
00654   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
00655   *         output frequency is between 100 and 432 MHz.
00656   * 
00657   * @param  PLLI2SQ: specifies the division factor for SAI1 clock
00658   *          This parameter must be a number between 2 and 15.
00659   *                 
00660   * @param  PLLI2SR: specifies the division factor for I2S clock
00661   *          This parameter must be a number between 2 and 7.
00662   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
00663   *         on the I2S clock frequency.
00664   *   
00665   * @retval None
00666   */
00667 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR)
00668 {
00669   /* Check the parameters */
00670   assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
00671   assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
00672   assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
00673 
00674   RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28);
00675 }
00676 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
00677 
00678 #if defined(STM32F412xG ) || defined(STM32F413_423xx) || defined(STM32F446xx)
00679 /**
00680   * @brief  Configures the PLLI2S clock multiplication and division factors.
00681   * 
00682   * @note   This function can be used only for STM32F446xx devices 
00683   *         
00684   * @note   This function must be used only when the PLLI2S is disabled.
00685   * @note   PLLI2S clock source is common with the main PLL (configured in 
00686   *         RCC_PLLConfig function )  
00687   * 
00688   * @param  PLLI2SM: specifies the division factor for PLLI2S VCO input clock
00689   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
00690   * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
00691   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
00692   *         of 2 MHz to limit PLLI2S jitter.
00693   *
00694   * @param  PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
00695   *          This parameter must be a number between 50 and 432.
00696   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
00697   *         output frequency is between 100 and 432 MHz.
00698   *
00699   * @param  PLLI2SP: specifies the division factor for PLL 48Mhz clock output
00700   *          This parameter must be a number in the range {2, 4, 6, or 8}.
00701   *
00702   * @param  PLLI2SQ: specifies the division factor for SAI1 clock
00703   *          This parameter must be a number between 2 and 15.
00704   *                 
00705   * @param  PLLI2SR: specifies the division factor for I2S clock
00706   *          This parameter must be a number between 2 and 7.
00707   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
00708   *         on the I2S clock frequency.
00709   * @note   the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices.  
00710   *   
00711   * @retval None
00712   */
00713 void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR)
00714 {
00715   /* Check the parameters */
00716   assert_param(IS_RCC_PLLI2SM_VALUE_MORT(PLLI2SM));
00717   assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
00718   assert_param(IS_RCC_PLLI2SP_VALUE_MORT(PLLI2SP));
00719   assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
00720   assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
00721 
00722   RCC->PLLI2SCFGR =  PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28);
00723 }
00724 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
00725 
00726 /**
00727   * @brief  Enables or disables the PLLI2S. 
00728   * @note   The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.  
00729   * @param  NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
00730   * @retval None
00731   */
00732 void RCC_PLLI2SCmd(FunctionalState NewState)
00733 {
00734   /* Check the parameters */
00735   assert_param(IS_FUNCTIONAL_STATE(NewState));
00736   *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
00737 }
00738 
00739 #if defined(STM32F469_479xx)
00740 /**
00741   * @brief  Configures the PLLSAI clock multiplication and division factors.
00742   *
00743   * @note   This function can be used only for STM32F469_479xx devices 
00744   *        
00745   * @note   This function must be used only when the PLLSAI is disabled.
00746   * @note   PLLSAI clock source is common with the main PLL (configured in 
00747   *         RCC_PLLConfig function )  
00748   *
00749   * @param  PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
00750   *         This parameter must be a number between 50 and 432.
00751   * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
00752   *         output frequency is between 100 and 432 MHz.
00753   *
00754   * @param  PLLSAIP: specifies the division factor for PLL 48Mhz clock output
00755   *         This parameter must be a number in the range {2, 4, 6, or 8}..
00756   *           
00757   * @param  PLLSAIQ: specifies the division factor for SAI1 clock
00758   *         This parameter must be a number between 2 and 15.
00759   *            
00760   * @param  PLLSAIR: specifies the division factor for LTDC clock
00761   *          This parameter must be a number between 2 and 7.
00762   *   
00763   * @retval None
00764   */
00765 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR)
00766 {
00767   /* Check the parameters */
00768   assert_param(IS_RCC_PLLSAIN_VALUE_MORT(PLLSAIN));
00769   assert_param(IS_RCC_PLLSAIP_VALUE_MORT(PLLSAIP));
00770   assert_param(IS_RCC_PLLSAIQ_VALUE_MORT(PLLSAIQ));
00771   assert_param(IS_RCC_PLLSAIR_VALUE_MORT(PLLSAIR));
00772 
00773   RCC->PLLSAICFGR = (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28);
00774 }
00775 #endif /* STM32F469_479xx */
00776 
00777 #if defined(STM32F446xx)
00778 /**
00779   * @brief  Configures the PLLSAI clock multiplication and division factors.
00780   *
00781   * @note   This function can be used only for STM32F446xx devices 
00782   *        
00783   * @note   This function must be used only when the PLLSAI is disabled.
00784   * @note   PLLSAI clock source is common with the main PLL (configured in 
00785   *         RCC_PLLConfig function )  
00786   * 
00787   * @param  PLLSAIM: specifies the division factor for PLLSAI VCO input clock
00788   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
00789   * @note   You have to set the PLLSAIM parameter correctly to ensure that the VCO input
00790   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
00791   *         of 2 MHz to limit PLLSAI jitter.
00792   *
00793   * @param  PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
00794   *         This parameter must be a number between 50 and 432.
00795   * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
00796   *         output frequency is between 100 and 432 MHz.
00797   * 
00798   * @param  PLLSAIP: specifies the division factor for PLL 48Mhz clock output
00799   *         This parameter must be a number in the range {2, 4, 6, or 8}.
00800   *
00801   * @param  PLLSAIQ: specifies the division factor for SAI1 clock
00802   *         This parameter must be a number between 2 and 15.
00803   *   
00804   * @retval None
00805   */
00806 void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ)
00807 {
00808   /* Check the parameters */
00809   assert_param(IS_RCC_PLLSAIM_VALUE_MORT(PLLSAIM));
00810   assert_param(IS_RCC_PLLSAIN_VALUE_MORT(PLLSAIN));
00811   assert_param(IS_RCC_PLLSAIP_VALUE_MORT(PLLSAIP));
00812   assert_param(IS_RCC_PLLSAIQ_VALUE_MORT(PLLSAIQ));
00813 
00814   RCC->PLLSAICFGR = PLLSAIM | (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16)  | (PLLSAIQ << 24);
00815 }
00816 #endif /* STM32F446xx */
00817 
00818 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
00819 /**
00820   * @brief  Configures the PLLSAI clock multiplication and division factors.
00821   *
00822   * @note   This function can be used only for STM32F42xxx/43xxx devices 
00823   *        
00824   * @note   This function must be used only when the PLLSAI is disabled.
00825   * @note   PLLSAI clock source is common with the main PLL (configured in 
00826   *         RCC_PLLConfig function )  
00827   *             
00828   * @param  PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
00829   *          This parameter must be a number between 50 and 432.
00830   * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
00831   *         output frequency is between 100 and 432 MHz.
00832   *           
00833   * @param  PLLSAIQ: specifies the division factor for SAI1 clock
00834   *          This parameter must be a number between 2 and 15.
00835   *            
00836   * @param  PLLSAIR: specifies the division factor for LTDC clock
00837   *          This parameter must be a number between 2 and 7.
00838   *   
00839   * @retval None
00840   */
00841 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
00842 {
00843   /* Check the parameters */
00844   assert_param(IS_RCC_PLLSAIN_VALUE_MORT(PLLSAIN));
00845   assert_param(IS_RCC_PLLSAIR_VALUE_MORT(PLLSAIR));
00846   assert_param(IS_RCC_PLLSAIQ_VALUE_MORT(PLLSAIQ));
00847   
00848   RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28);
00849 }
00850 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
00851 
00852 /**
00853   * @brief  Enables or disables the PLLSAI. 
00854   * 
00855   * @note   This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices 
00856   *       
00857   * @note   The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.  
00858   * @param  NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE.
00859   * @retval None
00860   */
00861 void RCC_PLLSAICmd(FunctionalState NewState)
00862 {
00863   /* Check the parameters */
00864   assert_param(IS_FUNCTIONAL_STATE(NewState));
00865   *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState;
00866 }
00867 
00868 /**
00869   * @brief  Enables or disables the Clock Security System.
00870   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
00871   *         is automatically disabled and an interrupt is generated to inform the
00872   *         software about the failure (Clock Security System Interrupt, CSSI),
00873   *         allowing the MCU to perform rescue operations. The CSSI is linked to 
00874   *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.  
00875   * @param  NewState: new state of the Clock Security System.
00876   *         This parameter can be: ENABLE or DISABLE.
00877   * @retval None
00878   */
00879 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
00880 {
00881   /* Check the parameters */
00882   assert_param(IS_FUNCTIONAL_STATE(NewState));
00883   *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
00884 }
00885 
00886 /**
00887   * @brief  Selects the clock source to output on MCO1 pin(PA8).
00888   * @note   PA8 should be configured in alternate function mode.
00889   * @param  RCC_MCO1Source: specifies the clock source to output.
00890   *          This parameter can be one of the following values:
00891   *            @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
00892   *            @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
00893   *            @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
00894   *            @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
00895   * @param  RCC_MCO1Div: specifies the MCO1 prescaler.
00896   *          This parameter can be one of the following values:
00897   *            @arg RCC_MCO1Div_1: no division applied to MCO1 clock
00898   *            @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
00899   *            @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
00900   *            @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
00901   *            @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
00902   * @retval None
00903   */
00904 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
00905 {
00906   uint32_t tmpreg = 0;
00907   
00908   /* Check the parameters */
00909   assert_param(IS_RCC_MCO1SOURCE_MORT(RCC_MCO1Source));
00910   assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));  
00911 
00912   tmpreg = RCC->CFGR;
00913 
00914   /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
00915   tmpreg &= CFGR_MCO1_RESET_MASK;
00916 
00917   /* Select MCO1 clock source and prescaler */
00918   tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
00919   
00920   /* Store the new value */
00921   RCC->CFGR = tmpreg;
00922 
00923 #if defined(STM32F410xx)
00924   RCC_MCO1Cmd(ENABLE);
00925 #endif /* STM32F410xx */   
00926 }
00927 
00928 /**
00929   * @brief  Selects the clock source to output on MCO2 pin(PC9).
00930   * @note   PC9 should be configured in alternate function mode.
00931   * @param  RCC_MCO2Source: specifies the clock source to output.
00932   *          This parameter can be one of the following values:
00933   *            @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
00934   *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx 
00935   *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410xx devices   
00936   *            @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
00937   *            @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
00938   * @param  RCC_MCO2Div: specifies the MCO2 prescaler.
00939   *          This parameter can be one of the following values:
00940   *            @arg RCC_MCO2Div_1: no division applied to MCO2 clock
00941   *            @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
00942   *            @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
00943   *            @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
00944   *            @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
00945   * @note  For STM32F410xx devices to output I2SCLK clock on MCO2 you should have
00946   *        at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
00947   * @retval None
00948   */
00949 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
00950 {
00951   uint32_t tmpreg = 0;
00952   
00953   /* Check the parameters */
00954   assert_param(IS_RCC_MCO2SOURCE_MORT(RCC_MCO2Source));
00955   assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
00956   
00957   tmpreg = RCC->CFGR;
00958   
00959   /* Clear MCO2 and MCO2PRE[2:0] bits */
00960   tmpreg &= CFGR_MCO2_RESET_MASK;
00961 
00962   /* Select MCO2 clock source and prescaler */
00963   tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
00964   
00965   /* Store the new value */
00966   RCC->CFGR = tmpreg;
00967 
00968 #if defined(STM32F410xx)
00969   RCC_MCO2Cmd(ENABLE);
00970 #endif /* STM32F410xx */   
00971 }
00972 
00973 /**
00974   * @}
00975   */
00976 
00977 /** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
00978  *  @brief   System, AHB and APB busses clocks configuration functions
00979  *
00980 @verbatim   
00981  ===============================================================================
00982       ##### System, AHB and APB busses clocks configuration functions #####
00983  ===============================================================================  
00984     [..]
00985       This section provide functions allowing to configure the System, AHB, APB1 and 
00986       APB2 busses clocks.
00987   
00988       (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
00989           HSE and PLL.
00990           The AHB clock (HCLK) is derived from System clock through configurable 
00991           prescaler and used to clock the CPU, memory and peripherals mapped 
00992           on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived 
00993           from AHB clock through configurable prescalers and used to clock 
00994           the peripherals mapped on these busses. You can use 
00995           "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.  
00996 
00997       -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
00998         (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
00999              from an external clock mapped on the I2S_CKIN pin. 
01000              You have to use RCC_I2SCLKConfig() function to configure this clock. 
01001         (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
01002              divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
01003              functions to configure this clock. 
01004         (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
01005              to work correctly, while the SDIO require a frequency equal or lower than
01006              to 48. This clock is derived of the main PLL through PLLQ divider.
01007         (+@) IWDG clock which is always the LSI clock.
01008        
01009       (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency 
01010          of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending 
01011          on the device voltage range, the maximum frequency should be adapted accordingly:
01012  +-------------------------------------------------------------------------------------+
01013  | Latency       |                HCLK clock frequency (MHz)                           |
01014  |               |---------------------------------------------------------------------|
01015  |               | voltage range  | voltage range  | voltage range   | voltage range   |
01016  |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
01017  |---------------|----------------|----------------|-----------------|-----------------|
01018  |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
01019  |---------------|----------------|----------------|-----------------|-----------------|
01020  |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  |
01021  |---------------|----------------|----------------|-----------------|-----------------|
01022  |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
01023  |---------------|----------------|----------------|-----------------|-----------------|
01024  |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88  |60 < HCLK <= 80  |
01025  |---------------|----------------|----------------|-----------------|-----------------|
01026  |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
01027  |---------------|----------------|----------------|-----------------|-----------------|
01028  |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
01029  |---------------|----------------|----------------|-----------------|-----------------|
01030  |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
01031  |---------------|----------------|----------------|-----------------|-----------------|
01032  |7WS(8CPU cycle)|      NA        |      NA        |154 < HCLK <= 168|140 < HCLK <= 160|
01033  +---------------|----------------|----------------|-----------------|-----------------+
01034       (#) For STM32F42xxx/43xxx/469xx/479xx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, 
01035           PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum 
01036           frequency should be adapted accordingly:
01037  +-------------------------------------------------------------------------------------+
01038  | Latency       |                HCLK clock frequency (MHz)                           |
01039  |               |---------------------------------------------------------------------|
01040  |               | voltage range  | voltage range  | voltage range   | voltage range   |
01041  |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
01042  |---------------|----------------|----------------|-----------------|-----------------|
01043  |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
01044  |---------------|----------------|----------------|-----------------|-----------------|
01045  |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  |
01046  |---------------|----------------|----------------|-----------------|-----------------|
01047  |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
01048  |---------------|----------------|----------------|-----------------|-----------------|
01049  |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88  |60 < HCLK <= 80  |
01050  |---------------|----------------|----------------|-----------------|-----------------|
01051  |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
01052  |---------------|----------------|----------------|-----------------|-----------------|
01053  |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
01054  |---------------|----------------|----------------|-----------------|-----------------|
01055  |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
01056  |---------------|----------------|----------------|-----------------|-----------------|
01057  |7WS(8CPU cycle)|      NA        |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
01058  |---------------|----------------|----------------|-----------------|-----------------|
01059  |8WS(9CPU cycle)|      NA        |      NA        |176 < HCLK <= 180|160 < HCLK <= 168|
01060  +-------------------------------------------------------------------------------------+
01061    
01062       (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz, 
01063           PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum 
01064           frequency should be adapted accordingly:
01065  +-------------------------------------------------------------------------------------+
01066  | Latency       |                HCLK clock frequency (MHz)                           |
01067  |               |---------------------------------------------------------------------|
01068  |               | voltage range  | voltage range  | voltage range   | voltage range   |
01069  |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
01070  |---------------|----------------|----------------|-----------------|-----------------|
01071  |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
01072  |---------------|----------------|----------------|-----------------|-----------------|
01073  |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  |
01074  |---------------|----------------|----------------|-----------------|-----------------|
01075  |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
01076  |---------------|----------------|----------------|-----------------|-----------------|
01077  |3WS(4CPU cycle)|      NA        |72 < HCLK <= 84 |66 < HCLK <= 84  |60 < HCLK <= 80  |
01078  |---------------|----------------|----------------|-----------------|-----------------|
01079  |4WS(5CPU cycle)|      NA        |      NA        |      NA         |80 < HCLK <= 84  |
01080  +-------------------------------------------------------------------------------------+
01081 
01082       (#) For STM32F410xx/STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz, 
01083           PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum 
01084           frequency should be adapted accordingly:
01085  +-------------------------------------------------------------------------------------+
01086  | Latency       |                HCLK clock frequency (MHz)                           |
01087  |               |---------------------------------------------------------------------|
01088  |               | voltage range  | voltage range  | voltage range   | voltage range   |
01089  |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
01090  |---------------|----------------|----------------|-----------------|-----------------|
01091  |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 18   |0 < HCLK <= 16   |
01092  |---------------|----------------|----------------|-----------------|-----------------|
01093  |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36  |16 < HCLK <= 32  |
01094  |---------------|----------------|----------------|-----------------|-----------------|
01095  |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54  |32 < HCLK <= 48  |
01096  |---------------|----------------|----------------|-----------------|-----------------|
01097  |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72  |48 < HCLK <= 64  |
01098  |---------------|----------------|----------------|-----------------|-----------------|
01099  |4WS(5CPU cycle)|      NA        |96 < HCLK <= 100|72 < HCLK <= 90  |64 < HCLK <= 80  |
01100  |---------------|----------------|----------------|-----------------|-----------------|
01101  |5WS(6CPU cycle)|      NA        |       NA       |90 < HCLK <= 100 |80 < HCLK <= 96  |
01102  |---------------|----------------|----------------|-----------------|-----------------|
01103  |6WS(7CPU cycle)|      NA        |       NA       |        NA       |96 < HCLK <= 100 |
01104  +-------------------------------------------------------------------------------------+
01105   
01106       -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: 
01107            (++) when VOS = '0', the maximum value of fHCLK = 144MHz. 
01108            (++) when VOS = '1', the maximum value of fHCLK = 168MHz. 
01109           [..] 
01110           On STM32F42xxx/43xxx/469xx/479xx devices:
01111            (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
01112            (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
01113            (++) when VOS[1:0] = '0x11', the maximum value of f  is 168MHz 
01114           [..]  
01115           On STM32F401x devices:
01116            (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz.
01117            (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz.
01118           On STM32F410xx/STM32F411xE devices:
01119            (++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz.
01120            (++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz.
01121            (++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz.
01122 
01123        You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
01124 
01125 @endverbatim
01126   * @{
01127   */
01128 
01129 /**
01130   * @brief  Configures the system clock (SYSCLK).
01131   * @note   The HSI is used (enabled by hardware) as system clock source after
01132   *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
01133   *         of failure of the HSE used directly or indirectly as system clock
01134   *         (if the Clock Security System CSS is enabled).
01135   * @note   A switch from one clock source to another occurs only if the target
01136   *         clock source is ready (clock stable after startup delay or PLL locked). 
01137   *         If a clock source which is not yet ready is selected, the switch will
01138   *         occur when the clock source will be ready. 
01139   *         You can use RCC_GetSYSCLKSource() function to know which clock is
01140   *         currently used as system clock source. 
01141   * @param  RCC_SYSCLKSource: specifies the clock source used as system clock.
01142   *          This parameter can be one of the following values:
01143   *            @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
01144   *            @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
01145   *            @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices)
01146   *            @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F412xG, STM32F413_423xx and STM32F446xx devices
01147   * @retval None
01148   */
01149 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
01150 {
01151   uint32_t tmpreg = 0;
01152 
01153   /* Check the parameters */
01154   assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
01155 
01156   tmpreg = RCC->CFGR;
01157 
01158   /* Clear SW[1:0] bits */
01159   tmpreg &= ~RCC_CFGR_SW_MORT;
01160 
01161   /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
01162   tmpreg |= RCC_SYSCLKSource;
01163 
01164   /* Store the new value */
01165   RCC->CFGR = tmpreg;
01166 }
01167 
01168 /**
01169   * @brief  Returns the clock source used as system clock.
01170   * @param  None
01171   * @retval The clock source used as system clock. The returned value can be one
01172   *         of the following:
01173   *              - 0x00: HSI used as system clock
01174   *              - 0x04: HSE used as system clock
01175   *              - 0x08: PLL used as system clock (PLL P for STM32F446xx devices)
01176   *              - 0x0C: PLL R used as system clock (only for STM32F412xG, STM32F413_423xx and STM32F446xx devices)
01177   */
01178 uint8_t RCC_GetSYSCLKSource(void)
01179 {
01180   return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS_MORT));
01181 }
01182 
01183 /**
01184   * @brief  Configures the AHB clock (HCLK).
01185   * @note   Depending on the device voltage range, the software has to set correctly
01186   *         these bits to ensure that HCLK not exceed the maximum allowed frequency
01187   *         (for more details refer to section above
01188   *           "CPU, AHB and APB busses clocks configuration functions")
01189   * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
01190   *         the system clock (SYSCLK).
01191   *          This parameter can be one of the following values:
01192   *            @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
01193   *            @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
01194   *            @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
01195   *            @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
01196   *            @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
01197   *            @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
01198   *            @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
01199   *            @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
01200   *            @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
01201   * @retval None
01202   */
01203 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
01204 {
01205   uint32_t tmpreg = 0;
01206   
01207   /* Check the parameters */
01208   assert_param(IS_RCC_HCLK_MORT(RCC_SYSCLK));
01209 
01210   tmpreg = RCC->CFGR;
01211 
01212   /* Clear HPRE[3:0] bits */
01213   tmpreg &= ~RCC_CFGR_HPRE_MORT;
01214 
01215   /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
01216   tmpreg |= RCC_SYSCLK;
01217 
01218   /* Store the new value */
01219   RCC->CFGR = tmpreg;
01220 }
01221 
01222 /**
01223   * @brief  Configures the Low Speed APB clock (PCLK1).
01224   * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from 
01225   *         the AHB clock (HCLK).
01226   *          This parameter can be one of the following values:
01227   *            @arg RCC_HCLK_Div1:  APB1 clock = HCLK
01228   *            @arg RCC_HCLK_Div2:  APB1 clock = HCLK/2
01229   *            @arg RCC_HCLK_Div4:  APB1 clock = HCLK/4
01230   *            @arg RCC_HCLK_Div8:  APB1 clock = HCLK/8
01231   *            @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
01232   * @retval None
01233   */
01234 void RCC_PCLK1Config(uint32_t RCC_HCLK)
01235 {
01236   uint32_t tmpreg = 0;
01237 
01238   /* Check the parameters */
01239   assert_param(IS_RCC_PCLK_MORT(RCC_HCLK));
01240 
01241   tmpreg = RCC->CFGR;
01242 
01243   /* Clear PPRE1[2:0] bits */
01244   tmpreg &= ~RCC_CFGR_PPRE1_MORT;
01245 
01246   /* Set PPRE1[2:0] bits according to RCC_HCLK value */
01247   tmpreg |= RCC_HCLK;
01248 
01249   /* Store the new value */
01250   RCC->CFGR = tmpreg;
01251 }
01252 
01253 /**
01254   * @brief  Configures the High Speed APB clock (PCLK2).
01255   * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from 
01256   *         the AHB clock (HCLK).
01257   *          This parameter can be one of the following values:
01258   *            @arg RCC_HCLK_Div1:  APB2 clock = HCLK
01259   *            @arg RCC_HCLK_Div2:  APB2 clock = HCLK/2
01260   *            @arg RCC_HCLK_Div4:  APB2 clock = HCLK/4
01261   *            @arg RCC_HCLK_Div8:  APB2 clock = HCLK/8
01262   *            @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
01263   * @retval None
01264   */
01265 void RCC_PCLK2Config(uint32_t RCC_HCLK)
01266 {
01267   uint32_t tmpreg = 0;
01268 
01269   /* Check the parameters */
01270   assert_param(IS_RCC_PCLK_MORT(RCC_HCLK));
01271 
01272   tmpreg = RCC->CFGR;
01273 
01274   /* Clear PPRE2[2:0] bits */
01275   tmpreg &= ~RCC_CFGR_PPRE2_MORT;
01276 
01277   /* Set PPRE2[2:0] bits according to RCC_HCLK value */
01278   tmpreg |= RCC_HCLK << 3;
01279 
01280   /* Store the new value */
01281   RCC->CFGR = tmpreg;
01282 }
01283 
01284 /**
01285   * @brief  Returns the frequencies of different on chip clocks; SYSCLK, HCLK, 
01286   *         PCLK1 and PCLK2.
01287   * 
01288   * @note   The system frequency computed by this function is not the real 
01289   *         frequency in the chip. It is calculated based on the predefined 
01290   *         constant and the selected clock source:
01291   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
01292   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
01293   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) 
01294   *           or HSI_VALUE(*) multiplied/divided by the PLL factors.         
01295   * @note     (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
01296   *               16 MHz) but the real value may vary depending on the variations
01297   *               in voltage and temperature.
01298   * @note     (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
01299   *                25 MHz), user has to ensure that HSE_VALUE is same as the real
01300   *                frequency of the crystal used. Otherwise, this function may
01301   *                have wrong result.
01302   *                
01303   * @note   The result of this function could be not correct when using fractional
01304   *         value for HSE crystal.
01305   *   
01306   * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
01307   *          the clocks frequencies.
01308   *     
01309   * @note   This function can be used by the user application to compute the 
01310   *         baudrate for the communication peripherals or configure other parameters.
01311   * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
01312   *         must be called to update the structure's field. Otherwise, any
01313   *         configuration based on this function will be incorrect.
01314   *    
01315   * @retval None
01316   */
01317 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
01318 {
01319   uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
01320 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)  
01321   uint32_t pllr = 2;
01322 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
01323   
01324   /* Get SYSCLK source -------------------------------------------------------*/
01325   tmp = RCC->CFGR & RCC_CFGR_SWS_MORT;
01326   
01327   switch (tmp)
01328   {
01329   case 0x00:  /* HSI used as system clock source */
01330     RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
01331     break;
01332   case 0x04:  /* HSE used as system clock  source */
01333     RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
01334     break;
01335   case 0x08:  /* PLL P used as system clock  source */
01336     
01337     /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
01338     SYSCLK = PLL_VCO / PLLP
01339     */    
01340     pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC_MORT) >> 22;
01341     pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM_MORT;
01342     
01343     if (pllsource != 0)
01344     {
01345       /* HSE used as PLL clock source */
01346       pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);
01347     }
01348     else
01349     {
01350       /* HSI used as PLL clock source */
01351       pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);      
01352     }
01353     
01354     pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP_MORT) >>16) + 1 ) *2;
01355     RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
01356     break;
01357 
01358 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
01359   case 0x0C:  /* PLL R used as system clock  source */
01360     /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
01361     SYSCLK = PLL_VCO / PLLR
01362     */    
01363     pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC_MORT) >> 22;
01364     pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM_MORT;
01365     
01366     if (pllsource != 0)
01367     {
01368       /* HSE used as PLL clock source */
01369       pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);
01370     }
01371     else
01372     {
01373       /* HSI used as PLL clock source */
01374       pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);      
01375     }
01376     
01377     pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR_MORT) >>28) + 1 ) *2;
01378     RCC_Clocks->SYSCLK_Frequency = pllvco/pllr;    
01379     break;
01380 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
01381     
01382   default:
01383     RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
01384     break;
01385   }
01386   /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
01387   
01388   /* Get HCLK prescaler */
01389   tmp = RCC->CFGR & RCC_CFGR_HPRE_MORT;
01390   tmp = tmp >> 4;
01391   presc = APBAHBPrescTable[tmp];
01392   /* HCLK clock frequency */
01393   RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
01394 
01395   /* Get PCLK1 prescaler */
01396   tmp = RCC->CFGR & RCC_CFGR_PPRE1_MORT;
01397   tmp = tmp >> 10;
01398   presc = APBAHBPrescTable[tmp];
01399   /* PCLK1 clock frequency */
01400   RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
01401 
01402   /* Get PCLK2 prescaler */
01403   tmp = RCC->CFGR & RCC_CFGR_PPRE2_MORT;
01404   tmp = tmp >> 13;
01405   presc = APBAHBPrescTable[tmp];
01406   /* PCLK2 clock frequency */
01407   RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
01408 }
01409 
01410 /**
01411   * @}
01412   */
01413 
01414 /** @defgroup RCC_Group3 Peripheral clocks configuration functions
01415  *  @brief   Peripheral clocks configuration functions 
01416  *
01417 @verbatim   
01418  ===============================================================================
01419               ##### Peripheral clocks configuration functions #####
01420  ===============================================================================  
01421     [..] This section provide functions allowing to configure the Peripheral clocks. 
01422   
01423       (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided 
01424           by 2 to 31.
01425      
01426       (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
01427           except internal SRAM, Flash and JTAG. Before to start using a peripheral 
01428           you have to enable its interface clock. You can do this using 
01429           RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
01430 
01431       (#) To reset the peripherals configuration (to the default state after device reset)
01432           you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and 
01433           RCC_APB1PeriphResetCmd() functions.
01434      
01435       (#) To further reduce power consumption in SLEEP mode the peripheral clocks 
01436           can be disabled prior to executing the WFI or WFE instructions. 
01437           You can do this using RCC_AHBPeriphClockLPModeCmd(), 
01438           RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.  
01439 
01440 @endverbatim
01441   * @{
01442   */
01443 
01444 /**
01445   * @brief  Configures the RTC clock (RTCCLK).
01446   * @note   As the RTC clock configuration bits are in the Backup domain and write
01447   *         access is denied to this domain after reset, you have to enable write
01448   *         access using PWR_BackupAccessCmd(ENABLE) function before to configure
01449   *         the RTC clock source (to be done once after reset).    
01450   * @note   Once the RTC clock is configured it can't be changed unless the  
01451   *         Backup domain is reset using RCC_BackupResetCmd() function, or by
01452   *         a Power On Reset (POR).
01453   *    
01454   * @param  RCC_RTCCLKSource: specifies the RTC clock source.
01455   *          This parameter can be one of the following values:
01456   *            @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
01457   *            @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
01458   *            @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
01459   *                                            as RTC clock, where x:[2,31]
01460   *  
01461   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
01462   *         work in STOP and STANDBY modes, and can be used as wakeup source.
01463   *         However, when the HSE clock is used as RTC clock source, the RTC
01464   *         cannot be used in STOP and STANDBY modes.    
01465   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
01466   *         RTC clock source).
01467   *  
01468   * @retval None
01469   */
01470 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
01471 {
01472   uint32_t tmpreg = 0;
01473 
01474   /* Check the parameters */
01475   assert_param(IS_RCC_RTCCLK_SOURCE_MORT(RCC_RTCCLKSource));
01476 
01477   if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
01478   { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
01479     tmpreg = RCC->CFGR;
01480 
01481     /* Clear RTCPRE[4:0] bits */
01482     tmpreg &= ~RCC_CFGR_RTCPRE_MORT;
01483 
01484     /* Configure HSE division factor for RTC clock */
01485     tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
01486 
01487     /* Store the new value */
01488     RCC->CFGR = tmpreg;
01489   }
01490     
01491   /* Select the RTC clock source */
01492   RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
01493 }
01494 
01495 /**
01496   * @brief  Enables or disables the RTC clock.
01497   * @note   This function must be used only after the RTC clock source was selected
01498   *         using the RCC_RTCCLKConfig function.
01499   * @param  NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
01500   * @retval None
01501   */
01502 void RCC_RTCCLKCmd(FunctionalState NewState)
01503 {
01504   /* Check the parameters */
01505   assert_param(IS_FUNCTIONAL_STATE(NewState));
01506 
01507   *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
01508 }
01509 
01510 /**
01511   * @brief  Forces or releases the Backup domain reset.
01512   * @note   This function resets the RTC peripheral (including the backup registers)
01513   *         and the RTC clock source selection in RCC_CSR register.
01514   * @note   The BKPSRAM is not affected by this reset.    
01515   * @param  NewState: new state of the Backup domain reset.
01516   *          This parameter can be: ENABLE or DISABLE.
01517   * @retval None
01518   */
01519 void RCC_BackupResetCmd(FunctionalState NewState)
01520 {
01521   /* Check the parameters */
01522   assert_param(IS_FUNCTIONAL_STATE(NewState));
01523   *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
01524 }
01525 
01526 #if defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
01527 /**
01528   * @brief  Configures the I2S clock source (I2SCLK).
01529   * @note   This function must be called before enabling the I2S APB clock.
01530   *
01531   * @param  RCC_I2SAPBx: specifies the APBx I2S clock source.
01532   *          This parameter can be one of the following values:
01533   *            @arg RCC_I2SBus_APB1: I2S peripheral instance is on APB1 Bus
01534   *            @arg RCC_I2SBus_APB2: I2S peripheral instance is on APB2 Bus
01535   *
01536   * @param  RCC_I2SCLKSource: specifies the I2S clock source.
01537   *          This parameter can be one of the following values:
01538   *            @arg RCC_I2SCLKSource_PLLI2S: PLLI2S clock used as I2S clock source
01539   *            @arg RCC_I2SCLKSource_Ext: External clock mapped on the I2S_CKIN pin
01540   *                                        used as I2S clock source
01541   *            @arg RCC_I2SCLKSource_PLL: PLL clock used as I2S clock source
01542   *            @arg RCC_I2SCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as I2S clock source
01543   * @retval None
01544   */
01545 void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource)
01546 {
01547   /* Check the parameters */
01548   assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
01549   assert_param(IS_RCC_I2S_APBx(RCC_I2SAPBx));
01550   
01551   if(RCC_I2SAPBx == RCC_I2SBus_APB1)
01552   {
01553     /* Clear APB1 I2Sx clock source selection bits */
01554     RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S1SRC_MORT;
01555     /* Set new APB1 I2Sx clock source*/
01556     RCC->DCKCFGR |= RCC_I2SCLKSource;
01557   }
01558   else
01559   {
01560     /* Clear APB2 I2Sx clock source selection  bits */
01561     RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S2SRC_MORT;
01562     /* Set new APB2 I2Sx clock source */
01563     RCC->DCKCFGR |= (RCC_I2SCLKSource << 2);
01564   }
01565 }
01566 #if defined(STM32F446xx)
01567 /**
01568   * @brief  Configures the SAIx clock source (SAIxCLK).
01569   * @note   This function must be called before enabling the SAIx APB clock.
01570   *
01571   * @param  RCC_SAIInstance: specifies the SAIx clock source.
01572   *          This parameter can be one of the following values:
01573   *            @arg RCC_SAIInstance_SAI1: SAI1 clock source selection
01574   *            @arg RCC_SAIInstance_SAI2: SAI2 clock source selections
01575   *
01576   * @param  RCC_SAICLKSource: specifies the SAI clock source.
01577   *          This parameter can be one of the following values:
01578   *            @arg RCC_SAICLKSource_PLLSAI: PLLSAI clock used as SAI clock source
01579   *            @arg RCC_SAICLKSource_PLLI2S: PLLI2S clock used as SAI clock source
01580   *            @arg RCC_SAICLKSource_PLL: PLL clock used as SAI clock source
01581   *            @arg RCC_SAICLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
01582   * @retval None
01583   */
01584 void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource)
01585 {
01586   /* Check the parameters */
01587   assert_param(IS_RCC_SAICLK_SOURCE(RCC_SAICLKSource));
01588   assert_param(IS_RCC_SAI_INSTANCE(RCC_SAIInstance));
01589   
01590   if(RCC_SAIInstance == RCC_SAIInstance_SAI1)
01591   {
01592     /* Clear SAI1 clock source selection bits */
01593     RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI1SRC_MORT;
01594     /* Set new SAI1 clock source */
01595     RCC->DCKCFGR |= RCC_SAICLKSource;
01596   }
01597   else
01598   {
01599     /* Clear SAI2 clock source selection bits */
01600     RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI2SRC_MORT;
01601     /* Set new SAI2 clock source */
01602     RCC->DCKCFGR |= (RCC_SAICLKSource << 2);
01603   }
01604 }
01605 #endif /* STM32F446xx */
01606 
01607 #if defined(STM32F413_423xx)
01608 /**
01609   * @brief  Configures SAI1BlockA clock source selection.      
01610   * @note   This function must be called before enabling PLLSAI, PLLI2S and  
01611   *         the SAI clock.
01612   * @param  RCC_SAIBlockACLKSource: specifies the SAI Block A clock source.
01613   *          This parameter can be one of the following values:
01614   *            @arg RCC_SAIACLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source
01615   *            @arg RCC_SAIACLKSource_PLLI2S: PLLI2S clock used as SAI clock source
01616   *            @arg RCC_SAIACLKSource_PLL: PLL clock used as SAI clock source
01617   *            @arg RCC_SAIACLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
01618   * @retval None
01619   */
01620 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
01621 {
01622   uint32_t tmpreg = 0;
01623   
01624   /* Check the parameters */
01625   assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
01626   
01627   tmpreg = RCC->DCKCFGR;
01628 
01629   /* Clear RCC_DCKCFGR_SAI1ASRC_MORT[1:0] bits */
01630   tmpreg &= ~RCC_DCKCFGR_SAI1ASRC_MORT;
01631 
01632   /* Set SAI Block A source selection value */
01633   tmpreg |= RCC_SAIBlockACLKSource;
01634 
01635   /* Store the new value */
01636   RCC->DCKCFGR = tmpreg;
01637 }
01638 
01639 /**
01640   * @brief  Configures SAI1BlockB clock source selection.      
01641   * @note   This function must be called before enabling PLLSAI, PLLI2S and  
01642   *         the SAI clock.
01643   * @param  RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source.
01644   *          This parameter can be one of the following values:
01645   *            @arg RCC_SAIBCLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source
01646   *            @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S clock used as SAI clock source
01647   *            @arg RCC_SAIBCLKSource_PLL: PLL clock used as SAI clock source
01648   *            @arg RCC_SAIBCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
01649   * @retval None
01650   */
01651 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
01652 {
01653   uint32_t tmpreg = 0;
01654   
01655   /* Check the parameters */
01656   assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
01657   
01658   tmpreg = RCC->DCKCFGR;
01659 
01660   /* Clear RCC_DCKCFGR_SAI1ASRC_MORT[1:0] bits */
01661   tmpreg &= ~RCC_DCKCFGR_SAI1BSRC_MORT;
01662 
01663   /* Set SAI Block B source selection value */
01664   tmpreg |= RCC_SAIBlockBCLKSource;
01665 
01666   /* Store the new value */
01667   RCC->DCKCFGR = tmpreg;
01668 }
01669 #endif /* STM32F413_423xx */
01670 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
01671 
01672 #if defined(STM32F410xx)
01673 /**
01674   * @brief  Configures the I2S clock source (I2SCLK).
01675   * @note   This function must be called before enabling the I2S clock.
01676   *
01677   * @param  RCC_I2SCLKSource: specifies the I2S clock source.
01678   *         This parameter can be one of the following values:
01679   *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
01680   *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
01681   *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
01682   * @retval None
01683   */
01684 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
01685 {
01686   /* Check the parameters */
01687   assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
01688   
01689   /* Clear I2Sx clock source selection bits */
01690   RCC->DCKCFGR &= ~RCC_DCKCFGR_I2SSRC;
01691   /* Set new I2Sx clock source*/
01692   RCC->DCKCFGR |= RCC_I2SCLKSource;
01693 }
01694 #endif /* STM32F410xx */
01695 
01696 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
01697 /**
01698   * @brief  Configures the I2S clock source (I2SCLK).
01699   * @note   This function must be called before enabling the I2S APB clock.
01700   * @param  RCC_I2SCLKSource: specifies the I2S clock source.
01701   *          This parameter can be one of the following values:
01702   *            @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
01703   *            @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
01704   *                                        used as I2S clock source
01705   * @retval None
01706   */
01707 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
01708 {
01709   /* Check the parameters */
01710   assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
01711 
01712   *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;  
01713 }
01714 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
01715 
01716 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
01717 /**
01718   * @brief  Configures SAI1BlockA clock source selection.
01719   * 
01720   * @note   This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
01721   *       
01722   * @note   This function must be called before enabling PLLSAI, PLLI2S and  
01723   *         the SAI clock.
01724   * @param  RCC_SAIBlockACLKSource: specifies the SAI Block A clock source.
01725   *          This parameter can be one of the following values:
01726   *            @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
01727   *                                           as SAI1 Block A clock 
01728   *            @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
01729   *                                           as SAI1 Block A clock 
01730   *            @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin
01731   *                                        used as SAI1 Block A clock
01732   * @retval None
01733   */
01734 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
01735 {
01736   uint32_t tmpreg = 0;
01737   
01738   /* Check the parameters */
01739   assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
01740   
01741   tmpreg = RCC->DCKCFGR;
01742 
01743   /* Clear RCC_DCKCFGR_SAI1ASRC_MORT[1:0] bits */
01744   tmpreg &= ~RCC_DCKCFGR_SAI1ASRC_MORT;
01745 
01746   /* Set SAI Block A source selection value */
01747   tmpreg |= RCC_SAIBlockACLKSource;
01748 
01749   /* Store the new value */
01750   RCC->DCKCFGR = tmpreg;
01751 }
01752 
01753 /**
01754   * @brief  Configures SAI1BlockB clock source selection.
01755   * 
01756   * @note   This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
01757   *       
01758   * @note   This function must be called before enabling PLLSAI, PLLI2S and  
01759   *         the SAI clock.
01760   * @param  RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source.
01761   *          This parameter can be one of the following values:
01762   *            @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
01763   *                                           as SAI1 Block B clock 
01764   *            @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
01765   *                                           as SAI1 Block B clock 
01766   *            @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin
01767   *                                        used as SAI1 Block B clock
01768   * @retval None
01769   */
01770 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
01771 {
01772   uint32_t tmpreg = 0;
01773   
01774   /* Check the parameters */
01775   assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
01776   
01777   tmpreg = RCC->DCKCFGR;
01778 
01779   /* Clear RCC_DCKCFGR_SAI1BSRC_MORT[1:0] bits */
01780   tmpreg &= ~RCC_DCKCFGR_SAI1BSRC_MORT;
01781 
01782   /* Set SAI Block B source selection value */
01783   tmpreg |= RCC_SAIBlockBCLKSource;
01784 
01785   /* Store the new value */
01786   RCC->DCKCFGR = tmpreg;
01787 }
01788 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
01789 
01790 /**
01791   * @brief  Configures the SAI clock Divider coming from PLLI2S.
01792   * 
01793   * @note   This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
01794   *   
01795   * @note   This function must be called before enabling the PLLI2S.
01796   *              
01797   * @param  RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock .
01798   *          This parameter must be a number between 1 and 32.
01799   *          SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ 
01800   *              
01801   * @retval None
01802   */
01803 void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)  
01804 {
01805   uint32_t tmpreg = 0;
01806   
01807   /* Check the parameters */
01808   assert_param(IS_RCC_PLLI2S_DIVQ_VALUE_MORT(RCC_PLLI2SDivQ));
01809   
01810   tmpreg = RCC->DCKCFGR;
01811 
01812   /* Clear PLLI2SDIVQ[4:0] bits */
01813   tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ_MORT);
01814 
01815   /* Set PLLI2SDIVQ values */
01816   tmpreg |= (RCC_PLLI2SDivQ - 1);
01817 
01818   /* Store the new value */
01819   RCC->DCKCFGR = tmpreg;
01820 }
01821 
01822 /**
01823   * @brief  Configures the SAI clock Divider coming from PLLSAI.
01824   * 
01825   * @note   This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
01826   *        
01827   * @note   This function must be called before enabling the PLLSAI.
01828   *   
01829   * @param  RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock .
01830   *          This parameter must be a number between 1 and 32.
01831   *          SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ  
01832   *              
01833   * @retval None
01834   */
01835 void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)  
01836 {
01837   uint32_t tmpreg = 0;
01838   
01839   /* Check the parameters */
01840   assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ));
01841   
01842   tmpreg = RCC->DCKCFGR;
01843 
01844   /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */
01845   tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ_MORT);
01846 
01847   /* Set PLLSAIDIVQ values */
01848   tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8);
01849 
01850   /* Store the new value */
01851   RCC->DCKCFGR = tmpreg;
01852 }
01853 
01854 #if defined(STM32F413_423xx)
01855 /**
01856   * @brief  Configures the SAI clock Divider coming from PLLI2S.
01857   * 
01858   * @note   This function can be used only for STM32F413_423xx
01859   *   
01860   * @param   RCC_PLLI2SDivR: specifies the PLLI2S division factor for SAI1 clock.
01861   *          This parameter must be a number between 1 and 32.
01862   *          SAI1 clock frequency = f(PLLI2SR) / RCC_PLLI2SDivR 
01863   * @retval None
01864   */
01865 void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR)  
01866 {
01867   uint32_t tmpreg = 0;
01868   
01869   /* Check the parameters */
01870   assert_param(IS_RCC_PLLI2S_DIVR_VALUE(RCC_PLLI2SDivR));
01871   
01872   tmpreg = RCC->DCKCFGR;
01873 
01874   /* Clear PLLI2SDIVR[4:0] bits */
01875   tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVR);
01876 
01877   /* Set PLLI2SDIVR values */
01878   tmpreg |= (RCC_PLLI2SDivR-1);
01879 
01880   /* Store the new value */
01881   RCC->DCKCFGR = tmpreg;
01882 }
01883 
01884 /**
01885   * @brief  Configures the SAI clock Divider coming from PLL.
01886   * 
01887   * @note   This function can be used only for STM32F413_423xx
01888   *        
01889   * @note   This function must be called before enabling the PLLSAI.
01890   *   
01891   * @param  RCC_PLLDivR: specifies the PLL division factor for SAI1 clock.
01892   *          This parameter must be a number between 1 and 32.
01893   *          SAI1 clock frequency = f(PLLR) / RCC_PLLDivR 
01894   *              
01895   * @retval None
01896   */
01897 void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR)  
01898 {
01899   uint32_t tmpreg = 0;
01900   
01901   /* Check the parameters */
01902   assert_param(IS_RCC_PLL_DIVR_VALUE(RCC_PLLDivR));
01903   
01904   tmpreg = RCC->DCKCFGR;
01905 
01906   /* Clear PLLDIVR[12:8] */
01907   tmpreg &= ~(RCC_DCKCFGR_PLLDIVR);
01908 
01909   /* Set PLLDivR values */
01910   tmpreg |= ((RCC_PLLDivR - 1 ) << 8);
01911 
01912   /* Store the new value */
01913   RCC->DCKCFGR = tmpreg;
01914 }
01915 #endif /* STM32F413_423xx */
01916 
01917 /**
01918   * @brief  Configures the LTDC clock Divider coming from PLLSAI.
01919   * 
01920   * @note   The LTDC peripheral is only available with STM32F42xxx/43xxx/446xx/469xx/479xx Devices.
01921   *      
01922   * @note   This function must be called before enabling the PLLSAI.
01923   *   
01924   * @param  RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock .
01925   *          LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR  
01926   *          This parameter can be one of the following values:
01927   *            @arg RCC_PLLSAIDivR_Div2: LTDC clock = f(PLLSAI_R)/2
01928   *            @arg RCC_PLLSAIDivR_Div4: LTDC clock = f(PLLSAI_R)/4
01929   *            @arg RCC_PLLSAIDivR_Div8: LTDC clock = f(PLLSAI_R)/8
01930   *            @arg RCC_PLLSAIDivR_Div16: LTDC clock = f(PLLSAI_R)/16
01931   *            
01932   * @retval None
01933   */
01934 void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
01935 {
01936   uint32_t tmpreg = 0;
01937   
01938   /* Check the parameters */
01939   assert_param(IS_RCC_PLLSAI_DIVR_VALUE_MORT(RCC_PLLSAIDivR));
01940   
01941   tmpreg = RCC->DCKCFGR;
01942 
01943   /* Clear PLLSAIDIVR[2:0] bits */
01944   tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR_MORT;
01945 
01946   /* Set PLLSAIDIVR values */
01947   tmpreg |= RCC_PLLSAIDivR;
01948 
01949   /* Store the new value */
01950   RCC->DCKCFGR = tmpreg;
01951 }
01952 
01953 #if defined(STM32F412xG) || defined(STM32F413_423xx)
01954 /**
01955   * @brief  Configures the DFSDM clock source (DFSDMCLK).
01956   * @note   This function must be called before enabling the DFSDM APB clock.
01957   * @param  RCC_DFSDMCLKSource: specifies the DFSDM clock source.
01958   *          This parameter can be one of the following values:
01959   *            @arg RCC_DFSDMCLKSource_APB: APB clock used as DFSDM clock source.
01960   *            @arg RCC_DFSDMCLKSource_SYS: System clock used as DFSDM clock source.
01961   *                                        
01962   * @retval None
01963   */
01964 void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDMCLKSource)
01965 {
01966   uint32_t tmpreg = 0;
01967   
01968   /* Check the parameters */
01969   assert_param(IS_RCC_DFSDM1CLK_SOURCE(RCC_DFSDMCLKSource));
01970   
01971   tmpreg = RCC->DCKCFGR;
01972 
01973   /* Clear CKDFSDM-SEL  bit */
01974   tmpreg &= ~RCC_DCKCFGR_CKDFSDM1SEL;
01975 
01976   /* Set CKDFSDM-SEL bit according to RCC_DFSDMCLKSource value */
01977   tmpreg |= (RCC_DFSDMCLKSource << 31) ;
01978 
01979   /* Store the new value */
01980   RCC->DCKCFGR = tmpreg;
01981 }
01982 
01983 /**
01984   * @brief  Configures the DFSDM Audio clock source (DFSDMACLK).
01985   * @note   This function must be called before enabling the DFSDM APB clock.
01986   * @param  RCC_DFSDM1ACLKSource: specifies the DFSDM clock source.
01987   *          This parameter can be one of the following values:
01988   *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
01989   *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
01990   *                                        
01991   * @retval None
01992   */
01993 void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource)
01994 {
01995   uint32_t tmpreg = 0;
01996   
01997   /* Check the parameters */
01998   assert_param(IS_RCC_DFSDMACLK_SOURCE(RCC_DFSDM1ACLKSource));
01999   
02000   tmpreg = RCC->DCKCFGR;
02001 
02002   /* Clear CKDFSDMA SEL  bit */
02003   tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
02004 
02005   /* Set CKDFSDM-SEL   bt according to RCC_DFSDMCLKSource value */
02006   tmpreg |= RCC_DFSDM1ACLKSource;
02007 
02008   /* Store the new value */
02009   RCC->DCKCFGR = tmpreg;
02010 }
02011 
02012 #if defined(STM32F413_423xx)
02013 /**
02014   * @brief  Configures the DFSDM Audio clock source (DFSDMACLK).
02015   * @note   This function must be called before enabling the DFSDM APB clock.
02016   * @param  RCC_DFSDM2ACLKSource: specifies the DFSDM clock source.
02017   *          This parameter can be one of the following values:
02018   *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
02019   *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
02020   *                                        
02021   * @retval None
02022   */
02023 void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource)
02024 {
02025   uint32_t tmpreg = 0;
02026   
02027   /* Check the parameters */
02028   assert_param(IS_RCC_DFSDMCLK_SOURCE(RCC_DFSDMACLKSource));
02029   
02030   tmpreg = RCC->DCKCFGR;
02031 
02032   /* Clear CKDFSDMA SEL  bit */
02033   tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
02034 
02035   /* Set CKDFSDM-SEL   bt according to RCC_DFSDMCLKSource value */
02036   tmpreg |= RCC_DFSDMACLKSource;
02037 
02038   /* Store the new value */
02039   RCC->DCKCFGR = tmpreg;
02040 }
02041 #endif /* STM32F413_423xx */
02042 #endif /* STM32F412xG || STM32F413_423xx */
02043 
02044 /**
02045   * @brief  Configures the Timers clocks prescalers selection.
02046   * 
02047   * @note   This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. 
02048   *   
02049   * @param  RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection
02050   *         This parameter can be one of the following values:
02051   *            @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is 
02052   *                 equal to HPRE if PPREx is corresponding to division by 1 or 2, 
02053   *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 
02054   *                 division by 4 or more.
02055   *                   
02056   *            @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is 
02057   *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 
02058   *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 
02059   *                 to division by 8 or more.
02060   * @retval None
02061   */
02062 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
02063 {
02064   /* Check the parameters */
02065   assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
02066 
02067   *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
02068 }
02069 
02070 /**
02071   * @brief  Enables or disables the AHB1 peripheral clock.
02072   * @note   After reset, the peripheral clock (used for registers read/write access)
02073   *         is disabled and the application software has to enable this clock before 
02074   *         using it.   
02075   * @param  RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
02076   *          This parameter can be any combination of the following values:
02077   *            @arg RCC_AHB1Periph_GPIOA:       GPIOA clock
02078   *            @arg RCC_AHB1Periph_GPIOB:       GPIOB clock 
02079   *            @arg RCC_AHB1Periph_GPIOC:       GPIOC clock
02080   *            @arg RCC_AHB1Periph_GPIOD:       GPIOD clock
02081   *            @arg RCC_AHB1Periph_GPIOE:       GPIOE clock
02082   *            @arg RCC_AHB1Periph_GPIOF:       GPIOF clock
02083   *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
02084   *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
02085   *            @arg RCC_AHB1Periph_GPIOI:       GPIOI clock
02086   *            @arg RCC_AHB1Periph_GPIOJ:       GPIOJ clock (STM32F42xxx/43xxx devices) 
02087   *            @arg RCC_AHB1Periph_GPIOK:       GPIOK clock (STM32F42xxx/43xxx devices)  
02088   *            @arg RCC_AHB1Periph_CRC:         CRC clock
02089   *            @arg RCC_AHB1Periph_BKPSRAM:     BKPSRAM interface clock
02090   *            @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
02091   *            @arg RCC_AHB1Periph_DMA1:        DMA1_MORT clock
02092   *            @arg RCC_AHB1Periph_DMA2:        DMA2_MORT clock
02093   *            @arg RCC_AHB1Periph_DMA2D:       DMA2D clock (STM32F429xx/439xx devices)  
02094   *            @arg RCC_AHB1Periph_ETH_MAC:     Ethernet MAC clock
02095   *            @arg RCC_AHB1Periph_ETH_MAC_Tx:  Ethernet Transmission clock
02096   *            @arg RCC_AHB1Periph_ETH_MAC_Rx:  Ethernet Reception clock
02097   *            @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
02098   *            @arg RCC_AHB1Periph_OTG_HS:      USB OTG HS clock
02099   *            @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
02100   * @param  NewState: new state of the specified peripheral clock.
02101   *          This parameter can be: ENABLE or DISABLE.
02102   * @retval None
02103   */
02104 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
02105 {
02106   /* Check the parameters */
02107   assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
02108 
02109   assert_param(IS_FUNCTIONAL_STATE(NewState));
02110   if (NewState != DISABLE)
02111   {
02112     RCC->AHB1ENR |= RCC_AHB1Periph;
02113   }
02114   else
02115   {
02116     RCC->AHB1ENR &= ~RCC_AHB1Periph;
02117   }
02118 }
02119 
02120 /**
02121   * @brief  Enables or disables the AHB2 peripheral clock.
02122   * @note   After reset, the peripheral clock (used for registers read/write access)
02123   *         is disabled and the application software has to enable this clock before 
02124   *         using it. 
02125   * @param  RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
02126   *          This parameter can be any combination of the following values:
02127   *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
02128   *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
02129   *            @arg RCC_AHB2Periph_HASH:   HASH clock
02130   *            @arg RCC_AHB2Periph_RNG:    RNG clock
02131   *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
02132   * @param  NewState: new state of the specified peripheral clock.
02133   *          This parameter can be: ENABLE or DISABLE.
02134   * @retval None
02135   */
02136 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
02137 {
02138   /* Check the parameters */
02139   assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
02140   assert_param(IS_FUNCTIONAL_STATE(NewState));
02141 
02142   if (NewState != DISABLE)
02143   {
02144     RCC->AHB2ENR |= RCC_AHB2Periph;
02145   }
02146   else
02147   {
02148     RCC->AHB2ENR &= ~RCC_AHB2Periph;
02149   }
02150 }
02151 
02152 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
02153 /**
02154   * @brief  Enables or disables the AHB3 peripheral clock.
02155   * @note   After reset, the peripheral clock (used for registers read/write access)
02156   *         is disabled and the application software has to enable this clock before 
02157   *         using it. 
02158   * @param  RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
02159   *          This parameter must be: 
02160   *           - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices)
02161   *           - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices)
02162   * @param  NewState: new state of the specified peripheral clock.
02163   *          This parameter can be: ENABLE or DISABLE.
02164   * @retval None
02165   */
02166 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
02167 {
02168   /* Check the parameters */
02169   assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));  
02170   assert_param(IS_FUNCTIONAL_STATE(NewState));
02171 
02172   if (NewState != DISABLE)
02173   {
02174     RCC->AHB3ENR |= RCC_AHB3Periph;
02175   }
02176   else
02177   {
02178     RCC->AHB3ENR &= ~RCC_AHB3Periph;
02179   }
02180 }
02181 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
02182 
02183 /**
02184   * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
02185   * @note   After reset, the peripheral clock (used for registers read/write access)
02186   *         is disabled and the application software has to enable this clock before 
02187   *         using it. 
02188   * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
02189   *          This parameter can be any combination of the following values:
02190   *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
02191   *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
02192   *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
02193   *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
02194   *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
02195   *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
02196   *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
02197   *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
02198   *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
02199   *            @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) 
02200   *            @arg RCC_APB1Periph_WWDG:   WWDG clock
02201   *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
02202   *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
02203   *            @arg RCC_APB1Periph_SPDIF:  SPDIF RX clock (STM32F446xx devices) 
02204   *            @arg RCC_APB1Periph_USART2: USART2 clock
02205   *            @arg RCC_APB1Periph_USART3: USART3 clock
02206   *            @arg RCC_APB1Periph_UART4:  UART4 clock
02207   *            @arg RCC_APB1Periph_UART5:  UART5 clock
02208   *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
02209   *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
02210   *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
02211   *            @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock
02212   *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
02213   *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
02214   *            @arg RCC_APB1Periph_CEC:    CEC clock (STM32F446xx devices)
02215   *            @arg RCC_APB1Periph_PWR:    PWR clock
02216   *            @arg RCC_APB1Periph_DAC:    DAC clock
02217   *            @arg RCC_APB1Periph_UART7:  UART7 clock
02218   *            @arg RCC_APB1Periph_UART8:  UART8 clock
02219   * @param  NewState: new state of the specified peripheral clock.
02220   *          This parameter can be: ENABLE or DISABLE.
02221   * @retval None
02222   */
02223 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
02224 {
02225   /* Check the parameters */
02226   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));  
02227   assert_param(IS_FUNCTIONAL_STATE(NewState));
02228 
02229   if (NewState != DISABLE)
02230   {
02231     RCC->APB1ENR |= RCC_APB1Periph;
02232   }
02233   else
02234   {
02235     RCC->APB1ENR &= ~RCC_APB1Periph;
02236   }
02237 }
02238 
02239 /**
02240   * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
02241   * @note   After reset, the peripheral clock (used for registers read/write access)
02242   *         is disabled and the application software has to enable this clock before 
02243   *         using it.
02244   * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
02245   *          This parameter can be any combination of the following values:
02246   *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
02247   *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
02248   *            @arg RCC_APB2Periph_USART1: USART1 clock
02249   *            @arg RCC_APB2Periph_USART6: USART6 clock
02250   *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
02251   *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
02252   *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
02253   *            @arg RCC_APB2Periph_SDIO:   SDIO clock
02254   *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
02255   *            @arg RCC_APB2Periph_SPI4:   SPI4 clock
02256   *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
02257   *            @arg RCC_APB2Periph_EXTIT:  EXTIIT clock
02258   *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
02259   *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
02260   *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
02261   *            @arg RCC_APB2Periph_SPI5:   SPI5 clock
02262   *            @arg RCC_APB2Periph_SPI6:   SPI6 clock
02263   *            @arg RCC_APB2Periph_SAI1:   SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
02264   *            @arg RCC_APB2Periph_SAI2:   SAI2 clock (STM32F446xx devices) 
02265   *            @arg RCC_APB2Periph_LTDC:   LTDC clock (STM32F429xx/439xx devices)
02266   *            @arg RCC_APB2Periph_DSI:    DSI clock (STM32F469_479xx devices)
02267   *            @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
02268   *            @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
02269   *            @arg RCC_APB2Periph_UART9:  UART9 Clock (STM32F413_423xx Devices)
02270   *            @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
02271   * @param  NewState: new state of the specified peripheral clock.
02272   *          This parameter can be: ENABLE or DISABLE.
02273   * @retval None
02274   */
02275 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
02276 {
02277   /* Check the parameters */
02278   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
02279   assert_param(IS_FUNCTIONAL_STATE(NewState));
02280 
02281   if (NewState != DISABLE)
02282   {
02283     RCC->APB2ENR |= RCC_APB2Periph;
02284   }
02285   else
02286   {
02287     RCC->APB2ENR &= ~RCC_APB2Periph;
02288   }
02289 }
02290 
02291 /**
02292   * @brief  Forces or releases AHB1 peripheral reset.
02293   * @param  RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
02294   *          This parameter can be any combination of the following values:
02295   *            @arg RCC_AHB1Periph_GPIOA:   GPIOA clock
02296   *            @arg RCC_AHB1Periph_GPIOB:   GPIOB clock 
02297   *            @arg RCC_AHB1Periph_GPIOC:   GPIOC clock
02298   *            @arg RCC_AHB1Periph_GPIOD:   GPIOD clock
02299   *            @arg RCC_AHB1Periph_GPIOE:   GPIOE clock
02300   *            @arg RCC_AHB1Periph_GPIOF:   GPIOF clock
02301   *            @arg RCC_AHB1Periph_GPIOG:   GPIOG clock
02302   *            @arg RCC_AHB1Periph_GPIOG:   GPIOG clock
02303   *            @arg RCC_AHB1Periph_GPIOI:   GPIOI clock
02304   *            @arg RCC_AHB1Periph_GPIOJ:   GPIOJ clock (STM32F42xxx/43xxx devices) 
02305   *            @arg RCC_AHB1Periph_GPIOK:   GPIOK clock (STM32F42xxx/43xxxdevices)   
02306   *            @arg RCC_AHB1Periph_CRC:     CRC clock
02307   *            @arg RCC_AHB1Periph_DMA1:    DMA1_MORT clock
02308   *            @arg RCC_AHB1Periph_DMA2:    DMA2_MORT clock
02309   *            @arg RCC_AHB1Periph_DMA2D:   DMA2D clock (STM32F429xx/439xx devices)   
02310   *            @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
02311   *            @arg RCC_AHB1Periph_OTG_HS:  USB OTG HS clock
02312   *            @arg RCC_AHB1Periph_RNG:     RNG clock for STM32F410xx devices   
02313   * @param  NewState: new state of the specified peripheral reset.
02314   *          This parameter can be: ENABLE or DISABLE.
02315   * @retval None
02316   */
02317 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
02318 {
02319   /* Check the parameters */
02320   assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
02321   assert_param(IS_FUNCTIONAL_STATE(NewState));
02322 
02323   if (NewState != DISABLE)
02324   {
02325     RCC->AHB1RSTR |= RCC_AHB1Periph;
02326   }
02327   else
02328   {
02329     RCC->AHB1RSTR &= ~RCC_AHB1Periph;
02330   }
02331 }
02332 
02333 /**
02334   * @brief  Forces or releases AHB2 peripheral reset.
02335   * @param  RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
02336   *          This parameter can be any combination of the following values:
02337   *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
02338   *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
02339   *            @arg RCC_AHB2Periph_HASH:   HASH clock
02340   *            @arg RCC_AHB2Periph_RNG:    RNG clock for STM32F40_41xxx/STM32F412xG/STM32F413_423xx/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices
02341   *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
02342   * @param  NewState: new state of the specified peripheral reset.
02343   *          This parameter can be: ENABLE or DISABLE.
02344   * @retval None
02345   */
02346 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
02347 {
02348   /* Check the parameters */
02349   assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
02350   assert_param(IS_FUNCTIONAL_STATE(NewState));
02351 
02352   if (NewState != DISABLE)
02353   {
02354     RCC->AHB2RSTR |= RCC_AHB2Periph;
02355   }
02356   else
02357   {
02358     RCC->AHB2RSTR &= ~RCC_AHB2Periph;
02359   }
02360 }
02361 
02362 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
02363 /**
02364   * @brief  Forces or releases AHB3 peripheral reset.
02365   * @param  RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
02366   *          This parameter must be: 
02367   *           - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG, STM32F413_423xx and STM32F429x/439x devices)
02368   *           - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
02369   * @param  NewState: new state of the specified peripheral reset.
02370   *          This parameter can be: ENABLE or DISABLE.
02371   * @retval None
02372   */
02373 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
02374 {
02375   /* Check the parameters */
02376   assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
02377   assert_param(IS_FUNCTIONAL_STATE(NewState));
02378 
02379   if (NewState != DISABLE)
02380   {
02381     RCC->AHB3RSTR |= RCC_AHB3Periph;
02382   }
02383   else
02384   {
02385     RCC->AHB3RSTR &= ~RCC_AHB3Periph;
02386   }
02387 }
02388 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
02389 
02390 /**
02391   * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
02392   * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
02393   *          This parameter can be any combination of the following values:
02394   *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
02395   *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
02396   *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
02397   *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
02398   *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
02399   *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
02400   *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
02401   *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
02402   *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
02403   *            @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) 
02404   *            @arg RCC_APB1Periph_WWDG:   WWDG clock
02405   *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
02406   *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
02407   *            @arg RCC_APB1Periph_SPDIF:  SPDIF RX clock (STM32F446xx devices) 
02408   *            @arg RCC_APB1Periph_USART2: USART2 clock
02409   *            @arg RCC_APB1Periph_USART3: USART3 clock
02410   *            @arg RCC_APB1Periph_UART4:  UART4 clock
02411   *            @arg RCC_APB1Periph_UART5:  UART5 clock
02412   *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
02413   *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
02414   *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
02415   *            @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock
02416   *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
02417   *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
02418   *            @arg RCC_APB1Periph_CEC:    CEC clock(STM32F446xx devices)
02419   *            @arg RCC_APB1Periph_PWR:    PWR clock
02420   *            @arg RCC_APB1Periph_DAC:    DAC clock
02421   *            @arg RCC_APB1Periph_UART7:  UART7 clock
02422   *            @arg RCC_APB1Periph_UART8:  UART8 clock  
02423   * @param  NewState: new state of the specified peripheral reset.
02424   *          This parameter can be: ENABLE or DISABLE.
02425   * @retval None
02426   */
02427 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
02428 {
02429   /* Check the parameters */
02430   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
02431   assert_param(IS_FUNCTIONAL_STATE(NewState));
02432   if (NewState != DISABLE)
02433   {
02434     RCC->APB1RSTR |= RCC_APB1Periph;
02435   }
02436   else
02437   {
02438     RCC->APB1RSTR &= ~RCC_APB1Periph;
02439   }
02440 }
02441 
02442 /**
02443   * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
02444   * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
02445   *          This parameter can be any combination of the following values:
02446   *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
02447   *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
02448   *            @arg RCC_APB2Periph_USART1: USART1 clock
02449   *            @arg RCC_APB2Periph_USART6: USART6 clock
02450   *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
02451   *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
02452   *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
02453   *            @arg RCC_APB2Periph_SDIO:   SDIO clock
02454   *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
02455   *            @arg RCC_APB2Periph_SPI4:   SPI4 clock  
02456   *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
02457   *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
02458   *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
02459   *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
02460   *            @arg RCC_APB2Periph_SPI5:   SPI5 clock
02461   *            @arg RCC_APB2Periph_SPI6:   SPI6 clock
02462   *            @arg RCC_APB2Periph_SAI1:   SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
02463   *            @arg RCC_APB2Periph_SAI2:   SAI2 clock (STM32F446xx devices) 
02464   *            @arg RCC_APB2Periph_LTDC:   LTDC clock (STM32F429xx/439xx devices)
02465   *            @arg RCC_APB2Periph_DSI:    DSI clock (STM32F469_479xx devices)
02466   *            @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
02467   *            @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
02468   *            @arg RCC_APB2Periph_UART9:  UART9 Clock (STM32F413_423xx Devices)
02469   *            @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
02470   * @param  NewState: new state of the specified peripheral reset.
02471   *          This parameter can be: ENABLE or DISABLE.
02472   * @retval None
02473   */
02474 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
02475 {
02476   /* Check the parameters */
02477   assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
02478   assert_param(IS_FUNCTIONAL_STATE(NewState));
02479   if (NewState != DISABLE)
02480   {
02481     RCC->APB2RSTR |= RCC_APB2Periph;
02482   }
02483   else
02484   {
02485     RCC->APB2RSTR &= ~RCC_APB2Periph;
02486   }
02487 }
02488 
02489 /**
02490   * @brief  Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
02491   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02492   *         power consumption.
02493   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02494   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02495   * @param  RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
02496   *          This parameter can be any combination of the following values:
02497   *            @arg RCC_AHB1Periph_GPIOA:       GPIOA clock
02498   *            @arg RCC_AHB1Periph_GPIOB:       GPIOB clock 
02499   *            @arg RCC_AHB1Periph_GPIOC:       GPIOC clock
02500   *            @arg RCC_AHB1Periph_GPIOD:       GPIOD clock
02501   *            @arg RCC_AHB1Periph_GPIOE:       GPIOE clock
02502   *            @arg RCC_AHB1Periph_GPIOF:       GPIOF clock
02503   *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
02504   *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
02505   *            @arg RCC_AHB1Periph_GPIOI:       GPIOI clock
02506   *            @arg RCC_AHB1Periph_GPIOJ:       GPIOJ clock (STM32F42xxx/43xxx devices) 
02507   *            @arg RCC_AHB1Periph_GPIOK:       GPIOK clock (STM32F42xxx/43xxx devices)   
02508   *            @arg RCC_AHB1Periph_CRC:         CRC clock
02509   *            @arg RCC_AHB1Periph_BKPSRAM:     BKPSRAM interface clock
02510   *            @arg RCC_AHB1Periph_DMA1:        DMA1_MORT clock
02511   *            @arg RCC_AHB1Periph_DMA2:        DMA2_MORT clock
02512   *            @arg RCC_AHB1Periph_DMA2D:       DMA2D clock (STM32F429xx/439xx devices) 
02513   *            @arg RCC_AHB1Periph_ETH_MAC:     Ethernet MAC clock
02514   *            @arg RCC_AHB1Periph_ETH_MAC_Tx:  Ethernet Transmission clock
02515   *            @arg RCC_AHB1Periph_ETH_MAC_Rx:  Ethernet Reception clock
02516   *            @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
02517   *            @arg RCC_AHB1Periph_OTG_HS:      USB OTG HS clock
02518   *            @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
02519   * @param  NewState: new state of the specified peripheral clock.
02520   *          This parameter can be: ENABLE or DISABLE.
02521   * @retval None
02522   */
02523 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
02524 {
02525   /* Check the parameters */
02526   assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
02527   assert_param(IS_FUNCTIONAL_STATE(NewState));
02528   if (NewState != DISABLE)
02529   {
02530     RCC->AHB1LPENR |= RCC_AHB1Periph;
02531   }
02532   else
02533   {
02534     RCC->AHB1LPENR &= ~RCC_AHB1Periph;
02535   }
02536 }
02537 
02538 /**
02539   * @brief  Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
02540   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02541   *           power consumption.
02542   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02543   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02544   * @param  RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
02545   *          This parameter can be any combination of the following values:
02546   *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
02547   *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
02548   *            @arg RCC_AHB2Periph_HASH:   HASH clock
02549   *            @arg RCC_AHB2Periph_RNG:    RNG clock
02550   *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock  
02551   * @param  NewState: new state of the specified peripheral clock.
02552   *          This parameter can be: ENABLE or DISABLE.
02553   * @retval None
02554   */
02555 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
02556 {
02557   /* Check the parameters */
02558   assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
02559   assert_param(IS_FUNCTIONAL_STATE(NewState));
02560   if (NewState != DISABLE)
02561   {
02562     RCC->AHB2LPENR |= RCC_AHB2Periph;
02563   }
02564   else
02565   {
02566     RCC->AHB2LPENR &= ~RCC_AHB2Periph;
02567   }
02568 }
02569 
02570 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
02571 /**
02572   * @brief  Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
02573   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02574   *         power consumption.
02575   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02576   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02577   * @param  RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
02578   *          This parameter must be: 
02579   *           - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices)
02580   *           - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices) 
02581   * @param  NewState: new state of the specified peripheral clock.
02582   *          This parameter can be: ENABLE or DISABLE.
02583   * @retval None
02584   */
02585 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
02586 {
02587   /* Check the parameters */
02588   assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
02589   assert_param(IS_FUNCTIONAL_STATE(NewState));
02590   if (NewState != DISABLE)
02591   {
02592     RCC->AHB3LPENR |= RCC_AHB3Periph;
02593   }
02594   else
02595   {
02596     RCC->AHB3LPENR &= ~RCC_AHB3Periph;
02597   }
02598 }
02599 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
02600 
02601 /**
02602   * @brief  Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
02603   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02604   *         power consumption.
02605   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02606   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02607   * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
02608   *          This parameter can be any combination of the following values:
02609   *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
02610   *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
02611   *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
02612   *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
02613   *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
02614   *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
02615   *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
02616   *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
02617   *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
02618   *            @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) 
02619   *            @arg RCC_APB1Periph_WWDG:   WWDG clock
02620   *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
02621   *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
02622   *            @arg RCC_APB1Periph_SPDIF:   SPDIF RX clock (STM32F446xx devices) 
02623   *            @arg RCC_APB1Periph_USART2: USART2 clock
02624   *            @arg RCC_APB1Periph_USART3: USART3 clock
02625   *            @arg RCC_APB1Periph_UART4:  UART4 clock
02626   *            @arg RCC_APB1Periph_UART5:  UART5 clock
02627   *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
02628   *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
02629   *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
02630   *            @arg RCC_APB1Periph_FMPI2C1:   FMPI2C1 clock
02631   *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
02632   *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
02633   *            @arg RCC_APB1Periph_CEC:    CEC clock (STM32F446xx devices)
02634   *            @arg RCC_APB1Periph_PWR:    PWR clock
02635   *            @arg RCC_APB1Periph_DAC:    DAC clock
02636   *            @arg RCC_APB1Periph_UART7:  UART7 clock
02637   *            @arg RCC_APB1Periph_UART8:  UART8 clock
02638   * @param  NewState: new state of the specified peripheral clock.
02639   *          This parameter can be: ENABLE or DISABLE.
02640   * @retval None
02641   */
02642 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
02643 {
02644   /* Check the parameters */
02645   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
02646   assert_param(IS_FUNCTIONAL_STATE(NewState));
02647   if (NewState != DISABLE)
02648   {
02649     RCC->APB1LPENR |= RCC_APB1Periph;
02650   }
02651   else
02652   {
02653     RCC->APB1LPENR &= ~RCC_APB1Periph;
02654   }
02655 }
02656 
02657 /**
02658   * @brief  Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
02659   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02660   *         power consumption.
02661   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02662   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02663   * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
02664   *          This parameter can be any combination of the following values:
02665   *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
02666   *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
02667   *            @arg RCC_APB2Periph_USART1: USART1 clock
02668   *            @arg RCC_APB2Periph_USART6: USART6 clock
02669   *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
02670   *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
02671   *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
02672   *            @arg RCC_APB2Periph_SDIO:   SDIO clock
02673   *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
02674   *            @arg RCC_APB2Periph_SPI4:   SPI4 clock
02675   *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
02676   *            @arg RCC_APB2Periph_EXTIT:  EXTIIT clock
02677   *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
02678   *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
02679   *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
02680   *            @arg RCC_APB2Periph_SPI5:   SPI5 clock
02681   *            @arg RCC_APB2Periph_SPI6:   SPI6 clock
02682   *            @arg RCC_APB2Periph_SAI1:   SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
02683   *            @arg RCC_APB2Periph_SAI2:   SAI2 clock (STM32F446xx devices)
02684   *            @arg RCC_APB2Periph_LTDC:   LTDC clock (STM32F429xx/439xx devices)
02685   *            @arg RCC_APB2Periph_DSI:    DSI clock (STM32F469_479xx devices)
02686   *            @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
02687   *            @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
02688   *            @arg RCC_APB2Periph_UART9:  UART9 Clock (STM32F413_423xx Devices)
02689   *            @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
02690   * @param  NewState: new state of the specified peripheral clock.
02691   *          This parameter can be: ENABLE or DISABLE.
02692   * @retval None
02693   */
02694 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
02695 {
02696   /* Check the parameters */
02697   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
02698   assert_param(IS_FUNCTIONAL_STATE(NewState));
02699   if (NewState != DISABLE)
02700   {
02701     RCC->APB2LPENR |= RCC_APB2Periph;
02702   }
02703   else
02704   {
02705     RCC->APB2LPENR &= ~RCC_APB2Periph;
02706   }
02707 }
02708 
02709 /**
02710   * @brief Configures the External Low Speed oscillator mode (LSE mode).
02711   * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices.
02712   * @param  Mode: specifies the LSE mode.
02713   *          This parameter can be one of the following values:
02714   *            @arg RCC_LSE_LOWPOWER_MODE:  LSE oscillator in low power mode.
02715   *            @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode.
02716   * @retval None
02717   */
02718 void RCC_LSEModeConfig(uint8_t RCC_Mode)
02719 {
02720   /* Check the parameters */
02721   assert_param(IS_RCC_LSE_MODE(RCC_Mode));
02722   
02723   if(RCC_Mode == RCC_LSE_HIGHDRIVE_MODE)
02724   {
02725     SET_BIT_MORT(RCC->BDCR, RCC_BDCR_LSEMOD_MORT);
02726   }
02727   else
02728   {
02729     CLEAR_BIT_MORT(RCC->BDCR, RCC_BDCR_LSEMOD_MORT);
02730   }
02731 }
02732 
02733 #if defined(STM32F410xx) || defined(STM32F413_423xx)
02734 /**
02735   * @brief Configures the LPTIM1 clock Source.
02736   * @note This feature is only available for STM32F410xx devices.
02737   * @param RCC_ClockSource: specifies the LPTIM1 clock Source.
02738   *          This parameter can be one of the following values:
02739   *            @arg RCC_LPTIM1CLKSOURCE_PCLK: LPTIM1 clock from APB1 selected.
02740   *            @arg RCC_LPTIM1CLKSOURCE_HSI:  LPTIM1 clock from HSI selected.
02741   *            @arg RCC_LPTIM1CLKSOURCE_LSI:  LPTIM1 clock from LSI selected.
02742   *            @arg RCC_LPTIM1CLKSOURCE_LSE:  LPTIM1 clock from LSE selected.
02743   * @retval None
02744   */
02745 void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource)
02746 {
02747   /* Check the parameters */
02748   assert_param(IS_RCC_LPTIM1_CLOCKSOURCE(RCC_ClockSource));
02749 
02750   /* Clear LPTIM1 clock source selection source bits */
02751   RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_LPTIM1SEL;
02752   /* Set new LPTIM1 clock source */
02753   RCC->DCKCFGR2 |= RCC_ClockSource;
02754 }
02755 #endif /* STM32F410xx || STM32F413_423xx */
02756 
02757 #if defined(STM32F469_479xx)
02758 /**
02759   * @brief Configures the DSI clock Source.
02760   * @note This feature is only available for STM32F469_479xx devices.
02761   * @param RCC_ClockSource: specifies the DSI clock Source.
02762   *          This parameter can be one of the following values:
02763   *            @arg RCC_DSICLKSource_PHY: DSI-PHY used as DSI byte lane clock source (usual case).
02764   *            @arg RCC_DSICLKSource_PLLR: PLL_R used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode).
02765   * @retval None
02766   */
02767 void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource)
02768 {
02769   /* Check the parameters */
02770   assert_param(IS_RCC_DSI_CLOCKSOURCE(RCC_ClockSource));
02771   
02772   if(RCC_ClockSource == RCC_DSICLKSource_PLLR)
02773   {
02774     SET_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
02775   }
02776   else
02777   {
02778     CLEAR_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
02779   }
02780 }
02781 #endif /*  STM32F469_479xx */
02782 
02783 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
02784 /**
02785   * @brief Configures the 48MHz clock Source.
02786   * @note This feature is only available for STM32F446xx/STM32F469_479xx devices.
02787   * @param RCC_ClockSource: specifies the 48MHz clock Source.
02788   *          This parameter can be one of the following values:
02789   *            @arg RCC_48MHZCLKSource_PLL: 48MHz from PLL selected.
02790   *            @arg RCC_48MHZCLKSource_PLLSAI: 48MHz from PLLSAI selected.
02791   *            @arg RCC_CK48CLKSOURCE_PLLI2SQ : 48MHz from PLLI2SQ
02792   * @retval None
02793   */
02794 void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
02795 {
02796   /* Check the parameters */
02797   assert_param(IS_RCC_48MHZ_CLOCKSOURCE(RCC_ClockSource));
02798 #if defined(STM32F469_479xx) 
02799   if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
02800   {
02801     SET_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
02802   }
02803   else
02804   {
02805     CLEAR_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
02806   }
02807 #elif  defined(STM32F446xx)
02808   if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
02809   {
02810     SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
02811   }
02812   else
02813   {
02814     CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
02815   }
02816 #elif defined(STM32F412xG) || defined(STM32F413_423xx)
02817   if(RCC_ClockSource == RCC_CK48CLKSOURCE_PLLI2SQ)
02818   {
02819     SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
02820   }
02821   else
02822   {
02823     CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
02824   }
02825 #else
02826 #endif /* STM32F469_479xx */  
02827 }
02828 
02829 /**
02830   * @brief Configures the SDIO clock Source.
02831   * @note This feature is only available for STM32F469_479xx/STM32F446xx devices.
02832   * @param RCC_ClockSource: specifies the SDIO clock Source.
02833   *          This parameter can be one of the following values:
02834   *            @arg RCC_SDIOCLKSource_48MHZ: 48MHz clock selected.
02835   *            @arg RCC_SDIOCLKSource_SYSCLK: system clock selected.
02836   * @retval None
02837   */
02838 void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
02839 {
02840   /* Check the parameters */
02841   assert_param(IS_RCC_SDIO_CLOCKSOURCE(RCC_ClockSource));
02842 #if defined(STM32F469_479xx)   
02843   if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
02844   {
02845     SET_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
02846   }
02847   else
02848   {
02849     CLEAR_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
02850   }
02851 #elif defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
02852   if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
02853   {
02854     SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL_MORT);
02855   }
02856   else
02857   {
02858     CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL_MORT);
02859   }
02860 #else
02861 #endif /* STM32F469_479xx */ 
02862 }
02863 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
02864 
02865 #if defined(STM32F446xx)
02866 /**
02867   * @brief  Enables or disables the AHB1 clock gating for the specified IPs.
02868   * @note This feature is only available for STM32F446xx devices.
02869   * @param  RCC_AHB1ClockGating: specifies the AHB1 clock gating.
02870   *          This parameter can be any combination of the following values:
02871   *            @arg RCC_AHB1ClockGating_APB1Bridge: AHB1 to APB1 clock
02872   *            @arg RCC_AHB1ClockGating_APB2Bridge: AHB1 to APB2 clock 
02873   *            @arg RCC_AHB1ClockGating_CM4DBG: Cortex M4 ETM clock
02874   *            @arg RCC_AHB1ClockGating_SPARE: Spare clock
02875   *            @arg RCC_AHB1ClockGating_SRAM: SRAM controller clock
02876   *            @arg RCC_AHB1ClockGating_FLITF: Flash interface clock
02877   *            @arg RCC_AHB1ClockGating_RCC: RCC clock
02878   * @param  NewState: new state of the specified peripheral clock.
02879   *          This parameter can be: ENABLE or DISABLE.
02880   * @retval None
02881   */
02882 void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState)
02883 {
02884   /* Check the parameters */
02885   assert_param(IS_RCC_AHB1_CLOCKGATING(RCC_AHB1ClockGating));
02886 
02887   assert_param(IS_FUNCTIONAL_STATE(NewState));
02888   if (NewState != DISABLE)
02889   {
02890     RCC->CKGATENR &= ~RCC_AHB1ClockGating;
02891   }
02892   else
02893   {
02894     RCC->CKGATENR |= RCC_AHB1ClockGating;
02895   }
02896 }
02897 
02898 /**
02899   * @brief Configures the SPDIFRX clock Source.
02900   * @note This feature is only available for STM32F446xx devices.
02901   * @param RCC_ClockSource: specifies the SPDIFRX clock Source.
02902   *          This parameter can be one of the following values:
02903   *            @arg RCC_SPDIFRXCLKSource_PLLR: SPDIFRX clock from PLL_R selected.
02904   *            @arg RCC_SPDIFRXCLKSource_PLLI2SP: SPDIFRX clock from PLLI2S_P selected.
02905   * @retval None
02906   */
02907 void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource)
02908 {
02909   /* Check the parameters */
02910   assert_param(IS_RCC_SPDIFRX_CLOCKSOURCE(RCC_ClockSource));
02911   
02912   if(RCC_ClockSource == RCC_SPDIFRXCLKSource_PLLI2SP)
02913   {
02914     SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL_MORT);
02915   }
02916   else
02917   {
02918     CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL_MORT);
02919   }
02920 }
02921 
02922 /**
02923   * @brief Configures the CEC clock Source.
02924   * @note This feature is only available for STM32F446xx devices.
02925   * @param RCC_ClockSource: specifies the CEC clock Source.
02926   *          This parameter can be one of the following values:
02927   *            @arg RCC_CECCLKSource_HSIDiv488: CEC clock from HSI/488 selected.
02928   *            @arg RCC_CECCLKSource_LSE: CEC clock from LSE selected.
02929   * @retval None
02930   */
02931 void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource)
02932 {
02933   /* Check the parameters */
02934   assert_param(IS_RCC_CEC_CLOCKSOURCE(RCC_ClockSource));
02935   
02936   if(RCC_ClockSource == RCC_CECCLKSource_LSE)
02937   {
02938     SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL_MORT);
02939   }
02940   else
02941   {
02942     CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL_MORT);
02943   }
02944 }
02945 #endif /* STM32F446xx */
02946 
02947 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
02948 /**
02949   * @brief Configures the FMPI2C1 clock Source.
02950   * @note This feature is only available for STM32F446xx devices.
02951   * @param RCC_ClockSource: specifies the FMPI2C1 clock Source.
02952   *          This parameter can be one of the following values:
02953   *            @arg RCC_FMPI2C1CLKSource_APB1: FMPI2C1 clock from APB1 selected.
02954   *            @arg RCC_FMPI2C1CLKSource_SYSCLK: FMPI2C1 clock from Sytem clock selected.
02955   *            @arg RCC_FMPI2C1CLKSource_HSI: FMPI2C1 clock from HSI selected.
02956   * @retval None
02957   */
02958 void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource)
02959 {
02960   /* Check the parameters */
02961   assert_param(IS_RCC_FMPI2C1_CLOCKSOURCE(RCC_ClockSource));
02962 
02963   /* Clear FMPI2C1 clock source selection source bits */
02964   RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_FMPI2C1SEL_MORT;
02965   /* Set new FMPI2C1 clock source */
02966   RCC->DCKCFGR2 |= RCC_ClockSource;
02967 }
02968 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
02969 /**
02970   * @}
02971   */
02972 
02973 #if defined(STM32F410xx)
02974 /**
02975   * @brief  Enables or disables the MCO1.
02976   * @param  NewState: new state of the MCO1.
02977   *          This parameter can be: ENABLE or DISABLE.
02978   * @retval None
02979   */
02980 void RCC_MCO1Cmd(FunctionalState NewState)
02981 {
02982   /* Check the parameters */
02983   assert_param(IS_FUNCTIONAL_STATE(NewState));
02984 
02985   *(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = (uint32_t)NewState;
02986 }
02987 
02988 /**
02989   * @brief  Enables or disables the MCO2.
02990   * @param  NewState: new state of the MCO2.
02991   *          This parameter can be: ENABLE or DISABLE.
02992   * @retval None
02993   */
02994 void RCC_MCO2Cmd(FunctionalState NewState)
02995 {
02996   /* Check the parameters */
02997   assert_param(IS_FUNCTIONAL_STATE(NewState));
02998 
02999   *(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = (uint32_t)NewState;
03000 }
03001 #endif /* STM32F410xx */
03002 
03003 /** @defgroup RCC_Group4 Interrupts and flags management functions
03004  *  @brief   Interrupts and flags management functions 
03005  *
03006 @verbatim   
03007  ===============================================================================
03008                 ##### Interrupts and flags management functions #####
03009  ===============================================================================  
03010 
03011 @endverbatim
03012   * @{
03013   */
03014 
03015 /**
03016   * @brief  Enables or disables the specified RCC interrupts.
03017   * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
03018   *          This parameter can be any combination of the following values:
03019   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
03020   *            @arg RCC_IT_LSERDY: LSE ready interrupt
03021   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
03022   *            @arg RCC_IT_HSERDY: HSE ready interrupt
03023   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
03024   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
03025   *            @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
03026   * @param  NewState: new state of the specified RCC interrupts.
03027   *          This parameter can be: ENABLE or DISABLE.
03028   * @retval None
03029   */
03030 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
03031 {
03032   /* Check the parameters */
03033   assert_param(IS_RCC_IT(RCC_IT));
03034   assert_param(IS_FUNCTIONAL_STATE(NewState));
03035   if (NewState != DISABLE)
03036   {
03037     /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
03038     *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
03039   }
03040   else
03041   {
03042     /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
03043     *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
03044   }
03045 }
03046 
03047 /**
03048   * @brief  Checks whether the specified RCC flag is set or not.
03049   * @param  RCC_FLAG: specifies the flag to check.
03050   *          This parameter can be one of the following values:
03051   *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
03052   *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
03053   *            @arg RCC_FLAG_PLLRDY: main PLL clock ready
03054   *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
03055   *            @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
03056   *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
03057   *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
03058   *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
03059   *            @arg RCC_FLAG_PINRST: Pin reset
03060   *            @arg RCC_FLAG_PORRST: POR/PDR reset
03061   *            @arg RCC_FLAG_SFTRST: Software reset
03062   *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
03063   *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset
03064   *            @arg RCC_FLAG_LPWRRST: Low Power reset
03065   * @retval The new state of RCC_FLAG (SET or RESET).
03066   */
03067 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
03068 {
03069   uint32_t tmp = 0;
03070   uint32_t statusreg = 0;
03071   FlagStatus bitstatus = RESET;
03072 
03073   /* Check the parameters */
03074   assert_param(IS_RCC_FLAG(RCC_FLAG));
03075 
03076   /* Get the RCC register index */
03077   tmp = RCC_FLAG >> 5;
03078   if (tmp == 1)               /* The flag to check is in CR register */
03079   {
03080     statusreg = RCC->CR;
03081   }
03082   else if (tmp == 2)          /* The flag to check is in BDCR register */
03083   {
03084     statusreg = RCC->BDCR;
03085   }
03086   else                       /* The flag to check is in CSR register */
03087   {
03088     statusreg = RCC->CSR;
03089   }
03090 
03091   /* Get the flag position */
03092   tmp = RCC_FLAG & FLAG_MASK;
03093   if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
03094   {
03095     bitstatus = SET;
03096   }
03097   else
03098   {
03099     bitstatus = RESET;
03100   }
03101   /* Return the flag status */
03102   return bitstatus;
03103 }
03104 
03105 /**
03106   * @brief  Clears the RCC reset flags.
03107   *         The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,  RCC_FLAG_SFTRST,
03108   *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
03109   * @param  None
03110   * @retval None
03111   */
03112 void RCC_ClearFlag(void)
03113 {
03114   /* Set RMVF bit to clear the reset flags */
03115   RCC->CSR |= RCC_CSR_RMVF_MORT;
03116 }
03117 
03118 /**
03119   * @brief  Checks whether the specified RCC interrupt has occurred or not.
03120   * @param  RCC_IT: specifies the RCC interrupt source to check.
03121   *          This parameter can be one of the following values:
03122   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
03123   *            @arg RCC_IT_LSERDY: LSE ready interrupt
03124   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
03125   *            @arg RCC_IT_HSERDY: HSE ready interrupt
03126   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
03127   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
03128   *            @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
03129   *            @arg RCC_IT_CSS: Clock Security System interrupt
03130   * @retval The new state of RCC_IT (SET or RESET).
03131   */
03132 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
03133 {
03134   ITStatus bitstatus = RESET;
03135 
03136   /* Check the parameters */
03137   assert_param(IS_RCC_GET_IT(RCC_IT));
03138 
03139   /* Check the status of the specified RCC interrupt */
03140   if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
03141   {
03142     bitstatus = SET;
03143   }
03144   else
03145   {
03146     bitstatus = RESET;
03147   }
03148   /* Return the RCC_IT status */
03149   return  bitstatus;
03150 }
03151 
03152 /**
03153   * @brief  Clears the RCC's interrupt pending bits.
03154   * @param  RCC_IT: specifies the interrupt pending bit to clear.
03155   *          This parameter can be any combination of the following values:
03156   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
03157   *            @arg RCC_IT_LSERDY: LSE ready interrupt
03158   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
03159   *            @arg RCC_IT_HSERDY: HSE ready interrupt
03160   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
03161   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt  
03162   *            @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices) 
03163   *            @arg RCC_IT_CSS: Clock Security System interrupt
03164   * @retval None
03165   */
03166 void RCC_ClearITPendingBit(uint8_t RCC_IT)
03167 {
03168   /* Check the parameters */
03169   assert_param(IS_RCC_CLEAR_IT(RCC_IT));
03170 
03171   /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
03172      pending bits */
03173   *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
03174 }
03175 
03176 /**
03177   * @}
03178   */ 
03179 
03180 /**
03181   * @}
03182   */ 
03183 
03184 /**
03185   * @}
03186   */ 
03187 
03188 /**
03189   * @}
03190   */ 
03191 
03192 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
03193 
03194 
03195 
03196 
03197