Il y avait des problèmes dans la libraire...
Fork of USBDEVICE by
USBDevice/USBHAL_STM32F4.cpp@3:d9c7334e2183, 2017-02-15 (annotated)
- Committer:
- frq08711@LMECWL0871.LME.ST.COM
- Date:
- Wed Feb 15 09:48:15 2017 +0100
- Revision:
- 3:d9c7334e2183
- Parent:
- 1:2a3ae13b45ef
update 5.3.5
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 1 | /* Copyright (c) 2010-2011 mbed.org, MIT License |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 2 | * |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 3 | * Permission is hereby granted, free of charge, to any person obtaining a copy of this software |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 4 | * and associated documentation files (the "Software"), to deal in the Software without |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 5 | * restriction, including without limitation the rights to use, copy, modify, merge, publish, |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 6 | * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 7 | * Software is furnished to do so, subject to the following conditions: |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 8 | * |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 9 | * The above copyright notice and this permission notice shall be included in all copies or |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 10 | * substantial portions of the Software. |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 11 | * |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 12 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 13 | * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 14 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 15 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 16 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 17 | */ |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 18 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 19 | #if defined(TARGET_STM32F4) && !defined(USB_STM_HAL) |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 20 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 21 | #include "USBHAL.h" |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 22 | #include "USBRegs_STM32.h" |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 23 | #include "pinmap.h" |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 24 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 25 | USBHAL * USBHAL::instance; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 26 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 27 | static volatile int epComplete = 0; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 28 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 29 | static uint32_t bufferEnd = 0; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 30 | static const uint32_t rxFifoSize = 512; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 31 | static uint32_t rxFifoCount = 0; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 32 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 33 | static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2]; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 34 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 35 | uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 36 | return 0; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 37 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 38 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 39 | USBHAL::USBHAL(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 40 | NVIC_DisableIRQ(OTG_FS_IRQn); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 41 | epCallback[0] = &USBHAL::EP1_OUT_callback; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 42 | epCallback[1] = &USBHAL::EP1_IN_callback; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 43 | epCallback[2] = &USBHAL::EP2_OUT_callback; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 44 | epCallback[3] = &USBHAL::EP2_IN_callback; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 45 | epCallback[4] = &USBHAL::EP3_OUT_callback; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 46 | epCallback[5] = &USBHAL::EP3_IN_callback; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 47 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 48 | // Enable power and clocking |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 49 | RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 50 | |
frq08711@LMECWL0871.LME.ST.COM | 3:d9c7334e2183 | 51 | #if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F412ZG) || defined(TARGET_STM32F429ZI) |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 52 | pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 53 | pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 54 | pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 55 | pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 56 | pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 57 | #else |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 58 | pin_function(PA_8, STM_PIN_DATA(2, 10)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 59 | pin_function(PA_9, STM_PIN_DATA(0, 0)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 60 | pin_function(PA_10, STM_PIN_DATA(2, 10)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 61 | pin_function(PA_11, STM_PIN_DATA(2, 10)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 62 | pin_function(PA_12, STM_PIN_DATA(2, 10)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 63 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 64 | // Set ID pin to open drain with pull-up resistor |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 65 | pin_mode(PA_10, OpenDrain); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 66 | GPIOA->PUPDR &= ~(0x3 << 20); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 67 | GPIOA->PUPDR |= 1 << 20; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 68 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 69 | // Set VBUS pin to open drain |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 70 | pin_mode(PA_9, OpenDrain); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 71 | #endif |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 72 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 73 | RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 74 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 75 | // Enable interrupts |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 76 | OTG_FS->GREGS.GAHBCFG |= (1 << 0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 77 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 78 | // Turnaround time to maximum value - too small causes packet loss |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 79 | OTG_FS->GREGS.GUSBCFG |= (0xF << 10); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 80 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 81 | // Unmask global interrupts |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 82 | OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 83 | (1 << 4) | // RX FIFO not empty |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 84 | (1 << 12); // USB reset |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 85 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 86 | OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 87 | (1 << 2); // Non-zero-length status OUT handshake |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 88 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 89 | OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 90 | (1 << 16); // Power Up |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 91 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 92 | instance = this; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 93 | NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 94 | NVIC_SetPriority(OTG_FS_IRQn, 1); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 95 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 96 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 97 | USBHAL::~USBHAL(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 98 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 99 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 100 | void USBHAL::connect(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 101 | NVIC_EnableIRQ(OTG_FS_IRQn); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 102 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 103 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 104 | void USBHAL::disconnect(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 105 | NVIC_DisableIRQ(OTG_FS_IRQn); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 106 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 107 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 108 | void USBHAL::configureDevice(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 109 | // Not needed |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 110 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 111 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 112 | void USBHAL::unconfigureDevice(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 113 | // Not needed |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 114 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 115 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 116 | void USBHAL::setAddress(uint8_t address) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 117 | OTG_FS->DREGS.DCFG |= (address << 4); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 118 | EP0write(0, 0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 119 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 120 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 121 | bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 122 | uint32_t flags) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 123 | uint32_t epIndex = endpoint >> 1; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 124 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 125 | uint32_t type; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 126 | switch (endpoint) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 127 | case EP0IN: |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 128 | case EP0OUT: |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 129 | type = 0; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 130 | break; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 131 | case EPISO_IN: |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 132 | case EPISO_OUT: |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 133 | type = 1; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 134 | case EPBULK_IN: |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 135 | case EPBULK_OUT: |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 136 | type = 2; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 137 | break; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 138 | case EPINT_IN: |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 139 | case EPINT_OUT: |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 140 | type = 3; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 141 | break; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 142 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 143 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 144 | // Generic in or out EP controls |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 145 | uint32_t control = (maxPacket << 0) | // Packet size |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 146 | (1 << 15) | // Active endpoint |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 147 | (type << 18); // Endpoint type |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 148 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 149 | if (endpoint & 0x1) { // In Endpoint |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 150 | // Set up the Tx FIFO |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 151 | if (endpoint == EP0IN) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 152 | OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 153 | (bufferEnd << 0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 154 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 155 | else { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 156 | OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 157 | (bufferEnd << 0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 158 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 159 | bufferEnd += maxPacket >> 2; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 160 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 161 | // Set the In EP specific control settings |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 162 | if (endpoint != EP0IN) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 163 | control |= (1 << 28); // SD0PID |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 164 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 165 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 166 | control |= (epIndex << 22) | // TxFIFO index |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 167 | (1 << 27); // SNAK |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 168 | OTG_FS->INEP_REGS[epIndex].DIEPCTL = control; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 169 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 170 | // Unmask the interrupt |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 171 | OTG_FS->DREGS.DAINTMSK |= (1 << epIndex); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 172 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 173 | else { // Out endpoint |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 174 | // Set the out EP specific control settings |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 175 | control |= (1 << 26); // CNAK |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 176 | OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 177 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 178 | // Unmask the interrupt |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 179 | OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 180 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 181 | return true; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 182 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 183 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 184 | // read setup packet |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 185 | void USBHAL::EP0setup(uint8_t *buffer) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 186 | memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 187 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 188 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 189 | void USBHAL::EP0readStage(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 190 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 191 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 192 | void USBHAL::EP0read(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 193 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 194 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 195 | uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 196 | uint32_t* buffer32 = (uint32_t *) buffer; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 197 | uint32_t length = rxFifoCount; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 198 | for (uint32_t i = 0; i < length; i += 4) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 199 | buffer32[i >> 2] = OTG_FS->FIFO[0][0]; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 200 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 201 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 202 | rxFifoCount = 0; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 203 | return length; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 204 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 205 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 206 | void USBHAL::EP0write(uint8_t *buffer, uint32_t size) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 207 | endpointWrite(0, buffer, size); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 208 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 209 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 210 | void USBHAL::EP0getWriteResult(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 211 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 212 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 213 | void USBHAL::EP0stall(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 214 | // If we stall the out endpoint here then we have problems transferring |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 215 | // and setup requests after the (stalled) get device qualifier requests. |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 216 | // TODO: Find out if this is correct behavior, or whether we are doing |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 217 | // something else wrong |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 218 | stallEndpoint(EP0IN); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 219 | // stallEndpoint(EP0OUT); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 220 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 221 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 222 | EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 223 | uint32_t epIndex = endpoint >> 1; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 224 | uint32_t size = (1 << 19) | // 1 packet |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 225 | (maximumSize << 0); // Packet size |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 226 | // if (endpoint == EP0OUT) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 227 | size |= (1 << 29); // 1 setup packet |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 228 | // } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 229 | OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 230 | OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 231 | (1 << 26); // Clear NAK |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 232 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 233 | epComplete &= ~(1 << endpoint); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 234 | return EP_PENDING; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 235 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 236 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 237 | EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 238 | if (!(epComplete & (1 << endpoint))) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 239 | return EP_PENDING; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 240 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 241 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 242 | uint32_t* buffer32 = (uint32_t *) buffer; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 243 | uint32_t length = rxFifoCount; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 244 | for (uint32_t i = 0; i < length; i += 4) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 245 | buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0]; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 246 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 247 | rxFifoCount = 0; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 248 | *bytesRead = length; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 249 | return EP_COMPLETED; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 250 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 251 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 252 | EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 253 | uint32_t epIndex = endpoint >> 1; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 254 | OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 255 | (size << 0); // Size of packet |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 256 | OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 257 | (1 << 26); // CNAK |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 258 | OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 259 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 260 | while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2)); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 261 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 262 | for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 263 | OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 264 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 265 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 266 | epComplete &= ~(1 << endpoint); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 267 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 268 | return EP_PENDING; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 269 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 270 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 271 | EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 272 | if (epComplete & (1 << endpoint)) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 273 | epComplete &= ~(1 << endpoint); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 274 | return EP_COMPLETED; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 275 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 276 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 277 | return EP_PENDING; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 278 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 279 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 280 | void USBHAL::stallEndpoint(uint8_t endpoint) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 281 | if (endpoint & 0x1) { // In EP |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 282 | OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 283 | (1 << 21); // Stall |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 284 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 285 | else { // Out EP |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 286 | OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 287 | OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 288 | (1 << 21); // Stall |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 289 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 290 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 291 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 292 | void USBHAL::unstallEndpoint(uint8_t endpoint) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 293 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 294 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 295 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 296 | bool USBHAL::getEndpointStallState(uint8_t endpoint) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 297 | return false; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 298 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 299 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 300 | void USBHAL::remoteWakeup(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 301 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 302 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 303 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 304 | void USBHAL::_usbisr(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 305 | instance->usbisr(); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 306 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 307 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 308 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 309 | void USBHAL::usbisr(void) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 310 | if (OTG_FS->GREGS.GINTSTS & (1 << 11)) { // USB Suspend |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 311 | suspendStateChanged(1); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 312 | }; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 313 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 314 | if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 315 | suspendStateChanged(0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 316 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 317 | // Set SNAK bits |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 318 | OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 319 | OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 320 | OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 321 | OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 322 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 323 | OTG_FS->DREGS.DIEPMSK = (1 << 0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 324 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 325 | bufferEnd = 0; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 326 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 327 | // Set the receive FIFO size |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 328 | OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 329 | bufferEnd += rxFifoSize >> 2; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 330 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 331 | // Create the endpoints, and wait for setup packets on out EP0 |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 332 | realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 333 | realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 334 | endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 335 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 336 | OTG_FS->GREGS.GINTSTS = (1 << 12); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 337 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 338 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 339 | if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 340 | uint32_t status = OTG_FS->GREGS.GRXSTSP; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 341 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 342 | uint32_t endpoint = (status & 0xF) << 1; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 343 | uint32_t length = (status >> 4) & 0x7FF; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 344 | uint32_t type = (status >> 17) & 0xF; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 345 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 346 | rxFifoCount = length; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 347 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 348 | if (type == 0x6) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 349 | // Setup packet |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 350 | for (uint32_t i=0; i<length; i+=4) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 351 | setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2]; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 352 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 353 | rxFifoCount = 0; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 354 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 355 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 356 | if (type == 0x4) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 357 | // Setup complete |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 358 | EP0setupCallback(); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 359 | endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 360 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 361 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 362 | if (type == 0x2) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 363 | // Out packet |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 364 | if (endpoint == EP0OUT) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 365 | EP0out(); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 366 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 367 | else { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 368 | epComplete |= (1 << endpoint); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 369 | if ((instance->*(epCallback[endpoint - 2]))()) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 370 | epComplete &= ~(1 << endpoint); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 371 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 372 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 373 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 374 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 375 | for (uint32_t i=0; i<rxFifoCount; i+=4) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 376 | (void) OTG_FS->FIFO[0][0]; |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 377 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 378 | OTG_FS->GREGS.GINTSTS = (1 << 4); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 379 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 380 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 381 | if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 382 | // Loop through the in endpoints |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 383 | for (uint32_t i=0; i<4; i++) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 384 | if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 385 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 386 | if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 387 | // If the Tx FIFO is empty on EP0 we need to send a further |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 388 | // packet, so call EP0in() |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 389 | if (i == 0) { |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 390 | EP0in(); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 391 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 392 | // Clear the interrupt |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 393 | OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 394 | // Stop firing Tx empty interrupts |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 395 | // Will get turned on again if another write is called |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 396 | OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 397 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 398 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 399 | // If the transfer is complete |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 400 | if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 401 | epComplete |= (1 << (1 + (i << 1))); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 402 | OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 403 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 404 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 405 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 406 | OTG_FS->GREGS.GINTSTS = (1 << 18); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 407 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 408 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 409 | if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 410 | SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 411 | OTG_FS->GREGS.GINTSTS = (1 << 3); |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 412 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 413 | } |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 414 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 415 | |
frq08711@LMECWL0871.LME.ST.COM | 1:2a3ae13b45ef | 416 | #endif |