Prasanth B J / Mbed 2 deprecated debugi2ccdms_working_1

cdms_i2c_hardware_test

Dependencies:   FreescaleIAP SimpleDMA mbed-rtos mbed

Fork of standaloneworkingi2c_cdms by Team Fox

i2c.h@160:25a01d8da5d4, 2016-07-06 (annotated)

Committer:
prasanthbj05
Date:
Wed Jul 06 10:17:44 2016 +0000
Revision:
160:25a01d8da5d4
Parent:
157:d99f525edc4c 
cdms_i2c_hardware;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
prasanthbj05 155:80e7c7ff8aaf 1 #define tm_len 135
prasanthbj05 155:80e7c7ff8aaf 2 #define tc_len 134
aniruddhv 52:0bd68655c651 3 #define tc_test_len 135
aniruddhv 52:0bd68655c651 4
ee12b079 146:7fd1ca3a35a1 5 const int addr_bae = 0x20; //slave address
ee12b079 129:d5b53088270b 6 const int addr_pl = 0x20<<1; //PL slave address
ee12b079 131:d4a4461214ad 7
aniruddhv 52:0bd68655c651 8 bool write_ack = true;
aniruddhv 52:0bd68655c651 9 bool read_ack = true;
aniruddhv 52:0bd68655c651 10
ee12b079 131:d4a4461214ad 11
ee12b079 131:d4a4461214ad 12 char PL_I2C_DATA[134];//Payload i2c array
ee12b079 131:d4a4461214ad 13 uint8_t PL_TM_SIZE;//size of data to bev read from i2c
prasanthbj05 157:d99f525edc4c 14 /**************************************************************************************************
prasanthbj05 157:d99f525edc4c 15 ***** *****
prasanthbj05 157:d99f525edc4c 16 ***** Name: KL25Z I2C_busreset.cpp *****
prasanthbj05 157:d99f525edc4c 17 ***** Date: 24/11/2013 *****
prasanthbj05 157:d99f525edc4c 18 ***** Auth: Frank Vannieuwkerke *****
prasanthbj05 157:d99f525edc4c 19 ***** Func: library for unblocking I2C bus on KL25Z board *****
prasanthbj05 157:d99f525edc4c 20 ***** Info: MPL3115A2-AN4481 *****
prasanthbj05 157:d99f525edc4c 21 **************************************************************************************************/
aniruddhv 52:0bd68655c651 22
prasanthbj05 157:d99f525edc4c 23
prasanthbj05 157:d99f525edc4c 24 /*void I2C_busreset(void)
prasanthbj05 157:d99f525edc4c 25 {
prasanthbj05 157:d99f525edc4c 26 if((PORTE->PCR[1] & PORT_PCR_MUX(6)) && (PORTE->PCR[0] & PORT_PCR_MUX(6)))
prasanthbj05 157:d99f525edc4c 27 {
prasanthbj05 157:d99f525edc4c 28 I2C1->C1 &= 0x7f; // Disable I2C1 bus
prasanthbj05 157:d99f525edc4c 29 PORTE->PCR[1] = PORT_PCR_MUX(1); // PTE1 Alt1 (pin)
prasanthbj05 157:d99f525edc4c 30 PORTE->PCR[0] = PORT_PCR_MUX(1); // PTE0 Alt1 (pin)
prasanthbj05 157:d99f525edc4c 31 if((PTE->PDIR & 0x3) != 3) // When PTE0 / PTE1 are not 1 : I2C1 bus lock-up
prasanthbj05 157:d99f525edc4c 32 {
prasanthbj05 157:d99f525edc4c 33 PTE->PDDR |= 0x2; // Set PTE1 as a GPIO output so we can bit bang it
prasanthbj05 157:d99f525edc4c 34 PTE->PDOR |= 0x2; // Set PTE1 (SCL) pin high;
prasanthbj05 157:d99f525edc4c 35 wait_ms(1);
prasanthbj05 157:d99f525edc4c 36 while(!(PTE->PDIR & 0x1)) // bit bang SCL until the offending device releases the bus
prasanthbj05 157:d99f525edc4c 37 {
prasanthbj05 157:d99f525edc4c 38 PTE->PDOR &= 0xfffffffd; // Set PTE1 (SCL) pin low;
prasanthbj05 157:d99f525edc4c 39 wait_ms(1);
prasanthbj05 157:d99f525edc4c 40 PTE->PDOR |= 0x2; // Set PTE1 (SCL) pin high;
prasanthbj05 157:d99f525edc4c 41 wait_ms(1);
prasanthbj05 157:d99f525edc4c 42 }
prasanthbj05 157:d99f525edc4c 43 }
prasanthbj05 157:d99f525edc4c 44 // Reinstate I2C1 bus pins
prasanthbj05 157:d99f525edc4c 45 PORTE->PCR[1] = PORT_PCR_MUX(6); // PTE1 Alt6 (SCL)
prasanthbj05 157:d99f525edc4c 46 PORTE->PCR[0] = PORT_PCR_MUX(6); // PTE0 Alt6 (SDA)
prasanthbj05 157:d99f525edc4c 47 I2C1->C1 |= 0x80; // Enable I2C1 bus
prasanthbj05 157:d99f525edc4c 48 }
prasanthbj05 157:d99f525edc4c 49
prasanthbj05 157:d99f525edc4c 50 if((PORTE->PCR[24] & PORT_PCR_MUX(5)) && (PORTE->PCR[25] & PORT_PCR_MUX(5)))
prasanthbj05 157:d99f525edc4c 51 {
prasanthbj05 157:d99f525edc4c 52 uint8_t count =0;
prasanthbj05 157:d99f525edc4c 53 printf("\n\rEntered");
prasanthbj05 157:d99f525edc4c 54 I2C0->C1 &= 0x7f; // Disable I2C0 bus
prasanthbj05 157:d99f525edc4c 55 PORTE->PCR[24] = PORT_PCR_MUX(1); // PTE24 Alt1 (pin)
prasanthbj05 157:d99f525edc4c 56 PORTE->PCR[25] = PORT_PCR_MUX(1); // PTE25 Alt1 (pin)
prasanthbj05 157:d99f525edc4c 57 if((PTE->PDIR & 0x03000000) != 0x03000000) // When PTE24 / PTE25 are not 1 : I2C0 bus lock-up
prasanthbj05 157:d99f525edc4c 58 {
prasanthbj05 157:d99f525edc4c 59 PTE->PDDR |= 0x01000000; // Set PTE24 as a GPIO output so we can bit bang it
prasanthbj05 157:d99f525edc4c 60 PTE->PDOR |= 0x01000000; // Set PTE24 (SCL) pin high;
prasanthbj05 157:d99f525edc4c 61 wait_ms(1);
prasanthbj05 157:d99f525edc4c 62 while((!(PTE->PDIR & 0x1))&&count<10) // bit bang SCL until the offending device releases the bus
prasanthbj05 157:d99f525edc4c 63 {
prasanthbj05 157:d99f525edc4c 64 PTE->PDOR &= 0xfeffffff; // Set PTE24 (SCL) pin low;
prasanthbj05 157:d99f525edc4c 65 wait_ms(1);
prasanthbj05 157:d99f525edc4c 66 PTE->PDOR |= 0x01000000; // Set PTE24 (SCL) pin high;
prasanthbj05 157:d99f525edc4c 67 wait_ms(1);
prasanthbj05 157:d99f525edc4c 68 count++;
prasanthbj05 157:d99f525edc4c 69 }
prasanthbj05 157:d99f525edc4c 70 }
prasanthbj05 157:d99f525edc4c 71 // Reinstate I2C0 bus pins
prasanthbj05 157:d99f525edc4c 72 PORTE->PCR[24] = PORT_PCR_MUX(5); // PTE24 Alt5 (SCL)
prasanthbj05 157:d99f525edc4c 73 PORTE->PCR[25] = PORT_PCR_MUX(5); // PTE25 Alt5 (SDA)
prasanthbj05 157:d99f525edc4c 74 I2C0->C1 |= 0x80; // Enable I2C0 bus
prasanthbj05 157:d99f525edc4c 75 }
prasanthbj05 157:d99f525edc4c 76 }*/
prasanthbj05 157:d99f525edc4c 77 void debug()
prasanthbj05 157:d99f525edc4c 78 {
prasanthbj05 157:d99f525edc4c 79 //gPC.printf("\n\rPORTE->PCR[24] = 0x%08X",PORTE->PCR[24]);
prasanthbj05 157:d99f525edc4c 80 //gPC.printf("\n\rPORTE->PCR[25] = 0x%08X",PORTE->PCR[25]);
prasanthbj05 157:d99f525edc4c 81 gPC.printf("\n\rPTE->PDIR = 0x%08X",PTE->PDIR);
prasanthbj05 157:d99f525edc4c 82 }
prasanthbj05 157:d99f525edc4c 83 void debug1()
prasanthbj05 157:d99f525edc4c 84 {
prasanthbj05 157:d99f525edc4c 85 gPC.printf("\n\r Before disabling");
prasanthbj05 157:d99f525edc4c 86 debug();
prasanthbj05 157:d99f525edc4c 87 wait(2);
prasanthbj05 157:d99f525edc4c 88 I2C0->C1 &= 0x7f;
prasanthbj05 157:d99f525edc4c 89 gPC.printf("\n\r After disabling");
prasanthbj05 157:d99f525edc4c 90 debug();
prasanthbj05 157:d99f525edc4c 91 I2C0->C1 |= 0x80;
prasanthbj05 157:d99f525edc4c 92 gPC.printf("\n\r After enabling");
prasanthbj05 157:d99f525edc4c 93 debug();
prasanthbj05 157:d99f525edc4c 94 gPC.printf("\n");
prasanthbj05 157:d99f525edc4c 95 }
prasanthbj05 157:d99f525edc4c 96 /*
prasanthbj05 157:d99f525edc4c 97 #define PORT_PCR_MUX_MASK2 0x00000700u
prasanthbj05 157:d99f525edc4c 98
prasanthbj05 157:d99f525edc4c 99 void I2C_busreset(void)
prasanthbj05 157:d99f525edc4c 100 {
prasanthbj05 157:d99f525edc4c 101 uint8_t count=0;
prasanthbj05 157:d99f525edc4c 102 if(((PORTE->PCR[24]&(PORT_PCR_MUX_MASK2))==PORT_PCR_MUX(5)) && ((PORTE->PCR[24]&(PORT_PCR_MUX_MASK2))==PORT_PCR_MUX(5)))
prasanthbj05 157:d99f525edc4c 103 {
prasanthbj05 157:d99f525edc4c 104 gPC.printf("\n\rEntered\n\r");
prasanthbj05 157:d99f525edc4c 105 I2C0->C1 &= 0x7f; // Disable I2C0 bus
prasanthbj05 157:d99f525edc4c 106 PORTE->PCR[24] &= (~(PORT_PCR_MUX_MASK2));
prasanthbj05 157:d99f525edc4c 107 PORTE->PCR[25] &= (~(PORT_PCR_MUX_MASK2));
prasanthbj05 157:d99f525edc4c 108 PORTE->PCR[24] |= PORT_PCR_MUX(1); // PTE24 Alt1 (pin)
prasanthbj05 157:d99f525edc4c 109 PORTE->PCR[25] |= PORT_PCR_MUX(1); // PTE25 Alt1 (pin)
prasanthbj05 157:d99f525edc4c 110 //1011=Interrupt on either edge, check later
prasanthbj05 157:d99f525edc4c 111 if((PTE->PDIR & 0x03000000) != 0x03000000) // When PTE24 / PTE25 are not 1 : I2C0 bus lock-up
prasanthbj05 157:d99f525edc4c 112 {
prasanthbj05 157:d99f525edc4c 113 PTE->PDDR |= 0x01000000; // Set PTE24 as a GPIO output so we can bit bang it
prasanthbj05 157:d99f525edc4c 114 PTE->PDOR |= 0x01000000; // Set PTE24 (SCL) pin high;
prasanthbj05 157:d99f525edc4c 115 wait_ms(1);
prasanthbj05 157:d99f525edc4c 116 while(((PTE->PDIR & 0x01000000) == 0x00000000) && count<10) // bit bang SCL until the offending device releases the bus
prasanthbj05 157:d99f525edc4c 117 {
prasanthbj05 157:d99f525edc4c 118 gPC.printf("Entered\n\r");
prasanthbj05 157:d99f525edc4c 119 PTE->PDOR &= 0xfeffffff; // Set PTE24 (SCL) pin low;
prasanthbj05 157:d99f525edc4c 120 wait_ms(5);
prasanthbj05 157:d99f525edc4c 121 PTE->PDOR |= 0x01000000; // Set PTE24 (SCL) pin high;
prasanthbj05 157:d99f525edc4c 122 wait_ms(5);
prasanthbj05 157:d99f525edc4c 123 count++;
prasanthbj05 157:d99f525edc4c 124 }
prasanthbj05 157:d99f525edc4c 125 }
prasanthbj05 157:d99f525edc4c 126 PORTE->PCR[24] &= (~(PORT_PCR_MUX_MASK2));
prasanthbj05 157:d99f525edc4c 127 PORTE->PCR[25] &= (~(PORT_PCR_MUX_MASK2));
prasanthbj05 157:d99f525edc4c 128 PORTE->PCR[24] |= PORT_PCR_MUX(5); // PTE24 Alt5 (SCL)
prasanthbj05 157:d99f525edc4c 129 PORTE->PCR[25] |= PORT_PCR_MUX(5); // PTE25 Alt5 (SDA)
prasanthbj05 157:d99f525edc4c 130 I2C0->C1 |= 0x80; // Enable I2C0 bus
prasanthbj05 157:d99f525edc4c 131 }
prasanthbj05 157:d99f525edc4c 132 gPC.printf("Count %d\n",count);
prasanthbj05 157:d99f525edc4c 133 }*/
prasanthbj05 157:d99f525edc4c 134 /*void I2C_reInit(void)
prasanthbj05 157:d99f525edc4c 135 {
prasanthbj05 157:d99f525edc4c 136 if((PORTE->PCR[24] & PORT_PCR_MUX(5)) && (PORTE->PCR[25] & PORT_PCR_MUX(5)))
prasanthbj05 157:d99f525edc4c 137 {
prasanthbj05 157:d99f525edc4c 138 gPC.printf("\n\rRe-Initializing I2C");
prasanthbj05 157:d99f525edc4c 139 I2C0->C1 &= 0x7f; // Disable I2C0 bus
prasanthbj05 157:d99f525edc4c 140 PORTE->PCR[24] = PORT_PCR_MUX(1); // PTE24 Alt1 (pin)
prasanthbj05 157:d99f525edc4c 141 PORTE->PCR[25] = PORT_PCR_MUX(1); // PTE25 Alt1 (pin)
prasanthbj05 157:d99f525edc4c 142 PTE->PDDR |= 0x03000000; // Set PTE24 as a GPIO output so we can bit bang it
prasanthbj05 157:d99f525edc4c 143 //wait(5);
prasanthbj05 157:d99f525edc4c 144 if((PTE->PDIR & 0x03000000) != 0x03000000) // When PTE24 / PTE25 are not 1 : I2C1 bus lock-up
prasanthbj05 157:d99f525edc4c 145 {
prasanthbj05 157:d99f525edc4c 146 gPC.printf("\nEntered\n");
prasanthbj05 157:d99f525edc4c 147 //PTE->PDOR |= 0x1; // Set PTE1 (SCL) pin high;
prasanthbj05 157:d99f525edc4c 148 //wait_us(5);
prasanthbj05 157:d99f525edc4c 149 //PTE->PDOR |= 0x2; // Set PTE0 (SDA) pin high;
prasanthbj05 157:d99f525edc4c 150 //wait_us(5);
prasanthbj05 157:d99f525edc4c 151 }
prasanthbj05 157:d99f525edc4c 152 // Reinstate I2C0 bus pins
prasanthbj05 157:d99f525edc4c 153 PORTE->PCR[24] = PORT_PCR_MUX(5); // PTE24 Alt6 (SCL)
prasanthbj05 157:d99f525edc4c 154 PORTE->PCR[25] = PORT_PCR_MUX(5); // PTE25 Alt6 (SDA)
prasanthbj05 157:d99f525edc4c 155 I2C0->C1 |= 0x80; // Enable I2C0 bus
prasanthbj05 157:d99f525edc4c 156 //wait_ms(1);
prasanthbj05 157:d99f525edc4c 157 }
prasanthbj05 157:d99f525edc4c 158 }*/
prasanthbj05 157:d99f525edc4c 159 void debug2()
prasanthbj05 157:d99f525edc4c 160 {
prasanthbj05 157:d99f525edc4c 161 gPC.printf("\n\rI2C0->A1 = 0x%02X",I2C0->A1);
prasanthbj05 157:d99f525edc4c 162 gPC.printf("\n\rI2C0->F = 0x%02X",I2C0->F);
prasanthbj05 157:d99f525edc4c 163 gPC.printf("\n\rI2C0->C1 = 0x%02X",I2C0->C1);
prasanthbj05 157:d99f525edc4c 164 gPC.printf("\n\rI2C0->S = 0x%02X",I2C0->S);
prasanthbj05 157:d99f525edc4c 165 gPC.printf("\n\rI2C0->D = 0x%02X",I2C0->D);
prasanthbj05 157:d99f525edc4c 166 gPC.printf("\n\rI2C0->C2 = 0x%02X",I2C0->C2);
prasanthbj05 157:d99f525edc4c 167 gPC.printf("\n\rI2C0->FLT = 0x%02X",I2C0->FLT);
prasanthbj05 157:d99f525edc4c 168 gPC.printf("\n\rI2C0->RA = 0x%02X",I2C0->RA);
prasanthbj05 157:d99f525edc4c 169 gPC.printf("\n\rI2C0->SMB = 0x%02X",I2C0->SMB);
prasanthbj05 157:d99f525edc4c 170 gPC.printf("\n\rI2C0->A2 = 0x%02X",I2C0->A2);
prasanthbj05 157:d99f525edc4c 171 gPC.printf("\n\rI2C0->SLTH = 0x%02X",I2C0->SLTH);
prasanthbj05 157:d99f525edc4c 172 gPC.printf("\n\rI2C0->SLTL = 0x%02X\n",I2C0->SLTL);
prasanthbj05 157:d99f525edc4c 173 }
prasanthbj05 157:d99f525edc4c 174 void debug3()
prasanthbj05 157:d99f525edc4c 175 {
prasanthbj05 157:d99f525edc4c 176 //gPC.printf("\n\r Resetting I2C");
prasanthbj05 157:d99f525edc4c 177 //debug2();
prasanthbj05 157:d99f525edc4c 178 //gPC.printf("\n\r SIM->SCGC4 = 0x%08X",SIM->SCGC4);
prasanthbj05 157:d99f525edc4c 179 PORTE->PCR[1] &= 0xfffffffb;
prasanthbj05 157:d99f525edc4c 180 PORTE->PCR[0] &= 0xfffffffb;
prasanthbj05 157:d99f525edc4c 181 I2C0->C1 &= 0x7f;
prasanthbj05 157:d99f525edc4c 182 //wait_ms(2);
prasanthbj05 157:d99f525edc4c 183 SIM->SCGC4 &= 0xffffffbf;
prasanthbj05 157:d99f525edc4c 184 //gPC.printf("\n\r SIM->SCGC4 = 0x%08X",SIM->SCGC4);
prasanthbj05 157:d99f525edc4c 185 //wait_ms(10);
prasanthbj05 157:d99f525edc4c 186 SIM->SCGC4 |= 0x00000040;
prasanthbj05 157:d99f525edc4c 187 //gPC.printf("\n\r SIM->SCGC4 = 0x%08X",SIM->SCGC4);
prasanthbj05 157:d99f525edc4c 188 //wait_ms(10);
prasanthbj05 157:d99f525edc4c 189 I2C0->C1 |= 0x80;
prasanthbj05 157:d99f525edc4c 190 PORTE->PCR[1] |= 0x00000004;
prasanthbj05 157:d99f525edc4c 191 PORTE->PCR[0] |= 0x00000004;
prasanthbj05 157:d99f525edc4c 192 //wait_us(0);
prasanthbj05 157:d99f525edc4c 193 wait_ms(2);
prasanthbj05 157:d99f525edc4c 194 //gPC.printf("\n\r After enabling clock");
prasanthbj05 157:d99f525edc4c 195 //debug2();
prasanthbj05 157:d99f525edc4c 196 //gPC.printf("\n");
prasanthbj05 157:d99f525edc4c 197 }
prasanthbj05 157:d99f525edc4c 198 void I2C_busreset()
prasanthbj05 157:d99f525edc4c 199 {
prasanthbj05 157:d99f525edc4c 200 //Thread::wait(1);
prasanthbj05 157:d99f525edc4c 201 PORTE->PCR[1] &= 0xfffffffb;
prasanthbj05 157:d99f525edc4c 202 //Thread::wait(1);
prasanthbj05 157:d99f525edc4c 203 PORTE->PCR[0] &= 0xfffffffb;
prasanthbj05 157:d99f525edc4c 204 //Thread::wait(1);
prasanthbj05 157:d99f525edc4c 205 I2C0->C1 &= 0x7f;
prasanthbj05 157:d99f525edc4c 206 //Thread::wait(1);
prasanthbj05 157:d99f525edc4c 207 SIM->SCGC4 &= 0xffffffbf;
prasanthbj05 157:d99f525edc4c 208 //Thread::wait(1);
prasanthbj05 157:d99f525edc4c 209 SIM->SCGC4 |= 0x00000040;
prasanthbj05 157:d99f525edc4c 210 //Thread::wait(1);
prasanthbj05 157:d99f525edc4c 211 I2C0->C1 |= 0x80;
prasanthbj05 157:d99f525edc4c 212 //Thread::wait(1);
prasanthbj05 157:d99f525edc4c 213 PORTE->PCR[1] |= 0x00000004;
prasanthbj05 157:d99f525edc4c 214 //Thread::wait(1);
prasanthbj05 157:d99f525edc4c 215 PORTE->PCR[0] |= 0x00000004;
prasanthbj05 157:d99f525edc4c 216 Thread::wait(1);
prasanthbj05 157:d99f525edc4c 217 }
prasanthbj05 157:d99f525edc4c 218 /*
prasanthbj05 157:d99f525edc4c 219 #define I2C_busreset {\
prasanthbj05 157:d99f525edc4c 220 PORTE->PCR[1] &= 0xfffffffb;\
prasanthbj05 157:d99f525edc4c 221 Thread::wait(1);\
prasanthbj05 157:d99f525edc4c 222 PORTE->PCR[0] &= 0xfffffffb;\
prasanthbj05 157:d99f525edc4c 223 Thread::wait(1);\
prasanthbj05 157:d99f525edc4c 224 I2C0->C1 &= 0x7f;\
prasanthbj05 157:d99f525edc4c 225 Thread::wait(1);\
prasanthbj05 157:d99f525edc4c 226 SIM->SCGC4 &= 0xffffffbf;\
prasanthbj05 157:d99f525edc4c 227 Thread::wait(1);\
prasanthbj05 157:d99f525edc4c 228 SIM->SCGC4 |= 0x00000040;\
prasanthbj05 157:d99f525edc4c 229 Thread::wait(1);\
prasanthbj05 157:d99f525edc4c 230 I2C0->C1 |= 0x80;\
prasanthbj05 157:d99f525edc4c 231 Thread::wait(1);\
prasanthbj05 157:d99f525edc4c 232 PORTE->PCR[1] |= 0x00000004;\
prasanthbj05 157:d99f525edc4c 233 Thread::wait(1);\
prasanthbj05 157:d99f525edc4c 234 PORTE->PCR[0] |= 0x00000004;\
prasanthbj05 157:d99f525edc4c 235 Thread::wait(1);\
prasanthbj05 157:d99f525edc4c 236 }
prasanthbj05 157:d99f525edc4c 237 */
prasanthbj05 157:d99f525edc4c 238 Timer synch;
ee12b079 129:d5b53088270b 239 void FCTN_I2C_WRITE_PL(char *data2,uint8_t tc_len2)
aniruddhv 52:0bd68655c651 240 {
ee12b079 129:d5b53088270b 241 write_ack = master.write(addr_pl|0x00,data2,tc_len2);//address to be defined in payload
ee12b079 131:d4a4461214ad 242 if(write_ack == 1)
ee12b079 129:d5b53088270b 243 {
prasanthbj05 157:d99f525edc4c 244 printf("\n\rData not sent");
prasanthbj05 157:d99f525edc4c 245 }
ee12b079 129:d5b53088270b 246 else
aniruddhv 52:0bd68655c651 247 {
ee12b079 131:d4a4461214ad 248
prasanthbj05 157:d99f525edc4c 249 }
ee12b079 129:d5b53088270b 250 }
prasanthbj05 157:d99f525edc4c 251 uint32_t pdirr1,pdirr2;
prasanthbj05 157:d99f525edc4c 252 uint32_t pdirw1,pdirw2;
ee12b079 146:7fd1ca3a35a1 253
prasanthbj05 157:d99f525edc4c 254 bool FCTN_I2C_READ(char *data,int length)
prasanthbj05 157:d99f525edc4c 255 {
ee12b079 146:7fd1ca3a35a1 256 CDMS_I2C_GPIO = 1;
prasanthbj05 157:d99f525edc4c 257 //gPC.printf("\n\n\rGiven TM Size : %d",length);
ee12b079 129:d5b53088270b 258 //t_read.start();
prasanthbj05 157:d99f525edc4c 259 //gPC.printf("\n\rEntered read");
prasanthbj05 157:d99f525edc4c 260 //Thread::wait(1);
ee12b079 146:7fd1ca3a35a1 261 read_ack = master.read(addr_bae|1,data,length);
prasanthbj05 157:d99f525edc4c 262 //gPC.printf("\n\rExited read");
prasanthbj05 157:d99f525edc4c 263 Thread::wait(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms
prasanthbj05 157:d99f525edc4c 264 pdirr1=PTE->PDIR;
prasanthbj05 157:d99f525edc4c 265 uint8_t i2c_count = 0;
prasanthbj05 155:80e7c7ff8aaf 266 if(read_ack == 0)
aniruddhv 52:0bd68655c651 267 {
prasanthbj05 157:d99f525edc4c 268 while(((pdirr1 & 0x03000000)!=0x03000000)&& i2c_count<10)
prasanthbj05 157:d99f525edc4c 269 {
prasanthbj05 157:d99f525edc4c 270 Thread::wait(1);
prasanthbj05 157:d99f525edc4c 271 pdirr1=PTE->PDIR;
prasanthbj05 157:d99f525edc4c 272 i2c_count++;
prasanthbj05 157:d99f525edc4c 273 }
prasanthbj05 157:d99f525edc4c 274 if(((pdirr1 & 0x03000000)==0x03000000))
prasanthbj05 157:d99f525edc4c 275 {
prasanthbj05 157:d99f525edc4c 276 gPC.printf("\n\rData received from BAE");
prasanthbj05 157:d99f525edc4c 277 //printf("Telemetry : %d\n\r",data);
prasanthbj05 157:d99f525edc4c 278 }
prasanthbj05 157:d99f525edc4c 279 else
prasanthbj05 157:d99f525edc4c 280 {
prasanthbj05 157:d99f525edc4c 281 #if PRINT
prasanthbj05 157:d99f525edc4c 282 gPC.printf("\n\rData not received");
prasanthbj05 157:d99f525edc4c 283 gPC.printf("\n\rPTE->DIR = 0x%08X",pdirr1);
prasanthbj05 157:d99f525edc4c 284 #endif
prasanthbj05 157:d99f525edc4c 285 I2C_busreset();
prasanthbj05 157:d99f525edc4c 286 pdirr2=PTE->PDIR;
prasanthbj05 157:d99f525edc4c 287 #if PRINT
prasanthbj05 157:d99f525edc4c 288 gPC.printf("\n\rPTE->DIR = 0x%08X",pdirr2);
prasanthbj05 157:d99f525edc4c 289 #endif
prasanthbj05 157:d99f525edc4c 290 read_ack = 1;
prasanthbj05 157:d99f525edc4c 291 }
prasanthbj05 157:d99f525edc4c 292 //gPC.printf("\n\rRead count:%d",i2c_count);
aniruddhv 52:0bd68655c651 293 }
prasanthbj05 157:d99f525edc4c 294 else if (read_ack == 1)
prasanthbj05 157:d99f525edc4c 295 {
prasanthbj05 157:d99f525edc4c 296 //Thread::wait(10);
prasanthbj05 157:d99f525edc4c 297 #if PRINT
prasanthbj05 157:d99f525edc4c 298 gPC.printf("\n\rRead Ack failed");
prasanthbj05 157:d99f525edc4c 299 gPC.printf("\n\rPTE->DIR = 0x%08X",pdirr1);
prasanthbj05 157:d99f525edc4c 300 #endif
prasanthbj05 157:d99f525edc4c 301 I2C_busreset();
prasanthbj05 157:d99f525edc4c 302 //wait(1);
prasanthbj05 157:d99f525edc4c 303 pdirr2=PTE->PDIR;
prasanthbj05 157:d99f525edc4c 304 #if PRINT
prasanthbj05 157:d99f525edc4c 305 gPC.printf("\n\rPTE->DIR = 0x%08X",pdirr2);
prasanthbj05 157:d99f525edc4c 306 #endif
prasanthbj05 157:d99f525edc4c 307 //wait_ms(30);
prasanthbj05 157:d99f525edc4c 308 //gPC.printf("\n\rPTE->DIR = 0x%08X",PTE->PDIR);
prasanthbj05 157:d99f525edc4c 309 //debug3();
prasanthbj05 157:d99f525edc4c 310 //gPC.printf("\n\rPTE->DIR = 0x%08X",PTE->PDIR);
prasanthbj05 157:d99f525edc4c 311 //wait_ms(30);
prasanthbj05 157:d99f525edc4c 312 }
prasanthbj05 157:d99f525edc4c 313 //gPC.printf("\n\rPTE->DIR = 0x%08X",pdirr1);
prasanthbj05 157:d99f525edc4c 314 //gPC.printf("\n\rPORTE->PCR[24] = 0x%08X",PORTE->PCR[24]);
prasanthbj05 157:d99f525edc4c 315 //gPC.printf("\n\rPORTE->PCR[25] = 0x%08X",PORTE->PCR[25]);
prasanthbj05 157:d99f525edc4c 316
prasanthbj05 157:d99f525edc4c 317 //if(temp==2)
prasanthbj05 157:d99f525edc4c 318 //debug();
prasanthbj05 157:d99f525edc4c 319 //else
prasanthbj05 157:d99f525edc4c 320 //debug();
ee12b079 146:7fd1ca3a35a1 321 CDMS_I2C_GPIO = 0;
prasanthbj05 157:d99f525edc4c 322 i2c_count = 0;
prasanthbj05 157:d99f525edc4c 323 return read_ack;
shreeshas95 104:b55559925dc1 324 //printf("\n\r %d \n",t.read_us());
aniruddhv 52:0bd68655c651 325 //t.reset();
ee12b079 129:d5b53088270b 326 }
ee12b079 129:d5b53088270b 327
prasanthbj05 157:d99f525edc4c 328 bool FCTN_I2C_WRITE(char *data,int tc_len2)
prasanthbj05 157:d99f525edc4c 329 {
ee12b079 146:7fd1ca3a35a1 330 CDMS_I2C_GPIO = 1;
prasanthbj05 157:d99f525edc4c 331 //synch.start();
ee12b079 129:d5b53088270b 332 //t.start();
prasanthbj05 157:d99f525edc4c 333 //wait_us(300);
prasanthbj05 157:d99f525edc4c 334 //Thread::wait(1);
prasanthbj05 157:d99f525edc4c 335 //synch.stop();
prasanthbj05 157:d99f525edc4c 336 temp_flag = 1;
prasanthbj05 157:d99f525edc4c 337 write_ack = master.write(addr_bae|0x00,data,tc_len2);
prasanthbj05 157:d99f525edc4c 338 if(temp_flag==1)
prasanthbj05 157:d99f525edc4c 339 temp_flag = 0;
prasanthbj05 157:d99f525edc4c 340 Thread::wait(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms
prasanthbj05 157:d99f525edc4c 341 pdirw1=PTE->PDIR;
prasanthbj05 157:d99f525edc4c 342 uint8_t i2c_count = 0;
ee12b079 129:d5b53088270b 343 //t.stop();
prasanthbj05 157:d99f525edc4c 344 //gPC.printf("\n\n\rGiven TC Size : %d",tc_len2);
prasanthbj05 157:d99f525edc4c 345 //printf("\n\rTelecommand: ");
prasanthbj05 157:d99f525edc4c 346 //for(uint8_t j=0;j<11;j++)
prasanthbj05 157:d99f525edc4c 347 //printf("%02x ",data[j]);
prasanthbj05 155:80e7c7ff8aaf 348 if(write_ack == 0)
ee12b079 129:d5b53088270b 349 {
prasanthbj05 157:d99f525edc4c 350 while(((pdirw1 & 0x03000000)!=0x03000000)&& i2c_count<10)
prasanthbj05 157:d99f525edc4c 351 {
prasanthbj05 157:d99f525edc4c 352 Thread::wait(1);
prasanthbj05 157:d99f525edc4c 353 pdirw1=PTE->PDIR;
prasanthbj05 157:d99f525edc4c 354 i2c_count++;
prasanthbj05 157:d99f525edc4c 355 }
prasanthbj05 157:d99f525edc4c 356 if(((pdirw1 & 0x03000000)==0x03000000))
prasanthbj05 157:d99f525edc4c 357 {
prasanthbj05 157:d99f525edc4c 358 gPC.printf("\n\r Data sent");
prasanthbj05 157:d99f525edc4c 359 //gPC.printf("\n\rPTE->DIR = 0x%08X",PTE->PDIR);
prasanthbj05 157:d99f525edc4c 360 }
prasanthbj05 157:d99f525edc4c 361 else
prasanthbj05 157:d99f525edc4c 362 {
prasanthbj05 157:d99f525edc4c 363 #if PRINT
prasanthbj05 157:d99f525edc4c 364 gPC.printf("\n\r Data not sent");
prasanthbj05 157:d99f525edc4c 365 gPC.printf("\n\rPTE->DIR = 0x%08X",PTE->PDIR);
prasanthbj05 157:d99f525edc4c 366 #endif
prasanthbj05 157:d99f525edc4c 367 I2C_busreset();
prasanthbj05 157:d99f525edc4c 368 //pdirw2=PTE->PDIR;
prasanthbj05 157:d99f525edc4c 369 #if PRINT
prasanthbj05 157:d99f525edc4c 370 gPC.printf("\n\rPTE->DIR = 0x%08X",PTE->PDIR);
prasanthbj05 157:d99f525edc4c 371 #endif
prasanthbj05 157:d99f525edc4c 372 write_ack = 1;
prasanthbj05 157:d99f525edc4c 373 }
prasanthbj05 157:d99f525edc4c 374 //gPC.printf("\n\rWrite count:%d",i2c_count);
prasanthbj05 157:d99f525edc4c 375 }
prasanthbj05 157:d99f525edc4c 376 if (write_ack == 1)
prasanthbj05 157:d99f525edc4c 377 {
prasanthbj05 157:d99f525edc4c 378 #if PRINT
prasanthbj05 157:d99f525edc4c 379 gPC.printf("\n\rWrite Ack failed");
prasanthbj05 157:d99f525edc4c 380 gPC.printf("\n\rPTE->DIR = 0x%08X",PTE->PDIR);
prasanthbj05 157:d99f525edc4c 381 #endif
prasanthbj05 157:d99f525edc4c 382 I2C_busreset();
prasanthbj05 157:d99f525edc4c 383 //pdirw2=PTE->PDIR;
prasanthbj05 157:d99f525edc4c 384 #if PRINT
prasanthbj05 157:d99f525edc4c 385 gPC.printf("\n\rPTE->DIR = 0x%08X",PTE->PDIR);
prasanthbj05 157:d99f525edc4c 386 #endif
ee12b079 129:d5b53088270b 387 }
prasanthbj05 157:d99f525edc4c 388 //gPC.printf("\n\rPTE->DIR = 0x%08X",pdirw1);
prasanthbj05 157:d99f525edc4c 389 //wait_ms(10);
prasanthbj05 157:d99f525edc4c 390 //debug();
ee12b079 146:7fd1ca3a35a1 391 CDMS_I2C_GPIO = 0;
prasanthbj05 157:d99f525edc4c 392 i2c_count = 0;
prasanthbj05 157:d99f525edc4c 393 //gPC.printf("Time after master.write() = %d",synch.read_us());
prasanthbj05 157:d99f525edc4c 394 //synch.reset();
prasanthbj05 157:d99f525edc4c 395 return write_ack;
ee12b079 129:d5b53088270b 396 //gPC.printf("\n\r %d \n",t.read_us());
ee12b079 129:d5b53088270b 397 //t.reset();
aniruddhv 52:0bd68655c651 398 }