cdms_rtos_v1_1_test_sat - aadadf

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Pradeep Kotipalli / Mbed 2 deprecated cdms_rtos_v1_1_test_sat

aadadf

Fork of cdms_rtos_v1_1_test by Team Fox

MKL46Z4.h@1:c0c5ac8eac80, 2015-11-07 (annotated)

Committer:: pradeepvk2208
Date:: Sat Nov 07 12:06:40 2015 +0000
Revision:: 1:c0c5ac8eac80

hey cdms_pl

Who changed what in which revision?

User	Revision	Line number	New contents of line
pradeepvk2208	1:c0c5ac8eac80	1	/*
pradeepvk2208	1:c0c5ac8eac80	2	** ###################################################################
pradeepvk2208	1:c0c5ac8eac80	3	** Processors: MKL46Z256VLH4
pradeepvk2208	1:c0c5ac8eac80	4	** MKL46Z128VLH4
pradeepvk2208	1:c0c5ac8eac80	5	** MKL46Z256VLL4
pradeepvk2208	1:c0c5ac8eac80	6	** MKL46Z128VLL4
pradeepvk2208	1:c0c5ac8eac80	7	** MKL46Z256VMC4
pradeepvk2208	1:c0c5ac8eac80	8	** MKL46Z128VMC4
pradeepvk2208	1:c0c5ac8eac80	9	**
pradeepvk2208	1:c0c5ac8eac80	10	** Compilers: ARM Compiler
pradeepvk2208	1:c0c5ac8eac80	11	** Freescale C/C++ for Embedded ARM
pradeepvk2208	1:c0c5ac8eac80	12	** GNU C Compiler
pradeepvk2208	1:c0c5ac8eac80	13	** IAR ANSI C/C++ Compiler for ARM
pradeepvk2208	1:c0c5ac8eac80	14	**
pradeepvk2208	1:c0c5ac8eac80	15	** Reference manual: KL46P121M48SF4RM, Rev.2, Dec 2012
pradeepvk2208	1:c0c5ac8eac80	16	** Version: rev. 2.2, 2013-04-12
pradeepvk2208	1:c0c5ac8eac80	17	**
pradeepvk2208	1:c0c5ac8eac80	18	** Abstract:
pradeepvk2208	1:c0c5ac8eac80	19	** CMSIS Peripheral Access Layer for MKL46Z4
pradeepvk2208	1:c0c5ac8eac80	20	**
pradeepvk2208	1:c0c5ac8eac80	21	** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
pradeepvk2208	1:c0c5ac8eac80	22	**
pradeepvk2208	1:c0c5ac8eac80	23	** http: www.freescale.com
pradeepvk2208	1:c0c5ac8eac80	24	** mail: support@freescale.com
pradeepvk2208	1:c0c5ac8eac80	25	**
pradeepvk2208	1:c0c5ac8eac80	26	** Revisions:
pradeepvk2208	1:c0c5ac8eac80	27	** - rev. 1.0 (2012-10-16)
pradeepvk2208	1:c0c5ac8eac80	28	** Initial version.
pradeepvk2208	1:c0c5ac8eac80	29	** - rev. 2.0 (2012-12-12)
pradeepvk2208	1:c0c5ac8eac80	30	** Update to reference manual rev. 1.
pradeepvk2208	1:c0c5ac8eac80	31	** - rev. 2.1 (2013-04-05)
pradeepvk2208	1:c0c5ac8eac80	32	** Changed start of doxygen comment.
pradeepvk2208	1:c0c5ac8eac80	33	** - rev. 2.2 (2013-04-12)
pradeepvk2208	1:c0c5ac8eac80	34	** SystemInit function fixed for clock configuration 1.
pradeepvk2208	1:c0c5ac8eac80	35	** Name of the interrupt num. 31 updated to reflect proper function.
pradeepvk2208	1:c0c5ac8eac80	36	**
pradeepvk2208	1:c0c5ac8eac80	37	** ###################################################################
pradeepvk2208	1:c0c5ac8eac80	38	*/
pradeepvk2208	1:c0c5ac8eac80	39
pradeepvk2208	1:c0c5ac8eac80	40	/*!
pradeepvk2208	1:c0c5ac8eac80	41	* @file MKL46Z4.h
pradeepvk2208	1:c0c5ac8eac80	42	* @version 2.2
pradeepvk2208	1:c0c5ac8eac80	43	* @date 2013-04-12
pradeepvk2208	1:c0c5ac8eac80	44	* @brief CMSIS Peripheral Access Layer for MKL46Z4
pradeepvk2208	1:c0c5ac8eac80	45	*
pradeepvk2208	1:c0c5ac8eac80	46	* CMSIS Peripheral Access Layer for MKL46Z4
pradeepvk2208	1:c0c5ac8eac80	47	*/
pradeepvk2208	1:c0c5ac8eac80	48
pradeepvk2208	1:c0c5ac8eac80	49	#if !defined(MKL46Z4_H_)
pradeepvk2208	1:c0c5ac8eac80	50	#define MKL46Z4_H_ /*< Symbol preventing repeated inclusion /
pradeepvk2208	1:c0c5ac8eac80	51
pradeepvk2208	1:c0c5ac8eac80	52	/** Memory map major version (memory maps with equal major version number are
pradeepvk2208	1:c0c5ac8eac80	53	* compatible) */
pradeepvk2208	1:c0c5ac8eac80	54	#define MCU_MEM_MAP_VERSION 0x0200u
pradeepvk2208	1:c0c5ac8eac80	55	/** Memory map minor version */
pradeepvk2208	1:c0c5ac8eac80	56	#define MCU_MEM_MAP_VERSION_MINOR 0x0002u
pradeepvk2208	1:c0c5ac8eac80	57
pradeepvk2208	1:c0c5ac8eac80	58
pradeepvk2208	1:c0c5ac8eac80	59	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	60	-- Interrupt vector numbers
pradeepvk2208	1:c0c5ac8eac80	61	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	62
pradeepvk2208	1:c0c5ac8eac80	63	/*!
pradeepvk2208	1:c0c5ac8eac80	64	* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
pradeepvk2208	1:c0c5ac8eac80	65	* @{
pradeepvk2208	1:c0c5ac8eac80	66	*/
pradeepvk2208	1:c0c5ac8eac80	67
pradeepvk2208	1:c0c5ac8eac80	68	/** Interrupt Number Definitions */
pradeepvk2208	1:c0c5ac8eac80	69	typedef enum IRQn {
pradeepvk2208	1:c0c5ac8eac80	70	/* Core interrupts */
pradeepvk2208	1:c0c5ac8eac80	71	NonMaskableInt_IRQn = -14, /*< Non Maskable Interrupt /
pradeepvk2208	1:c0c5ac8eac80	72	HardFault_IRQn = -13, /*< Cortex-M0 SV Hard Fault Interrupt /
pradeepvk2208	1:c0c5ac8eac80	73	SVCall_IRQn = -5, /*< Cortex-M0 SV Call Interrupt /
pradeepvk2208	1:c0c5ac8eac80	74	PendSV_IRQn = -2, /*< Cortex-M0 Pend SV Interrupt /
pradeepvk2208	1:c0c5ac8eac80	75	SysTick_IRQn = -1, /*< Cortex-M0 System Tick Interrupt /
pradeepvk2208	1:c0c5ac8eac80	76
pradeepvk2208	1:c0c5ac8eac80	77	/* Device specific interrupts */
pradeepvk2208	1:c0c5ac8eac80	78	DMA0_IRQn = 0, /*< DMA channel 0 transfer complete/error interrupt /
pradeepvk2208	1:c0c5ac8eac80	79	DMA1_IRQn = 1, /*< DMA channel 1 transfer complete/error interrupt /
pradeepvk2208	1:c0c5ac8eac80	80	DMA2_IRQn = 2, /*< DMA channel 2 transfer complete/error interrupt /
pradeepvk2208	1:c0c5ac8eac80	81	DMA3_IRQn = 3, /*< DMA channel 3 transfer complete/error interrupt /
pradeepvk2208	1:c0c5ac8eac80	82	Reserved20_IRQn = 4, /*< Reserved interrupt 20 /
pradeepvk2208	1:c0c5ac8eac80	83	FTFA_IRQn = 5, /*< FTFA command complete/read collision interrupt /
pradeepvk2208	1:c0c5ac8eac80	84	LVD_LVW_IRQn = 6, /*< Low Voltage Detect, Low Voltage Warning /
pradeepvk2208	1:c0c5ac8eac80	85	LLW_IRQn = 7, /*< Low Leakage Wakeup /
pradeepvk2208	1:c0c5ac8eac80	86	I2C0_IRQn = 8, /*< I2C0 interrupt /
pradeepvk2208	1:c0c5ac8eac80	87	I2C1_IRQn = 9, /*< I2C0 interrupt 25 /
pradeepvk2208	1:c0c5ac8eac80	88	SPI0_IRQn = 10, /*< SPI0 interrupt /
pradeepvk2208	1:c0c5ac8eac80	89	SPI1_IRQn = 11, /*< SPI1 interrupt /
pradeepvk2208	1:c0c5ac8eac80	90	UART0_IRQn = 12, /*< UART0 status/error interrupt /
pradeepvk2208	1:c0c5ac8eac80	91	UART1_IRQn = 13, /*< UART1 status/error interrupt /
pradeepvk2208	1:c0c5ac8eac80	92	UART2_IRQn = 14, /*< UART2 status/error interrupt /
pradeepvk2208	1:c0c5ac8eac80	93	ADC0_IRQn = 15, /*< ADC0 interrupt /
pradeepvk2208	1:c0c5ac8eac80	94	CMP0_IRQn = 16, /*< CMP0 interrupt /
pradeepvk2208	1:c0c5ac8eac80	95	TPM0_IRQn = 17, /*< TPM0 fault, overflow and channels interrupt /
pradeepvk2208	1:c0c5ac8eac80	96	TPM1_IRQn = 18, /*< TPM1 fault, overflow and channels interrupt /
pradeepvk2208	1:c0c5ac8eac80	97	TPM2_IRQn = 19, /*< TPM2 fault, overflow and channels interrupt /
pradeepvk2208	1:c0c5ac8eac80	98	RTC_IRQn = 20, /*< RTC interrupt /
pradeepvk2208	1:c0c5ac8eac80	99	RTC_Seconds_IRQn = 21, /*< RTC seconds interrupt /
pradeepvk2208	1:c0c5ac8eac80	100	PIT_IRQn = 22, /*< PIT timer interrupt /
pradeepvk2208	1:c0c5ac8eac80	101	I2S0_IRQn = 23, /*< I2S0 transmit interrupt /
pradeepvk2208	1:c0c5ac8eac80	102	USB0_IRQn = 24, /*< USB0 interrupt /
pradeepvk2208	1:c0c5ac8eac80	103	DAC0_IRQn = 25, /*< DAC0 interrupt /
pradeepvk2208	1:c0c5ac8eac80	104	TSI0_IRQn = 26, /*< TSI0 interrupt /
pradeepvk2208	1:c0c5ac8eac80	105	MCG_IRQn = 27, /*< MCG interrupt /
pradeepvk2208	1:c0c5ac8eac80	106	LPTimer_IRQn = 28, /*< LPTimer interrupt /
pradeepvk2208	1:c0c5ac8eac80	107	LCD_IRQn = 29, /*< Segment LCD Interrupt /
pradeepvk2208	1:c0c5ac8eac80	108	PORTA_IRQn = 30, /*< Port A interrupt /
pradeepvk2208	1:c0c5ac8eac80	109	PORTC_PORTD_IRQn = 31 /*< Port C and port D interrupt /
pradeepvk2208	1:c0c5ac8eac80	110	} IRQn_Type;
pradeepvk2208	1:c0c5ac8eac80	111
pradeepvk2208	1:c0c5ac8eac80	112	/*!
pradeepvk2208	1:c0c5ac8eac80	113	* @}
pradeepvk2208	1:c0c5ac8eac80	114	/ / end of group Interrupt_vector_numbers */
pradeepvk2208	1:c0c5ac8eac80	115
pradeepvk2208	1:c0c5ac8eac80	116
pradeepvk2208	1:c0c5ac8eac80	117	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	118	-- Cortex M0 Core Configuration
pradeepvk2208	1:c0c5ac8eac80	119	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	120
pradeepvk2208	1:c0c5ac8eac80	121	/*!
pradeepvk2208	1:c0c5ac8eac80	122	* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
pradeepvk2208	1:c0c5ac8eac80	123	* @{
pradeepvk2208	1:c0c5ac8eac80	124	*/
pradeepvk2208	1:c0c5ac8eac80	125
pradeepvk2208	1:c0c5ac8eac80	126	#define __CM0PLUS_REV 0x0000 /*< Core revision r0p0 /
pradeepvk2208	1:c0c5ac8eac80	127	#define __MPU_PRESENT 0 /*< Defines if an MPU is present or not /
pradeepvk2208	1:c0c5ac8eac80	128	#define __VTOR_PRESENT 1 /*< Defines if an MPU is present or not /
pradeepvk2208	1:c0c5ac8eac80	129	#define __NVIC_PRIO_BITS 2 /*< Number of priority bits implemented in the NVIC /
pradeepvk2208	1:c0c5ac8eac80	130	#define __Vendor_SysTickConfig 0 /*< Vendor specific implementation of SysTickConfig is defined /
pradeepvk2208	1:c0c5ac8eac80	131
pradeepvk2208	1:c0c5ac8eac80	132	#include "core_cm0plus.h" /* Core Peripheral Access Layer */
pradeepvk2208	1:c0c5ac8eac80	133	#include "system_MKL46Z4.h" /* Device specific configuration file */
pradeepvk2208	1:c0c5ac8eac80	134
pradeepvk2208	1:c0c5ac8eac80	135	/*!
pradeepvk2208	1:c0c5ac8eac80	136	* @}
pradeepvk2208	1:c0c5ac8eac80	137	/ / end of group Cortex_Core_Configuration */
pradeepvk2208	1:c0c5ac8eac80	138
pradeepvk2208	1:c0c5ac8eac80	139
pradeepvk2208	1:c0c5ac8eac80	140	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	141	-- Device Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	142	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	143
pradeepvk2208	1:c0c5ac8eac80	144	/*!
pradeepvk2208	1:c0c5ac8eac80	145	* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	146	* @{
pradeepvk2208	1:c0c5ac8eac80	147	*/
pradeepvk2208	1:c0c5ac8eac80	148
pradeepvk2208	1:c0c5ac8eac80	149
pradeepvk2208	1:c0c5ac8eac80	150	/*
pradeepvk2208	1:c0c5ac8eac80	151	** Start of section using anonymous unions
pradeepvk2208	1:c0c5ac8eac80	152	*/
pradeepvk2208	1:c0c5ac8eac80	153
pradeepvk2208	1:c0c5ac8eac80	154	#if defined(__ARMCC_VERSION)
pradeepvk2208	1:c0c5ac8eac80	155	#pragma push
pradeepvk2208	1:c0c5ac8eac80	156	#pragma anon_unions
pradeepvk2208	1:c0c5ac8eac80	157	#elif defined(__CWCC__)
pradeepvk2208	1:c0c5ac8eac80	158	#pragma push
pradeepvk2208	1:c0c5ac8eac80	159	#pragma cpp_extensions on
pradeepvk2208	1:c0c5ac8eac80	160	#elif defined(__GNUC__)
pradeepvk2208	1:c0c5ac8eac80	161	/* anonymous unions are enabled by default */
pradeepvk2208	1:c0c5ac8eac80	162	#elif defined(__IAR_SYSTEMS_ICC__)
pradeepvk2208	1:c0c5ac8eac80	163	#pragma language=extended
pradeepvk2208	1:c0c5ac8eac80	164	#else
pradeepvk2208	1:c0c5ac8eac80	165	#error Not supported compiler type
pradeepvk2208	1:c0c5ac8eac80	166	#endif
pradeepvk2208	1:c0c5ac8eac80	167
pradeepvk2208	1:c0c5ac8eac80	168	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	169	-- ADC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	170	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	171
pradeepvk2208	1:c0c5ac8eac80	172	/*!
pradeepvk2208	1:c0c5ac8eac80	173	* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	174	* @{
pradeepvk2208	1:c0c5ac8eac80	175	*/
pradeepvk2208	1:c0c5ac8eac80	176
pradeepvk2208	1:c0c5ac8eac80	177	/** ADC - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	178	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	179	__IO uint32_t SC1[2]; /*< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	180	__IO uint32_t CFG1; /*< ADC Configuration Register 1, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	181	__IO uint32_t CFG2; /*< ADC Configuration Register 2, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	182	__I uint32_t R[2]; /*< ADC Data Result Register, array offset: 0x10, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	183	__IO uint32_t CV1; /*< Compare Value Registers, offset: 0x18 /
pradeepvk2208	1:c0c5ac8eac80	184	__IO uint32_t CV2; /*< Compare Value Registers, offset: 0x1C /
pradeepvk2208	1:c0c5ac8eac80	185	__IO uint32_t SC2; /*< Status and Control Register 2, offset: 0x20 /
pradeepvk2208	1:c0c5ac8eac80	186	__IO uint32_t SC3; /*< Status and Control Register 3, offset: 0x24 /
pradeepvk2208	1:c0c5ac8eac80	187	__IO uint32_t OFS; /*< ADC Offset Correction Register, offset: 0x28 /
pradeepvk2208	1:c0c5ac8eac80	188	__IO uint32_t PG; /*< ADC Plus-Side Gain Register, offset: 0x2C /
pradeepvk2208	1:c0c5ac8eac80	189	__IO uint32_t MG; /*< ADC Minus-Side Gain Register, offset: 0x30 /
pradeepvk2208	1:c0c5ac8eac80	190	__IO uint32_t CLPD; /*< ADC Plus-Side General Calibration Value Register, offset: 0x34 /
pradeepvk2208	1:c0c5ac8eac80	191	__IO uint32_t CLPS; /*< ADC Plus-Side General Calibration Value Register, offset: 0x38 /
pradeepvk2208	1:c0c5ac8eac80	192	__IO uint32_t CLP4; /*< ADC Plus-Side General Calibration Value Register, offset: 0x3C /
pradeepvk2208	1:c0c5ac8eac80	193	__IO uint32_t CLP3; /*< ADC Plus-Side General Calibration Value Register, offset: 0x40 /
pradeepvk2208	1:c0c5ac8eac80	194	__IO uint32_t CLP2; /*< ADC Plus-Side General Calibration Value Register, offset: 0x44 /
pradeepvk2208	1:c0c5ac8eac80	195	__IO uint32_t CLP1; /*< ADC Plus-Side General Calibration Value Register, offset: 0x48 /
pradeepvk2208	1:c0c5ac8eac80	196	__IO uint32_t CLP0; /*< ADC Plus-Side General Calibration Value Register, offset: 0x4C /
pradeepvk2208	1:c0c5ac8eac80	197	uint8_t RESERVED_0[4];
pradeepvk2208	1:c0c5ac8eac80	198	__IO uint32_t CLMD; /*< ADC Minus-Side General Calibration Value Register, offset: 0x54 /
pradeepvk2208	1:c0c5ac8eac80	199	__IO uint32_t CLMS; /*< ADC Minus-Side General Calibration Value Register, offset: 0x58 /
pradeepvk2208	1:c0c5ac8eac80	200	__IO uint32_t CLM4; /*< ADC Minus-Side General Calibration Value Register, offset: 0x5C /
pradeepvk2208	1:c0c5ac8eac80	201	__IO uint32_t CLM3; /*< ADC Minus-Side General Calibration Value Register, offset: 0x60 /
pradeepvk2208	1:c0c5ac8eac80	202	__IO uint32_t CLM2; /*< ADC Minus-Side General Calibration Value Register, offset: 0x64 /
pradeepvk2208	1:c0c5ac8eac80	203	__IO uint32_t CLM1; /*< ADC Minus-Side General Calibration Value Register, offset: 0x68 /
pradeepvk2208	1:c0c5ac8eac80	204	__IO uint32_t CLM0; /*< ADC Minus-Side General Calibration Value Register, offset: 0x6C /
pradeepvk2208	1:c0c5ac8eac80	205	} ADC_Type;
pradeepvk2208	1:c0c5ac8eac80	206
pradeepvk2208	1:c0c5ac8eac80	207	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	208	-- ADC Register Masks
pradeepvk2208	1:c0c5ac8eac80	209	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	210
pradeepvk2208	1:c0c5ac8eac80	211	/*!
pradeepvk2208	1:c0c5ac8eac80	212	* @addtogroup ADC_Register_Masks ADC Register Masks
pradeepvk2208	1:c0c5ac8eac80	213	* @{
pradeepvk2208	1:c0c5ac8eac80	214	*/
pradeepvk2208	1:c0c5ac8eac80	215
pradeepvk2208	1:c0c5ac8eac80	216	/* SC1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	217	#define ADC_SC1_ADCH_MASK 0x1Fu
pradeepvk2208	1:c0c5ac8eac80	218	#define ADC_SC1_ADCH_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	219	#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
pradeepvk2208	1:c0c5ac8eac80	220	#define ADC_SC1_DIFF_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	221	#define ADC_SC1_DIFF_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	222	#define ADC_SC1_AIEN_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	223	#define ADC_SC1_AIEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	224	#define ADC_SC1_COCO_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	225	#define ADC_SC1_COCO_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	226	/* CFG1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	227	#define ADC_CFG1_ADICLK_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	228	#define ADC_CFG1_ADICLK_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	229	#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
pradeepvk2208	1:c0c5ac8eac80	230	#define ADC_CFG1_MODE_MASK 0xCu
pradeepvk2208	1:c0c5ac8eac80	231	#define ADC_CFG1_MODE_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	232	#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
pradeepvk2208	1:c0c5ac8eac80	233	#define ADC_CFG1_ADLSMP_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	234	#define ADC_CFG1_ADLSMP_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	235	#define ADC_CFG1_ADIV_MASK 0x60u
pradeepvk2208	1:c0c5ac8eac80	236	#define ADC_CFG1_ADIV_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	237	#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
pradeepvk2208	1:c0c5ac8eac80	238	#define ADC_CFG1_ADLPC_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	239	#define ADC_CFG1_ADLPC_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	240	/* CFG2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	241	#define ADC_CFG2_ADLSTS_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	242	#define ADC_CFG2_ADLSTS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	243	#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
pradeepvk2208	1:c0c5ac8eac80	244	#define ADC_CFG2_ADHSC_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	245	#define ADC_CFG2_ADHSC_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	246	#define ADC_CFG2_ADACKEN_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	247	#define ADC_CFG2_ADACKEN_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	248	#define ADC_CFG2_MUXSEL_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	249	#define ADC_CFG2_MUXSEL_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	250	/* R Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	251	#define ADC_R_D_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	252	#define ADC_R_D_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	253	#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
pradeepvk2208	1:c0c5ac8eac80	254	/* CV1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	255	#define ADC_CV1_CV_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	256	#define ADC_CV1_CV_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	257	#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
pradeepvk2208	1:c0c5ac8eac80	258	/* CV2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	259	#define ADC_CV2_CV_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	260	#define ADC_CV2_CV_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	261	#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
pradeepvk2208	1:c0c5ac8eac80	262	/* SC2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	263	#define ADC_SC2_REFSEL_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	264	#define ADC_SC2_REFSEL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	265	#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
pradeepvk2208	1:c0c5ac8eac80	266	#define ADC_SC2_DMAEN_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	267	#define ADC_SC2_DMAEN_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	268	#define ADC_SC2_ACREN_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	269	#define ADC_SC2_ACREN_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	270	#define ADC_SC2_ACFGT_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	271	#define ADC_SC2_ACFGT_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	272	#define ADC_SC2_ACFE_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	273	#define ADC_SC2_ACFE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	274	#define ADC_SC2_ADTRG_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	275	#define ADC_SC2_ADTRG_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	276	#define ADC_SC2_ADACT_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	277	#define ADC_SC2_ADACT_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	278	/* SC3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	279	#define ADC_SC3_AVGS_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	280	#define ADC_SC3_AVGS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	281	#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
pradeepvk2208	1:c0c5ac8eac80	282	#define ADC_SC3_AVGE_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	283	#define ADC_SC3_AVGE_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	284	#define ADC_SC3_ADCO_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	285	#define ADC_SC3_ADCO_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	286	#define ADC_SC3_CALF_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	287	#define ADC_SC3_CALF_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	288	#define ADC_SC3_CAL_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	289	#define ADC_SC3_CAL_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	290	/* OFS Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	291	#define ADC_OFS_OFS_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	292	#define ADC_OFS_OFS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	293	#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
pradeepvk2208	1:c0c5ac8eac80	294	/* PG Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	295	#define ADC_PG_PG_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	296	#define ADC_PG_PG_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	297	#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
pradeepvk2208	1:c0c5ac8eac80	298	/* MG Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	299	#define ADC_MG_MG_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	300	#define ADC_MG_MG_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	301	#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
pradeepvk2208	1:c0c5ac8eac80	302	/* CLPD Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	303	#define ADC_CLPD_CLPD_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	304	#define ADC_CLPD_CLPD_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	305	#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
pradeepvk2208	1:c0c5ac8eac80	306	/* CLPS Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	307	#define ADC_CLPS_CLPS_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	308	#define ADC_CLPS_CLPS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	309	#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
pradeepvk2208	1:c0c5ac8eac80	310	/* CLP4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	311	#define ADC_CLP4_CLP4_MASK 0x3FFu
pradeepvk2208	1:c0c5ac8eac80	312	#define ADC_CLP4_CLP4_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	313	#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
pradeepvk2208	1:c0c5ac8eac80	314	/* CLP3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	315	#define ADC_CLP3_CLP3_MASK 0x1FFu
pradeepvk2208	1:c0c5ac8eac80	316	#define ADC_CLP3_CLP3_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	317	#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
pradeepvk2208	1:c0c5ac8eac80	318	/* CLP2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	319	#define ADC_CLP2_CLP2_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	320	#define ADC_CLP2_CLP2_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	321	#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
pradeepvk2208	1:c0c5ac8eac80	322	/* CLP1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	323	#define ADC_CLP1_CLP1_MASK 0x7Fu
pradeepvk2208	1:c0c5ac8eac80	324	#define ADC_CLP1_CLP1_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	325	#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
pradeepvk2208	1:c0c5ac8eac80	326	/* CLP0 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	327	#define ADC_CLP0_CLP0_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	328	#define ADC_CLP0_CLP0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	329	#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
pradeepvk2208	1:c0c5ac8eac80	330	/* CLMD Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	331	#define ADC_CLMD_CLMD_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	332	#define ADC_CLMD_CLMD_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	333	#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
pradeepvk2208	1:c0c5ac8eac80	334	/* CLMS Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	335	#define ADC_CLMS_CLMS_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	336	#define ADC_CLMS_CLMS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	337	#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
pradeepvk2208	1:c0c5ac8eac80	338	/* CLM4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	339	#define ADC_CLM4_CLM4_MASK 0x3FFu
pradeepvk2208	1:c0c5ac8eac80	340	#define ADC_CLM4_CLM4_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	341	#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
pradeepvk2208	1:c0c5ac8eac80	342	/* CLM3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	343	#define ADC_CLM3_CLM3_MASK 0x1FFu
pradeepvk2208	1:c0c5ac8eac80	344	#define ADC_CLM3_CLM3_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	345	#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
pradeepvk2208	1:c0c5ac8eac80	346	/* CLM2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	347	#define ADC_CLM2_CLM2_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	348	#define ADC_CLM2_CLM2_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	349	#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
pradeepvk2208	1:c0c5ac8eac80	350	/* CLM1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	351	#define ADC_CLM1_CLM1_MASK 0x7Fu
pradeepvk2208	1:c0c5ac8eac80	352	#define ADC_CLM1_CLM1_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	353	#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
pradeepvk2208	1:c0c5ac8eac80	354	/* CLM0 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	355	#define ADC_CLM0_CLM0_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	356	#define ADC_CLM0_CLM0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	357	#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
pradeepvk2208	1:c0c5ac8eac80	358
pradeepvk2208	1:c0c5ac8eac80	359	/*!
pradeepvk2208	1:c0c5ac8eac80	360	* @}
pradeepvk2208	1:c0c5ac8eac80	361	/ / end of group ADC_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	362
pradeepvk2208	1:c0c5ac8eac80	363
pradeepvk2208	1:c0c5ac8eac80	364	/* ADC - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	365	/** Peripheral ADC0 base address */
pradeepvk2208	1:c0c5ac8eac80	366	#define ADC0_BASE (0x4003B000u)
pradeepvk2208	1:c0c5ac8eac80	367	/** Peripheral ADC0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	368	#define ADC0 ((ADC_Type *)ADC0_BASE)
pradeepvk2208	1:c0c5ac8eac80	369	/** Array initializer of ADC peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	370	#define ADC_BASES { ADC0 }
pradeepvk2208	1:c0c5ac8eac80	371
pradeepvk2208	1:c0c5ac8eac80	372	/*!
pradeepvk2208	1:c0c5ac8eac80	373	* @}
pradeepvk2208	1:c0c5ac8eac80	374	/ / end of group ADC_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	375
pradeepvk2208	1:c0c5ac8eac80	376
pradeepvk2208	1:c0c5ac8eac80	377	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	378	-- CMP Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	379	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	380
pradeepvk2208	1:c0c5ac8eac80	381	/*!
pradeepvk2208	1:c0c5ac8eac80	382	* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	383	* @{
pradeepvk2208	1:c0c5ac8eac80	384	*/
pradeepvk2208	1:c0c5ac8eac80	385
pradeepvk2208	1:c0c5ac8eac80	386	/** CMP - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	387	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	388	__IO uint8_t CR0; /*< CMP Control Register 0, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	389	__IO uint8_t CR1; /*< CMP Control Register 1, offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	390	__IO uint8_t FPR; /*< CMP Filter Period Register, offset: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	391	__IO uint8_t SCR; /*< CMP Status and Control Register, offset: 0x3 /
pradeepvk2208	1:c0c5ac8eac80	392	__IO uint8_t DACCR; /*< DAC Control Register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	393	__IO uint8_t MUXCR; /*< MUX Control Register, offset: 0x5 /
pradeepvk2208	1:c0c5ac8eac80	394	} CMP_Type;
pradeepvk2208	1:c0c5ac8eac80	395
pradeepvk2208	1:c0c5ac8eac80	396	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	397	-- CMP Register Masks
pradeepvk2208	1:c0c5ac8eac80	398	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	399
pradeepvk2208	1:c0c5ac8eac80	400	/*!
pradeepvk2208	1:c0c5ac8eac80	401	* @addtogroup CMP_Register_Masks CMP Register Masks
pradeepvk2208	1:c0c5ac8eac80	402	* @{
pradeepvk2208	1:c0c5ac8eac80	403	*/
pradeepvk2208	1:c0c5ac8eac80	404
pradeepvk2208	1:c0c5ac8eac80	405	/* CR0 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	406	#define CMP_CR0_HYSTCTR_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	407	#define CMP_CR0_HYSTCTR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	408	#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
pradeepvk2208	1:c0c5ac8eac80	409	#define CMP_CR0_FILTER_CNT_MASK 0x70u
pradeepvk2208	1:c0c5ac8eac80	410	#define CMP_CR0_FILTER_CNT_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	411	#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
pradeepvk2208	1:c0c5ac8eac80	412	/* CR1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	413	#define CMP_CR1_EN_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	414	#define CMP_CR1_EN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	415	#define CMP_CR1_OPE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	416	#define CMP_CR1_OPE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	417	#define CMP_CR1_COS_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	418	#define CMP_CR1_COS_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	419	#define CMP_CR1_INV_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	420	#define CMP_CR1_INV_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	421	#define CMP_CR1_PMODE_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	422	#define CMP_CR1_PMODE_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	423	#define CMP_CR1_TRIGM_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	424	#define CMP_CR1_TRIGM_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	425	#define CMP_CR1_WE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	426	#define CMP_CR1_WE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	427	#define CMP_CR1_SE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	428	#define CMP_CR1_SE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	429	/* FPR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	430	#define CMP_FPR_FILT_PER_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	431	#define CMP_FPR_FILT_PER_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	432	#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
pradeepvk2208	1:c0c5ac8eac80	433	/* SCR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	434	#define CMP_SCR_COUT_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	435	#define CMP_SCR_COUT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	436	#define CMP_SCR_CFF_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	437	#define CMP_SCR_CFF_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	438	#define CMP_SCR_CFR_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	439	#define CMP_SCR_CFR_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	440	#define CMP_SCR_IEF_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	441	#define CMP_SCR_IEF_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	442	#define CMP_SCR_IER_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	443	#define CMP_SCR_IER_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	444	#define CMP_SCR_DMAEN_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	445	#define CMP_SCR_DMAEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	446	/* DACCR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	447	#define CMP_DACCR_VOSEL_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	448	#define CMP_DACCR_VOSEL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	449	#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
pradeepvk2208	1:c0c5ac8eac80	450	#define CMP_DACCR_VRSEL_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	451	#define CMP_DACCR_VRSEL_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	452	#define CMP_DACCR_DACEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	453	#define CMP_DACCR_DACEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	454	/* MUXCR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	455	#define CMP_MUXCR_MSEL_MASK 0x7u
pradeepvk2208	1:c0c5ac8eac80	456	#define CMP_MUXCR_MSEL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	457	#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
pradeepvk2208	1:c0c5ac8eac80	458	#define CMP_MUXCR_PSEL_MASK 0x38u
pradeepvk2208	1:c0c5ac8eac80	459	#define CMP_MUXCR_PSEL_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	460	#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
pradeepvk2208	1:c0c5ac8eac80	461	#define CMP_MUXCR_PSTM_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	462	#define CMP_MUXCR_PSTM_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	463
pradeepvk2208	1:c0c5ac8eac80	464	/*!
pradeepvk2208	1:c0c5ac8eac80	465	* @}
pradeepvk2208	1:c0c5ac8eac80	466	/ / end of group CMP_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	467
pradeepvk2208	1:c0c5ac8eac80	468
pradeepvk2208	1:c0c5ac8eac80	469	/* CMP - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	470	/** Peripheral CMP0 base address */
pradeepvk2208	1:c0c5ac8eac80	471	#define CMP0_BASE (0x40073000u)
pradeepvk2208	1:c0c5ac8eac80	472	/** Peripheral CMP0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	473	#define CMP0 ((CMP_Type *)CMP0_BASE)
pradeepvk2208	1:c0c5ac8eac80	474	/** Array initializer of CMP peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	475	#define CMP_BASES { CMP0 }
pradeepvk2208	1:c0c5ac8eac80	476
pradeepvk2208	1:c0c5ac8eac80	477	/*!
pradeepvk2208	1:c0c5ac8eac80	478	* @}
pradeepvk2208	1:c0c5ac8eac80	479	/ / end of group CMP_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	480
pradeepvk2208	1:c0c5ac8eac80	481
pradeepvk2208	1:c0c5ac8eac80	482	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	483	-- DAC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	484	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	485
pradeepvk2208	1:c0c5ac8eac80	486	/*!
pradeepvk2208	1:c0c5ac8eac80	487	* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	488	* @{
pradeepvk2208	1:c0c5ac8eac80	489	*/
pradeepvk2208	1:c0c5ac8eac80	490
pradeepvk2208	1:c0c5ac8eac80	491	/** DAC - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	492	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	493	struct { /* offset: 0x0, array step: 0x2 */
pradeepvk2208	1:c0c5ac8eac80	494	__IO uint8_t DATL; /*< DAC Data Low Register, array offset: 0x0, array step: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	495	__IO uint8_t DATH; /*< DAC Data High Register, array offset: 0x1, array step: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	496	} DAT[2];
pradeepvk2208	1:c0c5ac8eac80	497	uint8_t RESERVED_0[28];
pradeepvk2208	1:c0c5ac8eac80	498	__IO uint8_t SR; /*< DAC Status Register, offset: 0x20 /
pradeepvk2208	1:c0c5ac8eac80	499	__IO uint8_t C0; /*< DAC Control Register, offset: 0x21 /
pradeepvk2208	1:c0c5ac8eac80	500	__IO uint8_t C1; /*< DAC Control Register 1, offset: 0x22 /
pradeepvk2208	1:c0c5ac8eac80	501	__IO uint8_t C2; /*< DAC Control Register 2, offset: 0x23 /
pradeepvk2208	1:c0c5ac8eac80	502	} DAC_Type;
pradeepvk2208	1:c0c5ac8eac80	503
pradeepvk2208	1:c0c5ac8eac80	504	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	505	-- DAC Register Masks
pradeepvk2208	1:c0c5ac8eac80	506	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	507
pradeepvk2208	1:c0c5ac8eac80	508	/*!
pradeepvk2208	1:c0c5ac8eac80	509	* @addtogroup DAC_Register_Masks DAC Register Masks
pradeepvk2208	1:c0c5ac8eac80	510	* @{
pradeepvk2208	1:c0c5ac8eac80	511	*/
pradeepvk2208	1:c0c5ac8eac80	512
pradeepvk2208	1:c0c5ac8eac80	513	/* DATL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	514	#define DAC_DATL_DATA0_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	515	#define DAC_DATL_DATA0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	516	#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
pradeepvk2208	1:c0c5ac8eac80	517	/* DATH Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	518	#define DAC_DATH_DATA1_MASK 0xFu
pradeepvk2208	1:c0c5ac8eac80	519	#define DAC_DATH_DATA1_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	520	#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
pradeepvk2208	1:c0c5ac8eac80	521	/* SR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	522	#define DAC_SR_DACBFRPBF_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	523	#define DAC_SR_DACBFRPBF_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	524	#define DAC_SR_DACBFRPTF_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	525	#define DAC_SR_DACBFRPTF_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	526	/* C0 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	527	#define DAC_C0_DACBBIEN_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	528	#define DAC_C0_DACBBIEN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	529	#define DAC_C0_DACBTIEN_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	530	#define DAC_C0_DACBTIEN_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	531	#define DAC_C0_LPEN_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	532	#define DAC_C0_LPEN_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	533	#define DAC_C0_DACSWTRG_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	534	#define DAC_C0_DACSWTRG_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	535	#define DAC_C0_DACTRGSEL_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	536	#define DAC_C0_DACTRGSEL_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	537	#define DAC_C0_DACRFS_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	538	#define DAC_C0_DACRFS_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	539	#define DAC_C0_DACEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	540	#define DAC_C0_DACEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	541	/* C1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	542	#define DAC_C1_DACBFEN_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	543	#define DAC_C1_DACBFEN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	544	#define DAC_C1_DACBFMD_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	545	#define DAC_C1_DACBFMD_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	546	#define DAC_C1_DMAEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	547	#define DAC_C1_DMAEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	548	/* C2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	549	#define DAC_C2_DACBFUP_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	550	#define DAC_C2_DACBFUP_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	551	#define DAC_C2_DACBFRP_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	552	#define DAC_C2_DACBFRP_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	553
pradeepvk2208	1:c0c5ac8eac80	554	/*!
pradeepvk2208	1:c0c5ac8eac80	555	* @}
pradeepvk2208	1:c0c5ac8eac80	556	/ / end of group DAC_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	557
pradeepvk2208	1:c0c5ac8eac80	558
pradeepvk2208	1:c0c5ac8eac80	559	/* DAC - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	560	/** Peripheral DAC0 base address */
pradeepvk2208	1:c0c5ac8eac80	561	#define DAC0_BASE (0x4003F000u)
pradeepvk2208	1:c0c5ac8eac80	562	/** Peripheral DAC0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	563	#define DAC0 ((DAC_Type *)DAC0_BASE)
pradeepvk2208	1:c0c5ac8eac80	564	/** Array initializer of DAC peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	565	#define DAC_BASES { DAC0 }
pradeepvk2208	1:c0c5ac8eac80	566
pradeepvk2208	1:c0c5ac8eac80	567	/*!
pradeepvk2208	1:c0c5ac8eac80	568	* @}
pradeepvk2208	1:c0c5ac8eac80	569	/ / end of group DAC_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	570
pradeepvk2208	1:c0c5ac8eac80	571
pradeepvk2208	1:c0c5ac8eac80	572	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	573	-- DMA Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	574	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	575
pradeepvk2208	1:c0c5ac8eac80	576	/*!
pradeepvk2208	1:c0c5ac8eac80	577	* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	578	* @{
pradeepvk2208	1:c0c5ac8eac80	579	*/
pradeepvk2208	1:c0c5ac8eac80	580
pradeepvk2208	1:c0c5ac8eac80	581	/** DMA - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	582	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	583	uint8_t RESERVED_0[256];
pradeepvk2208	1:c0c5ac8eac80	584	struct { /* offset: 0x100, array step: 0x10 */
pradeepvk2208	1:c0c5ac8eac80	585	__IO uint32_t SAR; /*< Source Address Register, array offset: 0x100, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	586	__IO uint32_t DAR; /*< Destination Address Register, array offset: 0x104, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	587	union { /* offset: 0x108, array step: 0x10 */
pradeepvk2208	1:c0c5ac8eac80	588	__IO uint32_t DSR_BCR; /*< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	589	struct { /* offset: 0x108, array step: 0x10 */
pradeepvk2208	1:c0c5ac8eac80	590	uint8_t RESERVED_0[3];
pradeepvk2208	1:c0c5ac8eac80	591	__IO uint8_t DSR; /*< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	592	} DMA_DSR_ACCESS8BIT;
pradeepvk2208	1:c0c5ac8eac80	593	};
pradeepvk2208	1:c0c5ac8eac80	594	__IO uint32_t DCR; /*< DMA Control Register, array offset: 0x10C, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	595	} DMA[4];
pradeepvk2208	1:c0c5ac8eac80	596	} DMA_Type;
pradeepvk2208	1:c0c5ac8eac80	597
pradeepvk2208	1:c0c5ac8eac80	598	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	599	-- DMA Register Masks
pradeepvk2208	1:c0c5ac8eac80	600	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	601
pradeepvk2208	1:c0c5ac8eac80	602	/*!
pradeepvk2208	1:c0c5ac8eac80	603	* @addtogroup DMA_Register_Masks DMA Register Masks
pradeepvk2208	1:c0c5ac8eac80	604	* @{
pradeepvk2208	1:c0c5ac8eac80	605	*/
pradeepvk2208	1:c0c5ac8eac80	606
pradeepvk2208	1:c0c5ac8eac80	607	/* SAR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	608	#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	609	#define DMA_SAR_SAR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	610	#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
pradeepvk2208	1:c0c5ac8eac80	611	/* DAR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	612	#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	613	#define DMA_DAR_DAR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	614	#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
pradeepvk2208	1:c0c5ac8eac80	615	/* DSR_BCR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	616	#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	617	#define DMA_DSR_BCR_BCR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	618	#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
pradeepvk2208	1:c0c5ac8eac80	619	#define DMA_DSR_BCR_DONE_MASK 0x1000000u
pradeepvk2208	1:c0c5ac8eac80	620	#define DMA_DSR_BCR_DONE_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	621	#define DMA_DSR_BCR_BSY_MASK 0x2000000u
pradeepvk2208	1:c0c5ac8eac80	622	#define DMA_DSR_BCR_BSY_SHIFT 25
pradeepvk2208	1:c0c5ac8eac80	623	#define DMA_DSR_BCR_REQ_MASK 0x4000000u
pradeepvk2208	1:c0c5ac8eac80	624	#define DMA_DSR_BCR_REQ_SHIFT 26
pradeepvk2208	1:c0c5ac8eac80	625	#define DMA_DSR_BCR_BED_MASK 0x10000000u
pradeepvk2208	1:c0c5ac8eac80	626	#define DMA_DSR_BCR_BED_SHIFT 28
pradeepvk2208	1:c0c5ac8eac80	627	#define DMA_DSR_BCR_BES_MASK 0x20000000u
pradeepvk2208	1:c0c5ac8eac80	628	#define DMA_DSR_BCR_BES_SHIFT 29
pradeepvk2208	1:c0c5ac8eac80	629	#define DMA_DSR_BCR_CE_MASK 0x40000000u
pradeepvk2208	1:c0c5ac8eac80	630	#define DMA_DSR_BCR_CE_SHIFT 30
pradeepvk2208	1:c0c5ac8eac80	631	/* DCR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	632	#define DMA_DCR_LCH2_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	633	#define DMA_DCR_LCH2_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	634	#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
pradeepvk2208	1:c0c5ac8eac80	635	#define DMA_DCR_LCH1_MASK 0xCu
pradeepvk2208	1:c0c5ac8eac80	636	#define DMA_DCR_LCH1_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	637	#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
pradeepvk2208	1:c0c5ac8eac80	638	#define DMA_DCR_LINKCC_MASK 0x30u
pradeepvk2208	1:c0c5ac8eac80	639	#define DMA_DCR_LINKCC_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	640	#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
pradeepvk2208	1:c0c5ac8eac80	641	#define DMA_DCR_D_REQ_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	642	#define DMA_DCR_D_REQ_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	643	#define DMA_DCR_DMOD_MASK 0xF00u
pradeepvk2208	1:c0c5ac8eac80	644	#define DMA_DCR_DMOD_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	645	#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
pradeepvk2208	1:c0c5ac8eac80	646	#define DMA_DCR_SMOD_MASK 0xF000u
pradeepvk2208	1:c0c5ac8eac80	647	#define DMA_DCR_SMOD_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	648	#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
pradeepvk2208	1:c0c5ac8eac80	649	#define DMA_DCR_START_MASK 0x10000u
pradeepvk2208	1:c0c5ac8eac80	650	#define DMA_DCR_START_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	651	#define DMA_DCR_DSIZE_MASK 0x60000u
pradeepvk2208	1:c0c5ac8eac80	652	#define DMA_DCR_DSIZE_SHIFT 17
pradeepvk2208	1:c0c5ac8eac80	653	#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
pradeepvk2208	1:c0c5ac8eac80	654	#define DMA_DCR_DINC_MASK 0x80000u
pradeepvk2208	1:c0c5ac8eac80	655	#define DMA_DCR_DINC_SHIFT 19
pradeepvk2208	1:c0c5ac8eac80	656	#define DMA_DCR_SSIZE_MASK 0x300000u
pradeepvk2208	1:c0c5ac8eac80	657	#define DMA_DCR_SSIZE_SHIFT 20
pradeepvk2208	1:c0c5ac8eac80	658	#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
pradeepvk2208	1:c0c5ac8eac80	659	#define DMA_DCR_SINC_MASK 0x400000u
pradeepvk2208	1:c0c5ac8eac80	660	#define DMA_DCR_SINC_SHIFT 22
pradeepvk2208	1:c0c5ac8eac80	661	#define DMA_DCR_EADREQ_MASK 0x800000u
pradeepvk2208	1:c0c5ac8eac80	662	#define DMA_DCR_EADREQ_SHIFT 23
pradeepvk2208	1:c0c5ac8eac80	663	#define DMA_DCR_AA_MASK 0x10000000u
pradeepvk2208	1:c0c5ac8eac80	664	#define DMA_DCR_AA_SHIFT 28
pradeepvk2208	1:c0c5ac8eac80	665	#define DMA_DCR_CS_MASK 0x20000000u
pradeepvk2208	1:c0c5ac8eac80	666	#define DMA_DCR_CS_SHIFT 29
pradeepvk2208	1:c0c5ac8eac80	667	#define DMA_DCR_ERQ_MASK 0x40000000u
pradeepvk2208	1:c0c5ac8eac80	668	#define DMA_DCR_ERQ_SHIFT 30
pradeepvk2208	1:c0c5ac8eac80	669	#define DMA_DCR_EINT_MASK 0x80000000u
pradeepvk2208	1:c0c5ac8eac80	670	#define DMA_DCR_EINT_SHIFT 31
pradeepvk2208	1:c0c5ac8eac80	671
pradeepvk2208	1:c0c5ac8eac80	672	/*!
pradeepvk2208	1:c0c5ac8eac80	673	* @}
pradeepvk2208	1:c0c5ac8eac80	674	/ / end of group DMA_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	675
pradeepvk2208	1:c0c5ac8eac80	676
pradeepvk2208	1:c0c5ac8eac80	677	/* DMA - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	678	/** Peripheral DMA base address */
pradeepvk2208	1:c0c5ac8eac80	679	#define DMA_BASE (0x40008000u)
pradeepvk2208	1:c0c5ac8eac80	680	/** Peripheral DMA base pointer */
pradeepvk2208	1:c0c5ac8eac80	681	#define DMA0 ((DMA_Type *)DMA_BASE)
pradeepvk2208	1:c0c5ac8eac80	682	/** Array initializer of DMA peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	683	#define DMA_BASES { DMA0 }
pradeepvk2208	1:c0c5ac8eac80	684
pradeepvk2208	1:c0c5ac8eac80	685	/*!
pradeepvk2208	1:c0c5ac8eac80	686	* @}
pradeepvk2208	1:c0c5ac8eac80	687	/ / end of group DMA_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	688
pradeepvk2208	1:c0c5ac8eac80	689
pradeepvk2208	1:c0c5ac8eac80	690	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	691	-- DMAMUX Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	692	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	693
pradeepvk2208	1:c0c5ac8eac80	694	/*!
pradeepvk2208	1:c0c5ac8eac80	695	* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	696	* @{
pradeepvk2208	1:c0c5ac8eac80	697	*/
pradeepvk2208	1:c0c5ac8eac80	698
pradeepvk2208	1:c0c5ac8eac80	699	/** DMAMUX - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	700	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	701	__IO uint8_t CHCFG[4]; /*< Channel Configuration register, array offset: 0x0, array step: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	702	} DMAMUX_Type;
pradeepvk2208	1:c0c5ac8eac80	703
pradeepvk2208	1:c0c5ac8eac80	704	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	705	-- DMAMUX Register Masks
pradeepvk2208	1:c0c5ac8eac80	706	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	707
pradeepvk2208	1:c0c5ac8eac80	708	/*!
pradeepvk2208	1:c0c5ac8eac80	709	* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
pradeepvk2208	1:c0c5ac8eac80	710	* @{
pradeepvk2208	1:c0c5ac8eac80	711	*/
pradeepvk2208	1:c0c5ac8eac80	712
pradeepvk2208	1:c0c5ac8eac80	713	/* CHCFG Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	714	#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	715	#define DMAMUX_CHCFG_SOURCE_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	716	#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
pradeepvk2208	1:c0c5ac8eac80	717	#define DMAMUX_CHCFG_TRIG_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	718	#define DMAMUX_CHCFG_TRIG_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	719	#define DMAMUX_CHCFG_ENBL_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	720	#define DMAMUX_CHCFG_ENBL_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	721
pradeepvk2208	1:c0c5ac8eac80	722	/*!
pradeepvk2208	1:c0c5ac8eac80	723	* @}
pradeepvk2208	1:c0c5ac8eac80	724	/ / end of group DMAMUX_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	725
pradeepvk2208	1:c0c5ac8eac80	726
pradeepvk2208	1:c0c5ac8eac80	727	/* DMAMUX - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	728	/** Peripheral DMAMUX0 base address */
pradeepvk2208	1:c0c5ac8eac80	729	#define DMAMUX0_BASE (0x40021000u)
pradeepvk2208	1:c0c5ac8eac80	730	/** Peripheral DMAMUX0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	731	#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
pradeepvk2208	1:c0c5ac8eac80	732	/** Array initializer of DMAMUX peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	733	#define DMAMUX_BASES { DMAMUX0 }
pradeepvk2208	1:c0c5ac8eac80	734
pradeepvk2208	1:c0c5ac8eac80	735	/*!
pradeepvk2208	1:c0c5ac8eac80	736	* @}
pradeepvk2208	1:c0c5ac8eac80	737	/ / end of group DMAMUX_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	738
pradeepvk2208	1:c0c5ac8eac80	739
pradeepvk2208	1:c0c5ac8eac80	740	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	741	-- FGPIO Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	742	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	743
pradeepvk2208	1:c0c5ac8eac80	744	/*!
pradeepvk2208	1:c0c5ac8eac80	745	* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	746	* @{
pradeepvk2208	1:c0c5ac8eac80	747	*/
pradeepvk2208	1:c0c5ac8eac80	748
pradeepvk2208	1:c0c5ac8eac80	749	/** FGPIO - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	750	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	751	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	752	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	753	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	754	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	755	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	756	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
pradeepvk2208	1:c0c5ac8eac80	757	} FGPIO_Type;
pradeepvk2208	1:c0c5ac8eac80	758
pradeepvk2208	1:c0c5ac8eac80	759	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	760	-- FGPIO Register Masks
pradeepvk2208	1:c0c5ac8eac80	761	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	762
pradeepvk2208	1:c0c5ac8eac80	763	/*!
pradeepvk2208	1:c0c5ac8eac80	764	* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
pradeepvk2208	1:c0c5ac8eac80	765	* @{
pradeepvk2208	1:c0c5ac8eac80	766	*/
pradeepvk2208	1:c0c5ac8eac80	767
pradeepvk2208	1:c0c5ac8eac80	768	/* PDOR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	769	#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	770	#define FGPIO_PDOR_PDO_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	771	#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
pradeepvk2208	1:c0c5ac8eac80	772	/* PSOR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	773	#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	774	#define FGPIO_PSOR_PTSO_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	775	#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
pradeepvk2208	1:c0c5ac8eac80	776	/* PCOR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	777	#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	778	#define FGPIO_PCOR_PTCO_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	779	#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
pradeepvk2208	1:c0c5ac8eac80	780	/* PTOR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	781	#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	782	#define FGPIO_PTOR_PTTO_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	783	#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
pradeepvk2208	1:c0c5ac8eac80	784	/* PDIR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	785	#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	786	#define FGPIO_PDIR_PDI_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	787	#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
pradeepvk2208	1:c0c5ac8eac80	788	/* PDDR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	789	#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	790	#define FGPIO_PDDR_PDD_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	791	#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
pradeepvk2208	1:c0c5ac8eac80	792
pradeepvk2208	1:c0c5ac8eac80	793	/*!
pradeepvk2208	1:c0c5ac8eac80	794	* @}
pradeepvk2208	1:c0c5ac8eac80	795	/ / end of group FGPIO_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	796
pradeepvk2208	1:c0c5ac8eac80	797
pradeepvk2208	1:c0c5ac8eac80	798	/* FGPIO - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	799	/** Peripheral FPTA base address */
pradeepvk2208	1:c0c5ac8eac80	800	#define FPTA_BASE (0xF80FF000u)
pradeepvk2208	1:c0c5ac8eac80	801	/** Peripheral FPTA base pointer */
pradeepvk2208	1:c0c5ac8eac80	802	#define FPTA ((FGPIO_Type *)FPTA_BASE)
pradeepvk2208	1:c0c5ac8eac80	803	/** Peripheral FPTB base address */
pradeepvk2208	1:c0c5ac8eac80	804	#define FPTB_BASE (0xF80FF040u)
pradeepvk2208	1:c0c5ac8eac80	805	/** Peripheral FPTB base pointer */
pradeepvk2208	1:c0c5ac8eac80	806	#define FPTB ((FGPIO_Type *)FPTB_BASE)
pradeepvk2208	1:c0c5ac8eac80	807	/** Peripheral FPTC base address */
pradeepvk2208	1:c0c5ac8eac80	808	#define FPTC_BASE (0xF80FF080u)
pradeepvk2208	1:c0c5ac8eac80	809	/** Peripheral FPTC base pointer */
pradeepvk2208	1:c0c5ac8eac80	810	#define FPTC ((FGPIO_Type *)FPTC_BASE)
pradeepvk2208	1:c0c5ac8eac80	811	/** Peripheral FPTD base address */
pradeepvk2208	1:c0c5ac8eac80	812	#define FPTD_BASE (0xF80FF0C0u)
pradeepvk2208	1:c0c5ac8eac80	813	/** Peripheral FPTD base pointer */
pradeepvk2208	1:c0c5ac8eac80	814	#define FPTD ((FGPIO_Type *)FPTD_BASE)
pradeepvk2208	1:c0c5ac8eac80	815	/** Peripheral FPTE base address */
pradeepvk2208	1:c0c5ac8eac80	816	#define FPTE_BASE (0xF80FF100u)
pradeepvk2208	1:c0c5ac8eac80	817	/** Peripheral FPTE base pointer */
pradeepvk2208	1:c0c5ac8eac80	818	#define FPTE ((FGPIO_Type *)FPTE_BASE)
pradeepvk2208	1:c0c5ac8eac80	819	/** Array initializer of FGPIO peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	820	#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
pradeepvk2208	1:c0c5ac8eac80	821
pradeepvk2208	1:c0c5ac8eac80	822	/*!
pradeepvk2208	1:c0c5ac8eac80	823	* @}
pradeepvk2208	1:c0c5ac8eac80	824	/ / end of group FGPIO_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	825
pradeepvk2208	1:c0c5ac8eac80	826
pradeepvk2208	1:c0c5ac8eac80	827	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	828	-- FTFA Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	829	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	830
pradeepvk2208	1:c0c5ac8eac80	831	/*!
pradeepvk2208	1:c0c5ac8eac80	832	* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	833	* @{
pradeepvk2208	1:c0c5ac8eac80	834	*/
pradeepvk2208	1:c0c5ac8eac80	835
pradeepvk2208	1:c0c5ac8eac80	836	/** FTFA - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	837	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	838	__IO uint8_t FSTAT; /*< Flash Status Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	839	__IO uint8_t FCNFG; /*< Flash Configuration Register, offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	840	__I uint8_t FSEC; /*< Flash Security Register, offset: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	841	__I uint8_t FOPT; /*< Flash Option Register, offset: 0x3 /
pradeepvk2208	1:c0c5ac8eac80	842	__IO uint8_t FCCOB3; /*< Flash Common Command Object Registers, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	843	__IO uint8_t FCCOB2; /*< Flash Common Command Object Registers, offset: 0x5 /
pradeepvk2208	1:c0c5ac8eac80	844	__IO uint8_t FCCOB1; /*< Flash Common Command Object Registers, offset: 0x6 /
pradeepvk2208	1:c0c5ac8eac80	845	__IO uint8_t FCCOB0; /*< Flash Common Command Object Registers, offset: 0x7 /
pradeepvk2208	1:c0c5ac8eac80	846	__IO uint8_t FCCOB7; /*< Flash Common Command Object Registers, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	847	__IO uint8_t FCCOB6; /*< Flash Common Command Object Registers, offset: 0x9 /
pradeepvk2208	1:c0c5ac8eac80	848	__IO uint8_t FCCOB5; /*< Flash Common Command Object Registers, offset: 0xA /
pradeepvk2208	1:c0c5ac8eac80	849	__IO uint8_t FCCOB4; /*< Flash Common Command Object Registers, offset: 0xB /
pradeepvk2208	1:c0c5ac8eac80	850	__IO uint8_t FCCOBB; /*< Flash Common Command Object Registers, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	851	__IO uint8_t FCCOBA; /*< Flash Common Command Object Registers, offset: 0xD /
pradeepvk2208	1:c0c5ac8eac80	852	__IO uint8_t FCCOB9; /*< Flash Common Command Object Registers, offset: 0xE /
pradeepvk2208	1:c0c5ac8eac80	853	__IO uint8_t FCCOB8; /*< Flash Common Command Object Registers, offset: 0xF /
pradeepvk2208	1:c0c5ac8eac80	854	__IO uint8_t FPROT3; /*< Program Flash Protection Registers, offset: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	855	__IO uint8_t FPROT2; /*< Program Flash Protection Registers, offset: 0x11 /
pradeepvk2208	1:c0c5ac8eac80	856	__IO uint8_t FPROT1; /*< Program Flash Protection Registers, offset: 0x12 /
pradeepvk2208	1:c0c5ac8eac80	857	__IO uint8_t FPROT0; /*< Program Flash Protection Registers, offset: 0x13 /
pradeepvk2208	1:c0c5ac8eac80	858	} FTFA_Type;
pradeepvk2208	1:c0c5ac8eac80	859
pradeepvk2208	1:c0c5ac8eac80	860	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	861	-- FTFA Register Masks
pradeepvk2208	1:c0c5ac8eac80	862	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	863
pradeepvk2208	1:c0c5ac8eac80	864	/*!
pradeepvk2208	1:c0c5ac8eac80	865	* @addtogroup FTFA_Register_Masks FTFA Register Masks
pradeepvk2208	1:c0c5ac8eac80	866	* @{
pradeepvk2208	1:c0c5ac8eac80	867	*/
pradeepvk2208	1:c0c5ac8eac80	868
pradeepvk2208	1:c0c5ac8eac80	869	/* FSTAT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	870	#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	871	#define FTFA_FSTAT_MGSTAT0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	872	#define FTFA_FSTAT_FPVIOL_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	873	#define FTFA_FSTAT_FPVIOL_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	874	#define FTFA_FSTAT_ACCERR_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	875	#define FTFA_FSTAT_ACCERR_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	876	#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	877	#define FTFA_FSTAT_RDCOLERR_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	878	#define FTFA_FSTAT_CCIF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	879	#define FTFA_FSTAT_CCIF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	880	/* FCNFG Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	881	#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	882	#define FTFA_FCNFG_ERSSUSP_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	883	#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	884	#define FTFA_FCNFG_ERSAREQ_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	885	#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	886	#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	887	#define FTFA_FCNFG_CCIE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	888	#define FTFA_FCNFG_CCIE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	889	/* FSEC Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	890	#define FTFA_FSEC_SEC_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	891	#define FTFA_FSEC_SEC_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	892	#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
pradeepvk2208	1:c0c5ac8eac80	893	#define FTFA_FSEC_FSLACC_MASK 0xCu
pradeepvk2208	1:c0c5ac8eac80	894	#define FTFA_FSEC_FSLACC_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	895	#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
pradeepvk2208	1:c0c5ac8eac80	896	#define FTFA_FSEC_MEEN_MASK 0x30u
pradeepvk2208	1:c0c5ac8eac80	897	#define FTFA_FSEC_MEEN_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	898	#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
pradeepvk2208	1:c0c5ac8eac80	899	#define FTFA_FSEC_KEYEN_MASK 0xC0u
pradeepvk2208	1:c0c5ac8eac80	900	#define FTFA_FSEC_KEYEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	901	#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
pradeepvk2208	1:c0c5ac8eac80	902	/* FOPT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	903	#define FTFA_FOPT_OPT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	904	#define FTFA_FOPT_OPT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	905	#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
pradeepvk2208	1:c0c5ac8eac80	906	/* FCCOB3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	907	#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	908	#define FTFA_FCCOB3_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	909	#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	910	/* FCCOB2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	911	#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	912	#define FTFA_FCCOB2_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	913	#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	914	/* FCCOB1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	915	#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	916	#define FTFA_FCCOB1_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	917	#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	918	/* FCCOB0 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	919	#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	920	#define FTFA_FCCOB0_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	921	#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	922	/* FCCOB7 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	923	#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	924	#define FTFA_FCCOB7_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	925	#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	926	/* FCCOB6 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	927	#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	928	#define FTFA_FCCOB6_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	929	#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	930	/* FCCOB5 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	931	#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	932	#define FTFA_FCCOB5_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	933	#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	934	/* FCCOB4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	935	#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	936	#define FTFA_FCCOB4_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	937	#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	938	/* FCCOBB Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	939	#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	940	#define FTFA_FCCOBB_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	941	#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	942	/* FCCOBA Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	943	#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	944	#define FTFA_FCCOBA_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	945	#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	946	/* FCCOB9 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	947	#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	948	#define FTFA_FCCOB9_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	949	#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	950	/* FCCOB8 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	951	#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	952	#define FTFA_FCCOB8_CCOBn_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	953	#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
pradeepvk2208	1:c0c5ac8eac80	954	/* FPROT3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	955	#define FTFA_FPROT3_PROT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	956	#define FTFA_FPROT3_PROT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	957	#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
pradeepvk2208	1:c0c5ac8eac80	958	/* FPROT2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	959	#define FTFA_FPROT2_PROT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	960	#define FTFA_FPROT2_PROT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	961	#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
pradeepvk2208	1:c0c5ac8eac80	962	/* FPROT1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	963	#define FTFA_FPROT1_PROT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	964	#define FTFA_FPROT1_PROT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	965	#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
pradeepvk2208	1:c0c5ac8eac80	966	/* FPROT0 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	967	#define FTFA_FPROT0_PROT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	968	#define FTFA_FPROT0_PROT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	969	#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
pradeepvk2208	1:c0c5ac8eac80	970
pradeepvk2208	1:c0c5ac8eac80	971	/*!
pradeepvk2208	1:c0c5ac8eac80	972	* @}
pradeepvk2208	1:c0c5ac8eac80	973	/ / end of group FTFA_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	974
pradeepvk2208	1:c0c5ac8eac80	975
pradeepvk2208	1:c0c5ac8eac80	976	/* FTFA - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	977	/** Peripheral FTFA base address */
pradeepvk2208	1:c0c5ac8eac80	978	#define FTFA_BASE (0x40020000u)
pradeepvk2208	1:c0c5ac8eac80	979	/** Peripheral FTFA base pointer */
pradeepvk2208	1:c0c5ac8eac80	980	#define FTFA ((FTFA_Type *)FTFA_BASE)
pradeepvk2208	1:c0c5ac8eac80	981	/** Array initializer of FTFA peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	982	#define FTFA_BASES { FTFA }
pradeepvk2208	1:c0c5ac8eac80	983
pradeepvk2208	1:c0c5ac8eac80	984	/*!
pradeepvk2208	1:c0c5ac8eac80	985	* @}
pradeepvk2208	1:c0c5ac8eac80	986	/ / end of group FTFA_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	987
pradeepvk2208	1:c0c5ac8eac80	988
pradeepvk2208	1:c0c5ac8eac80	989	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	990	-- GPIO Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	991	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	992
pradeepvk2208	1:c0c5ac8eac80	993	/*!
pradeepvk2208	1:c0c5ac8eac80	994	* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	995	* @{
pradeepvk2208	1:c0c5ac8eac80	996	*/
pradeepvk2208	1:c0c5ac8eac80	997
pradeepvk2208	1:c0c5ac8eac80	998	/** GPIO - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	999	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	1000	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	1001	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	1002	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	1003	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	1004	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	1005	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
pradeepvk2208	1:c0c5ac8eac80	1006	} GPIO_Type;
pradeepvk2208	1:c0c5ac8eac80	1007
pradeepvk2208	1:c0c5ac8eac80	1008	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	1009	-- GPIO Register Masks
pradeepvk2208	1:c0c5ac8eac80	1010	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	1011
pradeepvk2208	1:c0c5ac8eac80	1012	/*!
pradeepvk2208	1:c0c5ac8eac80	1013	* @addtogroup GPIO_Register_Masks GPIO Register Masks
pradeepvk2208	1:c0c5ac8eac80	1014	* @{
pradeepvk2208	1:c0c5ac8eac80	1015	*/
pradeepvk2208	1:c0c5ac8eac80	1016
pradeepvk2208	1:c0c5ac8eac80	1017	/* PDOR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1018	#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	1019	#define GPIO_PDOR_PDO_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1020	#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
pradeepvk2208	1:c0c5ac8eac80	1021	/* PSOR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1022	#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	1023	#define GPIO_PSOR_PTSO_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1024	#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
pradeepvk2208	1:c0c5ac8eac80	1025	/* PCOR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1026	#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	1027	#define GPIO_PCOR_PTCO_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1028	#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
pradeepvk2208	1:c0c5ac8eac80	1029	/* PTOR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1030	#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	1031	#define GPIO_PTOR_PTTO_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1032	#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
pradeepvk2208	1:c0c5ac8eac80	1033	/* PDIR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1034	#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	1035	#define GPIO_PDIR_PDI_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1036	#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
pradeepvk2208	1:c0c5ac8eac80	1037	/* PDDR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1038	#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	1039	#define GPIO_PDDR_PDD_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1040	#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
pradeepvk2208	1:c0c5ac8eac80	1041
pradeepvk2208	1:c0c5ac8eac80	1042	/*!
pradeepvk2208	1:c0c5ac8eac80	1043	* @}
pradeepvk2208	1:c0c5ac8eac80	1044	/ / end of group GPIO_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	1045
pradeepvk2208	1:c0c5ac8eac80	1046
pradeepvk2208	1:c0c5ac8eac80	1047	/* GPIO - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	1048	/** Peripheral PTA base address */
pradeepvk2208	1:c0c5ac8eac80	1049	#define PTA_BASE (0x400FF000u)
pradeepvk2208	1:c0c5ac8eac80	1050	/** Peripheral PTA base pointer */
pradeepvk2208	1:c0c5ac8eac80	1051	#define PTA ((GPIO_Type *)PTA_BASE)
pradeepvk2208	1:c0c5ac8eac80	1052	/** Peripheral PTB base address */
pradeepvk2208	1:c0c5ac8eac80	1053	#define PTB_BASE (0x400FF040u)
pradeepvk2208	1:c0c5ac8eac80	1054	/** Peripheral PTB base pointer */
pradeepvk2208	1:c0c5ac8eac80	1055	#define PTB ((GPIO_Type *)PTB_BASE)
pradeepvk2208	1:c0c5ac8eac80	1056	/** Peripheral PTC base address */
pradeepvk2208	1:c0c5ac8eac80	1057	#define PTC_BASE (0x400FF080u)
pradeepvk2208	1:c0c5ac8eac80	1058	/** Peripheral PTC base pointer */
pradeepvk2208	1:c0c5ac8eac80	1059	#define PTC ((GPIO_Type *)PTC_BASE)
pradeepvk2208	1:c0c5ac8eac80	1060	/** Peripheral PTD base address */
pradeepvk2208	1:c0c5ac8eac80	1061	#define PTD_BASE (0x400FF0C0u)
pradeepvk2208	1:c0c5ac8eac80	1062	/** Peripheral PTD base pointer */
pradeepvk2208	1:c0c5ac8eac80	1063	#define PTD ((GPIO_Type *)PTD_BASE)
pradeepvk2208	1:c0c5ac8eac80	1064	/** Peripheral PTE base address */
pradeepvk2208	1:c0c5ac8eac80	1065	#define PTE_BASE (0x400FF100u)
pradeepvk2208	1:c0c5ac8eac80	1066	/** Peripheral PTE base pointer */
pradeepvk2208	1:c0c5ac8eac80	1067	#define PTE ((GPIO_Type *)PTE_BASE)
pradeepvk2208	1:c0c5ac8eac80	1068	/** Array initializer of GPIO peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	1069	#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
pradeepvk2208	1:c0c5ac8eac80	1070
pradeepvk2208	1:c0c5ac8eac80	1071	/*!
pradeepvk2208	1:c0c5ac8eac80	1072	* @}
pradeepvk2208	1:c0c5ac8eac80	1073	/ / end of group GPIO_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	1074
pradeepvk2208	1:c0c5ac8eac80	1075
pradeepvk2208	1:c0c5ac8eac80	1076	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	1077	-- I2C Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	1078	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	1079
pradeepvk2208	1:c0c5ac8eac80	1080	/*!
pradeepvk2208	1:c0c5ac8eac80	1081	* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	1082	* @{
pradeepvk2208	1:c0c5ac8eac80	1083	*/
pradeepvk2208	1:c0c5ac8eac80	1084
pradeepvk2208	1:c0c5ac8eac80	1085	/** I2C - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	1086	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	1087	__IO uint8_t A1; /*< I2C Address Register 1, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	1088	__IO uint8_t F; /*< I2C Frequency Divider register, offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	1089	__IO uint8_t C1; /*< I2C Control Register 1, offset: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	1090	__IO uint8_t S; /*< I2C Status register, offset: 0x3 /
pradeepvk2208	1:c0c5ac8eac80	1091	__IO uint8_t D; /*< I2C Data I/O register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	1092	__IO uint8_t C2; /*< I2C Control Register 2, offset: 0x5 /
pradeepvk2208	1:c0c5ac8eac80	1093	__IO uint8_t FLT; /*< I2C Programmable Input Glitch Filter register, offset: 0x6 /
pradeepvk2208	1:c0c5ac8eac80	1094	__IO uint8_t RA; /*< I2C Range Address register, offset: 0x7 /
pradeepvk2208	1:c0c5ac8eac80	1095	__IO uint8_t SMB; /*< I2C SMBus Control and Status register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	1096	__IO uint8_t A2; /*< I2C Address Register 2, offset: 0x9 /
pradeepvk2208	1:c0c5ac8eac80	1097	__IO uint8_t SLTH; /*< I2C SCL Low Timeout Register High, offset: 0xA /
pradeepvk2208	1:c0c5ac8eac80	1098	__IO uint8_t SLTL; /*< I2C SCL Low Timeout Register Low, offset: 0xB /
pradeepvk2208	1:c0c5ac8eac80	1099	} I2C_Type;
pradeepvk2208	1:c0c5ac8eac80	1100
pradeepvk2208	1:c0c5ac8eac80	1101	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	1102	-- I2C Register Masks
pradeepvk2208	1:c0c5ac8eac80	1103	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	1104
pradeepvk2208	1:c0c5ac8eac80	1105	/*!
pradeepvk2208	1:c0c5ac8eac80	1106	* @addtogroup I2C_Register_Masks I2C Register Masks
pradeepvk2208	1:c0c5ac8eac80	1107	* @{
pradeepvk2208	1:c0c5ac8eac80	1108	*/
pradeepvk2208	1:c0c5ac8eac80	1109
pradeepvk2208	1:c0c5ac8eac80	1110	/* A1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1111	#define I2C_A1_AD_MASK 0xFEu
pradeepvk2208	1:c0c5ac8eac80	1112	#define I2C_A1_AD_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1113	#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
pradeepvk2208	1:c0c5ac8eac80	1114	/* F Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1115	#define I2C_F_ICR_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	1116	#define I2C_F_ICR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1117	#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
pradeepvk2208	1:c0c5ac8eac80	1118	#define I2C_F_MULT_MASK 0xC0u
pradeepvk2208	1:c0c5ac8eac80	1119	#define I2C_F_MULT_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	1120	#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
pradeepvk2208	1:c0c5ac8eac80	1121	/* C1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1122	#define I2C_C1_DMAEN_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1123	#define I2C_C1_DMAEN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1124	#define I2C_C1_WUEN_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1125	#define I2C_C1_WUEN_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1126	#define I2C_C1_RSTA_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	1127	#define I2C_C1_RSTA_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	1128	#define I2C_C1_TXAK_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	1129	#define I2C_C1_TXAK_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	1130	#define I2C_C1_TX_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	1131	#define I2C_C1_TX_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	1132	#define I2C_C1_MST_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	1133	#define I2C_C1_MST_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	1134	#define I2C_C1_IICIE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	1135	#define I2C_C1_IICIE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	1136	#define I2C_C1_IICEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	1137	#define I2C_C1_IICEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	1138	/* S Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1139	#define I2C_S_RXAK_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1140	#define I2C_S_RXAK_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1141	#define I2C_S_IICIF_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1142	#define I2C_S_IICIF_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1143	#define I2C_S_SRW_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	1144	#define I2C_S_SRW_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	1145	#define I2C_S_RAM_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	1146	#define I2C_S_RAM_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	1147	#define I2C_S_ARBL_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	1148	#define I2C_S_ARBL_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	1149	#define I2C_S_BUSY_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	1150	#define I2C_S_BUSY_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	1151	#define I2C_S_IAAS_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	1152	#define I2C_S_IAAS_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	1153	#define I2C_S_TCF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	1154	#define I2C_S_TCF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	1155	/* D Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1156	#define I2C_D_DATA_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1157	#define I2C_D_DATA_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1158	#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
pradeepvk2208	1:c0c5ac8eac80	1159	/* C2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1160	#define I2C_C2_AD_MASK 0x7u
pradeepvk2208	1:c0c5ac8eac80	1161	#define I2C_C2_AD_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1162	#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
pradeepvk2208	1:c0c5ac8eac80	1163	#define I2C_C2_RMEN_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	1164	#define I2C_C2_RMEN_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	1165	#define I2C_C2_SBRC_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	1166	#define I2C_C2_SBRC_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	1167	#define I2C_C2_HDRS_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	1168	#define I2C_C2_HDRS_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	1169	#define I2C_C2_ADEXT_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	1170	#define I2C_C2_ADEXT_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	1171	#define I2C_C2_GCAEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	1172	#define I2C_C2_GCAEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	1173	/* FLT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1174	#define I2C_FLT_FLT_MASK 0x1Fu
pradeepvk2208	1:c0c5ac8eac80	1175	#define I2C_FLT_FLT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1176	#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
pradeepvk2208	1:c0c5ac8eac80	1177	#define I2C_FLT_STOPIE_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	1178	#define I2C_FLT_STOPIE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	1179	#define I2C_FLT_STOPF_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	1180	#define I2C_FLT_STOPF_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	1181	#define I2C_FLT_SHEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	1182	#define I2C_FLT_SHEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	1183	/* RA Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1184	#define I2C_RA_RAD_MASK 0xFEu
pradeepvk2208	1:c0c5ac8eac80	1185	#define I2C_RA_RAD_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1186	#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
pradeepvk2208	1:c0c5ac8eac80	1187	/* SMB Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1188	#define I2C_SMB_SHTF2IE_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1189	#define I2C_SMB_SHTF2IE_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1190	#define I2C_SMB_SHTF2_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1191	#define I2C_SMB_SHTF2_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1192	#define I2C_SMB_SHTF1_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	1193	#define I2C_SMB_SHTF1_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	1194	#define I2C_SMB_SLTF_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	1195	#define I2C_SMB_SLTF_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	1196	#define I2C_SMB_TCKSEL_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	1197	#define I2C_SMB_TCKSEL_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	1198	#define I2C_SMB_SIICAEN_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	1199	#define I2C_SMB_SIICAEN_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	1200	#define I2C_SMB_ALERTEN_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	1201	#define I2C_SMB_ALERTEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	1202	#define I2C_SMB_FACK_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	1203	#define I2C_SMB_FACK_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	1204	/* A2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1205	#define I2C_A2_SAD_MASK 0xFEu
pradeepvk2208	1:c0c5ac8eac80	1206	#define I2C_A2_SAD_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1207	#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
pradeepvk2208	1:c0c5ac8eac80	1208	/* SLTH Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1209	#define I2C_SLTH_SSLT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1210	#define I2C_SLTH_SSLT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1211	#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
pradeepvk2208	1:c0c5ac8eac80	1212	/* SLTL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1213	#define I2C_SLTL_SSLT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1214	#define I2C_SLTL_SSLT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1215	#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
pradeepvk2208	1:c0c5ac8eac80	1216
pradeepvk2208	1:c0c5ac8eac80	1217	/*!
pradeepvk2208	1:c0c5ac8eac80	1218	* @}
pradeepvk2208	1:c0c5ac8eac80	1219	/ / end of group I2C_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	1220
pradeepvk2208	1:c0c5ac8eac80	1221
pradeepvk2208	1:c0c5ac8eac80	1222	/* I2C - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	1223	/** Peripheral I2C0 base address */
pradeepvk2208	1:c0c5ac8eac80	1224	#define I2C0_BASE (0x40066000u)
pradeepvk2208	1:c0c5ac8eac80	1225	/** Peripheral I2C0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	1226	#define I2C0 ((I2C_Type *)I2C0_BASE)
pradeepvk2208	1:c0c5ac8eac80	1227	/** Peripheral I2C1 base address */
pradeepvk2208	1:c0c5ac8eac80	1228	#define I2C1_BASE (0x40067000u)
pradeepvk2208	1:c0c5ac8eac80	1229	/** Peripheral I2C1 base pointer */
pradeepvk2208	1:c0c5ac8eac80	1230	#define I2C1 ((I2C_Type *)I2C1_BASE)
pradeepvk2208	1:c0c5ac8eac80	1231	/** Array initializer of I2C peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	1232	#define I2C_BASES { I2C0, I2C1 }
pradeepvk2208	1:c0c5ac8eac80	1233
pradeepvk2208	1:c0c5ac8eac80	1234	/*!
pradeepvk2208	1:c0c5ac8eac80	1235	* @}
pradeepvk2208	1:c0c5ac8eac80	1236	/ / end of group I2C_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	1237
pradeepvk2208	1:c0c5ac8eac80	1238
pradeepvk2208	1:c0c5ac8eac80	1239	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	1240	-- I2S Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	1241	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	1242
pradeepvk2208	1:c0c5ac8eac80	1243	/*!
pradeepvk2208	1:c0c5ac8eac80	1244	* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	1245	* @{
pradeepvk2208	1:c0c5ac8eac80	1246	*/
pradeepvk2208	1:c0c5ac8eac80	1247
pradeepvk2208	1:c0c5ac8eac80	1248	/** I2S - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	1249	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	1250	__IO uint32_t TCSR; /*< SAI Transmit Control Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	1251	uint8_t RESERVED_0[4];
pradeepvk2208	1:c0c5ac8eac80	1252	__IO uint32_t TCR2; /*< SAI Transmit Configuration 2 Register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	1253	__IO uint32_t TCR3; /*< SAI Transmit Configuration 3 Register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	1254	__IO uint32_t TCR4; /*< SAI Transmit Configuration 4 Register, offset: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	1255	__IO uint32_t TCR5; /*< SAI Transmit Configuration 5 Register, offset: 0x14 /
pradeepvk2208	1:c0c5ac8eac80	1256	uint8_t RESERVED_1[8];
pradeepvk2208	1:c0c5ac8eac80	1257	__O uint32_t TDR[1]; /*< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	1258	uint8_t RESERVED_2[60];
pradeepvk2208	1:c0c5ac8eac80	1259	__IO uint32_t TMR; /*< SAI Transmit Mask Register, offset: 0x60 /
pradeepvk2208	1:c0c5ac8eac80	1260	uint8_t RESERVED_3[28];
pradeepvk2208	1:c0c5ac8eac80	1261	__IO uint32_t RCSR; /*< SAI Receive Control Register, offset: 0x80 /
pradeepvk2208	1:c0c5ac8eac80	1262	uint8_t RESERVED_4[4];
pradeepvk2208	1:c0c5ac8eac80	1263	__IO uint32_t RCR2; /*< SAI Receive Configuration 2 Register, offset: 0x88 /
pradeepvk2208	1:c0c5ac8eac80	1264	__IO uint32_t RCR3; /*< SAI Receive Configuration 3 Register, offset: 0x8C /
pradeepvk2208	1:c0c5ac8eac80	1265	__IO uint32_t RCR4; /*< SAI Receive Configuration 4 Register, offset: 0x90 /
pradeepvk2208	1:c0c5ac8eac80	1266	__IO uint32_t RCR5; /*< SAI Receive Configuration 5 Register, offset: 0x94 /
pradeepvk2208	1:c0c5ac8eac80	1267	uint8_t RESERVED_5[8];
pradeepvk2208	1:c0c5ac8eac80	1268	__I uint32_t RDR[1]; /*< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	1269	uint8_t RESERVED_6[60];
pradeepvk2208	1:c0c5ac8eac80	1270	__IO uint32_t RMR; /*< SAI Receive Mask Register, offset: 0xE0 /
pradeepvk2208	1:c0c5ac8eac80	1271	uint8_t RESERVED_7[28];
pradeepvk2208	1:c0c5ac8eac80	1272	__IO uint32_t MCR; /*< SAI MCLK Control Register, offset: 0x100 /
pradeepvk2208	1:c0c5ac8eac80	1273	__IO uint32_t MDR; /*< SAI MCLK Divide Register, offset: 0x104 /
pradeepvk2208	1:c0c5ac8eac80	1274	} I2S_Type;
pradeepvk2208	1:c0c5ac8eac80	1275
pradeepvk2208	1:c0c5ac8eac80	1276	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	1277	-- I2S Register Masks
pradeepvk2208	1:c0c5ac8eac80	1278	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	1279
pradeepvk2208	1:c0c5ac8eac80	1280	/*!
pradeepvk2208	1:c0c5ac8eac80	1281	* @addtogroup I2S_Register_Masks I2S Register Masks
pradeepvk2208	1:c0c5ac8eac80	1282	* @{
pradeepvk2208	1:c0c5ac8eac80	1283	*/
pradeepvk2208	1:c0c5ac8eac80	1284
pradeepvk2208	1:c0c5ac8eac80	1285	/* TCSR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1286	#define I2S_TCSR_FWDE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1287	#define I2S_TCSR_FWDE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1288	#define I2S_TCSR_FWIE_MASK 0x200u
pradeepvk2208	1:c0c5ac8eac80	1289	#define I2S_TCSR_FWIE_SHIFT 9
pradeepvk2208	1:c0c5ac8eac80	1290	#define I2S_TCSR_FEIE_MASK 0x400u
pradeepvk2208	1:c0c5ac8eac80	1291	#define I2S_TCSR_FEIE_SHIFT 10
pradeepvk2208	1:c0c5ac8eac80	1292	#define I2S_TCSR_SEIE_MASK 0x800u
pradeepvk2208	1:c0c5ac8eac80	1293	#define I2S_TCSR_SEIE_SHIFT 11
pradeepvk2208	1:c0c5ac8eac80	1294	#define I2S_TCSR_WSIE_MASK 0x1000u
pradeepvk2208	1:c0c5ac8eac80	1295	#define I2S_TCSR_WSIE_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	1296	#define I2S_TCSR_FWF_MASK 0x20000u
pradeepvk2208	1:c0c5ac8eac80	1297	#define I2S_TCSR_FWF_SHIFT 17
pradeepvk2208	1:c0c5ac8eac80	1298	#define I2S_TCSR_FEF_MASK 0x40000u
pradeepvk2208	1:c0c5ac8eac80	1299	#define I2S_TCSR_FEF_SHIFT 18
pradeepvk2208	1:c0c5ac8eac80	1300	#define I2S_TCSR_SEF_MASK 0x80000u
pradeepvk2208	1:c0c5ac8eac80	1301	#define I2S_TCSR_SEF_SHIFT 19
pradeepvk2208	1:c0c5ac8eac80	1302	#define I2S_TCSR_WSF_MASK 0x100000u
pradeepvk2208	1:c0c5ac8eac80	1303	#define I2S_TCSR_WSF_SHIFT 20
pradeepvk2208	1:c0c5ac8eac80	1304	#define I2S_TCSR_SR_MASK 0x1000000u
pradeepvk2208	1:c0c5ac8eac80	1305	#define I2S_TCSR_SR_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1306	#define I2S_TCSR_FR_MASK 0x2000000u
pradeepvk2208	1:c0c5ac8eac80	1307	#define I2S_TCSR_FR_SHIFT 25
pradeepvk2208	1:c0c5ac8eac80	1308	#define I2S_TCSR_BCE_MASK 0x10000000u
pradeepvk2208	1:c0c5ac8eac80	1309	#define I2S_TCSR_BCE_SHIFT 28
pradeepvk2208	1:c0c5ac8eac80	1310	#define I2S_TCSR_DBGE_MASK 0x20000000u
pradeepvk2208	1:c0c5ac8eac80	1311	#define I2S_TCSR_DBGE_SHIFT 29
pradeepvk2208	1:c0c5ac8eac80	1312	#define I2S_TCSR_STOPE_MASK 0x40000000u
pradeepvk2208	1:c0c5ac8eac80	1313	#define I2S_TCSR_STOPE_SHIFT 30
pradeepvk2208	1:c0c5ac8eac80	1314	#define I2S_TCSR_TE_MASK 0x80000000u
pradeepvk2208	1:c0c5ac8eac80	1315	#define I2S_TCSR_TE_SHIFT 31
pradeepvk2208	1:c0c5ac8eac80	1316	/* TCR2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1317	#define I2S_TCR2_DIV_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1318	#define I2S_TCR2_DIV_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1319	#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
pradeepvk2208	1:c0c5ac8eac80	1320	#define I2S_TCR2_BCD_MASK 0x1000000u
pradeepvk2208	1:c0c5ac8eac80	1321	#define I2S_TCR2_BCD_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1322	#define I2S_TCR2_BCP_MASK 0x2000000u
pradeepvk2208	1:c0c5ac8eac80	1323	#define I2S_TCR2_BCP_SHIFT 25
pradeepvk2208	1:c0c5ac8eac80	1324	#define I2S_TCR2_CLKMODE_MASK 0xC000000u
pradeepvk2208	1:c0c5ac8eac80	1325	#define I2S_TCR2_CLKMODE_SHIFT 26
pradeepvk2208	1:c0c5ac8eac80	1326	#define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
pradeepvk2208	1:c0c5ac8eac80	1327	/* TCR3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1328	#define I2S_TCR3_WDFL_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1329	#define I2S_TCR3_WDFL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1330	#define I2S_TCR3_TCE_MASK 0x10000u
pradeepvk2208	1:c0c5ac8eac80	1331	#define I2S_TCR3_TCE_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1332	/* TCR4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1333	#define I2S_TCR4_FSD_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1334	#define I2S_TCR4_FSD_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1335	#define I2S_TCR4_FSP_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1336	#define I2S_TCR4_FSP_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1337	#define I2S_TCR4_FSE_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	1338	#define I2S_TCR4_FSE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	1339	#define I2S_TCR4_MF_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	1340	#define I2S_TCR4_MF_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	1341	#define I2S_TCR4_SYWD_MASK 0x1F00u
pradeepvk2208	1:c0c5ac8eac80	1342	#define I2S_TCR4_SYWD_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1343	#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
pradeepvk2208	1:c0c5ac8eac80	1344	#define I2S_TCR4_FRSZ_MASK 0x10000u
pradeepvk2208	1:c0c5ac8eac80	1345	#define I2S_TCR4_FRSZ_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1346	/* TCR5 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1347	#define I2S_TCR5_FBT_MASK 0x1F00u
pradeepvk2208	1:c0c5ac8eac80	1348	#define I2S_TCR5_FBT_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1349	#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
pradeepvk2208	1:c0c5ac8eac80	1350	#define I2S_TCR5_W0W_MASK 0x1F0000u
pradeepvk2208	1:c0c5ac8eac80	1351	#define I2S_TCR5_W0W_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1352	#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
pradeepvk2208	1:c0c5ac8eac80	1353	#define I2S_TCR5_WNW_MASK 0x1F000000u
pradeepvk2208	1:c0c5ac8eac80	1354	#define I2S_TCR5_WNW_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1355	#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
pradeepvk2208	1:c0c5ac8eac80	1356	/* TDR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1357	#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	1358	#define I2S_TDR_TDR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1359	#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
pradeepvk2208	1:c0c5ac8eac80	1360	/* TMR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1361	#define I2S_TMR_TWM_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	1362	#define I2S_TMR_TWM_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1363	#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
pradeepvk2208	1:c0c5ac8eac80	1364	/* RCSR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1365	#define I2S_RCSR_FWDE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1366	#define I2S_RCSR_FWDE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1367	#define I2S_RCSR_FWIE_MASK 0x200u
pradeepvk2208	1:c0c5ac8eac80	1368	#define I2S_RCSR_FWIE_SHIFT 9
pradeepvk2208	1:c0c5ac8eac80	1369	#define I2S_RCSR_FEIE_MASK 0x400u
pradeepvk2208	1:c0c5ac8eac80	1370	#define I2S_RCSR_FEIE_SHIFT 10
pradeepvk2208	1:c0c5ac8eac80	1371	#define I2S_RCSR_SEIE_MASK 0x800u
pradeepvk2208	1:c0c5ac8eac80	1372	#define I2S_RCSR_SEIE_SHIFT 11
pradeepvk2208	1:c0c5ac8eac80	1373	#define I2S_RCSR_WSIE_MASK 0x1000u
pradeepvk2208	1:c0c5ac8eac80	1374	#define I2S_RCSR_WSIE_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	1375	#define I2S_RCSR_FWF_MASK 0x20000u
pradeepvk2208	1:c0c5ac8eac80	1376	#define I2S_RCSR_FWF_SHIFT 17
pradeepvk2208	1:c0c5ac8eac80	1377	#define I2S_RCSR_FEF_MASK 0x40000u
pradeepvk2208	1:c0c5ac8eac80	1378	#define I2S_RCSR_FEF_SHIFT 18
pradeepvk2208	1:c0c5ac8eac80	1379	#define I2S_RCSR_SEF_MASK 0x80000u
pradeepvk2208	1:c0c5ac8eac80	1380	#define I2S_RCSR_SEF_SHIFT 19
pradeepvk2208	1:c0c5ac8eac80	1381	#define I2S_RCSR_WSF_MASK 0x100000u
pradeepvk2208	1:c0c5ac8eac80	1382	#define I2S_RCSR_WSF_SHIFT 20
pradeepvk2208	1:c0c5ac8eac80	1383	#define I2S_RCSR_SR_MASK 0x1000000u
pradeepvk2208	1:c0c5ac8eac80	1384	#define I2S_RCSR_SR_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1385	#define I2S_RCSR_FR_MASK 0x2000000u
pradeepvk2208	1:c0c5ac8eac80	1386	#define I2S_RCSR_FR_SHIFT 25
pradeepvk2208	1:c0c5ac8eac80	1387	#define I2S_RCSR_BCE_MASK 0x10000000u
pradeepvk2208	1:c0c5ac8eac80	1388	#define I2S_RCSR_BCE_SHIFT 28
pradeepvk2208	1:c0c5ac8eac80	1389	#define I2S_RCSR_DBGE_MASK 0x20000000u
pradeepvk2208	1:c0c5ac8eac80	1390	#define I2S_RCSR_DBGE_SHIFT 29
pradeepvk2208	1:c0c5ac8eac80	1391	#define I2S_RCSR_STOPE_MASK 0x40000000u
pradeepvk2208	1:c0c5ac8eac80	1392	#define I2S_RCSR_STOPE_SHIFT 30
pradeepvk2208	1:c0c5ac8eac80	1393	#define I2S_RCSR_RE_MASK 0x80000000u
pradeepvk2208	1:c0c5ac8eac80	1394	#define I2S_RCSR_RE_SHIFT 31
pradeepvk2208	1:c0c5ac8eac80	1395	/* RCR2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1396	#define I2S_RCR2_DIV_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1397	#define I2S_RCR2_DIV_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1398	#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
pradeepvk2208	1:c0c5ac8eac80	1399	#define I2S_RCR2_BCD_MASK 0x1000000u
pradeepvk2208	1:c0c5ac8eac80	1400	#define I2S_RCR2_BCD_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1401	#define I2S_RCR2_BCP_MASK 0x2000000u
pradeepvk2208	1:c0c5ac8eac80	1402	#define I2S_RCR2_BCP_SHIFT 25
pradeepvk2208	1:c0c5ac8eac80	1403	#define I2S_RCR2_CLKMODE_MASK 0xC000000u
pradeepvk2208	1:c0c5ac8eac80	1404	#define I2S_RCR2_CLKMODE_SHIFT 26
pradeepvk2208	1:c0c5ac8eac80	1405	#define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
pradeepvk2208	1:c0c5ac8eac80	1406	/* RCR3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1407	#define I2S_RCR3_WDFL_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1408	#define I2S_RCR3_WDFL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1409	#define I2S_RCR3_RCE_MASK 0x10000u
pradeepvk2208	1:c0c5ac8eac80	1410	#define I2S_RCR3_RCE_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1411	/* RCR4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1412	#define I2S_RCR4_FSD_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1413	#define I2S_RCR4_FSD_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1414	#define I2S_RCR4_FSP_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1415	#define I2S_RCR4_FSP_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1416	#define I2S_RCR4_FSE_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	1417	#define I2S_RCR4_FSE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	1418	#define I2S_RCR4_MF_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	1419	#define I2S_RCR4_MF_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	1420	#define I2S_RCR4_SYWD_MASK 0x1F00u
pradeepvk2208	1:c0c5ac8eac80	1421	#define I2S_RCR4_SYWD_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1422	#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
pradeepvk2208	1:c0c5ac8eac80	1423	#define I2S_RCR4_FRSZ_MASK 0x10000u
pradeepvk2208	1:c0c5ac8eac80	1424	#define I2S_RCR4_FRSZ_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1425	/* RCR5 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1426	#define I2S_RCR5_FBT_MASK 0x1F00u
pradeepvk2208	1:c0c5ac8eac80	1427	#define I2S_RCR5_FBT_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1428	#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
pradeepvk2208	1:c0c5ac8eac80	1429	#define I2S_RCR5_W0W_MASK 0x1F0000u
pradeepvk2208	1:c0c5ac8eac80	1430	#define I2S_RCR5_W0W_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1431	#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
pradeepvk2208	1:c0c5ac8eac80	1432	#define I2S_RCR5_WNW_MASK 0x1F000000u
pradeepvk2208	1:c0c5ac8eac80	1433	#define I2S_RCR5_WNW_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1434	#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
pradeepvk2208	1:c0c5ac8eac80	1435	/* RDR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1436	#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	1437	#define I2S_RDR_RDR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1438	#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
pradeepvk2208	1:c0c5ac8eac80	1439	/* RMR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1440	#define I2S_RMR_RWM_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	1441	#define I2S_RMR_RWM_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1442	#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
pradeepvk2208	1:c0c5ac8eac80	1443	/* MCR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1444	#define I2S_MCR_MICS_MASK 0x3000000u
pradeepvk2208	1:c0c5ac8eac80	1445	#define I2S_MCR_MICS_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1446	#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
pradeepvk2208	1:c0c5ac8eac80	1447	#define I2S_MCR_MOE_MASK 0x40000000u
pradeepvk2208	1:c0c5ac8eac80	1448	#define I2S_MCR_MOE_SHIFT 30
pradeepvk2208	1:c0c5ac8eac80	1449	#define I2S_MCR_DUF_MASK 0x80000000u
pradeepvk2208	1:c0c5ac8eac80	1450	#define I2S_MCR_DUF_SHIFT 31
pradeepvk2208	1:c0c5ac8eac80	1451	/* MDR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1452	#define I2S_MDR_DIVIDE_MASK 0xFFFu
pradeepvk2208	1:c0c5ac8eac80	1453	#define I2S_MDR_DIVIDE_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1454	#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
pradeepvk2208	1:c0c5ac8eac80	1455	#define I2S_MDR_FRACT_MASK 0xFF000u
pradeepvk2208	1:c0c5ac8eac80	1456	#define I2S_MDR_FRACT_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	1457	#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
pradeepvk2208	1:c0c5ac8eac80	1458
pradeepvk2208	1:c0c5ac8eac80	1459	/*!
pradeepvk2208	1:c0c5ac8eac80	1460	* @}
pradeepvk2208	1:c0c5ac8eac80	1461	/ / end of group I2S_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	1462
pradeepvk2208	1:c0c5ac8eac80	1463
pradeepvk2208	1:c0c5ac8eac80	1464	/* I2S - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	1465	/** Peripheral I2S0 base address */
pradeepvk2208	1:c0c5ac8eac80	1466	#define I2S0_BASE (0x4002F000u)
pradeepvk2208	1:c0c5ac8eac80	1467	/** Peripheral I2S0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	1468	#define I2S0 ((I2S_Type *)I2S0_BASE)
pradeepvk2208	1:c0c5ac8eac80	1469	/** Array initializer of I2S peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	1470	#define I2S_BASES { I2S0 }
pradeepvk2208	1:c0c5ac8eac80	1471
pradeepvk2208	1:c0c5ac8eac80	1472	/*!
pradeepvk2208	1:c0c5ac8eac80	1473	* @}
pradeepvk2208	1:c0c5ac8eac80	1474	/ / end of group I2S_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	1475
pradeepvk2208	1:c0c5ac8eac80	1476
pradeepvk2208	1:c0c5ac8eac80	1477	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	1478	-- LCD Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	1479	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	1480
pradeepvk2208	1:c0c5ac8eac80	1481	/*!
pradeepvk2208	1:c0c5ac8eac80	1482	* @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	1483	* @{
pradeepvk2208	1:c0c5ac8eac80	1484	*/
pradeepvk2208	1:c0c5ac8eac80	1485
pradeepvk2208	1:c0c5ac8eac80	1486	/** LCD - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	1487	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	1488	__IO uint32_t GCR; /*< LCD General Control Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	1489	__IO uint32_t AR; /*< LCD Auxiliary Register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	1490	__IO uint32_t FDCR; /*< LCD Fault Detect Control Register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	1491	__IO uint32_t FDSR; /*< LCD Fault Detect Status Register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	1492	__IO uint32_t PEN[2]; /*< LCD Pin Enable register, array offset: 0x10, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	1493	__IO uint32_t BPEN[2]; /*< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	1494	union { /* offset: 0x20 */
pradeepvk2208	1:c0c5ac8eac80	1495	__IO uint32_t WF[16]; /*< LCD Waveform register, array offset: 0x20, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	1496	__IO uint8_t WF8B[64]; /*< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	1497	};
pradeepvk2208	1:c0c5ac8eac80	1498	} LCD_Type;
pradeepvk2208	1:c0c5ac8eac80	1499
pradeepvk2208	1:c0c5ac8eac80	1500	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	1501	-- LCD Register Masks
pradeepvk2208	1:c0c5ac8eac80	1502	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	1503
pradeepvk2208	1:c0c5ac8eac80	1504	/*!
pradeepvk2208	1:c0c5ac8eac80	1505	* @addtogroup LCD_Register_Masks LCD Register Masks
pradeepvk2208	1:c0c5ac8eac80	1506	* @{
pradeepvk2208	1:c0c5ac8eac80	1507	*/
pradeepvk2208	1:c0c5ac8eac80	1508
pradeepvk2208	1:c0c5ac8eac80	1509	/* GCR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1510	#define LCD_GCR_DUTY_MASK 0x7u
pradeepvk2208	1:c0c5ac8eac80	1511	#define LCD_GCR_DUTY_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1512	#define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
pradeepvk2208	1:c0c5ac8eac80	1513	#define LCD_GCR_LCLK_MASK 0x38u
pradeepvk2208	1:c0c5ac8eac80	1514	#define LCD_GCR_LCLK_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	1515	#define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
pradeepvk2208	1:c0c5ac8eac80	1516	#define LCD_GCR_SOURCE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	1517	#define LCD_GCR_SOURCE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	1518	#define LCD_GCR_LCDEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	1519	#define LCD_GCR_LCDEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	1520	#define LCD_GCR_LCDSTP_MASK 0x100u
pradeepvk2208	1:c0c5ac8eac80	1521	#define LCD_GCR_LCDSTP_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1522	#define LCD_GCR_LCDDOZE_MASK 0x200u
pradeepvk2208	1:c0c5ac8eac80	1523	#define LCD_GCR_LCDDOZE_SHIFT 9
pradeepvk2208	1:c0c5ac8eac80	1524	#define LCD_GCR_FFR_MASK 0x400u
pradeepvk2208	1:c0c5ac8eac80	1525	#define LCD_GCR_FFR_SHIFT 10
pradeepvk2208	1:c0c5ac8eac80	1526	#define LCD_GCR_ALTSOURCE_MASK 0x800u
pradeepvk2208	1:c0c5ac8eac80	1527	#define LCD_GCR_ALTSOURCE_SHIFT 11
pradeepvk2208	1:c0c5ac8eac80	1528	#define LCD_GCR_ALTDIV_MASK 0x3000u
pradeepvk2208	1:c0c5ac8eac80	1529	#define LCD_GCR_ALTDIV_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	1530	#define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
pradeepvk2208	1:c0c5ac8eac80	1531	#define LCD_GCR_FDCIEN_MASK 0x4000u
pradeepvk2208	1:c0c5ac8eac80	1532	#define LCD_GCR_FDCIEN_SHIFT 14
pradeepvk2208	1:c0c5ac8eac80	1533	#define LCD_GCR_PADSAFE_MASK 0x8000u
pradeepvk2208	1:c0c5ac8eac80	1534	#define LCD_GCR_PADSAFE_SHIFT 15
pradeepvk2208	1:c0c5ac8eac80	1535	#define LCD_GCR_VSUPPLY_MASK 0x20000u
pradeepvk2208	1:c0c5ac8eac80	1536	#define LCD_GCR_VSUPPLY_SHIFT 17
pradeepvk2208	1:c0c5ac8eac80	1537	#define LCD_GCR_LADJ_MASK 0x300000u
pradeepvk2208	1:c0c5ac8eac80	1538	#define LCD_GCR_LADJ_SHIFT 20
pradeepvk2208	1:c0c5ac8eac80	1539	#define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
pradeepvk2208	1:c0c5ac8eac80	1540	#define LCD_GCR_CPSEL_MASK 0x800000u
pradeepvk2208	1:c0c5ac8eac80	1541	#define LCD_GCR_CPSEL_SHIFT 23
pradeepvk2208	1:c0c5ac8eac80	1542	#define LCD_GCR_RVTRIM_MASK 0xF000000u
pradeepvk2208	1:c0c5ac8eac80	1543	#define LCD_GCR_RVTRIM_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1544	#define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
pradeepvk2208	1:c0c5ac8eac80	1545	#define LCD_GCR_RVEN_MASK 0x80000000u
pradeepvk2208	1:c0c5ac8eac80	1546	#define LCD_GCR_RVEN_SHIFT 31
pradeepvk2208	1:c0c5ac8eac80	1547	/* AR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1548	#define LCD_AR_BRATE_MASK 0x7u
pradeepvk2208	1:c0c5ac8eac80	1549	#define LCD_AR_BRATE_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1550	#define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
pradeepvk2208	1:c0c5ac8eac80	1551	#define LCD_AR_BMODE_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	1552	#define LCD_AR_BMODE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	1553	#define LCD_AR_BLANK_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	1554	#define LCD_AR_BLANK_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	1555	#define LCD_AR_ALT_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	1556	#define LCD_AR_ALT_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	1557	#define LCD_AR_BLINK_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	1558	#define LCD_AR_BLINK_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	1559	/* FDCR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1560	#define LCD_FDCR_FDPINID_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	1561	#define LCD_FDCR_FDPINID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1562	#define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
pradeepvk2208	1:c0c5ac8eac80	1563	#define LCD_FDCR_FDBPEN_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	1564	#define LCD_FDCR_FDBPEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	1565	#define LCD_FDCR_FDEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	1566	#define LCD_FDCR_FDEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	1567	#define LCD_FDCR_FDSWW_MASK 0xE00u
pradeepvk2208	1:c0c5ac8eac80	1568	#define LCD_FDCR_FDSWW_SHIFT 9
pradeepvk2208	1:c0c5ac8eac80	1569	#define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
pradeepvk2208	1:c0c5ac8eac80	1570	#define LCD_FDCR_FDPRS_MASK 0x7000u
pradeepvk2208	1:c0c5ac8eac80	1571	#define LCD_FDCR_FDPRS_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	1572	#define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
pradeepvk2208	1:c0c5ac8eac80	1573	/* FDSR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1574	#define LCD_FDSR_FDCNT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1575	#define LCD_FDSR_FDCNT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1576	#define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
pradeepvk2208	1:c0c5ac8eac80	1577	#define LCD_FDSR_FDCF_MASK 0x8000u
pradeepvk2208	1:c0c5ac8eac80	1578	#define LCD_FDSR_FDCF_SHIFT 15
pradeepvk2208	1:c0c5ac8eac80	1579	/* PEN Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1580	#define LCD_PEN_PEN_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	1581	#define LCD_PEN_PEN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1582	#define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
pradeepvk2208	1:c0c5ac8eac80	1583	/* BPEN Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1584	#define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	1585	#define LCD_BPEN_BPEN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1586	#define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
pradeepvk2208	1:c0c5ac8eac80	1587	/* WF Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1588	#define LCD_WF_WF0_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1589	#define LCD_WF_WF0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1590	#define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
pradeepvk2208	1:c0c5ac8eac80	1591	#define LCD_WF_WF60_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1592	#define LCD_WF_WF60_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1593	#define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
pradeepvk2208	1:c0c5ac8eac80	1594	#define LCD_WF_WF56_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1595	#define LCD_WF_WF56_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1596	#define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
pradeepvk2208	1:c0c5ac8eac80	1597	#define LCD_WF_WF52_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1598	#define LCD_WF_WF52_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1599	#define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
pradeepvk2208	1:c0c5ac8eac80	1600	#define LCD_WF_WF4_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1601	#define LCD_WF_WF4_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1602	#define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
pradeepvk2208	1:c0c5ac8eac80	1603	#define LCD_WF_WF48_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1604	#define LCD_WF_WF48_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1605	#define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
pradeepvk2208	1:c0c5ac8eac80	1606	#define LCD_WF_WF44_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1607	#define LCD_WF_WF44_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1608	#define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
pradeepvk2208	1:c0c5ac8eac80	1609	#define LCD_WF_WF40_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1610	#define LCD_WF_WF40_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1611	#define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
pradeepvk2208	1:c0c5ac8eac80	1612	#define LCD_WF_WF8_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1613	#define LCD_WF_WF8_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1614	#define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
pradeepvk2208	1:c0c5ac8eac80	1615	#define LCD_WF_WF36_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1616	#define LCD_WF_WF36_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1617	#define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
pradeepvk2208	1:c0c5ac8eac80	1618	#define LCD_WF_WF32_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1619	#define LCD_WF_WF32_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1620	#define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
pradeepvk2208	1:c0c5ac8eac80	1621	#define LCD_WF_WF28_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1622	#define LCD_WF_WF28_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1623	#define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
pradeepvk2208	1:c0c5ac8eac80	1624	#define LCD_WF_WF12_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1625	#define LCD_WF_WF12_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1626	#define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
pradeepvk2208	1:c0c5ac8eac80	1627	#define LCD_WF_WF24_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1628	#define LCD_WF_WF24_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1629	#define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
pradeepvk2208	1:c0c5ac8eac80	1630	#define LCD_WF_WF20_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1631	#define LCD_WF_WF20_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1632	#define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
pradeepvk2208	1:c0c5ac8eac80	1633	#define LCD_WF_WF16_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	1634	#define LCD_WF_WF16_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1635	#define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
pradeepvk2208	1:c0c5ac8eac80	1636	#define LCD_WF_WF5_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1637	#define LCD_WF_WF5_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1638	#define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
pradeepvk2208	1:c0c5ac8eac80	1639	#define LCD_WF_WF49_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1640	#define LCD_WF_WF49_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1641	#define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
pradeepvk2208	1:c0c5ac8eac80	1642	#define LCD_WF_WF45_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1643	#define LCD_WF_WF45_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1644	#define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
pradeepvk2208	1:c0c5ac8eac80	1645	#define LCD_WF_WF61_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1646	#define LCD_WF_WF61_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1647	#define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
pradeepvk2208	1:c0c5ac8eac80	1648	#define LCD_WF_WF25_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1649	#define LCD_WF_WF25_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1650	#define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
pradeepvk2208	1:c0c5ac8eac80	1651	#define LCD_WF_WF17_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1652	#define LCD_WF_WF17_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1653	#define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
pradeepvk2208	1:c0c5ac8eac80	1654	#define LCD_WF_WF41_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1655	#define LCD_WF_WF41_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1656	#define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
pradeepvk2208	1:c0c5ac8eac80	1657	#define LCD_WF_WF13_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1658	#define LCD_WF_WF13_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1659	#define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
pradeepvk2208	1:c0c5ac8eac80	1660	#define LCD_WF_WF57_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1661	#define LCD_WF_WF57_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1662	#define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
pradeepvk2208	1:c0c5ac8eac80	1663	#define LCD_WF_WF53_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1664	#define LCD_WF_WF53_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1665	#define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
pradeepvk2208	1:c0c5ac8eac80	1666	#define LCD_WF_WF37_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1667	#define LCD_WF_WF37_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1668	#define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
pradeepvk2208	1:c0c5ac8eac80	1669	#define LCD_WF_WF9_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1670	#define LCD_WF_WF9_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1671	#define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
pradeepvk2208	1:c0c5ac8eac80	1672	#define LCD_WF_WF1_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1673	#define LCD_WF_WF1_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1674	#define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
pradeepvk2208	1:c0c5ac8eac80	1675	#define LCD_WF_WF29_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1676	#define LCD_WF_WF29_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1677	#define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
pradeepvk2208	1:c0c5ac8eac80	1678	#define LCD_WF_WF33_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1679	#define LCD_WF_WF33_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1680	#define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
pradeepvk2208	1:c0c5ac8eac80	1681	#define LCD_WF_WF21_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	1682	#define LCD_WF_WF21_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	1683	#define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
pradeepvk2208	1:c0c5ac8eac80	1684	#define LCD_WF_WF26_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1685	#define LCD_WF_WF26_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1686	#define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
pradeepvk2208	1:c0c5ac8eac80	1687	#define LCD_WF_WF46_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1688	#define LCD_WF_WF46_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1689	#define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
pradeepvk2208	1:c0c5ac8eac80	1690	#define LCD_WF_WF6_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1691	#define LCD_WF_WF6_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1692	#define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
pradeepvk2208	1:c0c5ac8eac80	1693	#define LCD_WF_WF42_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1694	#define LCD_WF_WF42_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1695	#define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
pradeepvk2208	1:c0c5ac8eac80	1696	#define LCD_WF_WF18_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1697	#define LCD_WF_WF18_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1698	#define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
pradeepvk2208	1:c0c5ac8eac80	1699	#define LCD_WF_WF38_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1700	#define LCD_WF_WF38_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1701	#define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
pradeepvk2208	1:c0c5ac8eac80	1702	#define LCD_WF_WF22_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1703	#define LCD_WF_WF22_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1704	#define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
pradeepvk2208	1:c0c5ac8eac80	1705	#define LCD_WF_WF34_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1706	#define LCD_WF_WF34_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1707	#define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
pradeepvk2208	1:c0c5ac8eac80	1708	#define LCD_WF_WF50_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1709	#define LCD_WF_WF50_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1710	#define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
pradeepvk2208	1:c0c5ac8eac80	1711	#define LCD_WF_WF14_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1712	#define LCD_WF_WF14_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1713	#define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
pradeepvk2208	1:c0c5ac8eac80	1714	#define LCD_WF_WF54_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1715	#define LCD_WF_WF54_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1716	#define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
pradeepvk2208	1:c0c5ac8eac80	1717	#define LCD_WF_WF2_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1718	#define LCD_WF_WF2_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1719	#define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
pradeepvk2208	1:c0c5ac8eac80	1720	#define LCD_WF_WF58_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1721	#define LCD_WF_WF58_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1722	#define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
pradeepvk2208	1:c0c5ac8eac80	1723	#define LCD_WF_WF30_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1724	#define LCD_WF_WF30_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1725	#define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
pradeepvk2208	1:c0c5ac8eac80	1726	#define LCD_WF_WF62_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1727	#define LCD_WF_WF62_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1728	#define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
pradeepvk2208	1:c0c5ac8eac80	1729	#define LCD_WF_WF10_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	1730	#define LCD_WF_WF10_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	1731	#define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
pradeepvk2208	1:c0c5ac8eac80	1732	#define LCD_WF_WF63_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1733	#define LCD_WF_WF63_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1734	#define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
pradeepvk2208	1:c0c5ac8eac80	1735	#define LCD_WF_WF59_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1736	#define LCD_WF_WF59_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1737	#define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
pradeepvk2208	1:c0c5ac8eac80	1738	#define LCD_WF_WF55_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1739	#define LCD_WF_WF55_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1740	#define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
pradeepvk2208	1:c0c5ac8eac80	1741	#define LCD_WF_WF3_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1742	#define LCD_WF_WF3_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1743	#define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
pradeepvk2208	1:c0c5ac8eac80	1744	#define LCD_WF_WF51_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1745	#define LCD_WF_WF51_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1746	#define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
pradeepvk2208	1:c0c5ac8eac80	1747	#define LCD_WF_WF47_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1748	#define LCD_WF_WF47_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1749	#define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
pradeepvk2208	1:c0c5ac8eac80	1750	#define LCD_WF_WF43_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1751	#define LCD_WF_WF43_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1752	#define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
pradeepvk2208	1:c0c5ac8eac80	1753	#define LCD_WF_WF7_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1754	#define LCD_WF_WF7_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1755	#define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
pradeepvk2208	1:c0c5ac8eac80	1756	#define LCD_WF_WF39_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1757	#define LCD_WF_WF39_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1758	#define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
pradeepvk2208	1:c0c5ac8eac80	1759	#define LCD_WF_WF35_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1760	#define LCD_WF_WF35_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1761	#define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
pradeepvk2208	1:c0c5ac8eac80	1762	#define LCD_WF_WF31_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1763	#define LCD_WF_WF31_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1764	#define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
pradeepvk2208	1:c0c5ac8eac80	1765	#define LCD_WF_WF11_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1766	#define LCD_WF_WF11_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1767	#define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
pradeepvk2208	1:c0c5ac8eac80	1768	#define LCD_WF_WF27_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1769	#define LCD_WF_WF27_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1770	#define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
pradeepvk2208	1:c0c5ac8eac80	1771	#define LCD_WF_WF23_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1772	#define LCD_WF_WF23_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1773	#define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
pradeepvk2208	1:c0c5ac8eac80	1774	#define LCD_WF_WF19_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1775	#define LCD_WF_WF19_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1776	#define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
pradeepvk2208	1:c0c5ac8eac80	1777	#define LCD_WF_WF15_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	1778	#define LCD_WF_WF15_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	1779	#define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
pradeepvk2208	1:c0c5ac8eac80	1780	/* WF8B Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	1781	#define LCD_WF8B_BPALCD0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1782	#define LCD_WF8B_BPALCD0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1783	#define LCD_WF8B_BPALCD63_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1784	#define LCD_WF8B_BPALCD63_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1785	#define LCD_WF8B_BPALCD62_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1786	#define LCD_WF8B_BPALCD62_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1787	#define LCD_WF8B_BPALCD61_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1788	#define LCD_WF8B_BPALCD61_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1789	#define LCD_WF8B_BPALCD60_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1790	#define LCD_WF8B_BPALCD60_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1791	#define LCD_WF8B_BPALCD59_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1792	#define LCD_WF8B_BPALCD59_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1793	#define LCD_WF8B_BPALCD58_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1794	#define LCD_WF8B_BPALCD58_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1795	#define LCD_WF8B_BPALCD57_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1796	#define LCD_WF8B_BPALCD57_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1797	#define LCD_WF8B_BPALCD1_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1798	#define LCD_WF8B_BPALCD1_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1799	#define LCD_WF8B_BPALCD56_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1800	#define LCD_WF8B_BPALCD56_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1801	#define LCD_WF8B_BPALCD55_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1802	#define LCD_WF8B_BPALCD55_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1803	#define LCD_WF8B_BPALCD54_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1804	#define LCD_WF8B_BPALCD54_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1805	#define LCD_WF8B_BPALCD53_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1806	#define LCD_WF8B_BPALCD53_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1807	#define LCD_WF8B_BPALCD52_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1808	#define LCD_WF8B_BPALCD52_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1809	#define LCD_WF8B_BPALCD51_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1810	#define LCD_WF8B_BPALCD51_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1811	#define LCD_WF8B_BPALCD50_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1812	#define LCD_WF8B_BPALCD50_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1813	#define LCD_WF8B_BPALCD2_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1814	#define LCD_WF8B_BPALCD2_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1815	#define LCD_WF8B_BPALCD49_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1816	#define LCD_WF8B_BPALCD49_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1817	#define LCD_WF8B_BPALCD48_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1818	#define LCD_WF8B_BPALCD48_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1819	#define LCD_WF8B_BPALCD47_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1820	#define LCD_WF8B_BPALCD47_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1821	#define LCD_WF8B_BPALCD46_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1822	#define LCD_WF8B_BPALCD46_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1823	#define LCD_WF8B_BPALCD45_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1824	#define LCD_WF8B_BPALCD45_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1825	#define LCD_WF8B_BPALCD44_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1826	#define LCD_WF8B_BPALCD44_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1827	#define LCD_WF8B_BPALCD43_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1828	#define LCD_WF8B_BPALCD43_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1829	#define LCD_WF8B_BPALCD3_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1830	#define LCD_WF8B_BPALCD3_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1831	#define LCD_WF8B_BPALCD42_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1832	#define LCD_WF8B_BPALCD42_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1833	#define LCD_WF8B_BPALCD41_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1834	#define LCD_WF8B_BPALCD41_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1835	#define LCD_WF8B_BPALCD40_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1836	#define LCD_WF8B_BPALCD40_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1837	#define LCD_WF8B_BPALCD39_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1838	#define LCD_WF8B_BPALCD39_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1839	#define LCD_WF8B_BPALCD38_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1840	#define LCD_WF8B_BPALCD38_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1841	#define LCD_WF8B_BPALCD37_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1842	#define LCD_WF8B_BPALCD37_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1843	#define LCD_WF8B_BPALCD36_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1844	#define LCD_WF8B_BPALCD36_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1845	#define LCD_WF8B_BPALCD4_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1846	#define LCD_WF8B_BPALCD4_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1847	#define LCD_WF8B_BPALCD35_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1848	#define LCD_WF8B_BPALCD35_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1849	#define LCD_WF8B_BPALCD34_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1850	#define LCD_WF8B_BPALCD34_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1851	#define LCD_WF8B_BPALCD33_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1852	#define LCD_WF8B_BPALCD33_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1853	#define LCD_WF8B_BPALCD32_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1854	#define LCD_WF8B_BPALCD32_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1855	#define LCD_WF8B_BPALCD31_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1856	#define LCD_WF8B_BPALCD31_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1857	#define LCD_WF8B_BPALCD30_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1858	#define LCD_WF8B_BPALCD30_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1859	#define LCD_WF8B_BPALCD29_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1860	#define LCD_WF8B_BPALCD29_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1861	#define LCD_WF8B_BPALCD5_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1862	#define LCD_WF8B_BPALCD5_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1863	#define LCD_WF8B_BPALCD28_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1864	#define LCD_WF8B_BPALCD28_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1865	#define LCD_WF8B_BPALCD27_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1866	#define LCD_WF8B_BPALCD27_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1867	#define LCD_WF8B_BPALCD26_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1868	#define LCD_WF8B_BPALCD26_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1869	#define LCD_WF8B_BPALCD25_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1870	#define LCD_WF8B_BPALCD25_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1871	#define LCD_WF8B_BPALCD24_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1872	#define LCD_WF8B_BPALCD24_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1873	#define LCD_WF8B_BPALCD23_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1874	#define LCD_WF8B_BPALCD23_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1875	#define LCD_WF8B_BPALCD22_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1876	#define LCD_WF8B_BPALCD22_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1877	#define LCD_WF8B_BPALCD6_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1878	#define LCD_WF8B_BPALCD6_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1879	#define LCD_WF8B_BPALCD21_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1880	#define LCD_WF8B_BPALCD21_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1881	#define LCD_WF8B_BPALCD20_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1882	#define LCD_WF8B_BPALCD20_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1883	#define LCD_WF8B_BPALCD19_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1884	#define LCD_WF8B_BPALCD19_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1885	#define LCD_WF8B_BPALCD18_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1886	#define LCD_WF8B_BPALCD18_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1887	#define LCD_WF8B_BPALCD17_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1888	#define LCD_WF8B_BPALCD17_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1889	#define LCD_WF8B_BPALCD16_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1890	#define LCD_WF8B_BPALCD16_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1891	#define LCD_WF8B_BPALCD15_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1892	#define LCD_WF8B_BPALCD15_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1893	#define LCD_WF8B_BPALCD7_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1894	#define LCD_WF8B_BPALCD7_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1895	#define LCD_WF8B_BPALCD14_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1896	#define LCD_WF8B_BPALCD14_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1897	#define LCD_WF8B_BPALCD13_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1898	#define LCD_WF8B_BPALCD13_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1899	#define LCD_WF8B_BPALCD12_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1900	#define LCD_WF8B_BPALCD12_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1901	#define LCD_WF8B_BPALCD11_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1902	#define LCD_WF8B_BPALCD11_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1903	#define LCD_WF8B_BPALCD10_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1904	#define LCD_WF8B_BPALCD10_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1905	#define LCD_WF8B_BPALCD9_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1906	#define LCD_WF8B_BPALCD9_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1907	#define LCD_WF8B_BPALCD8_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	1908	#define LCD_WF8B_BPALCD8_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	1909	#define LCD_WF8B_BPBLCD1_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1910	#define LCD_WF8B_BPBLCD1_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1911	#define LCD_WF8B_BPBLCD32_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1912	#define LCD_WF8B_BPBLCD32_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1913	#define LCD_WF8B_BPBLCD30_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1914	#define LCD_WF8B_BPBLCD30_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1915	#define LCD_WF8B_BPBLCD60_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1916	#define LCD_WF8B_BPBLCD60_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1917	#define LCD_WF8B_BPBLCD24_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1918	#define LCD_WF8B_BPBLCD24_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1919	#define LCD_WF8B_BPBLCD28_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1920	#define LCD_WF8B_BPBLCD28_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1921	#define LCD_WF8B_BPBLCD23_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1922	#define LCD_WF8B_BPBLCD23_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1923	#define LCD_WF8B_BPBLCD48_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1924	#define LCD_WF8B_BPBLCD48_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1925	#define LCD_WF8B_BPBLCD10_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1926	#define LCD_WF8B_BPBLCD10_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1927	#define LCD_WF8B_BPBLCD15_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1928	#define LCD_WF8B_BPBLCD15_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1929	#define LCD_WF8B_BPBLCD36_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1930	#define LCD_WF8B_BPBLCD36_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1931	#define LCD_WF8B_BPBLCD44_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1932	#define LCD_WF8B_BPBLCD44_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1933	#define LCD_WF8B_BPBLCD62_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1934	#define LCD_WF8B_BPBLCD62_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1935	#define LCD_WF8B_BPBLCD53_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1936	#define LCD_WF8B_BPBLCD53_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1937	#define LCD_WF8B_BPBLCD22_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1938	#define LCD_WF8B_BPBLCD22_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1939	#define LCD_WF8B_BPBLCD47_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1940	#define LCD_WF8B_BPBLCD47_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1941	#define LCD_WF8B_BPBLCD33_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1942	#define LCD_WF8B_BPBLCD33_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1943	#define LCD_WF8B_BPBLCD2_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1944	#define LCD_WF8B_BPBLCD2_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1945	#define LCD_WF8B_BPBLCD49_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1946	#define LCD_WF8B_BPBLCD49_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1947	#define LCD_WF8B_BPBLCD0_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1948	#define LCD_WF8B_BPBLCD0_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1949	#define LCD_WF8B_BPBLCD55_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1950	#define LCD_WF8B_BPBLCD55_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1951	#define LCD_WF8B_BPBLCD56_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1952	#define LCD_WF8B_BPBLCD56_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1953	#define LCD_WF8B_BPBLCD21_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1954	#define LCD_WF8B_BPBLCD21_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1955	#define LCD_WF8B_BPBLCD6_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1956	#define LCD_WF8B_BPBLCD6_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1957	#define LCD_WF8B_BPBLCD29_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1958	#define LCD_WF8B_BPBLCD29_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1959	#define LCD_WF8B_BPBLCD25_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1960	#define LCD_WF8B_BPBLCD25_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1961	#define LCD_WF8B_BPBLCD8_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1962	#define LCD_WF8B_BPBLCD8_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1963	#define LCD_WF8B_BPBLCD54_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1964	#define LCD_WF8B_BPBLCD54_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1965	#define LCD_WF8B_BPBLCD38_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1966	#define LCD_WF8B_BPBLCD38_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1967	#define LCD_WF8B_BPBLCD43_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1968	#define LCD_WF8B_BPBLCD43_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1969	#define LCD_WF8B_BPBLCD20_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1970	#define LCD_WF8B_BPBLCD20_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1971	#define LCD_WF8B_BPBLCD9_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1972	#define LCD_WF8B_BPBLCD9_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1973	#define LCD_WF8B_BPBLCD7_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1974	#define LCD_WF8B_BPBLCD7_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1975	#define LCD_WF8B_BPBLCD50_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1976	#define LCD_WF8B_BPBLCD50_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1977	#define LCD_WF8B_BPBLCD40_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1978	#define LCD_WF8B_BPBLCD40_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1979	#define LCD_WF8B_BPBLCD63_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1980	#define LCD_WF8B_BPBLCD63_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1981	#define LCD_WF8B_BPBLCD26_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1982	#define LCD_WF8B_BPBLCD26_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1983	#define LCD_WF8B_BPBLCD12_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1984	#define LCD_WF8B_BPBLCD12_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1985	#define LCD_WF8B_BPBLCD19_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1986	#define LCD_WF8B_BPBLCD19_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1987	#define LCD_WF8B_BPBLCD34_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1988	#define LCD_WF8B_BPBLCD34_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1989	#define LCD_WF8B_BPBLCD39_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1990	#define LCD_WF8B_BPBLCD39_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1991	#define LCD_WF8B_BPBLCD59_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1992	#define LCD_WF8B_BPBLCD59_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1993	#define LCD_WF8B_BPBLCD61_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1994	#define LCD_WF8B_BPBLCD61_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1995	#define LCD_WF8B_BPBLCD37_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1996	#define LCD_WF8B_BPBLCD37_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1997	#define LCD_WF8B_BPBLCD31_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	1998	#define LCD_WF8B_BPBLCD31_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	1999	#define LCD_WF8B_BPBLCD58_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2000	#define LCD_WF8B_BPBLCD58_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2001	#define LCD_WF8B_BPBLCD18_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2002	#define LCD_WF8B_BPBLCD18_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2003	#define LCD_WF8B_BPBLCD45_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2004	#define LCD_WF8B_BPBLCD45_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2005	#define LCD_WF8B_BPBLCD27_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2006	#define LCD_WF8B_BPBLCD27_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2007	#define LCD_WF8B_BPBLCD14_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2008	#define LCD_WF8B_BPBLCD14_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2009	#define LCD_WF8B_BPBLCD51_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2010	#define LCD_WF8B_BPBLCD51_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2011	#define LCD_WF8B_BPBLCD52_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2012	#define LCD_WF8B_BPBLCD52_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2013	#define LCD_WF8B_BPBLCD4_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2014	#define LCD_WF8B_BPBLCD4_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2015	#define LCD_WF8B_BPBLCD35_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2016	#define LCD_WF8B_BPBLCD35_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2017	#define LCD_WF8B_BPBLCD17_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2018	#define LCD_WF8B_BPBLCD17_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2019	#define LCD_WF8B_BPBLCD41_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2020	#define LCD_WF8B_BPBLCD41_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2021	#define LCD_WF8B_BPBLCD11_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2022	#define LCD_WF8B_BPBLCD11_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2023	#define LCD_WF8B_BPBLCD46_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2024	#define LCD_WF8B_BPBLCD46_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2025	#define LCD_WF8B_BPBLCD57_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2026	#define LCD_WF8B_BPBLCD57_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2027	#define LCD_WF8B_BPBLCD42_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2028	#define LCD_WF8B_BPBLCD42_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2029	#define LCD_WF8B_BPBLCD5_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2030	#define LCD_WF8B_BPBLCD5_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2031	#define LCD_WF8B_BPBLCD3_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2032	#define LCD_WF8B_BPBLCD3_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2033	#define LCD_WF8B_BPBLCD16_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2034	#define LCD_WF8B_BPBLCD16_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2035	#define LCD_WF8B_BPBLCD13_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2036	#define LCD_WF8B_BPBLCD13_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2037	#define LCD_WF8B_BPCLCD10_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2038	#define LCD_WF8B_BPCLCD10_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2039	#define LCD_WF8B_BPCLCD55_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2040	#define LCD_WF8B_BPCLCD55_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2041	#define LCD_WF8B_BPCLCD2_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2042	#define LCD_WF8B_BPCLCD2_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2043	#define LCD_WF8B_BPCLCD23_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2044	#define LCD_WF8B_BPCLCD23_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2045	#define LCD_WF8B_BPCLCD48_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2046	#define LCD_WF8B_BPCLCD48_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2047	#define LCD_WF8B_BPCLCD24_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2048	#define LCD_WF8B_BPCLCD24_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2049	#define LCD_WF8B_BPCLCD60_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2050	#define LCD_WF8B_BPCLCD60_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2051	#define LCD_WF8B_BPCLCD47_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2052	#define LCD_WF8B_BPCLCD47_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2053	#define LCD_WF8B_BPCLCD22_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2054	#define LCD_WF8B_BPCLCD22_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2055	#define LCD_WF8B_BPCLCD8_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2056	#define LCD_WF8B_BPCLCD8_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2057	#define LCD_WF8B_BPCLCD21_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2058	#define LCD_WF8B_BPCLCD21_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2059	#define LCD_WF8B_BPCLCD49_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2060	#define LCD_WF8B_BPCLCD49_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2061	#define LCD_WF8B_BPCLCD25_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2062	#define LCD_WF8B_BPCLCD25_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2063	#define LCD_WF8B_BPCLCD1_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2064	#define LCD_WF8B_BPCLCD1_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2065	#define LCD_WF8B_BPCLCD20_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2066	#define LCD_WF8B_BPCLCD20_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2067	#define LCD_WF8B_BPCLCD50_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2068	#define LCD_WF8B_BPCLCD50_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2069	#define LCD_WF8B_BPCLCD19_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2070	#define LCD_WF8B_BPCLCD19_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2071	#define LCD_WF8B_BPCLCD26_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2072	#define LCD_WF8B_BPCLCD26_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2073	#define LCD_WF8B_BPCLCD59_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2074	#define LCD_WF8B_BPCLCD59_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2075	#define LCD_WF8B_BPCLCD61_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2076	#define LCD_WF8B_BPCLCD61_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2077	#define LCD_WF8B_BPCLCD46_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2078	#define LCD_WF8B_BPCLCD46_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2079	#define LCD_WF8B_BPCLCD18_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2080	#define LCD_WF8B_BPCLCD18_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2081	#define LCD_WF8B_BPCLCD5_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2082	#define LCD_WF8B_BPCLCD5_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2083	#define LCD_WF8B_BPCLCD63_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2084	#define LCD_WF8B_BPCLCD63_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2085	#define LCD_WF8B_BPCLCD27_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2086	#define LCD_WF8B_BPCLCD27_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2087	#define LCD_WF8B_BPCLCD17_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2088	#define LCD_WF8B_BPCLCD17_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2089	#define LCD_WF8B_BPCLCD51_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2090	#define LCD_WF8B_BPCLCD51_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2091	#define LCD_WF8B_BPCLCD9_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2092	#define LCD_WF8B_BPCLCD9_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2093	#define LCD_WF8B_BPCLCD54_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2094	#define LCD_WF8B_BPCLCD54_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2095	#define LCD_WF8B_BPCLCD15_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2096	#define LCD_WF8B_BPCLCD15_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2097	#define LCD_WF8B_BPCLCD16_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2098	#define LCD_WF8B_BPCLCD16_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2099	#define LCD_WF8B_BPCLCD14_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2100	#define LCD_WF8B_BPCLCD14_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2101	#define LCD_WF8B_BPCLCD32_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2102	#define LCD_WF8B_BPCLCD32_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2103	#define LCD_WF8B_BPCLCD28_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2104	#define LCD_WF8B_BPCLCD28_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2105	#define LCD_WF8B_BPCLCD53_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2106	#define LCD_WF8B_BPCLCD53_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2107	#define LCD_WF8B_BPCLCD33_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2108	#define LCD_WF8B_BPCLCD33_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2109	#define LCD_WF8B_BPCLCD0_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2110	#define LCD_WF8B_BPCLCD0_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2111	#define LCD_WF8B_BPCLCD43_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2112	#define LCD_WF8B_BPCLCD43_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2113	#define LCD_WF8B_BPCLCD7_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2114	#define LCD_WF8B_BPCLCD7_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2115	#define LCD_WF8B_BPCLCD4_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2116	#define LCD_WF8B_BPCLCD4_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2117	#define LCD_WF8B_BPCLCD34_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2118	#define LCD_WF8B_BPCLCD34_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2119	#define LCD_WF8B_BPCLCD29_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2120	#define LCD_WF8B_BPCLCD29_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2121	#define LCD_WF8B_BPCLCD45_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2122	#define LCD_WF8B_BPCLCD45_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2123	#define LCD_WF8B_BPCLCD57_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2124	#define LCD_WF8B_BPCLCD57_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2125	#define LCD_WF8B_BPCLCD42_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2126	#define LCD_WF8B_BPCLCD42_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2127	#define LCD_WF8B_BPCLCD35_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2128	#define LCD_WF8B_BPCLCD35_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2129	#define LCD_WF8B_BPCLCD13_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2130	#define LCD_WF8B_BPCLCD13_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2131	#define LCD_WF8B_BPCLCD36_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2132	#define LCD_WF8B_BPCLCD36_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2133	#define LCD_WF8B_BPCLCD30_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2134	#define LCD_WF8B_BPCLCD30_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2135	#define LCD_WF8B_BPCLCD52_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2136	#define LCD_WF8B_BPCLCD52_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2137	#define LCD_WF8B_BPCLCD58_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2138	#define LCD_WF8B_BPCLCD58_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2139	#define LCD_WF8B_BPCLCD41_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2140	#define LCD_WF8B_BPCLCD41_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2141	#define LCD_WF8B_BPCLCD37_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2142	#define LCD_WF8B_BPCLCD37_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2143	#define LCD_WF8B_BPCLCD3_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2144	#define LCD_WF8B_BPCLCD3_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2145	#define LCD_WF8B_BPCLCD12_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2146	#define LCD_WF8B_BPCLCD12_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2147	#define LCD_WF8B_BPCLCD11_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2148	#define LCD_WF8B_BPCLCD11_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2149	#define LCD_WF8B_BPCLCD38_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2150	#define LCD_WF8B_BPCLCD38_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2151	#define LCD_WF8B_BPCLCD44_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2152	#define LCD_WF8B_BPCLCD44_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2153	#define LCD_WF8B_BPCLCD31_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2154	#define LCD_WF8B_BPCLCD31_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2155	#define LCD_WF8B_BPCLCD40_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2156	#define LCD_WF8B_BPCLCD40_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2157	#define LCD_WF8B_BPCLCD62_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2158	#define LCD_WF8B_BPCLCD62_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2159	#define LCD_WF8B_BPCLCD56_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2160	#define LCD_WF8B_BPCLCD56_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2161	#define LCD_WF8B_BPCLCD39_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2162	#define LCD_WF8B_BPCLCD39_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2163	#define LCD_WF8B_BPCLCD6_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2164	#define LCD_WF8B_BPCLCD6_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2165	#define LCD_WF8B_BPDLCD47_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2166	#define LCD_WF8B_BPDLCD47_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2167	#define LCD_WF8B_BPDLCD23_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2168	#define LCD_WF8B_BPDLCD23_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2169	#define LCD_WF8B_BPDLCD48_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2170	#define LCD_WF8B_BPDLCD48_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2171	#define LCD_WF8B_BPDLCD24_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2172	#define LCD_WF8B_BPDLCD24_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2173	#define LCD_WF8B_BPDLCD15_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2174	#define LCD_WF8B_BPDLCD15_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2175	#define LCD_WF8B_BPDLCD22_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2176	#define LCD_WF8B_BPDLCD22_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2177	#define LCD_WF8B_BPDLCD60_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2178	#define LCD_WF8B_BPDLCD60_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2179	#define LCD_WF8B_BPDLCD10_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2180	#define LCD_WF8B_BPDLCD10_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2181	#define LCD_WF8B_BPDLCD21_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2182	#define LCD_WF8B_BPDLCD21_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2183	#define LCD_WF8B_BPDLCD49_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2184	#define LCD_WF8B_BPDLCD49_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2185	#define LCD_WF8B_BPDLCD1_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2186	#define LCD_WF8B_BPDLCD1_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2187	#define LCD_WF8B_BPDLCD25_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2188	#define LCD_WF8B_BPDLCD25_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2189	#define LCD_WF8B_BPDLCD20_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2190	#define LCD_WF8B_BPDLCD20_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2191	#define LCD_WF8B_BPDLCD2_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2192	#define LCD_WF8B_BPDLCD2_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2193	#define LCD_WF8B_BPDLCD55_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2194	#define LCD_WF8B_BPDLCD55_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2195	#define LCD_WF8B_BPDLCD59_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2196	#define LCD_WF8B_BPDLCD59_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2197	#define LCD_WF8B_BPDLCD5_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2198	#define LCD_WF8B_BPDLCD5_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2199	#define LCD_WF8B_BPDLCD19_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2200	#define LCD_WF8B_BPDLCD19_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2201	#define LCD_WF8B_BPDLCD6_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2202	#define LCD_WF8B_BPDLCD6_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2203	#define LCD_WF8B_BPDLCD26_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2204	#define LCD_WF8B_BPDLCD26_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2205	#define LCD_WF8B_BPDLCD0_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2206	#define LCD_WF8B_BPDLCD0_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2207	#define LCD_WF8B_BPDLCD50_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2208	#define LCD_WF8B_BPDLCD50_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2209	#define LCD_WF8B_BPDLCD46_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2210	#define LCD_WF8B_BPDLCD46_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2211	#define LCD_WF8B_BPDLCD18_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2212	#define LCD_WF8B_BPDLCD18_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2213	#define LCD_WF8B_BPDLCD61_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2214	#define LCD_WF8B_BPDLCD61_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2215	#define LCD_WF8B_BPDLCD9_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2216	#define LCD_WF8B_BPDLCD9_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2217	#define LCD_WF8B_BPDLCD17_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2218	#define LCD_WF8B_BPDLCD17_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2219	#define LCD_WF8B_BPDLCD27_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2220	#define LCD_WF8B_BPDLCD27_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2221	#define LCD_WF8B_BPDLCD53_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2222	#define LCD_WF8B_BPDLCD53_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2223	#define LCD_WF8B_BPDLCD51_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2224	#define LCD_WF8B_BPDLCD51_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2225	#define LCD_WF8B_BPDLCD54_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2226	#define LCD_WF8B_BPDLCD54_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2227	#define LCD_WF8B_BPDLCD13_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2228	#define LCD_WF8B_BPDLCD13_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2229	#define LCD_WF8B_BPDLCD16_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2230	#define LCD_WF8B_BPDLCD16_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2231	#define LCD_WF8B_BPDLCD32_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2232	#define LCD_WF8B_BPDLCD32_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2233	#define LCD_WF8B_BPDLCD14_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2234	#define LCD_WF8B_BPDLCD14_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2235	#define LCD_WF8B_BPDLCD28_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2236	#define LCD_WF8B_BPDLCD28_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2237	#define LCD_WF8B_BPDLCD43_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2238	#define LCD_WF8B_BPDLCD43_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2239	#define LCD_WF8B_BPDLCD4_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2240	#define LCD_WF8B_BPDLCD4_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2241	#define LCD_WF8B_BPDLCD45_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2242	#define LCD_WF8B_BPDLCD45_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2243	#define LCD_WF8B_BPDLCD8_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2244	#define LCD_WF8B_BPDLCD8_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2245	#define LCD_WF8B_BPDLCD62_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2246	#define LCD_WF8B_BPDLCD62_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2247	#define LCD_WF8B_BPDLCD33_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2248	#define LCD_WF8B_BPDLCD33_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2249	#define LCD_WF8B_BPDLCD34_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2250	#define LCD_WF8B_BPDLCD34_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2251	#define LCD_WF8B_BPDLCD29_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2252	#define LCD_WF8B_BPDLCD29_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2253	#define LCD_WF8B_BPDLCD58_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2254	#define LCD_WF8B_BPDLCD58_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2255	#define LCD_WF8B_BPDLCD57_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2256	#define LCD_WF8B_BPDLCD57_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2257	#define LCD_WF8B_BPDLCD42_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2258	#define LCD_WF8B_BPDLCD42_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2259	#define LCD_WF8B_BPDLCD35_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2260	#define LCD_WF8B_BPDLCD35_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2261	#define LCD_WF8B_BPDLCD52_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2262	#define LCD_WF8B_BPDLCD52_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2263	#define LCD_WF8B_BPDLCD7_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2264	#define LCD_WF8B_BPDLCD7_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2265	#define LCD_WF8B_BPDLCD36_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2266	#define LCD_WF8B_BPDLCD36_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2267	#define LCD_WF8B_BPDLCD30_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2268	#define LCD_WF8B_BPDLCD30_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2269	#define LCD_WF8B_BPDLCD41_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2270	#define LCD_WF8B_BPDLCD41_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2271	#define LCD_WF8B_BPDLCD37_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2272	#define LCD_WF8B_BPDLCD37_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2273	#define LCD_WF8B_BPDLCD44_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2274	#define LCD_WF8B_BPDLCD44_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2275	#define LCD_WF8B_BPDLCD63_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2276	#define LCD_WF8B_BPDLCD63_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2277	#define LCD_WF8B_BPDLCD38_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2278	#define LCD_WF8B_BPDLCD38_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2279	#define LCD_WF8B_BPDLCD56_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2280	#define LCD_WF8B_BPDLCD56_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2281	#define LCD_WF8B_BPDLCD40_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2282	#define LCD_WF8B_BPDLCD40_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2283	#define LCD_WF8B_BPDLCD31_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2284	#define LCD_WF8B_BPDLCD31_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2285	#define LCD_WF8B_BPDLCD12_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2286	#define LCD_WF8B_BPDLCD12_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2287	#define LCD_WF8B_BPDLCD39_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2288	#define LCD_WF8B_BPDLCD39_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2289	#define LCD_WF8B_BPDLCD3_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2290	#define LCD_WF8B_BPDLCD3_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2291	#define LCD_WF8B_BPDLCD11_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2292	#define LCD_WF8B_BPDLCD11_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2293	#define LCD_WF8B_BPELCD12_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2294	#define LCD_WF8B_BPELCD12_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2295	#define LCD_WF8B_BPELCD39_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2296	#define LCD_WF8B_BPELCD39_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2297	#define LCD_WF8B_BPELCD3_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2298	#define LCD_WF8B_BPELCD3_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2299	#define LCD_WF8B_BPELCD38_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2300	#define LCD_WF8B_BPELCD38_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2301	#define LCD_WF8B_BPELCD40_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2302	#define LCD_WF8B_BPELCD40_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2303	#define LCD_WF8B_BPELCD37_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2304	#define LCD_WF8B_BPELCD37_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2305	#define LCD_WF8B_BPELCD41_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2306	#define LCD_WF8B_BPELCD41_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2307	#define LCD_WF8B_BPELCD36_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2308	#define LCD_WF8B_BPELCD36_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2309	#define LCD_WF8B_BPELCD8_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2310	#define LCD_WF8B_BPELCD8_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2311	#define LCD_WF8B_BPELCD35_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2312	#define LCD_WF8B_BPELCD35_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2313	#define LCD_WF8B_BPELCD42_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2314	#define LCD_WF8B_BPELCD42_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2315	#define LCD_WF8B_BPELCD34_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2316	#define LCD_WF8B_BPELCD34_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2317	#define LCD_WF8B_BPELCD33_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2318	#define LCD_WF8B_BPELCD33_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2319	#define LCD_WF8B_BPELCD11_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2320	#define LCD_WF8B_BPELCD11_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2321	#define LCD_WF8B_BPELCD43_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2322	#define LCD_WF8B_BPELCD43_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2323	#define LCD_WF8B_BPELCD32_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2324	#define LCD_WF8B_BPELCD32_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2325	#define LCD_WF8B_BPELCD31_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2326	#define LCD_WF8B_BPELCD31_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2327	#define LCD_WF8B_BPELCD44_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2328	#define LCD_WF8B_BPELCD44_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2329	#define LCD_WF8B_BPELCD30_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2330	#define LCD_WF8B_BPELCD30_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2331	#define LCD_WF8B_BPELCD29_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2332	#define LCD_WF8B_BPELCD29_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2333	#define LCD_WF8B_BPELCD7_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2334	#define LCD_WF8B_BPELCD7_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2335	#define LCD_WF8B_BPELCD45_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2336	#define LCD_WF8B_BPELCD45_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2337	#define LCD_WF8B_BPELCD28_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2338	#define LCD_WF8B_BPELCD28_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2339	#define LCD_WF8B_BPELCD2_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2340	#define LCD_WF8B_BPELCD2_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2341	#define LCD_WF8B_BPELCD27_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2342	#define LCD_WF8B_BPELCD27_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2343	#define LCD_WF8B_BPELCD46_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2344	#define LCD_WF8B_BPELCD46_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2345	#define LCD_WF8B_BPELCD26_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2346	#define LCD_WF8B_BPELCD26_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2347	#define LCD_WF8B_BPELCD10_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2348	#define LCD_WF8B_BPELCD10_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2349	#define LCD_WF8B_BPELCD13_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2350	#define LCD_WF8B_BPELCD13_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2351	#define LCD_WF8B_BPELCD25_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2352	#define LCD_WF8B_BPELCD25_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2353	#define LCD_WF8B_BPELCD5_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2354	#define LCD_WF8B_BPELCD5_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2355	#define LCD_WF8B_BPELCD24_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2356	#define LCD_WF8B_BPELCD24_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2357	#define LCD_WF8B_BPELCD47_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2358	#define LCD_WF8B_BPELCD47_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2359	#define LCD_WF8B_BPELCD23_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2360	#define LCD_WF8B_BPELCD23_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2361	#define LCD_WF8B_BPELCD22_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2362	#define LCD_WF8B_BPELCD22_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2363	#define LCD_WF8B_BPELCD48_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2364	#define LCD_WF8B_BPELCD48_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2365	#define LCD_WF8B_BPELCD21_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2366	#define LCD_WF8B_BPELCD21_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2367	#define LCD_WF8B_BPELCD49_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2368	#define LCD_WF8B_BPELCD49_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2369	#define LCD_WF8B_BPELCD20_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2370	#define LCD_WF8B_BPELCD20_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2371	#define LCD_WF8B_BPELCD19_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2372	#define LCD_WF8B_BPELCD19_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2373	#define LCD_WF8B_BPELCD9_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2374	#define LCD_WF8B_BPELCD9_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2375	#define LCD_WF8B_BPELCD50_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2376	#define LCD_WF8B_BPELCD50_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2377	#define LCD_WF8B_BPELCD18_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2378	#define LCD_WF8B_BPELCD18_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2379	#define LCD_WF8B_BPELCD6_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2380	#define LCD_WF8B_BPELCD6_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2381	#define LCD_WF8B_BPELCD17_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2382	#define LCD_WF8B_BPELCD17_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2383	#define LCD_WF8B_BPELCD51_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2384	#define LCD_WF8B_BPELCD51_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2385	#define LCD_WF8B_BPELCD16_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2386	#define LCD_WF8B_BPELCD16_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2387	#define LCD_WF8B_BPELCD56_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2388	#define LCD_WF8B_BPELCD56_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2389	#define LCD_WF8B_BPELCD57_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2390	#define LCD_WF8B_BPELCD57_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2391	#define LCD_WF8B_BPELCD52_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2392	#define LCD_WF8B_BPELCD52_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2393	#define LCD_WF8B_BPELCD1_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2394	#define LCD_WF8B_BPELCD1_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2395	#define LCD_WF8B_BPELCD58_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2396	#define LCD_WF8B_BPELCD58_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2397	#define LCD_WF8B_BPELCD59_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2398	#define LCD_WF8B_BPELCD59_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2399	#define LCD_WF8B_BPELCD53_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2400	#define LCD_WF8B_BPELCD53_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2401	#define LCD_WF8B_BPELCD14_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2402	#define LCD_WF8B_BPELCD14_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2403	#define LCD_WF8B_BPELCD0_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2404	#define LCD_WF8B_BPELCD0_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2405	#define LCD_WF8B_BPELCD60_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2406	#define LCD_WF8B_BPELCD60_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2407	#define LCD_WF8B_BPELCD15_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2408	#define LCD_WF8B_BPELCD15_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2409	#define LCD_WF8B_BPELCD61_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2410	#define LCD_WF8B_BPELCD61_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2411	#define LCD_WF8B_BPELCD54_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2412	#define LCD_WF8B_BPELCD54_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2413	#define LCD_WF8B_BPELCD62_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2414	#define LCD_WF8B_BPELCD62_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2415	#define LCD_WF8B_BPELCD63_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2416	#define LCD_WF8B_BPELCD63_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2417	#define LCD_WF8B_BPELCD55_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2418	#define LCD_WF8B_BPELCD55_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2419	#define LCD_WF8B_BPELCD4_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2420	#define LCD_WF8B_BPELCD4_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2421	#define LCD_WF8B_BPFLCD13_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2422	#define LCD_WF8B_BPFLCD13_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2423	#define LCD_WF8B_BPFLCD39_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2424	#define LCD_WF8B_BPFLCD39_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2425	#define LCD_WF8B_BPFLCD55_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2426	#define LCD_WF8B_BPFLCD55_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2427	#define LCD_WF8B_BPFLCD47_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2428	#define LCD_WF8B_BPFLCD47_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2429	#define LCD_WF8B_BPFLCD63_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2430	#define LCD_WF8B_BPFLCD63_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2431	#define LCD_WF8B_BPFLCD43_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2432	#define LCD_WF8B_BPFLCD43_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2433	#define LCD_WF8B_BPFLCD5_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2434	#define LCD_WF8B_BPFLCD5_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2435	#define LCD_WF8B_BPFLCD62_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2436	#define LCD_WF8B_BPFLCD62_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2437	#define LCD_WF8B_BPFLCD14_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2438	#define LCD_WF8B_BPFLCD14_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2439	#define LCD_WF8B_BPFLCD24_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2440	#define LCD_WF8B_BPFLCD24_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2441	#define LCD_WF8B_BPFLCD54_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2442	#define LCD_WF8B_BPFLCD54_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2443	#define LCD_WF8B_BPFLCD15_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2444	#define LCD_WF8B_BPFLCD15_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2445	#define LCD_WF8B_BPFLCD32_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2446	#define LCD_WF8B_BPFLCD32_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2447	#define LCD_WF8B_BPFLCD61_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2448	#define LCD_WF8B_BPFLCD61_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2449	#define LCD_WF8B_BPFLCD25_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2450	#define LCD_WF8B_BPFLCD25_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2451	#define LCD_WF8B_BPFLCD60_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2452	#define LCD_WF8B_BPFLCD60_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2453	#define LCD_WF8B_BPFLCD41_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2454	#define LCD_WF8B_BPFLCD41_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2455	#define LCD_WF8B_BPFLCD33_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2456	#define LCD_WF8B_BPFLCD33_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2457	#define LCD_WF8B_BPFLCD53_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2458	#define LCD_WF8B_BPFLCD53_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2459	#define LCD_WF8B_BPFLCD59_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2460	#define LCD_WF8B_BPFLCD59_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2461	#define LCD_WF8B_BPFLCD0_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2462	#define LCD_WF8B_BPFLCD0_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2463	#define LCD_WF8B_BPFLCD46_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2464	#define LCD_WF8B_BPFLCD46_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2465	#define LCD_WF8B_BPFLCD58_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2466	#define LCD_WF8B_BPFLCD58_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2467	#define LCD_WF8B_BPFLCD26_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2468	#define LCD_WF8B_BPFLCD26_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2469	#define LCD_WF8B_BPFLCD36_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2470	#define LCD_WF8B_BPFLCD36_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2471	#define LCD_WF8B_BPFLCD10_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2472	#define LCD_WF8B_BPFLCD10_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2473	#define LCD_WF8B_BPFLCD52_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2474	#define LCD_WF8B_BPFLCD52_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2475	#define LCD_WF8B_BPFLCD57_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2476	#define LCD_WF8B_BPFLCD57_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2477	#define LCD_WF8B_BPFLCD27_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2478	#define LCD_WF8B_BPFLCD27_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2479	#define LCD_WF8B_BPFLCD11_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2480	#define LCD_WF8B_BPFLCD11_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2481	#define LCD_WF8B_BPFLCD56_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2482	#define LCD_WF8B_BPFLCD56_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2483	#define LCD_WF8B_BPFLCD1_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2484	#define LCD_WF8B_BPFLCD1_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2485	#define LCD_WF8B_BPFLCD8_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2486	#define LCD_WF8B_BPFLCD8_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2487	#define LCD_WF8B_BPFLCD40_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2488	#define LCD_WF8B_BPFLCD40_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2489	#define LCD_WF8B_BPFLCD51_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2490	#define LCD_WF8B_BPFLCD51_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2491	#define LCD_WF8B_BPFLCD16_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2492	#define LCD_WF8B_BPFLCD16_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2493	#define LCD_WF8B_BPFLCD45_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2494	#define LCD_WF8B_BPFLCD45_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2495	#define LCD_WF8B_BPFLCD6_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2496	#define LCD_WF8B_BPFLCD6_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2497	#define LCD_WF8B_BPFLCD17_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2498	#define LCD_WF8B_BPFLCD17_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2499	#define LCD_WF8B_BPFLCD28_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2500	#define LCD_WF8B_BPFLCD28_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2501	#define LCD_WF8B_BPFLCD42_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2502	#define LCD_WF8B_BPFLCD42_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2503	#define LCD_WF8B_BPFLCD29_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2504	#define LCD_WF8B_BPFLCD29_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2505	#define LCD_WF8B_BPFLCD50_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2506	#define LCD_WF8B_BPFLCD50_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2507	#define LCD_WF8B_BPFLCD18_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2508	#define LCD_WF8B_BPFLCD18_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2509	#define LCD_WF8B_BPFLCD34_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2510	#define LCD_WF8B_BPFLCD34_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2511	#define LCD_WF8B_BPFLCD19_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2512	#define LCD_WF8B_BPFLCD19_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2513	#define LCD_WF8B_BPFLCD2_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2514	#define LCD_WF8B_BPFLCD2_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2515	#define LCD_WF8B_BPFLCD9_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2516	#define LCD_WF8B_BPFLCD9_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2517	#define LCD_WF8B_BPFLCD3_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2518	#define LCD_WF8B_BPFLCD3_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2519	#define LCD_WF8B_BPFLCD37_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2520	#define LCD_WF8B_BPFLCD37_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2521	#define LCD_WF8B_BPFLCD49_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2522	#define LCD_WF8B_BPFLCD49_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2523	#define LCD_WF8B_BPFLCD20_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2524	#define LCD_WF8B_BPFLCD20_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2525	#define LCD_WF8B_BPFLCD44_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2526	#define LCD_WF8B_BPFLCD44_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2527	#define LCD_WF8B_BPFLCD30_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2528	#define LCD_WF8B_BPFLCD30_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2529	#define LCD_WF8B_BPFLCD21_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2530	#define LCD_WF8B_BPFLCD21_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2531	#define LCD_WF8B_BPFLCD35_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2532	#define LCD_WF8B_BPFLCD35_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2533	#define LCD_WF8B_BPFLCD4_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2534	#define LCD_WF8B_BPFLCD4_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2535	#define LCD_WF8B_BPFLCD31_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2536	#define LCD_WF8B_BPFLCD31_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2537	#define LCD_WF8B_BPFLCD48_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2538	#define LCD_WF8B_BPFLCD48_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2539	#define LCD_WF8B_BPFLCD7_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2540	#define LCD_WF8B_BPFLCD7_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2541	#define LCD_WF8B_BPFLCD22_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2542	#define LCD_WF8B_BPFLCD22_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2543	#define LCD_WF8B_BPFLCD38_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2544	#define LCD_WF8B_BPFLCD38_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2545	#define LCD_WF8B_BPFLCD12_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2546	#define LCD_WF8B_BPFLCD12_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2547	#define LCD_WF8B_BPFLCD23_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2548	#define LCD_WF8B_BPFLCD23_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2549	#define LCD_WF8B_BPGLCD14_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2550	#define LCD_WF8B_BPGLCD14_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2551	#define LCD_WF8B_BPGLCD55_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2552	#define LCD_WF8B_BPGLCD55_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2553	#define LCD_WF8B_BPGLCD63_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2554	#define LCD_WF8B_BPGLCD63_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2555	#define LCD_WF8B_BPGLCD15_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2556	#define LCD_WF8B_BPGLCD15_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2557	#define LCD_WF8B_BPGLCD62_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2558	#define LCD_WF8B_BPGLCD62_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2559	#define LCD_WF8B_BPGLCD54_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2560	#define LCD_WF8B_BPGLCD54_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2561	#define LCD_WF8B_BPGLCD61_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2562	#define LCD_WF8B_BPGLCD61_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2563	#define LCD_WF8B_BPGLCD60_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2564	#define LCD_WF8B_BPGLCD60_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2565	#define LCD_WF8B_BPGLCD59_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2566	#define LCD_WF8B_BPGLCD59_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2567	#define LCD_WF8B_BPGLCD53_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2568	#define LCD_WF8B_BPGLCD53_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2569	#define LCD_WF8B_BPGLCD58_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2570	#define LCD_WF8B_BPGLCD58_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2571	#define LCD_WF8B_BPGLCD0_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2572	#define LCD_WF8B_BPGLCD0_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2573	#define LCD_WF8B_BPGLCD57_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2574	#define LCD_WF8B_BPGLCD57_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2575	#define LCD_WF8B_BPGLCD52_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2576	#define LCD_WF8B_BPGLCD52_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2577	#define LCD_WF8B_BPGLCD7_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2578	#define LCD_WF8B_BPGLCD7_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2579	#define LCD_WF8B_BPGLCD56_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2580	#define LCD_WF8B_BPGLCD56_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2581	#define LCD_WF8B_BPGLCD6_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2582	#define LCD_WF8B_BPGLCD6_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2583	#define LCD_WF8B_BPGLCD51_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2584	#define LCD_WF8B_BPGLCD51_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2585	#define LCD_WF8B_BPGLCD16_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2586	#define LCD_WF8B_BPGLCD16_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2587	#define LCD_WF8B_BPGLCD1_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2588	#define LCD_WF8B_BPGLCD1_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2589	#define LCD_WF8B_BPGLCD17_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2590	#define LCD_WF8B_BPGLCD17_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2591	#define LCD_WF8B_BPGLCD50_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2592	#define LCD_WF8B_BPGLCD50_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2593	#define LCD_WF8B_BPGLCD18_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2594	#define LCD_WF8B_BPGLCD18_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2595	#define LCD_WF8B_BPGLCD19_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2596	#define LCD_WF8B_BPGLCD19_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2597	#define LCD_WF8B_BPGLCD8_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2598	#define LCD_WF8B_BPGLCD8_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2599	#define LCD_WF8B_BPGLCD49_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2600	#define LCD_WF8B_BPGLCD49_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2601	#define LCD_WF8B_BPGLCD20_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2602	#define LCD_WF8B_BPGLCD20_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2603	#define LCD_WF8B_BPGLCD9_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2604	#define LCD_WF8B_BPGLCD9_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2605	#define LCD_WF8B_BPGLCD21_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2606	#define LCD_WF8B_BPGLCD21_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2607	#define LCD_WF8B_BPGLCD13_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2608	#define LCD_WF8B_BPGLCD13_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2609	#define LCD_WF8B_BPGLCD48_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2610	#define LCD_WF8B_BPGLCD48_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2611	#define LCD_WF8B_BPGLCD22_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2612	#define LCD_WF8B_BPGLCD22_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2613	#define LCD_WF8B_BPGLCD5_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2614	#define LCD_WF8B_BPGLCD5_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2615	#define LCD_WF8B_BPGLCD47_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2616	#define LCD_WF8B_BPGLCD47_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2617	#define LCD_WF8B_BPGLCD23_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2618	#define LCD_WF8B_BPGLCD23_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2619	#define LCD_WF8B_BPGLCD24_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2620	#define LCD_WF8B_BPGLCD24_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2621	#define LCD_WF8B_BPGLCD25_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2622	#define LCD_WF8B_BPGLCD25_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2623	#define LCD_WF8B_BPGLCD46_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2624	#define LCD_WF8B_BPGLCD46_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2625	#define LCD_WF8B_BPGLCD26_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2626	#define LCD_WF8B_BPGLCD26_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2627	#define LCD_WF8B_BPGLCD27_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2628	#define LCD_WF8B_BPGLCD27_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2629	#define LCD_WF8B_BPGLCD10_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2630	#define LCD_WF8B_BPGLCD10_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2631	#define LCD_WF8B_BPGLCD45_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2632	#define LCD_WF8B_BPGLCD45_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2633	#define LCD_WF8B_BPGLCD28_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2634	#define LCD_WF8B_BPGLCD28_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2635	#define LCD_WF8B_BPGLCD29_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2636	#define LCD_WF8B_BPGLCD29_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2637	#define LCD_WF8B_BPGLCD4_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2638	#define LCD_WF8B_BPGLCD4_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2639	#define LCD_WF8B_BPGLCD44_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2640	#define LCD_WF8B_BPGLCD44_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2641	#define LCD_WF8B_BPGLCD30_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2642	#define LCD_WF8B_BPGLCD30_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2643	#define LCD_WF8B_BPGLCD2_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2644	#define LCD_WF8B_BPGLCD2_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2645	#define LCD_WF8B_BPGLCD31_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2646	#define LCD_WF8B_BPGLCD31_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2647	#define LCD_WF8B_BPGLCD43_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2648	#define LCD_WF8B_BPGLCD43_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2649	#define LCD_WF8B_BPGLCD32_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2650	#define LCD_WF8B_BPGLCD32_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2651	#define LCD_WF8B_BPGLCD33_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2652	#define LCD_WF8B_BPGLCD33_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2653	#define LCD_WF8B_BPGLCD42_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2654	#define LCD_WF8B_BPGLCD42_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2655	#define LCD_WF8B_BPGLCD34_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2656	#define LCD_WF8B_BPGLCD34_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2657	#define LCD_WF8B_BPGLCD11_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2658	#define LCD_WF8B_BPGLCD11_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2659	#define LCD_WF8B_BPGLCD35_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2660	#define LCD_WF8B_BPGLCD35_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2661	#define LCD_WF8B_BPGLCD12_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2662	#define LCD_WF8B_BPGLCD12_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2663	#define LCD_WF8B_BPGLCD41_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2664	#define LCD_WF8B_BPGLCD41_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2665	#define LCD_WF8B_BPGLCD36_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2666	#define LCD_WF8B_BPGLCD36_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2667	#define LCD_WF8B_BPGLCD3_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2668	#define LCD_WF8B_BPGLCD3_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2669	#define LCD_WF8B_BPGLCD37_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2670	#define LCD_WF8B_BPGLCD37_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2671	#define LCD_WF8B_BPGLCD40_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2672	#define LCD_WF8B_BPGLCD40_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2673	#define LCD_WF8B_BPGLCD38_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2674	#define LCD_WF8B_BPGLCD38_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2675	#define LCD_WF8B_BPGLCD39_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2676	#define LCD_WF8B_BPGLCD39_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2677	#define LCD_WF8B_BPHLCD63_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2678	#define LCD_WF8B_BPHLCD63_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2679	#define LCD_WF8B_BPHLCD62_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2680	#define LCD_WF8B_BPHLCD62_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2681	#define LCD_WF8B_BPHLCD61_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2682	#define LCD_WF8B_BPHLCD61_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2683	#define LCD_WF8B_BPHLCD60_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2684	#define LCD_WF8B_BPHLCD60_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2685	#define LCD_WF8B_BPHLCD59_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2686	#define LCD_WF8B_BPHLCD59_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2687	#define LCD_WF8B_BPHLCD58_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2688	#define LCD_WF8B_BPHLCD58_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2689	#define LCD_WF8B_BPHLCD57_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2690	#define LCD_WF8B_BPHLCD57_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2691	#define LCD_WF8B_BPHLCD0_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2692	#define LCD_WF8B_BPHLCD0_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2693	#define LCD_WF8B_BPHLCD56_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2694	#define LCD_WF8B_BPHLCD56_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2695	#define LCD_WF8B_BPHLCD55_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2696	#define LCD_WF8B_BPHLCD55_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2697	#define LCD_WF8B_BPHLCD54_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2698	#define LCD_WF8B_BPHLCD54_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2699	#define LCD_WF8B_BPHLCD53_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2700	#define LCD_WF8B_BPHLCD53_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2701	#define LCD_WF8B_BPHLCD52_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2702	#define LCD_WF8B_BPHLCD52_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2703	#define LCD_WF8B_BPHLCD51_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2704	#define LCD_WF8B_BPHLCD51_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2705	#define LCD_WF8B_BPHLCD50_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2706	#define LCD_WF8B_BPHLCD50_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2707	#define LCD_WF8B_BPHLCD1_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2708	#define LCD_WF8B_BPHLCD1_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2709	#define LCD_WF8B_BPHLCD49_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2710	#define LCD_WF8B_BPHLCD49_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2711	#define LCD_WF8B_BPHLCD48_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2712	#define LCD_WF8B_BPHLCD48_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2713	#define LCD_WF8B_BPHLCD47_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2714	#define LCD_WF8B_BPHLCD47_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2715	#define LCD_WF8B_BPHLCD46_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2716	#define LCD_WF8B_BPHLCD46_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2717	#define LCD_WF8B_BPHLCD45_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2718	#define LCD_WF8B_BPHLCD45_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2719	#define LCD_WF8B_BPHLCD44_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2720	#define LCD_WF8B_BPHLCD44_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2721	#define LCD_WF8B_BPHLCD43_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2722	#define LCD_WF8B_BPHLCD43_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2723	#define LCD_WF8B_BPHLCD2_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2724	#define LCD_WF8B_BPHLCD2_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2725	#define LCD_WF8B_BPHLCD42_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2726	#define LCD_WF8B_BPHLCD42_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2727	#define LCD_WF8B_BPHLCD41_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2728	#define LCD_WF8B_BPHLCD41_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2729	#define LCD_WF8B_BPHLCD40_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2730	#define LCD_WF8B_BPHLCD40_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2731	#define LCD_WF8B_BPHLCD39_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2732	#define LCD_WF8B_BPHLCD39_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2733	#define LCD_WF8B_BPHLCD38_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2734	#define LCD_WF8B_BPHLCD38_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2735	#define LCD_WF8B_BPHLCD37_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2736	#define LCD_WF8B_BPHLCD37_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2737	#define LCD_WF8B_BPHLCD36_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2738	#define LCD_WF8B_BPHLCD36_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2739	#define LCD_WF8B_BPHLCD3_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2740	#define LCD_WF8B_BPHLCD3_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2741	#define LCD_WF8B_BPHLCD35_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2742	#define LCD_WF8B_BPHLCD35_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2743	#define LCD_WF8B_BPHLCD34_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2744	#define LCD_WF8B_BPHLCD34_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2745	#define LCD_WF8B_BPHLCD33_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2746	#define LCD_WF8B_BPHLCD33_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2747	#define LCD_WF8B_BPHLCD32_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2748	#define LCD_WF8B_BPHLCD32_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2749	#define LCD_WF8B_BPHLCD31_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2750	#define LCD_WF8B_BPHLCD31_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2751	#define LCD_WF8B_BPHLCD30_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2752	#define LCD_WF8B_BPHLCD30_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2753	#define LCD_WF8B_BPHLCD29_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2754	#define LCD_WF8B_BPHLCD29_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2755	#define LCD_WF8B_BPHLCD4_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2756	#define LCD_WF8B_BPHLCD4_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2757	#define LCD_WF8B_BPHLCD28_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2758	#define LCD_WF8B_BPHLCD28_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2759	#define LCD_WF8B_BPHLCD27_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2760	#define LCD_WF8B_BPHLCD27_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2761	#define LCD_WF8B_BPHLCD26_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2762	#define LCD_WF8B_BPHLCD26_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2763	#define LCD_WF8B_BPHLCD25_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2764	#define LCD_WF8B_BPHLCD25_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2765	#define LCD_WF8B_BPHLCD24_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2766	#define LCD_WF8B_BPHLCD24_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2767	#define LCD_WF8B_BPHLCD23_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2768	#define LCD_WF8B_BPHLCD23_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2769	#define LCD_WF8B_BPHLCD22_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2770	#define LCD_WF8B_BPHLCD22_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2771	#define LCD_WF8B_BPHLCD5_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2772	#define LCD_WF8B_BPHLCD5_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2773	#define LCD_WF8B_BPHLCD21_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2774	#define LCD_WF8B_BPHLCD21_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2775	#define LCD_WF8B_BPHLCD20_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2776	#define LCD_WF8B_BPHLCD20_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2777	#define LCD_WF8B_BPHLCD19_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2778	#define LCD_WF8B_BPHLCD19_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2779	#define LCD_WF8B_BPHLCD18_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2780	#define LCD_WF8B_BPHLCD18_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2781	#define LCD_WF8B_BPHLCD17_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2782	#define LCD_WF8B_BPHLCD17_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2783	#define LCD_WF8B_BPHLCD16_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2784	#define LCD_WF8B_BPHLCD16_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2785	#define LCD_WF8B_BPHLCD15_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2786	#define LCD_WF8B_BPHLCD15_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2787	#define LCD_WF8B_BPHLCD6_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2788	#define LCD_WF8B_BPHLCD6_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2789	#define LCD_WF8B_BPHLCD14_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2790	#define LCD_WF8B_BPHLCD14_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2791	#define LCD_WF8B_BPHLCD13_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2792	#define LCD_WF8B_BPHLCD13_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2793	#define LCD_WF8B_BPHLCD12_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2794	#define LCD_WF8B_BPHLCD12_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2795	#define LCD_WF8B_BPHLCD11_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2796	#define LCD_WF8B_BPHLCD11_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2797	#define LCD_WF8B_BPHLCD10_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2798	#define LCD_WF8B_BPHLCD10_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2799	#define LCD_WF8B_BPHLCD9_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2800	#define LCD_WF8B_BPHLCD9_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2801	#define LCD_WF8B_BPHLCD8_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2802	#define LCD_WF8B_BPHLCD8_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2803	#define LCD_WF8B_BPHLCD7_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2804	#define LCD_WF8B_BPHLCD7_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2805
pradeepvk2208	1:c0c5ac8eac80	2806	/*!
pradeepvk2208	1:c0c5ac8eac80	2807	* @}
pradeepvk2208	1:c0c5ac8eac80	2808	/ / end of group LCD_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	2809
pradeepvk2208	1:c0c5ac8eac80	2810
pradeepvk2208	1:c0c5ac8eac80	2811	/* LCD - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	2812	/** Peripheral LCD base address */
pradeepvk2208	1:c0c5ac8eac80	2813	#define LCD_BASE (0x40053000u)
pradeepvk2208	1:c0c5ac8eac80	2814	/** Peripheral LCD base pointer */
pradeepvk2208	1:c0c5ac8eac80	2815	#define LCD ((LCD_Type *)LCD_BASE)
pradeepvk2208	1:c0c5ac8eac80	2816	/** Array initializer of LCD peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	2817	#define LCD_BASES { LCD }
pradeepvk2208	1:c0c5ac8eac80	2818
pradeepvk2208	1:c0c5ac8eac80	2819	/*!
pradeepvk2208	1:c0c5ac8eac80	2820	* @}
pradeepvk2208	1:c0c5ac8eac80	2821	/ / end of group LCD_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	2822
pradeepvk2208	1:c0c5ac8eac80	2823
pradeepvk2208	1:c0c5ac8eac80	2824	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	2825	-- LLWU Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	2826	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	2827
pradeepvk2208	1:c0c5ac8eac80	2828	/*!
pradeepvk2208	1:c0c5ac8eac80	2829	* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	2830	* @{
pradeepvk2208	1:c0c5ac8eac80	2831	*/
pradeepvk2208	1:c0c5ac8eac80	2832
pradeepvk2208	1:c0c5ac8eac80	2833	/** LLWU - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	2834	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	2835	__IO uint8_t PE1; /*< LLWU Pin Enable 1 register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	2836	__IO uint8_t PE2; /*< LLWU Pin Enable 2 register, offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	2837	__IO uint8_t PE3; /*< LLWU Pin Enable 3 register, offset: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	2838	__IO uint8_t PE4; /*< LLWU Pin Enable 4 register, offset: 0x3 /
pradeepvk2208	1:c0c5ac8eac80	2839	__IO uint8_t ME; /*< LLWU Module Enable register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	2840	__IO uint8_t F1; /*< LLWU Flag 1 register, offset: 0x5 /
pradeepvk2208	1:c0c5ac8eac80	2841	__IO uint8_t F2; /*< LLWU Flag 2 register, offset: 0x6 /
pradeepvk2208	1:c0c5ac8eac80	2842	__I uint8_t F3; /*< LLWU Flag 3 register, offset: 0x7 /
pradeepvk2208	1:c0c5ac8eac80	2843	__IO uint8_t FILT1; /*< LLWU Pin Filter 1 register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	2844	__IO uint8_t FILT2; /*< LLWU Pin Filter 2 register, offset: 0x9 /
pradeepvk2208	1:c0c5ac8eac80	2845	} LLWU_Type;
pradeepvk2208	1:c0c5ac8eac80	2846
pradeepvk2208	1:c0c5ac8eac80	2847	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	2848	-- LLWU Register Masks
pradeepvk2208	1:c0c5ac8eac80	2849	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	2850
pradeepvk2208	1:c0c5ac8eac80	2851	/*!
pradeepvk2208	1:c0c5ac8eac80	2852	* @addtogroup LLWU_Register_Masks LLWU Register Masks
pradeepvk2208	1:c0c5ac8eac80	2853	* @{
pradeepvk2208	1:c0c5ac8eac80	2854	*/
pradeepvk2208	1:c0c5ac8eac80	2855
pradeepvk2208	1:c0c5ac8eac80	2856	/* PE1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	2857	#define LLWU_PE1_WUPE0_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	2858	#define LLWU_PE1_WUPE0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	2859	#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
pradeepvk2208	1:c0c5ac8eac80	2860	#define LLWU_PE1_WUPE1_MASK 0xCu
pradeepvk2208	1:c0c5ac8eac80	2861	#define LLWU_PE1_WUPE1_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2862	#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
pradeepvk2208	1:c0c5ac8eac80	2863	#define LLWU_PE1_WUPE2_MASK 0x30u
pradeepvk2208	1:c0c5ac8eac80	2864	#define LLWU_PE1_WUPE2_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2865	#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
pradeepvk2208	1:c0c5ac8eac80	2866	#define LLWU_PE1_WUPE3_MASK 0xC0u
pradeepvk2208	1:c0c5ac8eac80	2867	#define LLWU_PE1_WUPE3_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2868	#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
pradeepvk2208	1:c0c5ac8eac80	2869	/* PE2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	2870	#define LLWU_PE2_WUPE4_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	2871	#define LLWU_PE2_WUPE4_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	2872	#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
pradeepvk2208	1:c0c5ac8eac80	2873	#define LLWU_PE2_WUPE5_MASK 0xCu
pradeepvk2208	1:c0c5ac8eac80	2874	#define LLWU_PE2_WUPE5_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2875	#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
pradeepvk2208	1:c0c5ac8eac80	2876	#define LLWU_PE2_WUPE6_MASK 0x30u
pradeepvk2208	1:c0c5ac8eac80	2877	#define LLWU_PE2_WUPE6_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2878	#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
pradeepvk2208	1:c0c5ac8eac80	2879	#define LLWU_PE2_WUPE7_MASK 0xC0u
pradeepvk2208	1:c0c5ac8eac80	2880	#define LLWU_PE2_WUPE7_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2881	#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
pradeepvk2208	1:c0c5ac8eac80	2882	/* PE3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	2883	#define LLWU_PE3_WUPE8_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	2884	#define LLWU_PE3_WUPE8_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	2885	#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
pradeepvk2208	1:c0c5ac8eac80	2886	#define LLWU_PE3_WUPE9_MASK 0xCu
pradeepvk2208	1:c0c5ac8eac80	2887	#define LLWU_PE3_WUPE9_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2888	#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
pradeepvk2208	1:c0c5ac8eac80	2889	#define LLWU_PE3_WUPE10_MASK 0x30u
pradeepvk2208	1:c0c5ac8eac80	2890	#define LLWU_PE3_WUPE10_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2891	#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
pradeepvk2208	1:c0c5ac8eac80	2892	#define LLWU_PE3_WUPE11_MASK 0xC0u
pradeepvk2208	1:c0c5ac8eac80	2893	#define LLWU_PE3_WUPE11_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2894	#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
pradeepvk2208	1:c0c5ac8eac80	2895	/* PE4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	2896	#define LLWU_PE4_WUPE12_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	2897	#define LLWU_PE4_WUPE12_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	2898	#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
pradeepvk2208	1:c0c5ac8eac80	2899	#define LLWU_PE4_WUPE13_MASK 0xCu
pradeepvk2208	1:c0c5ac8eac80	2900	#define LLWU_PE4_WUPE13_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2901	#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
pradeepvk2208	1:c0c5ac8eac80	2902	#define LLWU_PE4_WUPE14_MASK 0x30u
pradeepvk2208	1:c0c5ac8eac80	2903	#define LLWU_PE4_WUPE14_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2904	#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
pradeepvk2208	1:c0c5ac8eac80	2905	#define LLWU_PE4_WUPE15_MASK 0xC0u
pradeepvk2208	1:c0c5ac8eac80	2906	#define LLWU_PE4_WUPE15_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2907	#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
pradeepvk2208	1:c0c5ac8eac80	2908	/* ME Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	2909	#define LLWU_ME_WUME0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	2910	#define LLWU_ME_WUME0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	2911	#define LLWU_ME_WUME1_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2912	#define LLWU_ME_WUME1_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2913	#define LLWU_ME_WUME2_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2914	#define LLWU_ME_WUME2_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2915	#define LLWU_ME_WUME3_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2916	#define LLWU_ME_WUME3_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2917	#define LLWU_ME_WUME4_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2918	#define LLWU_ME_WUME4_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2919	#define LLWU_ME_WUME5_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2920	#define LLWU_ME_WUME5_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2921	#define LLWU_ME_WUME6_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2922	#define LLWU_ME_WUME6_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2923	#define LLWU_ME_WUME7_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2924	#define LLWU_ME_WUME7_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2925	/* F1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	2926	#define LLWU_F1_WUF0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	2927	#define LLWU_F1_WUF0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	2928	#define LLWU_F1_WUF1_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2929	#define LLWU_F1_WUF1_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2930	#define LLWU_F1_WUF2_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2931	#define LLWU_F1_WUF2_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2932	#define LLWU_F1_WUF3_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2933	#define LLWU_F1_WUF3_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2934	#define LLWU_F1_WUF4_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2935	#define LLWU_F1_WUF4_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2936	#define LLWU_F1_WUF5_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2937	#define LLWU_F1_WUF5_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2938	#define LLWU_F1_WUF6_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2939	#define LLWU_F1_WUF6_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2940	#define LLWU_F1_WUF7_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2941	#define LLWU_F1_WUF7_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2942	/* F2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	2943	#define LLWU_F2_WUF8_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	2944	#define LLWU_F2_WUF8_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	2945	#define LLWU_F2_WUF9_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2946	#define LLWU_F2_WUF9_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2947	#define LLWU_F2_WUF10_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2948	#define LLWU_F2_WUF10_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2949	#define LLWU_F2_WUF11_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2950	#define LLWU_F2_WUF11_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2951	#define LLWU_F2_WUF12_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2952	#define LLWU_F2_WUF12_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2953	#define LLWU_F2_WUF13_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2954	#define LLWU_F2_WUF13_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2955	#define LLWU_F2_WUF14_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2956	#define LLWU_F2_WUF14_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2957	#define LLWU_F2_WUF15_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2958	#define LLWU_F2_WUF15_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2959	/* F3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	2960	#define LLWU_F3_MWUF0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	2961	#define LLWU_F3_MWUF0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	2962	#define LLWU_F3_MWUF1_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	2963	#define LLWU_F3_MWUF1_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	2964	#define LLWU_F3_MWUF2_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	2965	#define LLWU_F3_MWUF2_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	2966	#define LLWU_F3_MWUF3_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	2967	#define LLWU_F3_MWUF3_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	2968	#define LLWU_F3_MWUF4_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	2969	#define LLWU_F3_MWUF4_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	2970	#define LLWU_F3_MWUF5_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	2971	#define LLWU_F3_MWUF5_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2972	#define LLWU_F3_MWUF6_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	2973	#define LLWU_F3_MWUF6_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	2974	#define LLWU_F3_MWUF7_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2975	#define LLWU_F3_MWUF7_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2976	/* FILT1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	2977	#define LLWU_FILT1_FILTSEL_MASK 0xFu
pradeepvk2208	1:c0c5ac8eac80	2978	#define LLWU_FILT1_FILTSEL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	2979	#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
pradeepvk2208	1:c0c5ac8eac80	2980	#define LLWU_FILT1_FILTE_MASK 0x60u
pradeepvk2208	1:c0c5ac8eac80	2981	#define LLWU_FILT1_FILTE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2982	#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
pradeepvk2208	1:c0c5ac8eac80	2983	#define LLWU_FILT1_FILTF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2984	#define LLWU_FILT1_FILTF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2985	/* FILT2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	2986	#define LLWU_FILT2_FILTSEL_MASK 0xFu
pradeepvk2208	1:c0c5ac8eac80	2987	#define LLWU_FILT2_FILTSEL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	2988	#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
pradeepvk2208	1:c0c5ac8eac80	2989	#define LLWU_FILT2_FILTE_MASK 0x60u
pradeepvk2208	1:c0c5ac8eac80	2990	#define LLWU_FILT2_FILTE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	2991	#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
pradeepvk2208	1:c0c5ac8eac80	2992	#define LLWU_FILT2_FILTF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	2993	#define LLWU_FILT2_FILTF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	2994
pradeepvk2208	1:c0c5ac8eac80	2995	/*!
pradeepvk2208	1:c0c5ac8eac80	2996	* @}
pradeepvk2208	1:c0c5ac8eac80	2997	/ / end of group LLWU_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	2998
pradeepvk2208	1:c0c5ac8eac80	2999
pradeepvk2208	1:c0c5ac8eac80	3000	/* LLWU - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	3001	/** Peripheral LLWU base address */
pradeepvk2208	1:c0c5ac8eac80	3002	#define LLWU_BASE (0x4007C000u)
pradeepvk2208	1:c0c5ac8eac80	3003	/** Peripheral LLWU base pointer */
pradeepvk2208	1:c0c5ac8eac80	3004	#define LLWU ((LLWU_Type *)LLWU_BASE)
pradeepvk2208	1:c0c5ac8eac80	3005	/** Array initializer of LLWU peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	3006	#define LLWU_BASES { LLWU }
pradeepvk2208	1:c0c5ac8eac80	3007
pradeepvk2208	1:c0c5ac8eac80	3008	/*!
pradeepvk2208	1:c0c5ac8eac80	3009	* @}
pradeepvk2208	1:c0c5ac8eac80	3010	/ / end of group LLWU_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	3011
pradeepvk2208	1:c0c5ac8eac80	3012
pradeepvk2208	1:c0c5ac8eac80	3013	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3014	-- LPTMR Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3015	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3016
pradeepvk2208	1:c0c5ac8eac80	3017	/*!
pradeepvk2208	1:c0c5ac8eac80	3018	* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3019	* @{
pradeepvk2208	1:c0c5ac8eac80	3020	*/
pradeepvk2208	1:c0c5ac8eac80	3021
pradeepvk2208	1:c0c5ac8eac80	3022	/** LPTMR - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	3023	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	3024	__IO uint32_t CSR; /*< Low Power Timer Control Status Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	3025	__IO uint32_t PSR; /*< Low Power Timer Prescale Register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	3026	__IO uint32_t CMR; /*< Low Power Timer Compare Register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	3027	__I uint32_t CNR; /*< Low Power Timer Counter Register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	3028	} LPTMR_Type;
pradeepvk2208	1:c0c5ac8eac80	3029
pradeepvk2208	1:c0c5ac8eac80	3030	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3031	-- LPTMR Register Masks
pradeepvk2208	1:c0c5ac8eac80	3032	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3033
pradeepvk2208	1:c0c5ac8eac80	3034	/*!
pradeepvk2208	1:c0c5ac8eac80	3035	* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
pradeepvk2208	1:c0c5ac8eac80	3036	* @{
pradeepvk2208	1:c0c5ac8eac80	3037	*/
pradeepvk2208	1:c0c5ac8eac80	3038
pradeepvk2208	1:c0c5ac8eac80	3039	/* CSR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3040	#define LPTMR_CSR_TEN_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3041	#define LPTMR_CSR_TEN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3042	#define LPTMR_CSR_TMS_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3043	#define LPTMR_CSR_TMS_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3044	#define LPTMR_CSR_TFC_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3045	#define LPTMR_CSR_TFC_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3046	#define LPTMR_CSR_TPP_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	3047	#define LPTMR_CSR_TPP_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	3048	#define LPTMR_CSR_TPS_MASK 0x30u
pradeepvk2208	1:c0c5ac8eac80	3049	#define LPTMR_CSR_TPS_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	3050	#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
pradeepvk2208	1:c0c5ac8eac80	3051	#define LPTMR_CSR_TIE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	3052	#define LPTMR_CSR_TIE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3053	#define LPTMR_CSR_TCF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	3054	#define LPTMR_CSR_TCF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	3055	/* PSR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3056	#define LPTMR_PSR_PCS_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	3057	#define LPTMR_PSR_PCS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3058	#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
pradeepvk2208	1:c0c5ac8eac80	3059	#define LPTMR_PSR_PBYP_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3060	#define LPTMR_PSR_PBYP_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3061	#define LPTMR_PSR_PRESCALE_MASK 0x78u
pradeepvk2208	1:c0c5ac8eac80	3062	#define LPTMR_PSR_PRESCALE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	3063	#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
pradeepvk2208	1:c0c5ac8eac80	3064	/* CMR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3065	#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	3066	#define LPTMR_CMR_COMPARE_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3067	#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
pradeepvk2208	1:c0c5ac8eac80	3068	/* CNR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3069	#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	3070	#define LPTMR_CNR_COUNTER_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3071	#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
pradeepvk2208	1:c0c5ac8eac80	3072
pradeepvk2208	1:c0c5ac8eac80	3073	/*!
pradeepvk2208	1:c0c5ac8eac80	3074	* @}
pradeepvk2208	1:c0c5ac8eac80	3075	/ / end of group LPTMR_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	3076
pradeepvk2208	1:c0c5ac8eac80	3077
pradeepvk2208	1:c0c5ac8eac80	3078	/* LPTMR - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	3079	/** Peripheral LPTMR0 base address */
pradeepvk2208	1:c0c5ac8eac80	3080	#define LPTMR0_BASE (0x40040000u)
pradeepvk2208	1:c0c5ac8eac80	3081	/** Peripheral LPTMR0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	3082	#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
pradeepvk2208	1:c0c5ac8eac80	3083	/** Array initializer of LPTMR peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	3084	#define LPTMR_BASES { LPTMR0 }
pradeepvk2208	1:c0c5ac8eac80	3085
pradeepvk2208	1:c0c5ac8eac80	3086	/*!
pradeepvk2208	1:c0c5ac8eac80	3087	* @}
pradeepvk2208	1:c0c5ac8eac80	3088	/ / end of group LPTMR_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	3089
pradeepvk2208	1:c0c5ac8eac80	3090
pradeepvk2208	1:c0c5ac8eac80	3091	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3092	-- MCG Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3093	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3094
pradeepvk2208	1:c0c5ac8eac80	3095	/*!
pradeepvk2208	1:c0c5ac8eac80	3096	* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3097	* @{
pradeepvk2208	1:c0c5ac8eac80	3098	*/
pradeepvk2208	1:c0c5ac8eac80	3099
pradeepvk2208	1:c0c5ac8eac80	3100	/** MCG - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	3101	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	3102	__IO uint8_t C1; /*< MCG Control 1 Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	3103	__IO uint8_t C2; /*< MCG Control 2 Register, offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	3104	__IO uint8_t C3; /*< MCG Control 3 Register, offset: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	3105	__IO uint8_t C4; /*< MCG Control 4 Register, offset: 0x3 /
pradeepvk2208	1:c0c5ac8eac80	3106	__IO uint8_t C5; /*< MCG Control 5 Register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	3107	__IO uint8_t C6; /*< MCG Control 6 Register, offset: 0x5 /
pradeepvk2208	1:c0c5ac8eac80	3108	__I uint8_t S; /*< MCG Status Register, offset: 0x6 /
pradeepvk2208	1:c0c5ac8eac80	3109	uint8_t RESERVED_0[1];
pradeepvk2208	1:c0c5ac8eac80	3110	__IO uint8_t SC; /*< MCG Status and Control Register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	3111	uint8_t RESERVED_1[1];
pradeepvk2208	1:c0c5ac8eac80	3112	__IO uint8_t ATCVH; /*< MCG Auto Trim Compare Value High Register, offset: 0xA /
pradeepvk2208	1:c0c5ac8eac80	3113	__IO uint8_t ATCVL; /*< MCG Auto Trim Compare Value Low Register, offset: 0xB /
pradeepvk2208	1:c0c5ac8eac80	3114	__I uint8_t C7; /*< MCG Control 7 Register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	3115	__IO uint8_t C8; /*< MCG Control 8 Register, offset: 0xD /
pradeepvk2208	1:c0c5ac8eac80	3116	__I uint8_t C9; /*< MCG Control 9 Register, offset: 0xE /
pradeepvk2208	1:c0c5ac8eac80	3117	__I uint8_t C10; /*< MCG Control 10 Register, offset: 0xF /
pradeepvk2208	1:c0c5ac8eac80	3118	} MCG_Type;
pradeepvk2208	1:c0c5ac8eac80	3119
pradeepvk2208	1:c0c5ac8eac80	3120	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3121	-- MCG Register Masks
pradeepvk2208	1:c0c5ac8eac80	3122	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3123
pradeepvk2208	1:c0c5ac8eac80	3124	/*!
pradeepvk2208	1:c0c5ac8eac80	3125	* @addtogroup MCG_Register_Masks MCG Register Masks
pradeepvk2208	1:c0c5ac8eac80	3126	* @{
pradeepvk2208	1:c0c5ac8eac80	3127	*/
pradeepvk2208	1:c0c5ac8eac80	3128
pradeepvk2208	1:c0c5ac8eac80	3129	/* C1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3130	#define MCG_C1_IREFSTEN_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3131	#define MCG_C1_IREFSTEN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3132	#define MCG_C1_IRCLKEN_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3133	#define MCG_C1_IRCLKEN_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3134	#define MCG_C1_IREFS_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3135	#define MCG_C1_IREFS_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3136	#define MCG_C1_FRDIV_MASK 0x38u
pradeepvk2208	1:c0c5ac8eac80	3137	#define MCG_C1_FRDIV_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	3138	#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
pradeepvk2208	1:c0c5ac8eac80	3139	#define MCG_C1_CLKS_MASK 0xC0u
pradeepvk2208	1:c0c5ac8eac80	3140	#define MCG_C1_CLKS_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3141	#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
pradeepvk2208	1:c0c5ac8eac80	3142	/* C2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3143	#define MCG_C2_IRCS_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3144	#define MCG_C2_IRCS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3145	#define MCG_C2_LP_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3146	#define MCG_C2_LP_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3147	#define MCG_C2_EREFS0_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3148	#define MCG_C2_EREFS0_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3149	#define MCG_C2_HGO0_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	3150	#define MCG_C2_HGO0_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	3151	#define MCG_C2_RANGE0_MASK 0x30u
pradeepvk2208	1:c0c5ac8eac80	3152	#define MCG_C2_RANGE0_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	3153	#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
pradeepvk2208	1:c0c5ac8eac80	3154	#define MCG_C2_FCFTRIM_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	3155	#define MCG_C2_FCFTRIM_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3156	#define MCG_C2_LOCRE0_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	3157	#define MCG_C2_LOCRE0_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	3158	/* C3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3159	#define MCG_C3_SCTRIM_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3160	#define MCG_C3_SCTRIM_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3161	#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
pradeepvk2208	1:c0c5ac8eac80	3162	/* C4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3163	#define MCG_C4_SCFTRIM_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3164	#define MCG_C4_SCFTRIM_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3165	#define MCG_C4_FCTRIM_MASK 0x1Eu
pradeepvk2208	1:c0c5ac8eac80	3166	#define MCG_C4_FCTRIM_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3167	#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
pradeepvk2208	1:c0c5ac8eac80	3168	#define MCG_C4_DRST_DRS_MASK 0x60u
pradeepvk2208	1:c0c5ac8eac80	3169	#define MCG_C4_DRST_DRS_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	3170	#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
pradeepvk2208	1:c0c5ac8eac80	3171	#define MCG_C4_DMX32_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	3172	#define MCG_C4_DMX32_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	3173	/* C5 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3174	#define MCG_C5_PRDIV0_MASK 0x1Fu
pradeepvk2208	1:c0c5ac8eac80	3175	#define MCG_C5_PRDIV0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3176	#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
pradeepvk2208	1:c0c5ac8eac80	3177	#define MCG_C5_PLLSTEN0_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	3178	#define MCG_C5_PLLSTEN0_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	3179	#define MCG_C5_PLLCLKEN0_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	3180	#define MCG_C5_PLLCLKEN0_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3181	/* C6 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3182	#define MCG_C6_VDIV0_MASK 0x1Fu
pradeepvk2208	1:c0c5ac8eac80	3183	#define MCG_C6_VDIV0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3184	#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
pradeepvk2208	1:c0c5ac8eac80	3185	#define MCG_C6_CME0_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	3186	#define MCG_C6_CME0_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	3187	#define MCG_C6_PLLS_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	3188	#define MCG_C6_PLLS_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3189	#define MCG_C6_LOLIE0_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	3190	#define MCG_C6_LOLIE0_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	3191	/* S Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3192	#define MCG_S_IRCST_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3193	#define MCG_S_IRCST_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3194	#define MCG_S_OSCINIT0_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3195	#define MCG_S_OSCINIT0_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3196	#define MCG_S_CLKST_MASK 0xCu
pradeepvk2208	1:c0c5ac8eac80	3197	#define MCG_S_CLKST_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3198	#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
pradeepvk2208	1:c0c5ac8eac80	3199	#define MCG_S_IREFST_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	3200	#define MCG_S_IREFST_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	3201	#define MCG_S_PLLST_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	3202	#define MCG_S_PLLST_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	3203	#define MCG_S_LOCK0_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	3204	#define MCG_S_LOCK0_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3205	#define MCG_S_LOLS_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	3206	#define MCG_S_LOLS_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	3207	/* SC Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3208	#define MCG_SC_LOCS0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3209	#define MCG_SC_LOCS0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3210	#define MCG_SC_FCRDIV_MASK 0xEu
pradeepvk2208	1:c0c5ac8eac80	3211	#define MCG_SC_FCRDIV_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3212	#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
pradeepvk2208	1:c0c5ac8eac80	3213	#define MCG_SC_FLTPRSRV_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	3214	#define MCG_SC_FLTPRSRV_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	3215	#define MCG_SC_ATMF_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	3216	#define MCG_SC_ATMF_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	3217	#define MCG_SC_ATMS_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	3218	#define MCG_SC_ATMS_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3219	#define MCG_SC_ATME_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	3220	#define MCG_SC_ATME_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	3221	/* ATCVH Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3222	#define MCG_ATCVH_ATCVH_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3223	#define MCG_ATCVH_ATCVH_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3224	#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
pradeepvk2208	1:c0c5ac8eac80	3225	/* ATCVL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3226	#define MCG_ATCVL_ATCVL_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3227	#define MCG_ATCVL_ATCVL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3228	#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
pradeepvk2208	1:c0c5ac8eac80	3229	/* C8 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3230	#define MCG_C8_LOLRE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	3231	#define MCG_C8_LOLRE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3232
pradeepvk2208	1:c0c5ac8eac80	3233	/*!
pradeepvk2208	1:c0c5ac8eac80	3234	* @}
pradeepvk2208	1:c0c5ac8eac80	3235	/ / end of group MCG_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	3236
pradeepvk2208	1:c0c5ac8eac80	3237
pradeepvk2208	1:c0c5ac8eac80	3238	/* MCG - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	3239	/** Peripheral MCG base address */
pradeepvk2208	1:c0c5ac8eac80	3240	#define MCG_BASE (0x40064000u)
pradeepvk2208	1:c0c5ac8eac80	3241	/** Peripheral MCG base pointer */
pradeepvk2208	1:c0c5ac8eac80	3242	#define MCG ((MCG_Type *)MCG_BASE)
pradeepvk2208	1:c0c5ac8eac80	3243	/** Array initializer of MCG peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	3244	#define MCG_BASES { MCG }
pradeepvk2208	1:c0c5ac8eac80	3245
pradeepvk2208	1:c0c5ac8eac80	3246	/*!
pradeepvk2208	1:c0c5ac8eac80	3247	* @}
pradeepvk2208	1:c0c5ac8eac80	3248	/ / end of group MCG_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	3249
pradeepvk2208	1:c0c5ac8eac80	3250
pradeepvk2208	1:c0c5ac8eac80	3251	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3252	-- MCM Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3253	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3254
pradeepvk2208	1:c0c5ac8eac80	3255	/*!
pradeepvk2208	1:c0c5ac8eac80	3256	* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3257	* @{
pradeepvk2208	1:c0c5ac8eac80	3258	*/
pradeepvk2208	1:c0c5ac8eac80	3259
pradeepvk2208	1:c0c5ac8eac80	3260	/** MCM - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	3261	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	3262	uint8_t RESERVED_0[8];
pradeepvk2208	1:c0c5ac8eac80	3263	__I uint16_t PLASC; /*< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	3264	__I uint16_t PLAMC; /*< Crossbar Switch (AXBS) Master Configuration, offset: 0xA /
pradeepvk2208	1:c0c5ac8eac80	3265	__IO uint32_t PLACR; /*< Platform Control Register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	3266	uint8_t RESERVED_1[48];
pradeepvk2208	1:c0c5ac8eac80	3267	__IO uint32_t CPO; /*< Compute Operation Control Register, offset: 0x40 /
pradeepvk2208	1:c0c5ac8eac80	3268	} MCM_Type;
pradeepvk2208	1:c0c5ac8eac80	3269
pradeepvk2208	1:c0c5ac8eac80	3270	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3271	-- MCM Register Masks
pradeepvk2208	1:c0c5ac8eac80	3272	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3273
pradeepvk2208	1:c0c5ac8eac80	3274	/*!
pradeepvk2208	1:c0c5ac8eac80	3275	* @addtogroup MCM_Register_Masks MCM Register Masks
pradeepvk2208	1:c0c5ac8eac80	3276	* @{
pradeepvk2208	1:c0c5ac8eac80	3277	*/
pradeepvk2208	1:c0c5ac8eac80	3278
pradeepvk2208	1:c0c5ac8eac80	3279	/* PLASC Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3280	#define MCM_PLASC_ASC_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3281	#define MCM_PLASC_ASC_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3282	#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
pradeepvk2208	1:c0c5ac8eac80	3283	/* PLAMC Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3284	#define MCM_PLAMC_AMC_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3285	#define MCM_PLAMC_AMC_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3286	#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
pradeepvk2208	1:c0c5ac8eac80	3287	/* PLACR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3288	#define MCM_PLACR_ARB_MASK 0x200u
pradeepvk2208	1:c0c5ac8eac80	3289	#define MCM_PLACR_ARB_SHIFT 9
pradeepvk2208	1:c0c5ac8eac80	3290	#define MCM_PLACR_CFCC_MASK 0x400u
pradeepvk2208	1:c0c5ac8eac80	3291	#define MCM_PLACR_CFCC_SHIFT 10
pradeepvk2208	1:c0c5ac8eac80	3292	#define MCM_PLACR_DFCDA_MASK 0x800u
pradeepvk2208	1:c0c5ac8eac80	3293	#define MCM_PLACR_DFCDA_SHIFT 11
pradeepvk2208	1:c0c5ac8eac80	3294	#define MCM_PLACR_DFCIC_MASK 0x1000u
pradeepvk2208	1:c0c5ac8eac80	3295	#define MCM_PLACR_DFCIC_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	3296	#define MCM_PLACR_DFCC_MASK 0x2000u
pradeepvk2208	1:c0c5ac8eac80	3297	#define MCM_PLACR_DFCC_SHIFT 13
pradeepvk2208	1:c0c5ac8eac80	3298	#define MCM_PLACR_EFDS_MASK 0x4000u
pradeepvk2208	1:c0c5ac8eac80	3299	#define MCM_PLACR_EFDS_SHIFT 14
pradeepvk2208	1:c0c5ac8eac80	3300	#define MCM_PLACR_DFCS_MASK 0x8000u
pradeepvk2208	1:c0c5ac8eac80	3301	#define MCM_PLACR_DFCS_SHIFT 15
pradeepvk2208	1:c0c5ac8eac80	3302	#define MCM_PLACR_ESFC_MASK 0x10000u
pradeepvk2208	1:c0c5ac8eac80	3303	#define MCM_PLACR_ESFC_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	3304	/* CPO Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3305	#define MCM_CPO_CPOREQ_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3306	#define MCM_CPO_CPOREQ_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3307	#define MCM_CPO_CPOACK_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3308	#define MCM_CPO_CPOACK_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3309	#define MCM_CPO_CPOWOI_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3310	#define MCM_CPO_CPOWOI_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3311
pradeepvk2208	1:c0c5ac8eac80	3312	/*!
pradeepvk2208	1:c0c5ac8eac80	3313	* @}
pradeepvk2208	1:c0c5ac8eac80	3314	/ / end of group MCM_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	3315
pradeepvk2208	1:c0c5ac8eac80	3316
pradeepvk2208	1:c0c5ac8eac80	3317	/* MCM - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	3318	/** Peripheral MCM base address */
pradeepvk2208	1:c0c5ac8eac80	3319	#define MCM_BASE (0xF0003000u)
pradeepvk2208	1:c0c5ac8eac80	3320	/** Peripheral MCM base pointer */
pradeepvk2208	1:c0c5ac8eac80	3321	#define MCM ((MCM_Type *)MCM_BASE)
pradeepvk2208	1:c0c5ac8eac80	3322	/** Array initializer of MCM peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	3323	#define MCM_BASES { MCM }
pradeepvk2208	1:c0c5ac8eac80	3324
pradeepvk2208	1:c0c5ac8eac80	3325	/*!
pradeepvk2208	1:c0c5ac8eac80	3326	* @}
pradeepvk2208	1:c0c5ac8eac80	3327	/ / end of group MCM_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	3328
pradeepvk2208	1:c0c5ac8eac80	3329
pradeepvk2208	1:c0c5ac8eac80	3330	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3331	-- MTB Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3332	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3333
pradeepvk2208	1:c0c5ac8eac80	3334	/*!
pradeepvk2208	1:c0c5ac8eac80	3335	* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3336	* @{
pradeepvk2208	1:c0c5ac8eac80	3337	*/
pradeepvk2208	1:c0c5ac8eac80	3338
pradeepvk2208	1:c0c5ac8eac80	3339	/** MTB - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	3340	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	3341	__IO uint32_t POSITION; /*< MTB Position Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	3342	__IO uint32_t MASTER; /*< MTB Master Register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	3343	__IO uint32_t FLOW; /*< MTB Flow Register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	3344	__I uint32_t BASE; /*< MTB Base Register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	3345	uint8_t RESERVED_0[3824];
pradeepvk2208	1:c0c5ac8eac80	3346	__I uint32_t MODECTRL; /*< Integration Mode Control Register, offset: 0xF00 /
pradeepvk2208	1:c0c5ac8eac80	3347	uint8_t RESERVED_1[156];
pradeepvk2208	1:c0c5ac8eac80	3348	__I uint32_t TAGSET; /*< Claim TAG Set Register, offset: 0xFA0 /
pradeepvk2208	1:c0c5ac8eac80	3349	__I uint32_t TAGCLEAR; /*< Claim TAG Clear Register, offset: 0xFA4 /
pradeepvk2208	1:c0c5ac8eac80	3350	uint8_t RESERVED_2[8];
pradeepvk2208	1:c0c5ac8eac80	3351	__I uint32_t LOCKACCESS; /*< Lock Access Register, offset: 0xFB0 /
pradeepvk2208	1:c0c5ac8eac80	3352	__I uint32_t LOCKSTAT; /*< Lock Status Register, offset: 0xFB4 /
pradeepvk2208	1:c0c5ac8eac80	3353	__I uint32_t AUTHSTAT; /*< Authentication Status Register, offset: 0xFB8 /
pradeepvk2208	1:c0c5ac8eac80	3354	__I uint32_t DEVICEARCH; /*< Device Architecture Register, offset: 0xFBC /
pradeepvk2208	1:c0c5ac8eac80	3355	uint8_t RESERVED_3[8];
pradeepvk2208	1:c0c5ac8eac80	3356	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
pradeepvk2208	1:c0c5ac8eac80	3357	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
pradeepvk2208	1:c0c5ac8eac80	3358	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	3359	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	3360	} MTB_Type;
pradeepvk2208	1:c0c5ac8eac80	3361
pradeepvk2208	1:c0c5ac8eac80	3362	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3363	-- MTB Register Masks
pradeepvk2208	1:c0c5ac8eac80	3364	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3365
pradeepvk2208	1:c0c5ac8eac80	3366	/*!
pradeepvk2208	1:c0c5ac8eac80	3367	* @addtogroup MTB_Register_Masks MTB Register Masks
pradeepvk2208	1:c0c5ac8eac80	3368	* @{
pradeepvk2208	1:c0c5ac8eac80	3369	*/
pradeepvk2208	1:c0c5ac8eac80	3370
pradeepvk2208	1:c0c5ac8eac80	3371	/* POSITION Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3372	#define MTB_POSITION_WRAP_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3373	#define MTB_POSITION_WRAP_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3374	#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
pradeepvk2208	1:c0c5ac8eac80	3375	#define MTB_POSITION_POINTER_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	3376	#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
pradeepvk2208	1:c0c5ac8eac80	3377	/* MASTER Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3378	#define MTB_MASTER_MASK_MASK 0x1Fu
pradeepvk2208	1:c0c5ac8eac80	3379	#define MTB_MASTER_MASK_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3380	#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
pradeepvk2208	1:c0c5ac8eac80	3381	#define MTB_MASTER_TSTARTEN_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	3382	#define MTB_MASTER_TSTARTEN_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	3383	#define MTB_MASTER_TSTOPEN_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	3384	#define MTB_MASTER_TSTOPEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3385	#define MTB_MASTER_SFRWPRIV_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	3386	#define MTB_MASTER_SFRWPRIV_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	3387	#define MTB_MASTER_RAMPRIV_MASK 0x100u
pradeepvk2208	1:c0c5ac8eac80	3388	#define MTB_MASTER_RAMPRIV_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	3389	#define MTB_MASTER_HALTREQ_MASK 0x200u
pradeepvk2208	1:c0c5ac8eac80	3390	#define MTB_MASTER_HALTREQ_SHIFT 9
pradeepvk2208	1:c0c5ac8eac80	3391	#define MTB_MASTER_EN_MASK 0x80000000u
pradeepvk2208	1:c0c5ac8eac80	3392	#define MTB_MASTER_EN_SHIFT 31
pradeepvk2208	1:c0c5ac8eac80	3393	/* FLOW Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3394	#define MTB_FLOW_AUTOSTOP_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3395	#define MTB_FLOW_AUTOSTOP_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3396	#define MTB_FLOW_AUTOHALT_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3397	#define MTB_FLOW_AUTOHALT_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3398	#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
pradeepvk2208	1:c0c5ac8eac80	3399	#define MTB_FLOW_WATERMARK_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	3400	#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
pradeepvk2208	1:c0c5ac8eac80	3401	/* BASE Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3402	#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3403	#define MTB_BASE_BASEADDR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3404	#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
pradeepvk2208	1:c0c5ac8eac80	3405	/* MODECTRL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3406	#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3407	#define MTB_MODECTRL_MODECTRL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3408	#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
pradeepvk2208	1:c0c5ac8eac80	3409	/* TAGSET Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3410	#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3411	#define MTB_TAGSET_TAGSET_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3412	#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
pradeepvk2208	1:c0c5ac8eac80	3413	/* TAGCLEAR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3414	#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3415	#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3416	#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
pradeepvk2208	1:c0c5ac8eac80	3417	/* LOCKACCESS Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3418	#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3419	#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3420	#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
pradeepvk2208	1:c0c5ac8eac80	3421	/* LOCKSTAT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3422	#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3423	#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3424	#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
pradeepvk2208	1:c0c5ac8eac80	3425	/* AUTHSTAT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3426	#define MTB_AUTHSTAT_BIT0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3427	#define MTB_AUTHSTAT_BIT0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3428	#define MTB_AUTHSTAT_BIT1_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3429	#define MTB_AUTHSTAT_BIT1_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3430	#define MTB_AUTHSTAT_BIT2_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3431	#define MTB_AUTHSTAT_BIT2_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3432	#define MTB_AUTHSTAT_BIT3_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	3433	#define MTB_AUTHSTAT_BIT3_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	3434	/* DEVICEARCH Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3435	#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3436	#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3437	#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
pradeepvk2208	1:c0c5ac8eac80	3438	/* DEVICECFG Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3439	#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3440	#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3441	#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
pradeepvk2208	1:c0c5ac8eac80	3442	/* DEVICETYPID Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3443	#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3444	#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3445	#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
pradeepvk2208	1:c0c5ac8eac80	3446	/* PERIPHID Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3447	#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3448	#define MTB_PERIPHID_PERIPHID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3449	#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
pradeepvk2208	1:c0c5ac8eac80	3450	/* COMPID Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3451	#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3452	#define MTB_COMPID_COMPID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3453	#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
pradeepvk2208	1:c0c5ac8eac80	3454
pradeepvk2208	1:c0c5ac8eac80	3455	/*!
pradeepvk2208	1:c0c5ac8eac80	3456	* @}
pradeepvk2208	1:c0c5ac8eac80	3457	/ / end of group MTB_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	3458
pradeepvk2208	1:c0c5ac8eac80	3459
pradeepvk2208	1:c0c5ac8eac80	3460	/* MTB - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	3461	/** Peripheral MTB base address */
pradeepvk2208	1:c0c5ac8eac80	3462	#define MTB_BASE (0xF0000000u)
pradeepvk2208	1:c0c5ac8eac80	3463	/** Peripheral MTB base pointer */
pradeepvk2208	1:c0c5ac8eac80	3464	#define MTB ((MTB_Type *)MTB_BASE)
pradeepvk2208	1:c0c5ac8eac80	3465	/** Array initializer of MTB peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	3466	#define MTB_BASES { MTB }
pradeepvk2208	1:c0c5ac8eac80	3467
pradeepvk2208	1:c0c5ac8eac80	3468	/*!
pradeepvk2208	1:c0c5ac8eac80	3469	* @}
pradeepvk2208	1:c0c5ac8eac80	3470	/ / end of group MTB_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	3471
pradeepvk2208	1:c0c5ac8eac80	3472
pradeepvk2208	1:c0c5ac8eac80	3473	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3474	-- MTBDWT Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3475	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3476
pradeepvk2208	1:c0c5ac8eac80	3477	/*!
pradeepvk2208	1:c0c5ac8eac80	3478	* @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3479	* @{
pradeepvk2208	1:c0c5ac8eac80	3480	*/
pradeepvk2208	1:c0c5ac8eac80	3481
pradeepvk2208	1:c0c5ac8eac80	3482	/** MTBDWT - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	3483	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	3484	__I uint32_t CTRL; /*< MTB DWT Control Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	3485	uint8_t RESERVED_0[28];
pradeepvk2208	1:c0c5ac8eac80	3486	struct { /* offset: 0x20, array step: 0x10 */
pradeepvk2208	1:c0c5ac8eac80	3487	__IO uint32_t COMP; /*< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	3488	__IO uint32_t MASK; /*< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	3489	__IO uint32_t FCT; /*< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	3490	uint8_t RESERVED_0[4];
pradeepvk2208	1:c0c5ac8eac80	3491	} COMPARATOR[2];
pradeepvk2208	1:c0c5ac8eac80	3492	uint8_t RESERVED_1[448];
pradeepvk2208	1:c0c5ac8eac80	3493	__IO uint32_t TBCTRL; /*< MTB_DWT Trace Buffer Control Register, offset: 0x200 /
pradeepvk2208	1:c0c5ac8eac80	3494	uint8_t RESERVED_2[3524];
pradeepvk2208	1:c0c5ac8eac80	3495	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
pradeepvk2208	1:c0c5ac8eac80	3496	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
pradeepvk2208	1:c0c5ac8eac80	3497	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	3498	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	3499	} MTBDWT_Type;
pradeepvk2208	1:c0c5ac8eac80	3500
pradeepvk2208	1:c0c5ac8eac80	3501	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3502	-- MTBDWT Register Masks
pradeepvk2208	1:c0c5ac8eac80	3503	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3504
pradeepvk2208	1:c0c5ac8eac80	3505	/*!
pradeepvk2208	1:c0c5ac8eac80	3506	* @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
pradeepvk2208	1:c0c5ac8eac80	3507	* @{
pradeepvk2208	1:c0c5ac8eac80	3508	*/
pradeepvk2208	1:c0c5ac8eac80	3509
pradeepvk2208	1:c0c5ac8eac80	3510	/* CTRL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3511	#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3512	#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3513	#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
pradeepvk2208	1:c0c5ac8eac80	3514	#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
pradeepvk2208	1:c0c5ac8eac80	3515	#define MTBDWT_CTRL_NUMCMP_SHIFT 28
pradeepvk2208	1:c0c5ac8eac80	3516	#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
pradeepvk2208	1:c0c5ac8eac80	3517	/* COMP Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3518	#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3519	#define MTBDWT_COMP_COMP_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3520	#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
pradeepvk2208	1:c0c5ac8eac80	3521	/* MASK Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3522	#define MTBDWT_MASK_MASK_MASK 0x1Fu
pradeepvk2208	1:c0c5ac8eac80	3523	#define MTBDWT_MASK_MASK_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3524	#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
pradeepvk2208	1:c0c5ac8eac80	3525	/* FCT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3526	#define MTBDWT_FCT_FUNCTION_MASK 0xFu
pradeepvk2208	1:c0c5ac8eac80	3527	#define MTBDWT_FCT_FUNCTION_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3528	#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
pradeepvk2208	1:c0c5ac8eac80	3529	#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
pradeepvk2208	1:c0c5ac8eac80	3530	#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	3531	#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
pradeepvk2208	1:c0c5ac8eac80	3532	#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
pradeepvk2208	1:c0c5ac8eac80	3533	#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
pradeepvk2208	1:c0c5ac8eac80	3534	#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
pradeepvk2208	1:c0c5ac8eac80	3535	#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	3536	#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
pradeepvk2208	1:c0c5ac8eac80	3537	#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
pradeepvk2208	1:c0c5ac8eac80	3538	#define MTBDWT_FCT_MATCHED_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	3539	/* TBCTRL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3540	#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3541	#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3542	#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3543	#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3544	#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
pradeepvk2208	1:c0c5ac8eac80	3545	#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
pradeepvk2208	1:c0c5ac8eac80	3546	#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
pradeepvk2208	1:c0c5ac8eac80	3547	/* DEVICECFG Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3548	#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3549	#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3550	#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
pradeepvk2208	1:c0c5ac8eac80	3551	/* DEVICETYPID Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3552	#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3553	#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3554	#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
pradeepvk2208	1:c0c5ac8eac80	3555	/* PERIPHID Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3556	#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3557	#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3558	#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
pradeepvk2208	1:c0c5ac8eac80	3559	/* COMPID Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3560	#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3561	#define MTBDWT_COMPID_COMPID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3562	#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
pradeepvk2208	1:c0c5ac8eac80	3563
pradeepvk2208	1:c0c5ac8eac80	3564	/*!
pradeepvk2208	1:c0c5ac8eac80	3565	* @}
pradeepvk2208	1:c0c5ac8eac80	3566	/ / end of group MTBDWT_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	3567
pradeepvk2208	1:c0c5ac8eac80	3568
pradeepvk2208	1:c0c5ac8eac80	3569	/* MTBDWT - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	3570	/** Peripheral MTBDWT base address */
pradeepvk2208	1:c0c5ac8eac80	3571	#define MTBDWT_BASE (0xF0001000u)
pradeepvk2208	1:c0c5ac8eac80	3572	/** Peripheral MTBDWT base pointer */
pradeepvk2208	1:c0c5ac8eac80	3573	#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
pradeepvk2208	1:c0c5ac8eac80	3574	/** Array initializer of MTBDWT peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	3575	#define MTBDWT_BASES { MTBDWT }
pradeepvk2208	1:c0c5ac8eac80	3576
pradeepvk2208	1:c0c5ac8eac80	3577	/*!
pradeepvk2208	1:c0c5ac8eac80	3578	* @}
pradeepvk2208	1:c0c5ac8eac80	3579	/ / end of group MTBDWT_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	3580
pradeepvk2208	1:c0c5ac8eac80	3581
pradeepvk2208	1:c0c5ac8eac80	3582	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3583	-- NV Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3584	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3585
pradeepvk2208	1:c0c5ac8eac80	3586	/*!
pradeepvk2208	1:c0c5ac8eac80	3587	* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3588	* @{
pradeepvk2208	1:c0c5ac8eac80	3589	*/
pradeepvk2208	1:c0c5ac8eac80	3590
pradeepvk2208	1:c0c5ac8eac80	3591	/** NV - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	3592	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	3593	__I uint8_t BACKKEY3; /*< Backdoor Comparison Key 3., offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	3594	__I uint8_t BACKKEY2; /*< Backdoor Comparison Key 2., offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	3595	__I uint8_t BACKKEY1; /*< Backdoor Comparison Key 1., offset: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	3596	__I uint8_t BACKKEY0; /*< Backdoor Comparison Key 0., offset: 0x3 /
pradeepvk2208	1:c0c5ac8eac80	3597	__I uint8_t BACKKEY7; /*< Backdoor Comparison Key 7., offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	3598	__I uint8_t BACKKEY6; /*< Backdoor Comparison Key 6., offset: 0x5 /
pradeepvk2208	1:c0c5ac8eac80	3599	__I uint8_t BACKKEY5; /*< Backdoor Comparison Key 5., offset: 0x6 /
pradeepvk2208	1:c0c5ac8eac80	3600	__I uint8_t BACKKEY4; /*< Backdoor Comparison Key 4., offset: 0x7 /
pradeepvk2208	1:c0c5ac8eac80	3601	__I uint8_t FPROT3; /*< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	3602	__I uint8_t FPROT2; /*< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 /
pradeepvk2208	1:c0c5ac8eac80	3603	__I uint8_t FPROT1; /*< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA /
pradeepvk2208	1:c0c5ac8eac80	3604	__I uint8_t FPROT0; /*< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB /
pradeepvk2208	1:c0c5ac8eac80	3605	__I uint8_t FSEC; /*< Non-volatile Flash Security Register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	3606	__I uint8_t FOPT; /*< Non-volatile Flash Option Register, offset: 0xD /
pradeepvk2208	1:c0c5ac8eac80	3607	} NV_Type;
pradeepvk2208	1:c0c5ac8eac80	3608
pradeepvk2208	1:c0c5ac8eac80	3609	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3610	-- NV Register Masks
pradeepvk2208	1:c0c5ac8eac80	3611	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3612
pradeepvk2208	1:c0c5ac8eac80	3613	/*!
pradeepvk2208	1:c0c5ac8eac80	3614	* @addtogroup NV_Register_Masks NV Register Masks
pradeepvk2208	1:c0c5ac8eac80	3615	* @{
pradeepvk2208	1:c0c5ac8eac80	3616	*/
pradeepvk2208	1:c0c5ac8eac80	3617
pradeepvk2208	1:c0c5ac8eac80	3618	/* BACKKEY3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3619	#define NV_BACKKEY3_KEY_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3620	#define NV_BACKKEY3_KEY_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3621	#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
pradeepvk2208	1:c0c5ac8eac80	3622	/* BACKKEY2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3623	#define NV_BACKKEY2_KEY_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3624	#define NV_BACKKEY2_KEY_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3625	#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
pradeepvk2208	1:c0c5ac8eac80	3626	/* BACKKEY1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3627	#define NV_BACKKEY1_KEY_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3628	#define NV_BACKKEY1_KEY_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3629	#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
pradeepvk2208	1:c0c5ac8eac80	3630	/* BACKKEY0 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3631	#define NV_BACKKEY0_KEY_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3632	#define NV_BACKKEY0_KEY_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3633	#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
pradeepvk2208	1:c0c5ac8eac80	3634	/* BACKKEY7 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3635	#define NV_BACKKEY7_KEY_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3636	#define NV_BACKKEY7_KEY_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3637	#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
pradeepvk2208	1:c0c5ac8eac80	3638	/* BACKKEY6 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3639	#define NV_BACKKEY6_KEY_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3640	#define NV_BACKKEY6_KEY_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3641	#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
pradeepvk2208	1:c0c5ac8eac80	3642	/* BACKKEY5 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3643	#define NV_BACKKEY5_KEY_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3644	#define NV_BACKKEY5_KEY_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3645	#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
pradeepvk2208	1:c0c5ac8eac80	3646	/* BACKKEY4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3647	#define NV_BACKKEY4_KEY_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3648	#define NV_BACKKEY4_KEY_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3649	#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
pradeepvk2208	1:c0c5ac8eac80	3650	/* FPROT3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3651	#define NV_FPROT3_PROT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3652	#define NV_FPROT3_PROT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3653	#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
pradeepvk2208	1:c0c5ac8eac80	3654	/* FPROT2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3655	#define NV_FPROT2_PROT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3656	#define NV_FPROT2_PROT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3657	#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
pradeepvk2208	1:c0c5ac8eac80	3658	/* FPROT1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3659	#define NV_FPROT1_PROT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3660	#define NV_FPROT1_PROT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3661	#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
pradeepvk2208	1:c0c5ac8eac80	3662	/* FPROT0 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3663	#define NV_FPROT0_PROT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	3664	#define NV_FPROT0_PROT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3665	#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
pradeepvk2208	1:c0c5ac8eac80	3666	/* FSEC Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3667	#define NV_FSEC_SEC_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	3668	#define NV_FSEC_SEC_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3669	#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
pradeepvk2208	1:c0c5ac8eac80	3670	#define NV_FSEC_FSLACC_MASK 0xCu
pradeepvk2208	1:c0c5ac8eac80	3671	#define NV_FSEC_FSLACC_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3672	#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
pradeepvk2208	1:c0c5ac8eac80	3673	#define NV_FSEC_MEEN_MASK 0x30u
pradeepvk2208	1:c0c5ac8eac80	3674	#define NV_FSEC_MEEN_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	3675	#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
pradeepvk2208	1:c0c5ac8eac80	3676	#define NV_FSEC_KEYEN_MASK 0xC0u
pradeepvk2208	1:c0c5ac8eac80	3677	#define NV_FSEC_KEYEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3678	#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
pradeepvk2208	1:c0c5ac8eac80	3679	/* FOPT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3680	#define NV_FOPT_LPBOOT0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3681	#define NV_FOPT_LPBOOT0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3682	#define NV_FOPT_NMI_DIS_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3683	#define NV_FOPT_NMI_DIS_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3684	#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	3685	#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	3686	#define NV_FOPT_LPBOOT1_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	3687	#define NV_FOPT_LPBOOT1_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	3688	#define NV_FOPT_FAST_INIT_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	3689	#define NV_FOPT_FAST_INIT_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	3690
pradeepvk2208	1:c0c5ac8eac80	3691	/*!
pradeepvk2208	1:c0c5ac8eac80	3692	* @}
pradeepvk2208	1:c0c5ac8eac80	3693	/ / end of group NV_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	3694
pradeepvk2208	1:c0c5ac8eac80	3695
pradeepvk2208	1:c0c5ac8eac80	3696	/* NV - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	3697	/** Peripheral FTFA_FlashConfig base address */
pradeepvk2208	1:c0c5ac8eac80	3698	#define FTFA_FlashConfig_BASE (0x400u)
pradeepvk2208	1:c0c5ac8eac80	3699	/** Peripheral FTFA_FlashConfig base pointer */
pradeepvk2208	1:c0c5ac8eac80	3700	#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
pradeepvk2208	1:c0c5ac8eac80	3701	/** Array initializer of NV peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	3702	#define NV_BASES { FTFA_FlashConfig }
pradeepvk2208	1:c0c5ac8eac80	3703
pradeepvk2208	1:c0c5ac8eac80	3704	/*!
pradeepvk2208	1:c0c5ac8eac80	3705	* @}
pradeepvk2208	1:c0c5ac8eac80	3706	/ / end of group NV_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	3707
pradeepvk2208	1:c0c5ac8eac80	3708
pradeepvk2208	1:c0c5ac8eac80	3709	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3710	-- OSC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3711	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3712
pradeepvk2208	1:c0c5ac8eac80	3713	/*!
pradeepvk2208	1:c0c5ac8eac80	3714	* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3715	* @{
pradeepvk2208	1:c0c5ac8eac80	3716	*/
pradeepvk2208	1:c0c5ac8eac80	3717
pradeepvk2208	1:c0c5ac8eac80	3718	/** OSC - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	3719	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	3720	__IO uint8_t CR; /*< OSC Control Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	3721	} OSC_Type;
pradeepvk2208	1:c0c5ac8eac80	3722
pradeepvk2208	1:c0c5ac8eac80	3723	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3724	-- OSC Register Masks
pradeepvk2208	1:c0c5ac8eac80	3725	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3726
pradeepvk2208	1:c0c5ac8eac80	3727	/*!
pradeepvk2208	1:c0c5ac8eac80	3728	* @addtogroup OSC_Register_Masks OSC Register Masks
pradeepvk2208	1:c0c5ac8eac80	3729	* @{
pradeepvk2208	1:c0c5ac8eac80	3730	*/
pradeepvk2208	1:c0c5ac8eac80	3731
pradeepvk2208	1:c0c5ac8eac80	3732	/* CR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3733	#define OSC_CR_SC16P_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3734	#define OSC_CR_SC16P_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3735	#define OSC_CR_SC8P_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3736	#define OSC_CR_SC8P_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3737	#define OSC_CR_SC4P_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3738	#define OSC_CR_SC4P_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3739	#define OSC_CR_SC2P_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	3740	#define OSC_CR_SC2P_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	3741	#define OSC_CR_EREFSTEN_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	3742	#define OSC_CR_EREFSTEN_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	3743	#define OSC_CR_ERCLKEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	3744	#define OSC_CR_ERCLKEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	3745
pradeepvk2208	1:c0c5ac8eac80	3746	/*!
pradeepvk2208	1:c0c5ac8eac80	3747	* @}
pradeepvk2208	1:c0c5ac8eac80	3748	/ / end of group OSC_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	3749
pradeepvk2208	1:c0c5ac8eac80	3750
pradeepvk2208	1:c0c5ac8eac80	3751	/* OSC - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	3752	/** Peripheral OSC0 base address */
pradeepvk2208	1:c0c5ac8eac80	3753	#define OSC0_BASE (0x40065000u)
pradeepvk2208	1:c0c5ac8eac80	3754	/** Peripheral OSC0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	3755	#define OSC0 ((OSC_Type *)OSC0_BASE)
pradeepvk2208	1:c0c5ac8eac80	3756	/** Array initializer of OSC peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	3757	#define OSC_BASES { OSC0 }
pradeepvk2208	1:c0c5ac8eac80	3758
pradeepvk2208	1:c0c5ac8eac80	3759	/*!
pradeepvk2208	1:c0c5ac8eac80	3760	* @}
pradeepvk2208	1:c0c5ac8eac80	3761	/ / end of group OSC_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	3762
pradeepvk2208	1:c0c5ac8eac80	3763
pradeepvk2208	1:c0c5ac8eac80	3764	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3765	-- PIT Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3766	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3767
pradeepvk2208	1:c0c5ac8eac80	3768	/*!
pradeepvk2208	1:c0c5ac8eac80	3769	* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3770	* @{
pradeepvk2208	1:c0c5ac8eac80	3771	*/
pradeepvk2208	1:c0c5ac8eac80	3772
pradeepvk2208	1:c0c5ac8eac80	3773	/** PIT - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	3774	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	3775	__IO uint32_t MCR; /*< PIT Module Control Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	3776	uint8_t RESERVED_0[220];
pradeepvk2208	1:c0c5ac8eac80	3777	__I uint32_t LTMR64H; /*< PIT Upper Lifetime Timer Register, offset: 0xE0 /
pradeepvk2208	1:c0c5ac8eac80	3778	__I uint32_t LTMR64L; /*< PIT Lower Lifetime Timer Register, offset: 0xE4 /
pradeepvk2208	1:c0c5ac8eac80	3779	uint8_t RESERVED_1[24];
pradeepvk2208	1:c0c5ac8eac80	3780	struct { /* offset: 0x100, array step: 0x10 */
pradeepvk2208	1:c0c5ac8eac80	3781	__IO uint32_t LDVAL; /*< Timer Load Value Register, array offset: 0x100, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	3782	__I uint32_t CVAL; /*< Current Timer Value Register, array offset: 0x104, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	3783	__IO uint32_t TCTRL; /*< Timer Control Register, array offset: 0x108, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	3784	__IO uint32_t TFLG; /*< Timer Flag Register, array offset: 0x10C, array step: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	3785	} CHANNEL[2];
pradeepvk2208	1:c0c5ac8eac80	3786	} PIT_Type;
pradeepvk2208	1:c0c5ac8eac80	3787
pradeepvk2208	1:c0c5ac8eac80	3788	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3789	-- PIT Register Masks
pradeepvk2208	1:c0c5ac8eac80	3790	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3791
pradeepvk2208	1:c0c5ac8eac80	3792	/*!
pradeepvk2208	1:c0c5ac8eac80	3793	* @addtogroup PIT_Register_Masks PIT Register Masks
pradeepvk2208	1:c0c5ac8eac80	3794	* @{
pradeepvk2208	1:c0c5ac8eac80	3795	*/
pradeepvk2208	1:c0c5ac8eac80	3796
pradeepvk2208	1:c0c5ac8eac80	3797	/* MCR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3798	#define PIT_MCR_FRZ_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3799	#define PIT_MCR_FRZ_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3800	#define PIT_MCR_MDIS_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3801	#define PIT_MCR_MDIS_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3802	/* LTMR64H Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3803	#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3804	#define PIT_LTMR64H_LTH_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3805	#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
pradeepvk2208	1:c0c5ac8eac80	3806	/* LTMR64L Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3807	#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3808	#define PIT_LTMR64L_LTL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3809	#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
pradeepvk2208	1:c0c5ac8eac80	3810	/* LDVAL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3811	#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3812	#define PIT_LDVAL_TSV_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3813	#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
pradeepvk2208	1:c0c5ac8eac80	3814	/* CVAL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3815	#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3816	#define PIT_CVAL_TVL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3817	#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
pradeepvk2208	1:c0c5ac8eac80	3818	/* TCTRL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3819	#define PIT_TCTRL_TEN_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3820	#define PIT_TCTRL_TEN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3821	#define PIT_TCTRL_TIE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3822	#define PIT_TCTRL_TIE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3823	#define PIT_TCTRL_CHN_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3824	#define PIT_TCTRL_CHN_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3825	/* TFLG Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3826	#define PIT_TFLG_TIF_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3827	#define PIT_TFLG_TIF_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3828
pradeepvk2208	1:c0c5ac8eac80	3829	/*!
pradeepvk2208	1:c0c5ac8eac80	3830	* @}
pradeepvk2208	1:c0c5ac8eac80	3831	/ / end of group PIT_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	3832
pradeepvk2208	1:c0c5ac8eac80	3833
pradeepvk2208	1:c0c5ac8eac80	3834	/* PIT - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	3835	/** Peripheral PIT base address */
pradeepvk2208	1:c0c5ac8eac80	3836	#define PIT_BASE (0x40037000u)
pradeepvk2208	1:c0c5ac8eac80	3837	/** Peripheral PIT base pointer */
pradeepvk2208	1:c0c5ac8eac80	3838	#define PIT ((PIT_Type *)PIT_BASE)
pradeepvk2208	1:c0c5ac8eac80	3839	/** Array initializer of PIT peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	3840	#define PIT_BASES { PIT }
pradeepvk2208	1:c0c5ac8eac80	3841
pradeepvk2208	1:c0c5ac8eac80	3842	/*!
pradeepvk2208	1:c0c5ac8eac80	3843	* @}
pradeepvk2208	1:c0c5ac8eac80	3844	/ / end of group PIT_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	3845
pradeepvk2208	1:c0c5ac8eac80	3846
pradeepvk2208	1:c0c5ac8eac80	3847	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3848	-- PMC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3849	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3850
pradeepvk2208	1:c0c5ac8eac80	3851	/*!
pradeepvk2208	1:c0c5ac8eac80	3852	* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3853	* @{
pradeepvk2208	1:c0c5ac8eac80	3854	*/
pradeepvk2208	1:c0c5ac8eac80	3855
pradeepvk2208	1:c0c5ac8eac80	3856	/** PMC - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	3857	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	3858	__IO uint8_t LVDSC1; /*< Low Voltage Detect Status And Control 1 register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	3859	__IO uint8_t LVDSC2; /*< Low Voltage Detect Status And Control 2 register, offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	3860	__IO uint8_t REGSC; /*< Regulator Status And Control register, offset: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	3861	} PMC_Type;
pradeepvk2208	1:c0c5ac8eac80	3862
pradeepvk2208	1:c0c5ac8eac80	3863	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3864	-- PMC Register Masks
pradeepvk2208	1:c0c5ac8eac80	3865	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3866
pradeepvk2208	1:c0c5ac8eac80	3867	/*!
pradeepvk2208	1:c0c5ac8eac80	3868	* @addtogroup PMC_Register_Masks PMC Register Masks
pradeepvk2208	1:c0c5ac8eac80	3869	* @{
pradeepvk2208	1:c0c5ac8eac80	3870	*/
pradeepvk2208	1:c0c5ac8eac80	3871
pradeepvk2208	1:c0c5ac8eac80	3872	/* LVDSC1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3873	#define PMC_LVDSC1_LVDV_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	3874	#define PMC_LVDSC1_LVDV_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3875	#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
pradeepvk2208	1:c0c5ac8eac80	3876	#define PMC_LVDSC1_LVDRE_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	3877	#define PMC_LVDSC1_LVDRE_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	3878	#define PMC_LVDSC1_LVDIE_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	3879	#define PMC_LVDSC1_LVDIE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	3880	#define PMC_LVDSC1_LVDACK_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	3881	#define PMC_LVDSC1_LVDACK_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3882	#define PMC_LVDSC1_LVDF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	3883	#define PMC_LVDSC1_LVDF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	3884	/* LVDSC2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3885	#define PMC_LVDSC2_LVWV_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	3886	#define PMC_LVDSC2_LVWV_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3887	#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
pradeepvk2208	1:c0c5ac8eac80	3888	#define PMC_LVDSC2_LVWIE_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	3889	#define PMC_LVDSC2_LVWIE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	3890	#define PMC_LVDSC2_LVWACK_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	3891	#define PMC_LVDSC2_LVWACK_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3892	#define PMC_LVDSC2_LVWF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	3893	#define PMC_LVDSC2_LVWF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	3894	/* REGSC Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3895	#define PMC_REGSC_BGBE_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3896	#define PMC_REGSC_BGBE_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3897	#define PMC_REGSC_REGONS_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3898	#define PMC_REGSC_REGONS_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3899	#define PMC_REGSC_ACKISO_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	3900	#define PMC_REGSC_ACKISO_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	3901	#define PMC_REGSC_BGEN_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	3902	#define PMC_REGSC_BGEN_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	3903
pradeepvk2208	1:c0c5ac8eac80	3904	/*!
pradeepvk2208	1:c0c5ac8eac80	3905	* @}
pradeepvk2208	1:c0c5ac8eac80	3906	/ / end of group PMC_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	3907
pradeepvk2208	1:c0c5ac8eac80	3908
pradeepvk2208	1:c0c5ac8eac80	3909	/* PMC - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	3910	/** Peripheral PMC base address */
pradeepvk2208	1:c0c5ac8eac80	3911	#define PMC_BASE (0x4007D000u)
pradeepvk2208	1:c0c5ac8eac80	3912	/** Peripheral PMC base pointer */
pradeepvk2208	1:c0c5ac8eac80	3913	#define PMC ((PMC_Type *)PMC_BASE)
pradeepvk2208	1:c0c5ac8eac80	3914	/** Array initializer of PMC peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	3915	#define PMC_BASES { PMC }
pradeepvk2208	1:c0c5ac8eac80	3916
pradeepvk2208	1:c0c5ac8eac80	3917	/*!
pradeepvk2208	1:c0c5ac8eac80	3918	* @}
pradeepvk2208	1:c0c5ac8eac80	3919	/ / end of group PMC_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	3920
pradeepvk2208	1:c0c5ac8eac80	3921
pradeepvk2208	1:c0c5ac8eac80	3922	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3923	-- PORT Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3924	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3925
pradeepvk2208	1:c0c5ac8eac80	3926	/*!
pradeepvk2208	1:c0c5ac8eac80	3927	* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	3928	* @{
pradeepvk2208	1:c0c5ac8eac80	3929	*/
pradeepvk2208	1:c0c5ac8eac80	3930
pradeepvk2208	1:c0c5ac8eac80	3931	/** PORT - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	3932	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	3933	__IO uint32_t PCR[32]; /*< Pin Control Register n, array offset: 0x0, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	3934	__O uint32_t GPCLR; /*< Global Pin Control Low Register, offset: 0x80 /
pradeepvk2208	1:c0c5ac8eac80	3935	__O uint32_t GPCHR; /*< Global Pin Control High Register, offset: 0x84 /
pradeepvk2208	1:c0c5ac8eac80	3936	uint8_t RESERVED_0[24];
pradeepvk2208	1:c0c5ac8eac80	3937	__IO uint32_t ISFR; /*< Interrupt Status Flag Register, offset: 0xA0 /
pradeepvk2208	1:c0c5ac8eac80	3938	} PORT_Type;
pradeepvk2208	1:c0c5ac8eac80	3939
pradeepvk2208	1:c0c5ac8eac80	3940	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	3941	-- PORT Register Masks
pradeepvk2208	1:c0c5ac8eac80	3942	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	3943
pradeepvk2208	1:c0c5ac8eac80	3944	/*!
pradeepvk2208	1:c0c5ac8eac80	3945	* @addtogroup PORT_Register_Masks PORT Register Masks
pradeepvk2208	1:c0c5ac8eac80	3946	* @{
pradeepvk2208	1:c0c5ac8eac80	3947	*/
pradeepvk2208	1:c0c5ac8eac80	3948
pradeepvk2208	1:c0c5ac8eac80	3949	/* PCR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3950	#define PORT_PCR_PS_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	3951	#define PORT_PCR_PS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3952	#define PORT_PCR_PE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	3953	#define PORT_PCR_PE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	3954	#define PORT_PCR_SRE_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	3955	#define PORT_PCR_SRE_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	3956	#define PORT_PCR_PFE_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	3957	#define PORT_PCR_PFE_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	3958	#define PORT_PCR_DSE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	3959	#define PORT_PCR_DSE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	3960	#define PORT_PCR_MUX_MASK 0x700u
pradeepvk2208	1:c0c5ac8eac80	3961	#define PORT_PCR_MUX_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	3962	#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
pradeepvk2208	1:c0c5ac8eac80	3963	#define PORT_PCR_IRQC_MASK 0xF0000u
pradeepvk2208	1:c0c5ac8eac80	3964	#define PORT_PCR_IRQC_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	3965	#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
pradeepvk2208	1:c0c5ac8eac80	3966	#define PORT_PCR_ISF_MASK 0x1000000u
pradeepvk2208	1:c0c5ac8eac80	3967	#define PORT_PCR_ISF_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	3968	/* GPCLR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3969	#define PORT_GPCLR_GPWD_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	3970	#define PORT_GPCLR_GPWD_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3971	#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
pradeepvk2208	1:c0c5ac8eac80	3972	#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
pradeepvk2208	1:c0c5ac8eac80	3973	#define PORT_GPCLR_GPWE_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	3974	#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
pradeepvk2208	1:c0c5ac8eac80	3975	/* GPCHR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3976	#define PORT_GPCHR_GPWD_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	3977	#define PORT_GPCHR_GPWD_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3978	#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
pradeepvk2208	1:c0c5ac8eac80	3979	#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
pradeepvk2208	1:c0c5ac8eac80	3980	#define PORT_GPCHR_GPWE_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	3981	#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
pradeepvk2208	1:c0c5ac8eac80	3982	/* ISFR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	3983	#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	3984	#define PORT_ISFR_ISF_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	3985	#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
pradeepvk2208	1:c0c5ac8eac80	3986
pradeepvk2208	1:c0c5ac8eac80	3987	/*!
pradeepvk2208	1:c0c5ac8eac80	3988	* @}
pradeepvk2208	1:c0c5ac8eac80	3989	/ / end of group PORT_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	3990
pradeepvk2208	1:c0c5ac8eac80	3991
pradeepvk2208	1:c0c5ac8eac80	3992	/* PORT - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	3993	/** Peripheral PORTA base address */
pradeepvk2208	1:c0c5ac8eac80	3994	#define PORTA_BASE (0x40049000u)
pradeepvk2208	1:c0c5ac8eac80	3995	/** Peripheral PORTA base pointer */
pradeepvk2208	1:c0c5ac8eac80	3996	#define PORTA ((PORT_Type *)PORTA_BASE)
pradeepvk2208	1:c0c5ac8eac80	3997	/** Peripheral PORTB base address */
pradeepvk2208	1:c0c5ac8eac80	3998	#define PORTB_BASE (0x4004A000u)
pradeepvk2208	1:c0c5ac8eac80	3999	/** Peripheral PORTB base pointer */
pradeepvk2208	1:c0c5ac8eac80	4000	#define PORTB ((PORT_Type *)PORTB_BASE)
pradeepvk2208	1:c0c5ac8eac80	4001	/** Peripheral PORTC base address */
pradeepvk2208	1:c0c5ac8eac80	4002	#define PORTC_BASE (0x4004B000u)
pradeepvk2208	1:c0c5ac8eac80	4003	/** Peripheral PORTC base pointer */
pradeepvk2208	1:c0c5ac8eac80	4004	#define PORTC ((PORT_Type *)PORTC_BASE)
pradeepvk2208	1:c0c5ac8eac80	4005	/** Peripheral PORTD base address */
pradeepvk2208	1:c0c5ac8eac80	4006	#define PORTD_BASE (0x4004C000u)
pradeepvk2208	1:c0c5ac8eac80	4007	/** Peripheral PORTD base pointer */
pradeepvk2208	1:c0c5ac8eac80	4008	#define PORTD ((PORT_Type *)PORTD_BASE)
pradeepvk2208	1:c0c5ac8eac80	4009	/** Peripheral PORTE base address */
pradeepvk2208	1:c0c5ac8eac80	4010	#define PORTE_BASE (0x4004D000u)
pradeepvk2208	1:c0c5ac8eac80	4011	/** Peripheral PORTE base pointer */
pradeepvk2208	1:c0c5ac8eac80	4012	#define PORTE ((PORT_Type *)PORTE_BASE)
pradeepvk2208	1:c0c5ac8eac80	4013	/** Array initializer of PORT peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	4014	#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
pradeepvk2208	1:c0c5ac8eac80	4015
pradeepvk2208	1:c0c5ac8eac80	4016	/*!
pradeepvk2208	1:c0c5ac8eac80	4017	* @}
pradeepvk2208	1:c0c5ac8eac80	4018	/ / end of group PORT_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	4019
pradeepvk2208	1:c0c5ac8eac80	4020
pradeepvk2208	1:c0c5ac8eac80	4021	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4022	-- RCM Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4023	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4024
pradeepvk2208	1:c0c5ac8eac80	4025	/*!
pradeepvk2208	1:c0c5ac8eac80	4026	* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4027	* @{
pradeepvk2208	1:c0c5ac8eac80	4028	*/
pradeepvk2208	1:c0c5ac8eac80	4029
pradeepvk2208	1:c0c5ac8eac80	4030	/** RCM - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	4031	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	4032	__I uint8_t SRS0; /*< System Reset Status Register 0, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	4033	__I uint8_t SRS1; /*< System Reset Status Register 1, offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	4034	uint8_t RESERVED_0[2];
pradeepvk2208	1:c0c5ac8eac80	4035	__IO uint8_t RPFC; /*< Reset Pin Filter Control register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	4036	__IO uint8_t RPFW; /*< Reset Pin Filter Width register, offset: 0x5 /
pradeepvk2208	1:c0c5ac8eac80	4037	} RCM_Type;
pradeepvk2208	1:c0c5ac8eac80	4038
pradeepvk2208	1:c0c5ac8eac80	4039	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4040	-- RCM Register Masks
pradeepvk2208	1:c0c5ac8eac80	4041	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4042
pradeepvk2208	1:c0c5ac8eac80	4043	/*!
pradeepvk2208	1:c0c5ac8eac80	4044	* @addtogroup RCM_Register_Masks RCM Register Masks
pradeepvk2208	1:c0c5ac8eac80	4045	* @{
pradeepvk2208	1:c0c5ac8eac80	4046	*/
pradeepvk2208	1:c0c5ac8eac80	4047
pradeepvk2208	1:c0c5ac8eac80	4048	/* SRS0 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4049	#define RCM_SRS0_WAKEUP_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4050	#define RCM_SRS0_WAKEUP_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4051	#define RCM_SRS0_LVD_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4052	#define RCM_SRS0_LVD_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4053	#define RCM_SRS0_LOC_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4054	#define RCM_SRS0_LOC_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4055	#define RCM_SRS0_LOL_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4056	#define RCM_SRS0_LOL_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4057	#define RCM_SRS0_WDOG_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4058	#define RCM_SRS0_WDOG_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4059	#define RCM_SRS0_PIN_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	4060	#define RCM_SRS0_PIN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4061	#define RCM_SRS0_POR_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	4062	#define RCM_SRS0_POR_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	4063	/* SRS1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4064	#define RCM_SRS1_LOCKUP_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4065	#define RCM_SRS1_LOCKUP_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4066	#define RCM_SRS1_SW_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4067	#define RCM_SRS1_SW_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4068	#define RCM_SRS1_MDM_AP_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4069	#define RCM_SRS1_MDM_AP_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4070	#define RCM_SRS1_SACKERR_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4071	#define RCM_SRS1_SACKERR_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4072	/* RPFC Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4073	#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	4074	#define RCM_RPFC_RSTFLTSRW_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4075	#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
pradeepvk2208	1:c0c5ac8eac80	4076	#define RCM_RPFC_RSTFLTSS_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4077	#define RCM_RPFC_RSTFLTSS_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4078	/* RPFW Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4079	#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
pradeepvk2208	1:c0c5ac8eac80	4080	#define RCM_RPFW_RSTFLTSEL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4081	#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
pradeepvk2208	1:c0c5ac8eac80	4082
pradeepvk2208	1:c0c5ac8eac80	4083	/*!
pradeepvk2208	1:c0c5ac8eac80	4084	* @}
pradeepvk2208	1:c0c5ac8eac80	4085	/ / end of group RCM_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	4086
pradeepvk2208	1:c0c5ac8eac80	4087
pradeepvk2208	1:c0c5ac8eac80	4088	/* RCM - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	4089	/** Peripheral RCM base address */
pradeepvk2208	1:c0c5ac8eac80	4090	#define RCM_BASE (0x4007F000u)
pradeepvk2208	1:c0c5ac8eac80	4091	/** Peripheral RCM base pointer */
pradeepvk2208	1:c0c5ac8eac80	4092	#define RCM ((RCM_Type *)RCM_BASE)
pradeepvk2208	1:c0c5ac8eac80	4093	/** Array initializer of RCM peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	4094	#define RCM_BASES { RCM }
pradeepvk2208	1:c0c5ac8eac80	4095
pradeepvk2208	1:c0c5ac8eac80	4096	/*!
pradeepvk2208	1:c0c5ac8eac80	4097	* @}
pradeepvk2208	1:c0c5ac8eac80	4098	/ / end of group RCM_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	4099
pradeepvk2208	1:c0c5ac8eac80	4100
pradeepvk2208	1:c0c5ac8eac80	4101	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4102	-- ROM Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4103	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4104
pradeepvk2208	1:c0c5ac8eac80	4105	/*!
pradeepvk2208	1:c0c5ac8eac80	4106	* @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4107	* @{
pradeepvk2208	1:c0c5ac8eac80	4108	*/
pradeepvk2208	1:c0c5ac8eac80	4109
pradeepvk2208	1:c0c5ac8eac80	4110	/** ROM - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	4111	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	4112	__I uint32_t ENTRY[3]; /*< Entry, array offset: 0x0, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	4113	__I uint32_t TABLEMARK; /*< End of Table Marker Register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	4114	uint8_t RESERVED_0[4028];
pradeepvk2208	1:c0c5ac8eac80	4115	__I uint32_t SYSACCESS; /*< System Access Register, offset: 0xFCC /
pradeepvk2208	1:c0c5ac8eac80	4116	__I uint32_t PERIPHID4; /*< Peripheral ID Register, offset: 0xFD0 /
pradeepvk2208	1:c0c5ac8eac80	4117	__I uint32_t PERIPHID5; /*< Peripheral ID Register, offset: 0xFD4 /
pradeepvk2208	1:c0c5ac8eac80	4118	__I uint32_t PERIPHID6; /*< Peripheral ID Register, offset: 0xFD8 /
pradeepvk2208	1:c0c5ac8eac80	4119	__I uint32_t PERIPHID7; /*< Peripheral ID Register, offset: 0xFDC /
pradeepvk2208	1:c0c5ac8eac80	4120	__I uint32_t PERIPHID0; /*< Peripheral ID Register, offset: 0xFE0 /
pradeepvk2208	1:c0c5ac8eac80	4121	__I uint32_t PERIPHID1; /*< Peripheral ID Register, offset: 0xFE4 /
pradeepvk2208	1:c0c5ac8eac80	4122	__I uint32_t PERIPHID2; /*< Peripheral ID Register, offset: 0xFE8 /
pradeepvk2208	1:c0c5ac8eac80	4123	__I uint32_t PERIPHID3; /*< Peripheral ID Register, offset: 0xFEC /
pradeepvk2208	1:c0c5ac8eac80	4124	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	4125	} ROM_Type;
pradeepvk2208	1:c0c5ac8eac80	4126
pradeepvk2208	1:c0c5ac8eac80	4127	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4128	-- ROM Register Masks
pradeepvk2208	1:c0c5ac8eac80	4129	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4130
pradeepvk2208	1:c0c5ac8eac80	4131	/*!
pradeepvk2208	1:c0c5ac8eac80	4132	* @addtogroup ROM_Register_Masks ROM Register Masks
pradeepvk2208	1:c0c5ac8eac80	4133	* @{
pradeepvk2208	1:c0c5ac8eac80	4134	*/
pradeepvk2208	1:c0c5ac8eac80	4135
pradeepvk2208	1:c0c5ac8eac80	4136	/* ENTRY Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4137	#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4138	#define ROM_ENTRY_ENTRY_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4139	#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
pradeepvk2208	1:c0c5ac8eac80	4140	/* TABLEMARK Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4141	#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4142	#define ROM_TABLEMARK_MARK_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4143	#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
pradeepvk2208	1:c0c5ac8eac80	4144	/* SYSACCESS Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4145	#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4146	#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4147	#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
pradeepvk2208	1:c0c5ac8eac80	4148	/* PERIPHID4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4149	#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4150	#define ROM_PERIPHID4_PERIPHID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4151	#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4152	/* PERIPHID5 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4153	#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4154	#define ROM_PERIPHID5_PERIPHID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4155	#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4156	/* PERIPHID6 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4157	#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4158	#define ROM_PERIPHID6_PERIPHID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4159	#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4160	/* PERIPHID7 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4161	#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4162	#define ROM_PERIPHID7_PERIPHID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4163	#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4164	/* PERIPHID0 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4165	#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4166	#define ROM_PERIPHID0_PERIPHID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4167	#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4168	/* PERIPHID1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4169	#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4170	#define ROM_PERIPHID1_PERIPHID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4171	#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4172	/* PERIPHID2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4173	#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4174	#define ROM_PERIPHID2_PERIPHID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4175	#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4176	/* PERIPHID3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4177	#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4178	#define ROM_PERIPHID3_PERIPHID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4179	#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4180	/* COMPID Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4181	#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4182	#define ROM_COMPID_COMPID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4183	#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4184
pradeepvk2208	1:c0c5ac8eac80	4185	/*!
pradeepvk2208	1:c0c5ac8eac80	4186	* @}
pradeepvk2208	1:c0c5ac8eac80	4187	/ / end of group ROM_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	4188
pradeepvk2208	1:c0c5ac8eac80	4189
pradeepvk2208	1:c0c5ac8eac80	4190	/* ROM - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	4191	/** Peripheral ROM base address */
pradeepvk2208	1:c0c5ac8eac80	4192	#define ROM_BASE (0xF0002000u)
pradeepvk2208	1:c0c5ac8eac80	4193	/** Peripheral ROM base pointer */
pradeepvk2208	1:c0c5ac8eac80	4194	#define ROM ((ROM_Type *)ROM_BASE)
pradeepvk2208	1:c0c5ac8eac80	4195	/** Array initializer of ROM peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	4196	#define ROM_BASES { ROM }
pradeepvk2208	1:c0c5ac8eac80	4197
pradeepvk2208	1:c0c5ac8eac80	4198	/*!
pradeepvk2208	1:c0c5ac8eac80	4199	* @}
pradeepvk2208	1:c0c5ac8eac80	4200	/ / end of group ROM_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	4201
pradeepvk2208	1:c0c5ac8eac80	4202
pradeepvk2208	1:c0c5ac8eac80	4203	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4204	-- RTC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4205	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4206
pradeepvk2208	1:c0c5ac8eac80	4207	/*!
pradeepvk2208	1:c0c5ac8eac80	4208	* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4209	* @{
pradeepvk2208	1:c0c5ac8eac80	4210	*/
pradeepvk2208	1:c0c5ac8eac80	4211
pradeepvk2208	1:c0c5ac8eac80	4212	/** RTC - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	4213	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	4214	__IO uint32_t TSR; /*< RTC Time Seconds Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	4215	__IO uint32_t TPR; /*< RTC Time Prescaler Register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	4216	__IO uint32_t TAR; /*< RTC Time Alarm Register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	4217	__IO uint32_t TCR; /*< RTC Time Compensation Register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	4218	__IO uint32_t CR; /*< RTC Control Register, offset: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	4219	__IO uint32_t SR; /*< RTC Status Register, offset: 0x14 /
pradeepvk2208	1:c0c5ac8eac80	4220	__IO uint32_t LR; /*< RTC Lock Register, offset: 0x18 /
pradeepvk2208	1:c0c5ac8eac80	4221	__IO uint32_t IER; /*< RTC Interrupt Enable Register, offset: 0x1C /
pradeepvk2208	1:c0c5ac8eac80	4222	} RTC_Type;
pradeepvk2208	1:c0c5ac8eac80	4223
pradeepvk2208	1:c0c5ac8eac80	4224	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4225	-- RTC Register Masks
pradeepvk2208	1:c0c5ac8eac80	4226	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4227
pradeepvk2208	1:c0c5ac8eac80	4228	/*!
pradeepvk2208	1:c0c5ac8eac80	4229	* @addtogroup RTC_Register_Masks RTC Register Masks
pradeepvk2208	1:c0c5ac8eac80	4230	* @{
pradeepvk2208	1:c0c5ac8eac80	4231	*/
pradeepvk2208	1:c0c5ac8eac80	4232
pradeepvk2208	1:c0c5ac8eac80	4233	/* TSR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4234	#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4235	#define RTC_TSR_TSR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4236	#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
pradeepvk2208	1:c0c5ac8eac80	4237	/* TPR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4238	#define RTC_TPR_TPR_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	4239	#define RTC_TPR_TPR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4240	#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
pradeepvk2208	1:c0c5ac8eac80	4241	/* TAR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4242	#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4243	#define RTC_TAR_TAR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4244	#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
pradeepvk2208	1:c0c5ac8eac80	4245	/* TCR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4246	#define RTC_TCR_TCR_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	4247	#define RTC_TCR_TCR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4248	#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
pradeepvk2208	1:c0c5ac8eac80	4249	#define RTC_TCR_CIR_MASK 0xFF00u
pradeepvk2208	1:c0c5ac8eac80	4250	#define RTC_TCR_CIR_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	4251	#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
pradeepvk2208	1:c0c5ac8eac80	4252	#define RTC_TCR_TCV_MASK 0xFF0000u
pradeepvk2208	1:c0c5ac8eac80	4253	#define RTC_TCR_TCV_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	4254	#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
pradeepvk2208	1:c0c5ac8eac80	4255	#define RTC_TCR_CIC_MASK 0xFF000000u
pradeepvk2208	1:c0c5ac8eac80	4256	#define RTC_TCR_CIC_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	4257	#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
pradeepvk2208	1:c0c5ac8eac80	4258	/* CR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4259	#define RTC_CR_SWR_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4260	#define RTC_CR_SWR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4261	#define RTC_CR_WPE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4262	#define RTC_CR_WPE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4263	#define RTC_CR_SUP_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4264	#define RTC_CR_SUP_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4265	#define RTC_CR_UM_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4266	#define RTC_CR_UM_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4267	#define RTC_CR_OSCE_MASK 0x100u
pradeepvk2208	1:c0c5ac8eac80	4268	#define RTC_CR_OSCE_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	4269	#define RTC_CR_CLKO_MASK 0x200u
pradeepvk2208	1:c0c5ac8eac80	4270	#define RTC_CR_CLKO_SHIFT 9
pradeepvk2208	1:c0c5ac8eac80	4271	#define RTC_CR_SC16P_MASK 0x400u
pradeepvk2208	1:c0c5ac8eac80	4272	#define RTC_CR_SC16P_SHIFT 10
pradeepvk2208	1:c0c5ac8eac80	4273	#define RTC_CR_SC8P_MASK 0x800u
pradeepvk2208	1:c0c5ac8eac80	4274	#define RTC_CR_SC8P_SHIFT 11
pradeepvk2208	1:c0c5ac8eac80	4275	#define RTC_CR_SC4P_MASK 0x1000u
pradeepvk2208	1:c0c5ac8eac80	4276	#define RTC_CR_SC4P_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	4277	#define RTC_CR_SC2P_MASK 0x2000u
pradeepvk2208	1:c0c5ac8eac80	4278	#define RTC_CR_SC2P_SHIFT 13
pradeepvk2208	1:c0c5ac8eac80	4279	/* SR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4280	#define RTC_SR_TIF_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4281	#define RTC_SR_TIF_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4282	#define RTC_SR_TOF_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4283	#define RTC_SR_TOF_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4284	#define RTC_SR_TAF_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4285	#define RTC_SR_TAF_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4286	#define RTC_SR_TCE_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4287	#define RTC_SR_TCE_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4288	/* LR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4289	#define RTC_LR_TCL_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4290	#define RTC_LR_TCL_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4291	#define RTC_LR_CRL_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4292	#define RTC_LR_CRL_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4293	#define RTC_LR_SRL_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4294	#define RTC_LR_SRL_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4295	#define RTC_LR_LRL_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	4296	#define RTC_LR_LRL_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4297	/* IER Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4298	#define RTC_IER_TIIE_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4299	#define RTC_IER_TIIE_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4300	#define RTC_IER_TOIE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4301	#define RTC_IER_TOIE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4302	#define RTC_IER_TAIE_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4303	#define RTC_IER_TAIE_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4304	#define RTC_IER_TSIE_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4305	#define RTC_IER_TSIE_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4306	#define RTC_IER_WPON_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	4307	#define RTC_IER_WPON_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	4308
pradeepvk2208	1:c0c5ac8eac80	4309	/*!
pradeepvk2208	1:c0c5ac8eac80	4310	* @}
pradeepvk2208	1:c0c5ac8eac80	4311	/ / end of group RTC_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	4312
pradeepvk2208	1:c0c5ac8eac80	4313
pradeepvk2208	1:c0c5ac8eac80	4314	/* RTC - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	4315	/** Peripheral RTC base address */
pradeepvk2208	1:c0c5ac8eac80	4316	#define RTC_BASE (0x4003D000u)
pradeepvk2208	1:c0c5ac8eac80	4317	/** Peripheral RTC base pointer */
pradeepvk2208	1:c0c5ac8eac80	4318	#define RTC ((RTC_Type *)RTC_BASE)
pradeepvk2208	1:c0c5ac8eac80	4319	/** Array initializer of RTC peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	4320	#define RTC_BASES { RTC }
pradeepvk2208	1:c0c5ac8eac80	4321
pradeepvk2208	1:c0c5ac8eac80	4322	/*!
pradeepvk2208	1:c0c5ac8eac80	4323	* @}
pradeepvk2208	1:c0c5ac8eac80	4324	/ / end of group RTC_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	4325
pradeepvk2208	1:c0c5ac8eac80	4326
pradeepvk2208	1:c0c5ac8eac80	4327	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4328	-- SIM Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4329	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4330
pradeepvk2208	1:c0c5ac8eac80	4331	/*!
pradeepvk2208	1:c0c5ac8eac80	4332	* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4333	* @{
pradeepvk2208	1:c0c5ac8eac80	4334	*/
pradeepvk2208	1:c0c5ac8eac80	4335
pradeepvk2208	1:c0c5ac8eac80	4336	/** SIM - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	4337	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	4338	__IO uint32_t SOPT1; /*< System Options Register 1, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	4339	__IO uint32_t SOPT1CFG; /*< SOPT1 Configuration Register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	4340	uint8_t RESERVED_0[4092];
pradeepvk2208	1:c0c5ac8eac80	4341	__IO uint32_t SOPT2; /*< System Options Register 2, offset: 0x1004 /
pradeepvk2208	1:c0c5ac8eac80	4342	uint8_t RESERVED_1[4];
pradeepvk2208	1:c0c5ac8eac80	4343	__IO uint32_t SOPT4; /*< System Options Register 4, offset: 0x100C /
pradeepvk2208	1:c0c5ac8eac80	4344	__IO uint32_t SOPT5; /*< System Options Register 5, offset: 0x1010 /
pradeepvk2208	1:c0c5ac8eac80	4345	uint8_t RESERVED_2[4];
pradeepvk2208	1:c0c5ac8eac80	4346	__IO uint32_t SOPT7; /*< System Options Register 7, offset: 0x1018 /
pradeepvk2208	1:c0c5ac8eac80	4347	uint8_t RESERVED_3[8];
pradeepvk2208	1:c0c5ac8eac80	4348	__I uint32_t SDID; /*< System Device Identification Register, offset: 0x1024 /
pradeepvk2208	1:c0c5ac8eac80	4349	uint8_t RESERVED_4[12];
pradeepvk2208	1:c0c5ac8eac80	4350	__IO uint32_t SCGC4; /*< System Clock Gating Control Register 4, offset: 0x1034 /
pradeepvk2208	1:c0c5ac8eac80	4351	__IO uint32_t SCGC5; /*< System Clock Gating Control Register 5, offset: 0x1038 /
pradeepvk2208	1:c0c5ac8eac80	4352	__IO uint32_t SCGC6; /*< System Clock Gating Control Register 6, offset: 0x103C /
pradeepvk2208	1:c0c5ac8eac80	4353	__IO uint32_t SCGC7; /*< System Clock Gating Control Register 7, offset: 0x1040 /
pradeepvk2208	1:c0c5ac8eac80	4354	__IO uint32_t CLKDIV1; /*< System Clock Divider Register 1, offset: 0x1044 /
pradeepvk2208	1:c0c5ac8eac80	4355	uint8_t RESERVED_5[4];
pradeepvk2208	1:c0c5ac8eac80	4356	__IO uint32_t FCFG1; /*< Flash Configuration Register 1, offset: 0x104C /
pradeepvk2208	1:c0c5ac8eac80	4357	__I uint32_t FCFG2; /*< Flash Configuration Register 2, offset: 0x1050 /
pradeepvk2208	1:c0c5ac8eac80	4358	uint8_t RESERVED_6[4];
pradeepvk2208	1:c0c5ac8eac80	4359	__I uint32_t UIDMH; /*< Unique Identification Register Mid-High, offset: 0x1058 /
pradeepvk2208	1:c0c5ac8eac80	4360	__I uint32_t UIDML; /*< Unique Identification Register Mid Low, offset: 0x105C /
pradeepvk2208	1:c0c5ac8eac80	4361	__I uint32_t UIDL; /*< Unique Identification Register Low, offset: 0x1060 /
pradeepvk2208	1:c0c5ac8eac80	4362	uint8_t RESERVED_7[156];
pradeepvk2208	1:c0c5ac8eac80	4363	__IO uint32_t COPC; /*< COP Control Register, offset: 0x1100 /
pradeepvk2208	1:c0c5ac8eac80	4364	__O uint32_t SRVCOP; /*< Service COP Register, offset: 0x1104 /
pradeepvk2208	1:c0c5ac8eac80	4365	} SIM_Type;
pradeepvk2208	1:c0c5ac8eac80	4366
pradeepvk2208	1:c0c5ac8eac80	4367	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4368	-- SIM Register Masks
pradeepvk2208	1:c0c5ac8eac80	4369	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4370
pradeepvk2208	1:c0c5ac8eac80	4371	/*!
pradeepvk2208	1:c0c5ac8eac80	4372	* @addtogroup SIM_Register_Masks SIM Register Masks
pradeepvk2208	1:c0c5ac8eac80	4373	* @{
pradeepvk2208	1:c0c5ac8eac80	4374	*/
pradeepvk2208	1:c0c5ac8eac80	4375
pradeepvk2208	1:c0c5ac8eac80	4376	/* SOPT1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4377	#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
pradeepvk2208	1:c0c5ac8eac80	4378	#define SIM_SOPT1_OSC32KSEL_SHIFT 18
pradeepvk2208	1:c0c5ac8eac80	4379	#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
pradeepvk2208	1:c0c5ac8eac80	4380	#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
pradeepvk2208	1:c0c5ac8eac80	4381	#define SIM_SOPT1_USBVSTBY_SHIFT 29
pradeepvk2208	1:c0c5ac8eac80	4382	#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
pradeepvk2208	1:c0c5ac8eac80	4383	#define SIM_SOPT1_USBSSTBY_SHIFT 30
pradeepvk2208	1:c0c5ac8eac80	4384	#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
pradeepvk2208	1:c0c5ac8eac80	4385	#define SIM_SOPT1_USBREGEN_SHIFT 31
pradeepvk2208	1:c0c5ac8eac80	4386	/* SOPT1CFG Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4387	#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
pradeepvk2208	1:c0c5ac8eac80	4388	#define SIM_SOPT1CFG_URWE_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	4389	#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
pradeepvk2208	1:c0c5ac8eac80	4390	#define SIM_SOPT1CFG_UVSWE_SHIFT 25
pradeepvk2208	1:c0c5ac8eac80	4391	#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
pradeepvk2208	1:c0c5ac8eac80	4392	#define SIM_SOPT1CFG_USSWE_SHIFT 26
pradeepvk2208	1:c0c5ac8eac80	4393	/* SOPT2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4394	#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4395	#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4396	#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
pradeepvk2208	1:c0c5ac8eac80	4397	#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4398	#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
pradeepvk2208	1:c0c5ac8eac80	4399	#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
pradeepvk2208	1:c0c5ac8eac80	4400	#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	4401	#define SIM_SOPT2_USBSRC_MASK 0x40000u
pradeepvk2208	1:c0c5ac8eac80	4402	#define SIM_SOPT2_USBSRC_SHIFT 18
pradeepvk2208	1:c0c5ac8eac80	4403	#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
pradeepvk2208	1:c0c5ac8eac80	4404	#define SIM_SOPT2_TPMSRC_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	4405	#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
pradeepvk2208	1:c0c5ac8eac80	4406	#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
pradeepvk2208	1:c0c5ac8eac80	4407	#define SIM_SOPT2_UART0SRC_SHIFT 26
pradeepvk2208	1:c0c5ac8eac80	4408	#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
pradeepvk2208	1:c0c5ac8eac80	4409	/* SOPT4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4410	#define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
pradeepvk2208	1:c0c5ac8eac80	4411	#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
pradeepvk2208	1:c0c5ac8eac80	4412	#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
pradeepvk2208	1:c0c5ac8eac80	4413	#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
pradeepvk2208	1:c0c5ac8eac80	4414	#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
pradeepvk2208	1:c0c5ac8eac80	4415	#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
pradeepvk2208	1:c0c5ac8eac80	4416	#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	4417	#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
pradeepvk2208	1:c0c5ac8eac80	4418	#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
pradeepvk2208	1:c0c5ac8eac80	4419	#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
pradeepvk2208	1:c0c5ac8eac80	4420	#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
pradeepvk2208	1:c0c5ac8eac80	4421	/* SOPT5 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4422	#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
pradeepvk2208	1:c0c5ac8eac80	4423	#define SIM_SOPT5_UART0TXSRC_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4424	#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
pradeepvk2208	1:c0c5ac8eac80	4425	#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4426	#define SIM_SOPT5_UART0RXSRC_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4427	#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
pradeepvk2208	1:c0c5ac8eac80	4428	#define SIM_SOPT5_UART1TXSRC_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4429	#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
pradeepvk2208	1:c0c5ac8eac80	4430	#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	4431	#define SIM_SOPT5_UART1RXSRC_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4432	#define SIM_SOPT5_UART0ODE_MASK 0x10000u
pradeepvk2208	1:c0c5ac8eac80	4433	#define SIM_SOPT5_UART0ODE_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	4434	#define SIM_SOPT5_UART1ODE_MASK 0x20000u
pradeepvk2208	1:c0c5ac8eac80	4435	#define SIM_SOPT5_UART1ODE_SHIFT 17
pradeepvk2208	1:c0c5ac8eac80	4436	#define SIM_SOPT5_UART2ODE_MASK 0x40000u
pradeepvk2208	1:c0c5ac8eac80	4437	#define SIM_SOPT5_UART2ODE_SHIFT 18
pradeepvk2208	1:c0c5ac8eac80	4438	/* SOPT7 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4439	#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
pradeepvk2208	1:c0c5ac8eac80	4440	#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4441	#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
pradeepvk2208	1:c0c5ac8eac80	4442	#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4443	#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4444	#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	4445	#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	4446	/* SDID Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4447	#define SIM_SDID_PINID_MASK 0xFu
pradeepvk2208	1:c0c5ac8eac80	4448	#define SIM_SDID_PINID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4449	#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4450	#define SIM_SDID_DIEID_MASK 0xF80u
pradeepvk2208	1:c0c5ac8eac80	4451	#define SIM_SDID_DIEID_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	4452	#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4453	#define SIM_SDID_REVID_MASK 0xF000u
pradeepvk2208	1:c0c5ac8eac80	4454	#define SIM_SDID_REVID_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	4455	#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4456	#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
pradeepvk2208	1:c0c5ac8eac80	4457	#define SIM_SDID_SRAMSIZE_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	4458	#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
pradeepvk2208	1:c0c5ac8eac80	4459	#define SIM_SDID_SERIESID_MASK 0xF00000u
pradeepvk2208	1:c0c5ac8eac80	4460	#define SIM_SDID_SERIESID_SHIFT 20
pradeepvk2208	1:c0c5ac8eac80	4461	#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4462	#define SIM_SDID_SUBFAMID_MASK 0xF000000u
pradeepvk2208	1:c0c5ac8eac80	4463	#define SIM_SDID_SUBFAMID_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	4464	#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4465	#define SIM_SDID_FAMID_MASK 0xF0000000u
pradeepvk2208	1:c0c5ac8eac80	4466	#define SIM_SDID_FAMID_SHIFT 28
pradeepvk2208	1:c0c5ac8eac80	4467	#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4468	/* SCGC4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4469	#define SIM_SCGC4_I2C0_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	4470	#define SIM_SCGC4_I2C0_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4471	#define SIM_SCGC4_I2C1_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	4472	#define SIM_SCGC4_I2C1_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	4473	#define SIM_SCGC4_UART0_MASK 0x400u
pradeepvk2208	1:c0c5ac8eac80	4474	#define SIM_SCGC4_UART0_SHIFT 10
pradeepvk2208	1:c0c5ac8eac80	4475	#define SIM_SCGC4_UART1_MASK 0x800u
pradeepvk2208	1:c0c5ac8eac80	4476	#define SIM_SCGC4_UART1_SHIFT 11
pradeepvk2208	1:c0c5ac8eac80	4477	#define SIM_SCGC4_UART2_MASK 0x1000u
pradeepvk2208	1:c0c5ac8eac80	4478	#define SIM_SCGC4_UART2_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	4479	#define SIM_SCGC4_USBOTG_MASK 0x40000u
pradeepvk2208	1:c0c5ac8eac80	4480	#define SIM_SCGC4_USBOTG_SHIFT 18
pradeepvk2208	1:c0c5ac8eac80	4481	#define SIM_SCGC4_CMP_MASK 0x80000u
pradeepvk2208	1:c0c5ac8eac80	4482	#define SIM_SCGC4_CMP_SHIFT 19
pradeepvk2208	1:c0c5ac8eac80	4483	#define SIM_SCGC4_SPI0_MASK 0x400000u
pradeepvk2208	1:c0c5ac8eac80	4484	#define SIM_SCGC4_SPI0_SHIFT 22
pradeepvk2208	1:c0c5ac8eac80	4485	#define SIM_SCGC4_SPI1_MASK 0x800000u
pradeepvk2208	1:c0c5ac8eac80	4486	#define SIM_SCGC4_SPI1_SHIFT 23
pradeepvk2208	1:c0c5ac8eac80	4487	/* SCGC5 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4488	#define SIM_SCGC5_LPTMR_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4489	#define SIM_SCGC5_LPTMR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4490	#define SIM_SCGC5_TSI_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4491	#define SIM_SCGC5_TSI_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4492	#define SIM_SCGC5_PORTA_MASK 0x200u
pradeepvk2208	1:c0c5ac8eac80	4493	#define SIM_SCGC5_PORTA_SHIFT 9
pradeepvk2208	1:c0c5ac8eac80	4494	#define SIM_SCGC5_PORTB_MASK 0x400u
pradeepvk2208	1:c0c5ac8eac80	4495	#define SIM_SCGC5_PORTB_SHIFT 10
pradeepvk2208	1:c0c5ac8eac80	4496	#define SIM_SCGC5_PORTC_MASK 0x800u
pradeepvk2208	1:c0c5ac8eac80	4497	#define SIM_SCGC5_PORTC_SHIFT 11
pradeepvk2208	1:c0c5ac8eac80	4498	#define SIM_SCGC5_PORTD_MASK 0x1000u
pradeepvk2208	1:c0c5ac8eac80	4499	#define SIM_SCGC5_PORTD_SHIFT 12
pradeepvk2208	1:c0c5ac8eac80	4500	#define SIM_SCGC5_PORTE_MASK 0x2000u
pradeepvk2208	1:c0c5ac8eac80	4501	#define SIM_SCGC5_PORTE_SHIFT 13
pradeepvk2208	1:c0c5ac8eac80	4502	#define SIM_SCGC5_SLCD_MASK 0x80000u
pradeepvk2208	1:c0c5ac8eac80	4503	#define SIM_SCGC5_SLCD_SHIFT 19
pradeepvk2208	1:c0c5ac8eac80	4504	/* SCGC6 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4505	#define SIM_SCGC6_FTF_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4506	#define SIM_SCGC6_FTF_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4507	#define SIM_SCGC6_DMAMUX_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4508	#define SIM_SCGC6_DMAMUX_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4509	#define SIM_SCGC6_I2S_MASK 0x8000u
pradeepvk2208	1:c0c5ac8eac80	4510	#define SIM_SCGC6_I2S_SHIFT 15
pradeepvk2208	1:c0c5ac8eac80	4511	#define SIM_SCGC6_PIT_MASK 0x800000u
pradeepvk2208	1:c0c5ac8eac80	4512	#define SIM_SCGC6_PIT_SHIFT 23
pradeepvk2208	1:c0c5ac8eac80	4513	#define SIM_SCGC6_TPM0_MASK 0x1000000u
pradeepvk2208	1:c0c5ac8eac80	4514	#define SIM_SCGC6_TPM0_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	4515	#define SIM_SCGC6_TPM1_MASK 0x2000000u
pradeepvk2208	1:c0c5ac8eac80	4516	#define SIM_SCGC6_TPM1_SHIFT 25
pradeepvk2208	1:c0c5ac8eac80	4517	#define SIM_SCGC6_TPM2_MASK 0x4000000u
pradeepvk2208	1:c0c5ac8eac80	4518	#define SIM_SCGC6_TPM2_SHIFT 26
pradeepvk2208	1:c0c5ac8eac80	4519	#define SIM_SCGC6_ADC0_MASK 0x8000000u
pradeepvk2208	1:c0c5ac8eac80	4520	#define SIM_SCGC6_ADC0_SHIFT 27
pradeepvk2208	1:c0c5ac8eac80	4521	#define SIM_SCGC6_RTC_MASK 0x20000000u
pradeepvk2208	1:c0c5ac8eac80	4522	#define SIM_SCGC6_RTC_SHIFT 29
pradeepvk2208	1:c0c5ac8eac80	4523	#define SIM_SCGC6_DAC0_MASK 0x80000000u
pradeepvk2208	1:c0c5ac8eac80	4524	#define SIM_SCGC6_DAC0_SHIFT 31
pradeepvk2208	1:c0c5ac8eac80	4525	/* SCGC7 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4526	#define SIM_SCGC7_DMA_MASK 0x100u
pradeepvk2208	1:c0c5ac8eac80	4527	#define SIM_SCGC7_DMA_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	4528	/* CLKDIV1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4529	#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
pradeepvk2208	1:c0c5ac8eac80	4530	#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	4531	#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
pradeepvk2208	1:c0c5ac8eac80	4532	#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
pradeepvk2208	1:c0c5ac8eac80	4533	#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
pradeepvk2208	1:c0c5ac8eac80	4534	#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
pradeepvk2208	1:c0c5ac8eac80	4535	/* FCFG1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4536	#define SIM_FCFG1_FLASHDIS_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4537	#define SIM_FCFG1_FLASHDIS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4538	#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4539	#define SIM_FCFG1_FLASHDOZE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4540	#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
pradeepvk2208	1:c0c5ac8eac80	4541	#define SIM_FCFG1_PFSIZE_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	4542	#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
pradeepvk2208	1:c0c5ac8eac80	4543	/* FCFG2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4544	#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
pradeepvk2208	1:c0c5ac8eac80	4545	#define SIM_FCFG2_MAXADDR1_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	4546	#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
pradeepvk2208	1:c0c5ac8eac80	4547	#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
pradeepvk2208	1:c0c5ac8eac80	4548	#define SIM_FCFG2_MAXADDR0_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	4549	#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
pradeepvk2208	1:c0c5ac8eac80	4550	/* UIDMH Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4551	#define SIM_UIDMH_UID_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	4552	#define SIM_UIDMH_UID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4553	#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4554	/* UIDML Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4555	#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4556	#define SIM_UIDML_UID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4557	#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4558	/* UIDL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4559	#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
pradeepvk2208	1:c0c5ac8eac80	4560	#define SIM_UIDL_UID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4561	#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
pradeepvk2208	1:c0c5ac8eac80	4562	/* COPC Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4563	#define SIM_COPC_COPW_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4564	#define SIM_COPC_COPW_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4565	#define SIM_COPC_COPCLKS_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4566	#define SIM_COPC_COPCLKS_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4567	#define SIM_COPC_COPT_MASK 0xCu
pradeepvk2208	1:c0c5ac8eac80	4568	#define SIM_COPC_COPT_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4569	#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
pradeepvk2208	1:c0c5ac8eac80	4570	/* SRVCOP Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4571	#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	4572	#define SIM_SRVCOP_SRVCOP_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4573	#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
pradeepvk2208	1:c0c5ac8eac80	4574
pradeepvk2208	1:c0c5ac8eac80	4575	/*!
pradeepvk2208	1:c0c5ac8eac80	4576	* @}
pradeepvk2208	1:c0c5ac8eac80	4577	/ / end of group SIM_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	4578
pradeepvk2208	1:c0c5ac8eac80	4579
pradeepvk2208	1:c0c5ac8eac80	4580	/* SIM - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	4581	/** Peripheral SIM base address */
pradeepvk2208	1:c0c5ac8eac80	4582	#define SIM_BASE (0x40047000u)
pradeepvk2208	1:c0c5ac8eac80	4583	/** Peripheral SIM base pointer */
pradeepvk2208	1:c0c5ac8eac80	4584	#define SIM ((SIM_Type *)SIM_BASE)
pradeepvk2208	1:c0c5ac8eac80	4585	/** Array initializer of SIM peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	4586	#define SIM_BASES { SIM }
pradeepvk2208	1:c0c5ac8eac80	4587
pradeepvk2208	1:c0c5ac8eac80	4588	/*!
pradeepvk2208	1:c0c5ac8eac80	4589	* @}
pradeepvk2208	1:c0c5ac8eac80	4590	/ / end of group SIM_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	4591
pradeepvk2208	1:c0c5ac8eac80	4592
pradeepvk2208	1:c0c5ac8eac80	4593	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4594	-- SMC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4595	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4596
pradeepvk2208	1:c0c5ac8eac80	4597	/*!
pradeepvk2208	1:c0c5ac8eac80	4598	* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4599	* @{
pradeepvk2208	1:c0c5ac8eac80	4600	*/
pradeepvk2208	1:c0c5ac8eac80	4601
pradeepvk2208	1:c0c5ac8eac80	4602	/** SMC - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	4603	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	4604	__IO uint8_t PMPROT; /*< Power Mode Protection register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	4605	__IO uint8_t PMCTRL; /*< Power Mode Control register, offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	4606	__IO uint8_t STOPCTRL; /*< Stop Control Register, offset: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	4607	__I uint8_t PMSTAT; /*< Power Mode Status register, offset: 0x3 /
pradeepvk2208	1:c0c5ac8eac80	4608	} SMC_Type;
pradeepvk2208	1:c0c5ac8eac80	4609
pradeepvk2208	1:c0c5ac8eac80	4610	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4611	-- SMC Register Masks
pradeepvk2208	1:c0c5ac8eac80	4612	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4613
pradeepvk2208	1:c0c5ac8eac80	4614	/*!
pradeepvk2208	1:c0c5ac8eac80	4615	* @addtogroup SMC_Register_Masks SMC Register Masks
pradeepvk2208	1:c0c5ac8eac80	4616	* @{
pradeepvk2208	1:c0c5ac8eac80	4617	*/
pradeepvk2208	1:c0c5ac8eac80	4618
pradeepvk2208	1:c0c5ac8eac80	4619	/* PMPROT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4620	#define SMC_PMPROT_AVLLS_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4621	#define SMC_PMPROT_AVLLS_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4622	#define SMC_PMPROT_ALLS_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4623	#define SMC_PMPROT_ALLS_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4624	#define SMC_PMPROT_AVLP_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4625	#define SMC_PMPROT_AVLP_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4626	/* PMCTRL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4627	#define SMC_PMCTRL_STOPM_MASK 0x7u
pradeepvk2208	1:c0c5ac8eac80	4628	#define SMC_PMCTRL_STOPM_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4629	#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
pradeepvk2208	1:c0c5ac8eac80	4630	#define SMC_PMCTRL_STOPA_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4631	#define SMC_PMCTRL_STOPA_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4632	#define SMC_PMCTRL_RUNM_MASK 0x60u
pradeepvk2208	1:c0c5ac8eac80	4633	#define SMC_PMCTRL_RUNM_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4634	#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
pradeepvk2208	1:c0c5ac8eac80	4635	/* STOPCTRL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4636	#define SMC_STOPCTRL_VLLSM_MASK 0x7u
pradeepvk2208	1:c0c5ac8eac80	4637	#define SMC_STOPCTRL_VLLSM_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4638	#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
pradeepvk2208	1:c0c5ac8eac80	4639	#define SMC_STOPCTRL_PORPO_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4640	#define SMC_STOPCTRL_PORPO_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4641	#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
pradeepvk2208	1:c0c5ac8eac80	4642	#define SMC_STOPCTRL_PSTOPO_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4643	#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
pradeepvk2208	1:c0c5ac8eac80	4644	/* PMSTAT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4645	#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
pradeepvk2208	1:c0c5ac8eac80	4646	#define SMC_PMSTAT_PMSTAT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4647	#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
pradeepvk2208	1:c0c5ac8eac80	4648
pradeepvk2208	1:c0c5ac8eac80	4649	/*!
pradeepvk2208	1:c0c5ac8eac80	4650	* @}
pradeepvk2208	1:c0c5ac8eac80	4651	/ / end of group SMC_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	4652
pradeepvk2208	1:c0c5ac8eac80	4653
pradeepvk2208	1:c0c5ac8eac80	4654	/* SMC - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	4655	/** Peripheral SMC base address */
pradeepvk2208	1:c0c5ac8eac80	4656	#define SMC_BASE (0x4007E000u)
pradeepvk2208	1:c0c5ac8eac80	4657	/** Peripheral SMC base pointer */
pradeepvk2208	1:c0c5ac8eac80	4658	#define SMC ((SMC_Type *)SMC_BASE)
pradeepvk2208	1:c0c5ac8eac80	4659	/** Array initializer of SMC peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	4660	#define SMC_BASES { SMC }
pradeepvk2208	1:c0c5ac8eac80	4661
pradeepvk2208	1:c0c5ac8eac80	4662	/*!
pradeepvk2208	1:c0c5ac8eac80	4663	* @}
pradeepvk2208	1:c0c5ac8eac80	4664	/ / end of group SMC_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	4665
pradeepvk2208	1:c0c5ac8eac80	4666
pradeepvk2208	1:c0c5ac8eac80	4667	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4668	-- SPI Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4669	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4670
pradeepvk2208	1:c0c5ac8eac80	4671	/*!
pradeepvk2208	1:c0c5ac8eac80	4672	* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4673	* @{
pradeepvk2208	1:c0c5ac8eac80	4674	*/
pradeepvk2208	1:c0c5ac8eac80	4675
pradeepvk2208	1:c0c5ac8eac80	4676	/** SPI - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	4677	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	4678	__I uint8_t S; /*< SPI status register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	4679	__IO uint8_t BR; /*< SPI baud rate register, offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	4680	__IO uint8_t C2; /*< SPI control register 2, offset: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	4681	__IO uint8_t C1; /*< SPI control register 1, offset: 0x3 /
pradeepvk2208	1:c0c5ac8eac80	4682	__IO uint8_t ML; /*< SPI match register low, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	4683	__IO uint8_t MH; /*< SPI match register high, offset: 0x5 /
pradeepvk2208	1:c0c5ac8eac80	4684	__IO uint8_t DL; /*< SPI data register low, offset: 0x6 /
pradeepvk2208	1:c0c5ac8eac80	4685	__IO uint8_t DH; /*< SPI data register high, offset: 0x7 /
pradeepvk2208	1:c0c5ac8eac80	4686	uint8_t RESERVED_0[2];
pradeepvk2208	1:c0c5ac8eac80	4687	__IO uint8_t CI; /*< SPI clear interrupt register, offset: 0xA /
pradeepvk2208	1:c0c5ac8eac80	4688	__IO uint8_t C3; /*< SPI control register 3, offset: 0xB /
pradeepvk2208	1:c0c5ac8eac80	4689	} SPI_Type;
pradeepvk2208	1:c0c5ac8eac80	4690
pradeepvk2208	1:c0c5ac8eac80	4691	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4692	-- SPI Register Masks
pradeepvk2208	1:c0c5ac8eac80	4693	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4694
pradeepvk2208	1:c0c5ac8eac80	4695	/*!
pradeepvk2208	1:c0c5ac8eac80	4696	* @addtogroup SPI_Register_Masks SPI Register Masks
pradeepvk2208	1:c0c5ac8eac80	4697	* @{
pradeepvk2208	1:c0c5ac8eac80	4698	*/
pradeepvk2208	1:c0c5ac8eac80	4699
pradeepvk2208	1:c0c5ac8eac80	4700	/* S Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4701	#define SPI_S_RFIFOEF_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4702	#define SPI_S_RFIFOEF_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4703	#define SPI_S_TXFULLF_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4704	#define SPI_S_TXFULLF_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4705	#define SPI_S_TNEAREF_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4706	#define SPI_S_TNEAREF_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4707	#define SPI_S_RNFULLF_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4708	#define SPI_S_RNFULLF_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4709	#define SPI_S_MODF_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4710	#define SPI_S_MODF_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4711	#define SPI_S_SPTEF_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4712	#define SPI_S_SPTEF_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4713	#define SPI_S_SPMF_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	4714	#define SPI_S_SPMF_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4715	#define SPI_S_SPRF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	4716	#define SPI_S_SPRF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	4717	/* BR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4718	#define SPI_BR_SPR_MASK 0xFu
pradeepvk2208	1:c0c5ac8eac80	4719	#define SPI_BR_SPR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4720	#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
pradeepvk2208	1:c0c5ac8eac80	4721	#define SPI_BR_SPPR_MASK 0x70u
pradeepvk2208	1:c0c5ac8eac80	4722	#define SPI_BR_SPPR_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4723	#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
pradeepvk2208	1:c0c5ac8eac80	4724	/* C2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4725	#define SPI_C2_SPC0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4726	#define SPI_C2_SPC0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4727	#define SPI_C2_SPISWAI_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4728	#define SPI_C2_SPISWAI_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4729	#define SPI_C2_RXDMAE_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4730	#define SPI_C2_RXDMAE_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4731	#define SPI_C2_BIDIROE_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4732	#define SPI_C2_BIDIROE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4733	#define SPI_C2_MODFEN_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4734	#define SPI_C2_MODFEN_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4735	#define SPI_C2_TXDMAE_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4736	#define SPI_C2_TXDMAE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4737	#define SPI_C2_SPIMODE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	4738	#define SPI_C2_SPIMODE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4739	#define SPI_C2_SPMIE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	4740	#define SPI_C2_SPMIE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	4741	/* C1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4742	#define SPI_C1_LSBFE_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4743	#define SPI_C1_LSBFE_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4744	#define SPI_C1_SSOE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4745	#define SPI_C1_SSOE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4746	#define SPI_C1_CPHA_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4747	#define SPI_C1_CPHA_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4748	#define SPI_C1_CPOL_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4749	#define SPI_C1_CPOL_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4750	#define SPI_C1_MSTR_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4751	#define SPI_C1_MSTR_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4752	#define SPI_C1_SPTIE_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4753	#define SPI_C1_SPTIE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4754	#define SPI_C1_SPE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	4755	#define SPI_C1_SPE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4756	#define SPI_C1_SPIE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	4757	#define SPI_C1_SPIE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	4758	/* ML Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4759	#define SPI_ML_Bits_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	4760	#define SPI_ML_Bits_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4761	#define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
pradeepvk2208	1:c0c5ac8eac80	4762	/* MH Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4763	#define SPI_MH_Bits_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	4764	#define SPI_MH_Bits_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4765	#define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
pradeepvk2208	1:c0c5ac8eac80	4766	/* DL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4767	#define SPI_DL_Bits_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	4768	#define SPI_DL_Bits_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4769	#define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
pradeepvk2208	1:c0c5ac8eac80	4770	/* DH Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4771	#define SPI_DH_Bits_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	4772	#define SPI_DH_Bits_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4773	#define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
pradeepvk2208	1:c0c5ac8eac80	4774	/* CI Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4775	#define SPI_CI_SPRFCI_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4776	#define SPI_CI_SPRFCI_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4777	#define SPI_CI_SPTEFCI_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4778	#define SPI_CI_SPTEFCI_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4779	#define SPI_CI_RNFULLFCI_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4780	#define SPI_CI_RNFULLFCI_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4781	#define SPI_CI_TNEAREFCI_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4782	#define SPI_CI_TNEAREFCI_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4783	#define SPI_CI_RXFOF_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4784	#define SPI_CI_RXFOF_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4785	#define SPI_CI_TXFOF_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4786	#define SPI_CI_TXFOF_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4787	#define SPI_CI_RXFERR_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	4788	#define SPI_CI_RXFERR_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4789	#define SPI_CI_TXFERR_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	4790	#define SPI_CI_TXFERR_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	4791	/* C3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4792	#define SPI_C3_FIFOMODE_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4793	#define SPI_C3_FIFOMODE_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4794	#define SPI_C3_RNFULLIEN_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4795	#define SPI_C3_RNFULLIEN_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4796	#define SPI_C3_TNEARIEN_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4797	#define SPI_C3_TNEARIEN_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4798	#define SPI_C3_INTCLR_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4799	#define SPI_C3_INTCLR_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4800	#define SPI_C3_RNFULLF_MARK_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4801	#define SPI_C3_RNFULLF_MARK_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4802	#define SPI_C3_TNEAREF_MARK_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4803	#define SPI_C3_TNEAREF_MARK_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4804
pradeepvk2208	1:c0c5ac8eac80	4805	/*!
pradeepvk2208	1:c0c5ac8eac80	4806	* @}
pradeepvk2208	1:c0c5ac8eac80	4807	/ / end of group SPI_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	4808
pradeepvk2208	1:c0c5ac8eac80	4809
pradeepvk2208	1:c0c5ac8eac80	4810	/* SPI - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	4811	/** Peripheral SPI0 base address */
pradeepvk2208	1:c0c5ac8eac80	4812	#define SPI0_BASE (0x40076000u)
pradeepvk2208	1:c0c5ac8eac80	4813	/** Peripheral SPI0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	4814	#define SPI0 ((SPI_Type *)SPI0_BASE)
pradeepvk2208	1:c0c5ac8eac80	4815	/** Peripheral SPI1 base address */
pradeepvk2208	1:c0c5ac8eac80	4816	#define SPI1_BASE (0x40077000u)
pradeepvk2208	1:c0c5ac8eac80	4817	/** Peripheral SPI1 base pointer */
pradeepvk2208	1:c0c5ac8eac80	4818	#define SPI1 ((SPI_Type *)SPI1_BASE)
pradeepvk2208	1:c0c5ac8eac80	4819	/** Array initializer of SPI peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	4820	#define SPI_BASES { SPI0, SPI1 }
pradeepvk2208	1:c0c5ac8eac80	4821
pradeepvk2208	1:c0c5ac8eac80	4822	/*!
pradeepvk2208	1:c0c5ac8eac80	4823	* @}
pradeepvk2208	1:c0c5ac8eac80	4824	/ / end of group SPI_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	4825
pradeepvk2208	1:c0c5ac8eac80	4826
pradeepvk2208	1:c0c5ac8eac80	4827	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4828	-- TPM Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4829	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4830
pradeepvk2208	1:c0c5ac8eac80	4831	/*!
pradeepvk2208	1:c0c5ac8eac80	4832	* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4833	* @{
pradeepvk2208	1:c0c5ac8eac80	4834	*/
pradeepvk2208	1:c0c5ac8eac80	4835
pradeepvk2208	1:c0c5ac8eac80	4836	/** TPM - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	4837	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	4838	__IO uint32_t SC; /*< Status and Control, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	4839	__IO uint32_t CNT; /*< Counter, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	4840	__IO uint32_t MOD; /*< Modulo, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	4841	struct { /* offset: 0xC, array step: 0x8 */
pradeepvk2208	1:c0c5ac8eac80	4842	__IO uint32_t CnSC; /*< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	4843	__IO uint32_t CnV; /*< Channel (n) Value, array offset: 0x10, array step: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	4844	} CONTROLS[6];
pradeepvk2208	1:c0c5ac8eac80	4845	uint8_t RESERVED_0[20];
pradeepvk2208	1:c0c5ac8eac80	4846	__IO uint32_t STATUS; /*< Capture and Compare Status, offset: 0x50 /
pradeepvk2208	1:c0c5ac8eac80	4847	uint8_t RESERVED_1[48];
pradeepvk2208	1:c0c5ac8eac80	4848	__IO uint32_t CONF; /*< Configuration, offset: 0x84 /
pradeepvk2208	1:c0c5ac8eac80	4849	} TPM_Type;
pradeepvk2208	1:c0c5ac8eac80	4850
pradeepvk2208	1:c0c5ac8eac80	4851	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4852	-- TPM Register Masks
pradeepvk2208	1:c0c5ac8eac80	4853	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4854
pradeepvk2208	1:c0c5ac8eac80	4855	/*!
pradeepvk2208	1:c0c5ac8eac80	4856	* @addtogroup TPM_Register_Masks TPM Register Masks
pradeepvk2208	1:c0c5ac8eac80	4857	* @{
pradeepvk2208	1:c0c5ac8eac80	4858	*/
pradeepvk2208	1:c0c5ac8eac80	4859
pradeepvk2208	1:c0c5ac8eac80	4860	/* SC Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4861	#define TPM_SC_PS_MASK 0x7u
pradeepvk2208	1:c0c5ac8eac80	4862	#define TPM_SC_PS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4863	#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
pradeepvk2208	1:c0c5ac8eac80	4864	#define TPM_SC_CMOD_MASK 0x18u
pradeepvk2208	1:c0c5ac8eac80	4865	#define TPM_SC_CMOD_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4866	#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
pradeepvk2208	1:c0c5ac8eac80	4867	#define TPM_SC_CPWMS_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4868	#define TPM_SC_CPWMS_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4869	#define TPM_SC_TOIE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	4870	#define TPM_SC_TOIE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4871	#define TPM_SC_TOF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	4872	#define TPM_SC_TOF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	4873	#define TPM_SC_DMA_MASK 0x100u
pradeepvk2208	1:c0c5ac8eac80	4874	#define TPM_SC_DMA_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	4875	/* CNT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4876	#define TPM_CNT_COUNT_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	4877	#define TPM_CNT_COUNT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4878	#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
pradeepvk2208	1:c0c5ac8eac80	4879	/* MOD Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4880	#define TPM_MOD_MOD_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	4881	#define TPM_MOD_MOD_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4882	#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
pradeepvk2208	1:c0c5ac8eac80	4883	/* CnSC Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4884	#define TPM_CnSC_DMA_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4885	#define TPM_CnSC_DMA_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4886	#define TPM_CnSC_ELSA_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4887	#define TPM_CnSC_ELSA_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4888	#define TPM_CnSC_ELSB_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4889	#define TPM_CnSC_ELSB_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4890	#define TPM_CnSC_MSA_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4891	#define TPM_CnSC_MSA_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4892	#define TPM_CnSC_MSB_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4893	#define TPM_CnSC_MSB_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4894	#define TPM_CnSC_CHIE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	4895	#define TPM_CnSC_CHIE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4896	#define TPM_CnSC_CHF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	4897	#define TPM_CnSC_CHF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	4898	/* CnV Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4899	#define TPM_CnV_VAL_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	4900	#define TPM_CnV_VAL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4901	#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
pradeepvk2208	1:c0c5ac8eac80	4902	/* STATUS Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4903	#define TPM_STATUS_CH0F_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	4904	#define TPM_STATUS_CH0F_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	4905	#define TPM_STATUS_CH1F_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4906	#define TPM_STATUS_CH1F_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4907	#define TPM_STATUS_CH2F_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4908	#define TPM_STATUS_CH2F_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4909	#define TPM_STATUS_CH3F_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4910	#define TPM_STATUS_CH3F_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4911	#define TPM_STATUS_CH4F_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4912	#define TPM_STATUS_CH4F_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4913	#define TPM_STATUS_CH5F_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4914	#define TPM_STATUS_CH5F_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4915	#define TPM_STATUS_TOF_MASK 0x100u
pradeepvk2208	1:c0c5ac8eac80	4916	#define TPM_STATUS_TOF_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	4917	/* CONF Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4918	#define TPM_CONF_DOZEEN_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4919	#define TPM_CONF_DOZEEN_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4920	#define TPM_CONF_DBGMODE_MASK 0xC0u
pradeepvk2208	1:c0c5ac8eac80	4921	#define TPM_CONF_DBGMODE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4922	#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
pradeepvk2208	1:c0c5ac8eac80	4923	#define TPM_CONF_GTBEEN_MASK 0x200u
pradeepvk2208	1:c0c5ac8eac80	4924	#define TPM_CONF_GTBEEN_SHIFT 9
pradeepvk2208	1:c0c5ac8eac80	4925	#define TPM_CONF_CSOT_MASK 0x10000u
pradeepvk2208	1:c0c5ac8eac80	4926	#define TPM_CONF_CSOT_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	4927	#define TPM_CONF_CSOO_MASK 0x20000u
pradeepvk2208	1:c0c5ac8eac80	4928	#define TPM_CONF_CSOO_SHIFT 17
pradeepvk2208	1:c0c5ac8eac80	4929	#define TPM_CONF_CROT_MASK 0x40000u
pradeepvk2208	1:c0c5ac8eac80	4930	#define TPM_CONF_CROT_SHIFT 18
pradeepvk2208	1:c0c5ac8eac80	4931	#define TPM_CONF_TRGSEL_MASK 0xF000000u
pradeepvk2208	1:c0c5ac8eac80	4932	#define TPM_CONF_TRGSEL_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	4933	#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
pradeepvk2208	1:c0c5ac8eac80	4934
pradeepvk2208	1:c0c5ac8eac80	4935	/*!
pradeepvk2208	1:c0c5ac8eac80	4936	* @}
pradeepvk2208	1:c0c5ac8eac80	4937	/ / end of group TPM_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	4938
pradeepvk2208	1:c0c5ac8eac80	4939
pradeepvk2208	1:c0c5ac8eac80	4940	/* TPM - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	4941	/** Peripheral TPM0 base address */
pradeepvk2208	1:c0c5ac8eac80	4942	#define TPM0_BASE (0x40038000u)
pradeepvk2208	1:c0c5ac8eac80	4943	/** Peripheral TPM0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	4944	#define TPM0 ((TPM_Type *)TPM0_BASE)
pradeepvk2208	1:c0c5ac8eac80	4945	/** Peripheral TPM1 base address */
pradeepvk2208	1:c0c5ac8eac80	4946	#define TPM1_BASE (0x40039000u)
pradeepvk2208	1:c0c5ac8eac80	4947	/** Peripheral TPM1 base pointer */
pradeepvk2208	1:c0c5ac8eac80	4948	#define TPM1 ((TPM_Type *)TPM1_BASE)
pradeepvk2208	1:c0c5ac8eac80	4949	/** Peripheral TPM2 base address */
pradeepvk2208	1:c0c5ac8eac80	4950	#define TPM2_BASE (0x4003A000u)
pradeepvk2208	1:c0c5ac8eac80	4951	/** Peripheral TPM2 base pointer */
pradeepvk2208	1:c0c5ac8eac80	4952	#define TPM2 ((TPM_Type *)TPM2_BASE)
pradeepvk2208	1:c0c5ac8eac80	4953	/** Array initializer of TPM peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	4954	#define TPM_BASES { TPM0, TPM1, TPM2 }
pradeepvk2208	1:c0c5ac8eac80	4955
pradeepvk2208	1:c0c5ac8eac80	4956	/*!
pradeepvk2208	1:c0c5ac8eac80	4957	* @}
pradeepvk2208	1:c0c5ac8eac80	4958	/ / end of group TPM_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	4959
pradeepvk2208	1:c0c5ac8eac80	4960
pradeepvk2208	1:c0c5ac8eac80	4961	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4962	-- TSI Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4963	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4964
pradeepvk2208	1:c0c5ac8eac80	4965	/*!
pradeepvk2208	1:c0c5ac8eac80	4966	* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	4967	* @{
pradeepvk2208	1:c0c5ac8eac80	4968	*/
pradeepvk2208	1:c0c5ac8eac80	4969
pradeepvk2208	1:c0c5ac8eac80	4970	/** TSI - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	4971	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	4972	__IO uint32_t GENCS; /*< TSI General Control and Status Register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	4973	__IO uint32_t DATA; /*< TSI DATA Register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	4974	__IO uint32_t TSHD; /*< TSI Threshold Register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	4975	} TSI_Type;
pradeepvk2208	1:c0c5ac8eac80	4976
pradeepvk2208	1:c0c5ac8eac80	4977	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	4978	-- TSI Register Masks
pradeepvk2208	1:c0c5ac8eac80	4979	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	4980
pradeepvk2208	1:c0c5ac8eac80	4981	/*!
pradeepvk2208	1:c0c5ac8eac80	4982	* @addtogroup TSI_Register_Masks TSI Register Masks
pradeepvk2208	1:c0c5ac8eac80	4983	* @{
pradeepvk2208	1:c0c5ac8eac80	4984	*/
pradeepvk2208	1:c0c5ac8eac80	4985
pradeepvk2208	1:c0c5ac8eac80	4986	/* GENCS Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	4987	#define TSI_GENCS_CURSW_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	4988	#define TSI_GENCS_CURSW_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	4989	#define TSI_GENCS_EOSF_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	4990	#define TSI_GENCS_EOSF_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	4991	#define TSI_GENCS_SCNIP_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	4992	#define TSI_GENCS_SCNIP_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	4993	#define TSI_GENCS_STM_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	4994	#define TSI_GENCS_STM_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	4995	#define TSI_GENCS_STPE_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	4996	#define TSI_GENCS_STPE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	4997	#define TSI_GENCS_TSIIEN_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	4998	#define TSI_GENCS_TSIIEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	4999	#define TSI_GENCS_TSIEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5000	#define TSI_GENCS_TSIEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5001	#define TSI_GENCS_NSCN_MASK 0x1F00u
pradeepvk2208	1:c0c5ac8eac80	5002	#define TSI_GENCS_NSCN_SHIFT 8
pradeepvk2208	1:c0c5ac8eac80	5003	#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
pradeepvk2208	1:c0c5ac8eac80	5004	#define TSI_GENCS_PS_MASK 0xE000u
pradeepvk2208	1:c0c5ac8eac80	5005	#define TSI_GENCS_PS_SHIFT 13
pradeepvk2208	1:c0c5ac8eac80	5006	#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
pradeepvk2208	1:c0c5ac8eac80	5007	#define TSI_GENCS_EXTCHRG_MASK 0x70000u
pradeepvk2208	1:c0c5ac8eac80	5008	#define TSI_GENCS_EXTCHRG_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	5009	#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
pradeepvk2208	1:c0c5ac8eac80	5010	#define TSI_GENCS_DVOLT_MASK 0x180000u
pradeepvk2208	1:c0c5ac8eac80	5011	#define TSI_GENCS_DVOLT_SHIFT 19
pradeepvk2208	1:c0c5ac8eac80	5012	#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
pradeepvk2208	1:c0c5ac8eac80	5013	#define TSI_GENCS_REFCHRG_MASK 0xE00000u
pradeepvk2208	1:c0c5ac8eac80	5014	#define TSI_GENCS_REFCHRG_SHIFT 21
pradeepvk2208	1:c0c5ac8eac80	5015	#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
pradeepvk2208	1:c0c5ac8eac80	5016	#define TSI_GENCS_MODE_MASK 0xF000000u
pradeepvk2208	1:c0c5ac8eac80	5017	#define TSI_GENCS_MODE_SHIFT 24
pradeepvk2208	1:c0c5ac8eac80	5018	#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
pradeepvk2208	1:c0c5ac8eac80	5019	#define TSI_GENCS_ESOR_MASK 0x10000000u
pradeepvk2208	1:c0c5ac8eac80	5020	#define TSI_GENCS_ESOR_SHIFT 28
pradeepvk2208	1:c0c5ac8eac80	5021	#define TSI_GENCS_OUTRGF_MASK 0x80000000u
pradeepvk2208	1:c0c5ac8eac80	5022	#define TSI_GENCS_OUTRGF_SHIFT 31
pradeepvk2208	1:c0c5ac8eac80	5023	/* DATA Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5024	#define TSI_DATA_TSICNT_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	5025	#define TSI_DATA_TSICNT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5026	#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
pradeepvk2208	1:c0c5ac8eac80	5027	#define TSI_DATA_SWTS_MASK 0x400000u
pradeepvk2208	1:c0c5ac8eac80	5028	#define TSI_DATA_SWTS_SHIFT 22
pradeepvk2208	1:c0c5ac8eac80	5029	#define TSI_DATA_DMAEN_MASK 0x800000u
pradeepvk2208	1:c0c5ac8eac80	5030	#define TSI_DATA_DMAEN_SHIFT 23
pradeepvk2208	1:c0c5ac8eac80	5031	#define TSI_DATA_TSICH_MASK 0xF0000000u
pradeepvk2208	1:c0c5ac8eac80	5032	#define TSI_DATA_TSICH_SHIFT 28
pradeepvk2208	1:c0c5ac8eac80	5033	#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
pradeepvk2208	1:c0c5ac8eac80	5034	/* TSHD Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5035	#define TSI_TSHD_THRESL_MASK 0xFFFFu
pradeepvk2208	1:c0c5ac8eac80	5036	#define TSI_TSHD_THRESL_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5037	#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
pradeepvk2208	1:c0c5ac8eac80	5038	#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
pradeepvk2208	1:c0c5ac8eac80	5039	#define TSI_TSHD_THRESH_SHIFT 16
pradeepvk2208	1:c0c5ac8eac80	5040	#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
pradeepvk2208	1:c0c5ac8eac80	5041
pradeepvk2208	1:c0c5ac8eac80	5042	/*!
pradeepvk2208	1:c0c5ac8eac80	5043	* @}
pradeepvk2208	1:c0c5ac8eac80	5044	/ / end of group TSI_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	5045
pradeepvk2208	1:c0c5ac8eac80	5046
pradeepvk2208	1:c0c5ac8eac80	5047	/* TSI - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	5048	/** Peripheral TSI0 base address */
pradeepvk2208	1:c0c5ac8eac80	5049	#define TSI0_BASE (0x40045000u)
pradeepvk2208	1:c0c5ac8eac80	5050	/** Peripheral TSI0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	5051	#define TSI0 ((TSI_Type *)TSI0_BASE)
pradeepvk2208	1:c0c5ac8eac80	5052	/** Array initializer of TSI peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	5053	#define TSI_BASES { TSI0 }
pradeepvk2208	1:c0c5ac8eac80	5054
pradeepvk2208	1:c0c5ac8eac80	5055	/*!
pradeepvk2208	1:c0c5ac8eac80	5056	* @}
pradeepvk2208	1:c0c5ac8eac80	5057	/ / end of group TSI_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	5058
pradeepvk2208	1:c0c5ac8eac80	5059
pradeepvk2208	1:c0c5ac8eac80	5060	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	5061	-- UART Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	5062	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	5063
pradeepvk2208	1:c0c5ac8eac80	5064	/*!
pradeepvk2208	1:c0c5ac8eac80	5065	* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	5066	* @{
pradeepvk2208	1:c0c5ac8eac80	5067	*/
pradeepvk2208	1:c0c5ac8eac80	5068
pradeepvk2208	1:c0c5ac8eac80	5069	/** UART - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	5070	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	5071	__IO uint8_t BDH; /*< UART Baud Rate Register: High, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	5072	__IO uint8_t BDL; /*< UART Baud Rate Register: Low, offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	5073	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	5074	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
pradeepvk2208	1:c0c5ac8eac80	5075	__I uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	5076	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
pradeepvk2208	1:c0c5ac8eac80	5077	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
pradeepvk2208	1:c0c5ac8eac80	5078	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
pradeepvk2208	1:c0c5ac8eac80	5079	__IO uint8_t C4; /*< UART Control Register 4, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	5080	} UART_Type;
pradeepvk2208	1:c0c5ac8eac80	5081
pradeepvk2208	1:c0c5ac8eac80	5082	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	5083	-- UART Register Masks
pradeepvk2208	1:c0c5ac8eac80	5084	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	5085
pradeepvk2208	1:c0c5ac8eac80	5086	/*!
pradeepvk2208	1:c0c5ac8eac80	5087	* @addtogroup UART_Register_Masks UART Register Masks
pradeepvk2208	1:c0c5ac8eac80	5088	* @{
pradeepvk2208	1:c0c5ac8eac80	5089	*/
pradeepvk2208	1:c0c5ac8eac80	5090
pradeepvk2208	1:c0c5ac8eac80	5091	/* BDH Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5092	#define UART_BDH_SBR_MASK 0x1Fu
pradeepvk2208	1:c0c5ac8eac80	5093	#define UART_BDH_SBR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5094	#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
pradeepvk2208	1:c0c5ac8eac80	5095	#define UART_BDH_SBNS_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5096	#define UART_BDH_SBNS_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5097	#define UART_BDH_RXEDGIE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5098	#define UART_BDH_RXEDGIE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5099	#define UART_BDH_LBKDIE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5100	#define UART_BDH_LBKDIE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5101	/* BDL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5102	#define UART_BDL_SBR_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	5103	#define UART_BDL_SBR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5104	#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
pradeepvk2208	1:c0c5ac8eac80	5105	/* C1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5106	#define UART_C1_PT_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5107	#define UART_C1_PT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5108	#define UART_C1_PE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5109	#define UART_C1_PE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5110	#define UART_C1_ILT_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5111	#define UART_C1_ILT_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5112	#define UART_C1_WAKE_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5113	#define UART_C1_WAKE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5114	#define UART_C1_M_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5115	#define UART_C1_M_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5116	#define UART_C1_RSRC_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5117	#define UART_C1_RSRC_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5118	#define UART_C1_UARTSWAI_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5119	#define UART_C1_UARTSWAI_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5120	#define UART_C1_LOOPS_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5121	#define UART_C1_LOOPS_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5122	/* C2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5123	#define UART_C2_SBK_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5124	#define UART_C2_SBK_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5125	#define UART_C2_RWU_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5126	#define UART_C2_RWU_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5127	#define UART_C2_RE_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5128	#define UART_C2_RE_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5129	#define UART_C2_TE_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5130	#define UART_C2_TE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5131	#define UART_C2_ILIE_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5132	#define UART_C2_ILIE_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5133	#define UART_C2_RIE_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5134	#define UART_C2_RIE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5135	#define UART_C2_TCIE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5136	#define UART_C2_TCIE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5137	#define UART_C2_TIE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5138	#define UART_C2_TIE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5139	/* S1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5140	#define UART_S1_PF_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5141	#define UART_S1_PF_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5142	#define UART_S1_FE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5143	#define UART_S1_FE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5144	#define UART_S1_NF_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5145	#define UART_S1_NF_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5146	#define UART_S1_OR_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5147	#define UART_S1_OR_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5148	#define UART_S1_IDLE_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5149	#define UART_S1_IDLE_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5150	#define UART_S1_RDRF_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5151	#define UART_S1_RDRF_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5152	#define UART_S1_TC_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5153	#define UART_S1_TC_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5154	#define UART_S1_TDRE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5155	#define UART_S1_TDRE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5156	/* S2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5157	#define UART_S2_RAF_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5158	#define UART_S2_RAF_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5159	#define UART_S2_LBKDE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5160	#define UART_S2_LBKDE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5161	#define UART_S2_BRK13_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5162	#define UART_S2_BRK13_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5163	#define UART_S2_RWUID_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5164	#define UART_S2_RWUID_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5165	#define UART_S2_RXINV_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5166	#define UART_S2_RXINV_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5167	#define UART_S2_RXEDGIF_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5168	#define UART_S2_RXEDGIF_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5169	#define UART_S2_LBKDIF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5170	#define UART_S2_LBKDIF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5171	/* C3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5172	#define UART_C3_PEIE_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5173	#define UART_C3_PEIE_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5174	#define UART_C3_FEIE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5175	#define UART_C3_FEIE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5176	#define UART_C3_NEIE_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5177	#define UART_C3_NEIE_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5178	#define UART_C3_ORIE_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5179	#define UART_C3_ORIE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5180	#define UART_C3_TXINV_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5181	#define UART_C3_TXINV_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5182	#define UART_C3_TXDIR_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5183	#define UART_C3_TXDIR_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5184	#define UART_C3_T8_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5185	#define UART_C3_T8_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5186	#define UART_C3_R8_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5187	#define UART_C3_R8_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5188	/* D Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5189	#define UART_D_R0T0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5190	#define UART_D_R0T0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5191	#define UART_D_R1T1_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5192	#define UART_D_R1T1_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5193	#define UART_D_R2T2_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5194	#define UART_D_R2T2_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5195	#define UART_D_R3T3_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5196	#define UART_D_R3T3_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5197	#define UART_D_R4T4_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5198	#define UART_D_R4T4_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5199	#define UART_D_R5T5_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5200	#define UART_D_R5T5_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5201	#define UART_D_R6T6_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5202	#define UART_D_R6T6_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5203	#define UART_D_R7T7_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5204	#define UART_D_R7T7_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5205	/* C4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5206	#define UART_C4_RDMAS_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5207	#define UART_C4_RDMAS_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5208	#define UART_C4_TDMAS_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5209	#define UART_C4_TDMAS_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5210
pradeepvk2208	1:c0c5ac8eac80	5211	/*!
pradeepvk2208	1:c0c5ac8eac80	5212	* @}
pradeepvk2208	1:c0c5ac8eac80	5213	/ / end of group UART_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	5214
pradeepvk2208	1:c0c5ac8eac80	5215
pradeepvk2208	1:c0c5ac8eac80	5216	/* UART - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	5217	/** Peripheral UART1 base address */
pradeepvk2208	1:c0c5ac8eac80	5218	#define UART1_BASE (0x4006B000u)
pradeepvk2208	1:c0c5ac8eac80	5219	/** Peripheral UART1 base pointer */
pradeepvk2208	1:c0c5ac8eac80	5220	#define UART1 ((UART_Type *)UART1_BASE)
pradeepvk2208	1:c0c5ac8eac80	5221	/** Peripheral UART2 base address */
pradeepvk2208	1:c0c5ac8eac80	5222	#define UART2_BASE (0x4006C000u)
pradeepvk2208	1:c0c5ac8eac80	5223	/** Peripheral UART2 base pointer */
pradeepvk2208	1:c0c5ac8eac80	5224	#define UART2 ((UART_Type *)UART2_BASE)
pradeepvk2208	1:c0c5ac8eac80	5225	/** Array initializer of UART peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	5226	#define UART_BASES { UART1, UART2 }
pradeepvk2208	1:c0c5ac8eac80	5227
pradeepvk2208	1:c0c5ac8eac80	5228	/*!
pradeepvk2208	1:c0c5ac8eac80	5229	* @}
pradeepvk2208	1:c0c5ac8eac80	5230	/ / end of group UART_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	5231
pradeepvk2208	1:c0c5ac8eac80	5232
pradeepvk2208	1:c0c5ac8eac80	5233	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	5234	-- UART0 Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	5235	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	5236
pradeepvk2208	1:c0c5ac8eac80	5237	/*!
pradeepvk2208	1:c0c5ac8eac80	5238	* @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	5239	* @{
pradeepvk2208	1:c0c5ac8eac80	5240	*/
pradeepvk2208	1:c0c5ac8eac80	5241
pradeepvk2208	1:c0c5ac8eac80	5242	/** UART0 - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	5243	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	5244	__IO uint8_t BDH; /*< UART Baud Rate Register High, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	5245	__IO uint8_t BDL; /*< UART Baud Rate Register Low, offset: 0x1 /
pradeepvk2208	1:c0c5ac8eac80	5246	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
pradeepvk2208	1:c0c5ac8eac80	5247	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
pradeepvk2208	1:c0c5ac8eac80	5248	__IO uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	5249	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
pradeepvk2208	1:c0c5ac8eac80	5250	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
pradeepvk2208	1:c0c5ac8eac80	5251	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
pradeepvk2208	1:c0c5ac8eac80	5252	__IO uint8_t MA1; /*< UART Match Address Registers 1, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	5253	__IO uint8_t MA2; /*< UART Match Address Registers 2, offset: 0x9 /
pradeepvk2208	1:c0c5ac8eac80	5254	__IO uint8_t C4; /*< UART Control Register 4, offset: 0xA /
pradeepvk2208	1:c0c5ac8eac80	5255	__IO uint8_t C5; /*< UART Control Register 5, offset: 0xB /
pradeepvk2208	1:c0c5ac8eac80	5256	} UART0_Type;
pradeepvk2208	1:c0c5ac8eac80	5257
pradeepvk2208	1:c0c5ac8eac80	5258	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	5259	-- UART0 Register Masks
pradeepvk2208	1:c0c5ac8eac80	5260	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	5261
pradeepvk2208	1:c0c5ac8eac80	5262	/*!
pradeepvk2208	1:c0c5ac8eac80	5263	* @addtogroup UART0_Register_Masks UART0 Register Masks
pradeepvk2208	1:c0c5ac8eac80	5264	* @{
pradeepvk2208	1:c0c5ac8eac80	5265	*/
pradeepvk2208	1:c0c5ac8eac80	5266
pradeepvk2208	1:c0c5ac8eac80	5267	/* BDH Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5268	#define UART0_BDH_SBR_MASK 0x1Fu
pradeepvk2208	1:c0c5ac8eac80	5269	#define UART0_BDH_SBR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5270	#define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
pradeepvk2208	1:c0c5ac8eac80	5271	#define UART0_BDH_SBNS_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5272	#define UART0_BDH_SBNS_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5273	#define UART0_BDH_RXEDGIE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5274	#define UART0_BDH_RXEDGIE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5275	#define UART0_BDH_LBKDIE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5276	#define UART0_BDH_LBKDIE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5277	/* BDL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5278	#define UART0_BDL_SBR_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	5279	#define UART0_BDL_SBR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5280	#define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
pradeepvk2208	1:c0c5ac8eac80	5281	/* C1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5282	#define UART0_C1_PT_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5283	#define UART0_C1_PT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5284	#define UART0_C1_PE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5285	#define UART0_C1_PE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5286	#define UART0_C1_ILT_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5287	#define UART0_C1_ILT_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5288	#define UART0_C1_WAKE_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5289	#define UART0_C1_WAKE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5290	#define UART0_C1_M_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5291	#define UART0_C1_M_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5292	#define UART0_C1_RSRC_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5293	#define UART0_C1_RSRC_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5294	#define UART0_C1_DOZEEN_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5295	#define UART0_C1_DOZEEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5296	#define UART0_C1_LOOPS_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5297	#define UART0_C1_LOOPS_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5298	/* C2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5299	#define UART0_C2_SBK_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5300	#define UART0_C2_SBK_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5301	#define UART0_C2_RWU_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5302	#define UART0_C2_RWU_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5303	#define UART0_C2_RE_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5304	#define UART0_C2_RE_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5305	#define UART0_C2_TE_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5306	#define UART0_C2_TE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5307	#define UART0_C2_ILIE_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5308	#define UART0_C2_ILIE_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5309	#define UART0_C2_RIE_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5310	#define UART0_C2_RIE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5311	#define UART0_C2_TCIE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5312	#define UART0_C2_TCIE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5313	#define UART0_C2_TIE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5314	#define UART0_C2_TIE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5315	/* S1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5316	#define UART0_S1_PF_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5317	#define UART0_S1_PF_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5318	#define UART0_S1_FE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5319	#define UART0_S1_FE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5320	#define UART0_S1_NF_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5321	#define UART0_S1_NF_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5322	#define UART0_S1_OR_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5323	#define UART0_S1_OR_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5324	#define UART0_S1_IDLE_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5325	#define UART0_S1_IDLE_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5326	#define UART0_S1_RDRF_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5327	#define UART0_S1_RDRF_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5328	#define UART0_S1_TC_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5329	#define UART0_S1_TC_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5330	#define UART0_S1_TDRE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5331	#define UART0_S1_TDRE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5332	/* S2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5333	#define UART0_S2_RAF_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5334	#define UART0_S2_RAF_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5335	#define UART0_S2_LBKDE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5336	#define UART0_S2_LBKDE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5337	#define UART0_S2_BRK13_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5338	#define UART0_S2_BRK13_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5339	#define UART0_S2_RWUID_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5340	#define UART0_S2_RWUID_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5341	#define UART0_S2_RXINV_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5342	#define UART0_S2_RXINV_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5343	#define UART0_S2_MSBF_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5344	#define UART0_S2_MSBF_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5345	#define UART0_S2_RXEDGIF_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5346	#define UART0_S2_RXEDGIF_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5347	#define UART0_S2_LBKDIF_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5348	#define UART0_S2_LBKDIF_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5349	/* C3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5350	#define UART0_C3_PEIE_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5351	#define UART0_C3_PEIE_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5352	#define UART0_C3_FEIE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5353	#define UART0_C3_FEIE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5354	#define UART0_C3_NEIE_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5355	#define UART0_C3_NEIE_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5356	#define UART0_C3_ORIE_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5357	#define UART0_C3_ORIE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5358	#define UART0_C3_TXINV_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5359	#define UART0_C3_TXINV_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5360	#define UART0_C3_TXDIR_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5361	#define UART0_C3_TXDIR_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5362	#define UART0_C3_R9T8_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5363	#define UART0_C3_R9T8_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5364	#define UART0_C3_R8T9_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5365	#define UART0_C3_R8T9_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5366	/* D Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5367	#define UART0_D_R0T0_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5368	#define UART0_D_R0T0_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5369	#define UART0_D_R1T1_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5370	#define UART0_D_R1T1_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5371	#define UART0_D_R2T2_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5372	#define UART0_D_R2T2_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5373	#define UART0_D_R3T3_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5374	#define UART0_D_R3T3_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5375	#define UART0_D_R4T4_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5376	#define UART0_D_R4T4_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5377	#define UART0_D_R5T5_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5378	#define UART0_D_R5T5_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5379	#define UART0_D_R6T6_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5380	#define UART0_D_R6T6_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5381	#define UART0_D_R7T7_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5382	#define UART0_D_R7T7_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5383	/* MA1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5384	#define UART0_MA1_MA_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	5385	#define UART0_MA1_MA_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5386	#define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
pradeepvk2208	1:c0c5ac8eac80	5387	/* MA2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5388	#define UART0_MA2_MA_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	5389	#define UART0_MA2_MA_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5390	#define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
pradeepvk2208	1:c0c5ac8eac80	5391	/* C4 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5392	#define UART0_C4_OSR_MASK 0x1Fu
pradeepvk2208	1:c0c5ac8eac80	5393	#define UART0_C4_OSR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5394	#define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
pradeepvk2208	1:c0c5ac8eac80	5395	#define UART0_C4_M10_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5396	#define UART0_C4_M10_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5397	#define UART0_C4_MAEN2_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5398	#define UART0_C4_MAEN2_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5399	#define UART0_C4_MAEN1_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5400	#define UART0_C4_MAEN1_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5401	/* C5 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5402	#define UART0_C5_RESYNCDIS_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5403	#define UART0_C5_RESYNCDIS_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5404	#define UART0_C5_BOTHEDGE_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5405	#define UART0_C5_BOTHEDGE_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5406	#define UART0_C5_RDMAE_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5407	#define UART0_C5_RDMAE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5408	#define UART0_C5_TDMAE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5409	#define UART0_C5_TDMAE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5410
pradeepvk2208	1:c0c5ac8eac80	5411	/*!
pradeepvk2208	1:c0c5ac8eac80	5412	* @}
pradeepvk2208	1:c0c5ac8eac80	5413	/ / end of group UART0_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	5414
pradeepvk2208	1:c0c5ac8eac80	5415
pradeepvk2208	1:c0c5ac8eac80	5416	/* UART0 - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	5417	/** Peripheral UART0 base address */
pradeepvk2208	1:c0c5ac8eac80	5418	#define UART0_BASE (0x4006A000u)
pradeepvk2208	1:c0c5ac8eac80	5419	/** Peripheral UART0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	5420	#define UART0 ((UART0_Type *)UART0_BASE)
pradeepvk2208	1:c0c5ac8eac80	5421	/** Array initializer of UART0 peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	5422	#define UART0_BASES { UART0 }
pradeepvk2208	1:c0c5ac8eac80	5423
pradeepvk2208	1:c0c5ac8eac80	5424	/*!
pradeepvk2208	1:c0c5ac8eac80	5425	* @}
pradeepvk2208	1:c0c5ac8eac80	5426	/ / end of group UART0_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	5427
pradeepvk2208	1:c0c5ac8eac80	5428
pradeepvk2208	1:c0c5ac8eac80	5429	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	5430	-- USB Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	5431	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	5432
pradeepvk2208	1:c0c5ac8eac80	5433	/*!
pradeepvk2208	1:c0c5ac8eac80	5434	* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
pradeepvk2208	1:c0c5ac8eac80	5435	* @{
pradeepvk2208	1:c0c5ac8eac80	5436	*/
pradeepvk2208	1:c0c5ac8eac80	5437
pradeepvk2208	1:c0c5ac8eac80	5438	/** USB - Register Layout Typedef */
pradeepvk2208	1:c0c5ac8eac80	5439	typedef struct {
pradeepvk2208	1:c0c5ac8eac80	5440	__I uint8_t PERID; /*< Peripheral ID register, offset: 0x0 /
pradeepvk2208	1:c0c5ac8eac80	5441	uint8_t RESERVED_0[3];
pradeepvk2208	1:c0c5ac8eac80	5442	__I uint8_t IDCOMP; /*< Peripheral ID Complement register, offset: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	5443	uint8_t RESERVED_1[3];
pradeepvk2208	1:c0c5ac8eac80	5444	__I uint8_t REV; /*< Peripheral Revision register, offset: 0x8 /
pradeepvk2208	1:c0c5ac8eac80	5445	uint8_t RESERVED_2[3];
pradeepvk2208	1:c0c5ac8eac80	5446	__I uint8_t ADDINFO; /*< Peripheral Additional Info register, offset: 0xC /
pradeepvk2208	1:c0c5ac8eac80	5447	uint8_t RESERVED_3[3];
pradeepvk2208	1:c0c5ac8eac80	5448	__IO uint8_t OTGISTAT; /*< OTG Interrupt Status register, offset: 0x10 /
pradeepvk2208	1:c0c5ac8eac80	5449	uint8_t RESERVED_4[3];
pradeepvk2208	1:c0c5ac8eac80	5450	__IO uint8_t OTGICR; /*< OTG Interrupt Control Register, offset: 0x14 /
pradeepvk2208	1:c0c5ac8eac80	5451	uint8_t RESERVED_5[3];
pradeepvk2208	1:c0c5ac8eac80	5452	__IO uint8_t OTGSTAT; /*< OTG Status register, offset: 0x18 /
pradeepvk2208	1:c0c5ac8eac80	5453	uint8_t RESERVED_6[3];
pradeepvk2208	1:c0c5ac8eac80	5454	__IO uint8_t OTGCTL; /*< OTG Control register, offset: 0x1C /
pradeepvk2208	1:c0c5ac8eac80	5455	uint8_t RESERVED_7[99];
pradeepvk2208	1:c0c5ac8eac80	5456	__IO uint8_t ISTAT; /*< Interrupt Status register, offset: 0x80 /
pradeepvk2208	1:c0c5ac8eac80	5457	uint8_t RESERVED_8[3];
pradeepvk2208	1:c0c5ac8eac80	5458	__IO uint8_t INTEN; /*< Interrupt Enable register, offset: 0x84 /
pradeepvk2208	1:c0c5ac8eac80	5459	uint8_t RESERVED_9[3];
pradeepvk2208	1:c0c5ac8eac80	5460	__IO uint8_t ERRSTAT; /*< Error Interrupt Status register, offset: 0x88 /
pradeepvk2208	1:c0c5ac8eac80	5461	uint8_t RESERVED_10[3];
pradeepvk2208	1:c0c5ac8eac80	5462	__IO uint8_t ERREN; /*< Error Interrupt Enable register, offset: 0x8C /
pradeepvk2208	1:c0c5ac8eac80	5463	uint8_t RESERVED_11[3];
pradeepvk2208	1:c0c5ac8eac80	5464	__I uint8_t STAT; /*< Status register, offset: 0x90 /
pradeepvk2208	1:c0c5ac8eac80	5465	uint8_t RESERVED_12[3];
pradeepvk2208	1:c0c5ac8eac80	5466	__IO uint8_t CTL; /*< Control register, offset: 0x94 /
pradeepvk2208	1:c0c5ac8eac80	5467	uint8_t RESERVED_13[3];
pradeepvk2208	1:c0c5ac8eac80	5468	__IO uint8_t ADDR; /*< Address register, offset: 0x98 /
pradeepvk2208	1:c0c5ac8eac80	5469	uint8_t RESERVED_14[3];
pradeepvk2208	1:c0c5ac8eac80	5470	__IO uint8_t BDTPAGE1; /*< BDT Page Register 1, offset: 0x9C /
pradeepvk2208	1:c0c5ac8eac80	5471	uint8_t RESERVED_15[3];
pradeepvk2208	1:c0c5ac8eac80	5472	__IO uint8_t FRMNUML; /*< Frame Number Register Low, offset: 0xA0 /
pradeepvk2208	1:c0c5ac8eac80	5473	uint8_t RESERVED_16[3];
pradeepvk2208	1:c0c5ac8eac80	5474	__IO uint8_t FRMNUMH; /*< Frame Number Register High, offset: 0xA4 /
pradeepvk2208	1:c0c5ac8eac80	5475	uint8_t RESERVED_17[3];
pradeepvk2208	1:c0c5ac8eac80	5476	__IO uint8_t TOKEN; /*< Token register, offset: 0xA8 /
pradeepvk2208	1:c0c5ac8eac80	5477	uint8_t RESERVED_18[3];
pradeepvk2208	1:c0c5ac8eac80	5478	__IO uint8_t SOFTHLD; /*< SOF Threshold Register, offset: 0xAC /
pradeepvk2208	1:c0c5ac8eac80	5479	uint8_t RESERVED_19[3];
pradeepvk2208	1:c0c5ac8eac80	5480	__IO uint8_t BDTPAGE2; /*< BDT Page Register 2, offset: 0xB0 /
pradeepvk2208	1:c0c5ac8eac80	5481	uint8_t RESERVED_20[3];
pradeepvk2208	1:c0c5ac8eac80	5482	__IO uint8_t BDTPAGE3; /*< BDT Page Register 3, offset: 0xB4 /
pradeepvk2208	1:c0c5ac8eac80	5483	uint8_t RESERVED_21[11];
pradeepvk2208	1:c0c5ac8eac80	5484	struct { /* offset: 0xC0, array step: 0x4 */
pradeepvk2208	1:c0c5ac8eac80	5485	__IO uint8_t ENDPT; /*< Endpoint Control register, array offset: 0xC0, array step: 0x4 /
pradeepvk2208	1:c0c5ac8eac80	5486	uint8_t RESERVED_0[3];
pradeepvk2208	1:c0c5ac8eac80	5487	} ENDPOINT[16];
pradeepvk2208	1:c0c5ac8eac80	5488	__IO uint8_t USBCTRL; /*< USB Control register, offset: 0x100 /
pradeepvk2208	1:c0c5ac8eac80	5489	uint8_t RESERVED_22[3];
pradeepvk2208	1:c0c5ac8eac80	5490	__I uint8_t OBSERVE; /*< USB OTG Observe register, offset: 0x104 /
pradeepvk2208	1:c0c5ac8eac80	5491	uint8_t RESERVED_23[3];
pradeepvk2208	1:c0c5ac8eac80	5492	__IO uint8_t CONTROL; /*< USB OTG Control register, offset: 0x108 /
pradeepvk2208	1:c0c5ac8eac80	5493	uint8_t RESERVED_24[3];
pradeepvk2208	1:c0c5ac8eac80	5494	__IO uint8_t USBTRC0; /*< USB Transceiver Control Register 0, offset: 0x10C /
pradeepvk2208	1:c0c5ac8eac80	5495	uint8_t RESERVED_25[7];
pradeepvk2208	1:c0c5ac8eac80	5496	__IO uint8_t USBFRMADJUST; /*< Frame Adjust Register, offset: 0x114 /
pradeepvk2208	1:c0c5ac8eac80	5497	} USB_Type;
pradeepvk2208	1:c0c5ac8eac80	5498
pradeepvk2208	1:c0c5ac8eac80	5499	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	5500	-- USB Register Masks
pradeepvk2208	1:c0c5ac8eac80	5501	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	5502
pradeepvk2208	1:c0c5ac8eac80	5503	/*!
pradeepvk2208	1:c0c5ac8eac80	5504	* @addtogroup USB_Register_Masks USB Register Masks
pradeepvk2208	1:c0c5ac8eac80	5505	* @{
pradeepvk2208	1:c0c5ac8eac80	5506	*/
pradeepvk2208	1:c0c5ac8eac80	5507
pradeepvk2208	1:c0c5ac8eac80	5508	/* PERID Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5509	#define USB_PERID_ID_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	5510	#define USB_PERID_ID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5511	#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
pradeepvk2208	1:c0c5ac8eac80	5512	/* IDCOMP Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5513	#define USB_IDCOMP_NID_MASK 0x3Fu
pradeepvk2208	1:c0c5ac8eac80	5514	#define USB_IDCOMP_NID_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5515	#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
pradeepvk2208	1:c0c5ac8eac80	5516	/* REV Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5517	#define USB_REV_REV_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	5518	#define USB_REV_REV_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5519	#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
pradeepvk2208	1:c0c5ac8eac80	5520	/* ADDINFO Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5521	#define USB_ADDINFO_IEHOST_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5522	#define USB_ADDINFO_IEHOST_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5523	#define USB_ADDINFO_IRQNUM_MASK 0xF8u
pradeepvk2208	1:c0c5ac8eac80	5524	#define USB_ADDINFO_IRQNUM_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5525	#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
pradeepvk2208	1:c0c5ac8eac80	5526	/* OTGISTAT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5527	#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5528	#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5529	#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5530	#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5531	#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5532	#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5533	#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5534	#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5535	#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5536	#define USB_OTGISTAT_ONEMSEC_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5537	#define USB_OTGISTAT_IDCHG_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5538	#define USB_OTGISTAT_IDCHG_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5539	/* OTGICR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5540	#define USB_OTGICR_AVBUSEN_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5541	#define USB_OTGICR_AVBUSEN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5542	#define USB_OTGICR_BSESSEN_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5543	#define USB_OTGICR_BSESSEN_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5544	#define USB_OTGICR_SESSVLDEN_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5545	#define USB_OTGICR_SESSVLDEN_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5546	#define USB_OTGICR_LINESTATEEN_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5547	#define USB_OTGICR_LINESTATEEN_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5548	#define USB_OTGICR_ONEMSECEN_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5549	#define USB_OTGICR_ONEMSECEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5550	#define USB_OTGICR_IDEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5551	#define USB_OTGICR_IDEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5552	/* OTGSTAT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5553	#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5554	#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5555	#define USB_OTGSTAT_BSESSEND_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5556	#define USB_OTGSTAT_BSESSEND_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5557	#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5558	#define USB_OTGSTAT_SESS_VLD_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5559	#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5560	#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5561	#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5562	#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5563	#define USB_OTGSTAT_ID_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5564	#define USB_OTGSTAT_ID_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5565	/* OTGCTL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5566	#define USB_OTGCTL_OTGEN_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5567	#define USB_OTGCTL_OTGEN_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5568	#define USB_OTGCTL_DMLOW_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5569	#define USB_OTGCTL_DMLOW_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5570	#define USB_OTGCTL_DPLOW_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5571	#define USB_OTGCTL_DPLOW_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5572	#define USB_OTGCTL_DPHIGH_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5573	#define USB_OTGCTL_DPHIGH_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5574	/* ISTAT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5575	#define USB_ISTAT_USBRST_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5576	#define USB_ISTAT_USBRST_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5577	#define USB_ISTAT_ERROR_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5578	#define USB_ISTAT_ERROR_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5579	#define USB_ISTAT_SOFTOK_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5580	#define USB_ISTAT_SOFTOK_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5581	#define USB_ISTAT_TOKDNE_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5582	#define USB_ISTAT_TOKDNE_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5583	#define USB_ISTAT_SLEEP_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5584	#define USB_ISTAT_SLEEP_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5585	#define USB_ISTAT_RESUME_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5586	#define USB_ISTAT_RESUME_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5587	#define USB_ISTAT_ATTACH_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5588	#define USB_ISTAT_ATTACH_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5589	#define USB_ISTAT_STALL_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5590	#define USB_ISTAT_STALL_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5591	/* INTEN Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5592	#define USB_INTEN_USBRSTEN_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5593	#define USB_INTEN_USBRSTEN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5594	#define USB_INTEN_ERROREN_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5595	#define USB_INTEN_ERROREN_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5596	#define USB_INTEN_SOFTOKEN_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5597	#define USB_INTEN_SOFTOKEN_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5598	#define USB_INTEN_TOKDNEEN_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5599	#define USB_INTEN_TOKDNEEN_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5600	#define USB_INTEN_SLEEPEN_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5601	#define USB_INTEN_SLEEPEN_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5602	#define USB_INTEN_RESUMEEN_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5603	#define USB_INTEN_RESUMEEN_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5604	#define USB_INTEN_ATTACHEN_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5605	#define USB_INTEN_ATTACHEN_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5606	#define USB_INTEN_STALLEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5607	#define USB_INTEN_STALLEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5608	/* ERRSTAT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5609	#define USB_ERRSTAT_PIDERR_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5610	#define USB_ERRSTAT_PIDERR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5611	#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5612	#define USB_ERRSTAT_CRC5EOF_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5613	#define USB_ERRSTAT_CRC16_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5614	#define USB_ERRSTAT_CRC16_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5615	#define USB_ERRSTAT_DFN8_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5616	#define USB_ERRSTAT_DFN8_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5617	#define USB_ERRSTAT_BTOERR_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5618	#define USB_ERRSTAT_BTOERR_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5619	#define USB_ERRSTAT_DMAERR_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5620	#define USB_ERRSTAT_DMAERR_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5621	#define USB_ERRSTAT_BTSERR_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5622	#define USB_ERRSTAT_BTSERR_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5623	/* ERREN Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5624	#define USB_ERREN_PIDERREN_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5625	#define USB_ERREN_PIDERREN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5626	#define USB_ERREN_CRC5EOFEN_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5627	#define USB_ERREN_CRC5EOFEN_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5628	#define USB_ERREN_CRC16EN_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5629	#define USB_ERREN_CRC16EN_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5630	#define USB_ERREN_DFN8EN_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5631	#define USB_ERREN_DFN8EN_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5632	#define USB_ERREN_BTOERREN_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5633	#define USB_ERREN_BTOERREN_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5634	#define USB_ERREN_DMAERREN_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5635	#define USB_ERREN_DMAERREN_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5636	#define USB_ERREN_BTSERREN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5637	#define USB_ERREN_BTSERREN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5638	/* STAT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5639	#define USB_STAT_ODD_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5640	#define USB_STAT_ODD_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5641	#define USB_STAT_TX_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5642	#define USB_STAT_TX_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5643	#define USB_STAT_ENDP_MASK 0xF0u
pradeepvk2208	1:c0c5ac8eac80	5644	#define USB_STAT_ENDP_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5645	#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
pradeepvk2208	1:c0c5ac8eac80	5646	/* CTL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5647	#define USB_CTL_USBENSOFEN_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5648	#define USB_CTL_USBENSOFEN_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5649	#define USB_CTL_ODDRST_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5650	#define USB_CTL_ODDRST_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5651	#define USB_CTL_RESUME_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5652	#define USB_CTL_RESUME_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5653	#define USB_CTL_HOSTMODEEN_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5654	#define USB_CTL_HOSTMODEEN_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5655	#define USB_CTL_RESET_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5656	#define USB_CTL_RESET_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5657	#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5658	#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5659	#define USB_CTL_SE0_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5660	#define USB_CTL_SE0_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5661	#define USB_CTL_JSTATE_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5662	#define USB_CTL_JSTATE_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5663	/* ADDR Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5664	#define USB_ADDR_ADDR_MASK 0x7Fu
pradeepvk2208	1:c0c5ac8eac80	5665	#define USB_ADDR_ADDR_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5666	#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
pradeepvk2208	1:c0c5ac8eac80	5667	#define USB_ADDR_LSEN_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5668	#define USB_ADDR_LSEN_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5669	/* BDTPAGE1 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5670	#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
pradeepvk2208	1:c0c5ac8eac80	5671	#define USB_BDTPAGE1_BDTBA_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5672	#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
pradeepvk2208	1:c0c5ac8eac80	5673	/* FRMNUML Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5674	#define USB_FRMNUML_FRM_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	5675	#define USB_FRMNUML_FRM_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5676	#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
pradeepvk2208	1:c0c5ac8eac80	5677	/* FRMNUMH Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5678	#define USB_FRMNUMH_FRM_MASK 0x7u
pradeepvk2208	1:c0c5ac8eac80	5679	#define USB_FRMNUMH_FRM_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5680	#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
pradeepvk2208	1:c0c5ac8eac80	5681	/* TOKEN Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5682	#define USB_TOKEN_TOKENENDPT_MASK 0xFu
pradeepvk2208	1:c0c5ac8eac80	5683	#define USB_TOKEN_TOKENENDPT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5684	#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
pradeepvk2208	1:c0c5ac8eac80	5685	#define USB_TOKEN_TOKENPID_MASK 0xF0u
pradeepvk2208	1:c0c5ac8eac80	5686	#define USB_TOKEN_TOKENPID_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5687	#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
pradeepvk2208	1:c0c5ac8eac80	5688	/* SOFTHLD Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5689	#define USB_SOFTHLD_CNT_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	5690	#define USB_SOFTHLD_CNT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5691	#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
pradeepvk2208	1:c0c5ac8eac80	5692	/* BDTPAGE2 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5693	#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	5694	#define USB_BDTPAGE2_BDTBA_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5695	#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
pradeepvk2208	1:c0c5ac8eac80	5696	/* BDTPAGE3 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5697	#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	5698	#define USB_BDTPAGE3_BDTBA_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5699	#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
pradeepvk2208	1:c0c5ac8eac80	5700	/* ENDPT Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5701	#define USB_ENDPT_EPHSHK_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5702	#define USB_ENDPT_EPHSHK_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5703	#define USB_ENDPT_EPSTALL_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5704	#define USB_ENDPT_EPSTALL_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5705	#define USB_ENDPT_EPTXEN_MASK 0x4u
pradeepvk2208	1:c0c5ac8eac80	5706	#define USB_ENDPT_EPTXEN_SHIFT 2
pradeepvk2208	1:c0c5ac8eac80	5707	#define USB_ENDPT_EPRXEN_MASK 0x8u
pradeepvk2208	1:c0c5ac8eac80	5708	#define USB_ENDPT_EPRXEN_SHIFT 3
pradeepvk2208	1:c0c5ac8eac80	5709	#define USB_ENDPT_EPCTLDIS_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5710	#define USB_ENDPT_EPCTLDIS_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5711	#define USB_ENDPT_RETRYDIS_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5712	#define USB_ENDPT_RETRYDIS_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5713	#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5714	#define USB_ENDPT_HOSTWOHUB_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5715	/* USBCTRL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5716	#define USB_USBCTRL_PDE_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5717	#define USB_USBCTRL_PDE_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5718	#define USB_USBCTRL_SUSP_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5719	#define USB_USBCTRL_SUSP_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5720	/* OBSERVE Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5721	#define USB_OBSERVE_DMPD_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5722	#define USB_OBSERVE_DMPD_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5723	#define USB_OBSERVE_DPPD_MASK 0x40u
pradeepvk2208	1:c0c5ac8eac80	5724	#define USB_OBSERVE_DPPD_SHIFT 6
pradeepvk2208	1:c0c5ac8eac80	5725	#define USB_OBSERVE_DPPU_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5726	#define USB_OBSERVE_DPPU_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5727	/* CONTROL Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5728	#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
pradeepvk2208	1:c0c5ac8eac80	5729	#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
pradeepvk2208	1:c0c5ac8eac80	5730	/* USBTRC0 Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5731	#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
pradeepvk2208	1:c0c5ac8eac80	5732	#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5733	#define USB_USBTRC0_SYNC_DET_MASK 0x2u
pradeepvk2208	1:c0c5ac8eac80	5734	#define USB_USBTRC0_SYNC_DET_SHIFT 1
pradeepvk2208	1:c0c5ac8eac80	5735	#define USB_USBTRC0_USBRESMEN_MASK 0x20u
pradeepvk2208	1:c0c5ac8eac80	5736	#define USB_USBTRC0_USBRESMEN_SHIFT 5
pradeepvk2208	1:c0c5ac8eac80	5737	#define USB_USBTRC0_USBRESET_MASK 0x80u
pradeepvk2208	1:c0c5ac8eac80	5738	#define USB_USBTRC0_USBRESET_SHIFT 7
pradeepvk2208	1:c0c5ac8eac80	5739	/* USBFRMADJUST Bit Fields */
pradeepvk2208	1:c0c5ac8eac80	5740	#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
pradeepvk2208	1:c0c5ac8eac80	5741	#define USB_USBFRMADJUST_ADJ_SHIFT 0
pradeepvk2208	1:c0c5ac8eac80	5742	#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
pradeepvk2208	1:c0c5ac8eac80	5743
pradeepvk2208	1:c0c5ac8eac80	5744	/*!
pradeepvk2208	1:c0c5ac8eac80	5745	* @}
pradeepvk2208	1:c0c5ac8eac80	5746	/ / end of group USB_Register_Masks */
pradeepvk2208	1:c0c5ac8eac80	5747
pradeepvk2208	1:c0c5ac8eac80	5748
pradeepvk2208	1:c0c5ac8eac80	5749	/* USB - Peripheral instance base addresses */
pradeepvk2208	1:c0c5ac8eac80	5750	/** Peripheral USB0 base address */
pradeepvk2208	1:c0c5ac8eac80	5751	#define USB0_BASE (0x40072000u)
pradeepvk2208	1:c0c5ac8eac80	5752	/** Peripheral USB0 base pointer */
pradeepvk2208	1:c0c5ac8eac80	5753	#define USB0 ((USB_Type *)USB0_BASE)
pradeepvk2208	1:c0c5ac8eac80	5754	/** Array initializer of USB peripheral base pointers */
pradeepvk2208	1:c0c5ac8eac80	5755	#define USB_BASES { USB0 }
pradeepvk2208	1:c0c5ac8eac80	5756
pradeepvk2208	1:c0c5ac8eac80	5757	/*!
pradeepvk2208	1:c0c5ac8eac80	5758	* @}
pradeepvk2208	1:c0c5ac8eac80	5759	/ / end of group USB_Peripheral_Access_Layer */
pradeepvk2208	1:c0c5ac8eac80	5760
pradeepvk2208	1:c0c5ac8eac80	5761
pradeepvk2208	1:c0c5ac8eac80	5762	/*
pradeepvk2208	1:c0c5ac8eac80	5763	** End of section using anonymous unions
pradeepvk2208	1:c0c5ac8eac80	5764	*/
pradeepvk2208	1:c0c5ac8eac80	5765
pradeepvk2208	1:c0c5ac8eac80	5766	#if defined(__ARMCC_VERSION)
pradeepvk2208	1:c0c5ac8eac80	5767	#pragma pop
pradeepvk2208	1:c0c5ac8eac80	5768	#elif defined(__CWCC__)
pradeepvk2208	1:c0c5ac8eac80	5769	#pragma pop
pradeepvk2208	1:c0c5ac8eac80	5770	#elif defined(__GNUC__)
pradeepvk2208	1:c0c5ac8eac80	5771	/* leave anonymous unions enabled */
pradeepvk2208	1:c0c5ac8eac80	5772	#elif defined(__IAR_SYSTEMS_ICC__)
pradeepvk2208	1:c0c5ac8eac80	5773	#pragma language=default
pradeepvk2208	1:c0c5ac8eac80	5774	#else
pradeepvk2208	1:c0c5ac8eac80	5775	#error Not supported compiler type
pradeepvk2208	1:c0c5ac8eac80	5776	#endif
pradeepvk2208	1:c0c5ac8eac80	5777
pradeepvk2208	1:c0c5ac8eac80	5778	/*!
pradeepvk2208	1:c0c5ac8eac80	5779	* @}
pradeepvk2208	1:c0c5ac8eac80	5780	/ / end of group Peripheral_access_layer */
pradeepvk2208	1:c0c5ac8eac80	5781
pradeepvk2208	1:c0c5ac8eac80	5782
pradeepvk2208	1:c0c5ac8eac80	5783	/* ----------------------------------------------------------------------------
pradeepvk2208	1:c0c5ac8eac80	5784	-- Backward Compatibility
pradeepvk2208	1:c0c5ac8eac80	5785	---------------------------------------------------------------------------- */
pradeepvk2208	1:c0c5ac8eac80	5786
pradeepvk2208	1:c0c5ac8eac80	5787	/*!
pradeepvk2208	1:c0c5ac8eac80	5788	* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
pradeepvk2208	1:c0c5ac8eac80	5789	* @{
pradeepvk2208	1:c0c5ac8eac80	5790	*/
pradeepvk2208	1:c0c5ac8eac80	5791
pradeepvk2208	1:c0c5ac8eac80	5792	/* No backward compatibility issues. */
pradeepvk2208	1:c0c5ac8eac80	5793
pradeepvk2208	1:c0c5ac8eac80	5794	/*!
pradeepvk2208	1:c0c5ac8eac80	5795	* @}
pradeepvk2208	1:c0c5ac8eac80	5796	/ / end of group Backward_Compatibility_Symbols */
pradeepvk2208	1:c0c5ac8eac80	5797
pradeepvk2208	1:c0c5ac8eac80	5798
pradeepvk2208	1:c0c5ac8eac80	5799	#endif /* #if !defined(MKL46Z4_H_) */
pradeepvk2208	1:c0c5ac8eac80	5800
pradeepvk2208	1:c0c5ac8eac80	5801	/* MKL46Z4.h, eof. */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	07 Nov 2015
Imports:	1
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	2
Followers:	1

MKL46Z4.h@1:c0c5ac8eac80, 2015-11-07 (annotated)

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