Pratyush Mallick / Mbed OS nano_dac

this is testing

noos_mbed/drivers/dac/ad5686/ad5686.c@0:e8a1ba50c46b, 2021-01-14 (annotated)

Committer:
pmallick
Date:
Thu Jan 14 19:12:57 2021 +0530
Revision:
0:e8a1ba50c46b
this is testing

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pmallick 0:e8a1ba50c46b 1 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 2 * @file ad5686.c
pmallick 0:e8a1ba50c46b 3 * @brief Implementation of AD5686 Driver.
pmallick 0:e8a1ba50c46b 4 * @author Istvan Csomortani (istvan.csomortani@analog.com)
pmallick 0:e8a1ba50c46b 5 *******************************************************************************
pmallick 0:e8a1ba50c46b 6 * Copyright 2013, 2020(c) Analog Devices, Inc.
pmallick 0:e8a1ba50c46b 7 *
pmallick 0:e8a1ba50c46b 8 * All rights reserved.
pmallick 0:e8a1ba50c46b 9 *
pmallick 0:e8a1ba50c46b 10 * Redistribution and use in source and binary forms, with or without
pmallick 0:e8a1ba50c46b 11 * modification,
pmallick 0:e8a1ba50c46b 12 * are permitted provided that the following conditions are met:
pmallick 0:e8a1ba50c46b 13 * - Redistributions of source code must retain the above copyright
pmallick 0:e8a1ba50c46b 14 * notice, this list of conditions and the following disclaimer.
pmallick 0:e8a1ba50c46b 15 * - Redistributions in binary form must reproduce the above copyright
pmallick 0:e8a1ba50c46b 16 * notice, this list of conditions and the following disclaimer in
pmallick 0:e8a1ba50c46b 17 * the documentation and/or other materials provided with the
pmallick 0:e8a1ba50c46b 18 * distribution.
pmallick 0:e8a1ba50c46b 19 * - Neither the name of Analog Devices, Inc. nor the names of its
pmallick 0:e8a1ba50c46b 20 * contributors may be used to endorse or promote products derived
pmallick 0:e8a1ba50c46b 21 * from this software without specific prior written permission.
pmallick 0:e8a1ba50c46b 22 * - The use of this software may or may not infringe the patent rights
pmallick 0:e8a1ba50c46b 23 * of one or more patent holders. This license does not release you
pmallick 0:e8a1ba50c46b 24 * from the requirement that you obtain separate licenses from these
pmallick 0:e8a1ba50c46b 25 * patent holders to use this software.
pmallick 0:e8a1ba50c46b 26 * - Use of the software either in source or binary form, must be run
pmallick 0:e8a1ba50c46b 27 * on or directly connected to an Analog Devices Inc. component.
pmallick 0:e8a1ba50c46b 28 *
pmallick 0:e8a1ba50c46b 29 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
pmallick 0:e8a1ba50c46b 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
pmallick 0:e8a1ba50c46b 31 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
pmallick 0:e8a1ba50c46b 32 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
pmallick 0:e8a1ba50c46b 33 * INCIDENTAL,SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
pmallick 0:e8a1ba50c46b 34 * * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS
pmallick 0:e8a1ba50c46b 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
pmallick 0:e8a1ba50c46b 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
pmallick 0:e8a1ba50c46b 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
pmallick 0:e8a1ba50c46b 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
pmallick 0:e8a1ba50c46b 39 * DAMAGE.
pmallick 0:e8a1ba50c46b 40 *
pmallick 0:e8a1ba50c46b 41 ******************************************************************************/
pmallick 0:e8a1ba50c46b 42
pmallick 0:e8a1ba50c46b 43 /*****************************************************************************/
pmallick 0:e8a1ba50c46b 44 /***************************** Include Files *********************************/
pmallick 0:e8a1ba50c46b 45 /*****************************************************************************/
pmallick 0:e8a1ba50c46b 46 #include <stdlib.h>
pmallick 0:e8a1ba50c46b 47 #include "ad5686.h"
pmallick 0:e8a1ba50c46b 48
pmallick 0:e8a1ba50c46b 49 /*****************************************************************************/
pmallick 0:e8a1ba50c46b 50 /***************************** Constant definition ***************************/
pmallick 0:e8a1ba50c46b 51 /*****************************************************************************/
pmallick 0:e8a1ba50c46b 52 static const uint32_t ad5683_channel_addr [] = {
pmallick 0:e8a1ba50c46b 53 [AD5686_CH_0] = 0,
pmallick 0:e8a1ba50c46b 54 };
pmallick 0:e8a1ba50c46b 55
pmallick 0:e8a1ba50c46b 56 static const uint32_t ad5689_channel_addr[] = {
pmallick 0:e8a1ba50c46b 57 [AD5686_CH_0] = 1,
pmallick 0:e8a1ba50c46b 58 [AD5686_CH_1] = 8,
pmallick 0:e8a1ba50c46b 59 };
pmallick 0:e8a1ba50c46b 60
pmallick 0:e8a1ba50c46b 61 static const uint32_t ad5686_channel_addr[] = {
pmallick 0:e8a1ba50c46b 62 [AD5686_CH_0] = 1,
pmallick 0:e8a1ba50c46b 63 [AD5686_CH_1] = 2,
pmallick 0:e8a1ba50c46b 64 [AD5686_CH_2] = 4,
pmallick 0:e8a1ba50c46b 65 [AD5686_CH_3] = 8,
pmallick 0:e8a1ba50c46b 66 };
pmallick 0:e8a1ba50c46b 67
pmallick 0:e8a1ba50c46b 68 static const uint32_t ad5676_channel_addr[] = {
pmallick 0:e8a1ba50c46b 69 [AD5686_CH_0] = 0,
pmallick 0:e8a1ba50c46b 70 [AD5686_CH_1] = 1,
pmallick 0:e8a1ba50c46b 71 [AD5686_CH_2] = 2,
pmallick 0:e8a1ba50c46b 72 [AD5686_CH_3] = 3,
pmallick 0:e8a1ba50c46b 73 [AD5686_CH_4] = 4,
pmallick 0:e8a1ba50c46b 74 [AD5686_CH_5] = 5,
pmallick 0:e8a1ba50c46b 75 [AD5686_CH_6] = 6,
pmallick 0:e8a1ba50c46b 76 [AD5686_CH_7] = 7,
pmallick 0:e8a1ba50c46b 77 };
pmallick 0:e8a1ba50c46b 78
pmallick 0:e8a1ba50c46b 79 static const uint32_t ad5679_channel_addr[] = {
pmallick 0:e8a1ba50c46b 80 [AD5686_CH_0] = 0,
pmallick 0:e8a1ba50c46b 81 [AD5686_CH_1] = 1,
pmallick 0:e8a1ba50c46b 82 [AD5686_CH_2] = 2,
pmallick 0:e8a1ba50c46b 83 [AD5686_CH_3] = 3,
pmallick 0:e8a1ba50c46b 84 [AD5686_CH_4] = 4,
pmallick 0:e8a1ba50c46b 85 [AD5686_CH_5] = 5,
pmallick 0:e8a1ba50c46b 86 [AD5686_CH_6] = 6,
pmallick 0:e8a1ba50c46b 87 [AD5686_CH_7] = 7,
pmallick 0:e8a1ba50c46b 88 [AD5686_CH_8] = 8,
pmallick 0:e8a1ba50c46b 89 [AD5686_CH_9] = 9,
pmallick 0:e8a1ba50c46b 90 [AD5686_CH_10] = 10,
pmallick 0:e8a1ba50c46b 91 [AD5686_CH_11] = 11,
pmallick 0:e8a1ba50c46b 92 [AD5686_CH_12] = 12,
pmallick 0:e8a1ba50c46b 93 [AD5686_CH_13] = 13,
pmallick 0:e8a1ba50c46b 94 [AD5686_CH_14] = 14,
pmallick 0:e8a1ba50c46b 95 [AD5686_CH_15] = 15,
pmallick 0:e8a1ba50c46b 96 };
pmallick 0:e8a1ba50c46b 97
pmallick 0:e8a1ba50c46b 98 static const struct ad5686_chip_info chip_info[] = {
pmallick 0:e8a1ba50c46b 99 [ID_AD5671R] = {
pmallick 0:e8a1ba50c46b 100 .resolution = 12,
pmallick 0:e8a1ba50c46b 101 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 102 .communication = I2C,
pmallick 0:e8a1ba50c46b 103 .channel_addr = ad5676_channel_addr,
pmallick 0:e8a1ba50c46b 104 },
pmallick 0:e8a1ba50c46b 105 [ID_AD5672R] = {
pmallick 0:e8a1ba50c46b 106 .resolution = 12,
pmallick 0:e8a1ba50c46b 107 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 108 .communication = SPI,
pmallick 0:e8a1ba50c46b 109 .channel_addr = ad5676_channel_addr,
pmallick 0:e8a1ba50c46b 110 },
pmallick 0:e8a1ba50c46b 111 [ID_AD5673R] = {
pmallick 0:e8a1ba50c46b 112 .resolution = 12,
pmallick 0:e8a1ba50c46b 113 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 114 .communication = I2C,
pmallick 0:e8a1ba50c46b 115 .channel_addr = ad5679_channel_addr,
pmallick 0:e8a1ba50c46b 116 },
pmallick 0:e8a1ba50c46b 117 [ID_AD5674] = {
pmallick 0:e8a1ba50c46b 118 .resolution = 12,
pmallick 0:e8a1ba50c46b 119 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 120 .communication = SPI,
pmallick 0:e8a1ba50c46b 121 .channel_addr = ad5679_channel_addr,
pmallick 0:e8a1ba50c46b 122 },
pmallick 0:e8a1ba50c46b 123 [ID_AD5674R] = {
pmallick 0:e8a1ba50c46b 124 .resolution = 12,
pmallick 0:e8a1ba50c46b 125 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 126 .communication = SPI,
pmallick 0:e8a1ba50c46b 127 .channel_addr = ad5679_channel_addr,
pmallick 0:e8a1ba50c46b 128 },
pmallick 0:e8a1ba50c46b 129 [ID_AD5675R] = {
pmallick 0:e8a1ba50c46b 130 .resolution = 16,
pmallick 0:e8a1ba50c46b 131 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 132 .communication = I2C,
pmallick 0:e8a1ba50c46b 133 .channel_addr = ad5676_channel_addr,
pmallick 0:e8a1ba50c46b 134 },
pmallick 0:e8a1ba50c46b 135 [ID_AD5676] = {
pmallick 0:e8a1ba50c46b 136 .resolution = 16,
pmallick 0:e8a1ba50c46b 137 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 138 .communication = SPI,
pmallick 0:e8a1ba50c46b 139 .channel_addr = ad5676_channel_addr,
pmallick 0:e8a1ba50c46b 140 },
pmallick 0:e8a1ba50c46b 141 [ID_AD5676R] = {
pmallick 0:e8a1ba50c46b 142 .resolution = 16,
pmallick 0:e8a1ba50c46b 143 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 144 .communication = SPI,
pmallick 0:e8a1ba50c46b 145 .channel_addr = ad5676_channel_addr,
pmallick 0:e8a1ba50c46b 146 },
pmallick 0:e8a1ba50c46b 147 [ID_AD5677R] = {
pmallick 0:e8a1ba50c46b 148 .resolution = 16,
pmallick 0:e8a1ba50c46b 149 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 150 .communication = I2C,
pmallick 0:e8a1ba50c46b 151 .channel_addr = ad5679_channel_addr,
pmallick 0:e8a1ba50c46b 152 },
pmallick 0:e8a1ba50c46b 153 [ID_AD5679] = {
pmallick 0:e8a1ba50c46b 154 .resolution = 16,
pmallick 0:e8a1ba50c46b 155 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 156 .communication = SPI,
pmallick 0:e8a1ba50c46b 157 .channel_addr = ad5679_channel_addr,
pmallick 0:e8a1ba50c46b 158 },
pmallick 0:e8a1ba50c46b 159 [ID_AD5679R] = {
pmallick 0:e8a1ba50c46b 160 .resolution = 16,
pmallick 0:e8a1ba50c46b 161 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 162 .communication = SPI,
pmallick 0:e8a1ba50c46b 163 .channel_addr = ad5679_channel_addr,
pmallick 0:e8a1ba50c46b 164 },
pmallick 0:e8a1ba50c46b 165 [ID_AD5684R] = {
pmallick 0:e8a1ba50c46b 166 .resolution = 12,
pmallick 0:e8a1ba50c46b 167 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 168 .communication = SPI,
pmallick 0:e8a1ba50c46b 169 .channel_addr = ad5686_channel_addr,
pmallick 0:e8a1ba50c46b 170 },
pmallick 0:e8a1ba50c46b 171 [ID_AD5685R] = {
pmallick 0:e8a1ba50c46b 172 .resolution = 14,
pmallick 0:e8a1ba50c46b 173 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 174 .communication = SPI,
pmallick 0:e8a1ba50c46b 175 .channel_addr = ad5686_channel_addr,
pmallick 0:e8a1ba50c46b 176 },
pmallick 0:e8a1ba50c46b 177 [ID_AD5686] = {
pmallick 0:e8a1ba50c46b 178 .resolution = 16,
pmallick 0:e8a1ba50c46b 179 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 180 .communication = SPI,
pmallick 0:e8a1ba50c46b 181 .channel_addr = ad5686_channel_addr,
pmallick 0:e8a1ba50c46b 182 },
pmallick 0:e8a1ba50c46b 183 [ID_AD5686R] = {
pmallick 0:e8a1ba50c46b 184 .resolution = 16,
pmallick 0:e8a1ba50c46b 185 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 186 .communication = SPI,
pmallick 0:e8a1ba50c46b 187 .channel_addr = ad5686_channel_addr,
pmallick 0:e8a1ba50c46b 188 },
pmallick 0:e8a1ba50c46b 189 [ID_AD5687] = {
pmallick 0:e8a1ba50c46b 190 .resolution = 12,
pmallick 0:e8a1ba50c46b 191 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 192 .communication = SPI,
pmallick 0:e8a1ba50c46b 193 .channel_addr = ad5689_channel_addr,
pmallick 0:e8a1ba50c46b 194 },
pmallick 0:e8a1ba50c46b 195 [ID_AD5687R] = {
pmallick 0:e8a1ba50c46b 196 .resolution = 12,
pmallick 0:e8a1ba50c46b 197 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 198 .communication = SPI,
pmallick 0:e8a1ba50c46b 199 .channel_addr = ad5689_channel_addr,
pmallick 0:e8a1ba50c46b 200 },
pmallick 0:e8a1ba50c46b 201 [ID_AD5689] = {
pmallick 0:e8a1ba50c46b 202 .resolution = 16,
pmallick 0:e8a1ba50c46b 203 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 204 .communication = SPI,
pmallick 0:e8a1ba50c46b 205 .channel_addr = ad5689_channel_addr,
pmallick 0:e8a1ba50c46b 206 },
pmallick 0:e8a1ba50c46b 207 [ID_AD5689R] = {
pmallick 0:e8a1ba50c46b 208 .resolution = 16,
pmallick 0:e8a1ba50c46b 209 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 210 .communication = SPI,
pmallick 0:e8a1ba50c46b 211 .channel_addr = ad5689_channel_addr,
pmallick 0:e8a1ba50c46b 212 },
pmallick 0:e8a1ba50c46b 213 [ID_AD5697R] = {
pmallick 0:e8a1ba50c46b 214 .resolution = 12,
pmallick 0:e8a1ba50c46b 215 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 216 .communication = I2C,
pmallick 0:e8a1ba50c46b 217 .channel_addr = ad5689_channel_addr,
pmallick 0:e8a1ba50c46b 218 },
pmallick 0:e8a1ba50c46b 219 [ID_AD5694] = {
pmallick 0:e8a1ba50c46b 220 .resolution = 12,
pmallick 0:e8a1ba50c46b 221 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 222 .communication = I2C,
pmallick 0:e8a1ba50c46b 223 .channel_addr = ad5686_channel_addr,
pmallick 0:e8a1ba50c46b 224 },
pmallick 0:e8a1ba50c46b 225 [ID_AD5694R] = {
pmallick 0:e8a1ba50c46b 226 .resolution = 12,
pmallick 0:e8a1ba50c46b 227 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 228 .communication = I2C,
pmallick 0:e8a1ba50c46b 229 .channel_addr = ad5686_channel_addr,
pmallick 0:e8a1ba50c46b 230 },
pmallick 0:e8a1ba50c46b 231 [ID_AD5695R] = {
pmallick 0:e8a1ba50c46b 232 .resolution = 14,
pmallick 0:e8a1ba50c46b 233 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 234 .communication = I2C,
pmallick 0:e8a1ba50c46b 235 .channel_addr = ad5686_channel_addr,
pmallick 0:e8a1ba50c46b 236 },
pmallick 0:e8a1ba50c46b 237 [ID_AD5696] = {
pmallick 0:e8a1ba50c46b 238 .resolution = 16,
pmallick 0:e8a1ba50c46b 239 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 240 .communication = I2C,
pmallick 0:e8a1ba50c46b 241 .channel_addr = ad5686_channel_addr,
pmallick 0:e8a1ba50c46b 242 },
pmallick 0:e8a1ba50c46b 243 [ID_AD5696R] = {
pmallick 0:e8a1ba50c46b 244 .resolution = 16,
pmallick 0:e8a1ba50c46b 245 .register_map = AD5686_REG_MAP,
pmallick 0:e8a1ba50c46b 246 .communication = I2C,
pmallick 0:e8a1ba50c46b 247 .channel_addr = ad5686_channel_addr,
pmallick 0:e8a1ba50c46b 248 },
pmallick 0:e8a1ba50c46b 249 [ID_AD5681R] = {
pmallick 0:e8a1ba50c46b 250 .resolution = 12,
pmallick 0:e8a1ba50c46b 251 .register_map = AD5683_REG_MAP,
pmallick 0:e8a1ba50c46b 252 .communication = SPI,
pmallick 0:e8a1ba50c46b 253 .channel_addr = ad5683_channel_addr,
pmallick 0:e8a1ba50c46b 254 },
pmallick 0:e8a1ba50c46b 255 [ID_AD5682R] = {
pmallick 0:e8a1ba50c46b 256 .resolution = 14,
pmallick 0:e8a1ba50c46b 257 .register_map = AD5683_REG_MAP,
pmallick 0:e8a1ba50c46b 258 .communication = SPI,
pmallick 0:e8a1ba50c46b 259 .channel_addr = ad5683_channel_addr,
pmallick 0:e8a1ba50c46b 260 },
pmallick 0:e8a1ba50c46b 261 [ID_AD5683R] = {
pmallick 0:e8a1ba50c46b 262 .resolution = 16,
pmallick 0:e8a1ba50c46b 263 .register_map = AD5683_REG_MAP,
pmallick 0:e8a1ba50c46b 264 .communication = SPI,
pmallick 0:e8a1ba50c46b 265 .channel_addr = ad5683_channel_addr,
pmallick 0:e8a1ba50c46b 266 },
pmallick 0:e8a1ba50c46b 267 [ID_AD5683] = {
pmallick 0:e8a1ba50c46b 268 .resolution = 16,
pmallick 0:e8a1ba50c46b 269 .register_map = AD5683_REG_MAP,
pmallick 0:e8a1ba50c46b 270 .communication = SPI,
pmallick 0:e8a1ba50c46b 271 .channel_addr = ad5683_channel_addr,
pmallick 0:e8a1ba50c46b 272 },
pmallick 0:e8a1ba50c46b 273 [ID_AD5691R] = {
pmallick 0:e8a1ba50c46b 274 .resolution = 12,
pmallick 0:e8a1ba50c46b 275 .register_map = AD5683_REG_MAP,
pmallick 0:e8a1ba50c46b 276 .communication = I2C,
pmallick 0:e8a1ba50c46b 277 .channel_addr = ad5683_channel_addr,
pmallick 0:e8a1ba50c46b 278 },
pmallick 0:e8a1ba50c46b 279 [ID_AD5692R] = {
pmallick 0:e8a1ba50c46b 280 .resolution = 14,
pmallick 0:e8a1ba50c46b 281 .register_map = AD5683_REG_MAP,
pmallick 0:e8a1ba50c46b 282 .communication = I2C,
pmallick 0:e8a1ba50c46b 283 .channel_addr = ad5683_channel_addr,
pmallick 0:e8a1ba50c46b 284 },
pmallick 0:e8a1ba50c46b 285 [ID_AD5693R] = {
pmallick 0:e8a1ba50c46b 286 .resolution = 16,
pmallick 0:e8a1ba50c46b 287 .register_map = AD5683_REG_MAP,
pmallick 0:e8a1ba50c46b 288 .communication = I2C,
pmallick 0:e8a1ba50c46b 289 .channel_addr = ad5683_channel_addr,
pmallick 0:e8a1ba50c46b 290 },
pmallick 0:e8a1ba50c46b 291 [ID_AD5693] = {
pmallick 0:e8a1ba50c46b 292 .resolution = 16,
pmallick 0:e8a1ba50c46b 293 .register_map = AD5683_REG_MAP,
pmallick 0:e8a1ba50c46b 294 .communication = I2C,
pmallick 0:e8a1ba50c46b 295 .channel_addr = ad5683_channel_addr,
pmallick 0:e8a1ba50c46b 296 }
pmallick 0:e8a1ba50c46b 297 };
pmallick 0:e8a1ba50c46b 298
pmallick 0:e8a1ba50c46b 299 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 300 * @brief Initializes the communication peripheral and the initial Values for
pmallick 0:e8a1ba50c46b 301 * AD5686 Board.
pmallick 0:e8a1ba50c46b 302 *
pmallick 0:e8a1ba50c46b 303 * @param device - The device structure.
pmallick 0:e8a1ba50c46b 304 * @param init_param - The structure that contains the device initial
pmallick 0:e8a1ba50c46b 305 * parameters.
pmallick 0:e8a1ba50c46b 306 *
pmallick 0:e8a1ba50c46b 307 * @return ret - The result of the initialization procedure.
pmallick 0:e8a1ba50c46b 308 * Example: -1 - I2C peripheral was not initialized or the
pmallick 0:e8a1ba50c46b 309 * device is not present.
pmallick 0:e8a1ba50c46b 310 * 0 - I2C peripheral was initialized and the
pmallick 0:e8a1ba50c46b 311 * device is present.
pmallick 0:e8a1ba50c46b 312 *******************************************************************************/
pmallick 0:e8a1ba50c46b 313 int32_t ad5686_init(struct ad5686_dev **device,
pmallick 0:e8a1ba50c46b 314 struct ad5686_init_param init_param)
pmallick 0:e8a1ba50c46b 315 {
pmallick 0:e8a1ba50c46b 316 struct ad5686_dev *dev;
pmallick 0:e8a1ba50c46b 317 int32_t ret;
pmallick 0:e8a1ba50c46b 318
pmallick 0:e8a1ba50c46b 319 dev = (struct ad5686_dev *)malloc(sizeof(*dev));
pmallick 0:e8a1ba50c46b 320 if (!dev)
pmallick 0:e8a1ba50c46b 321 return -1;
pmallick 0:e8a1ba50c46b 322
pmallick 0:e8a1ba50c46b 323 dev->act_device = init_param.act_device;
pmallick 0:e8a1ba50c46b 324 dev->power_down_mask = 0;
pmallick 0:e8a1ba50c46b 325 dev->ldac_mask = 0;
pmallick 0:e8a1ba50c46b 326
pmallick 0:e8a1ba50c46b 327 if (chip_info[dev->act_device].communication == SPI)
pmallick 0:e8a1ba50c46b 328 ret = spi_init(&dev->spi_desc, &init_param.spi_init);
pmallick 0:e8a1ba50c46b 329 else
pmallick 0:e8a1ba50c46b 330 ret = i2c_init(&dev->i2c_desc, &init_param.i2c_init);
pmallick 0:e8a1ba50c46b 331
pmallick 0:e8a1ba50c46b 332
pmallick 0:e8a1ba50c46b 333 /* GPIO */
pmallick 0:e8a1ba50c46b 334 ret |= gpio_get(&dev->gpio_reset, &init_param.gpio_reset);
pmallick 0:e8a1ba50c46b 335 ret |= gpio_get(&dev->gpio_ldac, &init_param.gpio_ldac);
pmallick 0:e8a1ba50c46b 336 ret |= gpio_get(&dev->gpio_gain, &init_param.gpio_gain);
pmallick 0:e8a1ba50c46b 337
pmallick 0:e8a1ba50c46b 338 if (dev->gpio_ldac)
pmallick 0:e8a1ba50c46b 339 ret |= gpio_direction_output(dev->gpio_ldac, GPIO_LOW);
pmallick 0:e8a1ba50c46b 340
pmallick 0:e8a1ba50c46b 341 if (dev->gpio_reset)
pmallick 0:e8a1ba50c46b 342 ret |= gpio_direction_output(dev->gpio_reset, GPIO_HIGH);
pmallick 0:e8a1ba50c46b 343
pmallick 0:e8a1ba50c46b 344 if (dev->gpio_gain)
pmallick 0:e8a1ba50c46b 345 ret |= gpio_direction_output(dev->gpio_gain, GPIO_LOW);
pmallick 0:e8a1ba50c46b 346 *device = dev;
pmallick 0:e8a1ba50c46b 347
pmallick 0:e8a1ba50c46b 348 return ret;
pmallick 0:e8a1ba50c46b 349 }
pmallick 0:e8a1ba50c46b 350
pmallick 0:e8a1ba50c46b 351 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 352 * @brief Free the resources allocated by ad5686_init().
pmallick 0:e8a1ba50c46b 353 *
pmallick 0:e8a1ba50c46b 354 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 355 *
pmallick 0:e8a1ba50c46b 356 * @return ret - The result of the remove procedure.
pmallick 0:e8a1ba50c46b 357 *******************************************************************************/
pmallick 0:e8a1ba50c46b 358 int32_t ad5686_remove(struct ad5686_dev *dev)
pmallick 0:e8a1ba50c46b 359 {
pmallick 0:e8a1ba50c46b 360 int32_t ret;
pmallick 0:e8a1ba50c46b 361
pmallick 0:e8a1ba50c46b 362 if (chip_info[dev->act_device].communication == SPI)
pmallick 0:e8a1ba50c46b 363 ret = spi_remove(dev->spi_desc);
pmallick 0:e8a1ba50c46b 364 else
pmallick 0:e8a1ba50c46b 365 ret = i2c_remove(dev->i2c_desc);
pmallick 0:e8a1ba50c46b 366
pmallick 0:e8a1ba50c46b 367 if (dev->gpio_ldac)
pmallick 0:e8a1ba50c46b 368 ret |= gpio_remove(dev->gpio_ldac);
pmallick 0:e8a1ba50c46b 369
pmallick 0:e8a1ba50c46b 370 if (dev->gpio_reset)
pmallick 0:e8a1ba50c46b 371 ret |= gpio_remove(dev->gpio_reset);
pmallick 0:e8a1ba50c46b 372
pmallick 0:e8a1ba50c46b 373 if (dev->gpio_gain)
pmallick 0:e8a1ba50c46b 374 ret |= gpio_remove(dev->gpio_gain);
pmallick 0:e8a1ba50c46b 375
pmallick 0:e8a1ba50c46b 376 free(dev);
pmallick 0:e8a1ba50c46b 377
pmallick 0:e8a1ba50c46b 378 return ret;
pmallick 0:e8a1ba50c46b 379 }
pmallick 0:e8a1ba50c46b 380
pmallick 0:e8a1ba50c46b 381 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 382 * @brief Write to input shift register.
pmallick 0:e8a1ba50c46b 383 *
pmallick 0:e8a1ba50c46b 384 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 385 * @param command - Command control bits.
pmallick 0:e8a1ba50c46b 386 * @param address - The address bits.
pmallick 0:e8a1ba50c46b 387 * @param data - Data to be written in input register.
pmallick 0:e8a1ba50c46b 388 *
pmallick 0:e8a1ba50c46b 389 * @return read_back_data - value read from register.
pmallick 0:e8a1ba50c46b 390 ******************************************************************************/
pmallick 0:e8a1ba50c46b 391 uint16_t ad5686_set_shift_reg(struct ad5686_dev *dev,
pmallick 0:e8a1ba50c46b 392 uint8_t command,
pmallick 0:e8a1ba50c46b 393 uint8_t address,
pmallick 0:e8a1ba50c46b 394 uint16_t data)
pmallick 0:e8a1ba50c46b 395 {
pmallick 0:e8a1ba50c46b 396 uint8_t data_buff [ PKT_LENGTH ] = {0, 0, 0};
pmallick 0:e8a1ba50c46b 397 uint16_t read_back_data = 0;
pmallick 0:e8a1ba50c46b 398
pmallick 0:e8a1ba50c46b 399 if(chip_info[dev->act_device].register_map == AD5686_REG_MAP) {
pmallick 0:e8a1ba50c46b 400 data_buff[0] = ((command & AD5686_CMD_MASK) << CMD_OFFSET) | \
pmallick 0:e8a1ba50c46b 401 (address & ADDR_MASK);
pmallick 0:e8a1ba50c46b 402 data_buff[1] = (data & AD5686_MSB_MASK) >> AD5686_MSB_OFFSET;
pmallick 0:e8a1ba50c46b 403 data_buff[2] = (data & AD5686_LSB_MASK);
pmallick 0:e8a1ba50c46b 404 } else {
pmallick 0:e8a1ba50c46b 405 data_buff[0] = ((command & AD5683_CMD_MASK) << CMD_OFFSET) |
pmallick 0:e8a1ba50c46b 406 ((data >> AD5683_MSB_OFFSET) & AD5683_MSB_MASK);
pmallick 0:e8a1ba50c46b 407 data_buff[1] = (data >> AD5683_MIDB_OFFSET) & AD5683_MIDB_MASK;
pmallick 0:e8a1ba50c46b 408 data_buff[2] = (data & AD5683_LSB_MASK) << AD5683_LSB_OFFSET;
pmallick 0:e8a1ba50c46b 409 }
pmallick 0:e8a1ba50c46b 410
pmallick 0:e8a1ba50c46b 411 if(chip_info[dev->act_device].communication == SPI) {
pmallick 0:e8a1ba50c46b 412 spi_write_and_read(dev->spi_desc, data_buff, PKT_LENGTH);
pmallick 0:e8a1ba50c46b 413 if(chip_info[dev->act_device].register_map == AD5686_REG_MAP)
pmallick 0:e8a1ba50c46b 414 read_back_data = (data_buff[1] << AD5686_MSB_OFFSET) | data_buff[2];
pmallick 0:e8a1ba50c46b 415 else
pmallick 0:e8a1ba50c46b 416 read_back_data = (data_buff[0] & AD5683_CMD_MASK) << AD5683_MSB_OFFSET |
pmallick 0:e8a1ba50c46b 417 data_buff[1] << AD5683_MIDB_OFFSET |
pmallick 0:e8a1ba50c46b 418 data_buff[2] >> AD5683_LSB_OFFSET;
pmallick 0:e8a1ba50c46b 419 } else
pmallick 0:e8a1ba50c46b 420 i2c_write(dev->i2c_desc, data_buff, PKT_LENGTH, 1);
pmallick 0:e8a1ba50c46b 421
pmallick 0:e8a1ba50c46b 422 return read_back_data;
pmallick 0:e8a1ba50c46b 423 }
pmallick 0:e8a1ba50c46b 424
pmallick 0:e8a1ba50c46b 425 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 426 * @brief Write to Input Register n (dependent on LDAC)
pmallick 0:e8a1ba50c46b 427 *
pmallick 0:e8a1ba50c46b 428 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 429 * @param channel - The chosen channel to write to.
pmallick 0:e8a1ba50c46b 430 * Accepted values: AD5686_CH_0
pmallick 0:e8a1ba50c46b 431 * AD5686_CH_1
pmallick 0:e8a1ba50c46b 432 * AD5686_CH_2
pmallick 0:e8a1ba50c46b 433 * AD5686_CH_3
pmallick 0:e8a1ba50c46b 434 * AD5686_CH_4
pmallick 0:e8a1ba50c46b 435 * AD5686_CH_5
pmallick 0:e8a1ba50c46b 436 * AD5686_CH_6
pmallick 0:e8a1ba50c46b 437 * AD5686_CH_7
pmallick 0:e8a1ba50c46b 438 * AD5686_CH_8
pmallick 0:e8a1ba50c46b 439 * AD5686_CH_9
pmallick 0:e8a1ba50c46b 440 * AD5686_CH_10
pmallick 0:e8a1ba50c46b 441 * AD5686_CH_11
pmallick 0:e8a1ba50c46b 442 * AD5686_CH_12
pmallick 0:e8a1ba50c46b 443 * AD5686_CH_13
pmallick 0:e8a1ba50c46b 444 * AD5686_CH_14
pmallick 0:e8a1ba50c46b 445 * AD5686_CH_15
pmallick 0:e8a1ba50c46b 446 * @param data - desired value to be written in register.
pmallick 0:e8a1ba50c46b 447 *
pmallick 0:e8a1ba50c46b 448 * @return None.
pmallick 0:e8a1ba50c46b 449 ******************************************************************************/
pmallick 0:e8a1ba50c46b 450 void ad5686_write_register(struct ad5686_dev *dev,
pmallick 0:e8a1ba50c46b 451 enum ad5686_dac_channels channel,
pmallick 0:e8a1ba50c46b 452 uint16_t data)
pmallick 0:e8a1ba50c46b 453 {
pmallick 0:e8a1ba50c46b 454 uint8_t data_offset = MAX_RESOLUTION - \
pmallick 0:e8a1ba50c46b 455 chip_info[dev->act_device].resolution;
pmallick 0:e8a1ba50c46b 456 uint8_t address = chip_info[dev->act_device].channel_addr[channel];
pmallick 0:e8a1ba50c46b 457
pmallick 0:e8a1ba50c46b 458 ad5686_set_shift_reg(dev, AD5686_CTRL_WRITE, address,
pmallick 0:e8a1ba50c46b 459 data << data_offset);
pmallick 0:e8a1ba50c46b 460 }
pmallick 0:e8a1ba50c46b 461
pmallick 0:e8a1ba50c46b 462 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 463 * @brief Update DAC Register n with contents of Input Register n
pmallick 0:e8a1ba50c46b 464 *
pmallick 0:e8a1ba50c46b 465 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 466 * @param channel - The chosen channel to write to.
pmallick 0:e8a1ba50c46b 467 * Accepted values: AD5686_CH_0
pmallick 0:e8a1ba50c46b 468 * AD5686_CH_1
pmallick 0:e8a1ba50c46b 469 * AD5686_CH_2
pmallick 0:e8a1ba50c46b 470 * AD5686_CH_3
pmallick 0:e8a1ba50c46b 471 * AD5686_CH_4
pmallick 0:e8a1ba50c46b 472 * AD5686_CH_5
pmallick 0:e8a1ba50c46b 473 * AD5686_CH_6
pmallick 0:e8a1ba50c46b 474 * AD5686_CH_7
pmallick 0:e8a1ba50c46b 475 * AD5686_CH_8
pmallick 0:e8a1ba50c46b 476 * AD5686_CH_9
pmallick 0:e8a1ba50c46b 477 * AD5686_CH_10
pmallick 0:e8a1ba50c46b 478 * AD5686_CH_11
pmallick 0:e8a1ba50c46b 479 * AD5686_CH_12
pmallick 0:e8a1ba50c46b 480 * AD5686_CH_13
pmallick 0:e8a1ba50c46b 481 * AD5686_CH_14
pmallick 0:e8a1ba50c46b 482 * AD5686_CH_15
pmallick 0:e8a1ba50c46b 483 * @return None.
pmallick 0:e8a1ba50c46b 484 ******************************************************************************/
pmallick 0:e8a1ba50c46b 485 void ad5686_update_register(struct ad5686_dev *dev,
pmallick 0:e8a1ba50c46b 486 enum ad5686_dac_channels channel)
pmallick 0:e8a1ba50c46b 487 {
pmallick 0:e8a1ba50c46b 488 uint8_t address = chip_info[dev->act_device].channel_addr[channel];
pmallick 0:e8a1ba50c46b 489
pmallick 0:e8a1ba50c46b 490 ad5686_set_shift_reg(dev, AD5686_CTRL_UPDATE, address, 0);
pmallick 0:e8a1ba50c46b 491 }
pmallick 0:e8a1ba50c46b 492
pmallick 0:e8a1ba50c46b 493 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 494 * @brief Write to and update DAC channel n
pmallick 0:e8a1ba50c46b 495 *
pmallick 0:e8a1ba50c46b 496 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 497 * @param channel - The chosen channel to write to.
pmallick 0:e8a1ba50c46b 498 * Accepted values: AD5686_CH_0
pmallick 0:e8a1ba50c46b 499 * AD5686_CH_1
pmallick 0:e8a1ba50c46b 500 * AD5686_CH_2
pmallick 0:e8a1ba50c46b 501 * AD5686_CH_3
pmallick 0:e8a1ba50c46b 502 * AD5686_CH_4
pmallick 0:e8a1ba50c46b 503 * AD5686_CH_5
pmallick 0:e8a1ba50c46b 504 * AD5686_CH_6
pmallick 0:e8a1ba50c46b 505 * AD5686_CH_7
pmallick 0:e8a1ba50c46b 506 * AD5686_CH_8
pmallick 0:e8a1ba50c46b 507 * AD5686_CH_9
pmallick 0:e8a1ba50c46b 508 * AD5686_CH_10
pmallick 0:e8a1ba50c46b 509 * AD5686_CH_11
pmallick 0:e8a1ba50c46b 510 * AD5686_CH_12
pmallick 0:e8a1ba50c46b 511 * AD5686_CH_13
pmallick 0:e8a1ba50c46b 512 * AD5686_CH_14
pmallick 0:e8a1ba50c46b 513 * AD5686_CH_15
pmallick 0:e8a1ba50c46b 514 * @param data - Desired value to be written in register.
pmallick 0:e8a1ba50c46b 515 *
pmallick 0:e8a1ba50c46b 516 * @return None.
pmallick 0:e8a1ba50c46b 517 ******************************************************************************/
pmallick 0:e8a1ba50c46b 518 void ad5686_write_update_register(struct ad5686_dev *dev,
pmallick 0:e8a1ba50c46b 519 enum ad5686_dac_channels channel,
pmallick 0:e8a1ba50c46b 520 uint16_t data)
pmallick 0:e8a1ba50c46b 521 {
pmallick 0:e8a1ba50c46b 522 uint8_t data_offset = MAX_RESOLUTION - \
pmallick 0:e8a1ba50c46b 523 chip_info[dev->act_device].resolution;
pmallick 0:e8a1ba50c46b 524 uint8_t address = chip_info[dev->act_device].channel_addr[channel];
pmallick 0:e8a1ba50c46b 525
pmallick 0:e8a1ba50c46b 526 ad5686_set_shift_reg(dev, AD5686_CTRL_WRITEUPDATE, address,
pmallick 0:e8a1ba50c46b 527 data << data_offset);
pmallick 0:e8a1ba50c46b 528 }
pmallick 0:e8a1ba50c46b 529
pmallick 0:e8a1ba50c46b 530 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 531 * @brief Read back Input Register n
pmallick 0:e8a1ba50c46b 532 *
pmallick 0:e8a1ba50c46b 533 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 534 * @param channel - The channel which will be read back. Note: only one
pmallick 0:e8a1ba50c46b 535 * channel should be selected, if there will be selected
pmallick 0:e8a1ba50c46b 536 * more than one channel, the channel A will be read back
pmallick 0:e8a1ba50c46b 537 * by default
pmallick 0:e8a1ba50c46b 538 * Accepted values: AD5686_CH_0
pmallick 0:e8a1ba50c46b 539 * AD5686_CH_1
pmallick 0:e8a1ba50c46b 540 * AD5686_CH_2
pmallick 0:e8a1ba50c46b 541 * AD5686_CH_3
pmallick 0:e8a1ba50c46b 542 * AD5686_CH_4
pmallick 0:e8a1ba50c46b 543 * AD5686_CH_5
pmallick 0:e8a1ba50c46b 544 * AD5686_CH_6
pmallick 0:e8a1ba50c46b 545 * AD5686_CH_7
pmallick 0:e8a1ba50c46b 546 * AD5686_CH_8
pmallick 0:e8a1ba50c46b 547 * AD5686_CH_9
pmallick 0:e8a1ba50c46b 548 * AD5686_CH_10
pmallick 0:e8a1ba50c46b 549 * AD5686_CH_11
pmallick 0:e8a1ba50c46b 550 * AD5686_CH_12
pmallick 0:e8a1ba50c46b 551 * AD5686_CH_13
pmallick 0:e8a1ba50c46b 552 * AD5686_CH_14
pmallick 0:e8a1ba50c46b 553 * AD5686_CH_15
pmallick 0:e8a1ba50c46b 554 * @return read_back_data - value read from register.
pmallick 0:e8a1ba50c46b 555 ******************************************************************************/
pmallick 0:e8a1ba50c46b 556 uint16_t ad5686_read_back_register(struct ad5686_dev *dev,
pmallick 0:e8a1ba50c46b 557 enum ad5686_dac_channels channel)
pmallick 0:e8a1ba50c46b 558 {
pmallick 0:e8a1ba50c46b 559
pmallick 0:e8a1ba50c46b 560 uint16_t read_back_data = 0;
pmallick 0:e8a1ba50c46b 561 uint16_t offset = MAX_RESOLUTION - \
pmallick 0:e8a1ba50c46b 562 chip_info[dev->act_device].resolution;
pmallick 0:e8a1ba50c46b 563 uint8_t address = chip_info[dev->act_device].channel_addr[channel];
pmallick 0:e8a1ba50c46b 564 uint8_t rb_data_i2c[3] = { 0 };
pmallick 0:e8a1ba50c46b 565
pmallick 0:e8a1ba50c46b 566 if(chip_info[dev->act_device].communication == SPI) {
pmallick 0:e8a1ba50c46b 567 ad5686_set_shift_reg(dev, AD5686_CTRL_RB_REG, address, 0);
pmallick 0:e8a1ba50c46b 568 read_back_data = ad5686_set_shift_reg(dev, AD5686_CTRL_NOP, 0,
pmallick 0:e8a1ba50c46b 569 0);
pmallick 0:e8a1ba50c46b 570 read_back_data >>= offset;
pmallick 0:e8a1ba50c46b 571 } else {
pmallick 0:e8a1ba50c46b 572 if (chip_info[dev->act_device].register_map == AD5683_REG_MAP)
pmallick 0:e8a1ba50c46b 573 rb_data_i2c[0] = (AD5683_CTRL_RB_REG << CMD_OFFSET) |
pmallick 0:e8a1ba50c46b 574 address;
pmallick 0:e8a1ba50c46b 575 else
pmallick 0:e8a1ba50c46b 576 rb_data_i2c[0] = (AD5686_CTRL_RB_REG << CMD_OFFSET) |
pmallick 0:e8a1ba50c46b 577 address;
pmallick 0:e8a1ba50c46b 578
pmallick 0:e8a1ba50c46b 579 i2c_write(dev->i2c_desc, rb_data_i2c, 3, 0);
pmallick 0:e8a1ba50c46b 580 i2c_read(dev->i2c_desc, rb_data_i2c, 2, 1);
pmallick 0:e8a1ba50c46b 581 read_back_data = (rb_data_i2c[0] << 8) | rb_data_i2c[1];
pmallick 0:e8a1ba50c46b 582 }
pmallick 0:e8a1ba50c46b 583
pmallick 0:e8a1ba50c46b 584 return read_back_data;
pmallick 0:e8a1ba50c46b 585 }
pmallick 0:e8a1ba50c46b 586
pmallick 0:e8a1ba50c46b 587 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 588 * @brief Set Power-down mode for DAC channel n
pmallick 0:e8a1ba50c46b 589 *
pmallick 0:e8a1ba50c46b 590 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 591 * @param channel - The chosen channel to change the power-down mode.
pmallick 0:e8a1ba50c46b 592 * Accepted values: AD5686_CH_0
pmallick 0:e8a1ba50c46b 593 * AD5686_CH_1
pmallick 0:e8a1ba50c46b 594 * AD5686_CH_2
pmallick 0:e8a1ba50c46b 595 * AD5686_CH_3
pmallick 0:e8a1ba50c46b 596 * AD5686_CH_4
pmallick 0:e8a1ba50c46b 597 * AD5686_CH_5
pmallick 0:e8a1ba50c46b 598 * AD5686_CH_6
pmallick 0:e8a1ba50c46b 599 * AD5686_CH_7
pmallick 0:e8a1ba50c46b 600 * AD5686_CH_8
pmallick 0:e8a1ba50c46b 601 * AD5686_CH_9
pmallick 0:e8a1ba50c46b 602 * AD5686_CH_10
pmallick 0:e8a1ba50c46b 603 * AD5686_CH_11
pmallick 0:e8a1ba50c46b 604 * AD5686_CH_12
pmallick 0:e8a1ba50c46b 605 * AD5686_CH_13
pmallick 0:e8a1ba50c46b 606 * AD5686_CH_14
pmallick 0:e8a1ba50c46b 607 * AD5686_CH_15
pmallick 0:e8a1ba50c46b 608 * @param mode - Power-down operation modes.
pmallick 0:e8a1ba50c46b 609 * Accepted values:
pmallick 0:e8a1ba50c46b 610 * 'AD5686_PWRM_NORMAL' - Normal Mode
pmallick 0:e8a1ba50c46b 611 * 'AD5686_PWRM_1K' - Power-down mode 1kOhm to GND
pmallick 0:e8a1ba50c46b 612 * 'AD5686_PWRM_100K' - Power-down mode 100kOhm to GND
pmallick 0:e8a1ba50c46b 613 * 'AD5686_PWRM_THREESTATE' - Three-State
pmallick 0:e8a1ba50c46b 614 * 'AD5686_PWRM_100K' is not available for AD5674R/AD5679R.
pmallick 0:e8a1ba50c46b 615 *
pmallick 0:e8a1ba50c46b 616 * @return None.
pmallick 0:e8a1ba50c46b 617 ******************************************************************************/
pmallick 0:e8a1ba50c46b 618 void ad5686_power_mode(struct ad5686_dev *dev,
pmallick 0:e8a1ba50c46b 619 enum ad5686_dac_channels channel,
pmallick 0:e8a1ba50c46b 620 uint8_t mode)
pmallick 0:e8a1ba50c46b 621 {
pmallick 0:e8a1ba50c46b 622 uint8_t address = chip_info[dev->act_device].channel_addr[channel];
pmallick 0:e8a1ba50c46b 623
pmallick 0:e8a1ba50c46b 624 if(chip_info[dev->act_device].register_map == AD5686_REG_MAP) {
pmallick 0:e8a1ba50c46b 625 /* AD5674R/AD5679R have 16 channels and 2 powerdown registers */
pmallick 0:e8a1ba50c46b 626 if (channel > AD5686_CH_7)
pmallick 0:e8a1ba50c46b 627 channel -= AD5686_CH_7 + 1;
pmallick 0:e8a1ba50c46b 628 dev->power_down_mask &= ~(0x3 << (channel *2));
pmallick 0:e8a1ba50c46b 629 dev->power_down_mask |= (mode << (channel *2));
pmallick 0:e8a1ba50c46b 630 ad5686_set_shift_reg(dev, AD5686_CTRL_PWR, address,
pmallick 0:e8a1ba50c46b 631 dev->power_down_mask);
pmallick 0:e8a1ba50c46b 632 } else {
pmallick 0:e8a1ba50c46b 633 ad5686_set_shift_reg(dev, AD5683_CMD_WR_CTRL_REG, address,
pmallick 0:e8a1ba50c46b 634 AD5683_CTRL_PWRM(mode));
pmallick 0:e8a1ba50c46b 635 }
pmallick 0:e8a1ba50c46b 636
pmallick 0:e8a1ba50c46b 637 }
pmallick 0:e8a1ba50c46b 638
pmallick 0:e8a1ba50c46b 639 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 640 * @brief Set hardware LDAC mask register
pmallick 0:e8a1ba50c46b 641 *
pmallick 0:e8a1ba50c46b 642 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 643 * @param channel - In case of which channel ignore transitions on the LDAC
pmallick 0:e8a1ba50c46b 644 * pin.
pmallick 0:e8a1ba50c46b 645 * Accepted values: AD5686_CH_0
pmallick 0:e8a1ba50c46b 646 * AD5686_CH_1
pmallick 0:e8a1ba50c46b 647 * AD5686_CH_2
pmallick 0:e8a1ba50c46b 648 * AD5686_CH_3
pmallick 0:e8a1ba50c46b 649 * AD5686_CH_4
pmallick 0:e8a1ba50c46b 650 * AD5686_CH_5
pmallick 0:e8a1ba50c46b 651 * AD5686_CH_6
pmallick 0:e8a1ba50c46b 652 * AD5686_CH_7
pmallick 0:e8a1ba50c46b 653 * AD5686_CH_8
pmallick 0:e8a1ba50c46b 654 * AD5686_CH_9
pmallick 0:e8a1ba50c46b 655 * AD5686_CH_10
pmallick 0:e8a1ba50c46b 656 * AD5686_CH_11
pmallick 0:e8a1ba50c46b 657 * AD5686_CH_12
pmallick 0:e8a1ba50c46b 658 * AD5686_CH_13
pmallick 0:e8a1ba50c46b 659 * AD5686_CH_14
pmallick 0:e8a1ba50c46b 660 * AD5686_CH_15
pmallick 0:e8a1ba50c46b 661 * @param enable - Enable/disable channel.
pmallick 0:e8a1ba50c46b 662 * @return None.
pmallick 0:e8a1ba50c46b 663 ******************************************************************************/
pmallick 0:e8a1ba50c46b 664 void ad5686_ldac_mask(struct ad5686_dev *dev,
pmallick 0:e8a1ba50c46b 665 enum ad5686_dac_channels channel,
pmallick 0:e8a1ba50c46b 666 uint8_t enable)
pmallick 0:e8a1ba50c46b 667 {
pmallick 0:e8a1ba50c46b 668 if(chip_info[dev->act_device].register_map == AD5686_REG_MAP) {
pmallick 0:e8a1ba50c46b 669 dev->ldac_mask &= ~(0x1 << channel);
pmallick 0:e8a1ba50c46b 670 dev->ldac_mask |= (enable << channel);
pmallick 0:e8a1ba50c46b 671 ad5686_set_shift_reg(dev, AD5686_CTRL_LDAC_MASK, 0, dev->ldac_mask);
pmallick 0:e8a1ba50c46b 672 }
pmallick 0:e8a1ba50c46b 673 }
pmallick 0:e8a1ba50c46b 674
pmallick 0:e8a1ba50c46b 675 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 676 * @brief Software reset (power-on reset)
pmallick 0:e8a1ba50c46b 677 *
pmallick 0:e8a1ba50c46b 678 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 679 *
pmallick 0:e8a1ba50c46b 680 * @return None.
pmallick 0:e8a1ba50c46b 681 ******************************************************************************/
pmallick 0:e8a1ba50c46b 682 void ad5686_software_reset(struct ad5686_dev *dev)
pmallick 0:e8a1ba50c46b 683 {
pmallick 0:e8a1ba50c46b 684 if(chip_info[dev->act_device].register_map == AD5686_REG_MAP)
pmallick 0:e8a1ba50c46b 685 ad5686_set_shift_reg(dev, AD5686_CTRL_SWRESET, 0, 0);
pmallick 0:e8a1ba50c46b 686 else
pmallick 0:e8a1ba50c46b 687 ad5686_set_shift_reg(dev, AD5683_CMD_WR_CTRL_REG, 0, AD5683_SW_RESET);
pmallick 0:e8a1ba50c46b 688 }
pmallick 0:e8a1ba50c46b 689
pmallick 0:e8a1ba50c46b 690
pmallick 0:e8a1ba50c46b 691 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 692 * @brief Write to Internal reference setup register
pmallick 0:e8a1ba50c46b 693 *
pmallick 0:e8a1ba50c46b 694 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 695 * @param value - The internal reference register value
pmallick 0:e8a1ba50c46b 696 * Example : 'AD5686_INTREF_EN' - enable internal reference
pmallick 0:e8a1ba50c46b 697 * 'AD5686_INTREF_DIS' - disable internal reference
pmallick 0:e8a1ba50c46b 698 *
pmallick 0:e8a1ba50c46b 699 * @return None.
pmallick 0:e8a1ba50c46b 700 ******************************************************************************/
pmallick 0:e8a1ba50c46b 701 void ad5686_internal_reference(struct ad5686_dev *dev,
pmallick 0:e8a1ba50c46b 702 uint8_t value)
pmallick 0:e8a1ba50c46b 703 {
pmallick 0:e8a1ba50c46b 704 if(chip_info[dev->act_device].register_map == AD5686_REG_MAP)
pmallick 0:e8a1ba50c46b 705 ad5686_set_shift_reg(dev, AD5686_CTRL_IREF_REG, 0, value);
pmallick 0:e8a1ba50c46b 706 else
pmallick 0:e8a1ba50c46b 707 ad5686_set_shift_reg(dev, AD5683_CMD_WR_CTRL_REG, 0,
pmallick 0:e8a1ba50c46b 708 AD5683_CTRL_INT_REF(value));
pmallick 0:e8a1ba50c46b 709 }
pmallick 0:e8a1ba50c46b 710
pmallick 0:e8a1ba50c46b 711 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 712 * @brief Set up DCEN register (daisy-chain enable)
pmallick 0:e8a1ba50c46b 713 *
pmallick 0:e8a1ba50c46b 714 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 715 * @param value - Enable or disable daisy-chain mode
pmallick 0:e8a1ba50c46b 716 * Example : 'AD5686_DC_EN' - daisy-chain enable
pmallick 0:e8a1ba50c46b 717 * 'AD5686_DC_DIS' - daisy-chain disable
pmallick 0:e8a1ba50c46b 718 *
pmallick 0:e8a1ba50c46b 719 * @return None.
pmallick 0:e8a1ba50c46b 720 ******************************************************************************/
pmallick 0:e8a1ba50c46b 721 void ad5686_daisy_chain_en(struct ad5686_dev *dev,
pmallick 0:e8a1ba50c46b 722 uint8_t value)
pmallick 0:e8a1ba50c46b 723 {
pmallick 0:e8a1ba50c46b 724 if(chip_info[dev->act_device].register_map == AD5686_REG_MAP)
pmallick 0:e8a1ba50c46b 725 ad5686_set_shift_reg(dev, AD5686_CTRL_DCEN, 0, value);
pmallick 0:e8a1ba50c46b 726 else
pmallick 0:e8a1ba50c46b 727 ad5686_set_shift_reg(dev, AD5683_CMD_WR_CTRL_REG, 0, AD5683_CTRL_DCEN(value));
pmallick 0:e8a1ba50c46b 728 }
pmallick 0:e8a1ba50c46b 729
pmallick 0:e8a1ba50c46b 730 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 731 * @brief Set up readback register (readback enable)
pmallick 0:e8a1ba50c46b 732 *
pmallick 0:e8a1ba50c46b 733 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 734 * @param value - Enable or disable daisy-chain mode
pmallick 0:e8a1ba50c46b 735 * Example : 'AD5686_RB_EN' - daisy-chain enable
pmallick 0:e8a1ba50c46b 736 * 'AD5686_RB_DIS' - daisy-chain disable
pmallick 0:e8a1ba50c46b 737 *
pmallick 0:e8a1ba50c46b 738 * @return None.
pmallick 0:e8a1ba50c46b 739 ******************************************************************************/
pmallick 0:e8a1ba50c46b 740 void ad5686_read_back_en(struct ad5686_dev *dev,
pmallick 0:e8a1ba50c46b 741 uint8_t value)
pmallick 0:e8a1ba50c46b 742 {
pmallick 0:e8a1ba50c46b 743 if(chip_info[dev->act_device].register_map == AD5686_REG_MAP)
pmallick 0:e8a1ba50c46b 744 ad5686_set_shift_reg(dev, AD5686_CTRL_RB_REG, 0, value);
pmallick 0:e8a1ba50c46b 745 }
pmallick 0:e8a1ba50c46b 746
pmallick 0:e8a1ba50c46b 747 /**************************************************************************//**
pmallick 0:e8a1ba50c46b 748 * @brief Set Gain mode
pmallick 0:e8a1ba50c46b 749 *
pmallick 0:e8a1ba50c46b 750 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 751 * @param value - Gain modes.
pmallick 0:e8a1ba50c46b 752 * Accepted values:
pmallick 0:e8a1ba50c46b 753 * Example : 'AD5683_GB_VREF' - 0V to VREF
pmallick 0:e8a1ba50c46b 754 * 'AD5683_GB_2VREF' - 0V to 2xVREF
pmallick 0:e8a1ba50c46b 755 *
pmallick 0:e8a1ba50c46b 756 * @return None.
pmallick 0:e8a1ba50c46b 757 ******************************************************************************/
pmallick 0:e8a1ba50c46b 758 int32_t ad5686_gain_mode(struct ad5686_dev *dev, uint8_t value)
pmallick 0:e8a1ba50c46b 759 {
pmallick 0:e8a1ba50c46b 760 if(chip_info[dev->act_device].register_map == AD5683_REG_MAP)
pmallick 0:e8a1ba50c46b 761 return ad5686_set_shift_reg(dev, AD5683_CMD_WR_CTRL_REG, 0,
pmallick 0:e8a1ba50c46b 762 AD5683_CTRL_GM(value));
pmallick 0:e8a1ba50c46b 763 return -1;
pmallick 0:e8a1ba50c46b 764 }