Diff: I2CDriverTest03.h

Revision:

13:530968937ccb

Parent:

7:04824382eafb

Child:

14:352609d395c1

--- a/I2CDriverTest03.h	Fri May 10 07:34:24 2013 +0000
+++ b/I2CDriverTest03.h	Fri May 10 20:38:35 2013 +0000
@@ -1,173 +1,97 @@
 #include "mbed.h"
 #include "rtos.h"
 #include "I2CMasterRtos.h"
-#include "stdint.h"
+#include "I2CSlaveRtos.h"
 
-const int dataReadySig = 1<<5;
-osThreadId mainThreadID = 0;
-char data[64];
-int16_t fifo[16];
-const int i2cAdr = 0x68<<1;
-int fifoAdr = 0x72;
+const int freq = 400000;
+const int adr = 42<<1;
+const int len=34;
+const char mstMsg[len]="We are mbed, resistance is futile";
+const char slvMsg[len]="Fine with me, let's get addicted ";
 
-//Serial pc(USBTX, USBRX);
-
-void configMPU6050(I2CMasterRtos& i2c);
-void config(I2CMasterRtos& i2c);
+static void slvRxMsg(I2CSlaveRtos& slv)
+{
+    char rxMsg[len];
+    memset(rxMsg,0,len);
+    if ( slv.receive() == I2CSlave::WriteAddressed ) {
+        int cnt=0;
+        while(cnt<len) rxMsg[cnt++]=slv.read();
+        slv.stop(); // stop sretching low level of scl
+        printf("thread %x received message (sz=%d) as i2c slave: '%s'\n",Thread::gettid(),cnt,rxMsg);
+    } else
+        printf("Ouch slv rx failure\n");
+}
 
+static void slvTxMsg(I2CSlaveRtos& slv)
+{
+    if ( slv.receive()==I2CSlave::ReadAddressed) {
+        int cnt=0;
+        while(cnt<len && slv.write(slvMsg[cnt++]));
+        slv.stop(); // stop sretching low level of scl
+    } else
+        printf("Ouch slv tx failure\n");
+}
 
-void dataReadyIsr()
+static void mstTxMsg(I2CMasterRtos& mst)
 {
-    osSignalSet(mainThreadID, dataReadySig);
+    mst.start();
+    if(!mst.write(adr & 0xfe))printf("adr+W not acked\n");
+    int cnt=0;
+    while(cnt<len && mst.write(mstMsg[cnt++]));
+    // give the slave a chance to stop stretching scl to low, otherwise we will busy wait for the stop forever
+    while(!mst.stop())Thread::wait(1);
 }
 
-void readModWrite(I2CMasterRtos& i2c, uint8_t reg, uint8_t dta)
+static void mstRxMsg(I2CMasterRtos& mst)
 {
+    char rxMsg[len];
+    memset(rxMsg,0,len);
     
-    char rd1;
-    int rStat1 = i2c.read(i2cAdr, reg, &rd1, 1);
-    char data[2];
-    data[0]=(char)reg;
-    data[1]=(char)dta;
-    char rd2;
-    int wStat = i2c.write(i2cAdr, data, 2);
-    osDelay(500);
-    int rStat2 = i2c.read(i2cAdr, reg, &rd2, 1);
-    printf("%2d%2d%2d  %2x <- %2x  => %2x -> %2x \n", rStat1, wStat, rStat2, reg, dta, rd1, rd2);
+    mst.lock(); // no special reason, just a test
+    mst.start();
+    if(!mst.write(adr | 0x01))printf("adr+R not acked\n");
+    int cnt=0;
+    while(cnt<len-1) rxMsg[cnt++]=mst.read(1);
+    mst.unlock();
+    rxMsg[cnt++]=mst.read(0);
+    // give the slave a chance to stop stretching scl to low, otherwise we will busy wait for the stop forever
+    while(!mst.stop())Thread::wait(1);
+    printf("thread %x received message (sz=%d) as i2c master: '%s'\n",Thread::gettid(),cnt,rxMsg);
 }
 
+static void channel1(void const *args)
+{
+    I2CMasterRtos mst(p9,p10,freq);
+    I2CSlaveRtos slv(p9,p10,freq,adr);
+    while(1) {
+        slvRxMsg(slv);
+        slvTxMsg(slv);
+        Thread::wait(100);
+        mstTxMsg(mst);
+        Thread::wait(100);
+        mstRxMsg(mst);
+    }
+}
+
+void channel2(void const *args)
+{
+    I2CMasterRtos mst(p28,p27,freq);
+    I2CSlaveRtos slv(p28,p27,freq,adr);
+    while(1) {
+        Thread::wait(100);
+        mstTxMsg(mst);
+        Thread::wait(100);
+        mstRxMsg(mst);
+        slvRxMsg(slv);
+        slvTxMsg(slv);
+    }
+}
 
 int doit()
 {
-    //pc.baud(115200);
-    mainThreadID = osThreadGetId();
-
-    I2CMasterRtos i2c(p28, p27,400000);
-    osDelay(500);
-
-    printf("Initialize ... \n");
-    config(i2c);
-
-    printf("Action!\n");
-
-    InterruptIn dataReadyIrq(p8);
-    dataReadyIrq.mode(PullNone);
-    dataReadyIrq.rise(&dataReadyIsr);
-
-    /*
-    data[0]=0x6a;   // pwr 1 reg
-    data[1]=(1<<6)|(1<<2); // fifo on
-    i2c.write(i2cAdr,data,2,1);
-
-    data[0]=0x38;   // irq conf  reg
-    data[1]=1;      // irq on data ready
-    i2c.write(i2cAdr,data,2,1);
-    */
-    //fifoAdr = 0x3b;
-    char devNull;
-    while(1) {
-        osSignalWait(dataReadySig, 1000); // osWaitForever
-        i2c.read(i2cAdr,fifoAdr,data,2);
-        i2c.read(i2cAdr,fifoAdr+2,data+2,12);
-        i2c.read(i2cAdr,0x3a,&devNull,1);
-        for(int i=0; i<7; i++) {
-            fifo[i] = (data[2*i]<<8) | data[2*i+1];
-            printf("%8d",fifo[i]);
-        }
-        printf("     %x\n",devNull);
-
-    }
+    Thread selftalk01(channel1,0);
+    Thread selftalk02(channel2,0);
+    Thread::wait(5000);
     return 0;
 }
 
-static void config(I2CMasterRtos& i2c)
-{
-    uint8_t ncfg=32;
-    uint8_t regs[ncfg];
-    uint8_t vals[ncfg];
-    int cnt=0;
-    regs[cnt]=0x6b;
-    vals[cnt++]=(1<<7); // pwr 1 reg //: device reset
-    regs[cnt]=0x6b;
-    vals[cnt++]=1; // pwr 1 reg // clock from x gyro all pwr sav modes off
-    regs[cnt]=0x19;
-    vals[cnt++]=199;  // sample rate divider reg  // sapmle rate = gyro rate / (1+x)
-    regs[cnt]=0x1a;
-    vals[cnt++]=1;// conf  reg // no ext frame sync / dig low pass set to 1 => 1kHz Sampling with ~200Hz bandwidth DLPF
-    regs[cnt]=0x1b;
-    vals[cnt++]=0;// gyro conf  reg // no test mode and gyro range 250°/s
-    regs[cnt]=0x1c;
-    vals[cnt++]=0;// accl conf  reg // no test mode and accl range 2g
-    regs[cnt]=0x23;
-    vals[cnt++]=0xf<<3;// fifo conf  reg // accl + all gyro -> fifo
-    regs[cnt]=0x37;
-    vals[cnt++]=(0<<7)|(0<<6)|(0<<5)|(0<<4); // irq conf  reg // act high | 0:pupu 1:opnDrn| pulse | clear on any read
-    regs[cnt]=0x38;
-    vals[cnt++]=1|(1<<4); // irq conf  reg // irq on data ready
-    regs[cnt]=0x6a;
-    vals[cnt++]=(1<<2); // pwr 1 reg // fifo reset
-    regs[cnt]=0x6a;
-    vals[cnt++]=(1<<6); // pwr 1 reg // fifo on
-
-    /*
-    readModWrite(i2c, regs[0], vals[0]);
-    char reset=0xff;
-    while(reset&(1<<7)) {
-        osDelay(100);
-        i2c.read(i2cAdr,0x6b,&reset,1,1);
-    }
-    */
-    for(int i=0; i<cnt; i++)
-        readModWrite(i2c, regs[i], vals[i]);
-}
-
-static void configMPU6050(I2CMasterRtos& i2c)
-{
-
-    data[0]=0x6b;   // pwr 1 reg
-    data[1]=1<<7;   // device reset
-    i2c.write(i2cAdr,data,2,1);
-    char reset=0xff;
-    while(reset&(1<<7)) {
-        osDelay(100);
-        i2c.read(i2cAdr,0x6b,&reset,1,1);
-    }
-
-    data[0]=0x19;   // sample rate divider reg
-    data[1]=99;    // sapmle rate = gyro rate / (1+x)
-    i2c.write(i2cAdr,data,2,1);
-
-    data[0]=0x1a;   // conf  reg
-    data[1]=1;      // no ext frame sync / dig low pass set to 1 => 1kHz Sampling with ~200Hz bandwidth DLPF
-    i2c.write(i2cAdr,data,2,1);
-
-    data[0]=0x1b;   // gyro conf  reg
-    data[1]=0;      // no test mode and gyro range 250°/s
-    i2c.write(i2cAdr,data,2,1);
-
-    data[0]=0x1c;   // accl conf  reg
-    data[1]=0;      // no test mode and accl range 2g
-    i2c.write(i2cAdr,data,2,1);
-
-    data[0]=0x23;   // fifo conf  reg
-    data[1]=0xf<<3; // accl + all gyro -> fifo
-    i2c.write(i2cAdr,data,2,1);
-
-    data[0]=0x37;   // irq conf  reg
-    data[1]=(1<<7)|(0<<6)|(0<<5)|(1<<4); // act high | pupu | pulse | clear on any read
-    i2c.write(i2cAdr,data,2,1);
-
-    /*
-    data[0]=0x38;   // irq conf  reg
-    data[1]=1;      // irq on data ready
-    i2c.write(i2cAdr,data,2,1);
-
-    data[0]=0x6a;   // pwr 1 reg
-    data[1]=(1<<6); // fifo on
-    i2c.write(i2cAdr,data,2,1);
-    */
-    data[0]=0x6b;   // pwr 1 reg
-    data[1]=1;      // clock from x gyro all pwr sav modes off
-    i2c.write(i2cAdr,data,2,1);
-}
-