Watchdog timer for stm32f10x

Dependents:   F103-Web-Server

Fork of Watchdog by David Smart

Revision:
5:38379e44fae3
Parent:
3:5959d3d35221
--- a/Watchdog.cpp	Sat Oct 11 17:28:07 2014 +0000
+++ b/Watchdog.cpp	Sat Nov 15 11:44:16 2014 +0000
@@ -18,27 +18,31 @@
 
 /// Watchdog gets instantiated at the module level
 Watchdog::Watchdog() {
-    wdreset = (LPC_WDT->WDMOD >> 2) & 1;    // capture the cause of the previous reset
+    wdreset = false;
 }
 
 /// Load timeout value in watchdog timer and enable
-void Watchdog::Configure(float s) {
-    LPC_WDT->WDCLKSEL = 0x1;                // Set CLK src to PCLK
-    uint32_t clk = SystemCoreClock / 16;    // WD has a fixed /4 prescaler, PCLK default is /4
-    LPC_WDT->WDTC = (uint32_t)(s * (float)clk);
-    LPC_WDT->WDMOD = 0x3;                   // Enabled and Reset
-    Service();
+void Watchdog::Configure(int pr) {
+    // http://www.st.com/web/en/resource/technical/document/reference_manual/CD00171190.pdf
+    IWDG->KR  = 0x5555;                                   // enable write to PR, RLR
+    IWDG->PR  = pr;                                        // Init prescaler, page 486 Reference Manual
+    IWDG->RLR = 0xFFF;                                    // Init RLR
+    IWDG->KR  = 0xAAAA;                                   // Reload the watchdog
+    IWDG->KR  = 0xCCCC;
 }
 
 /// "Service", "kick" or "feed" the dog - reset the watchdog timer
 /// by writing this required bit pattern
 void Watchdog::Service() {
-    LPC_WDT->WDFEED = 0xAA;
-    LPC_WDT->WDFEED = 0x55;
+    IWDG->KR  = 0xAAAA;
 }
 
 /// get the flag to indicate if the watchdog causes the reset
 bool Watchdog::WatchdogCausedReset() {
+    if (RCC->CSR & (1<<29)) {
+        wdreset = true;
+        RCC->CSR |= (1<<24); // clear reset flag
+    }
     return wdreset;
 }