0. What is this?¶

A sample code for I²C Fast mode plus operation.
Recent I²C standard defines "Fast mode plus (Fm+)" for faster and robust I²C data transfer.
It supports 1MHz SCL (bit clock) and 20mA_min sink current capability.

The class library "I2C_FmPlus" enables the I²C port of bed-LPC11U24 for the Fm+.

1. Operation sample¶

Next waveform was captured while the sample code is running.
I put 270Ω pull-up resisters on SDA and SCL lines to accelerate rise-time.

If you use weak (bigger value) resisters, the rise time will get slow and it makes lower SCL frequency.
Since the I²C interface supports "clock stretching", the slower rise time makes longer LOW time and master detects it as "someone on the bus pulling the signal LOW to keep me waiting".
Due to this mechanism, user may need to adjust the clock frequency for each bus loading conditions.

9 bytes transfer of sample code

transfer around start-condition

transfer around stop-condition