Nanda Fathurrahman / Mbed OS COG4050_adxl355_adxl357

Fixed algorithm to read 3 bytes of accelerometer data registers

Fork of COG4050_adxl355_adxl357 by valeria toffoli

ADXL35x/ADXL355.h@10:e054891b3598, 2018-09-10 (annotated)

Committer:
nfathurr
Date:
Mon Sep 10 10:01:49 2018 +0000
Revision:
10:e054891b3598
Parent:
8:9e6ead2ee8d7 
Fixed algorithm to read 3 bytes of accelerometer data registers

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vtoffoli 2:14dc1ec57f3b 1
vtoffoli 2:14dc1ec57f3b 2 #ifndef ADXL355_H_
vtoffoli 2:14dc1ec57f3b 3 #define ADXL355_H_
vtoffoli 2:14dc1ec57f3b 4
vtoffoli 2:14dc1ec57f3b 5 class ADXL355
vtoffoli 2:14dc1ec57f3b 6 {
nfathurr 10:e054891b3598 7 public:
vtoffoli 7:5aaa09c40283 8 // -------------------------- //
nfathurr 10:e054891b3598 9 // CONST AND VARIABLES //
nfathurr 10:e054891b3598 10 const static float t_sens = -9.05;
nfathurr 10:e054891b3598 11 const static float t_bias = 1852;
vtoffoli 6:45d2393ef468 12 float axis355_sens;
nfathurr 10:e054891b3598 13 float axis357_sens; //scale factor in ug per LSB
vtoffoli 2:14dc1ec57f3b 14 // -------------------------- //
nfathurr 10:e054891b3598 15 // REGISTERS //
vtoffoli 2:14dc1ec57f3b 16 // -------------------------- //
vtoffoli 2:14dc1ec57f3b 17 typedef enum {
vtoffoli 2:14dc1ec57f3b 18 DEVID_AD = 0x00,
vtoffoli 2:14dc1ec57f3b 19 DEVID_MST = 0x01,
vtoffoli 2:14dc1ec57f3b 20 PARTID = 0x02,
vtoffoli 2:14dc1ec57f3b 21 REVID = 0x03,
vtoffoli 2:14dc1ec57f3b 22 STATUS = 0x04,
vtoffoli 2:14dc1ec57f3b 23 FIFO_ENTRIES = 0x05,
vtoffoli 2:14dc1ec57f3b 24 TEMP2 = 0x06,
vtoffoli 2:14dc1ec57f3b 25 TEMP1 = 0x07,
vtoffoli 2:14dc1ec57f3b 26 XDATA3 = 0x08,
vtoffoli 2:14dc1ec57f3b 27 XDATA2 = 0x09,
vtoffoli 2:14dc1ec57f3b 28 XDATA1 = 0x0A,
vtoffoli 2:14dc1ec57f3b 29 YDATA3 = 0x0B,
vtoffoli 2:14dc1ec57f3b 30 YDATA2 = 0x0C,
vtoffoli 2:14dc1ec57f3b 31 YDATA1 = 0x0D,
vtoffoli 2:14dc1ec57f3b 32 ZDATA3 = 0x0E,
vtoffoli 2:14dc1ec57f3b 33 ZDATA2 = 0x0F,
vtoffoli 2:14dc1ec57f3b 34 ZDATA1 = 0x10,
vtoffoli 2:14dc1ec57f3b 35 FIFO_DATA = 0x11,
vtoffoli 2:14dc1ec57f3b 36 OFFSET_X_H = 0x1E,
vtoffoli 2:14dc1ec57f3b 37 OFFSET_X_L = 0x1F,
vtoffoli 2:14dc1ec57f3b 38 OFFSET_Y_H = 0x20,
vtoffoli 2:14dc1ec57f3b 39 OFFSET_Y_L = 0x21,
vtoffoli 2:14dc1ec57f3b 40 OFFSET_Z_H = 0x22,
vtoffoli 2:14dc1ec57f3b 41 OFFSET_Z_L = 0x23,
vtoffoli 2:14dc1ec57f3b 42 ACT_EN = 0x24,
vtoffoli 2:14dc1ec57f3b 43 ACT_THRESH_H = 0x25,
vtoffoli 2:14dc1ec57f3b 44 ACT_THRESH_L = 0x26,
vtoffoli 2:14dc1ec57f3b 45 ACT_COUNT = 0x27,
vtoffoli 2:14dc1ec57f3b 46 FILTER = 0x28,
vtoffoli 2:14dc1ec57f3b 47 FIFO_SAMPLES = 0x29,
vtoffoli 2:14dc1ec57f3b 48 INT_MAP = 0x2A,
vtoffoli 2:14dc1ec57f3b 49 SYNC = 0x2B,
vtoffoli 2:14dc1ec57f3b 50 RANGE = 0x2C,
vtoffoli 2:14dc1ec57f3b 51 POWER_CTL = 0x2D,
vtoffoli 2:14dc1ec57f3b 52 SELF_TEST = 0x2E,
vtoffoli 2:14dc1ec57f3b 53 RESET = 0x2F
vtoffoli 2:14dc1ec57f3b 54 } ADXL355_register_t;
vtoffoli 2:14dc1ec57f3b 55 // -------------------------- //
vtoffoli 2:14dc1ec57f3b 56 // REGISTERS - DEFAULT VALUES //
vtoffoli 2:14dc1ec57f3b 57 // -------------------------- //
nfathurr 10:e054891b3598 58 // Modes - POWER_CTL
vtoffoli 2:14dc1ec57f3b 59 typedef enum {
vtoffoli 2:14dc1ec57f3b 60 DRDY_OFF = 0x04,
vtoffoli 2:14dc1ec57f3b 61 TEMP_OFF = 0x02,
vtoffoli 4:23b53636b576 62 STANDBY = 0x01,
vtoffoli 4:23b53636b576 63 MEASUREMENT = 0x00
nfathurr 10:e054891b3598 64 } ADXL355_modes_t;
nfathurr 10:e054891b3598 65 // Activate Threshold - ACT_EN
vtoffoli 2:14dc1ec57f3b 66 typedef enum {
vtoffoli 2:14dc1ec57f3b 67 ACT_Z = 0x04,
vtoffoli 2:14dc1ec57f3b 68 ACT_Y = 0x02,
vtoffoli 2:14dc1ec57f3b 69 ACT_X = 0x01
vtoffoli 2:14dc1ec57f3b 70 } ADXL355_act_ctl_t;
nfathurr 10:e054891b3598 71 // High-Pass and Low-Pass Filter - FILTER
vtoffoli 2:14dc1ec57f3b 72 typedef enum {
vtoffoli 2:14dc1ec57f3b 73 HPFOFF = 0x00,
vtoffoli 2:14dc1ec57f3b 74 HPF247 = 0x10,
vtoffoli 2:14dc1ec57f3b 75 HPF62 = 0x20,
vtoffoli 2:14dc1ec57f3b 76 HPF15 = 0x30,
vtoffoli 2:14dc1ec57f3b 77 HPF3 = 0x40,
vtoffoli 2:14dc1ec57f3b 78 HPF09 = 0x50,
vtoffoli 2:14dc1ec57f3b 79 HPF02 = 0x60,
vtoffoli 2:14dc1ec57f3b 80 ODR4000HZ = 0x00,
vtoffoli 2:14dc1ec57f3b 81 ODR2000HZ = 0x01,
vtoffoli 2:14dc1ec57f3b 82 ODR1000HZ = 0x02,
vtoffoli 2:14dc1ec57f3b 83 ODR500HZ = 0x03,
vtoffoli 2:14dc1ec57f3b 84 ODR250HZ = 0x04,
vtoffoli 2:14dc1ec57f3b 85 ODR125Hz = 0x05,
vtoffoli 2:14dc1ec57f3b 86 ODR62HZ = 0x06,
vtoffoli 2:14dc1ec57f3b 87 ODR31Hz = 0x07,
vtoffoli 2:14dc1ec57f3b 88 ODR15Hz = 0x08,
vtoffoli 2:14dc1ec57f3b 89 ODR7Hz = 0x09,
vtoffoli 2:14dc1ec57f3b 90 ODR3HZ = 0x0A
vtoffoli 2:14dc1ec57f3b 91 } ADXL355_filter_ctl_t;
nfathurr 10:e054891b3598 92 // External timing register - INT_MAP
vtoffoli 2:14dc1ec57f3b 93 typedef enum {
vtoffoli 2:14dc1ec57f3b 94 OVR_EN = 0x04,
vtoffoli 2:14dc1ec57f3b 95 FULL_EN = 0x02,
vtoffoli 2:14dc1ec57f3b 96 RDY_EN = 0x01
vtoffoli 2:14dc1ec57f3b 97 } ADXL355_intmap_ctl_t;
nfathurr 10:e054891b3598 98 // External timing register - SYNC
vtoffoli 2:14dc1ec57f3b 99 typedef enum {
vtoffoli 2:14dc1ec57f3b 100 EXT_CLK = 0x04,
vtoffoli 2:14dc1ec57f3b 101 INT_SYNC = 0x00,
vtoffoli 2:14dc1ec57f3b 102 EXT_SYNC_NO_INT = 0x01,
vtoffoli 2:14dc1ec57f3b 103 EXT_SYNC_INT = 0x02
nfathurr 10:e054891b3598 104 } ADXL355_sync_ctl_t;
nfathurr 10:e054891b3598 105 // polarity and range - RANGE
vtoffoli 2:14dc1ec57f3b 106 typedef enum {
vtoffoli 2:14dc1ec57f3b 107 RANGE2G = 0x01,
vtoffoli 2:14dc1ec57f3b 108 RANGE4G = 0x02,
vtoffoli 2:14dc1ec57f3b 109 RANGE8G = 0x03,
vtoffoli 6:45d2393ef468 110 RANGE10 = 0x01,
vtoffoli 2:14dc1ec57f3b 111 RANGE20 = 0x02,
vtoffoli 2:14dc1ec57f3b 112 RANGE40 = 0x03
vtoffoli 2:14dc1ec57f3b 113 } ADXL355_range_ctl_t;
nfathurr 10:e054891b3598 114 // self test interrupt - INT
vtoffoli 2:14dc1ec57f3b 115 typedef enum {
vtoffoli 2:14dc1ec57f3b 116 ST2 = 0x02,
vtoffoli 2:14dc1ec57f3b 117 ST1 = 0x01
vtoffoli 2:14dc1ec57f3b 118 } ADXL355_int_ctl_t;
vtoffoli 2:14dc1ec57f3b 119 // -------------------------- //
nfathurr 10:e054891b3598 120 // FUNCTIONS //
vtoffoli 2:14dc1ec57f3b 121 // -------------------------- //
nfathurr 10:e054891b3598 122 // SPI configuration & constructor
vtoffoli 2:14dc1ec57f3b 123 ADXL355(PinName cs_pin , PinName MOSI , PinName MISO , PinName SCK );
vtoffoli 2:14dc1ec57f3b 124 void frequency(int hz);
nfathurr 10:e054891b3598 125 // Low level SPI bus comm methods
vtoffoli 2:14dc1ec57f3b 126 void reset(void);
vtoffoli 2:14dc1ec57f3b 127 void write_reg(ADXL355_register_t reg, uint8_t data);
vtoffoli 2:14dc1ec57f3b 128 void write_reg_u16(ADXL355_register_t reg, uint16_t data);
vtoffoli 2:14dc1ec57f3b 129 uint8_t read_reg(ADXL355_register_t reg);
vtoffoli 2:14dc1ec57f3b 130 uint16_t read_reg_u16(ADXL355_register_t reg);
vtoffoli 6:45d2393ef468 131 uint32_t read_reg_u20(ADXL355_register_t reg);
nfathurr 10:e054891b3598 132 // ADXL general register R/W methods
vtoffoli 2:14dc1ec57f3b 133 void set_power_ctl_reg(uint8_t data);
vtoffoli 2:14dc1ec57f3b 134 void set_filter_ctl_reg(ADXL355_filter_ctl_t hpf, ADXL355_filter_ctl_t odr);
vtoffoli 2:14dc1ec57f3b 135 void set_clk(ADXL355_sync_ctl_t data);
vtoffoli 2:14dc1ec57f3b 136 void set_device(ADXL355_range_ctl_t range);
vtoffoli 2:14dc1ec57f3b 137 uint8_t read_status();
nfathurr 10:e054891b3598 138 // ADXL X/Y/Z/T scanning methods
vtoffoli 2:14dc1ec57f3b 139 uint32_t scanx();
vtoffoli 2:14dc1ec57f3b 140 uint32_t scany();
vtoffoli 2:14dc1ec57f3b 141 uint32_t scanz();
vtoffoli 2:14dc1ec57f3b 142 uint16_t scant();
nfathurr 10:e054891b3598 143 // ADXL activity methods
vtoffoli 2:14dc1ec57f3b 144 void set_activity_axis(ADXL355_act_ctl_t axis);
vtoffoli 2:14dc1ec57f3b 145 void set_activity_cnt(uint8_t count);
vtoffoli 3:ee052fdb4331 146 void set_activity_threshold(uint8_t data_h, uint8_t data_l);
vtoffoli 2:14dc1ec57f3b 147 void set_inactivity();
nfathurr 10:e054891b3598 148 // ADXL interrupt methods
vtoffoli 2:14dc1ec57f3b 149 void set_interrupt1_pin(PinName in, ADXL355_intmap_ctl_t mode);
vtoffoli 2:14dc1ec57f3b 150 void set_interrupt2_pin(PinName in, ADXL355_intmap_ctl_t mode);
vtoffoli 2:14dc1ec57f3b 151 void enable_interrupt1();
vtoffoli 2:14dc1ec57f3b 152 void enable_interrupt2();
vtoffoli 2:14dc1ec57f3b 153 void disable_interrupt1();
vtoffoli 2:14dc1ec57f3b 154 void disable_interrupt2();
vtoffoli 2:14dc1ec57f3b 155 void set_polling_interrupt1_pin(uint8_t data);
vtoffoli 2:14dc1ec57f3b 156 void set_polling_interrupt2_pin(uint8_t data);
vtoffoli 2:14dc1ec57f3b 157 bool get_int1();
vtoffoli 2:14dc1ec57f3b 158 bool get_int2();
nfathurr 10:e054891b3598 159 // ADXL FIFO methods
vtoffoli 3:ee052fdb4331 160 uint8_t fifo_read_nr_of_entries();
vtoffoli 2:14dc1ec57f3b 161 void fifo_setup(uint8_t nr_of_entries);
vtoffoli 2:14dc1ec57f3b 162 uint32_t fifo_read_u32();
vtoffoli 2:14dc1ec57f3b 163 uint64_t fifo_scan();
vtoffoli 8:9e6ead2ee8d7 164 // ADXL conversion
vtoffoli 7:5aaa09c40283 165 float convert(uint32_t data);
nfathurr 10:e054891b3598 166
vtoffoli 2:14dc1ec57f3b 167 private:
vtoffoli 2:14dc1ec57f3b 168 // SPI adxl355; ///< SPI instance of the ADXL
nfathurr 10:e054891b3598 169 SPI adxl355;
nfathurr 10:e054891b3598 170 DigitalOut cs;
nfathurr 10:e054891b3598 171 const static uint8_t _DEVICE_AD = 0xAD; // contect of DEVID_AD (only-read) register
nfathurr 10:e054891b3598 172 const static uint8_t _RESET = 0x52; // reset code
vtoffoli 2:14dc1ec57f3b 173 const static uint8_t _DUMMY_BYTE = 0xAA; // 10101010
vtoffoli 2:14dc1ec57f3b 174 const static uint8_t _WRITE_REG_CMD = 0x00; // write register
vtoffoli 2:14dc1ec57f3b 175 const static uint8_t _READ_REG_CMD = 0x01; // read register
vtoffoli 2:14dc1ec57f3b 176 const static uint8_t _READ_FIFO_CMD = 0x23; // read FIFO
vtoffoli 2:14dc1ec57f3b 177 const static uint8_t _SPI_MODE = 0; // timing scheme
vtoffoli 2:14dc1ec57f3b 178 };
nfathurr 10:e054891b3598 179
vtoffoli 2:14dc1ec57f3b 180 #endif