Nanda Fathurrahman / Mbed OS COG4050_adxl355_adxl357

Fixed algorithm to read 3 bytes of accelerometer data registers

Fork of COG4050_adxl355_adxl357 by valeria toffoli

ADXL35x/ADXL355.h@7:5aaa09c40283, 2018-08-14 (annotated)

Committer:
vtoffoli
Date:
Tue Aug 14 11:33:30 2018 +0000
Revision:
7:5aaa09c40283
Parent:
6:45d2393ef468
Child:
8:9e6ead2ee8d7
update 14.08.2018;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vtoffoli 2:14dc1ec57f3b 1
vtoffoli 2:14dc1ec57f3b 2 #ifndef ADXL355_H_
vtoffoli 2:14dc1ec57f3b 3 #define ADXL355_H_
vtoffoli 2:14dc1ec57f3b 4
vtoffoli 2:14dc1ec57f3b 5 class ADXL355
vtoffoli 2:14dc1ec57f3b 6 {
vtoffoli 2:14dc1ec57f3b 7 public:
vtoffoli 7:5aaa09c40283 8 // -------------------------- //
vtoffoli 7:5aaa09c40283 9 // CONST AND VARIABLES //
vtoffoli 7:5aaa09c40283 10 // -------------------------- //
vtoffoli 7:5aaa09c40283 11 typedef struct {
vtoffoli 7:5aaa09c40283 12 // sensitivity
vtoffoli 7:5aaa09c40283 13 float Sxx;
vtoffoli 7:5aaa09c40283 14 float Sxy;
vtoffoli 7:5aaa09c40283 15 float Sxz;
vtoffoli 7:5aaa09c40283 16 float Syx;
vtoffoli 7:5aaa09c40283 17 float Syy;
vtoffoli 7:5aaa09c40283 18 float Syz;
vtoffoli 7:5aaa09c40283 19 float Szx;
vtoffoli 7:5aaa09c40283 20 float Szy;
vtoffoli 7:5aaa09c40283 21 float Szz;
vtoffoli 7:5aaa09c40283 22 float St;
vtoffoli 7:5aaa09c40283 23 // 0g offset
vtoffoli 7:5aaa09c40283 24 float Bx;
vtoffoli 7:5aaa09c40283 25 float By;
vtoffoli 7:5aaa09c40283 26 float Bz;
vtoffoli 7:5aaa09c40283 27 float Bt;
vtoffoli 7:5aaa09c40283 28 } ADXL355_calib_t;
vtoffoli 6:45d2393ef468 29 const static float t_sens = -9.05;
vtoffoli 6:45d2393ef468 30 const static float t_bias = 1852;
vtoffoli 6:45d2393ef468 31 float axis355_sens;
vtoffoli 6:45d2393ef468 32 float axis357_sens;
vtoffoli 7:5aaa09c40283 33 ADXL355_calib_t calib_data;
vtoffoli 2:14dc1ec57f3b 34 // -------------------------- //
vtoffoli 2:14dc1ec57f3b 35 // REGISTERS //
vtoffoli 2:14dc1ec57f3b 36 // -------------------------- //
vtoffoli 2:14dc1ec57f3b 37 typedef enum {
vtoffoli 2:14dc1ec57f3b 38 DEVID_AD = 0x00,
vtoffoli 2:14dc1ec57f3b 39 DEVID_MST = 0x01,
vtoffoli 2:14dc1ec57f3b 40 PARTID = 0x02,
vtoffoli 2:14dc1ec57f3b 41 REVID = 0x03,
vtoffoli 2:14dc1ec57f3b 42 STATUS = 0x04,
vtoffoli 2:14dc1ec57f3b 43 FIFO_ENTRIES = 0x05,
vtoffoli 2:14dc1ec57f3b 44 TEMP2 = 0x06,
vtoffoli 2:14dc1ec57f3b 45 TEMP1 = 0x07,
vtoffoli 2:14dc1ec57f3b 46 XDATA3 = 0x08,
vtoffoli 2:14dc1ec57f3b 47 XDATA2 = 0x09,
vtoffoli 2:14dc1ec57f3b 48 XDATA1 = 0x0A,
vtoffoli 2:14dc1ec57f3b 49 YDATA3 = 0x0B,
vtoffoli 2:14dc1ec57f3b 50 YDATA2 = 0x0C,
vtoffoli 2:14dc1ec57f3b 51 YDATA1 = 0x0D,
vtoffoli 2:14dc1ec57f3b 52 ZDATA3 = 0x0E,
vtoffoli 2:14dc1ec57f3b 53 ZDATA2 = 0x0F,
vtoffoli 2:14dc1ec57f3b 54 ZDATA1 = 0x10,
vtoffoli 2:14dc1ec57f3b 55 FIFO_DATA = 0x11,
vtoffoli 2:14dc1ec57f3b 56 OFFSET_X_H = 0x1E,
vtoffoli 2:14dc1ec57f3b 57 OFFSET_X_L = 0x1F,
vtoffoli 2:14dc1ec57f3b 58 OFFSET_Y_H = 0x20,
vtoffoli 2:14dc1ec57f3b 59 OFFSET_Y_L = 0x21,
vtoffoli 2:14dc1ec57f3b 60 OFFSET_Z_H = 0x22,
vtoffoli 2:14dc1ec57f3b 61 OFFSET_Z_L = 0x23,
vtoffoli 2:14dc1ec57f3b 62 ACT_EN = 0x24,
vtoffoli 2:14dc1ec57f3b 63 ACT_THRESH_H = 0x25,
vtoffoli 2:14dc1ec57f3b 64 ACT_THRESH_L = 0x26,
vtoffoli 2:14dc1ec57f3b 65 ACT_COUNT = 0x27,
vtoffoli 2:14dc1ec57f3b 66 FILTER = 0x28,
vtoffoli 2:14dc1ec57f3b 67 FIFO_SAMPLES = 0x29,
vtoffoli 2:14dc1ec57f3b 68 INT_MAP = 0x2A,
vtoffoli 2:14dc1ec57f3b 69 SYNC = 0x2B,
vtoffoli 2:14dc1ec57f3b 70 RANGE = 0x2C,
vtoffoli 2:14dc1ec57f3b 71 POWER_CTL = 0x2D,
vtoffoli 2:14dc1ec57f3b 72 SELF_TEST = 0x2E,
vtoffoli 2:14dc1ec57f3b 73 RESET = 0x2F
vtoffoli 2:14dc1ec57f3b 74 } ADXL355_register_t;
vtoffoli 2:14dc1ec57f3b 75 // -------------------------- //
vtoffoli 2:14dc1ec57f3b 76 // REGISTERS - DEFAULT VALUES //
vtoffoli 2:14dc1ec57f3b 77 // -------------------------- //
vtoffoli 2:14dc1ec57f3b 78 // Modes - POWER_CTL
vtoffoli 2:14dc1ec57f3b 79 typedef enum {
vtoffoli 2:14dc1ec57f3b 80 DRDY_OFF = 0x04,
vtoffoli 2:14dc1ec57f3b 81 TEMP_OFF = 0x02,
vtoffoli 4:23b53636b576 82 STANDBY = 0x01,
vtoffoli 4:23b53636b576 83 MEASUREMENT = 0x00
vtoffoli 2:14dc1ec57f3b 84 } ADXL355_modes_t;
vtoffoli 2:14dc1ec57f3b 85 // Activate Threshold - ACT_EN
vtoffoli 2:14dc1ec57f3b 86 typedef enum {
vtoffoli 2:14dc1ec57f3b 87 ACT_Z = 0x04,
vtoffoli 2:14dc1ec57f3b 88 ACT_Y = 0x02,
vtoffoli 2:14dc1ec57f3b 89 ACT_X = 0x01
vtoffoli 2:14dc1ec57f3b 90 } ADXL355_act_ctl_t;
vtoffoli 2:14dc1ec57f3b 91 // High-Pass and Low-Pass Filter - FILTER
vtoffoli 2:14dc1ec57f3b 92 typedef enum {
vtoffoli 2:14dc1ec57f3b 93 HPFOFF = 0x00,
vtoffoli 2:14dc1ec57f3b 94 HPF247 = 0x10,
vtoffoli 2:14dc1ec57f3b 95 HPF62 = 0x20,
vtoffoli 2:14dc1ec57f3b 96 HPF15 = 0x30,
vtoffoli 2:14dc1ec57f3b 97 HPF3 = 0x40,
vtoffoli 2:14dc1ec57f3b 98 HPF09 = 0x50,
vtoffoli 2:14dc1ec57f3b 99 HPF02 = 0x60,
vtoffoli 2:14dc1ec57f3b 100 ODR4000HZ = 0x00,
vtoffoli 2:14dc1ec57f3b 101 ODR2000HZ = 0x01,
vtoffoli 2:14dc1ec57f3b 102 ODR1000HZ = 0x02,
vtoffoli 2:14dc1ec57f3b 103 ODR500HZ = 0x03,
vtoffoli 2:14dc1ec57f3b 104 ODR250HZ = 0x04,
vtoffoli 2:14dc1ec57f3b 105 ODR125Hz = 0x05,
vtoffoli 2:14dc1ec57f3b 106 ODR62HZ = 0x06,
vtoffoli 2:14dc1ec57f3b 107 ODR31Hz = 0x07,
vtoffoli 2:14dc1ec57f3b 108 ODR15Hz = 0x08,
vtoffoli 2:14dc1ec57f3b 109 ODR7Hz = 0x09,
vtoffoli 2:14dc1ec57f3b 110 ODR3HZ = 0x0A
vtoffoli 2:14dc1ec57f3b 111 } ADXL355_filter_ctl_t;
vtoffoli 2:14dc1ec57f3b 112 // External timing register - INT_MAP
vtoffoli 2:14dc1ec57f3b 113 typedef enum {
vtoffoli 2:14dc1ec57f3b 114 OVR_EN = 0x04,
vtoffoli 2:14dc1ec57f3b 115 FULL_EN = 0x02,
vtoffoli 2:14dc1ec57f3b 116 RDY_EN = 0x01
vtoffoli 2:14dc1ec57f3b 117 } ADXL355_intmap_ctl_t;
vtoffoli 2:14dc1ec57f3b 118 // External timing register - SYNC
vtoffoli 2:14dc1ec57f3b 119 typedef enum {
vtoffoli 2:14dc1ec57f3b 120 EXT_CLK = 0x04,
vtoffoli 2:14dc1ec57f3b 121 INT_SYNC = 0x00,
vtoffoli 2:14dc1ec57f3b 122 EXT_SYNC_NO_INT = 0x01,
vtoffoli 2:14dc1ec57f3b 123 EXT_SYNC_INT = 0x02
vtoffoli 2:14dc1ec57f3b 124 } ADXL355_sync_ctl_t;
vtoffoli 2:14dc1ec57f3b 125 // polarity and range - RANGE
vtoffoli 2:14dc1ec57f3b 126 typedef enum {
vtoffoli 2:14dc1ec57f3b 127 RANGE2G = 0x01,
vtoffoli 2:14dc1ec57f3b 128 RANGE4G = 0x02,
vtoffoli 2:14dc1ec57f3b 129 RANGE8G = 0x03,
vtoffoli 6:45d2393ef468 130 RANGE10 = 0x01,
vtoffoli 2:14dc1ec57f3b 131 RANGE20 = 0x02,
vtoffoli 2:14dc1ec57f3b 132 RANGE40 = 0x03
vtoffoli 2:14dc1ec57f3b 133 } ADXL355_range_ctl_t;
vtoffoli 2:14dc1ec57f3b 134 // self test interrupt - INT
vtoffoli 2:14dc1ec57f3b 135 typedef enum {
vtoffoli 2:14dc1ec57f3b 136 ST2 = 0x02,
vtoffoli 2:14dc1ec57f3b 137 ST1 = 0x01
vtoffoli 2:14dc1ec57f3b 138 } ADXL355_int_ctl_t;
vtoffoli 2:14dc1ec57f3b 139 // -------------------------- //
vtoffoli 2:14dc1ec57f3b 140 // FUNCTIONS //
vtoffoli 2:14dc1ec57f3b 141 // -------------------------- //
vtoffoli 2:14dc1ec57f3b 142 // SPI configuration & constructor
vtoffoli 2:14dc1ec57f3b 143 ADXL355(PinName cs_pin , PinName MOSI , PinName MISO , PinName SCK );
vtoffoli 2:14dc1ec57f3b 144 void frequency(int hz);
vtoffoli 2:14dc1ec57f3b 145 // Low level SPI bus comm methods
vtoffoli 2:14dc1ec57f3b 146 void reset(void);
vtoffoli 2:14dc1ec57f3b 147 void write_reg(ADXL355_register_t reg, uint8_t data);
vtoffoli 2:14dc1ec57f3b 148 void write_reg_u16(ADXL355_register_t reg, uint16_t data);
vtoffoli 2:14dc1ec57f3b 149 uint8_t read_reg(ADXL355_register_t reg);
vtoffoli 2:14dc1ec57f3b 150 uint16_t read_reg_u16(ADXL355_register_t reg);
vtoffoli 6:45d2393ef468 151 uint32_t read_reg_u20(ADXL355_register_t reg);
vtoffoli 2:14dc1ec57f3b 152 // ADXL general register R/W methods
vtoffoli 2:14dc1ec57f3b 153 void set_power_ctl_reg(uint8_t data);
vtoffoli 2:14dc1ec57f3b 154 void set_filter_ctl_reg(ADXL355_filter_ctl_t hpf, ADXL355_filter_ctl_t odr);
vtoffoli 2:14dc1ec57f3b 155 void set_clk(ADXL355_sync_ctl_t data);
vtoffoli 2:14dc1ec57f3b 156 void set_device(ADXL355_range_ctl_t range);
vtoffoli 2:14dc1ec57f3b 157 uint8_t read_status();
vtoffoli 2:14dc1ec57f3b 158 // ADXL X/Y/Z/T scanning methods
vtoffoli 2:14dc1ec57f3b 159 uint32_t scanx();
vtoffoli 2:14dc1ec57f3b 160 uint32_t scany();
vtoffoli 2:14dc1ec57f3b 161 uint32_t scanz();
vtoffoli 2:14dc1ec57f3b 162 uint16_t scant();
vtoffoli 2:14dc1ec57f3b 163 // ADXL activity methods
vtoffoli 2:14dc1ec57f3b 164 void set_activity_axis(ADXL355_act_ctl_t axis);
vtoffoli 2:14dc1ec57f3b 165 void set_activity_cnt(uint8_t count);
vtoffoli 3:ee052fdb4331 166 void set_activity_threshold(uint8_t data_h, uint8_t data_l);
vtoffoli 2:14dc1ec57f3b 167 void set_inactivity();
vtoffoli 2:14dc1ec57f3b 168 // ADXL interrupt methods
vtoffoli 2:14dc1ec57f3b 169 void set_interrupt1_pin(PinName in, ADXL355_intmap_ctl_t mode);
vtoffoli 2:14dc1ec57f3b 170 void set_interrupt2_pin(PinName in, ADXL355_intmap_ctl_t mode);
vtoffoli 2:14dc1ec57f3b 171 void enable_interrupt1();
vtoffoli 2:14dc1ec57f3b 172 void enable_interrupt2();
vtoffoli 2:14dc1ec57f3b 173 void disable_interrupt1();
vtoffoli 2:14dc1ec57f3b 174 void disable_interrupt2();
vtoffoli 2:14dc1ec57f3b 175 void set_polling_interrupt1_pin(uint8_t data);
vtoffoli 2:14dc1ec57f3b 176 void set_polling_interrupt2_pin(uint8_t data);
vtoffoli 2:14dc1ec57f3b 177 bool get_int1();
vtoffoli 2:14dc1ec57f3b 178 bool get_int2();
vtoffoli 2:14dc1ec57f3b 179 // ADXL FIFO methods
vtoffoli 3:ee052fdb4331 180 uint8_t fifo_read_nr_of_entries();
vtoffoli 2:14dc1ec57f3b 181 void fifo_setup(uint8_t nr_of_entries);
vtoffoli 2:14dc1ec57f3b 182 uint32_t fifo_read_u32();
vtoffoli 2:14dc1ec57f3b 183 uint64_t fifo_scan();
vtoffoli 7:5aaa09c40283 184 // ADXL calibration
vtoffoli 7:5aaa09c40283 185 float convert(uint32_t data);
vtoffoli 7:5aaa09c40283 186 ADXL355_calib_t convert_2p();
vtoffoli 7:5aaa09c40283 187 ADXL355_calib_t convert_3to8p();
vtoffoli 7:5aaa09c40283 188 ADXL355_calib_t convert_12p();
vtoffoli 7:5aaa09c40283 189
vtoffoli 2:14dc1ec57f3b 190 private:
vtoffoli 2:14dc1ec57f3b 191 // SPI adxl355; ///< SPI instance of the ADXL
vtoffoli 2:14dc1ec57f3b 192 SPI adxl355; DigitalOut cs;
vtoffoli 2:14dc1ec57f3b 193 const static uint8_t _DEVICE_AD = 0xAD; // contect of DEVID_AD (only-read) register
vtoffoli 2:14dc1ec57f3b 194 const static uint8_t _RESET = 0x52; // reset code
vtoffoli 2:14dc1ec57f3b 195 const static uint8_t _DUMMY_BYTE = 0xAA; // 10101010
vtoffoli 2:14dc1ec57f3b 196 const static uint8_t _WRITE_REG_CMD = 0x00; // write register
vtoffoli 2:14dc1ec57f3b 197 const static uint8_t _READ_REG_CMD = 0x01; // read register
vtoffoli 2:14dc1ec57f3b 198 const static uint8_t _READ_FIFO_CMD = 0x23; // read FIFO
vtoffoli 2:14dc1ec57f3b 199 const static uint8_t _SPI_MODE = 0; // timing scheme
vtoffoli 2:14dc1ec57f3b 200 };
vtoffoli 2:14dc1ec57f3b 201
vtoffoli 2:14dc1ec57f3b 202 #endif