mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 113:b3775bf36a83

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_rcc.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	113:b3775bf36a83	5	* @version V1.5.0
mbed_official	113:b3775bf36a83	6	* @date 8-January-2016
bogdanm	0:9b334a45a8ff	7	* @brief Header file of RCC HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
mbed_official	113:b3775bf36a83	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32L0xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	40	#define __STM32L0xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32l0xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @defgroup RCC RCC
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
mbed_official	113:b3775bf36a83	57	/** @defgroup RCC_Exported_Types RCC Exported Types
mbed_official	113:b3775bf36a83	58	* @{
mbed_official	113:b3775bf36a83	59	*/
bogdanm	0:9b334a45a8ff	60
bogdanm	0:9b334a45a8ff	61	/**
bogdanm	0:9b334a45a8ff	62	* @brief RCC PLL configuration structure definition
bogdanm	0:9b334a45a8ff	63	*/
bogdanm	0:9b334a45a8ff	64	typedef struct
bogdanm	0:9b334a45a8ff	65	{
bogdanm	0:9b334a45a8ff	66	uint32_t PLLState; /*!< The new state of the PLL.
bogdanm	0:9b334a45a8ff	67	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	0:9b334a45a8ff	68
bogdanm	0:9b334a45a8ff	69	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
bogdanm	0:9b334a45a8ff	70	This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO output clock
bogdanm	0:9b334a45a8ff	73	This parameter must of @ref RCC_PLLMultiplication_Factor */
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75	uint32_t PLLDIV; /*!< PLLDIV: Division factor for main system clock (SYSCLK)
bogdanm	0:9b334a45a8ff	76	This parameter must be a value of @ref RCC_PLLDivider_Factor */
bogdanm	0:9b334a45a8ff	77
bogdanm	0:9b334a45a8ff	78	}RCC_PLLInitTypeDef;
bogdanm	0:9b334a45a8ff	79
bogdanm	0:9b334a45a8ff	80	/**
bogdanm	0:9b334a45a8ff	81	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm	0:9b334a45a8ff	82	*/
bogdanm	0:9b334a45a8ff	83	typedef struct
bogdanm	0:9b334a45a8ff	84	{
bogdanm	0:9b334a45a8ff	85	uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm	0:9b334a45a8ff	86	This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm	0:9b334a45a8ff	87
bogdanm	0:9b334a45a8ff	88	uint32_t HSEState; /*!< The new state of the HSE.
bogdanm	0:9b334a45a8ff	89	This parameter can be a value of @ref RCC_HSE_Config */
bogdanm	0:9b334a45a8ff	90
bogdanm	0:9b334a45a8ff	91	uint32_t LSEState; /*!< The new state of the LSE.
bogdanm	0:9b334a45a8ff	92	This parameter can be a value of @ref RCC_LSE_Config */
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	uint32_t HSIState; /*!< The new state of the HSI.
bogdanm	0:9b334a45a8ff	95	This parameter can be a value of @ref RCC_HSI_Config */
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
bogdanm	0:9b334a45a8ff	98	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	0:9b334a45a8ff	99
bogdanm	0:9b334a45a8ff	100	uint32_t LSIState; /*!< The new state of the LSI.
bogdanm	0:9b334a45a8ff	101	This parameter can be a value of @ref RCC_LSI_Config */
bogdanm	0:9b334a45a8ff	102
mbed_official	113:b3775bf36a83	103	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
mbed_official	113:b3775bf36a83	104	!defined (STM32L011xx) && !defined (STM32L021xx)
bogdanm	0:9b334a45a8ff	105	uint32_t HSI48State; /*!< The new state of the HSI48.
bogdanm	0:9b334a45a8ff	106	This parameter can be a value of @ref RCC_HSI48_Config */
bogdanm	0:9b334a45a8ff	107	#endif
bogdanm	0:9b334a45a8ff	108
bogdanm	0:9b334a45a8ff	109	uint32_t MSIState; /*!< The new state of the MSI.
bogdanm	0:9b334a45a8ff	110	This parameter can be a value of @ref RCC_MSI_Config */
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112	uint32_t MSICalibrationValue; /*!< The calibration trimming value.
bogdanm	0:9b334a45a8ff	113	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115	uint32_t MSIClockRange; /*!< The MSI frequency range.
bogdanm	0:9b334a45a8ff	116	This parameter can be a value of @ref RCC_MSI_Clock_Range */
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120	}RCC_OscInitTypeDef;
bogdanm	0:9b334a45a8ff	121
bogdanm	0:9b334a45a8ff	122	/**
bogdanm	0:9b334a45a8ff	123	* @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm	0:9b334a45a8ff	124	*/
bogdanm	0:9b334a45a8ff	125	typedef struct
bogdanm	0:9b334a45a8ff	126	{
bogdanm	0:9b334a45a8ff	127	uint32_t ClockType; /*!< The clock to be configured.
bogdanm	0:9b334a45a8ff	128	This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm	0:9b334a45a8ff	129
bogdanm	0:9b334a45a8ff	130	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm	0:9b334a45a8ff	131	This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm	0:9b334a45a8ff	134	This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm	0:9b334a45a8ff	135
bogdanm	0:9b334a45a8ff	136	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	0:9b334a45a8ff	137	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	0:9b334a45a8ff	138
bogdanm	0:9b334a45a8ff	139	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	0:9b334a45a8ff	140	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	}RCC_ClkInitTypeDef;
bogdanm	0:9b334a45a8ff	143
mbed_official	113:b3775bf36a83	144	/**
mbed_official	113:b3775bf36a83	145	* @}
mbed_official	113:b3775bf36a83	146	*/
mbed_official	113:b3775bf36a83	147
mbed_official	113:b3775bf36a83	148	/* Private constants --------------------------------------------------------*/
mbed_official	113:b3775bf36a83	149	/** @addtogroup RCC_Private
bogdanm	0:9b334a45a8ff	150	* @brief RCC registers bit address in the alias region
bogdanm	0:9b334a45a8ff	151	* @{
bogdanm	0:9b334a45a8ff	152	*/
bogdanm	0:9b334a45a8ff	153	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm	0:9b334a45a8ff	154	/* --- CR Register ---*/
bogdanm	0:9b334a45a8ff	155	/* Alias word address of HSION bit */
bogdanm	0:9b334a45a8ff	156	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm	0:9b334a45a8ff	157	/* --- CFGR Register ---*/
bogdanm	0:9b334a45a8ff	158	/* Alias word address of I2SSRC bit */
bogdanm	0:9b334a45a8ff	159	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
bogdanm	0:9b334a45a8ff	160	/* --- CSR Register ---*/
bogdanm	0:9b334a45a8ff	161	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
bogdanm	0:9b334a45a8ff	162
bogdanm	0:9b334a45a8ff	163	/* CR register byte 3 (Bits[23:16]) base address */
bogdanm	0:9b334a45a8ff	164	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
bogdanm	0:9b334a45a8ff	165
bogdanm	0:9b334a45a8ff	166	/* CIER register byte 0 (Bits[0:8]) base address */
bogdanm	0:9b334a45a8ff	167	#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	/**
bogdanm	0:9b334a45a8ff	170	* @}
bogdanm	0:9b334a45a8ff	171	*/
mbed_official	113:b3775bf36a83	172
mbed_official	113:b3775bf36a83	173	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	174	/** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm	0:9b334a45a8ff	175	* @{
bogdanm	0:9b334a45a8ff	176	*/
bogdanm	0:9b334a45a8ff	177
mbed_official	113:b3775bf36a83	178	/** @defgroup RCC_Timeout_Value Timeout Values
bogdanm	0:9b334a45a8ff	179	* @{
bogdanm	0:9b334a45a8ff	180	*/
mbed_official	113:b3775bf36a83	181	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	113:b3775bf36a83	182	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
mbed_official	113:b3775bf36a83	183	#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
mbed_official	113:b3775bf36a83	184	/**
mbed_official	113:b3775bf36a83	185	* @}
mbed_official	113:b3775bf36a83	186	*/
mbed_official	113:b3775bf36a83	187
mbed_official	113:b3775bf36a83	188	/** @defgroup RCC_Oscillator_Type Oscillator Type
mbed_official	113:b3775bf36a83	189	* @{
mbed_official	113:b3775bf36a83	190	*/
mbed_official	113:b3775bf36a83	191	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) /!< Oscillator configuration unchanged /
mbed_official	113:b3775bf36a83	192	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) /!< HSE to configure /
mbed_official	113:b3775bf36a83	193	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) /!< HSI to configure /
mbed_official	113:b3775bf36a83	194	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) /!< LSE to configure /
mbed_official	113:b3775bf36a83	195	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) /!< LSI to configure /
mbed_official	113:b3775bf36a83	196	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) /!< MSI to configure /
bogdanm	0:9b334a45a8ff	197	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	198	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	199	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	/**
bogdanm	0:9b334a45a8ff	202	* @}
bogdanm	0:9b334a45a8ff	203	*/
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205	/** @defgroup RCC_HSE_Config RCC HSE Config
bogdanm	0:9b334a45a8ff	206	* @{
bogdanm	0:9b334a45a8ff	207	*/
bogdanm	0:9b334a45a8ff	208	#define RCC_HSE_OFF ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	209	#define RCC_HSE_ON RCC_CR_HSEON
bogdanm	0:9b334a45a8ff	210	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	/**
bogdanm	0:9b334a45a8ff	213	* @}
bogdanm	0:9b334a45a8ff	214	*/
bogdanm	0:9b334a45a8ff	215
bogdanm	0:9b334a45a8ff	216	/** @defgroup RCC_LSE_Config RCC LSE Config
bogdanm	0:9b334a45a8ff	217	* @{
bogdanm	0:9b334a45a8ff	218	*/
bogdanm	0:9b334a45a8ff	219	#define RCC_LSE_OFF ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	220	#define RCC_LSE_ON RCC_CSR_LSEON
bogdanm	0:9b334a45a8ff	221	#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP \| RCC_CSR_LSEON))
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	/**
bogdanm	0:9b334a45a8ff	224	* @}
bogdanm	0:9b334a45a8ff	225	*/
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	/** @defgroup RCC_LSI_Config RCC LSI Config
bogdanm	0:9b334a45a8ff	230	* @{
bogdanm	0:9b334a45a8ff	231	*/
bogdanm	0:9b334a45a8ff	232	#define RCC_LSI_OFF ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	233	#define RCC_LSI_ON ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	/**
bogdanm	0:9b334a45a8ff	238	* @}
bogdanm	0:9b334a45a8ff	239	*/
bogdanm	0:9b334a45a8ff	240
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	/** @defgroup RCC_MSI_Config RCC MSI Config
bogdanm	0:9b334a45a8ff	243	* @{
bogdanm	0:9b334a45a8ff	244	*/
bogdanm	0:9b334a45a8ff	245	#define RCC_MSI_OFF ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	246	#define RCC_MSI_ON ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	/**
bogdanm	0:9b334a45a8ff	251	* @}
bogdanm	0:9b334a45a8ff	252	*/
bogdanm	0:9b334a45a8ff	253
bogdanm	0:9b334a45a8ff	254	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	255	/** @defgroup RCC_HSI48_Config RCC HSI48 Configuration
bogdanm	0:9b334a45a8ff	256	* @{
bogdanm	0:9b334a45a8ff	257	*/
bogdanm	0:9b334a45a8ff	258	#define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	259	#define RCC_HSI48_ON ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	/**
bogdanm	0:9b334a45a8ff	262	* @}
bogdanm	0:9b334a45a8ff	263	*/
bogdanm	0:9b334a45a8ff	264	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm	0:9b334a45a8ff	265
bogdanm	0:9b334a45a8ff	266	/** @defgroup RCC_PLL_Config RCC PLL Config
bogdanm	0:9b334a45a8ff	267	* @{
bogdanm	0:9b334a45a8ff	268	*/
bogdanm	0:9b334a45a8ff	269	#define RCC_PLL_NONE ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	270	#define RCC_PLL_OFF ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	271	#define RCC_PLL_ON ((uint8_t)0x02)
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/**
bogdanm	0:9b334a45a8ff	274	* @}
bogdanm	0:9b334a45a8ff	275	*/
bogdanm	0:9b334a45a8ff	276
mbed_official	113:b3775bf36a83	277	/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
bogdanm	0:9b334a45a8ff	278	* @{
bogdanm	0:9b334a45a8ff	279	*/
bogdanm	0:9b334a45a8ff	280	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
bogdanm	0:9b334a45a8ff	281	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
bogdanm	0:9b334a45a8ff	282
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/**
bogdanm	0:9b334a45a8ff	285	* @}
bogdanm	0:9b334a45a8ff	286	*/
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	/** @defgroup RCC_PLLMultiplication_Factor RCC PLL Multipliers
bogdanm	0:9b334a45a8ff	289	* @{
bogdanm	0:9b334a45a8ff	290	*/
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	#define RCC_PLLMUL_3 RCC_CFGR_PLLMUL3
bogdanm	0:9b334a45a8ff	293	#define RCC_PLLMUL_4 RCC_CFGR_PLLMUL4
bogdanm	0:9b334a45a8ff	294	#define RCC_PLLMUL_6 RCC_CFGR_PLLMUL6
bogdanm	0:9b334a45a8ff	295	#define RCC_PLLMUL_8 RCC_CFGR_PLLMUL8
bogdanm	0:9b334a45a8ff	296	#define RCC_PLLMUL_12 RCC_CFGR_PLLMUL12
bogdanm	0:9b334a45a8ff	297	#define RCC_PLLMUL_16 RCC_CFGR_PLLMUL16
bogdanm	0:9b334a45a8ff	298	#define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
bogdanm	0:9b334a45a8ff	299	#define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
bogdanm	0:9b334a45a8ff	300	#define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
mbed_official	113:b3775bf36a83	301
bogdanm	0:9b334a45a8ff	302	/**
bogdanm	0:9b334a45a8ff	303	* @}
bogdanm	0:9b334a45a8ff	304	*/
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/** @defgroup RCC_PLLDivider_Factor RCC PLL Dividers
bogdanm	0:9b334a45a8ff	307	* @{
bogdanm	0:9b334a45a8ff	308	*/
bogdanm	0:9b334a45a8ff	309
bogdanm	0:9b334a45a8ff	310	#define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
bogdanm	0:9b334a45a8ff	311	#define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
bogdanm	0:9b334a45a8ff	312	#define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
mbed_official	113:b3775bf36a83	313
mbed_official	113:b3775bf36a83	314	/**
mbed_official	113:b3775bf36a83	315	* @}
mbed_official	113:b3775bf36a83	316	*/
mbed_official	113:b3775bf36a83	317
mbed_official	113:b3775bf36a83	318	/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
mbed_official	113:b3775bf36a83	319	* @{
mbed_official	113:b3775bf36a83	320	*/
mbed_official	113:b3775bf36a83	321
mbed_official	113:b3775bf36a83	322	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
mbed_official	113:b3775bf36a83	323	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
mbed_official	113:b3775bf36a83	324	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
mbed_official	113:b3775bf36a83	325	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
mbed_official	113:b3775bf36a83	326	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
mbed_official	113:b3775bf36a83	327	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
mbed_official	113:b3775bf36a83	328	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
mbed_official	113:b3775bf36a83	329
mbed_official	113:b3775bf36a83	330
bogdanm	0:9b334a45a8ff	331	/**
bogdanm	0:9b334a45a8ff	332	* @}
bogdanm	0:9b334a45a8ff	333	*/
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
bogdanm	0:9b334a45a8ff	336	* @{
bogdanm	0:9b334a45a8ff	337	*/
mbed_official	113:b3775bf36a83	338	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
mbed_official	113:b3775bf36a83	339	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
mbed_official	113:b3775bf36a83	340	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
mbed_official	113:b3775bf36a83	341	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
bogdanm	0:9b334a45a8ff	342	/**
bogdanm	0:9b334a45a8ff	343	* @}
bogdanm	0:9b334a45a8ff	344	*/
mbed_official	113:b3775bf36a83	345
bogdanm	0:9b334a45a8ff	346	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
bogdanm	0:9b334a45a8ff	347	* @{
bogdanm	0:9b334a45a8ff	348	*/
mbed_official	113:b3775bf36a83	349	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
mbed_official	113:b3775bf36a83	350	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
mbed_official	113:b3775bf36a83	351	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
mbed_official	113:b3775bf36a83	352	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selection as system clock /
bogdanm	0:9b334a45a8ff	353	/**
bogdanm	0:9b334a45a8ff	354	* @}
bogdanm	0:9b334a45a8ff	355	*/
bogdanm	0:9b334a45a8ff	356
mbed_official	113:b3775bf36a83	357	/** @defgroup RCC_System_Clock_SOURCE_Status RCC System Clock Source Status
mbed_official	113:b3775bf36a83	358	* @{
mbed_official	113:b3775bf36a83	359	*/
mbed_official	113:b3775bf36a83	360	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
mbed_official	113:b3775bf36a83	361	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
mbed_official	113:b3775bf36a83	362	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
mbed_official	113:b3775bf36a83	363	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
mbed_official	113:b3775bf36a83	364	/**
mbed_official	113:b3775bf36a83	365	* @}
mbed_official	113:b3775bf36a83	366	*/
mbed_official	113:b3775bf36a83	367
mbed_official	113:b3775bf36a83	368	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
bogdanm	0:9b334a45a8ff	369	* @{
bogdanm	0:9b334a45a8ff	370	*/
mbed_official	113:b3775bf36a83	371	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
mbed_official	113:b3775bf36a83	372	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
mbed_official	113:b3775bf36a83	373	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
mbed_official	113:b3775bf36a83	374	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
mbed_official	113:b3775bf36a83	375	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
mbed_official	113:b3775bf36a83	376	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
mbed_official	113:b3775bf36a83	377	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
mbed_official	113:b3775bf36a83	378	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
mbed_official	113:b3775bf36a83	379	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
bogdanm	0:9b334a45a8ff	380	/**
bogdanm	0:9b334a45a8ff	381	* @}
mbed_official	113:b3775bf36a83	382	*/
mbed_official	113:b3775bf36a83	383
mbed_official	113:b3775bf36a83	384	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
bogdanm	0:9b334a45a8ff	385	* @{
bogdanm	0:9b334a45a8ff	386	*/
mbed_official	113:b3775bf36a83	387	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
mbed_official	113:b3775bf36a83	388	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
mbed_official	113:b3775bf36a83	389	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
mbed_official	113:b3775bf36a83	390	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
mbed_official	113:b3775bf36a83	391	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
bogdanm	0:9b334a45a8ff	392	/**
bogdanm	0:9b334a45a8ff	393	* @}
mbed_official	113:b3775bf36a83	394	*/
bogdanm	0:9b334a45a8ff	395
bogdanm	0:9b334a45a8ff	396	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
bogdanm	0:9b334a45a8ff	397	* @{
bogdanm	0:9b334a45a8ff	398	*/
bogdanm	0:9b334a45a8ff	399	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	400	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
bogdanm	0:9b334a45a8ff	401	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
mbed_official	113:b3775bf36a83	402	#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE
mbed_official	113:b3775bf36a83	403
bogdanm	0:9b334a45a8ff	404	#define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
bogdanm	0:9b334a45a8ff	405	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_0)
bogdanm	0:9b334a45a8ff	406	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_1)
bogdanm	0:9b334a45a8ff	407	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE)
mbed_official	113:b3775bf36a83	408
mbed_official	113:b3775bf36a83	409	#define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /!< HSE is divided by 2 for RTC clock /
mbed_official	113:b3775bf36a83	410	#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /!< HSE is divided by 4 for RTC clock /
mbed_official	113:b3775bf36a83	411	#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /!< HSE is divided by 8 for RTC clock /
mbed_official	113:b3775bf36a83	412	#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /!< HSE is divided by 16 for RTC clock /
mbed_official	113:b3775bf36a83	413
bogdanm	0:9b334a45a8ff	414	/**
bogdanm	0:9b334a45a8ff	415	* @}
bogdanm	0:9b334a45a8ff	416	*/
bogdanm	0:9b334a45a8ff	417
mbed_official	113:b3775bf36a83	418	/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
bogdanm	0:9b334a45a8ff	419	* @{
bogdanm	0:9b334a45a8ff	420	*/
bogdanm	0:9b334a45a8ff	421
bogdanm	0:9b334a45a8ff	422	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
bogdanm	0:9b334a45a8ff	423	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
bogdanm	0:9b334a45a8ff	424	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
bogdanm	0:9b334a45a8ff	425	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
bogdanm	0:9b334a45a8ff	426	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
bogdanm	0:9b334a45a8ff	427	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
bogdanm	0:9b334a45a8ff	428	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
bogdanm	0:9b334a45a8ff	429	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
mbed_official	113:b3775bf36a83	430	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) \
mbed_official	113:b3775bf36a83	431	&& !defined (STM32L011xx) && !defined (STM32L021xx)
bogdanm	0:9b334a45a8ff	432	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
bogdanm	0:9b334a45a8ff	433	#endif
mbed_official	113:b3775bf36a83	434
bogdanm	0:9b334a45a8ff	435
bogdanm	0:9b334a45a8ff	436	/**
bogdanm	0:9b334a45a8ff	437	* @}
bogdanm	0:9b334a45a8ff	438	*/
bogdanm	0:9b334a45a8ff	439
bogdanm	0:9b334a45a8ff	440	/** @defgroup RCC_MCOPrescaler RCC MCO Prescaler
bogdanm	0:9b334a45a8ff	441	* @{
bogdanm	0:9b334a45a8ff	442	*/
bogdanm	0:9b334a45a8ff	443
bogdanm	0:9b334a45a8ff	444	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
bogdanm	0:9b334a45a8ff	445	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
bogdanm	0:9b334a45a8ff	446	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
bogdanm	0:9b334a45a8ff	447	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
bogdanm	0:9b334a45a8ff	448	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/**
bogdanm	0:9b334a45a8ff	451	* @}
bogdanm	0:9b334a45a8ff	452	*/
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/** @defgroup RCC_MCO_Index RCC MCO Index
bogdanm	0:9b334a45a8ff	455	* @{
bogdanm	0:9b334a45a8ff	456	*/
bogdanm	0:9b334a45a8ff	457	#define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	458	#define RCC_MCO2 ((uint32_t)0x00000001)
mbed_official	113:b3775bf36a83	459	#if defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	113:b3775bf36a83	460	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	113:b3775bf36a83	461	#define RCC_MCO3 ((uint32_t)0x00000002)
mbed_official	113:b3775bf36a83	462	#endif
bogdanm	0:9b334a45a8ff	463
bogdanm	0:9b334a45a8ff	464	/**
bogdanm	0:9b334a45a8ff	465	* @}
bogdanm	0:9b334a45a8ff	466	*/
bogdanm	0:9b334a45a8ff	467
bogdanm	0:9b334a45a8ff	468	/** @defgroup RCC_Interrupt RCC Interruptions
bogdanm	0:9b334a45a8ff	469	* @{
bogdanm	0:9b334a45a8ff	470	*/
bogdanm	0:9b334a45a8ff	471	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
bogdanm	0:9b334a45a8ff	472	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF
bogdanm	0:9b334a45a8ff	473	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
bogdanm	0:9b334a45a8ff	474	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF
bogdanm	0:9b334a45a8ff	475	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
bogdanm	0:9b334a45a8ff	476	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
bogdanm	0:9b334a45a8ff	477
mbed_official	113:b3775bf36a83	478	#define RCC_IT_CSSLSE RCC_CIFR_CSSLSEF
mbed_official	113:b3775bf36a83	479	#define RCC_IT_CSSHSE RCC_CIFR_CSSHSEF
bogdanm	0:9b334a45a8ff	480
mbed_official	113:b3775bf36a83	481	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	482	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
bogdanm	0:9b334a45a8ff	483	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm	0:9b334a45a8ff	484	/**
bogdanm	0:9b334a45a8ff	485	* @}
bogdanm	0:9b334a45a8ff	486	*/
bogdanm	0:9b334a45a8ff	487
mbed_official	113:b3775bf36a83	488	/** @defgroup RCC_Flag RCC Flag
bogdanm	0:9b334a45a8ff	489	* Elements values convention: 0XXYYYYYb
bogdanm	0:9b334a45a8ff	490	* - YYYYY : Flag position in the register
bogdanm	0:9b334a45a8ff	491	* - 0XX : Register index
bogdanm	0:9b334a45a8ff	492	* - 01: CR register
bogdanm	0:9b334a45a8ff	493	* - 10: CSR register
bogdanm	0:9b334a45a8ff	494	* - 11: CRRCR register
bogdanm	0:9b334a45a8ff	495	* @{
bogdanm	0:9b334a45a8ff	496	*/
bogdanm	0:9b334a45a8ff	497	/* Flags in the CR register */
bogdanm	0:9b334a45a8ff	498	#define RCC_FLAG_HSIRDY ((uint8_t)0x22)
bogdanm	0:9b334a45a8ff	499	#define RCC_FLAG_HSIDIV ((uint8_t)0x24)
bogdanm	0:9b334a45a8ff	500	#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
bogdanm	0:9b334a45a8ff	501	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
bogdanm	0:9b334a45a8ff	502	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
bogdanm	0:9b334a45a8ff	503
bogdanm	0:9b334a45a8ff	504	/* Flags in the CSR register */
bogdanm	0:9b334a45a8ff	505	#define RCC_FLAG_LSERDY ((uint8_t)0x49)
bogdanm	0:9b334a45a8ff	506	#define RCC_FLAG_LSECSS ((uint8_t)0x4E)
bogdanm	0:9b334a45a8ff	507	#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
bogdanm	0:9b334a45a8ff	508	#define RCC_FLAG_FWRST ((uint8_t)0x58)
bogdanm	0:9b334a45a8ff	509	#define RCC_FLAG_OBLRST ((uint8_t)0x59)
bogdanm	0:9b334a45a8ff	510	#define RCC_FLAG_PINRST ((uint8_t)0x5A)
bogdanm	0:9b334a45a8ff	511	#define RCC_FLAG_PORRST ((uint8_t)0x5B)
bogdanm	0:9b334a45a8ff	512	#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
bogdanm	0:9b334a45a8ff	513	#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
bogdanm	0:9b334a45a8ff	514	#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
bogdanm	0:9b334a45a8ff	515	#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	518	/* Flags in the CRRCR register */
bogdanm	0:9b334a45a8ff	519	#define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
bogdanm	0:9b334a45a8ff	520	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm	0:9b334a45a8ff	521
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	/**
bogdanm	0:9b334a45a8ff	524	* @}
bogdanm	0:9b334a45a8ff	525	*/
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	/**
bogdanm	0:9b334a45a8ff	528	* @}
bogdanm	0:9b334a45a8ff	529	*/
bogdanm	0:9b334a45a8ff	530	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	531	/** @defgroup RCC_Exported_Macros RCC Exported Macros
bogdanm	0:9b334a45a8ff	532	* @{
bogdanm	0:9b334a45a8ff	533	*/
mbed_official	113:b3775bf36a83	534
mbed_official	113:b3775bf36a83	535	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
mbed_official	113:b3775bf36a83	536	* @brief Enable or disable the AHB peripheral clock.
bogdanm	0:9b334a45a8ff	537	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	538	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	539	* using it.
mbed_official	113:b3775bf36a83	540	* @{
bogdanm	0:9b334a45a8ff	541	*/
bogdanm	0:9b334a45a8ff	542	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	543	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	544	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
bogdanm	0:9b334a45a8ff	545	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	546	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
bogdanm	0:9b334a45a8ff	547	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	548	} while(0)
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	#define __HAL_RCC_MIF_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	551	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	552	SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
bogdanm	0:9b334a45a8ff	553	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	554	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
bogdanm	0:9b334a45a8ff	555	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	556	} while(0)
bogdanm	0:9b334a45a8ff	557
bogdanm	0:9b334a45a8ff	558	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	559	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	560	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
bogdanm	0:9b334a45a8ff	561	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	562	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
bogdanm	0:9b334a45a8ff	563	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	564	} while(0)
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566
mbed_official	113:b3775bf36a83	567	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
mbed_official	113:b3775bf36a83	568	#define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
mbed_official	113:b3775bf36a83	569	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
bogdanm	0:9b334a45a8ff	570
mbed_official	113:b3775bf36a83	571	/**
mbed_official	113:b3775bf36a83	572	* @}
mbed_official	113:b3775bf36a83	573	*/
bogdanm	0:9b334a45a8ff	574
mbed_official	113:b3775bf36a83	575	/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
mbed_official	113:b3775bf36a83	576	* @brief Enable or disable the IOPORT peripheral clock.
bogdanm	0:9b334a45a8ff	577	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	578	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	579	* using it.
mbed_official	113:b3775bf36a83	580	* @{
bogdanm	0:9b334a45a8ff	581	*/
bogdanm	0:9b334a45a8ff	582	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	583	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	584	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
bogdanm	0:9b334a45a8ff	585	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	586	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
bogdanm	0:9b334a45a8ff	587	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	588	} while(0)
bogdanm	0:9b334a45a8ff	589
bogdanm	0:9b334a45a8ff	590	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	591	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	592	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
bogdanm	0:9b334a45a8ff	593	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	594	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
bogdanm	0:9b334a45a8ff	595	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	596	} while(0)
bogdanm	0:9b334a45a8ff	597
bogdanm	0:9b334a45a8ff	598	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	599	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	600	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
bogdanm	0:9b334a45a8ff	601	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	602	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
bogdanm	0:9b334a45a8ff	603	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	604	} while(0)
bogdanm	0:9b334a45a8ff	605
bogdanm	0:9b334a45a8ff	606	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	607	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	608	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
bogdanm	0:9b334a45a8ff	609	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	610	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
bogdanm	0:9b334a45a8ff	611	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	612	} while(0)
bogdanm	0:9b334a45a8ff	613
bogdanm	0:9b334a45a8ff	614
mbed_official	113:b3775bf36a83	615	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
mbed_official	113:b3775bf36a83	616	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
mbed_official	113:b3775bf36a83	617	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
mbed_official	113:b3775bf36a83	618	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN)
bogdanm	0:9b334a45a8ff	619
mbed_official	113:b3775bf36a83	620	/**
mbed_official	113:b3775bf36a83	621	* @}
mbed_official	113:b3775bf36a83	622	*/
bogdanm	0:9b334a45a8ff	623
mbed_official	113:b3775bf36a83	624	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
mbed_official	113:b3775bf36a83	625	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	0:9b334a45a8ff	626	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	627	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	628	* using it.
mbed_official	113:b3775bf36a83	629	* @{
bogdanm	0:9b334a45a8ff	630	*/
mbed_official	113:b3775bf36a83	631	#define __HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
mbed_official	113:b3775bf36a83	632	#define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
bogdanm	0:9b334a45a8ff	633
mbed_official	113:b3775bf36a83	634	#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
mbed_official	113:b3775bf36a83	635	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
mbed_official	113:b3775bf36a83	636	/**
mbed_official	113:b3775bf36a83	637	* @}
mbed_official	113:b3775bf36a83	638	*/
bogdanm	0:9b334a45a8ff	639
mbed_official	113:b3775bf36a83	640	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
mbed_official	113:b3775bf36a83	641	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	0:9b334a45a8ff	642	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	643	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	644	* using it.
mbed_official	113:b3775bf36a83	645	* @{
bogdanm	0:9b334a45a8ff	646	*/
mbed_official	113:b3775bf36a83	647	#define __HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
mbed_official	113:b3775bf36a83	648	#define __HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
mbed_official	113:b3775bf36a83	649
mbed_official	113:b3775bf36a83	650	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
mbed_official	113:b3775bf36a83	651	#define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
mbed_official	113:b3775bf36a83	652	/**
mbed_official	113:b3775bf36a83	653	* @}
mbed_official	113:b3775bf36a83	654	*/
mbed_official	113:b3775bf36a83	655
mbed_official	113:b3775bf36a83	656	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status
mbed_official	113:b3775bf36a83	657	* @brief Check whether the AHB peripheral clock is enabled or not.
mbed_official	113:b3775bf36a83	658	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	113:b3775bf36a83	659	* is disabled and the application software has to enable this clock before
mbed_official	113:b3775bf36a83	660	* using it.
mbed_official	113:b3775bf36a83	661	* @{
mbed_official	113:b3775bf36a83	662	*/
mbed_official	113:b3775bf36a83	663
mbed_official	113:b3775bf36a83	664	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
mbed_official	113:b3775bf36a83	665	#define __HAL_RCC_MIF_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != RESET)
mbed_official	113:b3775bf36a83	666	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
mbed_official	113:b3775bf36a83	667
mbed_official	113:b3775bf36a83	668	/**
mbed_official	113:b3775bf36a83	669	* @}
mbed_official	113:b3775bf36a83	670	*/
mbed_official	113:b3775bf36a83	671
mbed_official	113:b3775bf36a83	672	/** @defgroup RCC_IOPORT_Peripheral_Clock_Enable_Disable_Status IOPORT Peripheral Clock Enabled or Disabled Status
mbed_official	113:b3775bf36a83	673	* @brief Check whether the IOPORT peripheral clock is enabled or not.
mbed_official	113:b3775bf36a83	674	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	113:b3775bf36a83	675	* is disabled and the application software has to enable this clock before
mbed_official	113:b3775bf36a83	676	* using it.
mbed_official	113:b3775bf36a83	677	* @{
mbed_official	113:b3775bf36a83	678	*/
bogdanm	0:9b334a45a8ff	679
mbed_official	113:b3775bf36a83	680	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
mbed_official	113:b3775bf36a83	681	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
mbed_official	113:b3775bf36a83	682	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
mbed_official	113:b3775bf36a83	683	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != RESET)
mbed_official	113:b3775bf36a83	684
mbed_official	113:b3775bf36a83	685	/**
mbed_official	113:b3775bf36a83	686	* @}
mbed_official	113:b3775bf36a83	687	*/
mbed_official	113:b3775bf36a83	688
mbed_official	113:b3775bf36a83	689	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
mbed_official	113:b3775bf36a83	690	* @brief Check whether the APB1 peripheral clock is enabled or not.
mbed_official	113:b3775bf36a83	691	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	113:b3775bf36a83	692	* is disabled and the application software has to enable this clock before
mbed_official	113:b3775bf36a83	693	* using it.
mbed_official	113:b3775bf36a83	694	* @{
mbed_official	113:b3775bf36a83	695	*/
mbed_official	113:b3775bf36a83	696	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != RESET)
mbed_official	113:b3775bf36a83	697	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != RESET)
bogdanm	0:9b334a45a8ff	698
mbed_official	113:b3775bf36a83	699	/**
mbed_official	113:b3775bf36a83	700	* @}
mbed_official	113:b3775bf36a83	701	*/
mbed_official	113:b3775bf36a83	702
mbed_official	113:b3775bf36a83	703	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
mbed_official	113:b3775bf36a83	704	* @brief Check whether the APB2 peripheral clock is enabled or not.
mbed_official	113:b3775bf36a83	705	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	113:b3775bf36a83	706	* is disabled and the application software has to enable this clock before
mbed_official	113:b3775bf36a83	707	* using it.
mbed_official	113:b3775bf36a83	708	* @{
mbed_official	113:b3775bf36a83	709	*/
mbed_official	113:b3775bf36a83	710	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
mbed_official	113:b3775bf36a83	711	#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != RESET)
mbed_official	113:b3775bf36a83	712
mbed_official	113:b3775bf36a83	713	/**
mbed_official	113:b3775bf36a83	714	* @}
mbed_official	113:b3775bf36a83	715	*/
mbed_official	113:b3775bf36a83	716
mbed_official	113:b3775bf36a83	717	/** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
mbed_official	113:b3775bf36a83	718	* @brief Force or release AHB peripheral reset.
mbed_official	113:b3775bf36a83	719	* @{
bogdanm	0:9b334a45a8ff	720	*/
bogdanm	0:9b334a45a8ff	721	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
mbed_official	113:b3775bf36a83	722	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
mbed_official	113:b3775bf36a83	723	#define __HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
mbed_official	113:b3775bf36a83	724	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
bogdanm	0:9b334a45a8ff	725
bogdanm	0:9b334a45a8ff	726	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
mbed_official	113:b3775bf36a83	727	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
mbed_official	113:b3775bf36a83	728	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
mbed_official	113:b3775bf36a83	729	#define __HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
mbed_official	113:b3775bf36a83	730	/**
mbed_official	113:b3775bf36a83	731	* @}
mbed_official	113:b3775bf36a83	732	*/
mbed_official	113:b3775bf36a83	733
mbed_official	113:b3775bf36a83	734	/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
mbed_official	113:b3775bf36a83	735	* @brief Force or release IOPORT peripheral reset.
mbed_official	113:b3775bf36a83	736	* @{
bogdanm	0:9b334a45a8ff	737	*/
bogdanm	0:9b334a45a8ff	738	#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
mbed_official	113:b3775bf36a83	739	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
mbed_official	113:b3775bf36a83	740	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
mbed_official	113:b3775bf36a83	741	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
mbed_official	113:b3775bf36a83	742	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
mbed_official	113:b3775bf36a83	745	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
mbed_official	113:b3775bf36a83	746	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
mbed_official	113:b3775bf36a83	747	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
mbed_official	113:b3775bf36a83	748	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
bogdanm	0:9b334a45a8ff	749
mbed_official	113:b3775bf36a83	750	/**
mbed_official	113:b3775bf36a83	751	* @}
mbed_official	113:b3775bf36a83	752	*/
mbed_official	113:b3775bf36a83	753
mbed_official	113:b3775bf36a83	754	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
mbed_official	113:b3775bf36a83	755	* @brief Force or release APB1 peripheral reset.
mbed_official	113:b3775bf36a83	756	* @{
bogdanm	0:9b334a45a8ff	757	*/
bogdanm	0:9b334a45a8ff	758	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
mbed_official	113:b3775bf36a83	759	#define __HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
mbed_official	113:b3775bf36a83	760	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official	113:b3775bf36a83	763	#define __HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
mbed_official	113:b3775bf36a83	764	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
bogdanm	0:9b334a45a8ff	765
mbed_official	113:b3775bf36a83	766	/**
mbed_official	113:b3775bf36a83	767	* @}
mbed_official	113:b3775bf36a83	768	*/
mbed_official	113:b3775bf36a83	769
mbed_official	113:b3775bf36a83	770	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
mbed_official	113:b3775bf36a83	771	* @brief Force or release APB2 peripheral reset.
mbed_official	113:b3775bf36a83	772	* @{
bogdanm	0:9b334a45a8ff	773	*/
bogdanm	0:9b334a45a8ff	774	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	113:b3775bf36a83	775	#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
mbed_official	113:b3775bf36a83	776	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
bogdanm	0:9b334a45a8ff	777
bogdanm	0:9b334a45a8ff	778	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official	113:b3775bf36a83	779	#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
mbed_official	113:b3775bf36a83	780	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
mbed_official	113:b3775bf36a83	781	/**
mbed_official	113:b3775bf36a83	782	* @}
mbed_official	113:b3775bf36a83	783	*/
mbed_official	113:b3775bf36a83	784
bogdanm	0:9b334a45a8ff	785
mbed_official	113:b3775bf36a83	786	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
mbed_official	113:b3775bf36a83	787	* @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	788	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	789	* power consumption.
bogdanm	0:9b334a45a8ff	790	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	791	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	792	* @{
bogdanm	0:9b334a45a8ff	793	*/
mbed_official	113:b3775bf36a83	794	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
mbed_official	113:b3775bf36a83	795	#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
mbed_official	113:b3775bf36a83	796	#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
mbed_official	113:b3775bf36a83	797	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
mbed_official	113:b3775bf36a83	798
mbed_official	113:b3775bf36a83	799	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
mbed_official	113:b3775bf36a83	800	#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
mbed_official	113:b3775bf36a83	801	#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
mbed_official	113:b3775bf36a83	802	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
mbed_official	113:b3775bf36a83	803	/**
mbed_official	113:b3775bf36a83	804	* @}
mbed_official	113:b3775bf36a83	805	*/
mbed_official	113:b3775bf36a83	806
mbed_official	113:b3775bf36a83	807	/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
mbed_official	113:b3775bf36a83	808	* @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
mbed_official	113:b3775bf36a83	809	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	113:b3775bf36a83	810	* power consumption.
mbed_official	113:b3775bf36a83	811	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	113:b3775bf36a83	812	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	813	* @{
mbed_official	113:b3775bf36a83	814	*/
mbed_official	113:b3775bf36a83	815
mbed_official	113:b3775bf36a83	816	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
mbed_official	113:b3775bf36a83	817	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
mbed_official	113:b3775bf36a83	818	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
mbed_official	113:b3775bf36a83	819	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
bogdanm	0:9b334a45a8ff	820
mbed_official	113:b3775bf36a83	821	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
mbed_official	113:b3775bf36a83	822	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
mbed_official	113:b3775bf36a83	823	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
mbed_official	113:b3775bf36a83	824	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
mbed_official	113:b3775bf36a83	825	/**
mbed_official	113:b3775bf36a83	826	* @}
mbed_official	113:b3775bf36a83	827	*/
mbed_official	113:b3775bf36a83	828
mbed_official	113:b3775bf36a83	829	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
mbed_official	113:b3775bf36a83	830	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	113:b3775bf36a83	831	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	113:b3775bf36a83	832	* power consumption.
mbed_official	113:b3775bf36a83	833	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	113:b3775bf36a83	834	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	835	* @{
mbed_official	113:b3775bf36a83	836	*/
mbed_official	113:b3775bf36a83	837	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
mbed_official	113:b3775bf36a83	838	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
bogdanm	0:9b334a45a8ff	839
mbed_official	113:b3775bf36a83	840	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
mbed_official	113:b3775bf36a83	841	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
mbed_official	113:b3775bf36a83	842
mbed_official	113:b3775bf36a83	843	/**
mbed_official	113:b3775bf36a83	844	* @}
mbed_official	113:b3775bf36a83	845	*/
mbed_official	113:b3775bf36a83	846
mbed_official	113:b3775bf36a83	847	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
mbed_official	113:b3775bf36a83	848	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	849	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	850	* power consumption.
bogdanm	0:9b334a45a8ff	851	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	852	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	853	* @{
mbed_official	113:b3775bf36a83	854	*/
mbed_official	113:b3775bf36a83	855	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
mbed_official	113:b3775bf36a83	856	#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
mbed_official	113:b3775bf36a83	857
mbed_official	113:b3775bf36a83	858	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
mbed_official	113:b3775bf36a83	859	#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
mbed_official	113:b3775bf36a83	860
mbed_official	113:b3775bf36a83	861	/**
mbed_official	113:b3775bf36a83	862	* @}
mbed_official	113:b3775bf36a83	863	*/
mbed_official	113:b3775bf36a83	864
mbed_official	113:b3775bf36a83	865	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enabled or Disabled Status
mbed_official	113:b3775bf36a83	866	* @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.
mbed_official	113:b3775bf36a83	867	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	113:b3775bf36a83	868	* power consumption.
mbed_official	113:b3775bf36a83	869	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	113:b3775bf36a83	870	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	871	* @{
mbed_official	113:b3775bf36a83	872	*/
mbed_official	113:b3775bf36a83	873	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET)
mbed_official	113:b3775bf36a83	874	#define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != RESET)
mbed_official	113:b3775bf36a83	875	#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)
mbed_official	113:b3775bf36a83	876	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)
mbed_official	113:b3775bf36a83	877
mbed_official	113:b3775bf36a83	878	/**
mbed_official	113:b3775bf36a83	879	* @}
mbed_official	113:b3775bf36a83	880	*/
mbed_official	113:b3775bf36a83	881
mbed_official	113:b3775bf36a83	882	/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable_Status IOPORT Peripheral Clock Sleep Enabled or Disabled Status
mbed_official	113:b3775bf36a83	883	* @brief Check whether the IOPORT peripheral clock during Low Power (Sleep) mode is enabled or not.
mbed_official	113:b3775bf36a83	884	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	113:b3775bf36a83	885	* power consumption.
mbed_official	113:b3775bf36a83	886	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	113:b3775bf36a83	887	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	888	* @{
mbed_official	113:b3775bf36a83	889	*/
mbed_official	113:b3775bf36a83	890	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != RESET)
mbed_official	113:b3775bf36a83	891	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != RESET)
mbed_official	113:b3775bf36a83	892	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != RESET)
mbed_official	113:b3775bf36a83	893	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != RESET)
mbed_official	113:b3775bf36a83	894
mbed_official	113:b3775bf36a83	895	/**
mbed_official	113:b3775bf36a83	896	* @}
bogdanm	0:9b334a45a8ff	897	*/
bogdanm	0:9b334a45a8ff	898
mbed_official	113:b3775bf36a83	899	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
mbed_official	113:b3775bf36a83	900	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
mbed_official	113:b3775bf36a83	901	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	113:b3775bf36a83	902	* power consumption.
mbed_official	113:b3775bf36a83	903	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	113:b3775bf36a83	904	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	905	* @{
mbed_official	113:b3775bf36a83	906	*/
mbed_official	113:b3775bf36a83	907	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != RESET)
mbed_official	113:b3775bf36a83	908	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != RESET)
bogdanm	0:9b334a45a8ff	909
mbed_official	113:b3775bf36a83	910	/**
mbed_official	113:b3775bf36a83	911	* @}
mbed_official	113:b3775bf36a83	912	*/
mbed_official	113:b3775bf36a83	913
mbed_official	113:b3775bf36a83	914	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
mbed_official	113:b3775bf36a83	915	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
bogdanm	0:9b334a45a8ff	916	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	917	* power consumption.
bogdanm	0:9b334a45a8ff	918	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	113:b3775bf36a83	919	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	920	* @{
mbed_official	113:b3775bf36a83	921	*/
mbed_official	113:b3775bf36a83	922	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
mbed_official	113:b3775bf36a83	923	#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != RESET)
mbed_official	113:b3775bf36a83	924
mbed_official	113:b3775bf36a83	925	/**
mbed_official	113:b3775bf36a83	926	* @}
bogdanm	0:9b334a45a8ff	927	*/
mbed_official	113:b3775bf36a83	928
mbed_official	113:b3775bf36a83	929	/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
mbed_official	113:b3775bf36a83	930	* @{
mbed_official	113:b3775bf36a83	931	*/
mbed_official	113:b3775bf36a83	932
mbed_official	113:b3775bf36a83	933	/** @brief Macros to force or release the Backup domain reset.
mbed_official	113:b3775bf36a83	934	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	113:b3775bf36a83	935	* and the RTC clock source selection in RCC_CSR register.
mbed_official	113:b3775bf36a83	936	* @note The BKPSRAM is not affected by this reset.
mbed_official	113:b3775bf36a83	937	*/
mbed_official	113:b3775bf36a83	938	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
mbed_official	113:b3775bf36a83	939	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
bogdanm	0:9b334a45a8ff	940
mbed_official	113:b3775bf36a83	941	/**
mbed_official	113:b3775bf36a83	942	* @}
mbed_official	113:b3775bf36a83	943	*/
bogdanm	0:9b334a45a8ff	944
mbed_official	113:b3775bf36a83	945	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
mbed_official	113:b3775bf36a83	946	* @{
mbed_official	113:b3775bf36a83	947	*/
mbed_official	113:b3775bf36a83	948
mbed_official	113:b3775bf36a83	949	/** @brief Macros to enable or disable the the RTC clock.
mbed_official	113:b3775bf36a83	950	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	113:b3775bf36a83	951	*/
mbed_official	113:b3775bf36a83	952	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
mbed_official	113:b3775bf36a83	953	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
mbed_official	113:b3775bf36a83	954
mbed_official	113:b3775bf36a83	955	/**
mbed_official	113:b3775bf36a83	956	* @}
bogdanm	0:9b334a45a8ff	957	*/
mbed_official	113:b3775bf36a83	958
mbed_official	113:b3775bf36a83	959	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	113:b3775bf36a83	960	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	113:b3775bf36a83	961	* It is used (enabled by hardware) as system clock source after startup
mbed_official	113:b3775bf36a83	962	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
mbed_official	113:b3775bf36a83	963	* of the HSE used directly or indirectly as system clock (if the Clock
mbed_official	113:b3775bf36a83	964	* Security System CSS is enabled).
mbed_official	113:b3775bf36a83	965	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	113:b3775bf36a83	966	* you have to select another source of the system clock then stop the HSI.
mbed_official	113:b3775bf36a83	967	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	113:b3775bf36a83	968	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	113:b3775bf36a83	969	* system clock source.
mbed_official	113:b3775bf36a83	970	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	113:b3775bf36a83	971	* clock cycles.
mbed_official	113:b3775bf36a83	972	*/
mbed_official	113:b3775bf36a83	973	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	113:b3775bf36a83	974	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	975
mbed_official	113:b3775bf36a83	976	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	113:b3775bf36a83	977	* @note The calibration is used to compensate for the variations in voltage
mbed_official	113:b3775bf36a83	978	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	113:b3775bf36a83	979	* @param __HSICalibrationValue__: specifies the calibration trimming value.
mbed_official	113:b3775bf36a83	980	* This parameter must be a number between 0 and 0x1F.
mbed_official	113:b3775bf36a83	981	*/
mbed_official	113:b3775bf36a83	982	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
mbed_official	113:b3775bf36a83	983	RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
mbed_official	113:b3775bf36a83	984
bogdanm	0:9b334a45a8ff	985	/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	0:9b334a45a8ff	986	* @note After enabling the HSI, the application software should wait on
bogdanm	0:9b334a45a8ff	987	* HSIRDY flag to be set indicating that HSI clock is stable and can
bogdanm	0:9b334a45a8ff	988	* be used to clock the PLL and/or system clock.
bogdanm	0:9b334a45a8ff	989	* @note HSI can not be stopped if it is used directly or through the PLL
bogdanm	0:9b334a45a8ff	990	* as system clock. In this case, you have to select another source
bogdanm	0:9b334a45a8ff	991	* of the system clock then stop the HSI.
bogdanm	0:9b334a45a8ff	992	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	993	* @param __STATE__: specifies the new state of the HSI.
bogdanm	0:9b334a45a8ff	994	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	995	* @arg RCC_HSI_OFF: turn OFF the HSI oscillator
bogdanm	0:9b334a45a8ff	996	* @arg RCC_HSI_ON: turn ON the HSI oscillator
bogdanm	0:9b334a45a8ff	997	* @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
bogdanm	0:9b334a45a8ff	998	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm	0:9b334a45a8ff	999	* clock cycles.
bogdanm	0:9b334a45a8ff	1000	*/
bogdanm	0:9b334a45a8ff	1001	#define __HAL_RCC_HSI_CONFIG(__STATE__) \
mbed_official	113:b3775bf36a83	1002	MODIFY_REG(RCC->CR, RCC_CR_HSION \| RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
mbed_official	113:b3775bf36a83	1003
bogdanm	0:9b334a45a8ff	1004	/**
bogdanm	0:9b334a45a8ff	1005	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
bogdanm	0:9b334a45a8ff	1006	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1007	* It is used (enabled by hardware) as system clock source after
bogdanm	0:9b334a45a8ff	1008	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
bogdanm	0:9b334a45a8ff	1009	* of failure of the HSE used directly or indirectly as system clock
bogdanm	0:9b334a45a8ff	1010	* (if the Clock Security System CSS is enabled).
bogdanm	0:9b334a45a8ff	1011	* @note MSI can not be stopped if it is used as system clock source.
bogdanm	0:9b334a45a8ff	1012	* In this case, you have to select another source of the system
bogdanm	0:9b334a45a8ff	1013	* clock then stop the MSI.
bogdanm	0:9b334a45a8ff	1014	* @note After enabling the MSI, the application software should wait on
bogdanm	0:9b334a45a8ff	1015	* MSIRDY flag to be set indicating that MSI clock is stable and can
bogdanm	0:9b334a45a8ff	1016	* be used as system clock source.
bogdanm	0:9b334a45a8ff	1017	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
bogdanm	0:9b334a45a8ff	1018	* clock cycles.
bogdanm	0:9b334a45a8ff	1019	*/
bogdanm	0:9b334a45a8ff	1020	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
bogdanm	0:9b334a45a8ff	1021	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023
bogdanm	0:9b334a45a8ff	1024	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
bogdanm	0:9b334a45a8ff	1025	* @note The calibration is used to compensate for the variations in voltage
bogdanm	0:9b334a45a8ff	1026	* and temperature that influence the frequency of the internal MSI RC.
bogdanm	0:9b334a45a8ff	1027	* Refer to the Application Note AN3300 for more details on how to
bogdanm	0:9b334a45a8ff	1028	* calibrate the MSI.
bogdanm	0:9b334a45a8ff	1029	* @param __MSICalibrationValue__: specifies the calibration trimming value.
bogdanm	0:9b334a45a8ff	1030	* This parameter must be a number between 0 and 0xFF.
bogdanm	0:9b334a45a8ff	1031	*/
bogdanm	0:9b334a45a8ff	1032	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
bogdanm	0:9b334a45a8ff	1033	RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	/**
bogdanm	0:9b334a45a8ff	1036	* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
bogdanm	0:9b334a45a8ff	1037	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
bogdanm	0:9b334a45a8ff	1038	* around 2.097 MHz. The MSI clock does not change after wake-up from
bogdanm	0:9b334a45a8ff	1039	* STOP mode.
bogdanm	0:9b334a45a8ff	1040	* @note The MSI clock range can be modified on the fly.
mbed_official	113:b3775bf36a83	1041	* @param __RCC_MSIRange__: specifies the MSI Clock range.
bogdanm	0:9b334a45a8ff	1042	* This parameter must be one of the following values:
bogdanm	0:9b334a45a8ff	1043	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
bogdanm	0:9b334a45a8ff	1044	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
bogdanm	0:9b334a45a8ff	1045	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
bogdanm	0:9b334a45a8ff	1046	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
bogdanm	0:9b334a45a8ff	1047	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
bogdanm	0:9b334a45a8ff	1048	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
bogdanm	0:9b334a45a8ff	1049	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
bogdanm	0:9b334a45a8ff	1050	*/
bogdanm	0:9b334a45a8ff	1051	#define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
bogdanm	0:9b334a45a8ff	1052	RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
mbed_official	113:b3775bf36a83	1053
mbed_official	113:b3775bf36a83	1054	/** @brief Macro to get the Internal Multi Speed oscillator (__MSI__) clock range in run mode
mbed_official	113:b3775bf36a83	1055	* @retval MSI clock range.
mbed_official	113:b3775bf36a83	1056	* This parameter must be one of the following values:
mbed_official	113:b3775bf36a83	1057	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
mbed_official	113:b3775bf36a83	1058	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
mbed_official	113:b3775bf36a83	1059	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
mbed_official	113:b3775bf36a83	1060	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
mbed_official	113:b3775bf36a83	1061	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
mbed_official	113:b3775bf36a83	1062	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
mbed_official	113:b3775bf36a83	1063	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
mbed_official	113:b3775bf36a83	1064
mbed_official	113:b3775bf36a83	1065	*/
mbed_official	113:b3775bf36a83	1066	#define __HAL_RCC_GET_MSI_RANGE() \
mbed_official	113:b3775bf36a83	1067	((uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE) >> 12))
bogdanm	0:9b334a45a8ff	1068
bogdanm	0:9b334a45a8ff	1069	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm	0:9b334a45a8ff	1070	* @note After enabling the LSI, the application software should wait on
bogdanm	0:9b334a45a8ff	1071	* LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm	0:9b334a45a8ff	1072	* be used to clock the IWDG and/or the RTC.
bogdanm	0:9b334a45a8ff	1073	* @note LSI can not be disabled if the IWDG is running.
bogdanm	0:9b334a45a8ff	1074	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm	0:9b334a45a8ff	1075	* clock cycles.
bogdanm	0:9b334a45a8ff	1076	*/
mbed_official	113:b3775bf36a83	1077	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	1078	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	1079
bogdanm	0:9b334a45a8ff	1080	/**
bogdanm	0:9b334a45a8ff	1081	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	113:b3775bf36a83	1082	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
mbed_official	113:b3775bf36a83	1083	* supported by this macro. User should request a transition to HSE Off
mbed_official	113:b3775bf36a83	1084	* first and then HSE On or HSE Bypass.
bogdanm	0:9b334a45a8ff	1085	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	0:9b334a45a8ff	1086	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	0:9b334a45a8ff	1087	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	0:9b334a45a8ff	1088	* @note HSE state can not be changed if it is used directly or through the
bogdanm	0:9b334a45a8ff	1089	* PLL as system clock. In this case, you have to select another source
bogdanm	0:9b334a45a8ff	1090	* of the system clock then change the HSE state (ex. disable it).
bogdanm	0:9b334a45a8ff	1091	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1092	* @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm	0:9b334a45a8ff	1093	* was previously enabled you have to enable it again after calling this
bogdanm	0:9b334a45a8ff	1094	* function.
bogdanm	0:9b334a45a8ff	1095	* @param __STATE__: specifies the new state of the HSE.
bogdanm	0:9b334a45a8ff	1096	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1097	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	0:9b334a45a8ff	1098	* 6 HSE oscillator clock cycles.
bogdanm	0:9b334a45a8ff	1099	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm	0:9b334a45a8ff	1100	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm	0:9b334a45a8ff	1101	*/
bogdanm	0:9b334a45a8ff	1102	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
bogdanm	0:9b334a45a8ff	1103	do { \
mbed_official	113:b3775bf36a83	1104	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1105	if((__STATE__) == RCC_HSE_ON) \
bogdanm	0:9b334a45a8ff	1106	{ \
bogdanm	0:9b334a45a8ff	1107	SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	1108	} \
bogdanm	0:9b334a45a8ff	1109	else if((__STATE__) == RCC_HSE_BYPASS) \
bogdanm	0:9b334a45a8ff	1110	{ \
mbed_official	113:b3775bf36a83	1111	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	1112	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	1113	SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	1114	} \
bogdanm	0:9b334a45a8ff	1115	else \
bogdanm	0:9b334a45a8ff	1116	{ \
mbed_official	113:b3775bf36a83	1117	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	113:b3775bf36a83	1118	/* Delay after an RCC peripheral clock */ \
mbed_official	113:b3775bf36a83	1119	tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	113:b3775bf36a83	1120	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1121	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	1122	} \
bogdanm	0:9b334a45a8ff	1123	} while(0)
mbed_official	113:b3775bf36a83	1124
bogdanm	0:9b334a45a8ff	1125	/**
bogdanm	0:9b334a45a8ff	1126	* @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official	113:b3775bf36a83	1127	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
mbed_official	113:b3775bf36a83	1128	* supported by this macro. User should request a transition to LSE Off
mbed_official	113:b3775bf36a83	1129	* first and then LSE On or LSE Bypass.
bogdanm	0:9b334a45a8ff	1130	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	113:b3775bf36a83	1131	* this domain after reset, you have to enable write access using
bogdanm	0:9b334a45a8ff	1132	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	113:b3775bf36a83	1133	* (to be done once after reset).
bogdanm	0:9b334a45a8ff	1134	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm	0:9b334a45a8ff	1135	* software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm	0:9b334a45a8ff	1136	* is stable and can be used to clock the RTC.
bogdanm	0:9b334a45a8ff	1137	* @param __STATE__: specifies the new state of the LSE.
bogdanm	0:9b334a45a8ff	1138	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1139	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm	0:9b334a45a8ff	1140	* 6 LSE oscillator clock cycles.
bogdanm	0:9b334a45a8ff	1141	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm	0:9b334a45a8ff	1142	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm	0:9b334a45a8ff	1143	*/
mbed_official	113:b3775bf36a83	1144	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
bogdanm	0:9b334a45a8ff	1145	do { \
bogdanm	0:9b334a45a8ff	1146	if((__STATE__) == RCC_LSE_ON) \
bogdanm	0:9b334a45a8ff	1147	{ \
bogdanm	0:9b334a45a8ff	1148	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
bogdanm	0:9b334a45a8ff	1149	} \
bogdanm	0:9b334a45a8ff	1150	else if((__STATE__) == RCC_LSE_OFF) \
bogdanm	0:9b334a45a8ff	1151	{ \
bogdanm	0:9b334a45a8ff	1152	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
mbed_official	113:b3775bf36a83	1153	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
bogdanm	0:9b334a45a8ff	1154	} \
bogdanm	0:9b334a45a8ff	1155	else if((__STATE__) == RCC_LSE_BYPASS) \
bogdanm	0:9b334a45a8ff	1156	{ \
bogdanm	0:9b334a45a8ff	1157	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
bogdanm	0:9b334a45a8ff	1158	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
bogdanm	0:9b334a45a8ff	1159	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
bogdanm	0:9b334a45a8ff	1160	} \
bogdanm	0:9b334a45a8ff	1161	else \
bogdanm	0:9b334a45a8ff	1162	{ \
bogdanm	0:9b334a45a8ff	1163	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
bogdanm	0:9b334a45a8ff	1164	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
bogdanm	0:9b334a45a8ff	1165	} \
bogdanm	0:9b334a45a8ff	1166	} while(0)
bogdanm	0:9b334a45a8ff	1167
mbed_official	113:b3775bf36a83	1168
bogdanm	0:9b334a45a8ff	1169
bogdanm	0:9b334a45a8ff	1170	/**
bogdanm	0:9b334a45a8ff	1171	* @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
bogdanm	0:9b334a45a8ff	1172	* @note As the RTC clock configuration bits are in the RTC domain and write
bogdanm	0:9b334a45a8ff	1173	* access is denied to this domain after reset, you have to enable write
bogdanm	0:9b334a45a8ff	1174	* access using PWR_RTCAccessCmd(ENABLE) function before to configure
bogdanm	0:9b334a45a8ff	1175	* the RTC clock source (to be done once after reset).
bogdanm	0:9b334a45a8ff	1176	* @note Once the RTC clock is configured it cannot be changed unless the RTC
bogdanm	0:9b334a45a8ff	1177	* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
bogdanm	0:9b334a45a8ff	1178	* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
bogdanm	0:9b334a45a8ff	1179	*
mbed_official	113:b3775bf36a83	1180	* @param __RTCCLKSOURCE__: specifies the RTC clock source.
bogdanm	0:9b334a45a8ff	1181	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1182	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm	0:9b334a45a8ff	1183	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm	0:9b334a45a8ff	1184	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
bogdanm	0:9b334a45a8ff	1185	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
bogdanm	0:9b334a45a8ff	1186	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
bogdanm	0:9b334a45a8ff	1187	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
bogdanm	0:9b334a45a8ff	1188	*
bogdanm	0:9b334a45a8ff	1189	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm	0:9b334a45a8ff	1190	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	0:9b334a45a8ff	1191	* However, when the HSE clock is used as RTC clock source, the RTC
bogdanm	0:9b334a45a8ff	1192	* cannot be used in STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1193	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm	0:9b334a45a8ff	1194	* RTC clock source).
bogdanm	0:9b334a45a8ff	1195	*/
mbed_official	113:b3775bf36a83	1196
mbed_official	113:b3775bf36a83	1197	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSOURCE__) (((__RTCCLKSOURCE__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
mbed_official	113:b3775bf36a83	1198	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, (uint32_t)((__RTCCLKSOURCE__) & RCC_CR_RTCPRE)) : \
mbed_official	113:b3775bf36a83	1199	CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
bogdanm	0:9b334a45a8ff	1200
mbed_official	113:b3775bf36a83	1201	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSOURCE__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSOURCE__); \
mbed_official	113:b3775bf36a83	1202	MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)((__RTCCLKSOURCE__) & RCC_CSR_RTCSEL)); \
bogdanm	0:9b334a45a8ff	1203	} while (0)
bogdanm	0:9b334a45a8ff	1204
mbed_official	113:b3775bf36a83	1205
mbed_official	113:b3775bf36a83	1206	/**
mbed_official	113:b3775bf36a83	1207	* @brief Get the RTC and LCD clock (RTCCLK / LCDCLK).
mbed_official	113:b3775bf36a83	1208	*
mbed_official	113:b3775bf36a83	1209	* @retval The clock source can be one of the following values:
mbed_official	113:b3775bf36a83	1210	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
mbed_official	113:b3775bf36a83	1211	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
mbed_official	113:b3775bf36a83	1212	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
mbed_official	113:b3775bf36a83	1213	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
mbed_official	113:b3775bf36a83	1214	*
mbed_official	113:b3775bf36a83	1215	*/
bogdanm	0:9b334a45a8ff	1216	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
mbed_official	113:b3775bf36a83	1217
mbed_official	113:b3775bf36a83	1218	/**
mbed_official	113:b3775bf36a83	1219	* @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
mbed_official	113:b3775bf36a83	1220	*
mbed_official	113:b3775bf36a83	1221	* @retval Returned value can be one of the following values:
mbed_official	113:b3775bf36a83	1222	* @arg @ref RCC_RTC_HSE_DIV_2: HSE divided by 2 selected as RTC clock
mbed_official	113:b3775bf36a83	1223	* @arg @ref RCC_RTC_HSE_DIV_4: HSE divided by 4 selected as RTC clock
mbed_official	113:b3775bf36a83	1224	* @arg @ref RCC_RTC_HSE_DIV_8: HSE divided by 8 selected as RTC clock
mbed_official	113:b3775bf36a83	1225	* @arg @ref RCC_RTC_HSE_DIV_16: HSE divided by 16 selected as RTC clock
mbed_official	113:b3775bf36a83	1226	*
bogdanm	0:9b334a45a8ff	1227	*/
mbed_official	113:b3775bf36a83	1228	#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
bogdanm	0:9b334a45a8ff	1229
bogdanm	0:9b334a45a8ff	1230	/** @brief Macros to enable or disable the main PLL.
bogdanm	0:9b334a45a8ff	1231	* @note After enabling the main PLL, the application software should wait on
bogdanm	0:9b334a45a8ff	1232	* PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm	0:9b334a45a8ff	1233	* be used as system clock source.
bogdanm	0:9b334a45a8ff	1234	* @note The main PLL can not be disabled if it is used as system clock source
bogdanm	0:9b334a45a8ff	1235	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1236	*/
mbed_official	113:b3775bf36a83	1237	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	1238	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
bogdanm	0:9b334a45a8ff	1241	* @note This function must be used only when the main PLL is disabled.
mbed_official	113:b3775bf36a83	1242	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
bogdanm	0:9b334a45a8ff	1243	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1244	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	1245	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	1246	* @param __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
bogdanm	0:9b334a45a8ff	1247	* This parameter must be one of the following values:
bogdanm	0:9b334a45a8ff	1248	* @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
bogdanm	0:9b334a45a8ff	1249	* @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
bogdanm	0:9b334a45a8ff	1250	* @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
bogdanm	0:9b334a45a8ff	1251	* @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
bogdanm	0:9b334a45a8ff	1252	* @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
bogdanm	0:9b334a45a8ff	1253	* @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
bogdanm	0:9b334a45a8ff	1254	* @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
bogdanm	0:9b334a45a8ff	1255	* @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
bogdanm	0:9b334a45a8ff	1256	* @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
bogdanm	0:9b334a45a8ff	1257	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
bogdanm	0:9b334a45a8ff	1258	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
bogdanm	0:9b334a45a8ff	1259	* in Range 3.
bogdanm	0:9b334a45a8ff	1260	* @param __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
bogdanm	0:9b334a45a8ff	1261	* This parameter must be one of the following values:
bogdanm	0:9b334a45a8ff	1262	* @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
bogdanm	0:9b334a45a8ff	1263	* @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
bogdanm	0:9b334a45a8ff	1264	* @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
bogdanm	0:9b334a45a8ff	1265	*/
bogdanm	0:9b334a45a8ff	1266
mbed_official	113:b3775bf36a83	1267	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PLLMUL__ ,__PLLDIV__ ) \
mbed_official	113:b3775bf36a83	1268	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\| (__PLLDIV__)\| (__RCC_PLLSOURCE__)))
bogdanm	0:9b334a45a8ff	1269
mbed_official	113:b3775bf36a83	1270	/** @brief Macro to get the oscillator used as PLL clock source.
bogdanm	0:9b334a45a8ff	1271	* @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm	0:9b334a45a8ff	1272	* of the following:
bogdanm	0:9b334a45a8ff	1273	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm	0:9b334a45a8ff	1274	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm	0:9b334a45a8ff	1275	*/
bogdanm	0:9b334a45a8ff	1276	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
bogdanm	0:9b334a45a8ff	1277
mbed_official	113:b3775bf36a83	1278	/**
mbed_official	113:b3775bf36a83	1279	* @brief Macro to configure the system clock source.
mbed_official	113:b3775bf36a83	1280	* @param __SYSCLKSOURCE__: specifies the system clock source.
mbed_official	113:b3775bf36a83	1281	* This parameter can be one of the following values:
mbed_official	113:b3775bf36a83	1282	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
mbed_official	113:b3775bf36a83	1283	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
mbed_official	113:b3775bf36a83	1284	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
mbed_official	113:b3775bf36a83	1285	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
mbed_official	113:b3775bf36a83	1286	* @retval None
mbed_official	113:b3775bf36a83	1287	*/
mbed_official	113:b3775bf36a83	1288	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
mbed_official	113:b3775bf36a83	1289	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
mbed_official	113:b3775bf36a83	1290
mbed_official	113:b3775bf36a83	1291	/** @brief Macro to get the clock source used as system clock.
mbed_official	113:b3775bf36a83	1292	* @retval The clock source used as system clock. The returned value can be one
mbed_official	113:b3775bf36a83	1293	* of the following:
mbed_official	113:b3775bf36a83	1294	* - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
mbed_official	113:b3775bf36a83	1295	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
mbed_official	113:b3775bf36a83	1296	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
mbed_official	113:b3775bf36a83	1297	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
mbed_official	113:b3775bf36a83	1298	*/
mbed_official	113:b3775bf36a83	1299	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
mbed_official	113:b3775bf36a83	1300
mbed_official	113:b3775bf36a83	1301
mbed_official	113:b3775bf36a83	1302	/** @brief Macro to configure the MCO clock.
mbed_official	113:b3775bf36a83	1303	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
mbed_official	113:b3775bf36a83	1304	* This parameter can be one of the following values:
mbed_official	113:b3775bf36a83	1305	* @arg RCC_CFGR_MCO_HSI: HSI clock selected as MCO source
mbed_official	113:b3775bf36a83	1306	* @arg RCC_CFGR_MCO_MSI: MSI clock selected as MCO source
mbed_official	113:b3775bf36a83	1307	* @arg RCC_CFGR_MCO_HSE: HSE clock selected as MCO source
mbed_official	113:b3775bf36a83	1308	* @arg RCC_CFGR_MCO_PLL: PLL clock selected as MCO source
mbed_official	113:b3775bf36a83	1309	* @arg RCC_CFGR_MCO_LSI: LSI clock selected as MCO source
mbed_official	113:b3775bf36a83	1310	* @arg RCC_CFGR_MCO_LSE: LSE clock selected as MCO source
mbed_official	113:b3775bf36a83	1311	* @param __MCODIV__ specifies the MCO clock prescaler.
mbed_official	113:b3775bf36a83	1312	* This parameter can be one of the following values:
mbed_official	113:b3775bf36a83	1313	* @arg RCC_CFGR_MCO_PRE_1: no division applied to MCO clock
mbed_official	113:b3775bf36a83	1314	* @arg RCC_CFGR_MCO_PRE_2: division by 2 applied to MCO clock
mbed_official	113:b3775bf36a83	1315	* @arg RCC_CFGR_MCO_PRE_4: division by 4 applied to MCO clock
mbed_official	113:b3775bf36a83	1316	* @arg RCC_CFGR_MCO_PRE_8: division by 8 applied to MCO clock
mbed_official	113:b3775bf36a83	1317	* @arg RCC_CFGR_MCO_PRE_16: division by 16 applied to MCO clock
mbed_official	113:b3775bf36a83	1318	*/
mbed_official	113:b3775bf36a83	1319
mbed_official	113:b3775bf36a83	1320	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
mbed_official	113:b3775bf36a83	1321	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
mbed_official	113:b3775bf36a83	1322
mbed_official	113:b3775bf36a83	1323
mbed_official	113:b3775bf36a83	1324	/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
bogdanm	0:9b334a45a8ff	1325	* @brief macros to manage the specified RCC Flags and interrupts.
bogdanm	0:9b334a45a8ff	1326	* @{
bogdanm	0:9b334a45a8ff	1327	*/
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
bogdanm	0:9b334a45a8ff	1330	* the selected interrupts).
bogdanm	0:9b334a45a8ff	1331	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
bogdanm	0:9b334a45a8ff	1332	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
bogdanm	0:9b334a45a8ff	1333	* automatically generated. The NMI will be executed indefinitely, and
bogdanm	0:9b334a45a8ff	1334	* since NMI has higher priority than any other IRQ (and main program)
bogdanm	0:9b334a45a8ff	1335	* the application will be stacked in the NMI ISR unless the CSS interrupt
bogdanm	0:9b334a45a8ff	1336	* pending bit is cleared.
bogdanm	0:9b334a45a8ff	1337	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm	0:9b334a45a8ff	1338	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1339	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1340	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1341	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1342	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1343	* @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm	0:9b334a45a8ff	1344	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	113:b3775bf36a83	1345	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
bogdanm	0:9b334a45a8ff	1346	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
bogdanm	0:9b334a45a8ff	1347	*/
mbed_official	113:b3775bf36a83	1348	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1349
bogdanm	0:9b334a45a8ff	1350	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
bogdanm	0:9b334a45a8ff	1351	* the selected interrupts).
bogdanm	0:9b334a45a8ff	1352	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
bogdanm	0:9b334a45a8ff	1353	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
bogdanm	0:9b334a45a8ff	1354	* automatically generated. The NMI will be executed indefinitely, and
bogdanm	0:9b334a45a8ff	1355	* since NMI has higher priority than any other IRQ (and main program)
bogdanm	0:9b334a45a8ff	1356	* the application will be stacked in the NMI ISR unless the CSS interrupt
bogdanm	0:9b334a45a8ff	1357	* pending bit is cleared.
bogdanm	0:9b334a45a8ff	1358	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm	0:9b334a45a8ff	1359	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1360	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1361	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1362	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1363	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1364	* @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm	0:9b334a45a8ff	1365	* @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm	0:9b334a45a8ff	1366	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
mbed_official	113:b3775bf36a83	1367	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
bogdanm	0:9b334a45a8ff	1368
bogdanm	0:9b334a45a8ff	1369	*/
mbed_official	113:b3775bf36a83	1370	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm	0:9b334a45a8ff	1373	* bits to clear the selected interrupt pending bits.
bogdanm	0:9b334a45a8ff	1374	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	1375	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1376	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1377	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1378	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1379	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1380	* @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm	0:9b334a45a8ff	1381	* @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm	0:9b334a45a8ff	1382	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
mbed_official	113:b3775bf36a83	1383	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
mbed_official	113:b3775bf36a83	1384	* @arg RCC_IT_CSSHSE: Clock Security System interrupt
bogdanm	0:9b334a45a8ff	1385	*/
bogdanm	0:9b334a45a8ff	1386	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1387
bogdanm	0:9b334a45a8ff	1388	/** @brief Check the RCC's interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	1389	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm	0:9b334a45a8ff	1390	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1391	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1392	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1393	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1394	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1395	* @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm	0:9b334a45a8ff	1396	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	113:b3775bf36a83	1397	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
mbed_official	113:b3775bf36a83	1398	* @arg RCC_IT_CSSHSE: Clock Security System interrupt
bogdanm	0:9b334a45a8ff	1399	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1400	*/
mbed_official	113:b3775bf36a83	1401	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	113:b3775bf36a83	1402
bogdanm	0:9b334a45a8ff	1403
bogdanm	0:9b334a45a8ff	1404	/** @brief Set RMVF bit to clear the reset flags.
bogdanm	0:9b334a45a8ff	1405	* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
bogdanm	0:9b334a45a8ff	1406	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
bogdanm	0:9b334a45a8ff	1407	*/
bogdanm	0:9b334a45a8ff	1408	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410	/** @brief Check RCC flag is set or not.
bogdanm	0:9b334a45a8ff	1411	* @param __FLAG__: specifies the flag to check.
bogdanm	0:9b334a45a8ff	1412	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1413	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official	113:b3775bf36a83	1414	* @arg RCC_FLAG_HSIDIV: HSI clock divider flag
bogdanm	0:9b334a45a8ff	1415	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
bogdanm	0:9b334a45a8ff	1416	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
bogdanm	0:9b334a45a8ff	1417	* @arg RCC_FLAG_PLLRDY: PLL clock ready
bogdanm	0:9b334a45a8ff	1418	* @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
bogdanm	0:9b334a45a8ff	1419	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
bogdanm	0:9b334a45a8ff	1420	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
bogdanm	0:9b334a45a8ff	1421	* @arg RCC_FLAG_FWRST: Firewall reset
bogdanm	0:9b334a45a8ff	1422	* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
bogdanm	0:9b334a45a8ff	1423	* @arg RCC_FLAG_PINRST: Pin reset
bogdanm	0:9b334a45a8ff	1424	* @arg RCC_FLAG_PORRST: POR/PDR reset
bogdanm	0:9b334a45a8ff	1425	* @arg RCC_FLAG_SFTRST: Software reset
bogdanm	0:9b334a45a8ff	1426	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
bogdanm	0:9b334a45a8ff	1427	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
bogdanm	0:9b334a45a8ff	1428	* @arg RCC_FLAG_LPWRRST: Low Power reset
bogdanm	0:9b334a45a8ff	1429	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1430	*/
bogdanm	0:9b334a45a8ff	1431	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
bogdanm	0:9b334a45a8ff	1432	RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	/**
bogdanm	0:9b334a45a8ff	1435	* @}
bogdanm	0:9b334a45a8ff	1436	*/
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	/**
bogdanm	0:9b334a45a8ff	1439	* @}
bogdanm	0:9b334a45a8ff	1440	*/
bogdanm	0:9b334a45a8ff	1441
mbed_official	113:b3775bf36a83	1442
mbed_official	113:b3775bf36a83	1443	/* Private constants ---------------------------------------------------------*/
mbed_official	113:b3775bf36a83	1444	/** @defgroup RCC_Private_Constants RCC Private Constants
mbed_official	113:b3775bf36a83	1445	* @{
mbed_official	113:b3775bf36a83	1446	*/
mbed_official	113:b3775bf36a83	1447	/* Defines used for Flags */
mbed_official	113:b3775bf36a83	1448	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	113:b3775bf36a83	1449
mbed_official	113:b3775bf36a83	1450	/**
mbed_official	113:b3775bf36a83	1451	* @}
mbed_official	113:b3775bf36a83	1452	*/
mbed_official	113:b3775bf36a83	1453
mbed_official	113:b3775bf36a83	1454	/* Private macros ------------------------------------------------------------*/
mbed_official	113:b3775bf36a83	1455	/** @addtogroup RCC_Private_Macros
mbed_official	113:b3775bf36a83	1456	* @{
mbed_official	113:b3775bf36a83	1457	*/
mbed_official	113:b3775bf36a83	1458
mbed_official	113:b3775bf36a83	1459	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	1460	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F)
mbed_official	113:b3775bf36a83	1461	#else
mbed_official	113:b3775bf36a83	1462	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F)
mbed_official	113:b3775bf36a83	1463	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
mbed_official	113:b3775bf36a83	1464
mbed_official	113:b3775bf36a83	1465	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
mbed_official	113:b3775bf36a83	1466	((__HSE__) == RCC_HSE_BYPASS))
mbed_official	113:b3775bf36a83	1467	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
mbed_official	113:b3775bf36a83	1468	((__LSE__) == RCC_LSE_BYPASS))
mbed_official	113:b3775bf36a83	1469
mbed_official	113:b3775bf36a83	1470	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
mbed_official	113:b3775bf36a83	1471	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
mbed_official	113:b3775bf36a83	1472	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
mbed_official	113:b3775bf36a83	1473	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
mbed_official	113:b3775bf36a83	1474	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
mbed_official	113:b3775bf36a83	1475	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
mbed_official	113:b3775bf36a83	1476	((__RANGE__) == RCC_MSIRANGE_6))
mbed_official	113:b3775bf36a83	1477
mbed_official	113:b3775bf36a83	1478	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
mbed_official	113:b3775bf36a83	1479	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
mbed_official	113:b3775bf36a83	1480	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
mbed_official	113:b3775bf36a83	1481
mbed_official	113:b3775bf36a83	1482	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| ((__PLL__) == RCC_PLL_ON))
mbed_official	113:b3775bf36a83	1483
mbed_official	113:b3775bf36a83	1484	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	113:b3775bf36a83	1485	((__SOURCE__) == RCC_PLLSOURCE_HSE))
mbed_official	113:b3775bf36a83	1486
mbed_official	113:b3775bf36a83	1487	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) \|\| ((__MUL__) == RCC_PLLMUL_4) \|\| \
mbed_official	113:b3775bf36a83	1488	((__MUL__) == RCC_PLLMUL_6) \|\| ((__MUL__) == RCC_PLLMUL_8) \|\| \
mbed_official	113:b3775bf36a83	1489	((__MUL__) == RCC_PLLMUL_12) \|\| ((__MUL__) == RCC_PLLMUL_16) \|\| \
mbed_official	113:b3775bf36a83	1490	((__MUL__) == RCC_PLLMUL_24) \|\| ((__MUL__) == RCC_PLLMUL_32) \|\| \
mbed_official	113:b3775bf36a83	1491	((__MUL__) == RCC_PLLMUL_48))
mbed_official	113:b3775bf36a83	1492
mbed_official	113:b3775bf36a83	1493	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) \|\| ((__DIV__) == RCC_PLLDIV_3) \|\| \
mbed_official	113:b3775bf36a83	1494	((__DIV__) == RCC_PLLDIV_4))
mbed_official	113:b3775bf36a83	1495
mbed_official	113:b3775bf36a83	1496	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
mbed_official	113:b3775bf36a83	1497
mbed_official	113:b3775bf36a83	1498	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	113:b3775bf36a83	1499	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	113:b3775bf36a83	1500	((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
mbed_official	113:b3775bf36a83	1501	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	113:b3775bf36a83	1502
mbed_official	113:b3775bf36a83	1503	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	113:b3775bf36a83	1504	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	113:b3775bf36a83	1505	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	113:b3775bf36a83	1506	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	113:b3775bf36a83	1507	((__HCLK__) == RCC_SYSCLK_DIV512))
mbed_official	113:b3775bf36a83	1508
mbed_official	113:b3775bf36a83	1509	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
mbed_official	113:b3775bf36a83	1510	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
mbed_official	113:b3775bf36a83	1511	((__PCLK__) == RCC_HCLK_DIV16))
mbed_official	113:b3775bf36a83	1512
mbed_official	113:b3775bf36a83	1513	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
mbed_official	113:b3775bf36a83	1514	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
mbed_official	113:b3775bf36a83	1515	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
mbed_official	113:b3775bf36a83	1516	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
mbed_official	113:b3775bf36a83	1517	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
mbed_official	113:b3775bf36a83	1518	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
mbed_official	113:b3775bf36a83	1519
mbed_official	113:b3775bf36a83	1520	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) \
mbed_official	113:b3775bf36a83	1521	&& !defined (STM32L011xx) && !defined (STM32L021xx)
mbed_official	113:b3775bf36a83	1522	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
mbed_official	113:b3775bf36a83	1523	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
mbed_official	113:b3775bf36a83	1524	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
mbed_official	113:b3775bf36a83	1525	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
mbed_official	113:b3775bf36a83	1526	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
mbed_official	113:b3775bf36a83	1527	#else
mbed_official	113:b3775bf36a83	1528	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
mbed_official	113:b3775bf36a83	1529	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
mbed_official	113:b3775bf36a83	1530	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
mbed_official	113:b3775bf36a83	1531	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
mbed_official	113:b3775bf36a83	1532	#endif
mbed_official	113:b3775bf36a83	1533
mbed_official	113:b3775bf36a83	1534	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| \
mbed_official	113:b3775bf36a83	1535	((__DIV__) == RCC_MCODIV_2) \|\| \
mbed_official	113:b3775bf36a83	1536	((__DIV__) == RCC_MCODIV_4) \|\| \
mbed_official	113:b3775bf36a83	1537	((__DIV__) == RCC_MCODIV_8) \|\| \
mbed_official	113:b3775bf36a83	1538	((__DIV__) == RCC_MCODIV_16))
mbed_official	113:b3775bf36a83	1539
mbed_official	113:b3775bf36a83	1540	#if defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	113:b3775bf36a83	1541	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	113:b3775bf36a83	1542	#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) \|\| ((__MCOx__) == RCC_MCO2) \|\| ((__MCOx__) == RCC_MCO3))
mbed_official	113:b3775bf36a83	1543	#else
mbed_official	113:b3775bf36a83	1544	#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) \|\| ((__MCOx__) == RCC_MCO2))
mbed_official	113:b3775bf36a83	1545
mbed_official	113:b3775bf36a83	1546	#endif
mbed_official	113:b3775bf36a83	1547
mbed_official	113:b3775bf36a83	1548	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
mbed_official	113:b3775bf36a83	1549	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
mbed_official	113:b3775bf36a83	1550
mbed_official	113:b3775bf36a83	1551	/**
mbed_official	113:b3775bf36a83	1552	* @}
mbed_official	113:b3775bf36a83	1553	*/
mbed_official	113:b3775bf36a83	1554
bogdanm	0:9b334a45a8ff	1555	/* Include RCC HAL Extension module */
bogdanm	0:9b334a45a8ff	1556	#include "stm32l0xx_hal_rcc_ex.h"
bogdanm	0:9b334a45a8ff	1557
bogdanm	0:9b334a45a8ff	1558	/** @defgroup RCC_Exported_Functions RCC Exported Functions
bogdanm	0:9b334a45a8ff	1559	* @{
bogdanm	0:9b334a45a8ff	1560	*/
bogdanm	0:9b334a45a8ff	1561
bogdanm	0:9b334a45a8ff	1562	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	1563	* @{
bogdanm	0:9b334a45a8ff	1564	*/
bogdanm	0:9b334a45a8ff	1565	void HAL_RCC_DeInit(void);
bogdanm	0:9b334a45a8ff	1566	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	1567	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	0:9b334a45a8ff	1568	/**
bogdanm	0:9b334a45a8ff	1569	* @}
bogdanm	0:9b334a45a8ff	1570	*/
bogdanm	0:9b334a45a8ff	1571
bogdanm	0:9b334a45a8ff	1572	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1573	* @{
bogdanm	0:9b334a45a8ff	1574	*/
bogdanm	0:9b334a45a8ff	1575	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	113:b3775bf36a83	1576	#if !defined (STM32L011xx) && !defined (STM32L021xx)
bogdanm	0:9b334a45a8ff	1577	void HAL_RCC_EnableCSS(void);
mbed_official	113:b3775bf36a83	1578	#endif
bogdanm	0:9b334a45a8ff	1579	uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm	0:9b334a45a8ff	1580	uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm	0:9b334a45a8ff	1581	uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm	0:9b334a45a8ff	1582	uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm	0:9b334a45a8ff	1583	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	1584	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	0:9b334a45a8ff	1585	/* CSS NMI IRQ handler */
bogdanm	0:9b334a45a8ff	1586	void HAL_RCC_NMI_IRQHandler(void);
bogdanm	0:9b334a45a8ff	1587
bogdanm	0:9b334a45a8ff	1588	/* User Callbacks in non blocking mode (IT mode) */
bogdanm	0:9b334a45a8ff	1589	void HAL_RCC_CSSCallback(void);
bogdanm	0:9b334a45a8ff	1590	/**
bogdanm	0:9b334a45a8ff	1591	* @}
bogdanm	0:9b334a45a8ff	1592	*/
bogdanm	0:9b334a45a8ff	1593
bogdanm	0:9b334a45a8ff	1594	/**
bogdanm	0:9b334a45a8ff	1595	* @}
bogdanm	0:9b334a45a8ff	1596	*/
mbed_official	113:b3775bf36a83	1597
mbed_official	113:b3775bf36a83	1598
bogdanm	0:9b334a45a8ff	1599	/**
bogdanm	0:9b334a45a8ff	1600	* @}
bogdanm	0:9b334a45a8ff	1601	*/
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	/**
bogdanm	0:9b334a45a8ff	1604	* @}
bogdanm	0:9b334a45a8ff	1605	*/
bogdanm	0:9b334a45a8ff	1606
bogdanm	0:9b334a45a8ff	1607	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1608	}
bogdanm	0:9b334a45a8ff	1609	#endif
bogdanm	0:9b334a45a8ff	1610
bogdanm	0:9b334a45a8ff	1611	#endif /* __STM32l0xx_HAL_RCC_H */
bogdanm	0:9b334a45a8ff	1612
bogdanm	0:9b334a45a8ff	1613	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	1614

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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