mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 113:b3775bf36a83

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_rcc.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.2.0
bogdanm	0:9b334a45a8ff	6	* @date 06-February-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of RCC HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32L0xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	40	#define __STM32L0xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32l0xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @defgroup RCC RCC
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58
bogdanm	0:9b334a45a8ff	59	/**
bogdanm	0:9b334a45a8ff	60	* @brief RCC PLL configuration structure definition
bogdanm	0:9b334a45a8ff	61	*/
bogdanm	0:9b334a45a8ff	62	typedef struct
bogdanm	0:9b334a45a8ff	63	{
bogdanm	0:9b334a45a8ff	64	uint32_t PLLState; /*!< The new state of the PLL.
bogdanm	0:9b334a45a8ff	65	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
bogdanm	0:9b334a45a8ff	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO output clock
bogdanm	0:9b334a45a8ff	71	This parameter must of @ref RCC_PLLMultiplication_Factor */
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	uint32_t PLLDIV; /*!< PLLDIV: Division factor for main system clock (SYSCLK)
bogdanm	0:9b334a45a8ff	74	This parameter must be a value of @ref RCC_PLLDivider_Factor */
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76	}RCC_PLLInitTypeDef;
bogdanm	0:9b334a45a8ff	77
bogdanm	0:9b334a45a8ff	78	/**
bogdanm	0:9b334a45a8ff	79	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm	0:9b334a45a8ff	80	*/
bogdanm	0:9b334a45a8ff	81	typedef struct
bogdanm	0:9b334a45a8ff	82	{
bogdanm	0:9b334a45a8ff	83	uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm	0:9b334a45a8ff	84	This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	uint32_t HSEState; /*!< The new state of the HSE.
bogdanm	0:9b334a45a8ff	87	This parameter can be a value of @ref RCC_HSE_Config */
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	uint32_t LSEState; /*!< The new state of the LSE.
bogdanm	0:9b334a45a8ff	90	This parameter can be a value of @ref RCC_LSE_Config */
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	uint32_t HSIState; /*!< The new state of the HSI.
bogdanm	0:9b334a45a8ff	93	This parameter can be a value of @ref RCC_HSI_Config */
bogdanm	0:9b334a45a8ff	94
bogdanm	0:9b334a45a8ff	95	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
bogdanm	0:9b334a45a8ff	96	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	uint32_t LSIState; /*!< The new state of the LSI.
bogdanm	0:9b334a45a8ff	99	This parameter can be a value of @ref RCC_LSI_Config */
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	102	uint32_t HSI48State; /*!< The new state of the HSI48.
bogdanm	0:9b334a45a8ff	103	This parameter can be a value of @ref RCC_HSI48_Config */
bogdanm	0:9b334a45a8ff	104	#endif
bogdanm	0:9b334a45a8ff	105
bogdanm	0:9b334a45a8ff	106	uint32_t MSIState; /*!< The new state of the MSI.
bogdanm	0:9b334a45a8ff	107	This parameter can be a value of @ref RCC_MSI_Config */
bogdanm	0:9b334a45a8ff	108
bogdanm	0:9b334a45a8ff	109	uint32_t MSICalibrationValue; /*!< The calibration trimming value.
bogdanm	0:9b334a45a8ff	110	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112	uint32_t MSIClockRange; /*!< The MSI frequency range.
bogdanm	0:9b334a45a8ff	113	This parameter can be a value of @ref RCC_MSI_Clock_Range */
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	}RCC_OscInitTypeDef;
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	/**
bogdanm	0:9b334a45a8ff	120	* @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm	0:9b334a45a8ff	121	*/
bogdanm	0:9b334a45a8ff	122	typedef struct
bogdanm	0:9b334a45a8ff	123	{
bogdanm	0:9b334a45a8ff	124	uint32_t ClockType; /*!< The clock to be configured.
bogdanm	0:9b334a45a8ff	125	This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm	0:9b334a45a8ff	128	This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm	0:9b334a45a8ff	129
bogdanm	0:9b334a45a8ff	130	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm	0:9b334a45a8ff	131	This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	0:9b334a45a8ff	134	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	0:9b334a45a8ff	135
bogdanm	0:9b334a45a8ff	136	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	0:9b334a45a8ff	137	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	0:9b334a45a8ff	138
bogdanm	0:9b334a45a8ff	139	}RCC_ClkInitTypeDef;
bogdanm	0:9b334a45a8ff	140
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/** @defgroup RCC_Private_Constants RCC Private constatnts
bogdanm	0:9b334a45a8ff	143	* @brief RCC registers bit address in the alias region
bogdanm	0:9b334a45a8ff	144	* @{
bogdanm	0:9b334a45a8ff	145	*/
bogdanm	0:9b334a45a8ff	146	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm	0:9b334a45a8ff	147	/* --- CR Register ---*/
bogdanm	0:9b334a45a8ff	148	/* Alias word address of HSION bit */
bogdanm	0:9b334a45a8ff	149	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm	0:9b334a45a8ff	150	/* --- CFGR Register ---*/
bogdanm	0:9b334a45a8ff	151	/* Alias word address of I2SSRC bit */
bogdanm	0:9b334a45a8ff	152	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
bogdanm	0:9b334a45a8ff	153	/* --- CSR Register ---*/
bogdanm	0:9b334a45a8ff	154	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	/* CR register byte 3 (Bits[23:16]) base address */
bogdanm	0:9b334a45a8ff	157	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	/* CIER register byte 0 (Bits[0:8]) base address */
bogdanm	0:9b334a45a8ff	160	#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
bogdanm	0:9b334a45a8ff	163	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	164
bogdanm	0:9b334a45a8ff	165	/**
bogdanm	0:9b334a45a8ff	166	* @}
bogdanm	0:9b334a45a8ff	167	*/
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	/** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm	0:9b334a45a8ff	170	* @{
bogdanm	0:9b334a45a8ff	171	*/
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
bogdanm	0:9b334a45a8ff	174	* @{
bogdanm	0:9b334a45a8ff	175	*/
bogdanm	0:9b334a45a8ff	176	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	177	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	178	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	179	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	180	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	181	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	182	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	183	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	184	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F)
bogdanm	0:9b334a45a8ff	185	#else
bogdanm	0:9b334a45a8ff	186	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F)
bogdanm	0:9b334a45a8ff	187	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm	0:9b334a45a8ff	188
bogdanm	0:9b334a45a8ff	189	/**
bogdanm	0:9b334a45a8ff	190	* @}
bogdanm	0:9b334a45a8ff	191	*/
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	/** @defgroup RCC_HSE_Config RCC HSE Config
bogdanm	0:9b334a45a8ff	194	* @{
bogdanm	0:9b334a45a8ff	195	*/
bogdanm	0:9b334a45a8ff	196	#define RCC_HSE_OFF ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	197	#define RCC_HSE_ON RCC_CR_HSEON
bogdanm	0:9b334a45a8ff	198	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
bogdanm	0:9b334a45a8ff	201	((__HSE__) == RCC_HSE_BYPASS))
bogdanm	0:9b334a45a8ff	202	/**
bogdanm	0:9b334a45a8ff	203	* @}
bogdanm	0:9b334a45a8ff	204	*/
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	/** @defgroup RCC_LSE_Config RCC LSE Config
bogdanm	0:9b334a45a8ff	207	* @{
bogdanm	0:9b334a45a8ff	208	*/
bogdanm	0:9b334a45a8ff	209	#define RCC_LSE_OFF ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	210	#define RCC_LSE_ON RCC_CSR_LSEON
bogdanm	0:9b334a45a8ff	211	#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP \| RCC_CSR_LSEON))
bogdanm	0:9b334a45a8ff	212
bogdanm	0:9b334a45a8ff	213	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
bogdanm	0:9b334a45a8ff	214	((__LSE__) == RCC_LSE_BYPASS))
bogdanm	0:9b334a45a8ff	215	/**
bogdanm	0:9b334a45a8ff	216	* @}
bogdanm	0:9b334a45a8ff	217	*/
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219
bogdanm	0:9b334a45a8ff	220
bogdanm	0:9b334a45a8ff	221	/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
bogdanm	0:9b334a45a8ff	222	* @{
bogdanm	0:9b334a45a8ff	223	*/
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
bogdanm	0:9b334a45a8ff	226	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
bogdanm	0:9b334a45a8ff	227	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
bogdanm	0:9b334a45a8ff	228	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
bogdanm	0:9b334a45a8ff	229	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
bogdanm	0:9b334a45a8ff	230	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
bogdanm	0:9b334a45a8ff	231	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
bogdanm	0:9b334a45a8ff	232
bogdanm	0:9b334a45a8ff	233	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
bogdanm	0:9b334a45a8ff	234	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
bogdanm	0:9b334a45a8ff	235	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
bogdanm	0:9b334a45a8ff	236	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
bogdanm	0:9b334a45a8ff	237	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
bogdanm	0:9b334a45a8ff	238	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
bogdanm	0:9b334a45a8ff	239	((__RANGE__) == RCC_MSIRANGE_6))
bogdanm	0:9b334a45a8ff	240
bogdanm	0:9b334a45a8ff	241	/**
bogdanm	0:9b334a45a8ff	242	* @}
bogdanm	0:9b334a45a8ff	243	*/
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	/** @defgroup RCC_LSI_Config RCC LSI Config
bogdanm	0:9b334a45a8ff	246	* @{
bogdanm	0:9b334a45a8ff	247	*/
bogdanm	0:9b334a45a8ff	248	#define RCC_LSI_OFF ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	249	#define RCC_LSI_ON ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	250
bogdanm	0:9b334a45a8ff	251	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */
bogdanm	0:9b334a45a8ff	252
bogdanm	0:9b334a45a8ff	253	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
bogdanm	0:9b334a45a8ff	254	/**
bogdanm	0:9b334a45a8ff	255	* @}
bogdanm	0:9b334a45a8ff	256	*/
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258
bogdanm	0:9b334a45a8ff	259	/** @defgroup RCC_MSI_Config RCC MSI Config
bogdanm	0:9b334a45a8ff	260	* @{
bogdanm	0:9b334a45a8ff	261	*/
bogdanm	0:9b334a45a8ff	262	#define RCC_MSI_OFF ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	263	#define RCC_MSI_ON ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	264
bogdanm	0:9b334a45a8ff	265	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
bogdanm	0:9b334a45a8ff	266
bogdanm	0:9b334a45a8ff	267	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
bogdanm	0:9b334a45a8ff	268	/**
bogdanm	0:9b334a45a8ff	269	* @}
bogdanm	0:9b334a45a8ff	270	*/
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	273	/** @defgroup RCC_HSI48_Config
bogdanm	0:9b334a45a8ff	274	* @{
bogdanm	0:9b334a45a8ff	275	*/
bogdanm	0:9b334a45a8ff	276	#define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	277	#define RCC_HSI48_ON ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	278
bogdanm	0:9b334a45a8ff	279	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
bogdanm	0:9b334a45a8ff	280	/**
bogdanm	0:9b334a45a8ff	281	* @}
bogdanm	0:9b334a45a8ff	282	*/
bogdanm	0:9b334a45a8ff	283	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	/** @defgroup RCC_PLL_Config RCC PLL Config
bogdanm	0:9b334a45a8ff	286	* @{
bogdanm	0:9b334a45a8ff	287	*/
bogdanm	0:9b334a45a8ff	288	#define RCC_PLL_NONE ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	289	#define RCC_PLL_OFF ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	290	#define RCC_PLL_ON ((uint8_t)0x02)
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| ((__PLL__) == RCC_PLL_ON))
bogdanm	0:9b334a45a8ff	293	/**
bogdanm	0:9b334a45a8ff	294	* @}
bogdanm	0:9b334a45a8ff	295	*/
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/** @defgroup RCC_PLL_Clock_Source PCC PLL Clock Source
bogdanm	0:9b334a45a8ff	298	* @{
bogdanm	0:9b334a45a8ff	299	*/
bogdanm	0:9b334a45a8ff	300	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
bogdanm	0:9b334a45a8ff	301	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	304	((__SOURCE__) == RCC_PLLSOURCE_HSE))
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/**
bogdanm	0:9b334a45a8ff	307	* @}
bogdanm	0:9b334a45a8ff	308	*/
bogdanm	0:9b334a45a8ff	309
bogdanm	0:9b334a45a8ff	310	/** @defgroup RCC_PLLMultiplication_Factor RCC PLL Multipliers
bogdanm	0:9b334a45a8ff	311	* @{
bogdanm	0:9b334a45a8ff	312	*/
bogdanm	0:9b334a45a8ff	313
bogdanm	0:9b334a45a8ff	314	#define RCC_PLLMUL_3 RCC_CFGR_PLLMUL3
bogdanm	0:9b334a45a8ff	315	#define RCC_PLLMUL_4 RCC_CFGR_PLLMUL4
bogdanm	0:9b334a45a8ff	316	#define RCC_PLLMUL_6 RCC_CFGR_PLLMUL6
bogdanm	0:9b334a45a8ff	317	#define RCC_PLLMUL_8 RCC_CFGR_PLLMUL8
bogdanm	0:9b334a45a8ff	318	#define RCC_PLLMUL_12 RCC_CFGR_PLLMUL12
bogdanm	0:9b334a45a8ff	319	#define RCC_PLLMUL_16 RCC_CFGR_PLLMUL16
bogdanm	0:9b334a45a8ff	320	#define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
bogdanm	0:9b334a45a8ff	321	#define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
bogdanm	0:9b334a45a8ff	322	#define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
bogdanm	0:9b334a45a8ff	323	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) \|\| ((__MUL__) == RCC_PLLMUL_4) \|\| \
bogdanm	0:9b334a45a8ff	324	((__MUL__) == RCC_PLLMUL_6) \|\| ((__MUL__) == RCC_PLLMUL_8) \|\| \
bogdanm	0:9b334a45a8ff	325	((__MUL__) == RCC_PLLMUL_12) \|\| ((__MUL__) == RCC_PLLMUL_16) \|\| \
bogdanm	0:9b334a45a8ff	326	((__MUL__) == RCC_PLLMUL_24) \|\| ((__MUL__) == RCC_PLLMUL_32) \|\| \
bogdanm	0:9b334a45a8ff	327	((__MUL__) == RCC_PLLMUL_48))
bogdanm	0:9b334a45a8ff	328	/**
bogdanm	0:9b334a45a8ff	329	* @}
bogdanm	0:9b334a45a8ff	330	*/
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/** @defgroup RCC_PLLDivider_Factor RCC PLL Dividers
bogdanm	0:9b334a45a8ff	333	* @{
bogdanm	0:9b334a45a8ff	334	*/
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	#define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
bogdanm	0:9b334a45a8ff	337	#define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
bogdanm	0:9b334a45a8ff	338	#define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
bogdanm	0:9b334a45a8ff	339	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) \|\| ((__DIV__) == RCC_PLLDIV_3) \|\| \
bogdanm	0:9b334a45a8ff	340	((__DIV__) == RCC_PLLDIV_4))
bogdanm	0:9b334a45a8ff	341	/**
bogdanm	0:9b334a45a8ff	342	* @}
bogdanm	0:9b334a45a8ff	343	*/
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
bogdanm	0:9b334a45a8ff	346	* @{
bogdanm	0:9b334a45a8ff	347	*/
bogdanm	0:9b334a45a8ff	348	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	349	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	350	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	351	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	352
bogdanm	0:9b334a45a8ff	353	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
bogdanm	0:9b334a45a8ff	354	/**
bogdanm	0:9b334a45a8ff	355	* @}
bogdanm	0:9b334a45a8ff	356	*/
bogdanm	0:9b334a45a8ff	357
bogdanm	0:9b334a45a8ff	358	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
bogdanm	0:9b334a45a8ff	359	* @{
bogdanm	0:9b334a45a8ff	360	*/
bogdanm	0:9b334a45a8ff	361	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
bogdanm	0:9b334a45a8ff	362	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm	0:9b334a45a8ff	363	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm	0:9b334a45a8ff	364	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
bogdanm	0:9b334a45a8ff	365
bogdanm	0:9b334a45a8ff	366	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	367	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	368	((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
bogdanm	0:9b334a45a8ff	369	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm	0:9b334a45a8ff	370	/**
bogdanm	0:9b334a45a8ff	371	* @}
bogdanm	0:9b334a45a8ff	372	*/
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
bogdanm	0:9b334a45a8ff	375	* @{
bogdanm	0:9b334a45a8ff	376	*/
bogdanm	0:9b334a45a8ff	377	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
bogdanm	0:9b334a45a8ff	378	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
bogdanm	0:9b334a45a8ff	379	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	/**
bogdanm	0:9b334a45a8ff	382	* @}
bogdanm	0:9b334a45a8ff	383	*/
bogdanm	0:9b334a45a8ff	384
bogdanm	0:9b334a45a8ff	385	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock SOurce
bogdanm	0:9b334a45a8ff	386	* @{
bogdanm	0:9b334a45a8ff	387	*/
bogdanm	0:9b334a45a8ff	388	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm	0:9b334a45a8ff	389	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm	0:9b334a45a8ff	390	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm	0:9b334a45a8ff	391	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm	0:9b334a45a8ff	392	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm	0:9b334a45a8ff	393	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm	0:9b334a45a8ff	394	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm	0:9b334a45a8ff	395	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm	0:9b334a45a8ff	396	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm	0:9b334a45a8ff	397
bogdanm	0:9b334a45a8ff	398	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	399	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	400	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
bogdanm	0:9b334a45a8ff	401	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
bogdanm	0:9b334a45a8ff	402	((__HCLK__) == RCC_SYSCLK_DIV512))
bogdanm	0:9b334a45a8ff	403	/**
bogdanm	0:9b334a45a8ff	404	* @}
bogdanm	0:9b334a45a8ff	405	*/
bogdanm	0:9b334a45a8ff	406
bogdanm	0:9b334a45a8ff	407	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 Clock Source
bogdanm	0:9b334a45a8ff	408	* @{
bogdanm	0:9b334a45a8ff	409	*/
bogdanm	0:9b334a45a8ff	410	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm	0:9b334a45a8ff	411	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm	0:9b334a45a8ff	412	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm	0:9b334a45a8ff	413	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm	0:9b334a45a8ff	414	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	417	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	418	((__PCLK__) == RCC_HCLK_DIV16))
bogdanm	0:9b334a45a8ff	419	/**
bogdanm	0:9b334a45a8ff	420	* @}
bogdanm	0:9b334a45a8ff	421	*/
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
bogdanm	0:9b334a45a8ff	424	* @{
bogdanm	0:9b334a45a8ff	425	*/
bogdanm	0:9b334a45a8ff	426	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	427	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
bogdanm	0:9b334a45a8ff	428	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
bogdanm	0:9b334a45a8ff	429	#define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
bogdanm	0:9b334a45a8ff	430	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_0)
bogdanm	0:9b334a45a8ff	431	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_1)
bogdanm	0:9b334a45a8ff	432	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE)
bogdanm	0:9b334a45a8ff	433	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	434	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	435	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	436	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	437	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	438	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
bogdanm	0:9b334a45a8ff	439	/**
bogdanm	0:9b334a45a8ff	440	* @}
bogdanm	0:9b334a45a8ff	441	*/
bogdanm	0:9b334a45a8ff	442
bogdanm	0:9b334a45a8ff	443	/** @defgroup RCC_MCO_Clock_Source RCC MCo Clock Source
bogdanm	0:9b334a45a8ff	444	* @{
bogdanm	0:9b334a45a8ff	445	*/
bogdanm	0:9b334a45a8ff	446
bogdanm	0:9b334a45a8ff	447	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
bogdanm	0:9b334a45a8ff	448	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
bogdanm	0:9b334a45a8ff	449	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
bogdanm	0:9b334a45a8ff	450	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
bogdanm	0:9b334a45a8ff	451	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
bogdanm	0:9b334a45a8ff	452	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
bogdanm	0:9b334a45a8ff	453	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
bogdanm	0:9b334a45a8ff	454	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
bogdanm	0:9b334a45a8ff	455	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	456	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
bogdanm	0:9b334a45a8ff	457	#endif
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	460	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	461	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
bogdanm	0:9b334a45a8ff	462	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
bogdanm	0:9b334a45a8ff	463	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	464	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
bogdanm	0:9b334a45a8ff	465	#else
bogdanm	0:9b334a45a8ff	466	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	467	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
bogdanm	0:9b334a45a8ff	468	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
bogdanm	0:9b334a45a8ff	469	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
bogdanm	0:9b334a45a8ff	470	#endif
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	/**
bogdanm	0:9b334a45a8ff	473	* @}
bogdanm	0:9b334a45a8ff	474	*/
bogdanm	0:9b334a45a8ff	475
bogdanm	0:9b334a45a8ff	476	/** @defgroup RCC_MCOPrescaler RCC MCO Prescaler
bogdanm	0:9b334a45a8ff	477	* @{
bogdanm	0:9b334a45a8ff	478	*/
bogdanm	0:9b334a45a8ff	479
bogdanm	0:9b334a45a8ff	480	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
bogdanm	0:9b334a45a8ff	481	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
bogdanm	0:9b334a45a8ff	482	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
bogdanm	0:9b334a45a8ff	483	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
bogdanm	0:9b334a45a8ff	484	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
bogdanm	0:9b334a45a8ff	485
bogdanm	0:9b334a45a8ff	486	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| \
bogdanm	0:9b334a45a8ff	487	((__DIV__) == RCC_MCODIV_2) \|\| \
bogdanm	0:9b334a45a8ff	488	((__DIV__) == RCC_MCODIV_4) \|\| \
bogdanm	0:9b334a45a8ff	489	((__DIV__) == RCC_MCODIV_8) \|\| \
bogdanm	0:9b334a45a8ff	490	((__DIV__) == RCC_MCODIV_16))
bogdanm	0:9b334a45a8ff	491	/**
bogdanm	0:9b334a45a8ff	492	* @}
bogdanm	0:9b334a45a8ff	493	*/
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	/** @defgroup RCC_MCO_Index RCC MCO Index
bogdanm	0:9b334a45a8ff	496	* @{
bogdanm	0:9b334a45a8ff	497	*/
bogdanm	0:9b334a45a8ff	498	#define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	499	#define RCC_MCO2 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	500
bogdanm	0:9b334a45a8ff	501	#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) \|\| ((__MCOx__) == RCC_MCO2))
bogdanm	0:9b334a45a8ff	502	/**
bogdanm	0:9b334a45a8ff	503	* @}
bogdanm	0:9b334a45a8ff	504	*/
bogdanm	0:9b334a45a8ff	505
bogdanm	0:9b334a45a8ff	506	/** @defgroup RCC_Interrupt RCC Interruptions
bogdanm	0:9b334a45a8ff	507	* @{
bogdanm	0:9b334a45a8ff	508	*/
bogdanm	0:9b334a45a8ff	509	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
bogdanm	0:9b334a45a8ff	510	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF
bogdanm	0:9b334a45a8ff	511	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
bogdanm	0:9b334a45a8ff	512	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF
bogdanm	0:9b334a45a8ff	513	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
bogdanm	0:9b334a45a8ff	514	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
bogdanm	0:9b334a45a8ff	515
bogdanm	0:9b334a45a8ff	516	#define RCC_IT_LSECSS RCC_CIFR_LSECSSF
bogdanm	0:9b334a45a8ff	517	#define RCC_IT_CSS RCC_CIFR_CSSF
bogdanm	0:9b334a45a8ff	518	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	519	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
bogdanm	0:9b334a45a8ff	522	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
bogdanm	0:9b334a45a8ff	523	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
bogdanm	0:9b334a45a8ff	524	((__IT__) == RCC_IT_HSI48RDY) \|\| ((__IT__) == RCC_IT_LSECSS))
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
bogdanm	0:9b334a45a8ff	527	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
bogdanm	0:9b334a45a8ff	528	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
bogdanm	0:9b334a45a8ff	529	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_HSI48RDY) \|\| \
bogdanm	0:9b334a45a8ff	530	((__IT__) == RCC_IT_LSECSS))
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
bogdanm	0:9b334a45a8ff	533	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
bogdanm	0:9b334a45a8ff	534	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
bogdanm	0:9b334a45a8ff	535	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_HSI48RDY) \|\| \
bogdanm	0:9b334a45a8ff	536	((__IT__) == RCC_IT_LSECSS))
bogdanm	0:9b334a45a8ff	537	#else
bogdanm	0:9b334a45a8ff	538	#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
bogdanm	0:9b334a45a8ff	539	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
bogdanm	0:9b334a45a8ff	540	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
bogdanm	0:9b334a45a8ff	541	((__IT__) == RCC_IT_LSECSS))
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543	#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
bogdanm	0:9b334a45a8ff	544	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
bogdanm	0:9b334a45a8ff	545	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
bogdanm	0:9b334a45a8ff	546	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_LSECSS))
bogdanm	0:9b334a45a8ff	547
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549	#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
bogdanm	0:9b334a45a8ff	550	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
bogdanm	0:9b334a45a8ff	551	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
bogdanm	0:9b334a45a8ff	552	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_LSECSS))
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm	0:9b334a45a8ff	555	/**
bogdanm	0:9b334a45a8ff	556	* @}
bogdanm	0:9b334a45a8ff	557	*/
bogdanm	0:9b334a45a8ff	558
bogdanm	0:9b334a45a8ff	559	/** @defgroup RCC_Flag
bogdanm	0:9b334a45a8ff	560	* Elements values convention: 0XXYYYYYb
bogdanm	0:9b334a45a8ff	561	* - YYYYY : Flag position in the register
bogdanm	0:9b334a45a8ff	562	* - 0XX : Register index
bogdanm	0:9b334a45a8ff	563	* - 01: CR register
bogdanm	0:9b334a45a8ff	564	* - 10: CSR register
bogdanm	0:9b334a45a8ff	565	* - 11: CRRCR register
bogdanm	0:9b334a45a8ff	566	* @{
bogdanm	0:9b334a45a8ff	567	*/
bogdanm	0:9b334a45a8ff	568	/* Flags in the CR register */
bogdanm	0:9b334a45a8ff	569	#define RCC_FLAG_HSIRDY ((uint8_t)0x22)
bogdanm	0:9b334a45a8ff	570	#define RCC_FLAG_HSIDIV ((uint8_t)0x24)
bogdanm	0:9b334a45a8ff	571	#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
bogdanm	0:9b334a45a8ff	572	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
bogdanm	0:9b334a45a8ff	573	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	/* Flags in the CSR register */
bogdanm	0:9b334a45a8ff	576	#define RCC_FLAG_LSERDY ((uint8_t)0x49)
bogdanm	0:9b334a45a8ff	577	#define RCC_FLAG_LSECSS ((uint8_t)0x4E)
bogdanm	0:9b334a45a8ff	578	#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
bogdanm	0:9b334a45a8ff	579	#define RCC_FLAG_FWRST ((uint8_t)0x58)
bogdanm	0:9b334a45a8ff	580	#define RCC_FLAG_OBLRST ((uint8_t)0x59)
bogdanm	0:9b334a45a8ff	581	#define RCC_FLAG_PINRST ((uint8_t)0x5A)
bogdanm	0:9b334a45a8ff	582	#define RCC_FLAG_PORRST ((uint8_t)0x5B)
bogdanm	0:9b334a45a8ff	583	#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
bogdanm	0:9b334a45a8ff	584	#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
bogdanm	0:9b334a45a8ff	585	#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
bogdanm	0:9b334a45a8ff	586	#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
bogdanm	0:9b334a45a8ff	587
bogdanm	0:9b334a45a8ff	588	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	589	/* Flags in the CRRCR register */
bogdanm	0:9b334a45a8ff	590	#define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
bogdanm	0:9b334a45a8ff	591	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm	0:9b334a45a8ff	592
bogdanm	0:9b334a45a8ff	593	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
bogdanm	0:9b334a45a8ff	594	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	/**
bogdanm	0:9b334a45a8ff	597	* @}
bogdanm	0:9b334a45a8ff	598	*/
bogdanm	0:9b334a45a8ff	599
bogdanm	0:9b334a45a8ff	600	/**
bogdanm	0:9b334a45a8ff	601	* @}
bogdanm	0:9b334a45a8ff	602	*/
bogdanm	0:9b334a45a8ff	603	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	604	/** @defgroup RCC_Exported_Macros RCC Exported Macros
bogdanm	0:9b334a45a8ff	605	* @{
bogdanm	0:9b334a45a8ff	606	*/
bogdanm	0:9b334a45a8ff	607
bogdanm	0:9b334a45a8ff	608	/** @brief Enable or disable the AHB peripheral clock.
bogdanm	0:9b334a45a8ff	609	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	610	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	611	* using it.
bogdanm	0:9b334a45a8ff	612	*/
bogdanm	0:9b334a45a8ff	613	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	614	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	615	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
bogdanm	0:9b334a45a8ff	616	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	617	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
bogdanm	0:9b334a45a8ff	618	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	619	} while(0)
bogdanm	0:9b334a45a8ff	620
bogdanm	0:9b334a45a8ff	621	#define __HAL_RCC_MIF_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	622	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	623	SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
bogdanm	0:9b334a45a8ff	624	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	625	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
bogdanm	0:9b334a45a8ff	626	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	627	} while(0)
bogdanm	0:9b334a45a8ff	628
bogdanm	0:9b334a45a8ff	629	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	630	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	631	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
bogdanm	0:9b334a45a8ff	632	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	633	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
bogdanm	0:9b334a45a8ff	634	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	635	} while(0)
bogdanm	0:9b334a45a8ff	636
bogdanm	0:9b334a45a8ff	637
bogdanm	0:9b334a45a8ff	638	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_DMA1EN))
bogdanm	0:9b334a45a8ff	639	#define __HAL_RCC_MIF_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_MIFEN))
bogdanm	0:9b334a45a8ff	640	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRCEN))
bogdanm	0:9b334a45a8ff	641
bogdanm	0:9b334a45a8ff	642
bogdanm	0:9b334a45a8ff	643	/** @brief Enable or disable the IOPORT peripheral clock.
bogdanm	0:9b334a45a8ff	644	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	645	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	646	* using it.
bogdanm	0:9b334a45a8ff	647	*/
bogdanm	0:9b334a45a8ff	648	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	649	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	650	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
bogdanm	0:9b334a45a8ff	651	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	652	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
bogdanm	0:9b334a45a8ff	653	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	654	} while(0)
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	657	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	658	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
bogdanm	0:9b334a45a8ff	659	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	660	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
bogdanm	0:9b334a45a8ff	661	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	662	} while(0)
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	665	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	666	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
bogdanm	0:9b334a45a8ff	667	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	668	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
bogdanm	0:9b334a45a8ff	669	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	670	} while(0)
bogdanm	0:9b334a45a8ff	671
bogdanm	0:9b334a45a8ff	672	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	673	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	674	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
bogdanm	0:9b334a45a8ff	675	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	676	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
bogdanm	0:9b334a45a8ff	677	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	678	} while(0)
bogdanm	0:9b334a45a8ff	679
bogdanm	0:9b334a45a8ff	680	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	681	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	682	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
bogdanm	0:9b334a45a8ff	683	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	684	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
bogdanm	0:9b334a45a8ff	685	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	686	} while(0)
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688
bogdanm	0:9b334a45a8ff	689	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOAEN))
bogdanm	0:9b334a45a8ff	690	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOBEN))
bogdanm	0:9b334a45a8ff	691	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOCEN))
bogdanm	0:9b334a45a8ff	692	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIODEN))
bogdanm	0:9b334a45a8ff	693	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOHEN))
bogdanm	0:9b334a45a8ff	694
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	0:9b334a45a8ff	697	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	698	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	699	* using it.
bogdanm	0:9b334a45a8ff	700	*/
bogdanm	0:9b334a45a8ff	701	#define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
bogdanm	0:9b334a45a8ff	702	#define __HAL_RCC_PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_WWDGEN))
bogdanm	0:9b334a45a8ff	705	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_PWREN))
bogdanm	0:9b334a45a8ff	706
bogdanm	0:9b334a45a8ff	707	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	0:9b334a45a8ff	708	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	709	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	710	* using it.
bogdanm	0:9b334a45a8ff	711	*/
bogdanm	0:9b334a45a8ff	712	#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
bogdanm	0:9b334a45a8ff	713	#define __HAL_RCC_DBGMCU_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_DBGMCUEN))
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SYSCFGEN))
bogdanm	0:9b334a45a8ff	716	#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_DBGMCUEN))
bogdanm	0:9b334a45a8ff	717
bogdanm	0:9b334a45a8ff	718	/** @brief Force or release AHB peripheral reset.
bogdanm	0:9b334a45a8ff	719	*/
bogdanm	0:9b334a45a8ff	720	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	721	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_DMA1RST))
bogdanm	0:9b334a45a8ff	722	#define __HAL_RCC_MIF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_MIFRST))
bogdanm	0:9b334a45a8ff	723	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRCRST))
bogdanm	0:9b334a45a8ff	724
bogdanm	0:9b334a45a8ff	725	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
bogdanm	0:9b334a45a8ff	726	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRCRST))
bogdanm	0:9b334a45a8ff	727	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_DMA1RST))
bogdanm	0:9b334a45a8ff	728	#define __HAL_RCC_MIF_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_MIFRST))
bogdanm	0:9b334a45a8ff	729
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731	/** @brief Force or release IOPORT peripheral reset.
bogdanm	0:9b334a45a8ff	732	*/
bogdanm	0:9b334a45a8ff	733	#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	734	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOARST))
bogdanm	0:9b334a45a8ff	735	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOBRST))
bogdanm	0:9b334a45a8ff	736	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOCRST))
bogdanm	0:9b334a45a8ff	737	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIODRST))
bogdanm	0:9b334a45a8ff	738	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOHRST))
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
bogdanm	0:9b334a45a8ff	741	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOARST))
bogdanm	0:9b334a45a8ff	742	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOBRST))
bogdanm	0:9b334a45a8ff	743	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOCRST))
bogdanm	0:9b334a45a8ff	744	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIODRST))
bogdanm	0:9b334a45a8ff	745	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOHRST))
bogdanm	0:9b334a45a8ff	746
bogdanm	0:9b334a45a8ff	747	/** @brief Force or release APB1 peripheral reset.
bogdanm	0:9b334a45a8ff	748	*/
bogdanm	0:9b334a45a8ff	749	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	750	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
bogdanm	0:9b334a45a8ff	751	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
bogdanm	0:9b334a45a8ff	752
bogdanm	0:9b334a45a8ff	753	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm	0:9b334a45a8ff	754	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_WWDGRST))
bogdanm	0:9b334a45a8ff	755	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_PWRRST))
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	/** @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	758	*/
bogdanm	0:9b334a45a8ff	759	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	760	#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
bogdanm	0:9b334a45a8ff	761	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm	0:9b334a45a8ff	764	#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_DBGMCURST))
bogdanm	0:9b334a45a8ff	765	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SYSCFGRST))
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	768	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	769	* power consumption.
bogdanm	0:9b334a45a8ff	770	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	771	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	772	*/
bogdanm	0:9b334a45a8ff	773	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_CRCSMEN))
bogdanm	0:9b334a45a8ff	774	#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_MIFSMEN))
bogdanm	0:9b334a45a8ff	775	#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_SRAMSMEN))
bogdanm	0:9b334a45a8ff	776	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_DMA1SMEN))
bogdanm	0:9b334a45a8ff	777
bogdanm	0:9b334a45a8ff	778	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_CRCSMEN))
bogdanm	0:9b334a45a8ff	779	#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_MIFSMEN))
bogdanm	0:9b334a45a8ff	780	#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_SRAMSMEN))
bogdanm	0:9b334a45a8ff	781	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_DMA1SMEN))
bogdanm	0:9b334a45a8ff	782
bogdanm	0:9b334a45a8ff	783	/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	784	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	785	* power consumption.
bogdanm	0:9b334a45a8ff	786	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	787	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	788	*/
bogdanm	0:9b334a45a8ff	789
bogdanm	0:9b334a45a8ff	790	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOASMEN))
bogdanm	0:9b334a45a8ff	791	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOBSMEN))
bogdanm	0:9b334a45a8ff	792	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOCSMEN))
bogdanm	0:9b334a45a8ff	793	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIODSMEN))
bogdanm	0:9b334a45a8ff	794	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOHSMEN))
bogdanm	0:9b334a45a8ff	795
bogdanm	0:9b334a45a8ff	796	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOASMEN))
bogdanm	0:9b334a45a8ff	797	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOBSMEN))
bogdanm	0:9b334a45a8ff	798	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOCSMEN))
bogdanm	0:9b334a45a8ff	799	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIODSMEN))
bogdanm	0:9b334a45a8ff	800	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOHSMEN))
bogdanm	0:9b334a45a8ff	801
bogdanm	0:9b334a45a8ff	802	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	803	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	804	* power consumption.
bogdanm	0:9b334a45a8ff	805	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	806	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	807	*/
bogdanm	0:9b334a45a8ff	808	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_WWDGSMEN))
bogdanm	0:9b334a45a8ff	809	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_PWRSMEN))
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_WWDGSMEN))
bogdanm	0:9b334a45a8ff	812	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_PWRSMEN))
bogdanm	0:9b334a45a8ff	813
bogdanm	0:9b334a45a8ff	814	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	815	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	816	* power consumption.
bogdanm	0:9b334a45a8ff	817	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	818	* @note By default, all peripheral actiated clocks remain enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	819	*/
bogdanm	0:9b334a45a8ff	820	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_SYSCFGSMEN))
bogdanm	0:9b334a45a8ff	821	#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_DBGMCUSMEN))
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SYSCFGSMEN))
bogdanm	0:9b334a45a8ff	824	#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_DBGMCUSMEN))
bogdanm	0:9b334a45a8ff	825
bogdanm	0:9b334a45a8ff	826	/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	0:9b334a45a8ff	827	* @note After enabling the HSI, the application software should wait on
bogdanm	0:9b334a45a8ff	828	* HSIRDY flag to be set indicating that HSI clock is stable and can
bogdanm	0:9b334a45a8ff	829	* be used to clock the PLL and/or system clock.
bogdanm	0:9b334a45a8ff	830	* @note HSI can not be stopped if it is used directly or through the PLL
bogdanm	0:9b334a45a8ff	831	* as system clock. In this case, you have to select another source
bogdanm	0:9b334a45a8ff	832	* of the system clock then stop the HSI.
bogdanm	0:9b334a45a8ff	833	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	834	* @param __STATE__: specifies the new state of the HSI.
bogdanm	0:9b334a45a8ff	835	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	836	* @arg RCC_HSI_OFF: turn OFF the HSI oscillator
bogdanm	0:9b334a45a8ff	837	* @arg RCC_HSI_ON: turn ON the HSI oscillator
bogdanm	0:9b334a45a8ff	838	* @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
bogdanm	0:9b334a45a8ff	839	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm	0:9b334a45a8ff	840	* clock cycles.
bogdanm	0:9b334a45a8ff	841	*/
bogdanm	0:9b334a45a8ff	842	#define __HAL_RCC_HSI_CONFIG(__STATE__) \
bogdanm	0:9b334a45a8ff	843	MODIFY_REG(RCC->CR, RCC_CR_HSION \| RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	0:9b334a45a8ff	846	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	847	* It is used (enabled by hardware) as system clock source after startup
bogdanm	0:9b334a45a8ff	848	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm	0:9b334a45a8ff	849	* of the HSE used directly or indirectly as system clock (if the Clock
bogdanm	0:9b334a45a8ff	850	* Security System CSS is enabled).
bogdanm	0:9b334a45a8ff	851	* @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm	0:9b334a45a8ff	852	* you have to select another source of the system clock then stop the HSI.
bogdanm	0:9b334a45a8ff	853	* @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm	0:9b334a45a8ff	854	* flag to be set indicating that HSI clock is stable and can be used as
bogdanm	0:9b334a45a8ff	855	* system clock source.
bogdanm	0:9b334a45a8ff	856	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm	0:9b334a45a8ff	857	* clock cycles.
bogdanm	0:9b334a45a8ff	858	*/
bogdanm	0:9b334a45a8ff	859	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	860	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	861
bogdanm	0:9b334a45a8ff	862	/**
bogdanm	0:9b334a45a8ff	863	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
bogdanm	0:9b334a45a8ff	864	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	865	* It is used (enabled by hardware) as system clock source after
bogdanm	0:9b334a45a8ff	866	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
bogdanm	0:9b334a45a8ff	867	* of failure of the HSE used directly or indirectly as system clock
bogdanm	0:9b334a45a8ff	868	* (if the Clock Security System CSS is enabled).
bogdanm	0:9b334a45a8ff	869	* @note MSI can not be stopped if it is used as system clock source.
bogdanm	0:9b334a45a8ff	870	* In this case, you have to select another source of the system
bogdanm	0:9b334a45a8ff	871	* clock then stop the MSI.
bogdanm	0:9b334a45a8ff	872	* @note After enabling the MSI, the application software should wait on
bogdanm	0:9b334a45a8ff	873	* MSIRDY flag to be set indicating that MSI clock is stable and can
bogdanm	0:9b334a45a8ff	874	* be used as system clock source.
bogdanm	0:9b334a45a8ff	875	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
bogdanm	0:9b334a45a8ff	876	* clock cycles.
bogdanm	0:9b334a45a8ff	877	*/
bogdanm	0:9b334a45a8ff	878	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
bogdanm	0:9b334a45a8ff	879	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
bogdanm	0:9b334a45a8ff	880
bogdanm	0:9b334a45a8ff	881	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm	0:9b334a45a8ff	882	* @note The calibration is used to compensate for the variations in voltage
bogdanm	0:9b334a45a8ff	883	* and temperature that influence the frequency of the internal HSI RC.
bogdanm	0:9b334a45a8ff	884	* @param __HSICalibrationValue__: specifies the calibration trimming value.
bogdanm	0:9b334a45a8ff	885	* This parameter must be a number between 0 and 0x1F.
bogdanm	0:9b334a45a8ff	886	*/
bogdanm	0:9b334a45a8ff	887	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
bogdanm	0:9b334a45a8ff	888	RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
bogdanm	0:9b334a45a8ff	891	* @note The calibration is used to compensate for the variations in voltage
bogdanm	0:9b334a45a8ff	892	* and temperature that influence the frequency of the internal MSI RC.
bogdanm	0:9b334a45a8ff	893	* Refer to the Application Note AN3300 for more details on how to
bogdanm	0:9b334a45a8ff	894	* calibrate the MSI.
bogdanm	0:9b334a45a8ff	895	* @param __MSICalibrationValue__: specifies the calibration trimming value.
bogdanm	0:9b334a45a8ff	896	* This parameter must be a number between 0 and 0xFF.
bogdanm	0:9b334a45a8ff	897	*/
bogdanm	0:9b334a45a8ff	898	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
bogdanm	0:9b334a45a8ff	899	RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
bogdanm	0:9b334a45a8ff	900
bogdanm	0:9b334a45a8ff	901	/**
bogdanm	0:9b334a45a8ff	902	* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
bogdanm	0:9b334a45a8ff	903	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
bogdanm	0:9b334a45a8ff	904	* around 2.097 MHz. The MSI clock does not change after wake-up from
bogdanm	0:9b334a45a8ff	905	* STOP mode.
bogdanm	0:9b334a45a8ff	906	* @note The MSI clock range can be modified on the fly.
bogdanm	0:9b334a45a8ff	907	* @param RCC_MSIRange: specifies the MSI Clock range.
bogdanm	0:9b334a45a8ff	908	* This parameter must be one of the following values:
bogdanm	0:9b334a45a8ff	909	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
bogdanm	0:9b334a45a8ff	910	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
bogdanm	0:9b334a45a8ff	911	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
bogdanm	0:9b334a45a8ff	912	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
bogdanm	0:9b334a45a8ff	913	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
bogdanm	0:9b334a45a8ff	914	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
bogdanm	0:9b334a45a8ff	915	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
bogdanm	0:9b334a45a8ff	916	*/
bogdanm	0:9b334a45a8ff	917	#define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
bogdanm	0:9b334a45a8ff	918	RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
bogdanm	0:9b334a45a8ff	919
bogdanm	0:9b334a45a8ff	920	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm	0:9b334a45a8ff	921	* @note After enabling the LSI, the application software should wait on
bogdanm	0:9b334a45a8ff	922	* LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm	0:9b334a45a8ff	923	* be used to clock the IWDG and/or the RTC.
bogdanm	0:9b334a45a8ff	924	* @note LSI can not be disabled if the IWDG is running.
bogdanm	0:9b334a45a8ff	925	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm	0:9b334a45a8ff	926	* clock cycles.
bogdanm	0:9b334a45a8ff	927	*/
bogdanm	0:9b334a45a8ff	928	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	929	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	930
bogdanm	0:9b334a45a8ff	931	/**
bogdanm	0:9b334a45a8ff	932	* @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm	0:9b334a45a8ff	933	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	0:9b334a45a8ff	934	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	0:9b334a45a8ff	935	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	0:9b334a45a8ff	936	* @note HSE state can not be changed if it is used directly or through the
bogdanm	0:9b334a45a8ff	937	* PLL as system clock. In this case, you have to select another source
bogdanm	0:9b334a45a8ff	938	* of the system clock then change the HSE state (ex. disable it).
bogdanm	0:9b334a45a8ff	939	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	940	* @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm	0:9b334a45a8ff	941	* was previously enabled you have to enable it again after calling this
bogdanm	0:9b334a45a8ff	942	* function.
bogdanm	0:9b334a45a8ff	943	* @param __STATE__: specifies the new state of the HSE.
bogdanm	0:9b334a45a8ff	944	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	945	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	0:9b334a45a8ff	946	* 6 HSE oscillator clock cycles.
bogdanm	0:9b334a45a8ff	947	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm	0:9b334a45a8ff	948	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm	0:9b334a45a8ff	949	*/
bogdanm	0:9b334a45a8ff	950	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
bogdanm	0:9b334a45a8ff	951	do { \
bogdanm	0:9b334a45a8ff	952	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	953	if((__STATE__) == RCC_HSE_ON) \
bogdanm	0:9b334a45a8ff	954	{ \
bogdanm	0:9b334a45a8ff	955	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	956	SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	957	} \
bogdanm	0:9b334a45a8ff	958	else if((__STATE__) == RCC_HSE_BYPASS) \
bogdanm	0:9b334a45a8ff	959	{ \
bogdanm	0:9b334a45a8ff	960	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	961	SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	962	} \
bogdanm	0:9b334a45a8ff	963	else \
bogdanm	0:9b334a45a8ff	964	{ \
bogdanm	0:9b334a45a8ff	965	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	966	} \
bogdanm	0:9b334a45a8ff	967	} while(0)
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	/**
bogdanm	0:9b334a45a8ff	970	* @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm	0:9b334a45a8ff	971	* @note As the LSE is in the Backup domain and write access is denied to
bogdanm	0:9b334a45a8ff	972	* this domain after reset, you have to enable write access using
bogdanm	0:9b334a45a8ff	973	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm	0:9b334a45a8ff	974	* (to be done once after reset).
bogdanm	0:9b334a45a8ff	975	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm	0:9b334a45a8ff	976	* software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm	0:9b334a45a8ff	977	* is stable and can be used to clock the RTC.
bogdanm	0:9b334a45a8ff	978	* @param __STATE__: specifies the new state of the LSE.
bogdanm	0:9b334a45a8ff	979	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	980	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm	0:9b334a45a8ff	981	* 6 LSE oscillator clock cycles.
bogdanm	0:9b334a45a8ff	982	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm	0:9b334a45a8ff	983	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm	0:9b334a45a8ff	984	*/
bogdanm	0:9b334a45a8ff	985	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
bogdanm	0:9b334a45a8ff	986	do { \
bogdanm	0:9b334a45a8ff	987	if((__STATE__) == RCC_LSE_ON) \
bogdanm	0:9b334a45a8ff	988	{ \
bogdanm	0:9b334a45a8ff	989	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
bogdanm	0:9b334a45a8ff	990	} \
bogdanm	0:9b334a45a8ff	991	else if((__STATE__) == RCC_LSE_OFF) \
bogdanm	0:9b334a45a8ff	992	{ \
bogdanm	0:9b334a45a8ff	993	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
bogdanm	0:9b334a45a8ff	994	} \
bogdanm	0:9b334a45a8ff	995	else if((__STATE__) == RCC_LSE_BYPASS) \
bogdanm	0:9b334a45a8ff	996	{ \
bogdanm	0:9b334a45a8ff	997	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
bogdanm	0:9b334a45a8ff	998	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
bogdanm	0:9b334a45a8ff	999	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
bogdanm	0:9b334a45a8ff	1000	} \
bogdanm	0:9b334a45a8ff	1001	else \
bogdanm	0:9b334a45a8ff	1002	{ \
bogdanm	0:9b334a45a8ff	1003	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
bogdanm	0:9b334a45a8ff	1004	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
bogdanm	0:9b334a45a8ff	1005	} \
bogdanm	0:9b334a45a8ff	1006	} while(0)
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008	/** @brief Macros to enable or disable the the RTC clock.
bogdanm	0:9b334a45a8ff	1009	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	0:9b334a45a8ff	1010	*/
bogdanm	0:9b334a45a8ff	1011	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
bogdanm	0:9b334a45a8ff	1012	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/**
bogdanm	0:9b334a45a8ff	1015	* @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
bogdanm	0:9b334a45a8ff	1016	* @note As the RTC clock configuration bits are in the RTC domain and write
bogdanm	0:9b334a45a8ff	1017	* access is denied to this domain after reset, you have to enable write
bogdanm	0:9b334a45a8ff	1018	* access using PWR_RTCAccessCmd(ENABLE) function before to configure
bogdanm	0:9b334a45a8ff	1019	* the RTC clock source (to be done once after reset).
bogdanm	0:9b334a45a8ff	1020	* @note Once the RTC clock is configured it cannot be changed unless the RTC
bogdanm	0:9b334a45a8ff	1021	* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
bogdanm	0:9b334a45a8ff	1022	* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
bogdanm	0:9b334a45a8ff	1023	*
bogdanm	0:9b334a45a8ff	1024	* @param RCC_RTCCLKSource: specifies the RTC clock source.
bogdanm	0:9b334a45a8ff	1025	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1026	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm	0:9b334a45a8ff	1027	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm	0:9b334a45a8ff	1028	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
bogdanm	0:9b334a45a8ff	1029	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
bogdanm	0:9b334a45a8ff	1030	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
bogdanm	0:9b334a45a8ff	1031	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
bogdanm	0:9b334a45a8ff	1032	*
bogdanm	0:9b334a45a8ff	1033	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm	0:9b334a45a8ff	1034	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	0:9b334a45a8ff	1035	* However, when the HSE clock is used as RTC clock source, the RTC
bogdanm	0:9b334a45a8ff	1036	* cannot be used in STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1037	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm	0:9b334a45a8ff	1038	* RTC clock source).
bogdanm	0:9b334a45a8ff	1039	*/
bogdanm	0:9b334a45a8ff	1040	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
bogdanm	0:9b334a45a8ff	1041	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTCCLKSource__) & 0xFFFCFFFF)) : CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
bogdanm	0:9b334a45a8ff	1044	MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)(__RTCCLKSource__)); \
bogdanm	0:9b334a45a8ff	1045	} while (0)
bogdanm	0:9b334a45a8ff	1046
bogdanm	0:9b334a45a8ff	1047	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	/** @brief Macros to force or release the Backup domain reset.
bogdanm	0:9b334a45a8ff	1050	* @note This function resets the RTC peripheral (including the backup registers)
bogdanm	0:9b334a45a8ff	1051	* and the RTC clock source selection in RCC_CSR register.
bogdanm	0:9b334a45a8ff	1052	* @note The BKPSRAM is not affected by this reset.
bogdanm	0:9b334a45a8ff	1053	*/
bogdanm	0:9b334a45a8ff	1054	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
bogdanm	0:9b334a45a8ff	1055	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	/** @brief Macros to enable or disable the main PLL.
bogdanm	0:9b334a45a8ff	1058	* @note After enabling the main PLL, the application software should wait on
bogdanm	0:9b334a45a8ff	1059	* PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm	0:9b334a45a8ff	1060	* be used as system clock source.
bogdanm	0:9b334a45a8ff	1061	* @note The main PLL can not be disabled if it is used as system clock source
bogdanm	0:9b334a45a8ff	1062	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1063	*/
bogdanm	0:9b334a45a8ff	1064	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	1065	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	1066
bogdanm	0:9b334a45a8ff	1067	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
bogdanm	0:9b334a45a8ff	1068	* @note This function must be used only when the main PLL is disabled.
bogdanm	0:9b334a45a8ff	1069	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm	0:9b334a45a8ff	1070	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1071	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	1072	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	1073	* @param __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
bogdanm	0:9b334a45a8ff	1074	* This parameter must be one of the following values:
bogdanm	0:9b334a45a8ff	1075	* @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
bogdanm	0:9b334a45a8ff	1076	* @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
bogdanm	0:9b334a45a8ff	1077	* @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
bogdanm	0:9b334a45a8ff	1078	* @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
bogdanm	0:9b334a45a8ff	1079	* @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
bogdanm	0:9b334a45a8ff	1080	* @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
bogdanm	0:9b334a45a8ff	1081	* @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
bogdanm	0:9b334a45a8ff	1082	* @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
bogdanm	0:9b334a45a8ff	1083	* @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
bogdanm	0:9b334a45a8ff	1084	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
bogdanm	0:9b334a45a8ff	1085	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
bogdanm	0:9b334a45a8ff	1086	* in Range 3.
bogdanm	0:9b334a45a8ff	1087	* @param __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
bogdanm	0:9b334a45a8ff	1088	* This parameter must be one of the following values:
bogdanm	0:9b334a45a8ff	1089	* @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
bogdanm	0:9b334a45a8ff	1090	* @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
bogdanm	0:9b334a45a8ff	1091	* @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
bogdanm	0:9b334a45a8ff	1092	*/
bogdanm	0:9b334a45a8ff	1093
bogdanm	0:9b334a45a8ff	1094	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__ ,__PLLDIV__ ) \
bogdanm	0:9b334a45a8ff	1095	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\| (__PLLDIV__)\| (__RCC_PLLSource__)))
bogdanm	0:9b334a45a8ff	1096
bogdanm	0:9b334a45a8ff	1097	/** @brief Macro to get the clock source used as system clock.
bogdanm	0:9b334a45a8ff	1098	* @retval The clock source used as system clock. The returned value can be one
bogdanm	0:9b334a45a8ff	1099	* of the following:
bogdanm	0:9b334a45a8ff	1100	* - RCC_CFGR_SWS_HSI: HSI used as system clock.
bogdanm	0:9b334a45a8ff	1101	* - RCC_CFGR_SWS_HSE: HSE used as system clock.
bogdanm	0:9b334a45a8ff	1102	* - RCC_CFGR_SWS_PLL: PLL used as system clock.
bogdanm	0:9b334a45a8ff	1103	*/
bogdanm	0:9b334a45a8ff	1104	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
bogdanm	0:9b334a45a8ff	1105
bogdanm	0:9b334a45a8ff	1106	/** @brief Macro to get the oscillator used as PLL clock source.
bogdanm	0:9b334a45a8ff	1107	* @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm	0:9b334a45a8ff	1108	* of the following:
bogdanm	0:9b334a45a8ff	1109	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm	0:9b334a45a8ff	1110	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm	0:9b334a45a8ff	1111	*/
bogdanm	0:9b334a45a8ff	1112	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
bogdanm	0:9b334a45a8ff	1113
bogdanm	0:9b334a45a8ff	1114	/** @defgroup RCC_Flags_Interrupts_Management
bogdanm	0:9b334a45a8ff	1115	* @brief macros to manage the specified RCC Flags and interrupts.
bogdanm	0:9b334a45a8ff	1116	* @{
bogdanm	0:9b334a45a8ff	1117	*/
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
bogdanm	0:9b334a45a8ff	1120	* the selected interrupts).
bogdanm	0:9b334a45a8ff	1121	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
bogdanm	0:9b334a45a8ff	1122	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
bogdanm	0:9b334a45a8ff	1123	* automatically generated. The NMI will be executed indefinitely, and
bogdanm	0:9b334a45a8ff	1124	* since NMI has higher priority than any other IRQ (and main program)
bogdanm	0:9b334a45a8ff	1125	* the application will be stacked in the NMI ISR unless the CSS interrupt
bogdanm	0:9b334a45a8ff	1126	* pending bit is cleared.
bogdanm	0:9b334a45a8ff	1127	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm	0:9b334a45a8ff	1128	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1129	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1130	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1131	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1132	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1133	* @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm	0:9b334a45a8ff	1134	* @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm	0:9b334a45a8ff	1135	* @arg RCC_IT_LSECSS: LSE CSS interrupt
bogdanm	0:9b334a45a8ff	1136	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
bogdanm	0:9b334a45a8ff	1137	*/
bogdanm	0:9b334a45a8ff	1138	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (RCC->CIER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1139
bogdanm	0:9b334a45a8ff	1140	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
bogdanm	0:9b334a45a8ff	1141	* the selected interrupts).
bogdanm	0:9b334a45a8ff	1142	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
bogdanm	0:9b334a45a8ff	1143	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
bogdanm	0:9b334a45a8ff	1144	* automatically generated. The NMI will be executed indefinitely, and
bogdanm	0:9b334a45a8ff	1145	* since NMI has higher priority than any other IRQ (and main program)
bogdanm	0:9b334a45a8ff	1146	* the application will be stacked in the NMI ISR unless the CSS interrupt
bogdanm	0:9b334a45a8ff	1147	* pending bit is cleared.
bogdanm	0:9b334a45a8ff	1148	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm	0:9b334a45a8ff	1149	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1150	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1151	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1152	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1153	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1154	* @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm	0:9b334a45a8ff	1155	* @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm	0:9b334a45a8ff	1156	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
bogdanm	0:9b334a45a8ff	1157	* @arg RCC_IT_LSECSS: LSE CSS interrupt
bogdanm	0:9b334a45a8ff	1158
bogdanm	0:9b334a45a8ff	1159	*/
bogdanm	0:9b334a45a8ff	1160	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (RCC->CIER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1161
bogdanm	0:9b334a45a8ff	1162	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm	0:9b334a45a8ff	1163	* bits to clear the selected interrupt pending bits.
bogdanm	0:9b334a45a8ff	1164	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	1165	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1166	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1167	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1168	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1169	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1170	* @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm	0:9b334a45a8ff	1171	* @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm	0:9b334a45a8ff	1172	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
bogdanm	0:9b334a45a8ff	1173	* @arg RCC_IT_LSECSS: LSE CSS interrupt
bogdanm	0:9b334a45a8ff	1174	* @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm	0:9b334a45a8ff	1175	*/
bogdanm	0:9b334a45a8ff	1176	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	/** @brief Check the RCC's interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	1179	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm	0:9b334a45a8ff	1180	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1181	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1182	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1183	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1184	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1185	* @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm	0:9b334a45a8ff	1186	* @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm	0:9b334a45a8ff	1187	* @arg RCC_IT_LSECSS: LSE CSS interrupt
bogdanm	0:9b334a45a8ff	1188	* @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm	0:9b334a45a8ff	1189	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1190	*/
bogdanm	0:9b334a45a8ff	1191	#define __HAL_RCC_GET_IT_SOURCE(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	/** @brief Set RMVF bit to clear the reset flags.
bogdanm	0:9b334a45a8ff	1194	* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
bogdanm	0:9b334a45a8ff	1195	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
bogdanm	0:9b334a45a8ff	1196	*/
bogdanm	0:9b334a45a8ff	1197	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	/** @brief Check RCC flag is set or not.
bogdanm	0:9b334a45a8ff	1200	* @param __FLAG__: specifies the flag to check.
bogdanm	0:9b334a45a8ff	1201	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1202	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
bogdanm	0:9b334a45a8ff	1203	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
bogdanm	0:9b334a45a8ff	1204	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
bogdanm	0:9b334a45a8ff	1205	* @arg RCC_FLAG_PLLRDY: PLL clock ready
bogdanm	0:9b334a45a8ff	1206	* @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
bogdanm	0:9b334a45a8ff	1207	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
bogdanm	0:9b334a45a8ff	1208	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
bogdanm	0:9b334a45a8ff	1209	* @arg RCC_FLAG_FWRST: Firewall reset
bogdanm	0:9b334a45a8ff	1210	* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
bogdanm	0:9b334a45a8ff	1211	* @arg RCC_FLAG_PINRST: Pin reset
bogdanm	0:9b334a45a8ff	1212	* @arg RCC_FLAG_PORRST: POR/PDR reset
bogdanm	0:9b334a45a8ff	1213	* @arg RCC_FLAG_SFTRST: Software reset
bogdanm	0:9b334a45a8ff	1214	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
bogdanm	0:9b334a45a8ff	1215	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
bogdanm	0:9b334a45a8ff	1216	* @arg RCC_FLAG_LPWRRST: Low Power reset
bogdanm	0:9b334a45a8ff	1217	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1218	*/
bogdanm	0:9b334a45a8ff	1219	#define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm	0:9b334a45a8ff	1220	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
bogdanm	0:9b334a45a8ff	1221	RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
bogdanm	0:9b334a45a8ff	1222
bogdanm	0:9b334a45a8ff	1223	/**
bogdanm	0:9b334a45a8ff	1224	* @}
bogdanm	0:9b334a45a8ff	1225	*/
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	/**
bogdanm	0:9b334a45a8ff	1228	* @}
bogdanm	0:9b334a45a8ff	1229	*/
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231	/* Include RCC HAL Extension module */
bogdanm	0:9b334a45a8ff	1232	#include "stm32l0xx_hal_rcc_ex.h"
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/** @defgroup RCC_Exported_Functions RCC Exported Functions
bogdanm	0:9b334a45a8ff	1235	* @{
bogdanm	0:9b334a45a8ff	1236	*/
bogdanm	0:9b334a45a8ff	1237
bogdanm	0:9b334a45a8ff	1238	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	1239	* @{
bogdanm	0:9b334a45a8ff	1240	*/
bogdanm	0:9b334a45a8ff	1241	void HAL_RCC_DeInit(void);
bogdanm	0:9b334a45a8ff	1242	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	1243	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	0:9b334a45a8ff	1244	/**
bogdanm	0:9b334a45a8ff	1245	* @}
bogdanm	0:9b334a45a8ff	1246	*/
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1249	* @{
bogdanm	0:9b334a45a8ff	1250	*/
bogdanm	0:9b334a45a8ff	1251	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm	0:9b334a45a8ff	1252	void HAL_RCC_EnableCSS(void);
bogdanm	0:9b334a45a8ff	1253	uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm	0:9b334a45a8ff	1254	uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm	0:9b334a45a8ff	1255	uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm	0:9b334a45a8ff	1256	uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm	0:9b334a45a8ff	1257	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	1258	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	0:9b334a45a8ff	1259	/* CSS NMI IRQ handler */
bogdanm	0:9b334a45a8ff	1260	void HAL_RCC_NMI_IRQHandler(void);
bogdanm	0:9b334a45a8ff	1261
bogdanm	0:9b334a45a8ff	1262	/* User Callbacks in non blocking mode (IT mode) */
bogdanm	0:9b334a45a8ff	1263	void HAL_RCC_CSSCallback(void);
bogdanm	0:9b334a45a8ff	1264	/**
bogdanm	0:9b334a45a8ff	1265	* @}
bogdanm	0:9b334a45a8ff	1266	*/
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	/**
bogdanm	0:9b334a45a8ff	1269	* @}
bogdanm	0:9b334a45a8ff	1270	*/
bogdanm	0:9b334a45a8ff	1271
bogdanm	0:9b334a45a8ff	1272	/**
bogdanm	0:9b334a45a8ff	1273	* @}
bogdanm	0:9b334a45a8ff	1274	*/
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	/**
bogdanm	0:9b334a45a8ff	1277	* @}
bogdanm	0:9b334a45a8ff	1278	*/
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1281	}
bogdanm	0:9b334a45a8ff	1282	#endif
bogdanm	0:9b334a45a8ff	1283
bogdanm	0:9b334a45a8ff	1284	#endif /* __STM32l0xx_HAL_RCC_H */
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	1287

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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