mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 124:6a4a5b7d7324

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f1xx_hal_adc.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	124:6a4a5b7d7324	5	* @version V1.0.4
mbed_official	124:6a4a5b7d7324	6	* @date 29-April-2016
bogdanm	0:9b334a45a8ff	7	* @brief This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	8	* functionalities of the Analog to Digital Convertor (ADC)
bogdanm	0:9b334a45a8ff	9	* peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* ++ Initialization and Configuration of ADC
bogdanm	0:9b334a45a8ff	12	* + Operation functions
bogdanm	0:9b334a45a8ff	13	* ++ Start, stop, get result of conversions of regular
bogdanm	0:9b334a45a8ff	14	* group, using 3 possible modes: polling, interruption or DMA.
bogdanm	0:9b334a45a8ff	15	* + Control functions
bogdanm	0:9b334a45a8ff	16	* ++ Channels configuration on regular group
bogdanm	0:9b334a45a8ff	17	* ++ Channels configuration on injected group
bogdanm	0:9b334a45a8ff	18	* ++ Analog Watchdog configuration
bogdanm	0:9b334a45a8ff	19	* + State functions
bogdanm	0:9b334a45a8ff	20	* ++ ADC state machine management
bogdanm	0:9b334a45a8ff	21	* ++ Interrupts and flags management
bogdanm	0:9b334a45a8ff	22	* Other functions (extended functions) are available in file
bogdanm	0:9b334a45a8ff	23	* "stm32f1xx_hal_adc_ex.c".
bogdanm	0:9b334a45a8ff	24	*
bogdanm	0:9b334a45a8ff	25	@verbatim
bogdanm	0:9b334a45a8ff	26	==============================================================================
mbed_official	124:6a4a5b7d7324	27	##### ADC peripheral features #####
bogdanm	0:9b334a45a8ff	28	==============================================================================
mbed_official	124:6a4a5b7d7324	29	[..]
bogdanm	0:9b334a45a8ff	30	(+) 12-bit resolution
bogdanm	0:9b334a45a8ff	31
bogdanm	0:9b334a45a8ff	32	(+) Interrupt generation at the end of regular conversion, end of injected
bogdanm	0:9b334a45a8ff	33	conversion, and in case of analog watchdog or overrun events.
bogdanm	0:9b334a45a8ff	34
bogdanm	0:9b334a45a8ff	35	(+) Single and continuous conversion modes.
bogdanm	0:9b334a45a8ff	36
mbed_official	124:6a4a5b7d7324	37	(+) Scan mode for conversion of several channels sequentially.
bogdanm	0:9b334a45a8ff	38
bogdanm	0:9b334a45a8ff	39	(+) Data alignment with in-built data coherency.
bogdanm	0:9b334a45a8ff	40
mbed_official	124:6a4a5b7d7324	41	(+) Programmable sampling time (channel wise)
bogdanm	0:9b334a45a8ff	42
mbed_official	124:6a4a5b7d7324	43	(+) ADC conversion of regular group and injected group.
bogdanm	0:9b334a45a8ff	44
mbed_official	124:6a4a5b7d7324	45	(+) External trigger (timer or EXTI)
mbed_official	124:6a4a5b7d7324	46	for both regular and injected groups.
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	(+) DMA request generation for transfer of conversions data of regular group.
bogdanm	0:9b334a45a8ff	49
bogdanm	0:9b334a45a8ff	50	(+) Multimode Dual mode (available on devices with 2 ADCs or more).
bogdanm	0:9b334a45a8ff	51
bogdanm	0:9b334a45a8ff	52	(+) Configurable DMA data storage in Multimode Dual mode (available on devices
bogdanm	0:9b334a45a8ff	53	with 2 DCs or more).
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	(+) Configurable delay between conversions in Dual interleaved mode (available
bogdanm	0:9b334a45a8ff	56	on devices with 2 DCs or more).
bogdanm	0:9b334a45a8ff	57
bogdanm	0:9b334a45a8ff	58	(+) ADC calibration
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	(+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
bogdanm	0:9b334a45a8ff	61	slower speed.
bogdanm	0:9b334a45a8ff	62
bogdanm	0:9b334a45a8ff	63	(+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
bogdanm	0:9b334a45a8ff	64	Vdda or to an external voltage reference).
bogdanm	0:9b334a45a8ff	65
bogdanm	0:9b334a45a8ff	66
mbed_official	124:6a4a5b7d7324	67	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	68	==============================================================================
bogdanm	0:9b334a45a8ff	69	[..]
bogdanm	0:9b334a45a8ff	70
bogdanm	0:9b334a45a8ff	71	* Configuration of top level parameters related to ADC *
bogdanm	0:9b334a45a8ff	72	============================================================
bogdanm	0:9b334a45a8ff	73	[..]
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75	(#) Enable the ADC interface
bogdanm	0:9b334a45a8ff	76	(++) As prerequisite, ADC clock must be configured at RCC top level.
bogdanm	0:9b334a45a8ff	77	Caution: On STM32F1, ADC clock frequency max is 14MHz (refer
bogdanm	0:9b334a45a8ff	78	to device datasheet).
bogdanm	0:9b334a45a8ff	79	Therefore, ADC clock prescaler must be configured in
mbed_official	124:6a4a5b7d7324	80	function of ADC clock source frequency to remain below
mbed_official	124:6a4a5b7d7324	81	this maximum frequency.
mbed_official	124:6a4a5b7d7324	82	(++) One clock setting is mandatory:
mbed_official	124:6a4a5b7d7324	83	ADC clock (core clock, also possibly conversion clock).
bogdanm	0:9b334a45a8ff	84	(+++) Example:
bogdanm	0:9b334a45a8ff	85	Into HAL_ADC_MspInit() (recommended code location) or with
bogdanm	0:9b334a45a8ff	86	other device clock parameters configuration:
bogdanm	0:9b334a45a8ff	87	(+++) RCC_PeriphCLKInitTypeDef PeriphClkInit;
bogdanm	0:9b334a45a8ff	88	(+++) __ADC1_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	89	(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
bogdanm	0:9b334a45a8ff	90	(+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
bogdanm	0:9b334a45a8ff	91	(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	(#) ADC pins configuration
bogdanm	0:9b334a45a8ff	94	(++) Enable the clock for the ADC GPIOs
bogdanm	0:9b334a45a8ff	95	using macro __HAL_RCC_GPIOx_CLK_ENABLE()
bogdanm	0:9b334a45a8ff	96	(++) Configure these ADC pins in analog mode
bogdanm	0:9b334a45a8ff	97	using function HAL_GPIO_Init()
mbed_official	124:6a4a5b7d7324	98
bogdanm	0:9b334a45a8ff	99	(#) Optionally, in case of usage of ADC with interruptions:
bogdanm	0:9b334a45a8ff	100	(++) Configure the NVIC for ADC
bogdanm	0:9b334a45a8ff	101	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
bogdanm	0:9b334a45a8ff	102	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
bogdanm	0:9b334a45a8ff	103	into the function of corresponding ADC interruption vector
bogdanm	0:9b334a45a8ff	104	ADCx_IRQHandler().
bogdanm	0:9b334a45a8ff	105
bogdanm	0:9b334a45a8ff	106	(#) Optionally, in case of usage of DMA:
bogdanm	0:9b334a45a8ff	107	(++) Configure the DMA (DMA channel, mode normal or circular, ...)
bogdanm	0:9b334a45a8ff	108	using function HAL_DMA_Init().
bogdanm	0:9b334a45a8ff	109	(++) Configure the NVIC for DMA
bogdanm	0:9b334a45a8ff	110	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
bogdanm	0:9b334a45a8ff	111	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
bogdanm	0:9b334a45a8ff	112	into the function of corresponding DMA interruption vector
bogdanm	0:9b334a45a8ff	113	DMAx_Channelx_IRQHandler().
mbed_official	124:6a4a5b7d7324	114
bogdanm	0:9b334a45a8ff	115	* Configuration of ADC, groups regular/injected, channels parameters *
bogdanm	0:9b334a45a8ff	116	==========================================================================
bogdanm	0:9b334a45a8ff	117	[..]
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	(#) Configure the ADC parameters (resolution, data alignment, ...)
mbed_official	124:6a4a5b7d7324	120	and regular group parameters (conversion trigger, sequencer, ...)
bogdanm	0:9b334a45a8ff	121	using function HAL_ADC_Init().
bogdanm	0:9b334a45a8ff	122
bogdanm	0:9b334a45a8ff	123	(#) Configure the channels for regular group parameters (channel number,
bogdanm	0:9b334a45a8ff	124	channel rank into sequencer, ..., into regular group)
bogdanm	0:9b334a45a8ff	125	using function HAL_ADC_ConfigChannel().
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127	(#) Optionally, configure the injected group parameters (conversion trigger,
bogdanm	0:9b334a45a8ff	128	sequencer, ..., of injected group)
bogdanm	0:9b334a45a8ff	129	and the channels for injected group parameters (channel number,
bogdanm	0:9b334a45a8ff	130	channel rank into sequencer, ..., into injected group)
bogdanm	0:9b334a45a8ff	131	using function HAL_ADCEx_InjectedConfigChannel().
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	(#) Optionally, configure the analog watchdog parameters (channels
bogdanm	0:9b334a45a8ff	134	monitored, thresholds, ...)
bogdanm	0:9b334a45a8ff	135	using function HAL_ADC_AnalogWDGConfig().
bogdanm	0:9b334a45a8ff	136
bogdanm	0:9b334a45a8ff	137	(#) Optionally, for devices with several ADC instances: configure the
bogdanm	0:9b334a45a8ff	138	multimode parameters
bogdanm	0:9b334a45a8ff	139	using function HAL_ADCEx_MultiModeConfigChannel().
bogdanm	0:9b334a45a8ff	140
bogdanm	0:9b334a45a8ff	141	* Execution of ADC conversions *
bogdanm	0:9b334a45a8ff	142	====================================
bogdanm	0:9b334a45a8ff	143	[..]
bogdanm	0:9b334a45a8ff	144
bogdanm	0:9b334a45a8ff	145	(#) Optionally, perform an automatic ADC calibration to improve the
bogdanm	0:9b334a45a8ff	146	conversion accuracy
bogdanm	0:9b334a45a8ff	147	using function HAL_ADCEx_Calibration_Start().
bogdanm	0:9b334a45a8ff	148
bogdanm	0:9b334a45a8ff	149	(#) ADC driver can be used among three modes: polling, interruption,
bogdanm	0:9b334a45a8ff	150	transfer by DMA.
bogdanm	0:9b334a45a8ff	151
bogdanm	0:9b334a45a8ff	152	(++) ADC conversion by polling:
bogdanm	0:9b334a45a8ff	153	(+++) Activate the ADC peripheral and start conversions
bogdanm	0:9b334a45a8ff	154	using function HAL_ADC_Start()
bogdanm	0:9b334a45a8ff	155	(+++) Wait for ADC conversion completion
bogdanm	0:9b334a45a8ff	156	using function HAL_ADC_PollForConversion()
bogdanm	0:9b334a45a8ff	157	(or for injected group: HAL_ADCEx_InjectedPollForConversion() )
bogdanm	0:9b334a45a8ff	158	(+++) Retrieve conversion results
bogdanm	0:9b334a45a8ff	159	using function HAL_ADC_GetValue()
bogdanm	0:9b334a45a8ff	160	(or for injected group: HAL_ADCEx_InjectedGetValue() )
bogdanm	0:9b334a45a8ff	161	(+++) Stop conversion and disable the ADC peripheral
bogdanm	0:9b334a45a8ff	162	using function HAL_ADC_Stop()
bogdanm	0:9b334a45a8ff	163
bogdanm	0:9b334a45a8ff	164	(++) ADC conversion by interruption:
bogdanm	0:9b334a45a8ff	165	(+++) Activate the ADC peripheral and start conversions
bogdanm	0:9b334a45a8ff	166	using function HAL_ADC_Start_IT()
bogdanm	0:9b334a45a8ff	167	(+++) Wait for ADC conversion completion by call of function
bogdanm	0:9b334a45a8ff	168	HAL_ADC_ConvCpltCallback()
bogdanm	0:9b334a45a8ff	169	(this function must be implemented in user program)
bogdanm	0:9b334a45a8ff	170	(or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
bogdanm	0:9b334a45a8ff	171	(+++) Retrieve conversion results
bogdanm	0:9b334a45a8ff	172	using function HAL_ADC_GetValue()
bogdanm	0:9b334a45a8ff	173	(or for injected group: HAL_ADCEx_InjectedGetValue() )
bogdanm	0:9b334a45a8ff	174	(+++) Stop conversion and disable the ADC peripheral
bogdanm	0:9b334a45a8ff	175	using function HAL_ADC_Stop_IT()
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	(++) ADC conversion with transfer by DMA:
bogdanm	0:9b334a45a8ff	178	(+++) Activate the ADC peripheral and start conversions
bogdanm	0:9b334a45a8ff	179	using function HAL_ADC_Start_DMA()
bogdanm	0:9b334a45a8ff	180	(+++) Wait for ADC conversion completion by call of function
bogdanm	0:9b334a45a8ff	181	HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
bogdanm	0:9b334a45a8ff	182	(these functions must be implemented in user program)
bogdanm	0:9b334a45a8ff	183	(+++) Conversion results are automatically transferred by DMA into
bogdanm	0:9b334a45a8ff	184	destination variable address.
bogdanm	0:9b334a45a8ff	185	(+++) Stop conversion and disable the ADC peripheral
bogdanm	0:9b334a45a8ff	186	using function HAL_ADC_Stop_DMA()
bogdanm	0:9b334a45a8ff	187
bogdanm	0:9b334a45a8ff	188	(++) For devices with several ADCs: ADC multimode conversion
bogdanm	0:9b334a45a8ff	189	with transfer by DMA:
bogdanm	0:9b334a45a8ff	190	(+++) Activate the ADC peripheral (slave) and start conversions
bogdanm	0:9b334a45a8ff	191	using function HAL_ADC_Start()
bogdanm	0:9b334a45a8ff	192	(+++) Activate the ADC peripheral (master) and start conversions
bogdanm	0:9b334a45a8ff	193	using function HAL_ADCEx_MultiModeStart_DMA()
bogdanm	0:9b334a45a8ff	194	(+++) Wait for ADC conversion completion by call of function
bogdanm	0:9b334a45a8ff	195	HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
bogdanm	0:9b334a45a8ff	196	(these functions must be implemented in user program)
bogdanm	0:9b334a45a8ff	197	(+++) Conversion results are automatically transferred by DMA into
bogdanm	0:9b334a45a8ff	198	destination variable address.
bogdanm	0:9b334a45a8ff	199	(+++) Stop conversion and disable the ADC peripheral (master)
bogdanm	0:9b334a45a8ff	200	using function HAL_ADCEx_MultiModeStop_DMA()
bogdanm	0:9b334a45a8ff	201	(+++) Stop conversion and disable the ADC peripheral (slave)
bogdanm	0:9b334a45a8ff	202	using function HAL_ADC_Stop_IT()
bogdanm	0:9b334a45a8ff	203
bogdanm	0:9b334a45a8ff	204	[..]
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	(@) Callback functions must be implemented in user program:
bogdanm	0:9b334a45a8ff	207	(+@) HAL_ADC_ErrorCallback()
bogdanm	0:9b334a45a8ff	208	(+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
bogdanm	0:9b334a45a8ff	209	(+@) HAL_ADC_ConvCpltCallback()
bogdanm	0:9b334a45a8ff	210	(+@) HAL_ADC_ConvHalfCpltCallback
bogdanm	0:9b334a45a8ff	211	(+@) HAL_ADCEx_InjectedConvCpltCallback()
bogdanm	0:9b334a45a8ff	212
bogdanm	0:9b334a45a8ff	213	* Deinitialization of ADC *
bogdanm	0:9b334a45a8ff	214	============================================================
bogdanm	0:9b334a45a8ff	215	[..]
bogdanm	0:9b334a45a8ff	216
bogdanm	0:9b334a45a8ff	217	(#) Disable the ADC interface
bogdanm	0:9b334a45a8ff	218	(++) ADC clock can be hard reset and disabled at RCC top level.
bogdanm	0:9b334a45a8ff	219	(++) Hard reset of ADC peripherals
bogdanm	0:9b334a45a8ff	220	using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
bogdanm	0:9b334a45a8ff	221	(++) ADC clock disable
bogdanm	0:9b334a45a8ff	222	using the equivalent macro/functions as configuration step.
bogdanm	0:9b334a45a8ff	223	(+++) Example:
bogdanm	0:9b334a45a8ff	224	Into HAL_ADC_MspDeInit() (recommended code location) or with
bogdanm	0:9b334a45a8ff	225	other device clock parameters configuration:
bogdanm	0:9b334a45a8ff	226	(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
bogdanm	0:9b334a45a8ff	227	(+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF
bogdanm	0:9b334a45a8ff	228	(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
bogdanm	0:9b334a45a8ff	229
bogdanm	0:9b334a45a8ff	230	(#) ADC pins configuration
bogdanm	0:9b334a45a8ff	231	(++) Disable the clock for the ADC GPIOs
bogdanm	0:9b334a45a8ff	232	using macro __HAL_RCC_GPIOx_CLK_DISABLE()
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	(#) Optionally, in case of usage of ADC with interruptions:
bogdanm	0:9b334a45a8ff	235	(++) Disable the NVIC for ADC
bogdanm	0:9b334a45a8ff	236	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
bogdanm	0:9b334a45a8ff	237
bogdanm	0:9b334a45a8ff	238	(#) Optionally, in case of usage of DMA:
bogdanm	0:9b334a45a8ff	239	(++) Deinitialize the DMA
bogdanm	0:9b334a45a8ff	240	using function HAL_DMA_Init().
bogdanm	0:9b334a45a8ff	241	(++) Disable the NVIC for DMA
bogdanm	0:9b334a45a8ff	242	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244	[..]
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	@endverbatim
bogdanm	0:9b334a45a8ff	247	******************************************************************************
bogdanm	0:9b334a45a8ff	248	* @attention
bogdanm	0:9b334a45a8ff	249	*
mbed_official	124:6a4a5b7d7324	250	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	251	*
bogdanm	0:9b334a45a8ff	252	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	253	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	254	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	255	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	256	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	257	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	258	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	259	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	260	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	261	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	262	*
bogdanm	0:9b334a45a8ff	263	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	264	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	265	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	266	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	267	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	268	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	269	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	270	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	271	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	272	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	273	*
bogdanm	0:9b334a45a8ff	274	******************************************************************************
bogdanm	0:9b334a45a8ff	275	*/
bogdanm	0:9b334a45a8ff	276
bogdanm	0:9b334a45a8ff	277	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	278	#include "stm32f1xx_hal.h"
bogdanm	0:9b334a45a8ff	279
bogdanm	0:9b334a45a8ff	280	/** @addtogroup STM32F1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	281	* @{
bogdanm	0:9b334a45a8ff	282	*/
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/** @defgroup ADC ADC
bogdanm	0:9b334a45a8ff	285	* @brief ADC HAL module driver
bogdanm	0:9b334a45a8ff	286	* @{
bogdanm	0:9b334a45a8ff	287	*/
bogdanm	0:9b334a45a8ff	288
bogdanm	0:9b334a45a8ff	289	#ifdef HAL_ADC_MODULE_ENABLED
mbed_official	124:6a4a5b7d7324	290
bogdanm	0:9b334a45a8ff	291	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	292	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	293	/** @defgroup ADC_Private_Constants ADC Private Constants
bogdanm	0:9b334a45a8ff	294	* @{
bogdanm	0:9b334a45a8ff	295	*/
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/* Timeout values for ADC enable and disable settling time. */
bogdanm	0:9b334a45a8ff	298	/* Values defined to be higher than worst cases: low clocks freq, */
bogdanm	0:9b334a45a8ff	299	/* maximum prescaler. */
bogdanm	0:9b334a45a8ff	300	/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
bogdanm	0:9b334a45a8ff	301	/* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
bogdanm	0:9b334a45a8ff	302	/* Unit: ms */
bogdanm	0:9b334a45a8ff	303	#define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
bogdanm	0:9b334a45a8ff	304	#define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/* Delay for ADC stabilization time. */
bogdanm	0:9b334a45a8ff	307	/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
bogdanm	0:9b334a45a8ff	308	/* Unit: us */
bogdanm	0:9b334a45a8ff	309	#define ADC_STAB_DELAY_US ((uint32_t) 1)
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	/* Delay for temperature sensor stabilization time. */
bogdanm	0:9b334a45a8ff	312	/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
bogdanm	0:9b334a45a8ff	313	/* Unit: us */
bogdanm	0:9b334a45a8ff	314	#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	/**
bogdanm	0:9b334a45a8ff	317	* @}
bogdanm	0:9b334a45a8ff	318	*/
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	321	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	322	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	323	/** @defgroup ADC_Private_Functions ADC Private Functions
bogdanm	0:9b334a45a8ff	324	* @{
bogdanm	0:9b334a45a8ff	325	*/
bogdanm	0:9b334a45a8ff	326	/**
bogdanm	0:9b334a45a8ff	327	* @}
bogdanm	0:9b334a45a8ff	328	*/
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/** @defgroup ADC_Exported_Functions ADC Exported Functions
bogdanm	0:9b334a45a8ff	333	* @{
bogdanm	0:9b334a45a8ff	334	*/
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	337	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	338	*
bogdanm	0:9b334a45a8ff	339	@verbatim
bogdanm	0:9b334a45a8ff	340	===============================================================================
bogdanm	0:9b334a45a8ff	341	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	342	===============================================================================
bogdanm	0:9b334a45a8ff	343	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	344	(+) Initialize and configure the ADC.
bogdanm	0:9b334a45a8ff	345	(+) De-initialize the ADC.
bogdanm	0:9b334a45a8ff	346
bogdanm	0:9b334a45a8ff	347	@endverbatim
bogdanm	0:9b334a45a8ff	348	* @{
bogdanm	0:9b334a45a8ff	349	*/
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	/**
bogdanm	0:9b334a45a8ff	352	* @brief Initializes the ADC peripheral and regular group according to
bogdanm	0:9b334a45a8ff	353	* parameters specified in structure "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	354	* @note As prerequisite, ADC clock must be configured at RCC top level
bogdanm	0:9b334a45a8ff	355	* (clock source APB2).
bogdanm	0:9b334a45a8ff	356	* See commented example code below that can be copied and uncommented
bogdanm	0:9b334a45a8ff	357	* into HAL_ADC_MspInit().
bogdanm	0:9b334a45a8ff	358	* @note Possibility to update parameters on the fly:
bogdanm	0:9b334a45a8ff	359	* This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
bogdanm	0:9b334a45a8ff	360	* coming from ADC state reset. Following calls to this function can
bogdanm	0:9b334a45a8ff	361	* be used to reconfigure some parameters of ADC_InitTypeDef
bogdanm	0:9b334a45a8ff	362	* structure on the fly, without modifying MSP configuration. If ADC
bogdanm	0:9b334a45a8ff	363	* MSP has to be modified again, HAL_ADC_DeInit() must be called
bogdanm	0:9b334a45a8ff	364	* before HAL_ADC_Init().
bogdanm	0:9b334a45a8ff	365	* The setting of these parameters is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	366	* For parameters constraints, see comments of structure
bogdanm	0:9b334a45a8ff	367	* "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	368	* @note This function configures the ADC within 2 scopes: scope of entire
bogdanm	0:9b334a45a8ff	369	* ADC and scope of regular group. For parameters details, see comments
bogdanm	0:9b334a45a8ff	370	* of structure "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	371	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	372	* @retval HAL status
bogdanm	0:9b334a45a8ff	373	*/
bogdanm	0:9b334a45a8ff	374	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	375	{
bogdanm	0:9b334a45a8ff	376	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	377	uint32_t tmp_cr1 = 0;
bogdanm	0:9b334a45a8ff	378	uint32_t tmp_cr2 = 0;
bogdanm	0:9b334a45a8ff	379	uint32_t tmp_sqr1 = 0;
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	/* Check ADC handle */
bogdanm	0:9b334a45a8ff	382	if(hadc == NULL)
bogdanm	0:9b334a45a8ff	383	{
bogdanm	0:9b334a45a8ff	384	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	385	}
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	/* Check the parameters */
bogdanm	0:9b334a45a8ff	388	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	389	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
bogdanm	0:9b334a45a8ff	390	assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
bogdanm	0:9b334a45a8ff	391	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	392	assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
bogdanm	0:9b334a45a8ff	395	{
bogdanm	0:9b334a45a8ff	396	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
bogdanm	0:9b334a45a8ff	397	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
mbed_official	124:6a4a5b7d7324	398	if(hadc->Init.DiscontinuousConvMode != DISABLE)
mbed_official	124:6a4a5b7d7324	399	{
mbed_official	124:6a4a5b7d7324	400	assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
mbed_official	124:6a4a5b7d7324	401	}
mbed_official	124:6a4a5b7d7324	402	}
bogdanm	0:9b334a45a8ff	403
bogdanm	0:9b334a45a8ff	404	/* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
bogdanm	0:9b334a45a8ff	405	/* at RCC top level. */
bogdanm	0:9b334a45a8ff	406	/* Refer to header of this file for more details on clock enabling */
bogdanm	0:9b334a45a8ff	407	/* procedure. */
bogdanm	0:9b334a45a8ff	408
bogdanm	0:9b334a45a8ff	409	/* Actions performed only if ADC is coming from state reset: */
bogdanm	0:9b334a45a8ff	410	/* - Initialization of ADC MSP */
bogdanm	0:9b334a45a8ff	411	if (hadc->State == HAL_ADC_STATE_RESET)
bogdanm	0:9b334a45a8ff	412	{
mbed_official	124:6a4a5b7d7324	413	/* Initialize ADC error code */
mbed_official	124:6a4a5b7d7324	414	ADC_CLEAR_ERRORCODE(hadc);
mbed_official	124:6a4a5b7d7324	415
bogdanm	0:9b334a45a8ff	416	/* Allocate lock resource and initialize it */
mbed_official	124:6a4a5b7d7324	417	hadc->Lock = HAL_UNLOCKED;
mbed_official	124:6a4a5b7d7324	418
bogdanm	0:9b334a45a8ff	419	/* Init the low level hardware */
bogdanm	0:9b334a45a8ff	420	HAL_ADC_MspInit(hadc);
bogdanm	0:9b334a45a8ff	421	}
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	424	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	425	/* Note: In case of ADC already enabled, precaution to not launch an */
bogdanm	0:9b334a45a8ff	426	/* unwanted conversion while modifying register CR2 by writing 1 to */
bogdanm	0:9b334a45a8ff	427	/* bit ADON. */
bogdanm	0:9b334a45a8ff	428	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430
bogdanm	0:9b334a45a8ff	431	/* Configuration of ADC parameters if previous preliminary actions are */
bogdanm	0:9b334a45a8ff	432	/* correctly completed. */
mbed_official	124:6a4a5b7d7324	433	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
mbed_official	124:6a4a5b7d7324	434	(tmp_hal_status == HAL_OK) )
bogdanm	0:9b334a45a8ff	435	{
mbed_official	124:6a4a5b7d7324	436	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	437	ADC_STATE_CLR_SET(hadc->State,
mbed_official	124:6a4a5b7d7324	438	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
mbed_official	124:6a4a5b7d7324	439	HAL_ADC_STATE_BUSY_INTERNAL);
mbed_official	124:6a4a5b7d7324	440
bogdanm	0:9b334a45a8ff	441	/* Set ADC parameters */
bogdanm	0:9b334a45a8ff	442
bogdanm	0:9b334a45a8ff	443	/* Configuration of ADC: */
bogdanm	0:9b334a45a8ff	444	/* - data alignment */
bogdanm	0:9b334a45a8ff	445	/* - external trigger to start conversion */
bogdanm	0:9b334a45a8ff	446	/* - external trigger polarity (always set to 1, because needed for all */
bogdanm	0:9b334a45a8ff	447	/* triggers: external trigger of SW start) */
bogdanm	0:9b334a45a8ff	448	/* - continuous conversion mode */
bogdanm	0:9b334a45a8ff	449	/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
bogdanm	0:9b334a45a8ff	450	/* HAL_ADC_Start_xxx functions because if set in this function, */
bogdanm	0:9b334a45a8ff	451	/* a conversion on injected group would start a conversion also on */
bogdanm	0:9b334a45a8ff	452	/* regular group after ADC enabling. */
bogdanm	0:9b334a45a8ff	453	tmp_cr2 \|= (hadc->Init.DataAlign \|
bogdanm	0:9b334a45a8ff	454	ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) \|
bogdanm	0:9b334a45a8ff	455	ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457	/* Configuration of ADC: */
bogdanm	0:9b334a45a8ff	458	/* - scan mode */
bogdanm	0:9b334a45a8ff	459	/* - discontinuous mode disable/enable */
bogdanm	0:9b334a45a8ff	460	/* - discontinuous mode number of conversions */
bogdanm	0:9b334a45a8ff	461	tmp_cr1 \|= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
mbed_official	124:6a4a5b7d7324	462
bogdanm	0:9b334a45a8ff	463	/* Enable discontinuous mode only if continuous mode is disabled */
mbed_official	124:6a4a5b7d7324	464	/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
mbed_official	124:6a4a5b7d7324	465	/* discontinuous is set anyway, but will have no effect on ADC HW. */
mbed_official	124:6a4a5b7d7324	466	if (hadc->Init.DiscontinuousConvMode == ENABLE)
mbed_official	124:6a4a5b7d7324	467	{
mbed_official	124:6a4a5b7d7324	468	if (hadc->Init.ContinuousConvMode == DISABLE)
mbed_official	124:6a4a5b7d7324	469	{
mbed_official	124:6a4a5b7d7324	470	/* Enable the selected ADC regular discontinuous mode */
mbed_official	124:6a4a5b7d7324	471	/* Set the number of channels to be converted in discontinuous mode */
mbed_official	124:6a4a5b7d7324	472	SET_BIT(tmp_cr1, ADC_CR1_DISCEN \|
mbed_official	124:6a4a5b7d7324	473	ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
mbed_official	124:6a4a5b7d7324	474	}
mbed_official	124:6a4a5b7d7324	475	else
mbed_official	124:6a4a5b7d7324	476	{
mbed_official	124:6a4a5b7d7324	477	/* ADC regular group settings continuous and sequencer discontinuous*/
mbed_official	124:6a4a5b7d7324	478	/* cannot be enabled simultaneously. */
mbed_official	124:6a4a5b7d7324	479
mbed_official	124:6a4a5b7d7324	480	/* Update ADC state machine to error */
mbed_official	124:6a4a5b7d7324	481	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
mbed_official	124:6a4a5b7d7324	482
mbed_official	124:6a4a5b7d7324	483	/* Set ADC error code to ADC IP internal error */
mbed_official	124:6a4a5b7d7324	484	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
mbed_official	124:6a4a5b7d7324	485	}
bogdanm	0:9b334a45a8ff	486	}
bogdanm	0:9b334a45a8ff	487
bogdanm	0:9b334a45a8ff	488	/* Update ADC configuration register CR1 with previous settings */
bogdanm	0:9b334a45a8ff	489	MODIFY_REG(hadc->Instance->CR1,
bogdanm	0:9b334a45a8ff	490	ADC_CR1_SCAN \|
bogdanm	0:9b334a45a8ff	491	ADC_CR1_DISCEN \|
bogdanm	0:9b334a45a8ff	492	ADC_CR1_DISCNUM ,
bogdanm	0:9b334a45a8ff	493	tmp_cr1 );
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	/* Update ADC configuration register CR2 with previous settings */
bogdanm	0:9b334a45a8ff	496	MODIFY_REG(hadc->Instance->CR2,
bogdanm	0:9b334a45a8ff	497	ADC_CR2_ALIGN \|
bogdanm	0:9b334a45a8ff	498	ADC_CR2_EXTSEL \|
bogdanm	0:9b334a45a8ff	499	ADC_CR2_EXTTRIG \|
bogdanm	0:9b334a45a8ff	500	ADC_CR2_CONT ,
bogdanm	0:9b334a45a8ff	501	tmp_cr2 );
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/* Configuration of regular group sequencer: */
bogdanm	0:9b334a45a8ff	504	/* - if scan mode is disabled, regular channels sequence length is set to */
bogdanm	0:9b334a45a8ff	505	/* 0x00: 1 channel converted (channel on regular rank 1) */
bogdanm	0:9b334a45a8ff	506	/* Parameter "NbrOfConversion" is discarded. */
bogdanm	0:9b334a45a8ff	507	/* Note: Scan mode is present by hardware on this device and, if */
bogdanm	0:9b334a45a8ff	508	/* disabled, discards automatically nb of conversions. Anyway, nb of */
bogdanm	0:9b334a45a8ff	509	/* conversions is forced to 0x00 for alignment over all STM32 devices. */
bogdanm	0:9b334a45a8ff	510	/* - if scan mode is enabled, regular channels sequence length is set to */
bogdanm	0:9b334a45a8ff	511	/* parameter "NbrOfConversion" */
mbed_official	124:6a4a5b7d7324	512	if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
bogdanm	0:9b334a45a8ff	513	{
bogdanm	0:9b334a45a8ff	514	tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
bogdanm	0:9b334a45a8ff	515	}
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	MODIFY_REG(hadc->Instance->SQR1,
bogdanm	0:9b334a45a8ff	518	ADC_SQR1_L ,
bogdanm	0:9b334a45a8ff	519	tmp_sqr1 );
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	/* Check back that ADC registers have effectively been configured to */
bogdanm	0:9b334a45a8ff	522	/* ensure of no potential problem of ADC core IP clocking. */
bogdanm	0:9b334a45a8ff	523	/* Check through register CR2 (excluding bits set in other functions: */
mbed_official	124:6a4a5b7d7324	524	/* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
mbed_official	124:6a4a5b7d7324	525	/* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
mbed_official	124:6a4a5b7d7324	526	/* measurement path bit (TSVREFE). */
mbed_official	124:6a4a5b7d7324	527	if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON \| ADC_CR2_DMA \|
bogdanm	0:9b334a45a8ff	528	ADC_CR2_SWSTART \| ADC_CR2_JSWSTART \|
bogdanm	0:9b334a45a8ff	529	ADC_CR2_JEXTTRIG \| ADC_CR2_JEXTSEL \|
bogdanm	0:9b334a45a8ff	530	ADC_CR2_TSVREFE ))
bogdanm	0:9b334a45a8ff	531	== tmp_cr2)
bogdanm	0:9b334a45a8ff	532	{
bogdanm	0:9b334a45a8ff	533	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	534	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	535
mbed_official	124:6a4a5b7d7324	536	/* Set the ADC state */
mbed_official	124:6a4a5b7d7324	537	ADC_STATE_CLR_SET(hadc->State,
mbed_official	124:6a4a5b7d7324	538	HAL_ADC_STATE_BUSY_INTERNAL,
mbed_official	124:6a4a5b7d7324	539	HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	540	}
bogdanm	0:9b334a45a8ff	541	else
bogdanm	0:9b334a45a8ff	542	{
bogdanm	0:9b334a45a8ff	543	/* Update ADC state machine to error */
mbed_official	124:6a4a5b7d7324	544	ADC_STATE_CLR_SET(hadc->State,
mbed_official	124:6a4a5b7d7324	545	HAL_ADC_STATE_BUSY_INTERNAL,
mbed_official	124:6a4a5b7d7324	546	HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	547
bogdanm	0:9b334a45a8ff	548	/* Set ADC error code to ADC IP internal error */
mbed_official	124:6a4a5b7d7324	549	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551	tmp_hal_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	552	}
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	}
bogdanm	0:9b334a45a8ff	555	else
bogdanm	0:9b334a45a8ff	556	{
bogdanm	0:9b334a45a8ff	557	/* Update ADC state machine to error */
mbed_official	124:6a4a5b7d7324	558	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	tmp_hal_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	561	}
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	/* Return function status */
bogdanm	0:9b334a45a8ff	564	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	565	}
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	/**
bogdanm	0:9b334a45a8ff	568	* @brief Deinitialize the ADC peripheral registers to their default reset
bogdanm	0:9b334a45a8ff	569	* values, with deinitialization of the ADC MSP.
bogdanm	0:9b334a45a8ff	570	* If needed, the example code can be copied and uncommented into
bogdanm	0:9b334a45a8ff	571	* function HAL_ADC_MspDeInit().
bogdanm	0:9b334a45a8ff	572	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	573	* @retval HAL status
bogdanm	0:9b334a45a8ff	574	*/
bogdanm	0:9b334a45a8ff	575	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	576	{
bogdanm	0:9b334a45a8ff	577	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	578
bogdanm	0:9b334a45a8ff	579	/* Check ADC handle */
bogdanm	0:9b334a45a8ff	580	if(hadc == NULL)
bogdanm	0:9b334a45a8ff	581	{
bogdanm	0:9b334a45a8ff	582	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	583	}
bogdanm	0:9b334a45a8ff	584
bogdanm	0:9b334a45a8ff	585	/* Check the parameters */
bogdanm	0:9b334a45a8ff	586	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	587
mbed_official	124:6a4a5b7d7324	588	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	589	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
bogdanm	0:9b334a45a8ff	590
bogdanm	0:9b334a45a8ff	591	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	592	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	593	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	594
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	/* Configuration of ADC parameters if previous preliminary actions are */
bogdanm	0:9b334a45a8ff	597	/* correctly completed. */
mbed_official	124:6a4a5b7d7324	598	if (tmp_hal_status == HAL_OK)
bogdanm	0:9b334a45a8ff	599	{
bogdanm	0:9b334a45a8ff	600	/* ========== Reset ADC registers ========== */
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603
bogdanm	0:9b334a45a8ff	604
bogdanm	0:9b334a45a8ff	605	/* Reset register SR */
bogdanm	0:9b334a45a8ff	606	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD \| ADC_FLAG_JEOC \| ADC_FLAG_EOC \|
bogdanm	0:9b334a45a8ff	607	ADC_FLAG_JSTRT \| ADC_FLAG_STRT));
bogdanm	0:9b334a45a8ff	608
bogdanm	0:9b334a45a8ff	609	/* Reset register CR1 */
bogdanm	0:9b334a45a8ff	610	CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_DISCNUM \|
bogdanm	0:9b334a45a8ff	611	ADC_CR1_JDISCEN \| ADC_CR1_DISCEN \| ADC_CR1_JAUTO \|
bogdanm	0:9b334a45a8ff	612	ADC_CR1_AWDSGL \| ADC_CR1_SCAN \| ADC_CR1_JEOCIE \|
bogdanm	0:9b334a45a8ff	613	ADC_CR1_AWDIE \| ADC_CR1_EOCIE \| ADC_CR1_AWDCH ));
bogdanm	0:9b334a45a8ff	614
bogdanm	0:9b334a45a8ff	615	/* Reset register CR2 */
bogdanm	0:9b334a45a8ff	616	CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE \| ADC_CR2_SWSTART \| ADC_CR2_JSWSTART \|
bogdanm	0:9b334a45a8ff	617	ADC_CR2_EXTTRIG \| ADC_CR2_EXTSEL \| ADC_CR2_JEXTTRIG \|
bogdanm	0:9b334a45a8ff	618	ADC_CR2_JEXTSEL \| ADC_CR2_ALIGN \| ADC_CR2_DMA \|
bogdanm	0:9b334a45a8ff	619	ADC_CR2_RSTCAL \| ADC_CR2_CAL \| ADC_CR2_CONT \|
bogdanm	0:9b334a45a8ff	620	ADC_CR2_ADON ));
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622	/* Reset register SMPR1 */
bogdanm	0:9b334a45a8ff	623	CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 \| ADC_SMPR1_SMP16 \| ADC_SMPR1_SMP15 \|
bogdanm	0:9b334a45a8ff	624	ADC_SMPR1_SMP14 \| ADC_SMPR1_SMP13 \| ADC_SMPR1_SMP12 \|
bogdanm	0:9b334a45a8ff	625	ADC_SMPR1_SMP11 \| ADC_SMPR1_SMP10 ));
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	/* Reset register SMPR2 */
bogdanm	0:9b334a45a8ff	628	CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 \| ADC_SMPR2_SMP8 \| ADC_SMPR2_SMP7 \|
bogdanm	0:9b334a45a8ff	629	ADC_SMPR2_SMP6 \| ADC_SMPR2_SMP5 \| ADC_SMPR2_SMP4 \|
bogdanm	0:9b334a45a8ff	630	ADC_SMPR2_SMP3 \| ADC_SMPR2_SMP2 \| ADC_SMPR2_SMP1 \|
bogdanm	0:9b334a45a8ff	631	ADC_SMPR2_SMP0 ));
bogdanm	0:9b334a45a8ff	632
bogdanm	0:9b334a45a8ff	633	/* Reset register JOFR1 */
bogdanm	0:9b334a45a8ff	634	CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
bogdanm	0:9b334a45a8ff	635	/* Reset register JOFR2 */
bogdanm	0:9b334a45a8ff	636	CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
bogdanm	0:9b334a45a8ff	637	/* Reset register JOFR3 */
bogdanm	0:9b334a45a8ff	638	CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
bogdanm	0:9b334a45a8ff	639	/* Reset register JOFR4 */
bogdanm	0:9b334a45a8ff	640	CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
bogdanm	0:9b334a45a8ff	641
bogdanm	0:9b334a45a8ff	642	/* Reset register HTR */
bogdanm	0:9b334a45a8ff	643	CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
bogdanm	0:9b334a45a8ff	644	/* Reset register LTR */
bogdanm	0:9b334a45a8ff	645	CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
bogdanm	0:9b334a45a8ff	646
bogdanm	0:9b334a45a8ff	647	/* Reset register SQR1 */
bogdanm	0:9b334a45a8ff	648	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L \|
bogdanm	0:9b334a45a8ff	649	ADC_SQR1_SQ16 \| ADC_SQR1_SQ15 \|
bogdanm	0:9b334a45a8ff	650	ADC_SQR1_SQ14 \| ADC_SQR1_SQ13 );
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/* Reset register SQR1 */
bogdanm	0:9b334a45a8ff	653	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L \|
bogdanm	0:9b334a45a8ff	654	ADC_SQR1_SQ16 \| ADC_SQR1_SQ15 \|
bogdanm	0:9b334a45a8ff	655	ADC_SQR1_SQ14 \| ADC_SQR1_SQ13 );
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657	/* Reset register SQR2 */
bogdanm	0:9b334a45a8ff	658	CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 \| ADC_SQR2_SQ11 \| ADC_SQR2_SQ10 \|
bogdanm	0:9b334a45a8ff	659	ADC_SQR2_SQ9 \| ADC_SQR2_SQ8 \| ADC_SQR2_SQ7 );
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	/* Reset register SQR3 */
bogdanm	0:9b334a45a8ff	662	CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 \| ADC_SQR3_SQ5 \| ADC_SQR3_SQ4 \|
bogdanm	0:9b334a45a8ff	663	ADC_SQR3_SQ3 \| ADC_SQR3_SQ2 \| ADC_SQR3_SQ1 );
bogdanm	0:9b334a45a8ff	664
bogdanm	0:9b334a45a8ff	665	/* Reset register JSQR */
bogdanm	0:9b334a45a8ff	666	CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL \|
bogdanm	0:9b334a45a8ff	667	ADC_JSQR_JSQ4 \| ADC_JSQR_JSQ3 \|
bogdanm	0:9b334a45a8ff	668	ADC_JSQR_JSQ2 \| ADC_JSQR_JSQ1 );
bogdanm	0:9b334a45a8ff	669
bogdanm	0:9b334a45a8ff	670	/* Reset register JSQR */
bogdanm	0:9b334a45a8ff	671	CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL \|
bogdanm	0:9b334a45a8ff	672	ADC_JSQR_JSQ4 \| ADC_JSQR_JSQ3 \|
bogdanm	0:9b334a45a8ff	673	ADC_JSQR_JSQ2 \| ADC_JSQR_JSQ1 );
bogdanm	0:9b334a45a8ff	674
bogdanm	0:9b334a45a8ff	675	/* Reset register DR */
bogdanm	0:9b334a45a8ff	676	/* bits in access mode read only, no direct reset applicable*/
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	/* Reset registers JDR1, JDR2, JDR3, JDR4 */
bogdanm	0:9b334a45a8ff	679	/* bits in access mode read only, no direct reset applicable*/
bogdanm	0:9b334a45a8ff	680
bogdanm	0:9b334a45a8ff	681	/* ========== Hard reset ADC peripheral ========== */
bogdanm	0:9b334a45a8ff	682	/* Performs a global reset of the entire ADC peripheral: ADC state is */
bogdanm	0:9b334a45a8ff	683	/* forced to a similar state after device power-on. */
bogdanm	0:9b334a45a8ff	684	/* If needed, copy-paste and uncomment the following reset code into */
bogdanm	0:9b334a45a8ff	685	/* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
bogdanm	0:9b334a45a8ff	686	/* */
bogdanm	0:9b334a45a8ff	687	/* __HAL_RCC_ADC1_FORCE_RESET() */
bogdanm	0:9b334a45a8ff	688	/* __HAL_RCC_ADC1_RELEASE_RESET() */
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	/* DeInit the low level hardware */
bogdanm	0:9b334a45a8ff	691	HAL_ADC_MspDeInit(hadc);
bogdanm	0:9b334a45a8ff	692
bogdanm	0:9b334a45a8ff	693	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	694	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	695
mbed_official	124:6a4a5b7d7324	696	/* Set ADC state */
bogdanm	0:9b334a45a8ff	697	hadc->State = HAL_ADC_STATE_RESET;
bogdanm	0:9b334a45a8ff	698
bogdanm	0:9b334a45a8ff	699	}
bogdanm	0:9b334a45a8ff	700
bogdanm	0:9b334a45a8ff	701	/* Process unlocked */
bogdanm	0:9b334a45a8ff	702	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	/* Return function status */
bogdanm	0:9b334a45a8ff	705	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	706	}
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	/**
bogdanm	0:9b334a45a8ff	709	* @brief Initializes the ADC MSP.
bogdanm	0:9b334a45a8ff	710	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	711	* @retval None
bogdanm	0:9b334a45a8ff	712	*/
bogdanm	0:9b334a45a8ff	713	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	714	{
mbed_official	124:6a4a5b7d7324	715	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	716	UNUSED(hadc);
bogdanm	0:9b334a45a8ff	717	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	718	function HAL_ADC_MspInit must be implemented in the user file.
bogdanm	0:9b334a45a8ff	719	*/
bogdanm	0:9b334a45a8ff	720	}
bogdanm	0:9b334a45a8ff	721
bogdanm	0:9b334a45a8ff	722	/**
bogdanm	0:9b334a45a8ff	723	* @brief DeInitializes the ADC MSP.
bogdanm	0:9b334a45a8ff	724	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	725	* @retval None
bogdanm	0:9b334a45a8ff	726	*/
bogdanm	0:9b334a45a8ff	727	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	728	{
mbed_official	124:6a4a5b7d7324	729	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	730	UNUSED(hadc);
bogdanm	0:9b334a45a8ff	731	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	732	function HAL_ADC_MspDeInit must be implemented in the user file.
bogdanm	0:9b334a45a8ff	733	*/
bogdanm	0:9b334a45a8ff	734	}
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736	/**
bogdanm	0:9b334a45a8ff	737	* @}
bogdanm	0:9b334a45a8ff	738	*/
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	741	* @brief Input and Output operation functions
bogdanm	0:9b334a45a8ff	742	*
bogdanm	0:9b334a45a8ff	743	@verbatim
bogdanm	0:9b334a45a8ff	744	===============================================================================
bogdanm	0:9b334a45a8ff	745	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	746	===============================================================================
bogdanm	0:9b334a45a8ff	747	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	748	(+) Start conversion of regular group.
bogdanm	0:9b334a45a8ff	749	(+) Stop conversion of regular group.
bogdanm	0:9b334a45a8ff	750	(+) Poll for conversion complete on regular group.
bogdanm	0:9b334a45a8ff	751	(+) Poll for conversion event.
bogdanm	0:9b334a45a8ff	752	(+) Get result of regular channel conversion.
bogdanm	0:9b334a45a8ff	753	(+) Start conversion of regular group and enable interruptions.
bogdanm	0:9b334a45a8ff	754	(+) Stop conversion of regular group and disable interruptions.
bogdanm	0:9b334a45a8ff	755	(+) Handle ADC interrupt request
bogdanm	0:9b334a45a8ff	756	(+) Start conversion of regular group and enable DMA transfer.
bogdanm	0:9b334a45a8ff	757	(+) Stop conversion of regular group and disable ADC DMA transfer.
bogdanm	0:9b334a45a8ff	758	@endverbatim
bogdanm	0:9b334a45a8ff	759	* @{
bogdanm	0:9b334a45a8ff	760	*/
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	/**
bogdanm	0:9b334a45a8ff	763	* @brief Enables ADC, starts conversion of regular group.
bogdanm	0:9b334a45a8ff	764	* Interruptions enabled in this function: None.
bogdanm	0:9b334a45a8ff	765	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	766	* @retval HAL status
bogdanm	0:9b334a45a8ff	767	*/
bogdanm	0:9b334a45a8ff	768	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	769	{
bogdanm	0:9b334a45a8ff	770	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	771
bogdanm	0:9b334a45a8ff	772	/* Check the parameters */
bogdanm	0:9b334a45a8ff	773	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	774
bogdanm	0:9b334a45a8ff	775	/* Process locked */
bogdanm	0:9b334a45a8ff	776	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	777
bogdanm	0:9b334a45a8ff	778	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	779	tmp_hal_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	/* Start conversion if ADC is effectively enabled */
mbed_official	124:6a4a5b7d7324	782	if (tmp_hal_status == HAL_OK)
bogdanm	0:9b334a45a8ff	783	{
mbed_official	124:6a4a5b7d7324	784	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	785	/* - Clear state bitfield related to regular group conversion results */
mbed_official	124:6a4a5b7d7324	786	/* - Set state bitfield related to regular operation */
mbed_official	124:6a4a5b7d7324	787	ADC_STATE_CLR_SET(hadc->State,
mbed_official	124:6a4a5b7d7324	788	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC,
mbed_official	124:6a4a5b7d7324	789	HAL_ADC_STATE_REG_BUSY);
mbed_official	124:6a4a5b7d7324	790
mbed_official	124:6a4a5b7d7324	791	/* Set group injected state (from auto-injection) and multimode state */
mbed_official	124:6a4a5b7d7324	792	/* for all cases of multimode: independent mode, multimode ADC master */
mbed_official	124:6a4a5b7d7324	793	/* or multimode ADC slave (for devices with several ADCs): */
mbed_official	124:6a4a5b7d7324	794	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
bogdanm	0:9b334a45a8ff	795	{
mbed_official	124:6a4a5b7d7324	796	/* Set ADC state (ADC independent or master) */
mbed_official	124:6a4a5b7d7324	797	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
mbed_official	124:6a4a5b7d7324	798
mbed_official	124:6a4a5b7d7324	799	/* If conversions on group regular are also triggering group injected, */
mbed_official	124:6a4a5b7d7324	800	/* update ADC state. */
mbed_official	124:6a4a5b7d7324	801	if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
mbed_official	124:6a4a5b7d7324	802	{
mbed_official	124:6a4a5b7d7324	803	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
mbed_official	124:6a4a5b7d7324	804	}
bogdanm	0:9b334a45a8ff	805	}
bogdanm	0:9b334a45a8ff	806	else
bogdanm	0:9b334a45a8ff	807	{
mbed_official	124:6a4a5b7d7324	808	/* Set ADC state (ADC slave) */
mbed_official	124:6a4a5b7d7324	809	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
mbed_official	124:6a4a5b7d7324	810
mbed_official	124:6a4a5b7d7324	811	/* If conversions on group regular are also triggering group injected, */
mbed_official	124:6a4a5b7d7324	812	/* update ADC state. */
mbed_official	124:6a4a5b7d7324	813	if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
mbed_official	124:6a4a5b7d7324	814	{
mbed_official	124:6a4a5b7d7324	815	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
mbed_official	124:6a4a5b7d7324	816	}
bogdanm	0:9b334a45a8ff	817	}
mbed_official	124:6a4a5b7d7324	818
mbed_official	124:6a4a5b7d7324	819	/* State machine update: Check if an injected conversion is ongoing */
mbed_official	124:6a4a5b7d7324	820	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
mbed_official	124:6a4a5b7d7324	821	{
mbed_official	124:6a4a5b7d7324	822	/* Reset ADC error code fields related to conversions on group regular */
mbed_official	124:6a4a5b7d7324	823	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR \| HAL_ADC_ERROR_DMA));
mbed_official	124:6a4a5b7d7324	824	}
mbed_official	124:6a4a5b7d7324	825	else
mbed_official	124:6a4a5b7d7324	826	{
mbed_official	124:6a4a5b7d7324	827	/* Reset ADC all error code fields */
mbed_official	124:6a4a5b7d7324	828	ADC_CLEAR_ERRORCODE(hadc);
mbed_official	124:6a4a5b7d7324	829	}
mbed_official	124:6a4a5b7d7324	830
bogdanm	0:9b334a45a8ff	831	/* Process unlocked */
bogdanm	0:9b334a45a8ff	832	/* Unlock before starting ADC conversions: in case of potential */
bogdanm	0:9b334a45a8ff	833	/* interruption, to let the process to ADC IRQ Handler. */
bogdanm	0:9b334a45a8ff	834	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	835
mbed_official	124:6a4a5b7d7324	836	/* Clear regular group conversion flag */
bogdanm	0:9b334a45a8ff	837	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	838	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	/* Enable conversion of regular group. */
bogdanm	0:9b334a45a8ff	841	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	842	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	843	/* trigger event. */
mbed_official	124:6a4a5b7d7324	844	/* Case of multimode enabled: */
mbed_official	124:6a4a5b7d7324	845	/* - if ADC is slave, ADC is enabled only (conversion is not started). */
mbed_official	124:6a4a5b7d7324	846	/* - if ADC is master, ADC is enabled and conversion is started. */
mbed_official	124:6a4a5b7d7324	847	/* If ADC is master, ADC is enabled and conversion is started. */
bogdanm	0:9b334a45a8ff	848	/* Note: Alternate trigger for single conversion could be to force an */
bogdanm	0:9b334a45a8ff	849	/* additional set of bit ADON "hadc->Instance->CR2 \|= ADC_CR2_ADON;"*/
bogdanm	0:9b334a45a8ff	850	if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
bogdanm	0:9b334a45a8ff	851	ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
bogdanm	0:9b334a45a8ff	852	{
bogdanm	0:9b334a45a8ff	853	/* Start ADC conversion on regular group with SW start */
bogdanm	0:9b334a45a8ff	854	SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART \| ADC_CR2_EXTTRIG));
bogdanm	0:9b334a45a8ff	855	}
bogdanm	0:9b334a45a8ff	856	else
bogdanm	0:9b334a45a8ff	857	{
bogdanm	0:9b334a45a8ff	858	/* Start ADC conversion on regular group with external trigger */
bogdanm	0:9b334a45a8ff	859	SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
bogdanm	0:9b334a45a8ff	860	}
bogdanm	0:9b334a45a8ff	861	}
bogdanm	0:9b334a45a8ff	862	else
bogdanm	0:9b334a45a8ff	863	{
bogdanm	0:9b334a45a8ff	864	/* Process unlocked */
bogdanm	0:9b334a45a8ff	865	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	866	}
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	/* Return function status */
bogdanm	0:9b334a45a8ff	869	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	870	}
bogdanm	0:9b334a45a8ff	871
bogdanm	0:9b334a45a8ff	872	/**
bogdanm	0:9b334a45a8ff	873	* @brief Stop ADC conversion of regular group (and injected channels in
bogdanm	0:9b334a45a8ff	874	* case of auto_injection mode), disable ADC peripheral.
bogdanm	0:9b334a45a8ff	875	* @note: ADC peripheral disable is forcing stop of potential
bogdanm	0:9b334a45a8ff	876	* conversion on injected group. If injected group is under use, it
bogdanm	0:9b334a45a8ff	877	* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
bogdanm	0:9b334a45a8ff	878	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	879	* @retval HAL status.
bogdanm	0:9b334a45a8ff	880	*/
bogdanm	0:9b334a45a8ff	881	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	882	{
bogdanm	0:9b334a45a8ff	883	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	/* Check the parameters */
bogdanm	0:9b334a45a8ff	886	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	887
bogdanm	0:9b334a45a8ff	888	/* Process locked */
bogdanm	0:9b334a45a8ff	889	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	890
bogdanm	0:9b334a45a8ff	891	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	892	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	893	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	894
bogdanm	0:9b334a45a8ff	895	/* Check if ADC is effectively disabled */
mbed_official	124:6a4a5b7d7324	896	if (tmp_hal_status == HAL_OK)
bogdanm	0:9b334a45a8ff	897	{
mbed_official	124:6a4a5b7d7324	898	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	899	ADC_STATE_CLR_SET(hadc->State,
mbed_official	124:6a4a5b7d7324	900	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
mbed_official	124:6a4a5b7d7324	901	HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	902	}
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	/* Process unlocked */
bogdanm	0:9b334a45a8ff	905	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	906
bogdanm	0:9b334a45a8ff	907	/* Return function status */
bogdanm	0:9b334a45a8ff	908	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	909	}
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	/**
bogdanm	0:9b334a45a8ff	912	* @brief Wait for regular group conversion to be completed.
mbed_official	124:6a4a5b7d7324	913	* @note This function cannot be used in a particular setup: ADC configured
mbed_official	124:6a4a5b7d7324	914	* in DMA mode.
mbed_official	124:6a4a5b7d7324	915	* In this case, DMA resets the flag EOC and polling cannot be
mbed_official	124:6a4a5b7d7324	916	* performed on each conversion.
mbed_official	124:6a4a5b7d7324	917	* @note On STM32F1 devices, limitation in case of sequencer enabled
mbed_official	124:6a4a5b7d7324	918	* (several ranks selected): polling cannot be done on each
mbed_official	124:6a4a5b7d7324	919	* conversion inside the sequence. In this case, polling is replaced by
mbed_official	124:6a4a5b7d7324	920	* wait for maximum conversion time.
bogdanm	0:9b334a45a8ff	921	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	922	* @param Timeout: Timeout value in millisecond.
bogdanm	0:9b334a45a8ff	923	* @retval HAL status
bogdanm	0:9b334a45a8ff	924	*/
bogdanm	0:9b334a45a8ff	925	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	926	{
bogdanm	0:9b334a45a8ff	927	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	/* Variables for polling in case of scan mode enabled and polling for each */
bogdanm	0:9b334a45a8ff	930	/* conversion. */
bogdanm	0:9b334a45a8ff	931	__IO uint32_t Conversion_Timeout_CPU_cycles = 0;
bogdanm	0:9b334a45a8ff	932	uint32_t Conversion_Timeout_CPU_cycles_max = 0;
bogdanm	0:9b334a45a8ff	933
bogdanm	0:9b334a45a8ff	934	/* Check the parameters */
bogdanm	0:9b334a45a8ff	935	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	936
mbed_official	124:6a4a5b7d7324	937	/* Get tick count */
bogdanm	0:9b334a45a8ff	938	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	939
mbed_official	124:6a4a5b7d7324	940	/* Verification that ADC configuration is compliant with polling for */
mbed_official	124:6a4a5b7d7324	941	/* each conversion: */
mbed_official	124:6a4a5b7d7324	942	/* Particular case is ADC configured in DMA mode */
mbed_official	124:6a4a5b7d7324	943	if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
mbed_official	124:6a4a5b7d7324	944	{
mbed_official	124:6a4a5b7d7324	945	/* Update ADC state machine to error */
mbed_official	124:6a4a5b7d7324	946	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
mbed_official	124:6a4a5b7d7324	947
mbed_official	124:6a4a5b7d7324	948	/* Process unlocked */
mbed_official	124:6a4a5b7d7324	949	__HAL_UNLOCK(hadc);
mbed_official	124:6a4a5b7d7324	950
mbed_official	124:6a4a5b7d7324	951	return HAL_ERROR;
mbed_official	124:6a4a5b7d7324	952	}
mbed_official	124:6a4a5b7d7324	953
bogdanm	0:9b334a45a8ff	954	/* Polling for end of conversion: differentiation if single/sequence */
bogdanm	0:9b334a45a8ff	955	/* conversion. */
bogdanm	0:9b334a45a8ff	956	/* - If single conversion for regular group (Scan mode disabled or enabled */
bogdanm	0:9b334a45a8ff	957	/* with NbrOfConversion =1), flag EOC is used to determine the */
bogdanm	0:9b334a45a8ff	958	/* conversion completion. */
mbed_official	124:6a4a5b7d7324	959	/* - If sequence conversion for regular group (scan mode enabled and */
mbed_official	124:6a4a5b7d7324	960	/* NbrOfConversion >=2), flag EOC is set only at the end of the */
mbed_official	124:6a4a5b7d7324	961	/* sequence. */
mbed_official	124:6a4a5b7d7324	962	/* To poll for each conversion, the maximum conversion time is computed */
mbed_official	124:6a4a5b7d7324	963	/* from ADC conversion time (selected sampling time + conversion time of */
mbed_official	124:6a4a5b7d7324	964	/* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
mbed_official	124:6a4a5b7d7324	965	/* settings, conversion time range can be from 28 to 32256 CPU cycles). */
mbed_official	124:6a4a5b7d7324	966	/* As flag EOC is not set after each conversion, no timeout status can */
mbed_official	124:6a4a5b7d7324	967	/* be set. */
bogdanm	0:9b334a45a8ff	968	if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
bogdanm	0:9b334a45a8ff	969	HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
bogdanm	0:9b334a45a8ff	970	{
bogdanm	0:9b334a45a8ff	971	/* Wait until End of Conversion flag is raised */
bogdanm	0:9b334a45a8ff	972	while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
bogdanm	0:9b334a45a8ff	973	{
bogdanm	0:9b334a45a8ff	974	/* Check if timeout is disabled (set to infinite wait) */
bogdanm	0:9b334a45a8ff	975	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	976	{
bogdanm	0:9b334a45a8ff	977	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	978	{
bogdanm	0:9b334a45a8ff	979	/* Update ADC state machine to timeout */
mbed_official	124:6a4a5b7d7324	980	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982	/* Process unlocked */
bogdanm	0:9b334a45a8ff	983	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	984
mbed_official	124:6a4a5b7d7324	985	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	986	}
bogdanm	0:9b334a45a8ff	987	}
bogdanm	0:9b334a45a8ff	988	}
bogdanm	0:9b334a45a8ff	989	}
bogdanm	0:9b334a45a8ff	990	else
bogdanm	0:9b334a45a8ff	991	{
mbed_official	124:6a4a5b7d7324	992	/* Replace polling by wait for maximum conversion time */
bogdanm	0:9b334a45a8ff	993	/* - Computation of CPU clock cycles corresponding to ADC clock cycles */
bogdanm	0:9b334a45a8ff	994	/* and ADC maximum conversion cycles on all channels. */
bogdanm	0:9b334a45a8ff	995	/* - Wait for the expected ADC clock cycles delay */
bogdanm	0:9b334a45a8ff	996	Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
bogdanm	0:9b334a45a8ff	997	/ HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
bogdanm	0:9b334a45a8ff	998	* ADC_CONVCYCLES_MAX_RANGE(hadc) );
mbed_official	124:6a4a5b7d7324	999
bogdanm	0:9b334a45a8ff	1000	while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
bogdanm	0:9b334a45a8ff	1001	{
bogdanm	0:9b334a45a8ff	1002	/* Check if timeout is disabled (set to infinite wait) */
bogdanm	0:9b334a45a8ff	1003	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1004	{
bogdanm	0:9b334a45a8ff	1005	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	1006	{
bogdanm	0:9b334a45a8ff	1007	/* Update ADC state machine to timeout */
mbed_official	124:6a4a5b7d7324	1008	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1011	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1012
mbed_official	124:6a4a5b7d7324	1013	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1014	}
bogdanm	0:9b334a45a8ff	1015	}
bogdanm	0:9b334a45a8ff	1016	Conversion_Timeout_CPU_cycles ++;
bogdanm	0:9b334a45a8ff	1017	}
bogdanm	0:9b334a45a8ff	1018	}
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	/* Clear regular group conversion flag */
bogdanm	0:9b334a45a8ff	1021	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT \| ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	1022
mbed_official	124:6a4a5b7d7324	1023	/* Update ADC state machine */
mbed_official	124:6a4a5b7d7324	1024	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
mbed_official	124:6a4a5b7d7324	1025
mbed_official	124:6a4a5b7d7324	1026	/* Determine whether any further conversion upcoming on group regular */
mbed_official	124:6a4a5b7d7324	1027	/* by external trigger, continuous mode or scan sequence on going. */
mbed_official	124:6a4a5b7d7324	1028	/* Note: On STM32F1 devices, in case of sequencer enabled */
mbed_official	124:6a4a5b7d7324	1029	/* (several ranks selected), end of conversion flag is raised */
mbed_official	124:6a4a5b7d7324	1030	/* at the end of the sequence. */
mbed_official	124:6a4a5b7d7324	1031	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
mbed_official	124:6a4a5b7d7324	1032	(hadc->Init.ContinuousConvMode == DISABLE) )
mbed_official	124:6a4a5b7d7324	1033	{
mbed_official	124:6a4a5b7d7324	1034	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	1035	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
mbed_official	124:6a4a5b7d7324	1036
mbed_official	124:6a4a5b7d7324	1037	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
mbed_official	124:6a4a5b7d7324	1038	{
mbed_official	124:6a4a5b7d7324	1039	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1040	}
bogdanm	0:9b334a45a8ff	1041	}
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	/* Return ADC state */
bogdanm	0:9b334a45a8ff	1044	return HAL_OK;
bogdanm	0:9b334a45a8ff	1045	}
bogdanm	0:9b334a45a8ff	1046
bogdanm	0:9b334a45a8ff	1047	/**
bogdanm	0:9b334a45a8ff	1048	* @brief Poll for conversion event.
bogdanm	0:9b334a45a8ff	1049	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1050	* @param EventType: the ADC event type.
bogdanm	0:9b334a45a8ff	1051	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1052	* @arg ADC_AWD_EVENT: ADC Analog watchdog event.
bogdanm	0:9b334a45a8ff	1053	* @param Timeout: Timeout value in millisecond.
bogdanm	0:9b334a45a8ff	1054	* @retval HAL status
bogdanm	0:9b334a45a8ff	1055	*/
bogdanm	0:9b334a45a8ff	1056	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1057	{
bogdanm	0:9b334a45a8ff	1058	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1059
bogdanm	0:9b334a45a8ff	1060	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1061	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1062	assert_param(IS_ADC_EVENT_TYPE(EventType));
bogdanm	0:9b334a45a8ff	1063
mbed_official	124:6a4a5b7d7324	1064	/* Get tick count */
bogdanm	0:9b334a45a8ff	1065	tickstart = HAL_GetTick();
mbed_official	124:6a4a5b7d7324	1066
bogdanm	0:9b334a45a8ff	1067	/* Check selected event flag */
bogdanm	0:9b334a45a8ff	1068	while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
bogdanm	0:9b334a45a8ff	1069	{
bogdanm	0:9b334a45a8ff	1070	/* Check if timeout is disabled (set to infinite wait) */
bogdanm	0:9b334a45a8ff	1071	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1072	{
bogdanm	0:9b334a45a8ff	1073	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	1074	{
bogdanm	0:9b334a45a8ff	1075	/* Update ADC state machine to timeout */
mbed_official	124:6a4a5b7d7324	1076	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1079	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1080
mbed_official	124:6a4a5b7d7324	1081	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1082	}
bogdanm	0:9b334a45a8ff	1083	}
bogdanm	0:9b334a45a8ff	1084	}
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086	/* Analog watchdog (level out of window) event */
mbed_official	124:6a4a5b7d7324	1087	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	1088	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
bogdanm	0:9b334a45a8ff	1089
bogdanm	0:9b334a45a8ff	1090	/* Clear ADC analog watchdog flag */
bogdanm	0:9b334a45a8ff	1091	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
bogdanm	0:9b334a45a8ff	1092
bogdanm	0:9b334a45a8ff	1093	/* Return ADC state */
bogdanm	0:9b334a45a8ff	1094	return HAL_OK;
bogdanm	0:9b334a45a8ff	1095	}
bogdanm	0:9b334a45a8ff	1096
bogdanm	0:9b334a45a8ff	1097	/**
bogdanm	0:9b334a45a8ff	1098	* @brief Enables ADC, starts conversion of regular group with interruption.
bogdanm	0:9b334a45a8ff	1099	* Interruptions enabled in this function:
bogdanm	0:9b334a45a8ff	1100	* - EOC (end of conversion of regular group)
bogdanm	0:9b334a45a8ff	1101	* Each of these interruptions has its dedicated callback function.
bogdanm	0:9b334a45a8ff	1102	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1103	* @retval HAL status
bogdanm	0:9b334a45a8ff	1104	*/
bogdanm	0:9b334a45a8ff	1105	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1106	{
bogdanm	0:9b334a45a8ff	1107	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1110	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112	/* Process locked */
bogdanm	0:9b334a45a8ff	1113	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1114
bogdanm	0:9b334a45a8ff	1115	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1116	tmp_hal_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	1117
bogdanm	0:9b334a45a8ff	1118	/* Start conversion if ADC is effectively enabled */
mbed_official	124:6a4a5b7d7324	1119	if (tmp_hal_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1120	{
mbed_official	124:6a4a5b7d7324	1121	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	1122	/* - Clear state bitfield related to regular group conversion results */
mbed_official	124:6a4a5b7d7324	1123	/* - Set state bitfield related to regular operation */
mbed_official	124:6a4a5b7d7324	1124	ADC_STATE_CLR_SET(hadc->State,
mbed_official	124:6a4a5b7d7324	1125	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR \| HAL_ADC_STATE_REG_EOSMP,
mbed_official	124:6a4a5b7d7324	1126	HAL_ADC_STATE_REG_BUSY);
mbed_official	124:6a4a5b7d7324	1127
mbed_official	124:6a4a5b7d7324	1128	/* Set group injected state (from auto-injection) and multimode state */
mbed_official	124:6a4a5b7d7324	1129	/* for all cases of multimode: independent mode, multimode ADC master */
mbed_official	124:6a4a5b7d7324	1130	/* or multimode ADC slave (for devices with several ADCs): */
mbed_official	124:6a4a5b7d7324	1131	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
bogdanm	0:9b334a45a8ff	1132	{
mbed_official	124:6a4a5b7d7324	1133	/* Set ADC state (ADC independent or master) */
mbed_official	124:6a4a5b7d7324	1134	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
mbed_official	124:6a4a5b7d7324	1135
mbed_official	124:6a4a5b7d7324	1136	/* If conversions on group regular are also triggering group injected, */
mbed_official	124:6a4a5b7d7324	1137	/* update ADC state. */
mbed_official	124:6a4a5b7d7324	1138	if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
mbed_official	124:6a4a5b7d7324	1139	{
mbed_official	124:6a4a5b7d7324	1140	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
mbed_official	124:6a4a5b7d7324	1141	}
bogdanm	0:9b334a45a8ff	1142	}
bogdanm	0:9b334a45a8ff	1143	else
bogdanm	0:9b334a45a8ff	1144	{
mbed_official	124:6a4a5b7d7324	1145	/* Set ADC state (ADC slave) */
mbed_official	124:6a4a5b7d7324	1146	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
mbed_official	124:6a4a5b7d7324	1147
mbed_official	124:6a4a5b7d7324	1148	/* If conversions on group regular are also triggering group injected, */
mbed_official	124:6a4a5b7d7324	1149	/* update ADC state. */
mbed_official	124:6a4a5b7d7324	1150	if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
mbed_official	124:6a4a5b7d7324	1151	{
mbed_official	124:6a4a5b7d7324	1152	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
mbed_official	124:6a4a5b7d7324	1153	}
bogdanm	0:9b334a45a8ff	1154	}
mbed_official	124:6a4a5b7d7324	1155
mbed_official	124:6a4a5b7d7324	1156	/* State machine update: Check if an injected conversion is ongoing */
mbed_official	124:6a4a5b7d7324	1157	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
mbed_official	124:6a4a5b7d7324	1158	{
mbed_official	124:6a4a5b7d7324	1159	/* Reset ADC error code fields related to conversions on group regular */
mbed_official	124:6a4a5b7d7324	1160	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR \| HAL_ADC_ERROR_DMA));
mbed_official	124:6a4a5b7d7324	1161	}
mbed_official	124:6a4a5b7d7324	1162	else
mbed_official	124:6a4a5b7d7324	1163	{
mbed_official	124:6a4a5b7d7324	1164	/* Reset ADC all error code fields */
mbed_official	124:6a4a5b7d7324	1165	ADC_CLEAR_ERRORCODE(hadc);
mbed_official	124:6a4a5b7d7324	1166	}
mbed_official	124:6a4a5b7d7324	1167
bogdanm	0:9b334a45a8ff	1168	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1169	/* Unlock before starting ADC conversions: in case of potential */
bogdanm	0:9b334a45a8ff	1170	/* interruption, to let the process to ADC IRQ Handler. */
bogdanm	0:9b334a45a8ff	1171	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1172
bogdanm	0:9b334a45a8ff	1173	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	1174	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	1175	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	1176
bogdanm	0:9b334a45a8ff	1177	/* Enable end of conversion interrupt for regular group */
bogdanm	0:9b334a45a8ff	1178	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	1179
bogdanm	0:9b334a45a8ff	1180	/* Enable conversion of regular group. */
bogdanm	0:9b334a45a8ff	1181	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	1182	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	1183	/* trigger event. */
mbed_official	124:6a4a5b7d7324	1184	/* Case of multimode enabled: */
mbed_official	124:6a4a5b7d7324	1185	/* - if ADC is slave, ADC is enabled only (conversion is not started). */
mbed_official	124:6a4a5b7d7324	1186	/* - if ADC is master, ADC is enabled and conversion is started. */
bogdanm	0:9b334a45a8ff	1187	if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
bogdanm	0:9b334a45a8ff	1188	ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
bogdanm	0:9b334a45a8ff	1189	{
bogdanm	0:9b334a45a8ff	1190	/* Start ADC conversion on regular group with SW start */
bogdanm	0:9b334a45a8ff	1191	SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART \| ADC_CR2_EXTTRIG));
bogdanm	0:9b334a45a8ff	1192	}
bogdanm	0:9b334a45a8ff	1193	else
bogdanm	0:9b334a45a8ff	1194	{
bogdanm	0:9b334a45a8ff	1195	/* Start ADC conversion on regular group with external trigger */
bogdanm	0:9b334a45a8ff	1196	SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
bogdanm	0:9b334a45a8ff	1197	}
bogdanm	0:9b334a45a8ff	1198	}
bogdanm	0:9b334a45a8ff	1199	else
bogdanm	0:9b334a45a8ff	1200	{
bogdanm	0:9b334a45a8ff	1201	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1202	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1203	}
bogdanm	0:9b334a45a8ff	1204
bogdanm	0:9b334a45a8ff	1205	/* Return function status */
bogdanm	0:9b334a45a8ff	1206	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	1207	}
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209	/**
bogdanm	0:9b334a45a8ff	1210	* @brief Stop ADC conversion of regular group (and injected group in
bogdanm	0:9b334a45a8ff	1211	* case of auto_injection mode), disable interrution of
bogdanm	0:9b334a45a8ff	1212	* end-of-conversion, disable ADC peripheral.
bogdanm	0:9b334a45a8ff	1213	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1214	* @retval None
bogdanm	0:9b334a45a8ff	1215	*/
bogdanm	0:9b334a45a8ff	1216	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1217	{
bogdanm	0:9b334a45a8ff	1218	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1219
bogdanm	0:9b334a45a8ff	1220	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1221	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1222
bogdanm	0:9b334a45a8ff	1223	/* Process locked */
bogdanm	0:9b334a45a8ff	1224	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1225
bogdanm	0:9b334a45a8ff	1226	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	1227	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	1228	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	1229
bogdanm	0:9b334a45a8ff	1230	/* Check if ADC is effectively disabled */
mbed_official	124:6a4a5b7d7324	1231	if (tmp_hal_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1232	{
bogdanm	0:9b334a45a8ff	1233	/* Disable ADC end of conversion interrupt for regular group */
bogdanm	0:9b334a45a8ff	1234	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	1235
mbed_official	124:6a4a5b7d7324	1236	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	1237	ADC_STATE_CLR_SET(hadc->State,
mbed_official	124:6a4a5b7d7324	1238	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
mbed_official	124:6a4a5b7d7324	1239	HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1240	}
bogdanm	0:9b334a45a8ff	1241
bogdanm	0:9b334a45a8ff	1242	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1243	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1244
bogdanm	0:9b334a45a8ff	1245	/* Return function status */
bogdanm	0:9b334a45a8ff	1246	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	1247	}
bogdanm	0:9b334a45a8ff	1248
bogdanm	0:9b334a45a8ff	1249	/**
bogdanm	0:9b334a45a8ff	1250	* @brief Enables ADC, starts conversion of regular group and transfers result
bogdanm	0:9b334a45a8ff	1251	* through DMA.
bogdanm	0:9b334a45a8ff	1252	* Interruptions enabled in this function:
bogdanm	0:9b334a45a8ff	1253	* - DMA transfer complete
bogdanm	0:9b334a45a8ff	1254	* - DMA half transfer
bogdanm	0:9b334a45a8ff	1255	* Each of these interruptions has its dedicated callback function.
bogdanm	0:9b334a45a8ff	1256	* @note For devices with several ADCs: This function is for single-ADC mode
bogdanm	0:9b334a45a8ff	1257	* only. For multimode, use the dedicated MultimodeStart function.
bogdanm	0:9b334a45a8ff	1258	* @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
bogdanm	0:9b334a45a8ff	1259	* on devices) have DMA capability.
bogdanm	0:9b334a45a8ff	1260	* ADC2 converted data can be transferred in dual ADC mode using DMA
bogdanm	0:9b334a45a8ff	1261	* of ADC1 (ADC master in multimode).
bogdanm	0:9b334a45a8ff	1262	* In case of using ADC1 with DMA on a device featuring 2 ADC
bogdanm	0:9b334a45a8ff	1263	* instances: ADC1 conversion register DR contains ADC1 conversion
bogdanm	0:9b334a45a8ff	1264	* result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last
bogdanm	0:9b334a45a8ff	1265	* conversion result (ADC1 register DR bits 16 to 27). Therefore, to
bogdanm	0:9b334a45a8ff	1266	* have DMA transferring the conversion results of ADC1 only, DMA must
bogdanm	0:9b334a45a8ff	1267	* be configured to transfer size: half word.
bogdanm	0:9b334a45a8ff	1268	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1269	* @param pData: The destination Buffer address.
bogdanm	0:9b334a45a8ff	1270	* @param Length: The length of data to be transferred from ADC peripheral to memory.
bogdanm	0:9b334a45a8ff	1271	* @retval None
bogdanm	0:9b334a45a8ff	1272	*/
bogdanm	0:9b334a45a8ff	1273	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
bogdanm	0:9b334a45a8ff	1274	{
bogdanm	0:9b334a45a8ff	1275	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1278	assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/* Verification if multimode is disabled (for devices with several ADC) */
bogdanm	0:9b334a45a8ff	1281	/* If multimode is enabled, dedicated function multimode conversion */
bogdanm	0:9b334a45a8ff	1282	/* start DMA must be used. */
bogdanm	0:9b334a45a8ff	1283	if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1284	{
bogdanm	0:9b334a45a8ff	1285	/* Process locked */
bogdanm	0:9b334a45a8ff	1286	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1287
bogdanm	0:9b334a45a8ff	1288	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1289	tmp_hal_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	1290
bogdanm	0:9b334a45a8ff	1291	/* Start conversion if ADC is effectively enabled */
mbed_official	124:6a4a5b7d7324	1292	if (tmp_hal_status == HAL_OK)
mbed_official	124:6a4a5b7d7324	1293	{
mbed_official	124:6a4a5b7d7324	1294	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	1295	/* - Clear state bitfield related to regular group conversion results */
mbed_official	124:6a4a5b7d7324	1296	/* - Set state bitfield related to regular operation */
mbed_official	124:6a4a5b7d7324	1297	ADC_STATE_CLR_SET(hadc->State,
mbed_official	124:6a4a5b7d7324	1298	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR \| HAL_ADC_STATE_REG_EOSMP,
mbed_official	124:6a4a5b7d7324	1299	HAL_ADC_STATE_REG_BUSY);
mbed_official	124:6a4a5b7d7324	1300
mbed_official	124:6a4a5b7d7324	1301	/* Set group injected state (from auto-injection) and multimode state */
mbed_official	124:6a4a5b7d7324	1302	/* for all cases of multimode: independent mode, multimode ADC master */
mbed_official	124:6a4a5b7d7324	1303	/* or multimode ADC slave (for devices with several ADCs): */
mbed_official	124:6a4a5b7d7324	1304	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
bogdanm	0:9b334a45a8ff	1305	{
mbed_official	124:6a4a5b7d7324	1306	/* Set ADC state (ADC independent or master) */
mbed_official	124:6a4a5b7d7324	1307	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
mbed_official	124:6a4a5b7d7324	1308
mbed_official	124:6a4a5b7d7324	1309	/* If conversions on group regular are also triggering group injected, */
mbed_official	124:6a4a5b7d7324	1310	/* update ADC state. */
mbed_official	124:6a4a5b7d7324	1311	if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
mbed_official	124:6a4a5b7d7324	1312	{
mbed_official	124:6a4a5b7d7324	1313	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
mbed_official	124:6a4a5b7d7324	1314	}
mbed_official	124:6a4a5b7d7324	1315	}
mbed_official	124:6a4a5b7d7324	1316	else
mbed_official	124:6a4a5b7d7324	1317	{
mbed_official	124:6a4a5b7d7324	1318	/* Set ADC state (ADC slave) */
mbed_official	124:6a4a5b7d7324	1319	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
mbed_official	124:6a4a5b7d7324	1320
mbed_official	124:6a4a5b7d7324	1321	/* If conversions on group regular are also triggering group injected, */
mbed_official	124:6a4a5b7d7324	1322	/* update ADC state. */
mbed_official	124:6a4a5b7d7324	1323	if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
mbed_official	124:6a4a5b7d7324	1324	{
mbed_official	124:6a4a5b7d7324	1325	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
mbed_official	124:6a4a5b7d7324	1326	}
mbed_official	124:6a4a5b7d7324	1327	}
mbed_official	124:6a4a5b7d7324	1328
bogdanm	0:9b334a45a8ff	1329	/* State machine update: Check if an injected conversion is ongoing */
mbed_official	124:6a4a5b7d7324	1330	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
bogdanm	0:9b334a45a8ff	1331	{
mbed_official	124:6a4a5b7d7324	1332	/* Reset ADC error code fields related to conversions on group regular */
mbed_official	124:6a4a5b7d7324	1333	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR \| HAL_ADC_ERROR_DMA));
bogdanm	0:9b334a45a8ff	1334	}
bogdanm	0:9b334a45a8ff	1335	else
bogdanm	0:9b334a45a8ff	1336	{
mbed_official	124:6a4a5b7d7324	1337	/* Reset ADC all error code fields */
mbed_official	124:6a4a5b7d7324	1338	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	1339	}
bogdanm	0:9b334a45a8ff	1340
bogdanm	0:9b334a45a8ff	1341	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1342	/* Unlock before starting ADC conversions: in case of potential */
bogdanm	0:9b334a45a8ff	1343	/* interruption, to let the process to ADC IRQ Handler. */
bogdanm	0:9b334a45a8ff	1344	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1345
bogdanm	0:9b334a45a8ff	1346	/* Set the DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1347	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
bogdanm	0:9b334a45a8ff	1348
bogdanm	0:9b334a45a8ff	1349	/* Set the DMA half transfer complete callback */
bogdanm	0:9b334a45a8ff	1350	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1353	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
bogdanm	0:9b334a45a8ff	1354
bogdanm	0:9b334a45a8ff	1355
bogdanm	0:9b334a45a8ff	1356	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
bogdanm	0:9b334a45a8ff	1357	/* start (in case of SW start): */
bogdanm	0:9b334a45a8ff	1358
bogdanm	0:9b334a45a8ff	1359	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	1360	/* (To ensure of no unknown state from potential previous ADC */
bogdanm	0:9b334a45a8ff	1361	/* operations) */
bogdanm	0:9b334a45a8ff	1362	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	1363
bogdanm	0:9b334a45a8ff	1364	/* Enable ADC DMA mode */
bogdanm	0:9b334a45a8ff	1365	SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
bogdanm	0:9b334a45a8ff	1366
bogdanm	0:9b334a45a8ff	1367	/* Start the DMA channel */
bogdanm	0:9b334a45a8ff	1368	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1369
bogdanm	0:9b334a45a8ff	1370	/* Enable conversion of regular group. */
bogdanm	0:9b334a45a8ff	1371	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	1372	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	1373	/* trigger event. */
bogdanm	0:9b334a45a8ff	1374	if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	1375	{
bogdanm	0:9b334a45a8ff	1376	/* Start ADC conversion on regular group with SW start */
bogdanm	0:9b334a45a8ff	1377	SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART \| ADC_CR2_EXTTRIG));
bogdanm	0:9b334a45a8ff	1378	}
bogdanm	0:9b334a45a8ff	1379	else
bogdanm	0:9b334a45a8ff	1380	{
bogdanm	0:9b334a45a8ff	1381	/* Start ADC conversion on regular group with external trigger */
bogdanm	0:9b334a45a8ff	1382	SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
bogdanm	0:9b334a45a8ff	1383	}
bogdanm	0:9b334a45a8ff	1384	}
bogdanm	0:9b334a45a8ff	1385	else
bogdanm	0:9b334a45a8ff	1386	{
bogdanm	0:9b334a45a8ff	1387	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1388	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1389	}
bogdanm	0:9b334a45a8ff	1390	}
bogdanm	0:9b334a45a8ff	1391	else
bogdanm	0:9b334a45a8ff	1392	{
bogdanm	0:9b334a45a8ff	1393	tmp_hal_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1394	}
bogdanm	0:9b334a45a8ff	1395
bogdanm	0:9b334a45a8ff	1396	/* Return function status */
bogdanm	0:9b334a45a8ff	1397	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	1398	}
bogdanm	0:9b334a45a8ff	1399
bogdanm	0:9b334a45a8ff	1400	/**
bogdanm	0:9b334a45a8ff	1401	* @brief Stop ADC conversion of regular group (and injected group in
bogdanm	0:9b334a45a8ff	1402	* case of auto_injection mode), disable ADC DMA transfer, disable
bogdanm	0:9b334a45a8ff	1403	* ADC peripheral.
bogdanm	0:9b334a45a8ff	1404	* @note: ADC peripheral disable is forcing stop of potential
bogdanm	0:9b334a45a8ff	1405	* conversion on injected group. If injected group is under use, it
bogdanm	0:9b334a45a8ff	1406	* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
bogdanm	0:9b334a45a8ff	1407	* @note For devices with several ADCs: This function is for single-ADC mode
bogdanm	0:9b334a45a8ff	1408	* only. For multimode, use the dedicated MultimodeStop function.
bogdanm	0:9b334a45a8ff	1409	* @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
bogdanm	0:9b334a45a8ff	1410	* on devices) have DMA capability.
bogdanm	0:9b334a45a8ff	1411	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1412	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1413	*/
bogdanm	0:9b334a45a8ff	1414	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1415	{
bogdanm	0:9b334a45a8ff	1416	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1417
bogdanm	0:9b334a45a8ff	1418	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1419	assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	/* Process locked */
bogdanm	0:9b334a45a8ff	1422	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1423
bogdanm	0:9b334a45a8ff	1424	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	1425	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	1426	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	1427
bogdanm	0:9b334a45a8ff	1428	/* Check if ADC is effectively disabled */
mbed_official	124:6a4a5b7d7324	1429	if (tmp_hal_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1430	{
bogdanm	0:9b334a45a8ff	1431	/* Disable ADC DMA mode */
bogdanm	0:9b334a45a8ff	1432	CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	/* Disable the DMA channel (in case of DMA in circular mode or stop while */
bogdanm	0:9b334a45a8ff	1435	/* DMA transfer is on going) */
bogdanm	0:9b334a45a8ff	1436	tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	/* Check if DMA channel effectively disabled */
mbed_official	124:6a4a5b7d7324	1439	if (tmp_hal_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1440	{
mbed_official	124:6a4a5b7d7324	1441	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	1442	ADC_STATE_CLR_SET(hadc->State,
mbed_official	124:6a4a5b7d7324	1443	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
mbed_official	124:6a4a5b7d7324	1444	HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1445	}
bogdanm	0:9b334a45a8ff	1446	else
bogdanm	0:9b334a45a8ff	1447	{
bogdanm	0:9b334a45a8ff	1448	/* Update ADC state machine to error */
mbed_official	124:6a4a5b7d7324	1449	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
bogdanm	0:9b334a45a8ff	1450	}
bogdanm	0:9b334a45a8ff	1451	}
bogdanm	0:9b334a45a8ff	1452
bogdanm	0:9b334a45a8ff	1453	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1454	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1455
bogdanm	0:9b334a45a8ff	1456	/* Return function status */
bogdanm	0:9b334a45a8ff	1457	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	1458	}
bogdanm	0:9b334a45a8ff	1459
bogdanm	0:9b334a45a8ff	1460	/**
bogdanm	0:9b334a45a8ff	1461	* @brief Get ADC regular group conversion result.
mbed_official	124:6a4a5b7d7324	1462	* @note Reading register DR automatically clears ADC flag EOC
mbed_official	124:6a4a5b7d7324	1463	* (ADC group regular end of unitary conversion).
mbed_official	124:6a4a5b7d7324	1464	* @note This function does not clear ADC flag EOS
mbed_official	124:6a4a5b7d7324	1465	* (ADC group regular end of sequence conversion).
mbed_official	124:6a4a5b7d7324	1466	* Occurrence of flag EOS rising:
mbed_official	124:6a4a5b7d7324	1467	* - If sequencer is composed of 1 rank, flag EOS is equivalent
mbed_official	124:6a4a5b7d7324	1468	* to flag EOC.
mbed_official	124:6a4a5b7d7324	1469	* - If sequencer is composed of several ranks, during the scan
mbed_official	124:6a4a5b7d7324	1470	* sequence flag EOC only is raised, at the end of the scan sequence
mbed_official	124:6a4a5b7d7324	1471	* both flags EOC and EOS are raised.
mbed_official	124:6a4a5b7d7324	1472	* To clear this flag, either use function:
mbed_official	124:6a4a5b7d7324	1473	* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
mbed_official	124:6a4a5b7d7324	1474	* model polling: @ref HAL_ADC_PollForConversion()
mbed_official	124:6a4a5b7d7324	1475	* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
bogdanm	0:9b334a45a8ff	1476	* @param hadc: ADC handle
mbed_official	124:6a4a5b7d7324	1477	* @retval ADC group regular conversion data
bogdanm	0:9b334a45a8ff	1478	*/
bogdanm	0:9b334a45a8ff	1479	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1480	{
bogdanm	0:9b334a45a8ff	1481	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1482	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1483
bogdanm	0:9b334a45a8ff	1484	/* Note: EOC flag is not cleared here by software because automatically */
bogdanm	0:9b334a45a8ff	1485	/* cleared by hardware when reading register DR. */
bogdanm	0:9b334a45a8ff	1486
bogdanm	0:9b334a45a8ff	1487	/* Return ADC converted value */
bogdanm	0:9b334a45a8ff	1488	return hadc->Instance->DR;
bogdanm	0:9b334a45a8ff	1489	}
bogdanm	0:9b334a45a8ff	1490
bogdanm	0:9b334a45a8ff	1491	/**
bogdanm	0:9b334a45a8ff	1492	* @brief Handles ADC interrupt request
bogdanm	0:9b334a45a8ff	1493	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1494	* @retval None
bogdanm	0:9b334a45a8ff	1495	*/
bogdanm	0:9b334a45a8ff	1496	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1497	{
bogdanm	0:9b334a45a8ff	1498	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1499	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1500	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	1501	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
bogdanm	0:9b334a45a8ff	1502
bogdanm	0:9b334a45a8ff	1503
bogdanm	0:9b334a45a8ff	1504	/* ========== Check End of Conversion flag for regular group ========== */
bogdanm	0:9b334a45a8ff	1505	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
bogdanm	0:9b334a45a8ff	1506	{
bogdanm	0:9b334a45a8ff	1507	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
bogdanm	0:9b334a45a8ff	1508	{
bogdanm	0:9b334a45a8ff	1509	/* Update state machine on conversion status if not in error state */
mbed_official	124:6a4a5b7d7324	1510	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
bogdanm	0:9b334a45a8ff	1511	{
mbed_official	124:6a4a5b7d7324	1512	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	1513	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
bogdanm	0:9b334a45a8ff	1514	}
bogdanm	0:9b334a45a8ff	1515
mbed_official	124:6a4a5b7d7324	1516	/* Determine whether any further conversion upcoming on group regular */
mbed_official	124:6a4a5b7d7324	1517	/* by external trigger, continuous mode or scan sequence on going. */
mbed_official	124:6a4a5b7d7324	1518	/* Note: On STM32F1 devices, in case of sequencer enabled */
mbed_official	124:6a4a5b7d7324	1519	/* (several ranks selected), end of conversion flag is raised */
mbed_official	124:6a4a5b7d7324	1520	/* at the end of the sequence. */
bogdanm	0:9b334a45a8ff	1521	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
bogdanm	0:9b334a45a8ff	1522	(hadc->Init.ContinuousConvMode == DISABLE) )
bogdanm	0:9b334a45a8ff	1523	{
mbed_official	124:6a4a5b7d7324	1524	/* Disable ADC end of conversion interrupt on group regular */
bogdanm	0:9b334a45a8ff	1525	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
mbed_official	124:6a4a5b7d7324	1526
mbed_official	124:6a4a5b7d7324	1527	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	1528	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
mbed_official	124:6a4a5b7d7324	1529
mbed_official	124:6a4a5b7d7324	1530	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
mbed_official	124:6a4a5b7d7324	1531	{
mbed_official	124:6a4a5b7d7324	1532	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
mbed_official	124:6a4a5b7d7324	1533	}
bogdanm	0:9b334a45a8ff	1534	}
bogdanm	0:9b334a45a8ff	1535
bogdanm	0:9b334a45a8ff	1536	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	1537	HAL_ADC_ConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1538
bogdanm	0:9b334a45a8ff	1539	/* Clear regular group conversion flag */
bogdanm	0:9b334a45a8ff	1540	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT \| ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	1541	}
bogdanm	0:9b334a45a8ff	1542	}
bogdanm	0:9b334a45a8ff	1543
bogdanm	0:9b334a45a8ff	1544	/* ========== Check End of Conversion flag for injected group ========== */
bogdanm	0:9b334a45a8ff	1545	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
bogdanm	0:9b334a45a8ff	1546	{
bogdanm	0:9b334a45a8ff	1547	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
bogdanm	0:9b334a45a8ff	1548	{
bogdanm	0:9b334a45a8ff	1549	/* Update state machine on conversion status if not in error state */
mbed_official	124:6a4a5b7d7324	1550	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
bogdanm	0:9b334a45a8ff	1551	{
mbed_official	124:6a4a5b7d7324	1552	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	1553	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
bogdanm	0:9b334a45a8ff	1554	}
bogdanm	0:9b334a45a8ff	1555
mbed_official	124:6a4a5b7d7324	1556	/* Determine whether any further conversion upcoming on group injected */
mbed_official	124:6a4a5b7d7324	1557	/* by external trigger, scan sequence on going or by automatic injected */
mbed_official	124:6a4a5b7d7324	1558	/* conversion from group regular (same conditions as group regular */
mbed_official	124:6a4a5b7d7324	1559	/* interruption disabling above). */
mbed_official	124:6a4a5b7d7324	1560	/* Note: On STM32F1 devices, in case of sequencer enabled */
mbed_official	124:6a4a5b7d7324	1561	/* (several ranks selected), end of conversion flag is raised */
mbed_official	124:6a4a5b7d7324	1562	/* at the end of the sequence. */
bogdanm	0:9b334a45a8ff	1563	if(ADC_IS_SOFTWARE_START_INJECTED(hadc) \|\|
bogdanm	0:9b334a45a8ff	1564	(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
bogdanm	0:9b334a45a8ff	1565	(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
bogdanm	0:9b334a45a8ff	1566	(hadc->Init.ContinuousConvMode == DISABLE) ) ) )
bogdanm	0:9b334a45a8ff	1567	{
mbed_official	124:6a4a5b7d7324	1568	/* Disable ADC end of conversion interrupt on group injected */
bogdanm	0:9b334a45a8ff	1569	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
mbed_official	124:6a4a5b7d7324	1570
mbed_official	124:6a4a5b7d7324	1571	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	1572	CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
mbed_official	124:6a4a5b7d7324	1573
mbed_official	124:6a4a5b7d7324	1574	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
mbed_official	124:6a4a5b7d7324	1575	{
mbed_official	124:6a4a5b7d7324	1576	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
mbed_official	124:6a4a5b7d7324	1577	}
bogdanm	0:9b334a45a8ff	1578	}
bogdanm	0:9b334a45a8ff	1579
bogdanm	0:9b334a45a8ff	1580	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	1581	HAL_ADCEx_InjectedConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1582
bogdanm	0:9b334a45a8ff	1583	/* Clear injected group conversion flag */
bogdanm	0:9b334a45a8ff	1584	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT \| ADC_FLAG_JEOC));
bogdanm	0:9b334a45a8ff	1585	}
bogdanm	0:9b334a45a8ff	1586	}
bogdanm	0:9b334a45a8ff	1587
bogdanm	0:9b334a45a8ff	1588	/* ========== Check Analog watchdog flags ========== */
bogdanm	0:9b334a45a8ff	1589	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
bogdanm	0:9b334a45a8ff	1590	{
bogdanm	0:9b334a45a8ff	1591	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
bogdanm	0:9b334a45a8ff	1592	{
mbed_official	124:6a4a5b7d7324	1593	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	1594	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
bogdanm	0:9b334a45a8ff	1595
bogdanm	0:9b334a45a8ff	1596	/* Level out of window callback */
bogdanm	0:9b334a45a8ff	1597	HAL_ADC_LevelOutOfWindowCallback(hadc);
bogdanm	0:9b334a45a8ff	1598
mbed_official	124:6a4a5b7d7324	1599	/* Clear the ADC analog watchdog flag */
mbed_official	124:6a4a5b7d7324	1600	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
bogdanm	0:9b334a45a8ff	1601	}
bogdanm	0:9b334a45a8ff	1602	}
bogdanm	0:9b334a45a8ff	1603
bogdanm	0:9b334a45a8ff	1604	}
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	/**
bogdanm	0:9b334a45a8ff	1607	* @brief Conversion complete callback in non blocking mode
bogdanm	0:9b334a45a8ff	1608	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1609	* @retval None
bogdanm	0:9b334a45a8ff	1610	*/
bogdanm	0:9b334a45a8ff	1611	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1612	{
mbed_official	124:6a4a5b7d7324	1613	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1614	UNUSED(hadc);
bogdanm	0:9b334a45a8ff	1615	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1616	function HAL_ADC_ConvCpltCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1617	*/
bogdanm	0:9b334a45a8ff	1618	}
bogdanm	0:9b334a45a8ff	1619
bogdanm	0:9b334a45a8ff	1620	/**
bogdanm	0:9b334a45a8ff	1621	* @brief Conversion DMA half-transfer callback in non blocking mode
bogdanm	0:9b334a45a8ff	1622	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1623	* @retval None
bogdanm	0:9b334a45a8ff	1624	*/
bogdanm	0:9b334a45a8ff	1625	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1626	{
mbed_official	124:6a4a5b7d7324	1627	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1628	UNUSED(hadc);
bogdanm	0:9b334a45a8ff	1629	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1630	function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1631	*/
bogdanm	0:9b334a45a8ff	1632	}
bogdanm	0:9b334a45a8ff	1633
bogdanm	0:9b334a45a8ff	1634	/**
bogdanm	0:9b334a45a8ff	1635	* @brief Analog watchdog callback in non blocking mode.
bogdanm	0:9b334a45a8ff	1636	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1637	* @retval None
bogdanm	0:9b334a45a8ff	1638	*/
bogdanm	0:9b334a45a8ff	1639	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1640	{
mbed_official	124:6a4a5b7d7324	1641	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1642	UNUSED(hadc);
bogdanm	0:9b334a45a8ff	1643	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1644	function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1645	*/
bogdanm	0:9b334a45a8ff	1646	}
bogdanm	0:9b334a45a8ff	1647
bogdanm	0:9b334a45a8ff	1648	/**
bogdanm	0:9b334a45a8ff	1649	* @brief ADC error callback in non blocking mode
bogdanm	0:9b334a45a8ff	1650	* (ADC conversion with interruption or transfer by DMA)
bogdanm	0:9b334a45a8ff	1651	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1652	* @retval None
bogdanm	0:9b334a45a8ff	1653	*/
bogdanm	0:9b334a45a8ff	1654	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
bogdanm	0:9b334a45a8ff	1655	{
mbed_official	124:6a4a5b7d7324	1656	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1657	UNUSED(hadc);
bogdanm	0:9b334a45a8ff	1658	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1659	function HAL_ADC_ErrorCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1660	*/
bogdanm	0:9b334a45a8ff	1661	}
bogdanm	0:9b334a45a8ff	1662
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664	/**
bogdanm	0:9b334a45a8ff	1665	* @}
bogdanm	0:9b334a45a8ff	1666	*/
bogdanm	0:9b334a45a8ff	1667
bogdanm	0:9b334a45a8ff	1668	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1669	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	1670	*
bogdanm	0:9b334a45a8ff	1671	@verbatim
bogdanm	0:9b334a45a8ff	1672	===============================================================================
bogdanm	0:9b334a45a8ff	1673	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	1674	===============================================================================
bogdanm	0:9b334a45a8ff	1675	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1676	(+) Configure channels on regular group
bogdanm	0:9b334a45a8ff	1677	(+) Configure the analog watchdog
bogdanm	0:9b334a45a8ff	1678
bogdanm	0:9b334a45a8ff	1679	@endverbatim
bogdanm	0:9b334a45a8ff	1680	* @{
bogdanm	0:9b334a45a8ff	1681	*/
bogdanm	0:9b334a45a8ff	1682
bogdanm	0:9b334a45a8ff	1683	/**
bogdanm	0:9b334a45a8ff	1684	* @brief Configures the the selected channel to be linked to the regular
bogdanm	0:9b334a45a8ff	1685	* group.
bogdanm	0:9b334a45a8ff	1686	* @note In case of usage of internal measurement channels:
bogdanm	0:9b334a45a8ff	1687	* Vbat/VrefInt/TempSensor.
bogdanm	0:9b334a45a8ff	1688	* These internal paths can be be disabled using function
bogdanm	0:9b334a45a8ff	1689	* HAL_ADC_DeInit().
bogdanm	0:9b334a45a8ff	1690	* @note Possibility to update parameters on the fly:
bogdanm	0:9b334a45a8ff	1691	* This function initializes channel into regular group, following
bogdanm	0:9b334a45a8ff	1692	* calls to this function can be used to reconfigure some parameters
bogdanm	0:9b334a45a8ff	1693	* of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
bogdanm	0:9b334a45a8ff	1694	* the ADC.
bogdanm	0:9b334a45a8ff	1695	* The setting of these parameters is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	1696	* For parameters constraints, see comments of structure
bogdanm	0:9b334a45a8ff	1697	* "ADC_ChannelConfTypeDef".
bogdanm	0:9b334a45a8ff	1698	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1699	* @param sConfig: Structure of ADC channel for regular group.
bogdanm	0:9b334a45a8ff	1700	* @retval HAL status
bogdanm	0:9b334a45a8ff	1701	*/
bogdanm	0:9b334a45a8ff	1702	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
bogdanm	0:9b334a45a8ff	1703	{
bogdanm	0:9b334a45a8ff	1704	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1705	__IO uint32_t wait_loop_index = 0;
bogdanm	0:9b334a45a8ff	1706
bogdanm	0:9b334a45a8ff	1707	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1708	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1709	assert_param(IS_ADC_CHANNEL(sConfig->Channel));
bogdanm	0:9b334a45a8ff	1710	assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
bogdanm	0:9b334a45a8ff	1711	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
bogdanm	0:9b334a45a8ff	1712
bogdanm	0:9b334a45a8ff	1713	/* Process locked */
bogdanm	0:9b334a45a8ff	1714	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1715
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	/* Regular sequence configuration */
bogdanm	0:9b334a45a8ff	1718	/* For Rank 1 to 6 */
bogdanm	0:9b334a45a8ff	1719	if (sConfig->Rank < 7)
bogdanm	0:9b334a45a8ff	1720	{
bogdanm	0:9b334a45a8ff	1721	MODIFY_REG(hadc->Instance->SQR3 ,
bogdanm	0:9b334a45a8ff	1722	ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
bogdanm	0:9b334a45a8ff	1723	ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
bogdanm	0:9b334a45a8ff	1724	}
bogdanm	0:9b334a45a8ff	1725	/* For Rank 7 to 12 */
bogdanm	0:9b334a45a8ff	1726	else if (sConfig->Rank < 13)
bogdanm	0:9b334a45a8ff	1727	{
bogdanm	0:9b334a45a8ff	1728	MODIFY_REG(hadc->Instance->SQR2 ,
bogdanm	0:9b334a45a8ff	1729	ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
bogdanm	0:9b334a45a8ff	1730	ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
bogdanm	0:9b334a45a8ff	1731	}
bogdanm	0:9b334a45a8ff	1732	/* For Rank 13 to 16 */
bogdanm	0:9b334a45a8ff	1733	else
bogdanm	0:9b334a45a8ff	1734	{
bogdanm	0:9b334a45a8ff	1735	MODIFY_REG(hadc->Instance->SQR1 ,
bogdanm	0:9b334a45a8ff	1736	ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
bogdanm	0:9b334a45a8ff	1737	ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
bogdanm	0:9b334a45a8ff	1738	}
bogdanm	0:9b334a45a8ff	1739
bogdanm	0:9b334a45a8ff	1740
bogdanm	0:9b334a45a8ff	1741	/* Channel sampling time configuration */
bogdanm	0:9b334a45a8ff	1742	/* For channels 10 to 17 */
bogdanm	0:9b334a45a8ff	1743	if (sConfig->Channel >= ADC_CHANNEL_10)
bogdanm	0:9b334a45a8ff	1744	{
bogdanm	0:9b334a45a8ff	1745	MODIFY_REG(hadc->Instance->SMPR1 ,
bogdanm	0:9b334a45a8ff	1746	ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
bogdanm	0:9b334a45a8ff	1747	ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
bogdanm	0:9b334a45a8ff	1748	}
bogdanm	0:9b334a45a8ff	1749	else /* For channels 0 to 9 */
bogdanm	0:9b334a45a8ff	1750	{
bogdanm	0:9b334a45a8ff	1751	MODIFY_REG(hadc->Instance->SMPR2 ,
bogdanm	0:9b334a45a8ff	1752	ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
bogdanm	0:9b334a45a8ff	1753	ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
bogdanm	0:9b334a45a8ff	1754	}
bogdanm	0:9b334a45a8ff	1755
bogdanm	0:9b334a45a8ff	1756	/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
bogdanm	0:9b334a45a8ff	1757	/* and VREFINT measurement path. */
bogdanm	0:9b334a45a8ff	1758	if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) \|\|
bogdanm	0:9b334a45a8ff	1759	(sConfig->Channel == ADC_CHANNEL_VREFINT) )
bogdanm	0:9b334a45a8ff	1760	{
bogdanm	0:9b334a45a8ff	1761	/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
bogdanm	0:9b334a45a8ff	1762	/* measurement channels (VrefInt/TempSensor). If these channels are */
bogdanm	0:9b334a45a8ff	1763	/* intended to be set on other ADC instances, an error is reported. */
bogdanm	0:9b334a45a8ff	1764	if (hadc->Instance == ADC1)
bogdanm	0:9b334a45a8ff	1765	{
bogdanm	0:9b334a45a8ff	1766	if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
bogdanm	0:9b334a45a8ff	1767	{
bogdanm	0:9b334a45a8ff	1768	SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
bogdanm	0:9b334a45a8ff	1769
bogdanm	0:9b334a45a8ff	1770	if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
bogdanm	0:9b334a45a8ff	1771	{
bogdanm	0:9b334a45a8ff	1772	/* Delay for temperature sensor stabilization time */
bogdanm	0:9b334a45a8ff	1773	/* Compute number of CPU cycles to wait for */
bogdanm	0:9b334a45a8ff	1774	wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
bogdanm	0:9b334a45a8ff	1775	while(wait_loop_index != 0)
bogdanm	0:9b334a45a8ff	1776	{
bogdanm	0:9b334a45a8ff	1777	wait_loop_index--;
bogdanm	0:9b334a45a8ff	1778	}
bogdanm	0:9b334a45a8ff	1779	}
bogdanm	0:9b334a45a8ff	1780	}
bogdanm	0:9b334a45a8ff	1781	}
bogdanm	0:9b334a45a8ff	1782	else
bogdanm	0:9b334a45a8ff	1783	{
bogdanm	0:9b334a45a8ff	1784	/* Update ADC state machine to error */
mbed_official	124:6a4a5b7d7324	1785	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	1786
bogdanm	0:9b334a45a8ff	1787	tmp_hal_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1788	}
bogdanm	0:9b334a45a8ff	1789	}
bogdanm	0:9b334a45a8ff	1790
bogdanm	0:9b334a45a8ff	1791	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1792	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1793
bogdanm	0:9b334a45a8ff	1794	/* Return function status */
bogdanm	0:9b334a45a8ff	1795	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	1796	}
bogdanm	0:9b334a45a8ff	1797
bogdanm	0:9b334a45a8ff	1798	/**
bogdanm	0:9b334a45a8ff	1799	* @brief Configures the analog watchdog.
mbed_official	124:6a4a5b7d7324	1800	* @note Analog watchdog thresholds can be modified while ADC conversion
mbed_official	124:6a4a5b7d7324	1801	* is on going.
mbed_official	124:6a4a5b7d7324	1802	* In this case, some constraints must be taken into account:
mbed_official	124:6a4a5b7d7324	1803	* the programmed threshold values are effective from the next
mbed_official	124:6a4a5b7d7324	1804	* ADC EOC (end of unitary conversion).
mbed_official	124:6a4a5b7d7324	1805	* Considering that registers write delay may happen due to
mbed_official	124:6a4a5b7d7324	1806	* bus activity, this might cause an uncertainty on the
mbed_official	124:6a4a5b7d7324	1807	* effective timing of the new programmed threshold values.
bogdanm	0:9b334a45a8ff	1808	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1809	* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
bogdanm	0:9b334a45a8ff	1810	* @retval HAL status
bogdanm	0:9b334a45a8ff	1811	*/
bogdanm	0:9b334a45a8ff	1812	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
bogdanm	0:9b334a45a8ff	1813	{
bogdanm	0:9b334a45a8ff	1814	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1815	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1816	assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
bogdanm	0:9b334a45a8ff	1817	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
bogdanm	0:9b334a45a8ff	1818	assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
bogdanm	0:9b334a45a8ff	1819	assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
bogdanm	0:9b334a45a8ff	1820
bogdanm	0:9b334a45a8ff	1821	if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\|
bogdanm	0:9b334a45a8ff	1822	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\|
bogdanm	0:9b334a45a8ff	1823	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
bogdanm	0:9b334a45a8ff	1824	{
bogdanm	0:9b334a45a8ff	1825	assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
bogdanm	0:9b334a45a8ff	1826	}
bogdanm	0:9b334a45a8ff	1827
bogdanm	0:9b334a45a8ff	1828	/* Process locked */
bogdanm	0:9b334a45a8ff	1829	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1830
bogdanm	0:9b334a45a8ff	1831	/* Analog watchdog configuration */
bogdanm	0:9b334a45a8ff	1832
bogdanm	0:9b334a45a8ff	1833	/* Configure ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	1834	if(AnalogWDGConfig->ITMode == ENABLE)
bogdanm	0:9b334a45a8ff	1835	{
bogdanm	0:9b334a45a8ff	1836	/* Enable the ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	1837	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
bogdanm	0:9b334a45a8ff	1838	}
bogdanm	0:9b334a45a8ff	1839	else
bogdanm	0:9b334a45a8ff	1840	{
bogdanm	0:9b334a45a8ff	1841	/* Disable the ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	1842	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
bogdanm	0:9b334a45a8ff	1843	}
bogdanm	0:9b334a45a8ff	1844
bogdanm	0:9b334a45a8ff	1845	/* Configuration of analog watchdog: */
bogdanm	0:9b334a45a8ff	1846	/* - Set the analog watchdog enable mode: regular and/or injected groups, */
bogdanm	0:9b334a45a8ff	1847	/* one or all channels. */
bogdanm	0:9b334a45a8ff	1848	/* - Set the Analog watchdog channel (is not used if watchdog */
bogdanm	0:9b334a45a8ff	1849	/* mode "all channels": ADC_CFGR_AWD1SGL=0). */
bogdanm	0:9b334a45a8ff	1850	MODIFY_REG(hadc->Instance->CR1 ,
bogdanm	0:9b334a45a8ff	1851	ADC_CR1_AWDSGL \|
bogdanm	0:9b334a45a8ff	1852	ADC_CR1_JAWDEN \|
bogdanm	0:9b334a45a8ff	1853	ADC_CR1_AWDEN \|
bogdanm	0:9b334a45a8ff	1854	ADC_CR1_AWDCH ,
bogdanm	0:9b334a45a8ff	1855	AnalogWDGConfig->WatchdogMode \|
bogdanm	0:9b334a45a8ff	1856	AnalogWDGConfig->Channel );
bogdanm	0:9b334a45a8ff	1857
bogdanm	0:9b334a45a8ff	1858	/* Set the high threshold */
bogdanm	0:9b334a45a8ff	1859	WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
bogdanm	0:9b334a45a8ff	1860
bogdanm	0:9b334a45a8ff	1861	/* Set the low threshold */
bogdanm	0:9b334a45a8ff	1862	WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
bogdanm	0:9b334a45a8ff	1863
bogdanm	0:9b334a45a8ff	1864	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1865	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1866
bogdanm	0:9b334a45a8ff	1867	/* Return function status */
bogdanm	0:9b334a45a8ff	1868	return HAL_OK;
bogdanm	0:9b334a45a8ff	1869	}
bogdanm	0:9b334a45a8ff	1870
bogdanm	0:9b334a45a8ff	1871
bogdanm	0:9b334a45a8ff	1872	/**
bogdanm	0:9b334a45a8ff	1873	* @}
bogdanm	0:9b334a45a8ff	1874	*/
bogdanm	0:9b334a45a8ff	1875
bogdanm	0:9b334a45a8ff	1876
bogdanm	0:9b334a45a8ff	1877	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
bogdanm	0:9b334a45a8ff	1878	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	1879	*
bogdanm	0:9b334a45a8ff	1880	@verbatim
bogdanm	0:9b334a45a8ff	1881	===============================================================================
bogdanm	0:9b334a45a8ff	1882	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1883	===============================================================================
bogdanm	0:9b334a45a8ff	1884	[..]
bogdanm	0:9b334a45a8ff	1885	This subsection provides functions to get in run-time the status of the
bogdanm	0:9b334a45a8ff	1886	peripheral.
bogdanm	0:9b334a45a8ff	1887	(+) Check the ADC state
bogdanm	0:9b334a45a8ff	1888	(+) Check the ADC error code
bogdanm	0:9b334a45a8ff	1889
bogdanm	0:9b334a45a8ff	1890	@endverbatim
bogdanm	0:9b334a45a8ff	1891	* @{
bogdanm	0:9b334a45a8ff	1892	*/
bogdanm	0:9b334a45a8ff	1893
bogdanm	0:9b334a45a8ff	1894	/**
bogdanm	0:9b334a45a8ff	1895	* @brief return the ADC state
bogdanm	0:9b334a45a8ff	1896	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1897	* @retval HAL state
bogdanm	0:9b334a45a8ff	1898	*/
mbed_official	124:6a4a5b7d7324	1899	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1900	{
bogdanm	0:9b334a45a8ff	1901	/* Return ADC state */
bogdanm	0:9b334a45a8ff	1902	return hadc->State;
bogdanm	0:9b334a45a8ff	1903	}
bogdanm	0:9b334a45a8ff	1904
bogdanm	0:9b334a45a8ff	1905	/**
bogdanm	0:9b334a45a8ff	1906	* @brief Return the ADC error code
bogdanm	0:9b334a45a8ff	1907	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1908	* @retval ADC Error Code
bogdanm	0:9b334a45a8ff	1909	*/
bogdanm	0:9b334a45a8ff	1910	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
bogdanm	0:9b334a45a8ff	1911	{
bogdanm	0:9b334a45a8ff	1912	return hadc->ErrorCode;
bogdanm	0:9b334a45a8ff	1913	}
bogdanm	0:9b334a45a8ff	1914
bogdanm	0:9b334a45a8ff	1915	/**
bogdanm	0:9b334a45a8ff	1916	* @}
bogdanm	0:9b334a45a8ff	1917	*/
bogdanm	0:9b334a45a8ff	1918
bogdanm	0:9b334a45a8ff	1919	/**
bogdanm	0:9b334a45a8ff	1920	* @}
bogdanm	0:9b334a45a8ff	1921	*/
bogdanm	0:9b334a45a8ff	1922
bogdanm	0:9b334a45a8ff	1923	/** @defgroup ADC_Private_Functions ADC Private Functions
bogdanm	0:9b334a45a8ff	1924	* @{
bogdanm	0:9b334a45a8ff	1925	*/
bogdanm	0:9b334a45a8ff	1926
bogdanm	0:9b334a45a8ff	1927	/**
bogdanm	0:9b334a45a8ff	1928	* @brief Enable the selected ADC.
bogdanm	0:9b334a45a8ff	1929	* @note Prerequisite condition to use this function: ADC must be disabled
bogdanm	0:9b334a45a8ff	1930	* and voltage regulator must be enabled (done into HAL_ADC_Init()).
bogdanm	0:9b334a45a8ff	1931	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1932	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1933	*/
bogdanm	0:9b334a45a8ff	1934	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1935	{
bogdanm	0:9b334a45a8ff	1936	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1937	__IO uint32_t wait_loop_index = 0;
bogdanm	0:9b334a45a8ff	1938
bogdanm	0:9b334a45a8ff	1939	/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
bogdanm	0:9b334a45a8ff	1940	/* enabling phase not yet completed: flag ADC ready not yet set). */
bogdanm	0:9b334a45a8ff	1941	/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
bogdanm	0:9b334a45a8ff	1942	/* causes: ADC clock not running, ...). */
bogdanm	0:9b334a45a8ff	1943	if (ADC_IS_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1944	{
bogdanm	0:9b334a45a8ff	1945	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1946	__HAL_ADC_ENABLE(hadc);
bogdanm	0:9b334a45a8ff	1947
bogdanm	0:9b334a45a8ff	1948	/* Delay for ADC stabilization time */
bogdanm	0:9b334a45a8ff	1949	/* Compute number of CPU cycles to wait for */
bogdanm	0:9b334a45a8ff	1950	wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
bogdanm	0:9b334a45a8ff	1951	while(wait_loop_index != 0)
bogdanm	0:9b334a45a8ff	1952	{
bogdanm	0:9b334a45a8ff	1953	wait_loop_index--;
bogdanm	0:9b334a45a8ff	1954	}
bogdanm	0:9b334a45a8ff	1955
mbed_official	124:6a4a5b7d7324	1956	/* Get tick count */
bogdanm	0:9b334a45a8ff	1957	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1958
bogdanm	0:9b334a45a8ff	1959	/* Wait for ADC effectively enabled */
bogdanm	0:9b334a45a8ff	1960	while(ADC_IS_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1961	{
bogdanm	0:9b334a45a8ff	1962	if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
bogdanm	0:9b334a45a8ff	1963	{
bogdanm	0:9b334a45a8ff	1964	/* Update ADC state machine to error */
mbed_official	124:6a4a5b7d7324	1965	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	1966
bogdanm	0:9b334a45a8ff	1967	/* Set ADC error code to ADC IP internal error */
mbed_official	124:6a4a5b7d7324	1968	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	1969
bogdanm	0:9b334a45a8ff	1970	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1971	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1972
bogdanm	0:9b334a45a8ff	1973	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1974	}
bogdanm	0:9b334a45a8ff	1975	}
bogdanm	0:9b334a45a8ff	1976	}
bogdanm	0:9b334a45a8ff	1977
bogdanm	0:9b334a45a8ff	1978	/* Return HAL status */
bogdanm	0:9b334a45a8ff	1979	return HAL_OK;
bogdanm	0:9b334a45a8ff	1980	}
bogdanm	0:9b334a45a8ff	1981
bogdanm	0:9b334a45a8ff	1982	/**
bogdanm	0:9b334a45a8ff	1983	* @brief Stop ADC conversion and disable the selected ADC
bogdanm	0:9b334a45a8ff	1984	* @note Prerequisite condition to use this function: ADC conversions must be
bogdanm	0:9b334a45a8ff	1985	* stopped to disable the ADC.
bogdanm	0:9b334a45a8ff	1986	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1987	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1988	*/
bogdanm	0:9b334a45a8ff	1989	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1990	{
bogdanm	0:9b334a45a8ff	1991	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1992
bogdanm	0:9b334a45a8ff	1993	/* Verification if ADC is not already disabled */
bogdanm	0:9b334a45a8ff	1994	if (ADC_IS_ENABLE(hadc) != RESET)
bogdanm	0:9b334a45a8ff	1995	{
bogdanm	0:9b334a45a8ff	1996	/* Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1997	__HAL_ADC_DISABLE(hadc);
bogdanm	0:9b334a45a8ff	1998
mbed_official	124:6a4a5b7d7324	1999	/* Get tick count */
bogdanm	0:9b334a45a8ff	2000	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2001
bogdanm	0:9b334a45a8ff	2002	/* Wait for ADC effectively disabled */
bogdanm	0:9b334a45a8ff	2003	while(ADC_IS_ENABLE(hadc) != RESET)
bogdanm	0:9b334a45a8ff	2004	{
bogdanm	0:9b334a45a8ff	2005	if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
bogdanm	0:9b334a45a8ff	2006	{
bogdanm	0:9b334a45a8ff	2007	/* Update ADC state machine to error */
mbed_official	124:6a4a5b7d7324	2008	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2009
bogdanm	0:9b334a45a8ff	2010	/* Set ADC error code to ADC IP internal error */
mbed_official	124:6a4a5b7d7324	2011	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2012
bogdanm	0:9b334a45a8ff	2013	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2014	}
bogdanm	0:9b334a45a8ff	2015	}
bogdanm	0:9b334a45a8ff	2016	}
bogdanm	0:9b334a45a8ff	2017
bogdanm	0:9b334a45a8ff	2018	/* Return HAL status */
bogdanm	0:9b334a45a8ff	2019	return HAL_OK;
bogdanm	0:9b334a45a8ff	2020	}
bogdanm	0:9b334a45a8ff	2021
bogdanm	0:9b334a45a8ff	2022	/**
bogdanm	0:9b334a45a8ff	2023	* @brief DMA transfer complete callback.
bogdanm	0:9b334a45a8ff	2024	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	2025	* @retval None
bogdanm	0:9b334a45a8ff	2026	*/
bogdanm	0:9b334a45a8ff	2027	void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2028	{
bogdanm	0:9b334a45a8ff	2029	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	2030	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2031
bogdanm	0:9b334a45a8ff	2032	/* Update state machine on conversion status if not in error state */
mbed_official	124:6a4a5b7d7324	2033	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL \| HAL_ADC_STATE_ERROR_DMA))
bogdanm	0:9b334a45a8ff	2034	{
bogdanm	0:9b334a45a8ff	2035	/* Update ADC state machine */
mbed_official	124:6a4a5b7d7324	2036	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
mbed_official	124:6a4a5b7d7324	2037
mbed_official	124:6a4a5b7d7324	2038	/* Determine whether any further conversion upcoming on group regular */
mbed_official	124:6a4a5b7d7324	2039	/* by external trigger, continuous mode or scan sequence on going. */
mbed_official	124:6a4a5b7d7324	2040	/* Note: On STM32F1 devices, in case of sequencer enabled */
mbed_official	124:6a4a5b7d7324	2041	/* (several ranks selected), end of conversion flag is raised */
mbed_official	124:6a4a5b7d7324	2042	/* at the end of the sequence. */
mbed_official	124:6a4a5b7d7324	2043	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
mbed_official	124:6a4a5b7d7324	2044	(hadc->Init.ContinuousConvMode == DISABLE) )
bogdanm	0:9b334a45a8ff	2045	{
mbed_official	124:6a4a5b7d7324	2046	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	2047	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
mbed_official	124:6a4a5b7d7324	2048
mbed_official	124:6a4a5b7d7324	2049	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
bogdanm	0:9b334a45a8ff	2050	{
mbed_official	124:6a4a5b7d7324	2051	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	2052	}
bogdanm	0:9b334a45a8ff	2053	}
bogdanm	0:9b334a45a8ff	2054
bogdanm	0:9b334a45a8ff	2055	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	2056	HAL_ADC_ConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	2057	}
bogdanm	0:9b334a45a8ff	2058	else
bogdanm	0:9b334a45a8ff	2059	{
bogdanm	0:9b334a45a8ff	2060	/* Call DMA error callback */
bogdanm	0:9b334a45a8ff	2061	hadc->DMA_Handle->XferErrorCallback(hdma);
bogdanm	0:9b334a45a8ff	2062	}
bogdanm	0:9b334a45a8ff	2063	}
bogdanm	0:9b334a45a8ff	2064
bogdanm	0:9b334a45a8ff	2065	/**
bogdanm	0:9b334a45a8ff	2066	* @brief DMA half transfer complete callback.
bogdanm	0:9b334a45a8ff	2067	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	2068	* @retval None
bogdanm	0:9b334a45a8ff	2069	*/
bogdanm	0:9b334a45a8ff	2070	void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2071	{
bogdanm	0:9b334a45a8ff	2072	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	2073	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2074
bogdanm	0:9b334a45a8ff	2075	/* Half conversion callback */
bogdanm	0:9b334a45a8ff	2076	HAL_ADC_ConvHalfCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	2077	}
bogdanm	0:9b334a45a8ff	2078
bogdanm	0:9b334a45a8ff	2079	/**
bogdanm	0:9b334a45a8ff	2080	* @brief DMA error callback
bogdanm	0:9b334a45a8ff	2081	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	2082	* @retval None
bogdanm	0:9b334a45a8ff	2083	*/
bogdanm	0:9b334a45a8ff	2084	void ADC_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2085	{
bogdanm	0:9b334a45a8ff	2086	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	2087	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2088
mbed_official	124:6a4a5b7d7324	2089	/* Set ADC state */
mbed_official	124:6a4a5b7d7324	2090	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
bogdanm	0:9b334a45a8ff	2091
bogdanm	0:9b334a45a8ff	2092	/* Set ADC error code to DMA error */
mbed_official	124:6a4a5b7d7324	2093	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
bogdanm	0:9b334a45a8ff	2094
bogdanm	0:9b334a45a8ff	2095	/* Error callback */
bogdanm	0:9b334a45a8ff	2096	HAL_ADC_ErrorCallback(hadc);
bogdanm	0:9b334a45a8ff	2097	}
bogdanm	0:9b334a45a8ff	2098
bogdanm	0:9b334a45a8ff	2099	/**
bogdanm	0:9b334a45a8ff	2100	* @}
bogdanm	0:9b334a45a8ff	2101	*/
bogdanm	0:9b334a45a8ff	2102
bogdanm	0:9b334a45a8ff	2103	#endif /* HAL_ADC_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2104	/**
bogdanm	0:9b334a45a8ff	2105	* @}
bogdanm	0:9b334a45a8ff	2106	*/
bogdanm	0:9b334a45a8ff	2107
bogdanm	0:9b334a45a8ff	2108	/**
bogdanm	0:9b334a45a8ff	2109	* @}
bogdanm	0:9b334a45a8ff	2110	*/
bogdanm	0:9b334a45a8ff	2111
bogdanm	0:9b334a45a8ff	2112	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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