mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 124:6a4a5b7d7324

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f1xx_hal_adc.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 15-December-2014
bogdanm	0:9b334a45a8ff	7	* @brief This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	8	* functionalities of the Analog to Digital Convertor (ADC)
bogdanm	0:9b334a45a8ff	9	* peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* ++ Initialization and Configuration of ADC
bogdanm	0:9b334a45a8ff	12	* + Operation functions
bogdanm	0:9b334a45a8ff	13	* ++ Start, stop, get result of conversions of regular
bogdanm	0:9b334a45a8ff	14	* group, using 3 possible modes: polling, interruption or DMA.
bogdanm	0:9b334a45a8ff	15	* + Control functions
bogdanm	0:9b334a45a8ff	16	* ++ Channels configuration on regular group
bogdanm	0:9b334a45a8ff	17	* ++ Channels configuration on injected group
bogdanm	0:9b334a45a8ff	18	* ++ Analog Watchdog configuration
bogdanm	0:9b334a45a8ff	19	* + State functions
bogdanm	0:9b334a45a8ff	20	* ++ ADC state machine management
bogdanm	0:9b334a45a8ff	21	* ++ Interrupts and flags management
bogdanm	0:9b334a45a8ff	22	* Other functions (extended functions) are available in file
bogdanm	0:9b334a45a8ff	23	* "stm32f1xx_hal_adc_ex.c".
bogdanm	0:9b334a45a8ff	24	*
bogdanm	0:9b334a45a8ff	25	@verbatim
bogdanm	0:9b334a45a8ff	26	==============================================================================
bogdanm	0:9b334a45a8ff	27	##### ADC peripheral features #####
bogdanm	0:9b334a45a8ff	28	==============================================================================
bogdanm	0:9b334a45a8ff	29	[..]
bogdanm	0:9b334a45a8ff	30	(+) 12-bit resolution
bogdanm	0:9b334a45a8ff	31
bogdanm	0:9b334a45a8ff	32	(+) Interrupt generation at the end of regular conversion, end of injected
bogdanm	0:9b334a45a8ff	33	conversion, and in case of analog watchdog or overrun events.
bogdanm	0:9b334a45a8ff	34
bogdanm	0:9b334a45a8ff	35	(+) Single and continuous conversion modes.
bogdanm	0:9b334a45a8ff	36
bogdanm	0:9b334a45a8ff	37	(+) Scan mode for automatic conversion of channel 0 to channel 'n'.
bogdanm	0:9b334a45a8ff	38
bogdanm	0:9b334a45a8ff	39	(+) Data alignment with in-built data coherency.
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(+) Channel-wise programmable sampling time.
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	(+) ADC conversion Regular or Injected groups.
bogdanm	0:9b334a45a8ff	44
bogdanm	0:9b334a45a8ff	45	(+) External trigger (timer or EXTI) with configurable polarity for both
bogdanm	0:9b334a45a8ff	46	regular and injected groups.
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	(+) DMA request generation for transfer of conversions data of regular group.
bogdanm	0:9b334a45a8ff	49
bogdanm	0:9b334a45a8ff	50	(+) Multimode Dual mode (available on devices with 2 ADCs or more).
bogdanm	0:9b334a45a8ff	51
bogdanm	0:9b334a45a8ff	52	(+) Configurable DMA data storage in Multimode Dual mode (available on devices
bogdanm	0:9b334a45a8ff	53	with 2 DCs or more).
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	(+) Configurable delay between conversions in Dual interleaved mode (available
bogdanm	0:9b334a45a8ff	56	on devices with 2 DCs or more).
bogdanm	0:9b334a45a8ff	57
bogdanm	0:9b334a45a8ff	58	(+) ADC calibration
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	(+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
bogdanm	0:9b334a45a8ff	61	slower speed.
bogdanm	0:9b334a45a8ff	62
bogdanm	0:9b334a45a8ff	63	(+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
bogdanm	0:9b334a45a8ff	64	Vdda or to an external voltage reference).
bogdanm	0:9b334a45a8ff	65
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	68	==============================================================================
bogdanm	0:9b334a45a8ff	69	[..]
bogdanm	0:9b334a45a8ff	70
bogdanm	0:9b334a45a8ff	71	* Configuration of top level parameters related to ADC *
bogdanm	0:9b334a45a8ff	72	============================================================
bogdanm	0:9b334a45a8ff	73	[..]
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75	(#) Enable the ADC interface
bogdanm	0:9b334a45a8ff	76	(++) As prerequisite, ADC clock must be configured at RCC top level.
bogdanm	0:9b334a45a8ff	77	Caution: On STM32F1, ADC clock frequency max is 14MHz (refer
bogdanm	0:9b334a45a8ff	78	to device datasheet).
bogdanm	0:9b334a45a8ff	79	Therefore, ADC clock prescaler must be configured in
bogdanm	0:9b334a45a8ff	80	function of ADC clock source frequency to remain
bogdanm	0:9b334a45a8ff	81	below this maximum frequency.
bogdanm	0:9b334a45a8ff	82	(++) One clock setting is mandatory:
bogdanm	0:9b334a45a8ff	83	ADC clock (core and conversion clock).
bogdanm	0:9b334a45a8ff	84	(+++) Example:
bogdanm	0:9b334a45a8ff	85	Into HAL_ADC_MspInit() (recommended code location) or with
bogdanm	0:9b334a45a8ff	86	other device clock parameters configuration:
bogdanm	0:9b334a45a8ff	87	(+++) RCC_PeriphCLKInitTypeDef PeriphClkInit;
bogdanm	0:9b334a45a8ff	88	(+++) __ADC1_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	89	(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
bogdanm	0:9b334a45a8ff	90	(+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
bogdanm	0:9b334a45a8ff	91	(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	(#) ADC pins configuration
bogdanm	0:9b334a45a8ff	94	(++) Enable the clock for the ADC GPIOs
bogdanm	0:9b334a45a8ff	95	using macro __HAL_RCC_GPIOx_CLK_ENABLE()
bogdanm	0:9b334a45a8ff	96	(++) Configure these ADC pins in analog mode
bogdanm	0:9b334a45a8ff	97	using function HAL_GPIO_Init()
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	(#) Optionally, in case of usage of ADC with interruptions:
bogdanm	0:9b334a45a8ff	100	(++) Configure the NVIC for ADC
bogdanm	0:9b334a45a8ff	101	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
bogdanm	0:9b334a45a8ff	102	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
bogdanm	0:9b334a45a8ff	103	into the function of corresponding ADC interruption vector
bogdanm	0:9b334a45a8ff	104	ADCx_IRQHandler().
bogdanm	0:9b334a45a8ff	105
bogdanm	0:9b334a45a8ff	106	(#) Optionally, in case of usage of DMA:
bogdanm	0:9b334a45a8ff	107	(++) Configure the DMA (DMA channel, mode normal or circular, ...)
bogdanm	0:9b334a45a8ff	108	using function HAL_DMA_Init().
bogdanm	0:9b334a45a8ff	109	(++) Configure the NVIC for DMA
bogdanm	0:9b334a45a8ff	110	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
bogdanm	0:9b334a45a8ff	111	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
bogdanm	0:9b334a45a8ff	112	into the function of corresponding DMA interruption vector
bogdanm	0:9b334a45a8ff	113	DMAx_Channelx_IRQHandler().
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115	* Configuration of ADC, groups regular/injected, channels parameters *
bogdanm	0:9b334a45a8ff	116	==========================================================================
bogdanm	0:9b334a45a8ff	117	[..]
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	(#) Configure the ADC parameters (resolution, data alignment, ...)
bogdanm	0:9b334a45a8ff	120	and regular group parameters (conversion trigger, sequencer, ...,
bogdanm	0:9b334a45a8ff	121	of regular group)
bogdanm	0:9b334a45a8ff	122	using function HAL_ADC_Init().
bogdanm	0:9b334a45a8ff	123
bogdanm	0:9b334a45a8ff	124	(#) Configure the channels for regular group parameters (channel number,
bogdanm	0:9b334a45a8ff	125	channel rank into sequencer, ..., into regular group)
bogdanm	0:9b334a45a8ff	126	using function HAL_ADC_ConfigChannel().
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	(#) Optionally, configure the injected group parameters (conversion trigger,
bogdanm	0:9b334a45a8ff	129	sequencer, ..., of injected group)
bogdanm	0:9b334a45a8ff	130	and the channels for injected group parameters (channel number,
bogdanm	0:9b334a45a8ff	131	channel rank into sequencer, ..., into injected group)
bogdanm	0:9b334a45a8ff	132	using function HAL_ADCEx_InjectedConfigChannel().
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	(#) Optionally, configure the analog watchdog parameters (channels
bogdanm	0:9b334a45a8ff	135	monitored, thresholds, ...)
bogdanm	0:9b334a45a8ff	136	using function HAL_ADC_AnalogWDGConfig().
bogdanm	0:9b334a45a8ff	137
bogdanm	0:9b334a45a8ff	138	(#) Optionally, for devices with several ADC instances: configure the
bogdanm	0:9b334a45a8ff	139	multimode parameters
bogdanm	0:9b334a45a8ff	140	using function HAL_ADCEx_MultiModeConfigChannel().
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	* Execution of ADC conversions *
bogdanm	0:9b334a45a8ff	143	====================================
bogdanm	0:9b334a45a8ff	144	[..]
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	(#) Optionally, perform an automatic ADC calibration to improve the
bogdanm	0:9b334a45a8ff	147	conversion accuracy
bogdanm	0:9b334a45a8ff	148	using function HAL_ADCEx_Calibration_Start().
bogdanm	0:9b334a45a8ff	149
bogdanm	0:9b334a45a8ff	150	(#) ADC driver can be used among three modes: polling, interruption,
bogdanm	0:9b334a45a8ff	151	transfer by DMA.
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	(++) ADC conversion by polling:
bogdanm	0:9b334a45a8ff	154	(+++) Activate the ADC peripheral and start conversions
bogdanm	0:9b334a45a8ff	155	using function HAL_ADC_Start()
bogdanm	0:9b334a45a8ff	156	(+++) Wait for ADC conversion completion
bogdanm	0:9b334a45a8ff	157	using function HAL_ADC_PollForConversion()
bogdanm	0:9b334a45a8ff	158	(or for injected group: HAL_ADCEx_InjectedPollForConversion() )
bogdanm	0:9b334a45a8ff	159	(+++) Retrieve conversion results
bogdanm	0:9b334a45a8ff	160	using function HAL_ADC_GetValue()
bogdanm	0:9b334a45a8ff	161	(or for injected group: HAL_ADCEx_InjectedGetValue() )
bogdanm	0:9b334a45a8ff	162	(+++) Stop conversion and disable the ADC peripheral
bogdanm	0:9b334a45a8ff	163	using function HAL_ADC_Stop()
bogdanm	0:9b334a45a8ff	164
bogdanm	0:9b334a45a8ff	165	(++) ADC conversion by interruption:
bogdanm	0:9b334a45a8ff	166	(+++) Activate the ADC peripheral and start conversions
bogdanm	0:9b334a45a8ff	167	using function HAL_ADC_Start_IT()
bogdanm	0:9b334a45a8ff	168	(+++) Wait for ADC conversion completion by call of function
bogdanm	0:9b334a45a8ff	169	HAL_ADC_ConvCpltCallback()
bogdanm	0:9b334a45a8ff	170	(this function must be implemented in user program)
bogdanm	0:9b334a45a8ff	171	(or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
bogdanm	0:9b334a45a8ff	172	(+++) Retrieve conversion results
bogdanm	0:9b334a45a8ff	173	using function HAL_ADC_GetValue()
bogdanm	0:9b334a45a8ff	174	(or for injected group: HAL_ADCEx_InjectedGetValue() )
bogdanm	0:9b334a45a8ff	175	(+++) Stop conversion and disable the ADC peripheral
bogdanm	0:9b334a45a8ff	176	using function HAL_ADC_Stop_IT()
bogdanm	0:9b334a45a8ff	177
bogdanm	0:9b334a45a8ff	178	(++) ADC conversion with transfer by DMA:
bogdanm	0:9b334a45a8ff	179	(+++) Activate the ADC peripheral and start conversions
bogdanm	0:9b334a45a8ff	180	using function HAL_ADC_Start_DMA()
bogdanm	0:9b334a45a8ff	181	(+++) Wait for ADC conversion completion by call of function
bogdanm	0:9b334a45a8ff	182	HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
bogdanm	0:9b334a45a8ff	183	(these functions must be implemented in user program)
bogdanm	0:9b334a45a8ff	184	(+++) Conversion results are automatically transferred by DMA into
bogdanm	0:9b334a45a8ff	185	destination variable address.
bogdanm	0:9b334a45a8ff	186	(+++) Stop conversion and disable the ADC peripheral
bogdanm	0:9b334a45a8ff	187	using function HAL_ADC_Stop_DMA()
bogdanm	0:9b334a45a8ff	188
bogdanm	0:9b334a45a8ff	189	(++) For devices with several ADCs: ADC multimode conversion
bogdanm	0:9b334a45a8ff	190	with transfer by DMA:
bogdanm	0:9b334a45a8ff	191	(+++) Activate the ADC peripheral (slave) and start conversions
bogdanm	0:9b334a45a8ff	192	using function HAL_ADC_Start()
bogdanm	0:9b334a45a8ff	193	(+++) Activate the ADC peripheral (master) and start conversions
bogdanm	0:9b334a45a8ff	194	using function HAL_ADCEx_MultiModeStart_DMA()
bogdanm	0:9b334a45a8ff	195	(+++) Wait for ADC conversion completion by call of function
bogdanm	0:9b334a45a8ff	196	HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
bogdanm	0:9b334a45a8ff	197	(these functions must be implemented in user program)
bogdanm	0:9b334a45a8ff	198	(+++) Conversion results are automatically transferred by DMA into
bogdanm	0:9b334a45a8ff	199	destination variable address.
bogdanm	0:9b334a45a8ff	200	(+++) Stop conversion and disable the ADC peripheral (master)
bogdanm	0:9b334a45a8ff	201	using function HAL_ADCEx_MultiModeStop_DMA()
bogdanm	0:9b334a45a8ff	202	(+++) Stop conversion and disable the ADC peripheral (slave)
bogdanm	0:9b334a45a8ff	203	using function HAL_ADC_Stop_IT()
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205	[..]
bogdanm	0:9b334a45a8ff	206
bogdanm	0:9b334a45a8ff	207	(@) Callback functions must be implemented in user program:
bogdanm	0:9b334a45a8ff	208	(+@) HAL_ADC_ErrorCallback()
bogdanm	0:9b334a45a8ff	209	(+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
bogdanm	0:9b334a45a8ff	210	(+@) HAL_ADC_ConvCpltCallback()
bogdanm	0:9b334a45a8ff	211	(+@) HAL_ADC_ConvHalfCpltCallback
bogdanm	0:9b334a45a8ff	212	(+@) HAL_ADCEx_InjectedConvCpltCallback()
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	* Deinitialization of ADC *
bogdanm	0:9b334a45a8ff	215	============================================================
bogdanm	0:9b334a45a8ff	216	[..]
bogdanm	0:9b334a45a8ff	217
bogdanm	0:9b334a45a8ff	218	(#) Disable the ADC interface
bogdanm	0:9b334a45a8ff	219	(++) ADC clock can be hard reset and disabled at RCC top level.
bogdanm	0:9b334a45a8ff	220	(++) Hard reset of ADC peripherals
bogdanm	0:9b334a45a8ff	221	using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
bogdanm	0:9b334a45a8ff	222	(++) ADC clock disable
bogdanm	0:9b334a45a8ff	223	using the equivalent macro/functions as configuration step.
bogdanm	0:9b334a45a8ff	224	(+++) Example:
bogdanm	0:9b334a45a8ff	225	Into HAL_ADC_MspDeInit() (recommended code location) or with
bogdanm	0:9b334a45a8ff	226	other device clock parameters configuration:
bogdanm	0:9b334a45a8ff	227	(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
bogdanm	0:9b334a45a8ff	228	(+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF
bogdanm	0:9b334a45a8ff	229	(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	(#) ADC pins configuration
bogdanm	0:9b334a45a8ff	232	(++) Disable the clock for the ADC GPIOs
bogdanm	0:9b334a45a8ff	233	using macro __HAL_RCC_GPIOx_CLK_DISABLE()
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	(#) Optionally, in case of usage of ADC with interruptions:
bogdanm	0:9b334a45a8ff	236	(++) Disable the NVIC for ADC
bogdanm	0:9b334a45a8ff	237	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	(#) Optionally, in case of usage of DMA:
bogdanm	0:9b334a45a8ff	240	(++) Deinitialize the DMA
bogdanm	0:9b334a45a8ff	241	using function HAL_DMA_Init().
bogdanm	0:9b334a45a8ff	242	(++) Disable the NVIC for DMA
bogdanm	0:9b334a45a8ff	243	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	[..]
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	@endverbatim
bogdanm	0:9b334a45a8ff	248	******************************************************************************
bogdanm	0:9b334a45a8ff	249	* @attention
bogdanm	0:9b334a45a8ff	250	*
bogdanm	0:9b334a45a8ff	251	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	252	*
bogdanm	0:9b334a45a8ff	253	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	254	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	255	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	256	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	257	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	258	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	259	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	260	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	261	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	262	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	263	*
bogdanm	0:9b334a45a8ff	264	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	265	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	266	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	267	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	268	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	269	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	270	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	271	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	272	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	273	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	274	*
bogdanm	0:9b334a45a8ff	275	******************************************************************************
bogdanm	0:9b334a45a8ff	276	*/
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	279	#include "stm32f1xx_hal.h"
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/** @addtogroup STM32F1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	282	* @{
bogdanm	0:9b334a45a8ff	283	*/
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	/** @defgroup ADC ADC
bogdanm	0:9b334a45a8ff	286	* @brief ADC HAL module driver
bogdanm	0:9b334a45a8ff	287	* @{
bogdanm	0:9b334a45a8ff	288	*/
bogdanm	0:9b334a45a8ff	289
bogdanm	0:9b334a45a8ff	290	#ifdef HAL_ADC_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	293	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	294	/** @defgroup ADC_Private_Constants ADC Private Constants
bogdanm	0:9b334a45a8ff	295	* @{
bogdanm	0:9b334a45a8ff	296	*/
bogdanm	0:9b334a45a8ff	297
bogdanm	0:9b334a45a8ff	298	/* Timeout values for ADC enable and disable settling time. */
bogdanm	0:9b334a45a8ff	299	/* Values defined to be higher than worst cases: low clocks freq, */
bogdanm	0:9b334a45a8ff	300	/* maximum prescaler. */
bogdanm	0:9b334a45a8ff	301	/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
bogdanm	0:9b334a45a8ff	302	/* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
bogdanm	0:9b334a45a8ff	303	/* Unit: ms */
bogdanm	0:9b334a45a8ff	304	#define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
bogdanm	0:9b334a45a8ff	305	#define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
bogdanm	0:9b334a45a8ff	306
bogdanm	0:9b334a45a8ff	307	/* Delay for ADC stabilization time. */
bogdanm	0:9b334a45a8ff	308	/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
bogdanm	0:9b334a45a8ff	309	/* Unit: us */
bogdanm	0:9b334a45a8ff	310	#define ADC_STAB_DELAY_US ((uint32_t) 1)
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	/* Delay for temperature sensor stabilization time. */
bogdanm	0:9b334a45a8ff	313	/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
bogdanm	0:9b334a45a8ff	314	/* Unit: us */
bogdanm	0:9b334a45a8ff	315	#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
bogdanm	0:9b334a45a8ff	316
bogdanm	0:9b334a45a8ff	317	/**
bogdanm	0:9b334a45a8ff	318	* @}
bogdanm	0:9b334a45a8ff	319	*/
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	322	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	323	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	324	/** @defgroup ADC_Private_Functions ADC Private Functions
bogdanm	0:9b334a45a8ff	325	* @{
bogdanm	0:9b334a45a8ff	326	*/
bogdanm	0:9b334a45a8ff	327	/**
bogdanm	0:9b334a45a8ff	328	* @}
bogdanm	0:9b334a45a8ff	329	*/
bogdanm	0:9b334a45a8ff	330
bogdanm	0:9b334a45a8ff	331	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	/** @defgroup ADC_Exported_Functions ADC Exported Functions
bogdanm	0:9b334a45a8ff	334	* @{
bogdanm	0:9b334a45a8ff	335	*/
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	338	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	339	*
bogdanm	0:9b334a45a8ff	340	@verbatim
bogdanm	0:9b334a45a8ff	341	===============================================================================
bogdanm	0:9b334a45a8ff	342	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	343	===============================================================================
bogdanm	0:9b334a45a8ff	344	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	345	(+) Initialize and configure the ADC.
bogdanm	0:9b334a45a8ff	346	(+) De-initialize the ADC.
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	@endverbatim
bogdanm	0:9b334a45a8ff	349	* @{
bogdanm	0:9b334a45a8ff	350	*/
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/**
bogdanm	0:9b334a45a8ff	353	* @brief Initializes the ADC peripheral and regular group according to
bogdanm	0:9b334a45a8ff	354	* parameters specified in structure "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	355	* @note As prerequisite, ADC clock must be configured at RCC top level
bogdanm	0:9b334a45a8ff	356	* (clock source APB2).
bogdanm	0:9b334a45a8ff	357	* See commented example code below that can be copied and uncommented
bogdanm	0:9b334a45a8ff	358	* into HAL_ADC_MspInit().
bogdanm	0:9b334a45a8ff	359	* @note Possibility to update parameters on the fly:
bogdanm	0:9b334a45a8ff	360	* This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
bogdanm	0:9b334a45a8ff	361	* coming from ADC state reset. Following calls to this function can
bogdanm	0:9b334a45a8ff	362	* be used to reconfigure some parameters of ADC_InitTypeDef
bogdanm	0:9b334a45a8ff	363	* structure on the fly, without modifying MSP configuration. If ADC
bogdanm	0:9b334a45a8ff	364	* MSP has to be modified again, HAL_ADC_DeInit() must be called
bogdanm	0:9b334a45a8ff	365	* before HAL_ADC_Init().
bogdanm	0:9b334a45a8ff	366	* The setting of these parameters is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	367	* For parameters constraints, see comments of structure
bogdanm	0:9b334a45a8ff	368	* "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	369	* @note This function configures the ADC within 2 scopes: scope of entire
bogdanm	0:9b334a45a8ff	370	* ADC and scope of regular group. For parameters details, see comments
bogdanm	0:9b334a45a8ff	371	* of structure "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	372	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	373	* @retval HAL status
bogdanm	0:9b334a45a8ff	374	*/
bogdanm	0:9b334a45a8ff	375	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	376	{
bogdanm	0:9b334a45a8ff	377	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	378	uint32_t tmp_cr1 = 0;
bogdanm	0:9b334a45a8ff	379	uint32_t tmp_cr2 = 0;
bogdanm	0:9b334a45a8ff	380	uint32_t tmp_sqr1 = 0;
bogdanm	0:9b334a45a8ff	381
bogdanm	0:9b334a45a8ff	382	/* Check ADC handle */
bogdanm	0:9b334a45a8ff	383	if(hadc == NULL)
bogdanm	0:9b334a45a8ff	384	{
bogdanm	0:9b334a45a8ff	385	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	386	}
bogdanm	0:9b334a45a8ff	387
bogdanm	0:9b334a45a8ff	388	/* Check the parameters */
bogdanm	0:9b334a45a8ff	389	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	390	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
bogdanm	0:9b334a45a8ff	391	assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
bogdanm	0:9b334a45a8ff	392	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	393	assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
bogdanm	0:9b334a45a8ff	394
bogdanm	0:9b334a45a8ff	395	if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
bogdanm	0:9b334a45a8ff	396	{
bogdanm	0:9b334a45a8ff	397	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
bogdanm	0:9b334a45a8ff	398	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
bogdanm	0:9b334a45a8ff	399	assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
bogdanm	0:9b334a45a8ff	400	}
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	/* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
bogdanm	0:9b334a45a8ff	403	/* at RCC top level. */
bogdanm	0:9b334a45a8ff	404	/* Refer to header of this file for more details on clock enabling */
bogdanm	0:9b334a45a8ff	405	/* procedure. */
bogdanm	0:9b334a45a8ff	406
bogdanm	0:9b334a45a8ff	407	/* Actions performed only if ADC is coming from state reset: */
bogdanm	0:9b334a45a8ff	408	/* - Initialization of ADC MSP */
bogdanm	0:9b334a45a8ff	409	if (hadc->State == HAL_ADC_STATE_RESET)
bogdanm	0:9b334a45a8ff	410	{
bogdanm	0:9b334a45a8ff	411	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	412	hadc-> Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414	/* Init the low level hardware */
bogdanm	0:9b334a45a8ff	415	HAL_ADC_MspInit(hadc);
bogdanm	0:9b334a45a8ff	416	}
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	419	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	420	/* Note: In case of ADC already enabled, precaution to not launch an */
bogdanm	0:9b334a45a8ff	421	/* unwanted conversion while modifying register CR2 by writing 1 to */
bogdanm	0:9b334a45a8ff	422	/* bit ADON. */
bogdanm	0:9b334a45a8ff	423	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	424
bogdanm	0:9b334a45a8ff	425
bogdanm	0:9b334a45a8ff	426	/* Configuration of ADC parameters if previous preliminary actions are */
bogdanm	0:9b334a45a8ff	427	/* correctly completed. */
bogdanm	0:9b334a45a8ff	428	if (tmp_hal_status != HAL_ERROR)
bogdanm	0:9b334a45a8ff	429	{
bogdanm	0:9b334a45a8ff	430	/* Initialize the ADC state */
bogdanm	0:9b334a45a8ff	431	hadc->State = HAL_ADC_STATE_BUSY;
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/* Set ADC parameters */
bogdanm	0:9b334a45a8ff	434
bogdanm	0:9b334a45a8ff	435	/* Configuration of ADC: */
bogdanm	0:9b334a45a8ff	436	/* - data alignment */
bogdanm	0:9b334a45a8ff	437	/* - external trigger to start conversion */
bogdanm	0:9b334a45a8ff	438	/* - external trigger polarity (always set to 1, because needed for all */
bogdanm	0:9b334a45a8ff	439	/* triggers: external trigger of SW start) */
bogdanm	0:9b334a45a8ff	440	/* - continuous conversion mode */
bogdanm	0:9b334a45a8ff	441	/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
bogdanm	0:9b334a45a8ff	442	/* HAL_ADC_Start_xxx functions because if set in this function, */
bogdanm	0:9b334a45a8ff	443	/* a conversion on injected group would start a conversion also on */
bogdanm	0:9b334a45a8ff	444	/* regular group after ADC enabling. */
bogdanm	0:9b334a45a8ff	445	tmp_cr2 \|= (hadc->Init.DataAlign \|
bogdanm	0:9b334a45a8ff	446	ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) \|
bogdanm	0:9b334a45a8ff	447	ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	/* Configuration of ADC: */
bogdanm	0:9b334a45a8ff	450	/* - scan mode */
bogdanm	0:9b334a45a8ff	451	/* - discontinuous mode disable/enable */
bogdanm	0:9b334a45a8ff	452	/* - discontinuous mode number of conversions */
bogdanm	0:9b334a45a8ff	453	tmp_cr1 \|= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
bogdanm	0:9b334a45a8ff	454
bogdanm	0:9b334a45a8ff	455	/* Enable discontinuous mode only if continuous mode is disabled */
bogdanm	0:9b334a45a8ff	456	if ((hadc->Init.DiscontinuousConvMode == ENABLE) &&
bogdanm	0:9b334a45a8ff	457	(hadc->Init.ContinuousConvMode == DISABLE) )
bogdanm	0:9b334a45a8ff	458	{
bogdanm	0:9b334a45a8ff	459	/* Enable the selected ADC regular discontinuous mode */
bogdanm	0:9b334a45a8ff	460	/* Set the number of channels to be converted in discontinuous mode */
bogdanm	0:9b334a45a8ff	461	tmp_cr1 \|= (ADC_CR1_DISCEN \|
bogdanm	0:9b334a45a8ff	462	ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
bogdanm	0:9b334a45a8ff	463	}
bogdanm	0:9b334a45a8ff	464
bogdanm	0:9b334a45a8ff	465	/* Update ADC configuration register CR1 with previous settings */
bogdanm	0:9b334a45a8ff	466	MODIFY_REG(hadc->Instance->CR1,
bogdanm	0:9b334a45a8ff	467	ADC_CR1_SCAN \|
bogdanm	0:9b334a45a8ff	468	ADC_CR1_DISCEN \|
bogdanm	0:9b334a45a8ff	469	ADC_CR1_DISCNUM ,
bogdanm	0:9b334a45a8ff	470	tmp_cr1 );
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	/* Update ADC configuration register CR2 with previous settings */
bogdanm	0:9b334a45a8ff	473	MODIFY_REG(hadc->Instance->CR2,
bogdanm	0:9b334a45a8ff	474	ADC_CR2_ALIGN \|
bogdanm	0:9b334a45a8ff	475	ADC_CR2_EXTSEL \|
bogdanm	0:9b334a45a8ff	476	ADC_CR2_EXTTRIG \|
bogdanm	0:9b334a45a8ff	477	ADC_CR2_CONT ,
bogdanm	0:9b334a45a8ff	478	tmp_cr2 );
bogdanm	0:9b334a45a8ff	479
bogdanm	0:9b334a45a8ff	480	/* Configuration of regular group sequencer: */
bogdanm	0:9b334a45a8ff	481	/* - if scan mode is disabled, regular channels sequence length is set to */
bogdanm	0:9b334a45a8ff	482	/* 0x00: 1 channel converted (channel on regular rank 1) */
bogdanm	0:9b334a45a8ff	483	/* Parameter "NbrOfConversion" is discarded. */
bogdanm	0:9b334a45a8ff	484	/* Note: Scan mode is present by hardware on this device and, if */
bogdanm	0:9b334a45a8ff	485	/* disabled, discards automatically nb of conversions. Anyway, nb of */
bogdanm	0:9b334a45a8ff	486	/* conversions is forced to 0x00 for alignment over all STM32 devices. */
bogdanm	0:9b334a45a8ff	487	/* - if scan mode is enabled, regular channels sequence length is set to */
bogdanm	0:9b334a45a8ff	488	/* parameter "NbrOfConversion" */
bogdanm	0:9b334a45a8ff	489	if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
bogdanm	0:9b334a45a8ff	490	{
bogdanm	0:9b334a45a8ff	491	tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
bogdanm	0:9b334a45a8ff	492	}
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	MODIFY_REG(hadc->Instance->SQR1,
bogdanm	0:9b334a45a8ff	495	ADC_SQR1_L ,
bogdanm	0:9b334a45a8ff	496	tmp_sqr1 );
bogdanm	0:9b334a45a8ff	497
bogdanm	0:9b334a45a8ff	498	/* Check back that ADC registers have effectively been configured to */
bogdanm	0:9b334a45a8ff	499	/* ensure of no potential problem of ADC core IP clocking. */
bogdanm	0:9b334a45a8ff	500	/* Check through register CR2 (excluding bits set in other functions: */
bogdanm	0:9b334a45a8ff	501	/* execution control bits (ADON, JSWSTART, SWSTART), injected group bits */
bogdanm	0:9b334a45a8ff	502	/* (JEXTTRIG and JEXTSEL), channel internal measurement path bit (TSVREFE)*/
bogdanm	0:9b334a45a8ff	503	if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON \|
bogdanm	0:9b334a45a8ff	504	ADC_CR2_SWSTART \| ADC_CR2_JSWSTART \|
bogdanm	0:9b334a45a8ff	505	ADC_CR2_JEXTTRIG \| ADC_CR2_JEXTSEL \|
bogdanm	0:9b334a45a8ff	506	ADC_CR2_TSVREFE ))
bogdanm	0:9b334a45a8ff	507	== tmp_cr2)
bogdanm	0:9b334a45a8ff	508	{
bogdanm	0:9b334a45a8ff	509	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	510	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512	/* Initialize the ADC state */
bogdanm	0:9b334a45a8ff	513	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	514	}
bogdanm	0:9b334a45a8ff	515	else
bogdanm	0:9b334a45a8ff	516	{
bogdanm	0:9b334a45a8ff	517	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	518	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	519
bogdanm	0:9b334a45a8ff	520	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	521	hadc->ErrorCode \|= HAL_ADC_ERROR_INTERNAL;
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	tmp_hal_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	524	}
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	}
bogdanm	0:9b334a45a8ff	527	else
bogdanm	0:9b334a45a8ff	528	{
bogdanm	0:9b334a45a8ff	529	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	530	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	tmp_hal_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	533	}
bogdanm	0:9b334a45a8ff	534
bogdanm	0:9b334a45a8ff	535	/* Return function status */
bogdanm	0:9b334a45a8ff	536	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	537	}
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	/**
bogdanm	0:9b334a45a8ff	540	* @brief Deinitialize the ADC peripheral registers to their default reset
bogdanm	0:9b334a45a8ff	541	* values, with deinitialization of the ADC MSP.
bogdanm	0:9b334a45a8ff	542	* If needed, the example code can be copied and uncommented into
bogdanm	0:9b334a45a8ff	543	* function HAL_ADC_MspDeInit().
bogdanm	0:9b334a45a8ff	544	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	545	* @retval HAL status
bogdanm	0:9b334a45a8ff	546	*/
bogdanm	0:9b334a45a8ff	547	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	548	{
bogdanm	0:9b334a45a8ff	549	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551	/* Check ADC handle */
bogdanm	0:9b334a45a8ff	552	if(hadc == NULL)
bogdanm	0:9b334a45a8ff	553	{
bogdanm	0:9b334a45a8ff	554	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	555	}
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	/* Check the parameters */
bogdanm	0:9b334a45a8ff	558	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	/* Change ADC state */
bogdanm	0:9b334a45a8ff	561	hadc->State = HAL_ADC_STATE_BUSY;
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	564	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	565	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567
bogdanm	0:9b334a45a8ff	568	/* Configuration of ADC parameters if previous preliminary actions are */
bogdanm	0:9b334a45a8ff	569	/* correctly completed. */
bogdanm	0:9b334a45a8ff	570	if (tmp_hal_status != HAL_ERROR)
bogdanm	0:9b334a45a8ff	571	{
bogdanm	0:9b334a45a8ff	572	/* ========== Reset ADC registers ========== */
bogdanm	0:9b334a45a8ff	573
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575
bogdanm	0:9b334a45a8ff	576
bogdanm	0:9b334a45a8ff	577	/* Reset register SR */
bogdanm	0:9b334a45a8ff	578	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD \| ADC_FLAG_JEOC \| ADC_FLAG_EOC \|
bogdanm	0:9b334a45a8ff	579	ADC_FLAG_JSTRT \| ADC_FLAG_STRT));
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/* Reset register CR1 */
bogdanm	0:9b334a45a8ff	582	CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_DISCNUM \|
bogdanm	0:9b334a45a8ff	583	ADC_CR1_JDISCEN \| ADC_CR1_DISCEN \| ADC_CR1_JAUTO \|
bogdanm	0:9b334a45a8ff	584	ADC_CR1_AWDSGL \| ADC_CR1_SCAN \| ADC_CR1_JEOCIE \|
bogdanm	0:9b334a45a8ff	585	ADC_CR1_AWDIE \| ADC_CR1_EOCIE \| ADC_CR1_AWDCH ));
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	/* Reset register CR2 */
bogdanm	0:9b334a45a8ff	588	CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE \| ADC_CR2_SWSTART \| ADC_CR2_JSWSTART \|
bogdanm	0:9b334a45a8ff	589	ADC_CR2_EXTTRIG \| ADC_CR2_EXTSEL \| ADC_CR2_JEXTTRIG \|
bogdanm	0:9b334a45a8ff	590	ADC_CR2_JEXTSEL \| ADC_CR2_ALIGN \| ADC_CR2_DMA \|
bogdanm	0:9b334a45a8ff	591	ADC_CR2_RSTCAL \| ADC_CR2_CAL \| ADC_CR2_CONT \|
bogdanm	0:9b334a45a8ff	592	ADC_CR2_ADON ));
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594	/* Reset register SMPR1 */
bogdanm	0:9b334a45a8ff	595	CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 \| ADC_SMPR1_SMP16 \| ADC_SMPR1_SMP15 \|
bogdanm	0:9b334a45a8ff	596	ADC_SMPR1_SMP14 \| ADC_SMPR1_SMP13 \| ADC_SMPR1_SMP12 \|
bogdanm	0:9b334a45a8ff	597	ADC_SMPR1_SMP11 \| ADC_SMPR1_SMP10 ));
bogdanm	0:9b334a45a8ff	598
bogdanm	0:9b334a45a8ff	599	/* Reset register SMPR2 */
bogdanm	0:9b334a45a8ff	600	CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 \| ADC_SMPR2_SMP8 \| ADC_SMPR2_SMP7 \|
bogdanm	0:9b334a45a8ff	601	ADC_SMPR2_SMP6 \| ADC_SMPR2_SMP5 \| ADC_SMPR2_SMP4 \|
bogdanm	0:9b334a45a8ff	602	ADC_SMPR2_SMP3 \| ADC_SMPR2_SMP2 \| ADC_SMPR2_SMP1 \|
bogdanm	0:9b334a45a8ff	603	ADC_SMPR2_SMP0 ));
bogdanm	0:9b334a45a8ff	604
bogdanm	0:9b334a45a8ff	605	/* Reset register JOFR1 */
bogdanm	0:9b334a45a8ff	606	CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
bogdanm	0:9b334a45a8ff	607	/* Reset register JOFR2 */
bogdanm	0:9b334a45a8ff	608	CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
bogdanm	0:9b334a45a8ff	609	/* Reset register JOFR3 */
bogdanm	0:9b334a45a8ff	610	CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
bogdanm	0:9b334a45a8ff	611	/* Reset register JOFR4 */
bogdanm	0:9b334a45a8ff	612	CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
bogdanm	0:9b334a45a8ff	613
bogdanm	0:9b334a45a8ff	614	/* Reset register HTR */
bogdanm	0:9b334a45a8ff	615	CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
bogdanm	0:9b334a45a8ff	616	/* Reset register LTR */
bogdanm	0:9b334a45a8ff	617	CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619	/* Reset register SQR1 */
bogdanm	0:9b334a45a8ff	620	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L \|
bogdanm	0:9b334a45a8ff	621	ADC_SQR1_SQ16 \| ADC_SQR1_SQ15 \|
bogdanm	0:9b334a45a8ff	622	ADC_SQR1_SQ14 \| ADC_SQR1_SQ13 );
bogdanm	0:9b334a45a8ff	623
bogdanm	0:9b334a45a8ff	624	/* Reset register SQR1 */
bogdanm	0:9b334a45a8ff	625	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L \|
bogdanm	0:9b334a45a8ff	626	ADC_SQR1_SQ16 \| ADC_SQR1_SQ15 \|
bogdanm	0:9b334a45a8ff	627	ADC_SQR1_SQ14 \| ADC_SQR1_SQ13 );
bogdanm	0:9b334a45a8ff	628
bogdanm	0:9b334a45a8ff	629	/* Reset register SQR2 */
bogdanm	0:9b334a45a8ff	630	CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 \| ADC_SQR2_SQ11 \| ADC_SQR2_SQ10 \|
bogdanm	0:9b334a45a8ff	631	ADC_SQR2_SQ9 \| ADC_SQR2_SQ8 \| ADC_SQR2_SQ7 );
bogdanm	0:9b334a45a8ff	632
bogdanm	0:9b334a45a8ff	633	/* Reset register SQR3 */
bogdanm	0:9b334a45a8ff	634	CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 \| ADC_SQR3_SQ5 \| ADC_SQR3_SQ4 \|
bogdanm	0:9b334a45a8ff	635	ADC_SQR3_SQ3 \| ADC_SQR3_SQ2 \| ADC_SQR3_SQ1 );
bogdanm	0:9b334a45a8ff	636
bogdanm	0:9b334a45a8ff	637	/* Reset register JSQR */
bogdanm	0:9b334a45a8ff	638	CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL \|
bogdanm	0:9b334a45a8ff	639	ADC_JSQR_JSQ4 \| ADC_JSQR_JSQ3 \|
bogdanm	0:9b334a45a8ff	640	ADC_JSQR_JSQ2 \| ADC_JSQR_JSQ1 );
bogdanm	0:9b334a45a8ff	641
bogdanm	0:9b334a45a8ff	642	/* Reset register JSQR */
bogdanm	0:9b334a45a8ff	643	CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL \|
bogdanm	0:9b334a45a8ff	644	ADC_JSQR_JSQ4 \| ADC_JSQR_JSQ3 \|
bogdanm	0:9b334a45a8ff	645	ADC_JSQR_JSQ2 \| ADC_JSQR_JSQ1 );
bogdanm	0:9b334a45a8ff	646
bogdanm	0:9b334a45a8ff	647	/* Reset register DR */
bogdanm	0:9b334a45a8ff	648	/* bits in access mode read only, no direct reset applicable*/
bogdanm	0:9b334a45a8ff	649
bogdanm	0:9b334a45a8ff	650	/* Reset registers JDR1, JDR2, JDR3, JDR4 */
bogdanm	0:9b334a45a8ff	651	/* bits in access mode read only, no direct reset applicable*/
bogdanm	0:9b334a45a8ff	652
bogdanm	0:9b334a45a8ff	653	/* ========== Hard reset ADC peripheral ========== */
bogdanm	0:9b334a45a8ff	654	/* Performs a global reset of the entire ADC peripheral: ADC state is */
bogdanm	0:9b334a45a8ff	655	/* forced to a similar state after device power-on. */
bogdanm	0:9b334a45a8ff	656	/* If needed, copy-paste and uncomment the following reset code into */
bogdanm	0:9b334a45a8ff	657	/* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
bogdanm	0:9b334a45a8ff	658	/* */
bogdanm	0:9b334a45a8ff	659	/* __HAL_RCC_ADC1_FORCE_RESET() */
bogdanm	0:9b334a45a8ff	660	/* __HAL_RCC_ADC1_RELEASE_RESET() */
bogdanm	0:9b334a45a8ff	661
bogdanm	0:9b334a45a8ff	662	/* DeInit the low level hardware */
bogdanm	0:9b334a45a8ff	663	HAL_ADC_MspDeInit(hadc);
bogdanm	0:9b334a45a8ff	664
bogdanm	0:9b334a45a8ff	665	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	666	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668	/* Change ADC state */
bogdanm	0:9b334a45a8ff	669	hadc->State = HAL_ADC_STATE_RESET;
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	}
bogdanm	0:9b334a45a8ff	672
bogdanm	0:9b334a45a8ff	673	/* Process unlocked */
bogdanm	0:9b334a45a8ff	674	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	675
bogdanm	0:9b334a45a8ff	676	/* Return function status */
bogdanm	0:9b334a45a8ff	677	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	678	}
bogdanm	0:9b334a45a8ff	679
bogdanm	0:9b334a45a8ff	680	/**
bogdanm	0:9b334a45a8ff	681	* @brief Initializes the ADC MSP.
bogdanm	0:9b334a45a8ff	682	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	683	* @retval None
bogdanm	0:9b334a45a8ff	684	*/
bogdanm	0:9b334a45a8ff	685	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	686	{
bogdanm	0:9b334a45a8ff	687	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	688	function HAL_ADC_MspInit must be implemented in the user file.
bogdanm	0:9b334a45a8ff	689	*/
bogdanm	0:9b334a45a8ff	690	}
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	/**
bogdanm	0:9b334a45a8ff	693	* @brief DeInitializes the ADC MSP.
bogdanm	0:9b334a45a8ff	694	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	695	* @retval None
bogdanm	0:9b334a45a8ff	696	*/
bogdanm	0:9b334a45a8ff	697	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	698	{
bogdanm	0:9b334a45a8ff	699	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	700	function HAL_ADC_MspDeInit must be implemented in the user file.
bogdanm	0:9b334a45a8ff	701	*/
bogdanm	0:9b334a45a8ff	702	}
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	/**
bogdanm	0:9b334a45a8ff	705	* @}
bogdanm	0:9b334a45a8ff	706	*/
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	709	* @brief Input and Output operation functions
bogdanm	0:9b334a45a8ff	710	*
bogdanm	0:9b334a45a8ff	711	@verbatim
bogdanm	0:9b334a45a8ff	712	===============================================================================
bogdanm	0:9b334a45a8ff	713	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	714	===============================================================================
bogdanm	0:9b334a45a8ff	715	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	716	(+) Start conversion of regular group.
bogdanm	0:9b334a45a8ff	717	(+) Stop conversion of regular group.
bogdanm	0:9b334a45a8ff	718	(+) Poll for conversion complete on regular group.
bogdanm	0:9b334a45a8ff	719	(+) Poll for conversion event.
bogdanm	0:9b334a45a8ff	720	(+) Get result of regular channel conversion.
bogdanm	0:9b334a45a8ff	721	(+) Start conversion of regular group and enable interruptions.
bogdanm	0:9b334a45a8ff	722	(+) Stop conversion of regular group and disable interruptions.
bogdanm	0:9b334a45a8ff	723	(+) Handle ADC interrupt request
bogdanm	0:9b334a45a8ff	724	(+) Start conversion of regular group and enable DMA transfer.
bogdanm	0:9b334a45a8ff	725	(+) Stop conversion of regular group and disable ADC DMA transfer.
bogdanm	0:9b334a45a8ff	726	@endverbatim
bogdanm	0:9b334a45a8ff	727	* @{
bogdanm	0:9b334a45a8ff	728	*/
bogdanm	0:9b334a45a8ff	729
bogdanm	0:9b334a45a8ff	730	/**
bogdanm	0:9b334a45a8ff	731	* @brief Enables ADC, starts conversion of regular group.
bogdanm	0:9b334a45a8ff	732	* Interruptions enabled in this function: None.
bogdanm	0:9b334a45a8ff	733	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	734	* @retval HAL status
bogdanm	0:9b334a45a8ff	735	*/
bogdanm	0:9b334a45a8ff	736	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	737	{
bogdanm	0:9b334a45a8ff	738	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	/* Check the parameters */
bogdanm	0:9b334a45a8ff	741	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	742
bogdanm	0:9b334a45a8ff	743	/* Process locked */
bogdanm	0:9b334a45a8ff	744	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	747	tmp_hal_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	748
bogdanm	0:9b334a45a8ff	749	/* Start conversion if ADC is effectively enabled */
bogdanm	0:9b334a45a8ff	750	if (tmp_hal_status != HAL_ERROR)
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	/* State machine update: Check if an injected conversion is ongoing */
bogdanm	0:9b334a45a8ff	753	if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
bogdanm	0:9b334a45a8ff	754	{
bogdanm	0:9b334a45a8ff	755	/* Change ADC state */
bogdanm	0:9b334a45a8ff	756	hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
bogdanm	0:9b334a45a8ff	757	}
bogdanm	0:9b334a45a8ff	758	else
bogdanm	0:9b334a45a8ff	759	{
bogdanm	0:9b334a45a8ff	760	/* Change ADC state */
bogdanm	0:9b334a45a8ff	761	hadc->State = HAL_ADC_STATE_BUSY_REG;
bogdanm	0:9b334a45a8ff	762	}
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764	/* Process unlocked */
bogdanm	0:9b334a45a8ff	765	/* Unlock before starting ADC conversions: in case of potential */
bogdanm	0:9b334a45a8ff	766	/* interruption, to let the process to ADC IRQ Handler. */
bogdanm	0:9b334a45a8ff	767	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	768
bogdanm	0:9b334a45a8ff	769	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	770	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	771
bogdanm	0:9b334a45a8ff	772	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	773	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	774	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	/* Enable conversion of regular group. */
bogdanm	0:9b334a45a8ff	777	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	778	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	779	/* trigger event. */
bogdanm	0:9b334a45a8ff	780	/* Case of multimode enabled (for devices with several ADCs): if ADC is */
bogdanm	0:9b334a45a8ff	781	/* slave, ADC is enabled only (conversion is not started). If ADC is */
bogdanm	0:9b334a45a8ff	782	/* master, ADC is enabled and conversion is started. */
bogdanm	0:9b334a45a8ff	783	/* Note: Alternate trigger for single conversion could be to force an */
bogdanm	0:9b334a45a8ff	784	/* additional set of bit ADON "hadc->Instance->CR2 \|= ADC_CR2_ADON;"*/
bogdanm	0:9b334a45a8ff	785	if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
bogdanm	0:9b334a45a8ff	786	ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
bogdanm	0:9b334a45a8ff	787	{
bogdanm	0:9b334a45a8ff	788	/* Start ADC conversion on regular group with SW start */
bogdanm	0:9b334a45a8ff	789	SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART \| ADC_CR2_EXTTRIG));
bogdanm	0:9b334a45a8ff	790	}
bogdanm	0:9b334a45a8ff	791	else
bogdanm	0:9b334a45a8ff	792	{
bogdanm	0:9b334a45a8ff	793	/* Start ADC conversion on regular group with external trigger */
bogdanm	0:9b334a45a8ff	794	SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
bogdanm	0:9b334a45a8ff	795	}
bogdanm	0:9b334a45a8ff	796	}
bogdanm	0:9b334a45a8ff	797	else
bogdanm	0:9b334a45a8ff	798	{
bogdanm	0:9b334a45a8ff	799	/* Process unlocked */
bogdanm	0:9b334a45a8ff	800	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	801	}
bogdanm	0:9b334a45a8ff	802
bogdanm	0:9b334a45a8ff	803	/* Return function status */
bogdanm	0:9b334a45a8ff	804	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	805	}
bogdanm	0:9b334a45a8ff	806
bogdanm	0:9b334a45a8ff	807	/**
bogdanm	0:9b334a45a8ff	808	* @brief Stop ADC conversion of regular group (and injected channels in
bogdanm	0:9b334a45a8ff	809	* case of auto_injection mode), disable ADC peripheral.
bogdanm	0:9b334a45a8ff	810	* @note: ADC peripheral disable is forcing stop of potential
bogdanm	0:9b334a45a8ff	811	* conversion on injected group. If injected group is under use, it
bogdanm	0:9b334a45a8ff	812	* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
bogdanm	0:9b334a45a8ff	813	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	814	* @retval HAL status.
bogdanm	0:9b334a45a8ff	815	*/
bogdanm	0:9b334a45a8ff	816	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	817	{
bogdanm	0:9b334a45a8ff	818	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820	/* Check the parameters */
bogdanm	0:9b334a45a8ff	821	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	/* Process locked */
bogdanm	0:9b334a45a8ff	824	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	825
bogdanm	0:9b334a45a8ff	826	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	827	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	828	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	831	if (tmp_hal_status != HAL_ERROR)
bogdanm	0:9b334a45a8ff	832	{
bogdanm	0:9b334a45a8ff	833	/* Change ADC state */
bogdanm	0:9b334a45a8ff	834	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	835	}
bogdanm	0:9b334a45a8ff	836
bogdanm	0:9b334a45a8ff	837	/* Process unlocked */
bogdanm	0:9b334a45a8ff	838	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	/* Return function status */
bogdanm	0:9b334a45a8ff	841	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	842	}
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/**
bogdanm	0:9b334a45a8ff	845	* @brief Wait for regular group conversion to be completed.
bogdanm	0:9b334a45a8ff	846	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	847	* @param Timeout: Timeout value in millisecond.
bogdanm	0:9b334a45a8ff	848	* @retval HAL status
bogdanm	0:9b334a45a8ff	849	*/
bogdanm	0:9b334a45a8ff	850	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	851	{
bogdanm	0:9b334a45a8ff	852	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	/* Variables for polling in case of scan mode enabled and polling for each */
bogdanm	0:9b334a45a8ff	855	/* conversion. */
bogdanm	0:9b334a45a8ff	856	__IO uint32_t Conversion_Timeout_CPU_cycles = 0;
bogdanm	0:9b334a45a8ff	857	uint32_t Conversion_Timeout_CPU_cycles_max = 0;
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	/* Check the parameters */
bogdanm	0:9b334a45a8ff	860	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	861
bogdanm	0:9b334a45a8ff	862	/* Get timeout */
bogdanm	0:9b334a45a8ff	863	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/* Polling for end of conversion: differentiation if single/sequence */
bogdanm	0:9b334a45a8ff	866	/* conversion. */
bogdanm	0:9b334a45a8ff	867	/* - If single conversion for regular group (Scan mode disabled or enabled */
bogdanm	0:9b334a45a8ff	868	/* with NbrOfConversion =1), flag EOC is used to determine the */
bogdanm	0:9b334a45a8ff	869	/* conversion completion. */
bogdanm	0:9b334a45a8ff	870	/* - If sequence conversion for regular group, flag EOC is set only a the */
bogdanm	0:9b334a45a8ff	871	/* end of the sequence. To poll for each conversion, the maximum */
bogdanm	0:9b334a45a8ff	872	/* conversion time is calculated from ADC conversion time (selected */
bogdanm	0:9b334a45a8ff	873	/* sampling time + conversion time of 12.5 ADC clock cycles) and */
bogdanm	0:9b334a45a8ff	874	/* APB2/ADC clock prescalers (depending on settings, conversion time */
bogdanm	0:9b334a45a8ff	875	/* range can be from 28 to 32256 CPU cycles). */
bogdanm	0:9b334a45a8ff	876	if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
bogdanm	0:9b334a45a8ff	877	HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
bogdanm	0:9b334a45a8ff	878	{
bogdanm	0:9b334a45a8ff	879	/* Wait until End of Conversion flag is raised */
bogdanm	0:9b334a45a8ff	880	while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
bogdanm	0:9b334a45a8ff	881	{
bogdanm	0:9b334a45a8ff	882	/* Check if timeout is disabled (set to infinite wait) */
bogdanm	0:9b334a45a8ff	883	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	884	{
bogdanm	0:9b334a45a8ff	885	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	886	{
bogdanm	0:9b334a45a8ff	887	/* Update ADC state machine to timeout */
bogdanm	0:9b334a45a8ff	888	hadc->State = HAL_ADC_STATE_TIMEOUT;
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/* Process unlocked */
bogdanm	0:9b334a45a8ff	891	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	892
bogdanm	0:9b334a45a8ff	893	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	894	}
bogdanm	0:9b334a45a8ff	895	}
bogdanm	0:9b334a45a8ff	896	}
bogdanm	0:9b334a45a8ff	897	}
bogdanm	0:9b334a45a8ff	898	else
bogdanm	0:9b334a45a8ff	899	{
bogdanm	0:9b334a45a8ff	900	/* Poll with maximum conversion time */
bogdanm	0:9b334a45a8ff	901	/* - Computation of CPU clock cycles corresponding to ADC clock cycles */
bogdanm	0:9b334a45a8ff	902	/* and ADC maximum conversion cycles on all channels. */
bogdanm	0:9b334a45a8ff	903	/* - Wait for the expected ADC clock cycles delay */
bogdanm	0:9b334a45a8ff	904	Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
bogdanm	0:9b334a45a8ff	905	/ HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
bogdanm	0:9b334a45a8ff	906	* ADC_CONVCYCLES_MAX_RANGE(hadc) );
bogdanm	0:9b334a45a8ff	907
bogdanm	0:9b334a45a8ff	908	while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
bogdanm	0:9b334a45a8ff	909	{
bogdanm	0:9b334a45a8ff	910	/* Check if timeout is disabled (set to infinite wait) */
bogdanm	0:9b334a45a8ff	911	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	912	{
bogdanm	0:9b334a45a8ff	913	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	914	{
bogdanm	0:9b334a45a8ff	915	/* Update ADC state machine to timeout */
bogdanm	0:9b334a45a8ff	916	hadc->State = HAL_ADC_STATE_TIMEOUT;
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	/* Process unlocked */
bogdanm	0:9b334a45a8ff	919	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	922	}
bogdanm	0:9b334a45a8ff	923	}
bogdanm	0:9b334a45a8ff	924	Conversion_Timeout_CPU_cycles ++;
bogdanm	0:9b334a45a8ff	925	}
bogdanm	0:9b334a45a8ff	926	}
bogdanm	0:9b334a45a8ff	927
bogdanm	0:9b334a45a8ff	928	/* Clear regular group conversion flag */
bogdanm	0:9b334a45a8ff	929	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT \| ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	930
bogdanm	0:9b334a45a8ff	931	/* Update state machine on conversion status if not in error state */
bogdanm	0:9b334a45a8ff	932	if(hadc->State != HAL_ADC_STATE_ERROR)
bogdanm	0:9b334a45a8ff	933	{
bogdanm	0:9b334a45a8ff	934	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	935	if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
bogdanm	0:9b334a45a8ff	936	{
bogdanm	0:9b334a45a8ff	937	/* Check if a conversion is ready on injected group */
bogdanm	0:9b334a45a8ff	938	if(hadc->State == HAL_ADC_STATE_EOC_INJ)
bogdanm	0:9b334a45a8ff	939	{
bogdanm	0:9b334a45a8ff	940	/* Change ADC state */
bogdanm	0:9b334a45a8ff	941	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	942	}
bogdanm	0:9b334a45a8ff	943	else
bogdanm	0:9b334a45a8ff	944	{
bogdanm	0:9b334a45a8ff	945	/* Change ADC state */
bogdanm	0:9b334a45a8ff	946	hadc->State = HAL_ADC_STATE_EOC_REG;
bogdanm	0:9b334a45a8ff	947	}
bogdanm	0:9b334a45a8ff	948	}
bogdanm	0:9b334a45a8ff	949	}
bogdanm	0:9b334a45a8ff	950
bogdanm	0:9b334a45a8ff	951	/* Return ADC state */
bogdanm	0:9b334a45a8ff	952	return HAL_OK;
bogdanm	0:9b334a45a8ff	953	}
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	/**
bogdanm	0:9b334a45a8ff	956	* @brief Poll for conversion event.
bogdanm	0:9b334a45a8ff	957	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	958	* @param EventType: the ADC event type.
bogdanm	0:9b334a45a8ff	959	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	960	* @arg ADC_AWD_EVENT: ADC Analog watchdog event.
bogdanm	0:9b334a45a8ff	961	* @param Timeout: Timeout value in millisecond.
bogdanm	0:9b334a45a8ff	962	* @retval HAL status
bogdanm	0:9b334a45a8ff	963	*/
bogdanm	0:9b334a45a8ff	964	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	965	{
bogdanm	0:9b334a45a8ff	966	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	/* Check the parameters */
bogdanm	0:9b334a45a8ff	969	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	970	assert_param(IS_ADC_EVENT_TYPE(EventType));
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/* Get start tick count */
bogdanm	0:9b334a45a8ff	973	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	974
bogdanm	0:9b334a45a8ff	975	/* Check selected event flag */
bogdanm	0:9b334a45a8ff	976	while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
bogdanm	0:9b334a45a8ff	977	{
bogdanm	0:9b334a45a8ff	978	/* Check if timeout is disabled (set to infinite wait) */
bogdanm	0:9b334a45a8ff	979	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	980	{
bogdanm	0:9b334a45a8ff	981	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	982	{
bogdanm	0:9b334a45a8ff	983	/* Update ADC state machine to timeout */
bogdanm	0:9b334a45a8ff	984	hadc->State = HAL_ADC_STATE_TIMEOUT;
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/* Process unlocked */
bogdanm	0:9b334a45a8ff	987	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	990	}
bogdanm	0:9b334a45a8ff	991	}
bogdanm	0:9b334a45a8ff	992	}
bogdanm	0:9b334a45a8ff	993
bogdanm	0:9b334a45a8ff	994	/* Analog watchdog (level out of window) event */
bogdanm	0:9b334a45a8ff	995	/* Change ADC state */
bogdanm	0:9b334a45a8ff	996	hadc->State = HAL_ADC_STATE_AWD;
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	/* Clear ADC analog watchdog flag */
bogdanm	0:9b334a45a8ff	999	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001	/* Return ADC state */
bogdanm	0:9b334a45a8ff	1002	return HAL_OK;
bogdanm	0:9b334a45a8ff	1003	}
bogdanm	0:9b334a45a8ff	1004
bogdanm	0:9b334a45a8ff	1005	/**
bogdanm	0:9b334a45a8ff	1006	* @brief Enables ADC, starts conversion of regular group with interruption.
bogdanm	0:9b334a45a8ff	1007	* Interruptions enabled in this function:
bogdanm	0:9b334a45a8ff	1008	* - EOC (end of conversion of regular group)
bogdanm	0:9b334a45a8ff	1009	* Each of these interruptions has its dedicated callback function.
bogdanm	0:9b334a45a8ff	1010	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1011	* @retval HAL status
bogdanm	0:9b334a45a8ff	1012	*/
bogdanm	0:9b334a45a8ff	1013	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1014	{
bogdanm	0:9b334a45a8ff	1015	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1018	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	/* Process locked */
bogdanm	0:9b334a45a8ff	1021	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1024	tmp_hal_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/* Start conversion if ADC is effectively enabled */
bogdanm	0:9b334a45a8ff	1027	if (tmp_hal_status != HAL_ERROR)
bogdanm	0:9b334a45a8ff	1028	{
bogdanm	0:9b334a45a8ff	1029	/* State machine update: Check if an injected conversion is ongoing */
bogdanm	0:9b334a45a8ff	1030	if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
bogdanm	0:9b334a45a8ff	1031	{
bogdanm	0:9b334a45a8ff	1032	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1033	hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
bogdanm	0:9b334a45a8ff	1034	}
bogdanm	0:9b334a45a8ff	1035	else
bogdanm	0:9b334a45a8ff	1036	{
bogdanm	0:9b334a45a8ff	1037	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1038	hadc->State = HAL_ADC_STATE_BUSY_REG;
bogdanm	0:9b334a45a8ff	1039	}
bogdanm	0:9b334a45a8ff	1040
bogdanm	0:9b334a45a8ff	1041	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1042	/* Unlock before starting ADC conversions: in case of potential */
bogdanm	0:9b334a45a8ff	1043	/* interruption, to let the process to ADC IRQ Handler. */
bogdanm	0:9b334a45a8ff	1044	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1045
bogdanm	0:9b334a45a8ff	1046	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	1047	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	1050	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	1051	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	1052
bogdanm	0:9b334a45a8ff	1053	/* Enable end of conversion interrupt for regular group */
bogdanm	0:9b334a45a8ff	1054	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	1055
bogdanm	0:9b334a45a8ff	1056	/* Enable conversion of regular group. */
bogdanm	0:9b334a45a8ff	1057	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	1058	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	1059	/* trigger event. */
bogdanm	0:9b334a45a8ff	1060	/* Case of multimode enabled (for devices with several ADCs): if ADC is */
bogdanm	0:9b334a45a8ff	1061	/* slave, ADC is enabled only (conversion is not started). If ADC is */
bogdanm	0:9b334a45a8ff	1062	/* master, ADC is enabled and conversion is started. */
bogdanm	0:9b334a45a8ff	1063	if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
bogdanm	0:9b334a45a8ff	1064	ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
bogdanm	0:9b334a45a8ff	1065	{
bogdanm	0:9b334a45a8ff	1066	/* Start ADC conversion on regular group with SW start */
bogdanm	0:9b334a45a8ff	1067	SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART \| ADC_CR2_EXTTRIG));
bogdanm	0:9b334a45a8ff	1068	}
bogdanm	0:9b334a45a8ff	1069	else
bogdanm	0:9b334a45a8ff	1070	{
bogdanm	0:9b334a45a8ff	1071	/* Start ADC conversion on regular group with external trigger */
bogdanm	0:9b334a45a8ff	1072	SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
bogdanm	0:9b334a45a8ff	1073	}
bogdanm	0:9b334a45a8ff	1074	}
bogdanm	0:9b334a45a8ff	1075	else
bogdanm	0:9b334a45a8ff	1076	{
bogdanm	0:9b334a45a8ff	1077	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1078	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1079	}
bogdanm	0:9b334a45a8ff	1080
bogdanm	0:9b334a45a8ff	1081	/* Return function status */
bogdanm	0:9b334a45a8ff	1082	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	1083	}
bogdanm	0:9b334a45a8ff	1084
bogdanm	0:9b334a45a8ff	1085	/**
bogdanm	0:9b334a45a8ff	1086	* @brief Stop ADC conversion of regular group (and injected group in
bogdanm	0:9b334a45a8ff	1087	* case of auto_injection mode), disable interrution of
bogdanm	0:9b334a45a8ff	1088	* end-of-conversion, disable ADC peripheral.
bogdanm	0:9b334a45a8ff	1089	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1090	* @retval None
bogdanm	0:9b334a45a8ff	1091	*/
bogdanm	0:9b334a45a8ff	1092	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1093	{
bogdanm	0:9b334a45a8ff	1094	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1095
bogdanm	0:9b334a45a8ff	1096	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1097	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	/* Process locked */
bogdanm	0:9b334a45a8ff	1100	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1101
bogdanm	0:9b334a45a8ff	1102	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	1103	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	1104	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	1105
bogdanm	0:9b334a45a8ff	1106	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	1107	if (tmp_hal_status != HAL_ERROR)
bogdanm	0:9b334a45a8ff	1108	{
bogdanm	0:9b334a45a8ff	1109	/* Disable ADC end of conversion interrupt for regular group */
bogdanm	0:9b334a45a8ff	1110	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1113	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	1114	}
bogdanm	0:9b334a45a8ff	1115
bogdanm	0:9b334a45a8ff	1116	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1117	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119	/* Return function status */
bogdanm	0:9b334a45a8ff	1120	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	1121	}
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	/**
bogdanm	0:9b334a45a8ff	1124	* @brief Enables ADC, starts conversion of regular group and transfers result
bogdanm	0:9b334a45a8ff	1125	* through DMA.
bogdanm	0:9b334a45a8ff	1126	* Interruptions enabled in this function:
bogdanm	0:9b334a45a8ff	1127	* - DMA transfer complete
bogdanm	0:9b334a45a8ff	1128	* - DMA half transfer
bogdanm	0:9b334a45a8ff	1129	* Each of these interruptions has its dedicated callback function.
bogdanm	0:9b334a45a8ff	1130	* @note For devices with several ADCs: This function is for single-ADC mode
bogdanm	0:9b334a45a8ff	1131	* only. For multimode, use the dedicated MultimodeStart function.
bogdanm	0:9b334a45a8ff	1132	* @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
bogdanm	0:9b334a45a8ff	1133	* on devices) have DMA capability.
bogdanm	0:9b334a45a8ff	1134	* ADC2 converted data can be transferred in dual ADC mode using DMA
bogdanm	0:9b334a45a8ff	1135	* of ADC1 (ADC master in multimode).
bogdanm	0:9b334a45a8ff	1136	* In case of using ADC1 with DMA on a device featuring 2 ADC
bogdanm	0:9b334a45a8ff	1137	* instances: ADC1 conversion register DR contains ADC1 conversion
bogdanm	0:9b334a45a8ff	1138	* result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last
bogdanm	0:9b334a45a8ff	1139	* conversion result (ADC1 register DR bits 16 to 27). Therefore, to
bogdanm	0:9b334a45a8ff	1140	* have DMA transferring the conversion results of ADC1 only, DMA must
bogdanm	0:9b334a45a8ff	1141	* be configured to transfer size: half word.
bogdanm	0:9b334a45a8ff	1142	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1143	* @param pData: The destination Buffer address.
bogdanm	0:9b334a45a8ff	1144	* @param Length: The length of data to be transferred from ADC peripheral to memory.
bogdanm	0:9b334a45a8ff	1145	* @retval None
bogdanm	0:9b334a45a8ff	1146	*/
bogdanm	0:9b334a45a8ff	1147	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
bogdanm	0:9b334a45a8ff	1148	{
bogdanm	0:9b334a45a8ff	1149	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1152	assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	/* Verification if multimode is disabled (for devices with several ADC) */
bogdanm	0:9b334a45a8ff	1155	/* If multimode is enabled, dedicated function multimode conversion */
bogdanm	0:9b334a45a8ff	1156	/* start DMA must be used. */
bogdanm	0:9b334a45a8ff	1157	if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1158	{
bogdanm	0:9b334a45a8ff	1159	/* Process locked */
bogdanm	0:9b334a45a8ff	1160	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1161
bogdanm	0:9b334a45a8ff	1162	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1163	tmp_hal_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	/* Start conversion if ADC is effectively enabled */
bogdanm	0:9b334a45a8ff	1166	if (tmp_hal_status != HAL_ERROR)
bogdanm	0:9b334a45a8ff	1167	{
bogdanm	0:9b334a45a8ff	1168	/* State machine update: Check if an injected conversion is ongoing */
bogdanm	0:9b334a45a8ff	1169	if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
bogdanm	0:9b334a45a8ff	1170	{
bogdanm	0:9b334a45a8ff	1171	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1172	hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
bogdanm	0:9b334a45a8ff	1173	}
bogdanm	0:9b334a45a8ff	1174	else
bogdanm	0:9b334a45a8ff	1175	{
bogdanm	0:9b334a45a8ff	1176	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1177	hadc->State = HAL_ADC_STATE_BUSY_REG;
bogdanm	0:9b334a45a8ff	1178	}
bogdanm	0:9b334a45a8ff	1179
bogdanm	0:9b334a45a8ff	1180	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1181	/* Unlock before starting ADC conversions: in case of potential */
bogdanm	0:9b334a45a8ff	1182	/* interruption, to let the process to ADC IRQ Handler. */
bogdanm	0:9b334a45a8ff	1183	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	1186	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	1187
bogdanm	0:9b334a45a8ff	1188	/* Set the DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1189	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
bogdanm	0:9b334a45a8ff	1190
bogdanm	0:9b334a45a8ff	1191	/* Set the DMA half transfer complete callback */
bogdanm	0:9b334a45a8ff	1192	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1195	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
bogdanm	0:9b334a45a8ff	1196
bogdanm	0:9b334a45a8ff	1197
bogdanm	0:9b334a45a8ff	1198	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
bogdanm	0:9b334a45a8ff	1199	/* start (in case of SW start): */
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	1202	/* (To ensure of no unknown state from potential previous ADC */
bogdanm	0:9b334a45a8ff	1203	/* operations) */
bogdanm	0:9b334a45a8ff	1204	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206	/* Enable ADC DMA mode */
bogdanm	0:9b334a45a8ff	1207	SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209	/* Start the DMA channel */
bogdanm	0:9b334a45a8ff	1210	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1211
bogdanm	0:9b334a45a8ff	1212	/* Enable conversion of regular group. */
bogdanm	0:9b334a45a8ff	1213	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	1214	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	1215	/* trigger event. */
bogdanm	0:9b334a45a8ff	1216	if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	1217	{
bogdanm	0:9b334a45a8ff	1218	/* Start ADC conversion on regular group with SW start */
bogdanm	0:9b334a45a8ff	1219	SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART \| ADC_CR2_EXTTRIG));
bogdanm	0:9b334a45a8ff	1220	}
bogdanm	0:9b334a45a8ff	1221	else
bogdanm	0:9b334a45a8ff	1222	{
bogdanm	0:9b334a45a8ff	1223	/* Start ADC conversion on regular group with external trigger */
bogdanm	0:9b334a45a8ff	1224	SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
bogdanm	0:9b334a45a8ff	1225	}
bogdanm	0:9b334a45a8ff	1226	}
bogdanm	0:9b334a45a8ff	1227	else
bogdanm	0:9b334a45a8ff	1228	{
bogdanm	0:9b334a45a8ff	1229	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1230	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1231	}
bogdanm	0:9b334a45a8ff	1232	}
bogdanm	0:9b334a45a8ff	1233	else
bogdanm	0:9b334a45a8ff	1234	{
bogdanm	0:9b334a45a8ff	1235	tmp_hal_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1236	}
bogdanm	0:9b334a45a8ff	1237
bogdanm	0:9b334a45a8ff	1238	/* Return function status */
bogdanm	0:9b334a45a8ff	1239	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	1240	}
bogdanm	0:9b334a45a8ff	1241
bogdanm	0:9b334a45a8ff	1242	/**
bogdanm	0:9b334a45a8ff	1243	* @brief Stop ADC conversion of regular group (and injected group in
bogdanm	0:9b334a45a8ff	1244	* case of auto_injection mode), disable ADC DMA transfer, disable
bogdanm	0:9b334a45a8ff	1245	* ADC peripheral.
bogdanm	0:9b334a45a8ff	1246	* @note: ADC peripheral disable is forcing stop of potential
bogdanm	0:9b334a45a8ff	1247	* conversion on injected group. If injected group is under use, it
bogdanm	0:9b334a45a8ff	1248	* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
bogdanm	0:9b334a45a8ff	1249	* @note For devices with several ADCs: This function is for single-ADC mode
bogdanm	0:9b334a45a8ff	1250	* only. For multimode, use the dedicated MultimodeStop function.
bogdanm	0:9b334a45a8ff	1251	* @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
bogdanm	0:9b334a45a8ff	1252	* on devices) have DMA capability.
bogdanm	0:9b334a45a8ff	1253	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1254	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1255	*/
bogdanm	0:9b334a45a8ff	1256	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1257	{
bogdanm	0:9b334a45a8ff	1258	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1259
bogdanm	0:9b334a45a8ff	1260	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1261	assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1262
bogdanm	0:9b334a45a8ff	1263	/* Process locked */
bogdanm	0:9b334a45a8ff	1264	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1265
bogdanm	0:9b334a45a8ff	1266	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	1267	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	1268	tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	1269
bogdanm	0:9b334a45a8ff	1270	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	1271	if (tmp_hal_status != HAL_ERROR)
bogdanm	0:9b334a45a8ff	1272	{
bogdanm	0:9b334a45a8ff	1273	/* Disable ADC DMA mode */
bogdanm	0:9b334a45a8ff	1274	CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	/* Disable the DMA channel (in case of DMA in circular mode or stop while */
bogdanm	0:9b334a45a8ff	1277	/* DMA transfer is on going) */
bogdanm	0:9b334a45a8ff	1278	tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/* Check if DMA channel effectively disabled */
bogdanm	0:9b334a45a8ff	1281	if (tmp_hal_status != HAL_ERROR)
bogdanm	0:9b334a45a8ff	1282	{
bogdanm	0:9b334a45a8ff	1283	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1284	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	1285	}
bogdanm	0:9b334a45a8ff	1286	else
bogdanm	0:9b334a45a8ff	1287	{
bogdanm	0:9b334a45a8ff	1288	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1289	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1290	}
bogdanm	0:9b334a45a8ff	1291	}
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1294	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	/* Return function status */
bogdanm	0:9b334a45a8ff	1297	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	1298	}
bogdanm	0:9b334a45a8ff	1299
bogdanm	0:9b334a45a8ff	1300	/**
bogdanm	0:9b334a45a8ff	1301	* @brief Get ADC regular group conversion result.
bogdanm	0:9b334a45a8ff	1302	* @note Reading DR register automatically clears EOC (end of conversion of
bogdanm	0:9b334a45a8ff	1303	* regular group) flag.
bogdanm	0:9b334a45a8ff	1304	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1305	* @retval Converted value
bogdanm	0:9b334a45a8ff	1306	*/
bogdanm	0:9b334a45a8ff	1307	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1308	{
bogdanm	0:9b334a45a8ff	1309	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1310	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/* Note: EOC flag is not cleared here by software because automatically */
bogdanm	0:9b334a45a8ff	1313	/* cleared by hardware when reading register DR. */
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	/* Return ADC converted value */
bogdanm	0:9b334a45a8ff	1316	return hadc->Instance->DR;
bogdanm	0:9b334a45a8ff	1317	}
bogdanm	0:9b334a45a8ff	1318
bogdanm	0:9b334a45a8ff	1319	/**
bogdanm	0:9b334a45a8ff	1320	* @brief Handles ADC interrupt request
bogdanm	0:9b334a45a8ff	1321	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1322	* @retval None
bogdanm	0:9b334a45a8ff	1323	*/
bogdanm	0:9b334a45a8ff	1324	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1325	{
bogdanm	0:9b334a45a8ff	1326	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1327	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1328	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	1329	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
bogdanm	0:9b334a45a8ff	1330
bogdanm	0:9b334a45a8ff	1331
bogdanm	0:9b334a45a8ff	1332	/* ========== Check End of Conversion flag for regular group ========== */
bogdanm	0:9b334a45a8ff	1333	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
bogdanm	0:9b334a45a8ff	1334	{
bogdanm	0:9b334a45a8ff	1335	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
bogdanm	0:9b334a45a8ff	1336	{
bogdanm	0:9b334a45a8ff	1337	/* Update state machine on conversion status if not in error state */
bogdanm	0:9b334a45a8ff	1338	if(hadc->State != HAL_ADC_STATE_ERROR)
bogdanm	0:9b334a45a8ff	1339	{
bogdanm	0:9b334a45a8ff	1340	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	1341	if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
bogdanm	0:9b334a45a8ff	1342	{
bogdanm	0:9b334a45a8ff	1343	/* Check if a conversion is ready on injected group */
bogdanm	0:9b334a45a8ff	1344	if(hadc->State == HAL_ADC_STATE_EOC_INJ)
bogdanm	0:9b334a45a8ff	1345	{
bogdanm	0:9b334a45a8ff	1346	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1347	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	1348	}
bogdanm	0:9b334a45a8ff	1349	else
bogdanm	0:9b334a45a8ff	1350	{
bogdanm	0:9b334a45a8ff	1351	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1352	hadc->State = HAL_ADC_STATE_EOC_REG;
bogdanm	0:9b334a45a8ff	1353	}
bogdanm	0:9b334a45a8ff	1354	}
bogdanm	0:9b334a45a8ff	1355	}
bogdanm	0:9b334a45a8ff	1356
bogdanm	0:9b334a45a8ff	1357	/* Disable interruption if no further conversion upcoming regular */
bogdanm	0:9b334a45a8ff	1358	/* external trigger or by continuous mode */
bogdanm	0:9b334a45a8ff	1359	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
bogdanm	0:9b334a45a8ff	1360	(hadc->Init.ContinuousConvMode == DISABLE) )
bogdanm	0:9b334a45a8ff	1361	{
bogdanm	0:9b334a45a8ff	1362	/* Disable ADC end of single conversion interrupt */
bogdanm	0:9b334a45a8ff	1363	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	1364	}
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	1367	HAL_ADC_ConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1368
bogdanm	0:9b334a45a8ff	1369	/* Clear regular group conversion flag */
bogdanm	0:9b334a45a8ff	1370	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT \| ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	1371	}
bogdanm	0:9b334a45a8ff	1372	}
bogdanm	0:9b334a45a8ff	1373
bogdanm	0:9b334a45a8ff	1374	/* ========== Check End of Conversion flag for injected group ========== */
bogdanm	0:9b334a45a8ff	1375	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
bogdanm	0:9b334a45a8ff	1376	{
bogdanm	0:9b334a45a8ff	1377	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
bogdanm	0:9b334a45a8ff	1378	{
bogdanm	0:9b334a45a8ff	1379	/* Update state machine on conversion status if not in error state */
bogdanm	0:9b334a45a8ff	1380	if(hadc->State != HAL_ADC_STATE_ERROR)
bogdanm	0:9b334a45a8ff	1381	{
bogdanm	0:9b334a45a8ff	1382	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	1383	if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
bogdanm	0:9b334a45a8ff	1384	{
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	if(hadc->State == HAL_ADC_STATE_EOC_REG)
bogdanm	0:9b334a45a8ff	1387	{
bogdanm	0:9b334a45a8ff	1388	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1389	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	1390	}
bogdanm	0:9b334a45a8ff	1391	else
bogdanm	0:9b334a45a8ff	1392	{
bogdanm	0:9b334a45a8ff	1393	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1394	hadc->State = HAL_ADC_STATE_EOC_INJ;
bogdanm	0:9b334a45a8ff	1395	}
bogdanm	0:9b334a45a8ff	1396	}
bogdanm	0:9b334a45a8ff	1397	}
bogdanm	0:9b334a45a8ff	1398
bogdanm	0:9b334a45a8ff	1399	/* Disable interruption if no further conversion upcoming injected */
bogdanm	0:9b334a45a8ff	1400	/* external trigger or by automatic injected conversion with regular */
bogdanm	0:9b334a45a8ff	1401	/* group having no further conversion upcoming (same conditions as */
bogdanm	0:9b334a45a8ff	1402	/* regular group interruption disabling above). */
bogdanm	0:9b334a45a8ff	1403	if(ADC_IS_SOFTWARE_START_INJECTED(hadc) \|\|
bogdanm	0:9b334a45a8ff	1404	(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
bogdanm	0:9b334a45a8ff	1405	(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
bogdanm	0:9b334a45a8ff	1406	(hadc->Init.ContinuousConvMode == DISABLE) ) ) )
bogdanm	0:9b334a45a8ff	1407	{
bogdanm	0:9b334a45a8ff	1408	/* Disable ADC end of single conversion interrupt */
bogdanm	0:9b334a45a8ff	1409	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
bogdanm	0:9b334a45a8ff	1410	}
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	1413	HAL_ADCEx_InjectedConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	/* Clear injected group conversion flag */
bogdanm	0:9b334a45a8ff	1416	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT \| ADC_FLAG_JEOC));
bogdanm	0:9b334a45a8ff	1417	}
bogdanm	0:9b334a45a8ff	1418	}
bogdanm	0:9b334a45a8ff	1419
bogdanm	0:9b334a45a8ff	1420	/* ========== Check Analog watchdog flags ========== */
bogdanm	0:9b334a45a8ff	1421	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
bogdanm	0:9b334a45a8ff	1422	{
bogdanm	0:9b334a45a8ff	1423	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
bogdanm	0:9b334a45a8ff	1424	{
bogdanm	0:9b334a45a8ff	1425	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1426	hadc->State = HAL_ADC_STATE_AWD;
bogdanm	0:9b334a45a8ff	1427
bogdanm	0:9b334a45a8ff	1428	/* Level out of window callback */
bogdanm	0:9b334a45a8ff	1429	HAL_ADC_LevelOutOfWindowCallback(hadc);
bogdanm	0:9b334a45a8ff	1430
bogdanm	0:9b334a45a8ff	1431	/* Clear the ADCx's Analog watchdog flag */
bogdanm	0:9b334a45a8ff	1432	__HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
bogdanm	0:9b334a45a8ff	1433	}
bogdanm	0:9b334a45a8ff	1434	}
bogdanm	0:9b334a45a8ff	1435
bogdanm	0:9b334a45a8ff	1436	}
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	/**
bogdanm	0:9b334a45a8ff	1439	* @brief Conversion complete callback in non blocking mode
bogdanm	0:9b334a45a8ff	1440	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1441	* @retval None
bogdanm	0:9b334a45a8ff	1442	*/
bogdanm	0:9b334a45a8ff	1443	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1444	{
bogdanm	0:9b334a45a8ff	1445	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1446	function HAL_ADC_ConvCpltCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1447	*/
bogdanm	0:9b334a45a8ff	1448	}
bogdanm	0:9b334a45a8ff	1449
bogdanm	0:9b334a45a8ff	1450	/**
bogdanm	0:9b334a45a8ff	1451	* @brief Conversion DMA half-transfer callback in non blocking mode
bogdanm	0:9b334a45a8ff	1452	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1453	* @retval None
bogdanm	0:9b334a45a8ff	1454	*/
bogdanm	0:9b334a45a8ff	1455	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1456	{
bogdanm	0:9b334a45a8ff	1457	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1458	function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1459	*/
bogdanm	0:9b334a45a8ff	1460	}
bogdanm	0:9b334a45a8ff	1461
bogdanm	0:9b334a45a8ff	1462	/**
bogdanm	0:9b334a45a8ff	1463	* @brief Analog watchdog callback in non blocking mode.
bogdanm	0:9b334a45a8ff	1464	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1465	* @retval None
bogdanm	0:9b334a45a8ff	1466	*/
bogdanm	0:9b334a45a8ff	1467	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1468	{
bogdanm	0:9b334a45a8ff	1469	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1470	function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1471	*/
bogdanm	0:9b334a45a8ff	1472	}
bogdanm	0:9b334a45a8ff	1473
bogdanm	0:9b334a45a8ff	1474	/**
bogdanm	0:9b334a45a8ff	1475	* @brief ADC error callback in non blocking mode
bogdanm	0:9b334a45a8ff	1476	* (ADC conversion with interruption or transfer by DMA)
bogdanm	0:9b334a45a8ff	1477	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1478	* @retval None
bogdanm	0:9b334a45a8ff	1479	*/
bogdanm	0:9b334a45a8ff	1480	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
bogdanm	0:9b334a45a8ff	1481	{
bogdanm	0:9b334a45a8ff	1482	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1483	function HAL_ADC_ErrorCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1484	*/
bogdanm	0:9b334a45a8ff	1485	}
bogdanm	0:9b334a45a8ff	1486
bogdanm	0:9b334a45a8ff	1487
bogdanm	0:9b334a45a8ff	1488	/**
bogdanm	0:9b334a45a8ff	1489	* @}
bogdanm	0:9b334a45a8ff	1490	*/
bogdanm	0:9b334a45a8ff	1491
bogdanm	0:9b334a45a8ff	1492	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1493	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	1494	*
bogdanm	0:9b334a45a8ff	1495	@verbatim
bogdanm	0:9b334a45a8ff	1496	===============================================================================
bogdanm	0:9b334a45a8ff	1497	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	1498	===============================================================================
bogdanm	0:9b334a45a8ff	1499	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1500	(+) Configure channels on regular group
bogdanm	0:9b334a45a8ff	1501	(+) Configure the analog watchdog
bogdanm	0:9b334a45a8ff	1502
bogdanm	0:9b334a45a8ff	1503	@endverbatim
bogdanm	0:9b334a45a8ff	1504	* @{
bogdanm	0:9b334a45a8ff	1505	*/
bogdanm	0:9b334a45a8ff	1506
bogdanm	0:9b334a45a8ff	1507	/**
bogdanm	0:9b334a45a8ff	1508	* @brief Configures the the selected channel to be linked to the regular
bogdanm	0:9b334a45a8ff	1509	* group.
bogdanm	0:9b334a45a8ff	1510	* @note In case of usage of internal measurement channels:
bogdanm	0:9b334a45a8ff	1511	* Vbat/VrefInt/TempSensor.
bogdanm	0:9b334a45a8ff	1512	* These internal paths can be be disabled using function
bogdanm	0:9b334a45a8ff	1513	* HAL_ADC_DeInit().
bogdanm	0:9b334a45a8ff	1514	* @note Possibility to update parameters on the fly:
bogdanm	0:9b334a45a8ff	1515	* This function initializes channel into regular group, following
bogdanm	0:9b334a45a8ff	1516	* calls to this function can be used to reconfigure some parameters
bogdanm	0:9b334a45a8ff	1517	* of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
bogdanm	0:9b334a45a8ff	1518	* the ADC.
bogdanm	0:9b334a45a8ff	1519	* The setting of these parameters is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	1520	* For parameters constraints, see comments of structure
bogdanm	0:9b334a45a8ff	1521	* "ADC_ChannelConfTypeDef".
bogdanm	0:9b334a45a8ff	1522	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1523	* @param sConfig: Structure of ADC channel for regular group.
bogdanm	0:9b334a45a8ff	1524	* @retval HAL status
bogdanm	0:9b334a45a8ff	1525	*/
bogdanm	0:9b334a45a8ff	1526	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
bogdanm	0:9b334a45a8ff	1527	{
bogdanm	0:9b334a45a8ff	1528	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1529	__IO uint32_t wait_loop_index = 0;
bogdanm	0:9b334a45a8ff	1530
bogdanm	0:9b334a45a8ff	1531	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1532	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1533	assert_param(IS_ADC_CHANNEL(sConfig->Channel));
bogdanm	0:9b334a45a8ff	1534	assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
bogdanm	0:9b334a45a8ff	1535	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
bogdanm	0:9b334a45a8ff	1536
bogdanm	0:9b334a45a8ff	1537	/* Process locked */
bogdanm	0:9b334a45a8ff	1538	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1539
bogdanm	0:9b334a45a8ff	1540
bogdanm	0:9b334a45a8ff	1541	/* Regular sequence configuration */
bogdanm	0:9b334a45a8ff	1542	/* For Rank 1 to 6 */
bogdanm	0:9b334a45a8ff	1543	if (sConfig->Rank < 7)
bogdanm	0:9b334a45a8ff	1544	{
bogdanm	0:9b334a45a8ff	1545	MODIFY_REG(hadc->Instance->SQR3 ,
bogdanm	0:9b334a45a8ff	1546	ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
bogdanm	0:9b334a45a8ff	1547	ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
bogdanm	0:9b334a45a8ff	1548	}
bogdanm	0:9b334a45a8ff	1549	/* For Rank 7 to 12 */
bogdanm	0:9b334a45a8ff	1550	else if (sConfig->Rank < 13)
bogdanm	0:9b334a45a8ff	1551	{
bogdanm	0:9b334a45a8ff	1552	MODIFY_REG(hadc->Instance->SQR2 ,
bogdanm	0:9b334a45a8ff	1553	ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
bogdanm	0:9b334a45a8ff	1554	ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
bogdanm	0:9b334a45a8ff	1555	}
bogdanm	0:9b334a45a8ff	1556	/* For Rank 13 to 16 */
bogdanm	0:9b334a45a8ff	1557	else
bogdanm	0:9b334a45a8ff	1558	{
bogdanm	0:9b334a45a8ff	1559	MODIFY_REG(hadc->Instance->SQR1 ,
bogdanm	0:9b334a45a8ff	1560	ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
bogdanm	0:9b334a45a8ff	1561	ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
bogdanm	0:9b334a45a8ff	1562	}
bogdanm	0:9b334a45a8ff	1563
bogdanm	0:9b334a45a8ff	1564
bogdanm	0:9b334a45a8ff	1565	/* Channel sampling time configuration */
bogdanm	0:9b334a45a8ff	1566	/* For channels 10 to 17 */
bogdanm	0:9b334a45a8ff	1567	if (sConfig->Channel >= ADC_CHANNEL_10)
bogdanm	0:9b334a45a8ff	1568	{
bogdanm	0:9b334a45a8ff	1569	MODIFY_REG(hadc->Instance->SMPR1 ,
bogdanm	0:9b334a45a8ff	1570	ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
bogdanm	0:9b334a45a8ff	1571	ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
bogdanm	0:9b334a45a8ff	1572	}
bogdanm	0:9b334a45a8ff	1573	else /* For channels 0 to 9 */
bogdanm	0:9b334a45a8ff	1574	{
bogdanm	0:9b334a45a8ff	1575	MODIFY_REG(hadc->Instance->SMPR2 ,
bogdanm	0:9b334a45a8ff	1576	ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
bogdanm	0:9b334a45a8ff	1577	ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
bogdanm	0:9b334a45a8ff	1578	}
bogdanm	0:9b334a45a8ff	1579
bogdanm	0:9b334a45a8ff	1580	/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
bogdanm	0:9b334a45a8ff	1581	/* and VREFINT measurement path. */
bogdanm	0:9b334a45a8ff	1582	if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) \|\|
bogdanm	0:9b334a45a8ff	1583	(sConfig->Channel == ADC_CHANNEL_VREFINT) )
bogdanm	0:9b334a45a8ff	1584	{
bogdanm	0:9b334a45a8ff	1585	/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
bogdanm	0:9b334a45a8ff	1586	/* measurement channels (VrefInt/TempSensor). If these channels are */
bogdanm	0:9b334a45a8ff	1587	/* intended to be set on other ADC instances, an error is reported. */
bogdanm	0:9b334a45a8ff	1588	if (hadc->Instance == ADC1)
bogdanm	0:9b334a45a8ff	1589	{
bogdanm	0:9b334a45a8ff	1590	if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
bogdanm	0:9b334a45a8ff	1591	{
bogdanm	0:9b334a45a8ff	1592	SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
bogdanm	0:9b334a45a8ff	1593
bogdanm	0:9b334a45a8ff	1594	if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
bogdanm	0:9b334a45a8ff	1595	{
bogdanm	0:9b334a45a8ff	1596	/* Delay for temperature sensor stabilization time */
bogdanm	0:9b334a45a8ff	1597	/* Compute number of CPU cycles to wait for */
bogdanm	0:9b334a45a8ff	1598	wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
bogdanm	0:9b334a45a8ff	1599	while(wait_loop_index != 0)
bogdanm	0:9b334a45a8ff	1600	{
bogdanm	0:9b334a45a8ff	1601	wait_loop_index--;
bogdanm	0:9b334a45a8ff	1602	}
bogdanm	0:9b334a45a8ff	1603	}
bogdanm	0:9b334a45a8ff	1604	}
bogdanm	0:9b334a45a8ff	1605	}
bogdanm	0:9b334a45a8ff	1606	else
bogdanm	0:9b334a45a8ff	1607	{
bogdanm	0:9b334a45a8ff	1608	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1609	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1610
bogdanm	0:9b334a45a8ff	1611	tmp_hal_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1612	}
bogdanm	0:9b334a45a8ff	1613	}
bogdanm	0:9b334a45a8ff	1614
bogdanm	0:9b334a45a8ff	1615	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1616	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1617
bogdanm	0:9b334a45a8ff	1618	/* Return function status */
bogdanm	0:9b334a45a8ff	1619	return tmp_hal_status;
bogdanm	0:9b334a45a8ff	1620	}
bogdanm	0:9b334a45a8ff	1621
bogdanm	0:9b334a45a8ff	1622	/**
bogdanm	0:9b334a45a8ff	1623	* @brief Configures the analog watchdog.
bogdanm	0:9b334a45a8ff	1624	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1625	* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
bogdanm	0:9b334a45a8ff	1626	* @retval HAL status
bogdanm	0:9b334a45a8ff	1627	*/
bogdanm	0:9b334a45a8ff	1628	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
bogdanm	0:9b334a45a8ff	1629	{
bogdanm	0:9b334a45a8ff	1630	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1631	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1632	assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
bogdanm	0:9b334a45a8ff	1633	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
bogdanm	0:9b334a45a8ff	1634	assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
bogdanm	0:9b334a45a8ff	1635	assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
bogdanm	0:9b334a45a8ff	1636
bogdanm	0:9b334a45a8ff	1637	if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\|
bogdanm	0:9b334a45a8ff	1638	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\|
bogdanm	0:9b334a45a8ff	1639	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
bogdanm	0:9b334a45a8ff	1640	{
bogdanm	0:9b334a45a8ff	1641	assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
bogdanm	0:9b334a45a8ff	1642	}
bogdanm	0:9b334a45a8ff	1643
bogdanm	0:9b334a45a8ff	1644	/* Process locked */
bogdanm	0:9b334a45a8ff	1645	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1646
bogdanm	0:9b334a45a8ff	1647	/* Analog watchdog configuration */
bogdanm	0:9b334a45a8ff	1648
bogdanm	0:9b334a45a8ff	1649	/* Configure ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	1650	if(AnalogWDGConfig->ITMode == ENABLE)
bogdanm	0:9b334a45a8ff	1651	{
bogdanm	0:9b334a45a8ff	1652	/* Enable the ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	1653	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
bogdanm	0:9b334a45a8ff	1654	}
bogdanm	0:9b334a45a8ff	1655	else
bogdanm	0:9b334a45a8ff	1656	{
bogdanm	0:9b334a45a8ff	1657	/* Disable the ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	1658	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
bogdanm	0:9b334a45a8ff	1659	}
bogdanm	0:9b334a45a8ff	1660
bogdanm	0:9b334a45a8ff	1661	/* Configuration of analog watchdog: */
bogdanm	0:9b334a45a8ff	1662	/* - Set the analog watchdog enable mode: regular and/or injected groups, */
bogdanm	0:9b334a45a8ff	1663	/* one or all channels. */
bogdanm	0:9b334a45a8ff	1664	/* - Set the Analog watchdog channel (is not used if watchdog */
bogdanm	0:9b334a45a8ff	1665	/* mode "all channels": ADC_CFGR_AWD1SGL=0). */
bogdanm	0:9b334a45a8ff	1666	MODIFY_REG(hadc->Instance->CR1 ,
bogdanm	0:9b334a45a8ff	1667	ADC_CR1_AWDSGL \|
bogdanm	0:9b334a45a8ff	1668	ADC_CR1_JAWDEN \|
bogdanm	0:9b334a45a8ff	1669	ADC_CR1_AWDEN \|
bogdanm	0:9b334a45a8ff	1670	ADC_CR1_AWDCH ,
bogdanm	0:9b334a45a8ff	1671	AnalogWDGConfig->WatchdogMode \|
bogdanm	0:9b334a45a8ff	1672	AnalogWDGConfig->Channel );
bogdanm	0:9b334a45a8ff	1673
bogdanm	0:9b334a45a8ff	1674	/* Set the high threshold */
bogdanm	0:9b334a45a8ff	1675	WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
bogdanm	0:9b334a45a8ff	1676
bogdanm	0:9b334a45a8ff	1677	/* Set the low threshold */
bogdanm	0:9b334a45a8ff	1678	WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
bogdanm	0:9b334a45a8ff	1679
bogdanm	0:9b334a45a8ff	1680	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1681	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1682
bogdanm	0:9b334a45a8ff	1683	/* Return function status */
bogdanm	0:9b334a45a8ff	1684	return HAL_OK;
bogdanm	0:9b334a45a8ff	1685	}
bogdanm	0:9b334a45a8ff	1686
bogdanm	0:9b334a45a8ff	1687
bogdanm	0:9b334a45a8ff	1688	/**
bogdanm	0:9b334a45a8ff	1689	* @}
bogdanm	0:9b334a45a8ff	1690	*/
bogdanm	0:9b334a45a8ff	1691
bogdanm	0:9b334a45a8ff	1692
bogdanm	0:9b334a45a8ff	1693	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
bogdanm	0:9b334a45a8ff	1694	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	1695	*
bogdanm	0:9b334a45a8ff	1696	@verbatim
bogdanm	0:9b334a45a8ff	1697	===============================================================================
bogdanm	0:9b334a45a8ff	1698	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1699	===============================================================================
bogdanm	0:9b334a45a8ff	1700	[..]
bogdanm	0:9b334a45a8ff	1701	This subsection provides functions to get in run-time the status of the
bogdanm	0:9b334a45a8ff	1702	peripheral.
bogdanm	0:9b334a45a8ff	1703	(+) Check the ADC state
bogdanm	0:9b334a45a8ff	1704	(+) Check the ADC error code
bogdanm	0:9b334a45a8ff	1705
bogdanm	0:9b334a45a8ff	1706	@endverbatim
bogdanm	0:9b334a45a8ff	1707	* @{
bogdanm	0:9b334a45a8ff	1708	*/
bogdanm	0:9b334a45a8ff	1709
bogdanm	0:9b334a45a8ff	1710	/**
bogdanm	0:9b334a45a8ff	1711	* @brief return the ADC state
bogdanm	0:9b334a45a8ff	1712	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1713	* @retval HAL state
bogdanm	0:9b334a45a8ff	1714	*/
bogdanm	0:9b334a45a8ff	1715	HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1716	{
bogdanm	0:9b334a45a8ff	1717	/* Return ADC state */
bogdanm	0:9b334a45a8ff	1718	return hadc->State;
bogdanm	0:9b334a45a8ff	1719	}
bogdanm	0:9b334a45a8ff	1720
bogdanm	0:9b334a45a8ff	1721	/**
bogdanm	0:9b334a45a8ff	1722	* @brief Return the ADC error code
bogdanm	0:9b334a45a8ff	1723	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1724	* @retval ADC Error Code
bogdanm	0:9b334a45a8ff	1725	*/
bogdanm	0:9b334a45a8ff	1726	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
bogdanm	0:9b334a45a8ff	1727	{
bogdanm	0:9b334a45a8ff	1728	return hadc->ErrorCode;
bogdanm	0:9b334a45a8ff	1729	}
bogdanm	0:9b334a45a8ff	1730
bogdanm	0:9b334a45a8ff	1731	/**
bogdanm	0:9b334a45a8ff	1732	* @}
bogdanm	0:9b334a45a8ff	1733	*/
bogdanm	0:9b334a45a8ff	1734
bogdanm	0:9b334a45a8ff	1735	/**
bogdanm	0:9b334a45a8ff	1736	* @}
bogdanm	0:9b334a45a8ff	1737	*/
bogdanm	0:9b334a45a8ff	1738
bogdanm	0:9b334a45a8ff	1739	/** @defgroup ADC_Private_Functions ADC Private Functions
bogdanm	0:9b334a45a8ff	1740	* @{
bogdanm	0:9b334a45a8ff	1741	*/
bogdanm	0:9b334a45a8ff	1742
bogdanm	0:9b334a45a8ff	1743	/**
bogdanm	0:9b334a45a8ff	1744	* @brief Enable the selected ADC.
bogdanm	0:9b334a45a8ff	1745	* @note Prerequisite condition to use this function: ADC must be disabled
bogdanm	0:9b334a45a8ff	1746	* and voltage regulator must be enabled (done into HAL_ADC_Init()).
bogdanm	0:9b334a45a8ff	1747	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1748	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1749	*/
bogdanm	0:9b334a45a8ff	1750	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1751	{
bogdanm	0:9b334a45a8ff	1752	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1753	__IO uint32_t wait_loop_index = 0;
bogdanm	0:9b334a45a8ff	1754
bogdanm	0:9b334a45a8ff	1755	/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
bogdanm	0:9b334a45a8ff	1756	/* enabling phase not yet completed: flag ADC ready not yet set). */
bogdanm	0:9b334a45a8ff	1757	/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
bogdanm	0:9b334a45a8ff	1758	/* causes: ADC clock not running, ...). */
bogdanm	0:9b334a45a8ff	1759	if (ADC_IS_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1760	{
bogdanm	0:9b334a45a8ff	1761	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1762	__HAL_ADC_ENABLE(hadc);
bogdanm	0:9b334a45a8ff	1763
bogdanm	0:9b334a45a8ff	1764	/* Delay for ADC stabilization time */
bogdanm	0:9b334a45a8ff	1765	/* Compute number of CPU cycles to wait for */
bogdanm	0:9b334a45a8ff	1766	wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
bogdanm	0:9b334a45a8ff	1767	while(wait_loop_index != 0)
bogdanm	0:9b334a45a8ff	1768	{
bogdanm	0:9b334a45a8ff	1769	wait_loop_index--;
bogdanm	0:9b334a45a8ff	1770	}
bogdanm	0:9b334a45a8ff	1771
bogdanm	0:9b334a45a8ff	1772	/* Get timeout */
bogdanm	0:9b334a45a8ff	1773	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1774
bogdanm	0:9b334a45a8ff	1775	/* Wait for ADC effectively enabled */
bogdanm	0:9b334a45a8ff	1776	while(ADC_IS_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1777	{
bogdanm	0:9b334a45a8ff	1778	if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
bogdanm	0:9b334a45a8ff	1779	{
bogdanm	0:9b334a45a8ff	1780	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1781	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1782
bogdanm	0:9b334a45a8ff	1783	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	1784	hadc->ErrorCode \|= HAL_ADC_ERROR_INTERNAL;
bogdanm	0:9b334a45a8ff	1785
bogdanm	0:9b334a45a8ff	1786	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1787	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1788
bogdanm	0:9b334a45a8ff	1789	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1790	}
bogdanm	0:9b334a45a8ff	1791	}
bogdanm	0:9b334a45a8ff	1792	}
bogdanm	0:9b334a45a8ff	1793
bogdanm	0:9b334a45a8ff	1794	/* Return HAL status */
bogdanm	0:9b334a45a8ff	1795	return HAL_OK;
bogdanm	0:9b334a45a8ff	1796	}
bogdanm	0:9b334a45a8ff	1797
bogdanm	0:9b334a45a8ff	1798	/**
bogdanm	0:9b334a45a8ff	1799	* @brief Stop ADC conversion and disable the selected ADC
bogdanm	0:9b334a45a8ff	1800	* @note Prerequisite condition to use this function: ADC conversions must be
bogdanm	0:9b334a45a8ff	1801	* stopped to disable the ADC.
bogdanm	0:9b334a45a8ff	1802	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1803	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1804	*/
bogdanm	0:9b334a45a8ff	1805	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1806	{
bogdanm	0:9b334a45a8ff	1807	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1808
bogdanm	0:9b334a45a8ff	1809	/* Verification if ADC is not already disabled */
bogdanm	0:9b334a45a8ff	1810	if (ADC_IS_ENABLE(hadc) != RESET)
bogdanm	0:9b334a45a8ff	1811	{
bogdanm	0:9b334a45a8ff	1812	/* Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1813	__HAL_ADC_DISABLE(hadc);
bogdanm	0:9b334a45a8ff	1814
bogdanm	0:9b334a45a8ff	1815	/* Get timeout */
bogdanm	0:9b334a45a8ff	1816	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1817
bogdanm	0:9b334a45a8ff	1818	/* Wait for ADC effectively disabled */
bogdanm	0:9b334a45a8ff	1819	while(ADC_IS_ENABLE(hadc) != RESET)
bogdanm	0:9b334a45a8ff	1820	{
bogdanm	0:9b334a45a8ff	1821	if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
bogdanm	0:9b334a45a8ff	1822	{
bogdanm	0:9b334a45a8ff	1823	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1824	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1825
bogdanm	0:9b334a45a8ff	1826	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	1827	hadc->ErrorCode \|= HAL_ADC_ERROR_INTERNAL;
bogdanm	0:9b334a45a8ff	1828
bogdanm	0:9b334a45a8ff	1829	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1830	}
bogdanm	0:9b334a45a8ff	1831	}
bogdanm	0:9b334a45a8ff	1832	}
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	/* Return HAL status */
bogdanm	0:9b334a45a8ff	1835	return HAL_OK;
bogdanm	0:9b334a45a8ff	1836	}
bogdanm	0:9b334a45a8ff	1837
bogdanm	0:9b334a45a8ff	1838	/**
bogdanm	0:9b334a45a8ff	1839	* @brief DMA transfer complete callback.
bogdanm	0:9b334a45a8ff	1840	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	1841	* @retval None
bogdanm	0:9b334a45a8ff	1842	*/
bogdanm	0:9b334a45a8ff	1843	void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1844	{
bogdanm	0:9b334a45a8ff	1845	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	1846	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1847
bogdanm	0:9b334a45a8ff	1848	/* Update state machine on conversion status if not in error state */
bogdanm	0:9b334a45a8ff	1849	if(hadc->State != HAL_ADC_STATE_ERROR)
bogdanm	0:9b334a45a8ff	1850	{
bogdanm	0:9b334a45a8ff	1851	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	1852	if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
bogdanm	0:9b334a45a8ff	1853	{
bogdanm	0:9b334a45a8ff	1854	/* Check if a conversion is ready on injected group */
bogdanm	0:9b334a45a8ff	1855	if(hadc->State == HAL_ADC_STATE_EOC_INJ)
bogdanm	0:9b334a45a8ff	1856	{
bogdanm	0:9b334a45a8ff	1857	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1858	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	1859	}
bogdanm	0:9b334a45a8ff	1860	else
bogdanm	0:9b334a45a8ff	1861	{
bogdanm	0:9b334a45a8ff	1862	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1863	hadc->State = HAL_ADC_STATE_EOC_REG;
bogdanm	0:9b334a45a8ff	1864	}
bogdanm	0:9b334a45a8ff	1865	}
bogdanm	0:9b334a45a8ff	1866
bogdanm	0:9b334a45a8ff	1867	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	1868	HAL_ADC_ConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1869	}
bogdanm	0:9b334a45a8ff	1870	else
bogdanm	0:9b334a45a8ff	1871	{
bogdanm	0:9b334a45a8ff	1872	/* Call DMA error callback */
bogdanm	0:9b334a45a8ff	1873	hadc->DMA_Handle->XferErrorCallback(hdma);
bogdanm	0:9b334a45a8ff	1874	}
bogdanm	0:9b334a45a8ff	1875	}
bogdanm	0:9b334a45a8ff	1876
bogdanm	0:9b334a45a8ff	1877	/**
bogdanm	0:9b334a45a8ff	1878	* @brief DMA half transfer complete callback.
bogdanm	0:9b334a45a8ff	1879	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	1880	* @retval None
bogdanm	0:9b334a45a8ff	1881	*/
bogdanm	0:9b334a45a8ff	1882	void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1883	{
bogdanm	0:9b334a45a8ff	1884	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	1885	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1886
bogdanm	0:9b334a45a8ff	1887	/* Half conversion callback */
bogdanm	0:9b334a45a8ff	1888	HAL_ADC_ConvHalfCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1889	}
bogdanm	0:9b334a45a8ff	1890
bogdanm	0:9b334a45a8ff	1891	/**
bogdanm	0:9b334a45a8ff	1892	* @brief DMA error callback
bogdanm	0:9b334a45a8ff	1893	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	1894	* @retval None
bogdanm	0:9b334a45a8ff	1895	*/
bogdanm	0:9b334a45a8ff	1896	void ADC_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1897	{
bogdanm	0:9b334a45a8ff	1898	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	1899	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1900
bogdanm	0:9b334a45a8ff	1901	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1902	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1903
bogdanm	0:9b334a45a8ff	1904	/* Set ADC error code to DMA error */
bogdanm	0:9b334a45a8ff	1905	hadc->ErrorCode \|= HAL_ADC_ERROR_DMA;
bogdanm	0:9b334a45a8ff	1906
bogdanm	0:9b334a45a8ff	1907	/* Error callback */
bogdanm	0:9b334a45a8ff	1908	HAL_ADC_ErrorCallback(hadc);
bogdanm	0:9b334a45a8ff	1909	}
bogdanm	0:9b334a45a8ff	1910
bogdanm	0:9b334a45a8ff	1911	/**
bogdanm	0:9b334a45a8ff	1912	* @}
bogdanm	0:9b334a45a8ff	1913	*/
bogdanm	0:9b334a45a8ff	1914
bogdanm	0:9b334a45a8ff	1915	#endif /* HAL_ADC_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1916	/**
bogdanm	0:9b334a45a8ff	1917	* @}
bogdanm	0:9b334a45a8ff	1918	*/
bogdanm	0:9b334a45a8ff	1919
bogdanm	0:9b334a45a8ff	1920	/**
bogdanm	0:9b334a45a8ff	1921	* @}
bogdanm	0:9b334a45a8ff	1922	*/
bogdanm	0:9b334a45a8ff	1923
bogdanm	0:9b334a45a8ff	1924	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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