mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32_hal_legacy.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 124:6a4a5b7d7324

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32_hal_legacy.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	124:6a4a5b7d7324	5	* @version V1.0.4
mbed_official	124:6a4a5b7d7324	6	* @date 29-April-2016
bogdanm	0:9b334a45a8ff	7	* @brief This file contains aliases definition for the STM32Cube HAL constants
bogdanm	0:9b334a45a8ff	8	* macros and functions maintained for legacy purpose.
bogdanm	0:9b334a45a8ff	9	******************************************************************************
bogdanm	0:9b334a45a8ff	10	* @attention
bogdanm	0:9b334a45a8ff	11	*
mbed_official	124:6a4a5b7d7324	12	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	13	*
bogdanm	0:9b334a45a8ff	14	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	15	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	16	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	17	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	19	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	20	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	22	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	23	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	24	*
bogdanm	0:9b334a45a8ff	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	124:6a4a5b7d7324	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	35	*
bogdanm	0:9b334a45a8ff	36	******************************************************************************
bogdanm	0:9b334a45a8ff	37	*/
bogdanm	0:9b334a45a8ff	38
bogdanm	0:9b334a45a8ff	39	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	40	#ifndef __STM32_HAL_LEGACY
bogdanm	0:9b334a45a8ff	41	#define __STM32_HAL_LEGACY
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	44	extern "C" {
bogdanm	0:9b334a45a8ff	45	#endif
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	48	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	49	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	50
bogdanm	0:9b334a45a8ff	51	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	52	* @{
bogdanm	0:9b334a45a8ff	53	*/
mbed_official	124:6a4a5b7d7324	54	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
mbed_official	124:6a4a5b7d7324	55	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
bogdanm	0:9b334a45a8ff	56	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
bogdanm	0:9b334a45a8ff	57	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
bogdanm	0:9b334a45a8ff	58	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	/**
bogdanm	0:9b334a45a8ff	61	* @}
bogdanm	0:9b334a45a8ff	62	*/
bogdanm	0:9b334a45a8ff	63
bogdanm	0:9b334a45a8ff	64	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	65	* @{
bogdanm	0:9b334a45a8ff	66	*/
bogdanm	0:9b334a45a8ff	67	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
bogdanm	0:9b334a45a8ff	68	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
bogdanm	0:9b334a45a8ff	69	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
bogdanm	0:9b334a45a8ff	70	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
bogdanm	0:9b334a45a8ff	71	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
bogdanm	0:9b334a45a8ff	72	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
bogdanm	0:9b334a45a8ff	73	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
bogdanm	0:9b334a45a8ff	74	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
bogdanm	0:9b334a45a8ff	75	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
bogdanm	0:9b334a45a8ff	76	#define REGULAR_GROUP ADC_REGULAR_GROUP
bogdanm	0:9b334a45a8ff	77	#define INJECTED_GROUP ADC_INJECTED_GROUP
bogdanm	0:9b334a45a8ff	78	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
bogdanm	0:9b334a45a8ff	79	#define AWD_EVENT ADC_AWD_EVENT
bogdanm	0:9b334a45a8ff	80	#define AWD1_EVENT ADC_AWD1_EVENT
bogdanm	0:9b334a45a8ff	81	#define AWD2_EVENT ADC_AWD2_EVENT
bogdanm	0:9b334a45a8ff	82	#define AWD3_EVENT ADC_AWD3_EVENT
bogdanm	0:9b334a45a8ff	83	#define OVR_EVENT ADC_OVR_EVENT
bogdanm	0:9b334a45a8ff	84	#define JQOVF_EVENT ADC_JQOVF_EVENT
bogdanm	0:9b334a45a8ff	85	#define ALL_CHANNELS ADC_ALL_CHANNELS
bogdanm	0:9b334a45a8ff	86	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
bogdanm	0:9b334a45a8ff	87	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
bogdanm	0:9b334a45a8ff	88	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
bogdanm	0:9b334a45a8ff	89	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
bogdanm	0:9b334a45a8ff	90	#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
bogdanm	0:9b334a45a8ff	91	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
bogdanm	0:9b334a45a8ff	92	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
mbed_official	124:6a4a5b7d7324	93	#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
mbed_official	124:6a4a5b7d7324	94	#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
bogdanm	0:9b334a45a8ff	95	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
bogdanm	0:9b334a45a8ff	96	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
bogdanm	0:9b334a45a8ff	97	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
bogdanm	0:9b334a45a8ff	98	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
bogdanm	0:9b334a45a8ff	99	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
bogdanm	0:9b334a45a8ff	100	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
bogdanm	0:9b334a45a8ff	101	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
mbed_official	124:6a4a5b7d7324	102	#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
mbed_official	124:6a4a5b7d7324	103	#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
mbed_official	124:6a4a5b7d7324	104	#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
mbed_official	124:6a4a5b7d7324	105	#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
mbed_official	124:6a4a5b7d7324	106	#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
bogdanm	0:9b334a45a8ff	107
mbed_official	124:6a4a5b7d7324	108	#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
mbed_official	124:6a4a5b7d7324	109	#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
mbed_official	124:6a4a5b7d7324	110	#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
mbed_official	124:6a4a5b7d7324	111	#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
mbed_official	124:6a4a5b7d7324	112	#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
mbed_official	124:6a4a5b7d7324	113	#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
mbed_official	124:6a4a5b7d7324	114	#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
bogdanm	0:9b334a45a8ff	115	/**
bogdanm	0:9b334a45a8ff	116	* @}
bogdanm	0:9b334a45a8ff	117	*/
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	120	* @{
bogdanm	0:9b334a45a8ff	121	*/
bogdanm	0:9b334a45a8ff	122
bogdanm	0:9b334a45a8ff	123	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125	/**
bogdanm	0:9b334a45a8ff	126	* @}
bogdanm	0:9b334a45a8ff	127	*/
bogdanm	0:9b334a45a8ff	128
bogdanm	0:9b334a45a8ff	129	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	130	* @{
bogdanm	0:9b334a45a8ff	131	*/
mbed_official	124:6a4a5b7d7324	132	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
mbed_official	124:6a4a5b7d7324	133	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
mbed_official	124:6a4a5b7d7324	134	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
mbed_official	124:6a4a5b7d7324	135	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
mbed_official	124:6a4a5b7d7324	136	#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
mbed_official	124:6a4a5b7d7324	137	#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
mbed_official	124:6a4a5b7d7324	138	#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
mbed_official	124:6a4a5b7d7324	139	#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
mbed_official	124:6a4a5b7d7324	140	#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
mbed_official	124:6a4a5b7d7324	141	#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
mbed_official	124:6a4a5b7d7324	142	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	124:6a4a5b7d7324	143	#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
mbed_official	124:6a4a5b7d7324	144	#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
mbed_official	124:6a4a5b7d7324	145	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	124:6a4a5b7d7324	146
mbed_official	124:6a4a5b7d7324	147	#if defined(STM32L0) \|\| defined(STM32L4)
mbed_official	124:6a4a5b7d7324	148	#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
mbed_official	124:6a4a5b7d7324	149
mbed_official	124:6a4a5b7d7324	150	#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
mbed_official	124:6a4a5b7d7324	151	#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
mbed_official	124:6a4a5b7d7324	152	#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
mbed_official	124:6a4a5b7d7324	153
mbed_official	124:6a4a5b7d7324	154	#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
mbed_official	124:6a4a5b7d7324	155	#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
mbed_official	124:6a4a5b7d7324	156	#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
mbed_official	124:6a4a5b7d7324	157	#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
mbed_official	124:6a4a5b7d7324	158	#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
mbed_official	124:6a4a5b7d7324	159	#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
mbed_official	124:6a4a5b7d7324	160	#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
mbed_official	124:6a4a5b7d7324	161	#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
mbed_official	124:6a4a5b7d7324	162	#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
mbed_official	124:6a4a5b7d7324	163	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
mbed_official	124:6a4a5b7d7324	164	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
mbed_official	124:6a4a5b7d7324	165	#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
mbed_official	124:6a4a5b7d7324	166	#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
mbed_official	124:6a4a5b7d7324	167
mbed_official	124:6a4a5b7d7324	168	#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
mbed_official	124:6a4a5b7d7324	169	#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
bogdanm	0:9b334a45a8ff	170
mbed_official	124:6a4a5b7d7324	171	/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
mbed_official	124:6a4a5b7d7324	172	/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
mbed_official	124:6a4a5b7d7324	173	#if defined(COMP_CSR_LOCK)
mbed_official	124:6a4a5b7d7324	174	#define COMP_FLAG_LOCK COMP_CSR_LOCK
mbed_official	124:6a4a5b7d7324	175	#elif defined(COMP_CSR_COMP1LOCK)
mbed_official	124:6a4a5b7d7324	176	#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
mbed_official	124:6a4a5b7d7324	177	#elif defined(COMP_CSR_COMPxLOCK)
mbed_official	124:6a4a5b7d7324	178	#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
mbed_official	124:6a4a5b7d7324	179	#endif
mbed_official	124:6a4a5b7d7324	180
mbed_official	124:6a4a5b7d7324	181	#if defined(STM32L4)
mbed_official	124:6a4a5b7d7324	182	#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
mbed_official	124:6a4a5b7d7324	183	#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
mbed_official	124:6a4a5b7d7324	184	#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
mbed_official	124:6a4a5b7d7324	185	#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
mbed_official	124:6a4a5b7d7324	186	#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
mbed_official	124:6a4a5b7d7324	187	#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
mbed_official	124:6a4a5b7d7324	188	#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
mbed_official	124:6a4a5b7d7324	189	#endif
mbed_official	124:6a4a5b7d7324	190
mbed_official	124:6a4a5b7d7324	191	#if defined(STM32L0)
mbed_official	124:6a4a5b7d7324	192	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
mbed_official	124:6a4a5b7d7324	193	#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
mbed_official	124:6a4a5b7d7324	194	#else
mbed_official	124:6a4a5b7d7324	195	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
mbed_official	124:6a4a5b7d7324	196	#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
mbed_official	124:6a4a5b7d7324	197	#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
mbed_official	124:6a4a5b7d7324	198	#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
mbed_official	124:6a4a5b7d7324	199	#endif
mbed_official	124:6a4a5b7d7324	200
mbed_official	124:6a4a5b7d7324	201	#endif
mbed_official	124:6a4a5b7d7324	202	/**
mbed_official	124:6a4a5b7d7324	203	* @}
mbed_official	124:6a4a5b7d7324	204	*/
mbed_official	124:6a4a5b7d7324	205
mbed_official	124:6a4a5b7d7324	206	/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
mbed_official	124:6a4a5b7d7324	207	* @{
mbed_official	124:6a4a5b7d7324	208	*/
mbed_official	124:6a4a5b7d7324	209	#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
bogdanm	0:9b334a45a8ff	210	/**
bogdanm	0:9b334a45a8ff	211	* @}
bogdanm	0:9b334a45a8ff	212	*/
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	215	* @{
bogdanm	0:9b334a45a8ff	216	*/
bogdanm	0:9b334a45a8ff	217
bogdanm	0:9b334a45a8ff	218	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
bogdanm	0:9b334a45a8ff	219	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
bogdanm	0:9b334a45a8ff	220
bogdanm	0:9b334a45a8ff	221	/**
bogdanm	0:9b334a45a8ff	222	* @}
bogdanm	0:9b334a45a8ff	223	*/
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	226	* @{
bogdanm	0:9b334a45a8ff	227	*/
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
bogdanm	0:9b334a45a8ff	230	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
bogdanm	0:9b334a45a8ff	231	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
mbed_official	124:6a4a5b7d7324	232	#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
mbed_official	124:6a4a5b7d7324	233	#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
mbed_official	124:6a4a5b7d7324	234	#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
mbed_official	124:6a4a5b7d7324	235	#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
mbed_official	124:6a4a5b7d7324	236	#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
mbed_official	124:6a4a5b7d7324	237	#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	/**
bogdanm	0:9b334a45a8ff	240	* @}
bogdanm	0:9b334a45a8ff	241	*/
bogdanm	0:9b334a45a8ff	242
mbed_official	124:6a4a5b7d7324	243	/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
mbed_official	124:6a4a5b7d7324	244	* @{
mbed_official	124:6a4a5b7d7324	245	*/
mbed_official	124:6a4a5b7d7324	246	#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
mbed_official	124:6a4a5b7d7324	247	#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
mbed_official	124:6a4a5b7d7324	248	#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
mbed_official	124:6a4a5b7d7324	249	#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
mbed_official	124:6a4a5b7d7324	250	#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
mbed_official	124:6a4a5b7d7324	251	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
mbed_official	124:6a4a5b7d7324	252	#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
mbed_official	124:6a4a5b7d7324	253	#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
mbed_official	124:6a4a5b7d7324	254	#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
mbed_official	124:6a4a5b7d7324	255	#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
mbed_official	124:6a4a5b7d7324	256	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
mbed_official	124:6a4a5b7d7324	257	#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
mbed_official	124:6a4a5b7d7324	258	#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
mbed_official	124:6a4a5b7d7324	259	#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
mbed_official	124:6a4a5b7d7324	260	#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
mbed_official	124:6a4a5b7d7324	261
mbed_official	124:6a4a5b7d7324	262	#define IS_HAL_REMAPDMA IS_DMA_REMAP
mbed_official	124:6a4a5b7d7324	263	#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
mbed_official	124:6a4a5b7d7324	264	#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
mbed_official	124:6a4a5b7d7324	265
mbed_official	124:6a4a5b7d7324	266
mbed_official	124:6a4a5b7d7324	267
mbed_official	124:6a4a5b7d7324	268	/**
mbed_official	124:6a4a5b7d7324	269	* @}
mbed_official	124:6a4a5b7d7324	270	*/
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	273	* @{
bogdanm	0:9b334a45a8ff	274	*/
bogdanm	0:9b334a45a8ff	275
bogdanm	0:9b334a45a8ff	276	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
bogdanm	0:9b334a45a8ff	277	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
bogdanm	0:9b334a45a8ff	278	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
bogdanm	0:9b334a45a8ff	279	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
bogdanm	0:9b334a45a8ff	280	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
bogdanm	0:9b334a45a8ff	281	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
bogdanm	0:9b334a45a8ff	282	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
bogdanm	0:9b334a45a8ff	283	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
bogdanm	0:9b334a45a8ff	284	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
bogdanm	0:9b334a45a8ff	285	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
bogdanm	0:9b334a45a8ff	286	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	287	#define OBEX_PCROP OPTIONBYTE_PCROP
bogdanm	0:9b334a45a8ff	288	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
bogdanm	0:9b334a45a8ff	289	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
bogdanm	0:9b334a45a8ff	290	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
bogdanm	0:9b334a45a8ff	291	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
bogdanm	0:9b334a45a8ff	292	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
bogdanm	0:9b334a45a8ff	293	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
bogdanm	0:9b334a45a8ff	294	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
bogdanm	0:9b334a45a8ff	295	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
bogdanm	0:9b334a45a8ff	296	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
bogdanm	0:9b334a45a8ff	297	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
bogdanm	0:9b334a45a8ff	298	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
bogdanm	0:9b334a45a8ff	299	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
bogdanm	0:9b334a45a8ff	300	#define PAGESIZE FLASH_PAGE_SIZE
bogdanm	0:9b334a45a8ff	301	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
bogdanm	0:9b334a45a8ff	302	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
bogdanm	0:9b334a45a8ff	303	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
bogdanm	0:9b334a45a8ff	304	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
bogdanm	0:9b334a45a8ff	305	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
bogdanm	0:9b334a45a8ff	306	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
bogdanm	0:9b334a45a8ff	307	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
bogdanm	0:9b334a45a8ff	308	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
bogdanm	0:9b334a45a8ff	309	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
bogdanm	0:9b334a45a8ff	310	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
bogdanm	0:9b334a45a8ff	311	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
bogdanm	0:9b334a45a8ff	312	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
bogdanm	0:9b334a45a8ff	313	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
bogdanm	0:9b334a45a8ff	314	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
bogdanm	0:9b334a45a8ff	315	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
bogdanm	0:9b334a45a8ff	316	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
bogdanm	0:9b334a45a8ff	317	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
bogdanm	0:9b334a45a8ff	318	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
bogdanm	0:9b334a45a8ff	319	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
bogdanm	0:9b334a45a8ff	320	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
bogdanm	0:9b334a45a8ff	321	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
bogdanm	0:9b334a45a8ff	322	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
bogdanm	0:9b334a45a8ff	323	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
bogdanm	0:9b334a45a8ff	324	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
bogdanm	0:9b334a45a8ff	325	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
bogdanm	0:9b334a45a8ff	326	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
bogdanm	0:9b334a45a8ff	327	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
bogdanm	0:9b334a45a8ff	328	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
bogdanm	0:9b334a45a8ff	329	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
bogdanm	0:9b334a45a8ff	330	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
bogdanm	0:9b334a45a8ff	331	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
bogdanm	0:9b334a45a8ff	332	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
bogdanm	0:9b334a45a8ff	333	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
bogdanm	0:9b334a45a8ff	334	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
bogdanm	0:9b334a45a8ff	335	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
bogdanm	0:9b334a45a8ff	336	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
mbed_official	124:6a4a5b7d7324	337	#define OB_WDG_SW OB_IWDG_SW
mbed_official	124:6a4a5b7d7324	338	#define OB_WDG_HW OB_IWDG_HW
mbed_official	124:6a4a5b7d7324	339	#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
mbed_official	124:6a4a5b7d7324	340	#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
mbed_official	124:6a4a5b7d7324	341	#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
mbed_official	124:6a4a5b7d7324	342	#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
mbed_official	124:6a4a5b7d7324	343	#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
mbed_official	124:6a4a5b7d7324	344	#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
mbed_official	124:6a4a5b7d7324	345	#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
mbed_official	124:6a4a5b7d7324	346	#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
bogdanm	0:9b334a45a8ff	347	/**
bogdanm	0:9b334a45a8ff	348	* @}
bogdanm	0:9b334a45a8ff	349	*/
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	352	* @{
bogdanm	0:9b334a45a8ff	353	*/
bogdanm	0:9b334a45a8ff	354
mbed_official	124:6a4a5b7d7324	355	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
mbed_official	124:6a4a5b7d7324	356	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
mbed_official	124:6a4a5b7d7324	357	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
mbed_official	124:6a4a5b7d7324	358	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
mbed_official	124:6a4a5b7d7324	359	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
mbed_official	124:6a4a5b7d7324	360	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
mbed_official	124:6a4a5b7d7324	361	#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
mbed_official	124:6a4a5b7d7324	362	#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
mbed_official	124:6a4a5b7d7324	363	#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
bogdanm	0:9b334a45a8ff	364	/**
bogdanm	0:9b334a45a8ff	365	* @}
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368
mbed_official	124:6a4a5b7d7324	369	/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
mbed_official	124:6a4a5b7d7324	370	* @{
mbed_official	124:6a4a5b7d7324	371	*/
mbed_official	124:6a4a5b7d7324	372	#if defined(STM32L4) \|\| defined(STM32F7)
mbed_official	124:6a4a5b7d7324	373	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
mbed_official	124:6a4a5b7d7324	374	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
mbed_official	124:6a4a5b7d7324	375	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
mbed_official	124:6a4a5b7d7324	376	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
mbed_official	124:6a4a5b7d7324	377	#else
mbed_official	124:6a4a5b7d7324	378	#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
mbed_official	124:6a4a5b7d7324	379	#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
mbed_official	124:6a4a5b7d7324	380	#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
mbed_official	124:6a4a5b7d7324	381	#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
mbed_official	124:6a4a5b7d7324	382	#endif
mbed_official	124:6a4a5b7d7324	383	/**
mbed_official	124:6a4a5b7d7324	384	* @}
mbed_official	124:6a4a5b7d7324	385	*/
mbed_official	124:6a4a5b7d7324	386
bogdanm	0:9b334a45a8ff	387	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	388	* @{
bogdanm	0:9b334a45a8ff	389	*/
bogdanm	0:9b334a45a8ff	390
bogdanm	0:9b334a45a8ff	391	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
bogdanm	0:9b334a45a8ff	392	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
bogdanm	0:9b334a45a8ff	393	/**
bogdanm	0:9b334a45a8ff	394	* @}
bogdanm	0:9b334a45a8ff	395	*/
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	398	* @{
bogdanm	0:9b334a45a8ff	399	*/
bogdanm	0:9b334a45a8ff	400	#define GET_GPIO_SOURCE GPIO_GET_INDEX
bogdanm	0:9b334a45a8ff	401	#define GET_GPIO_INDEX GPIO_GET_INDEX
mbed_official	124:6a4a5b7d7324	402
mbed_official	124:6a4a5b7d7324	403	#if defined(STM32F4)
mbed_official	124:6a4a5b7d7324	404	#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
mbed_official	124:6a4a5b7d7324	405	#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
mbed_official	124:6a4a5b7d7324	406	#endif
mbed_official	124:6a4a5b7d7324	407
mbed_official	124:6a4a5b7d7324	408	#if defined(STM32F7)
mbed_official	124:6a4a5b7d7324	409	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
mbed_official	124:6a4a5b7d7324	410	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
mbed_official	124:6a4a5b7d7324	411	#endif
mbed_official	124:6a4a5b7d7324	412
mbed_official	124:6a4a5b7d7324	413	#if defined(STM32L4)
mbed_official	124:6a4a5b7d7324	414	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
mbed_official	124:6a4a5b7d7324	415	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
mbed_official	124:6a4a5b7d7324	416	#endif
mbed_official	124:6a4a5b7d7324	417
mbed_official	124:6a4a5b7d7324	418	#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
mbed_official	124:6a4a5b7d7324	419	#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
mbed_official	124:6a4a5b7d7324	420	#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
mbed_official	124:6a4a5b7d7324	421
mbed_official	124:6a4a5b7d7324	422	#if defined(STM32L0) \|\| defined(STM32L4) \|\| defined(STM32F4) \|\| defined(STM32F2) \|\| defined(STM32F7)
mbed_official	124:6a4a5b7d7324	423	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
mbed_official	124:6a4a5b7d7324	424	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
mbed_official	124:6a4a5b7d7324	425	#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
mbed_official	124:6a4a5b7d7324	426	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
mbed_official	124:6a4a5b7d7324	427	#endif /* STM32L0 \|\| STM32L4 \|\| STM32F4 \|\| STM32F2 \|\| STM32F7 */
mbed_official	124:6a4a5b7d7324	428
mbed_official	124:6a4a5b7d7324	429	#if defined(STM32L1)
mbed_official	124:6a4a5b7d7324	430	#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
mbed_official	124:6a4a5b7d7324	431	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
mbed_official	124:6a4a5b7d7324	432	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
mbed_official	124:6a4a5b7d7324	433	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
mbed_official	124:6a4a5b7d7324	434	#endif /* STM32L1 */
mbed_official	124:6a4a5b7d7324	435
mbed_official	124:6a4a5b7d7324	436	#if defined(STM32F0) \|\| defined(STM32F3) \|\| defined(STM32F1)
mbed_official	124:6a4a5b7d7324	437	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
mbed_official	124:6a4a5b7d7324	438	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
mbed_official	124:6a4a5b7d7324	439	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
mbed_official	124:6a4a5b7d7324	440	#endif /* STM32F0 \|\| STM32F3 \|\| STM32F1 */
mbed_official	124:6a4a5b7d7324	441
mbed_official	124:6a4a5b7d7324	442	#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
bogdanm	0:9b334a45a8ff	443	/**
bogdanm	0:9b334a45a8ff	444	* @}
bogdanm	0:9b334a45a8ff	445	*/
bogdanm	0:9b334a45a8ff	446
mbed_official	124:6a4a5b7d7324	447	/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
mbed_official	124:6a4a5b7d7324	448	* @{
mbed_official	124:6a4a5b7d7324	449	*/
mbed_official	124:6a4a5b7d7324	450	#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
mbed_official	124:6a4a5b7d7324	451	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
mbed_official	124:6a4a5b7d7324	452	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
mbed_official	124:6a4a5b7d7324	453	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
mbed_official	124:6a4a5b7d7324	454	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
mbed_official	124:6a4a5b7d7324	455	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
mbed_official	124:6a4a5b7d7324	456	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
mbed_official	124:6a4a5b7d7324	457	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
mbed_official	124:6a4a5b7d7324	458	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
mbed_official	124:6a4a5b7d7324	459
mbed_official	124:6a4a5b7d7324	460	#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
mbed_official	124:6a4a5b7d7324	461	#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
mbed_official	124:6a4a5b7d7324	462	#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
mbed_official	124:6a4a5b7d7324	463	#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
mbed_official	124:6a4a5b7d7324	464	#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
mbed_official	124:6a4a5b7d7324	465	#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
mbed_official	124:6a4a5b7d7324	466	#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
mbed_official	124:6a4a5b7d7324	467	#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
mbed_official	124:6a4a5b7d7324	468	/**
mbed_official	124:6a4a5b7d7324	469	* @}
mbed_official	124:6a4a5b7d7324	470	*/
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	473	* @{
bogdanm	0:9b334a45a8ff	474	*/
bogdanm	0:9b334a45a8ff	475	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
bogdanm	0:9b334a45a8ff	476	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
bogdanm	0:9b334a45a8ff	477	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
bogdanm	0:9b334a45a8ff	478	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
bogdanm	0:9b334a45a8ff	479	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
bogdanm	0:9b334a45a8ff	480	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
bogdanm	0:9b334a45a8ff	481	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
bogdanm	0:9b334a45a8ff	482	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
mbed_official	124:6a4a5b7d7324	483	#if defined(STM32F0) \|\| defined(STM32F1) \|\| defined(STM32F3) \|\| defined(STM32G0) \|\| defined(STM32L4) \|\| defined(STM32L1) \|\| defined(STM32F7)
mbed_official	124:6a4a5b7d7324	484	#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
mbed_official	124:6a4a5b7d7324	485	#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
mbed_official	124:6a4a5b7d7324	486	#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
mbed_official	124:6a4a5b7d7324	487	#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
mbed_official	124:6a4a5b7d7324	488	#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
mbed_official	124:6a4a5b7d7324	489	#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
mbed_official	124:6a4a5b7d7324	490	#endif
bogdanm	0:9b334a45a8ff	491	/**
bogdanm	0:9b334a45a8ff	492	* @}
bogdanm	0:9b334a45a8ff	493	*/
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	496	* @{
bogdanm	0:9b334a45a8ff	497	*/
bogdanm	0:9b334a45a8ff	498	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	499	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	500
bogdanm	0:9b334a45a8ff	501	/**
bogdanm	0:9b334a45a8ff	502	* @}
bogdanm	0:9b334a45a8ff	503	*/
bogdanm	0:9b334a45a8ff	504
bogdanm	0:9b334a45a8ff	505	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	506	* @{
bogdanm	0:9b334a45a8ff	507	*/
bogdanm	0:9b334a45a8ff	508	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
bogdanm	0:9b334a45a8ff	509	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
bogdanm	0:9b334a45a8ff	510	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
bogdanm	0:9b334a45a8ff	511	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
bogdanm	0:9b334a45a8ff	512	/**
bogdanm	0:9b334a45a8ff	513	* @}
bogdanm	0:9b334a45a8ff	514	*/
bogdanm	0:9b334a45a8ff	515
mbed_official	124:6a4a5b7d7324	516	/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
mbed_official	124:6a4a5b7d7324	517	* @{
mbed_official	124:6a4a5b7d7324	518	*/
mbed_official	124:6a4a5b7d7324	519
mbed_official	124:6a4a5b7d7324	520	#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
mbed_official	124:6a4a5b7d7324	521	#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
mbed_official	124:6a4a5b7d7324	522	#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
mbed_official	124:6a4a5b7d7324	523	#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
mbed_official	124:6a4a5b7d7324	524
mbed_official	124:6a4a5b7d7324	525	#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
mbed_official	124:6a4a5b7d7324	526	#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
mbed_official	124:6a4a5b7d7324	527	#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
mbed_official	124:6a4a5b7d7324	528
mbed_official	124:6a4a5b7d7324	529	#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
mbed_official	124:6a4a5b7d7324	530	#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
mbed_official	124:6a4a5b7d7324	531	#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
mbed_official	124:6a4a5b7d7324	532	#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
mbed_official	124:6a4a5b7d7324	533
mbed_official	124:6a4a5b7d7324	534	/* The following 3 definition have also been present in a temporary version of lptim.h */
mbed_official	124:6a4a5b7d7324	535	/* They need to be renamed also to the right name, just in case */
mbed_official	124:6a4a5b7d7324	536	#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
mbed_official	124:6a4a5b7d7324	537	#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
mbed_official	124:6a4a5b7d7324	538	#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
mbed_official	124:6a4a5b7d7324	539
mbed_official	124:6a4a5b7d7324	540	/**
mbed_official	124:6a4a5b7d7324	541	* @}
mbed_official	124:6a4a5b7d7324	542	*/
mbed_official	124:6a4a5b7d7324	543
bogdanm	0:9b334a45a8ff	544	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	545	* @{
bogdanm	0:9b334a45a8ff	546	*/
mbed_official	124:6a4a5b7d7324	547	#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
mbed_official	124:6a4a5b7d7324	548	#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
mbed_official	124:6a4a5b7d7324	549	#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
mbed_official	124:6a4a5b7d7324	550	#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
mbed_official	124:6a4a5b7d7324	551
bogdanm	0:9b334a45a8ff	552	#define NAND_AddressTypedef NAND_AddressTypeDef
bogdanm	0:9b334a45a8ff	553
mbed_official	124:6a4a5b7d7324	554	#define __ARRAY_ADDRESS ARRAY_ADDRESS
mbed_official	124:6a4a5b7d7324	555	#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
mbed_official	124:6a4a5b7d7324	556	#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
mbed_official	124:6a4a5b7d7324	557	#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
mbed_official	124:6a4a5b7d7324	558	#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
bogdanm	0:9b334a45a8ff	559	/**
bogdanm	0:9b334a45a8ff	560	* @}
bogdanm	0:9b334a45a8ff	561	*/
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	564	* @{
bogdanm	0:9b334a45a8ff	565	*/
bogdanm	0:9b334a45a8ff	566	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
bogdanm	0:9b334a45a8ff	567	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
bogdanm	0:9b334a45a8ff	568	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
bogdanm	0:9b334a45a8ff	569	#define NOR_ERROR HAL_NOR_STATUS_ERROR
bogdanm	0:9b334a45a8ff	570	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
bogdanm	0:9b334a45a8ff	571
mbed_official	124:6a4a5b7d7324	572	#define __NOR_WRITE NOR_WRITE
mbed_official	124:6a4a5b7d7324	573	#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
bogdanm	0:9b334a45a8ff	574	/**
bogdanm	0:9b334a45a8ff	575	* @}
bogdanm	0:9b334a45a8ff	576	*/
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	579	* @{
bogdanm	0:9b334a45a8ff	580	*/
bogdanm	0:9b334a45a8ff	581
bogdanm	0:9b334a45a8ff	582	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	583	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	584	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
bogdanm	0:9b334a45a8ff	585	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	588	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	589	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
bogdanm	0:9b334a45a8ff	590	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	593	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	594
bogdanm	0:9b334a45a8ff	595	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	596	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	597
bogdanm	0:9b334a45a8ff	598	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	599	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
bogdanm	0:9b334a45a8ff	604	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	605	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	/**
bogdanm	0:9b334a45a8ff	608	* @}
bogdanm	0:9b334a45a8ff	609	*/
bogdanm	0:9b334a45a8ff	610
bogdanm	0:9b334a45a8ff	611	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	612	* @{
bogdanm	0:9b334a45a8ff	613	*/
bogdanm	0:9b334a45a8ff	614	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
mbed_official	124:6a4a5b7d7324	615	#if defined(STM32F7)
mbed_official	124:6a4a5b7d7324	616	#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
mbed_official	124:6a4a5b7d7324	617	#endif
bogdanm	0:9b334a45a8ff	618	/**
bogdanm	0:9b334a45a8ff	619	* @}
bogdanm	0:9b334a45a8ff	620	*/
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	623	* @{
bogdanm	0:9b334a45a8ff	624	*/
bogdanm	0:9b334a45a8ff	625
bogdanm	0:9b334a45a8ff	626	/* Compact Flash-ATA registers description */
bogdanm	0:9b334a45a8ff	627	#define CF_DATA ATA_DATA
bogdanm	0:9b334a45a8ff	628	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
bogdanm	0:9b334a45a8ff	629	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
bogdanm	0:9b334a45a8ff	630	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
bogdanm	0:9b334a45a8ff	631	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
bogdanm	0:9b334a45a8ff	632	#define CF_CARD_HEAD ATA_CARD_HEAD
bogdanm	0:9b334a45a8ff	633	#define CF_STATUS_CMD ATA_STATUS_CMD
bogdanm	0:9b334a45a8ff	634	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
bogdanm	0:9b334a45a8ff	635	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
bogdanm	0:9b334a45a8ff	636
bogdanm	0:9b334a45a8ff	637	/* Compact Flash-ATA commands */
bogdanm	0:9b334a45a8ff	638	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
bogdanm	0:9b334a45a8ff	639	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
bogdanm	0:9b334a45a8ff	640	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
bogdanm	0:9b334a45a8ff	641	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
bogdanm	0:9b334a45a8ff	642
bogdanm	0:9b334a45a8ff	643	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
bogdanm	0:9b334a45a8ff	644	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
bogdanm	0:9b334a45a8ff	645	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
bogdanm	0:9b334a45a8ff	646	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
bogdanm	0:9b334a45a8ff	647	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
bogdanm	0:9b334a45a8ff	648	/**
bogdanm	0:9b334a45a8ff	649	* @}
bogdanm	0:9b334a45a8ff	650	*/
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	653	* @{
bogdanm	0:9b334a45a8ff	654	*/
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656	#define FORMAT_BIN RTC_FORMAT_BIN
bogdanm	0:9b334a45a8ff	657	#define FORMAT_BCD RTC_FORMAT_BCD
bogdanm	0:9b334a45a8ff	658
bogdanm	0:9b334a45a8ff	659	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
bogdanm	0:9b334a45a8ff	660	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
bogdanm	0:9b334a45a8ff	661	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
bogdanm	0:9b334a45a8ff	662	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
bogdanm	0:9b334a45a8ff	663	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
bogdanm	0:9b334a45a8ff	664
mbed_official	124:6a4a5b7d7324	665	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
bogdanm	0:9b334a45a8ff	666	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
mbed_official	124:6a4a5b7d7324	667	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
mbed_official	124:6a4a5b7d7324	668	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
mbed_official	124:6a4a5b7d7324	669	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
bogdanm	0:9b334a45a8ff	670	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
mbed_official	124:6a4a5b7d7324	671	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
mbed_official	124:6a4a5b7d7324	672	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
mbed_official	124:6a4a5b7d7324	673
mbed_official	124:6a4a5b7d7324	674	#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
mbed_official	124:6a4a5b7d7324	675	#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
mbed_official	124:6a4a5b7d7324	676	#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
mbed_official	124:6a4a5b7d7324	677	#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
mbed_official	124:6a4a5b7d7324	678
mbed_official	124:6a4a5b7d7324	679	#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
mbed_official	124:6a4a5b7d7324	680	#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
mbed_official	124:6a4a5b7d7324	681	#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
mbed_official	124:6a4a5b7d7324	682
mbed_official	124:6a4a5b7d7324	683	#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
mbed_official	124:6a4a5b7d7324	684	#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
mbed_official	124:6a4a5b7d7324	685	#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
bogdanm	0:9b334a45a8ff	686
bogdanm	0:9b334a45a8ff	687	/**
bogdanm	0:9b334a45a8ff	688	* @}
bogdanm	0:9b334a45a8ff	689	*/
bogdanm	0:9b334a45a8ff	690
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	693	* @{
bogdanm	0:9b334a45a8ff	694	*/
bogdanm	0:9b334a45a8ff	695	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
bogdanm	0:9b334a45a8ff	696	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
bogdanm	0:9b334a45a8ff	697
bogdanm	0:9b334a45a8ff	698	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	699	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	700	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	701	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
bogdanm	0:9b334a45a8ff	704	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
bogdanm	0:9b334a45a8ff	707	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
bogdanm	0:9b334a45a8ff	708	/**
bogdanm	0:9b334a45a8ff	709	* @}
bogdanm	0:9b334a45a8ff	710	*/
bogdanm	0:9b334a45a8ff	711
bogdanm	0:9b334a45a8ff	712
mbed_official	124:6a4a5b7d7324	713	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	714	* @{
bogdanm	0:9b334a45a8ff	715	*/
bogdanm	0:9b334a45a8ff	716	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
bogdanm	0:9b334a45a8ff	717	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
bogdanm	0:9b334a45a8ff	718	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
bogdanm	0:9b334a45a8ff	719	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
bogdanm	0:9b334a45a8ff	720	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
bogdanm	0:9b334a45a8ff	721	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
bogdanm	0:9b334a45a8ff	722	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
bogdanm	0:9b334a45a8ff	723	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
mbed_official	124:6a4a5b7d7324	724	#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
mbed_official	124:6a4a5b7d7324	725	#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
bogdanm	0:9b334a45a8ff	726	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
bogdanm	0:9b334a45a8ff	727	/**
bogdanm	0:9b334a45a8ff	728	* @}
bogdanm	0:9b334a45a8ff	729	*/
bogdanm	0:9b334a45a8ff	730
mbed_official	124:6a4a5b7d7324	731	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	732	* @{
bogdanm	0:9b334a45a8ff	733	*/
bogdanm	0:9b334a45a8ff	734	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
bogdanm	0:9b334a45a8ff	735	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
bogdanm	0:9b334a45a8ff	738	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
bogdanm	0:9b334a45a8ff	741	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
bogdanm	0:9b334a45a8ff	742
bogdanm	0:9b334a45a8ff	743	/**
bogdanm	0:9b334a45a8ff	744	* @}
bogdanm	0:9b334a45a8ff	745	*/
bogdanm	0:9b334a45a8ff	746
bogdanm	0:9b334a45a8ff	747	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	748	* @{
bogdanm	0:9b334a45a8ff	749	*/
bogdanm	0:9b334a45a8ff	750	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
bogdanm	0:9b334a45a8ff	751	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
bogdanm	0:9b334a45a8ff	752
bogdanm	0:9b334a45a8ff	753	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	754	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	755	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	756	#define TIM_DMABase_DIER TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	757	#define TIM_DMABase_SR TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	758	#define TIM_DMABase_EGR TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	759	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	760	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	761	#define TIM_DMABase_CCER TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	762	#define TIM_DMABase_CNT TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	763	#define TIM_DMABase_PSC TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	764	#define TIM_DMABase_ARR TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	765	#define TIM_DMABase_RCR TIM_DMABASE_RCR
bogdanm	0:9b334a45a8ff	766	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	767	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	768	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	769	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	770	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
bogdanm	0:9b334a45a8ff	771	#define TIM_DMABase_DCR TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	772	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
bogdanm	0:9b334a45a8ff	773	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
bogdanm	0:9b334a45a8ff	774	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
bogdanm	0:9b334a45a8ff	775	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
bogdanm	0:9b334a45a8ff	776	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
bogdanm	0:9b334a45a8ff	777	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
bogdanm	0:9b334a45a8ff	778	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
mbed_official	124:6a4a5b7d7324	779	#define TIM_DMABase_OR TIM_DMABASE_OR
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
bogdanm	0:9b334a45a8ff	782	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
bogdanm	0:9b334a45a8ff	783	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
bogdanm	0:9b334a45a8ff	784	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
bogdanm	0:9b334a45a8ff	785	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
bogdanm	0:9b334a45a8ff	786	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
bogdanm	0:9b334a45a8ff	787	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
bogdanm	0:9b334a45a8ff	788	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
bogdanm	0:9b334a45a8ff	789	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
bogdanm	0:9b334a45a8ff	790
bogdanm	0:9b334a45a8ff	791	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
bogdanm	0:9b334a45a8ff	792	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
bogdanm	0:9b334a45a8ff	793	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
bogdanm	0:9b334a45a8ff	794	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
bogdanm	0:9b334a45a8ff	795	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
bogdanm	0:9b334a45a8ff	796	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
bogdanm	0:9b334a45a8ff	797	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
bogdanm	0:9b334a45a8ff	798	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
bogdanm	0:9b334a45a8ff	799	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
bogdanm	0:9b334a45a8ff	800	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
bogdanm	0:9b334a45a8ff	801	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
bogdanm	0:9b334a45a8ff	802	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
bogdanm	0:9b334a45a8ff	803	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
bogdanm	0:9b334a45a8ff	804	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
bogdanm	0:9b334a45a8ff	805	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
bogdanm	0:9b334a45a8ff	806	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
bogdanm	0:9b334a45a8ff	807	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
bogdanm	0:9b334a45a8ff	808	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
bogdanm	0:9b334a45a8ff	809
bogdanm	0:9b334a45a8ff	810	/**
bogdanm	0:9b334a45a8ff	811	* @}
bogdanm	0:9b334a45a8ff	812	*/
bogdanm	0:9b334a45a8ff	813
mbed_official	124:6a4a5b7d7324	814	/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
mbed_official	124:6a4a5b7d7324	815	* @{
mbed_official	124:6a4a5b7d7324	816	*/
mbed_official	124:6a4a5b7d7324	817	#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
mbed_official	124:6a4a5b7d7324	818	#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
mbed_official	124:6a4a5b7d7324	819	/**
mbed_official	124:6a4a5b7d7324	820	* @}
mbed_official	124:6a4a5b7d7324	821	*/
mbed_official	124:6a4a5b7d7324	822
bogdanm	0:9b334a45a8ff	823	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	824	* @{
bogdanm	0:9b334a45a8ff	825	*/
bogdanm	0:9b334a45a8ff	826	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	827	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	828	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	829	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	830
bogdanm	0:9b334a45a8ff	831	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	832	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	833
bogdanm	0:9b334a45a8ff	834	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
bogdanm	0:9b334a45a8ff	835	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
bogdanm	0:9b334a45a8ff	836	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
bogdanm	0:9b334a45a8ff	837	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
bogdanm	0:9b334a45a8ff	838
bogdanm	0:9b334a45a8ff	839	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
bogdanm	0:9b334a45a8ff	840	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
bogdanm	0:9b334a45a8ff	841	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
bogdanm	0:9b334a45a8ff	842	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
bogdanm	0:9b334a45a8ff	845	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
bogdanm	0:9b334a45a8ff	846
bogdanm	0:9b334a45a8ff	847	/**
bogdanm	0:9b334a45a8ff	848	* @}
bogdanm	0:9b334a45a8ff	849	*/
bogdanm	0:9b334a45a8ff	850
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	853	* @{
bogdanm	0:9b334a45a8ff	854	*/
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
bogdanm	0:9b334a45a8ff	857	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	#define USARTNACK_ENABLED USART_NACK_ENABLE
bogdanm	0:9b334a45a8ff	860	#define USARTNACK_DISABLED USART_NACK_DISABLE
bogdanm	0:9b334a45a8ff	861	/**
bogdanm	0:9b334a45a8ff	862	* @}
bogdanm	0:9b334a45a8ff	863	*/
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	866	* @{
bogdanm	0:9b334a45a8ff	867	*/
bogdanm	0:9b334a45a8ff	868	#define CFR_BASE WWDG_CFR_BASE
bogdanm	0:9b334a45a8ff	869
bogdanm	0:9b334a45a8ff	870	/**
bogdanm	0:9b334a45a8ff	871	* @}
bogdanm	0:9b334a45a8ff	872	*/
bogdanm	0:9b334a45a8ff	873
bogdanm	0:9b334a45a8ff	874	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	875	* @{
bogdanm	0:9b334a45a8ff	876	*/
bogdanm	0:9b334a45a8ff	877	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
bogdanm	0:9b334a45a8ff	878	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
bogdanm	0:9b334a45a8ff	879	#define CAN_IT_RQCP0 CAN_IT_TME
bogdanm	0:9b334a45a8ff	880	#define CAN_IT_RQCP1 CAN_IT_TME
bogdanm	0:9b334a45a8ff	881	#define CAN_IT_RQCP2 CAN_IT_TME
bogdanm	0:9b334a45a8ff	882	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	883	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
mbed_official	124:6a4a5b7d7324	884	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
mbed_official	124:6a4a5b7d7324	885	#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
mbed_official	124:6a4a5b7d7324	886	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
bogdanm	0:9b334a45a8ff	887
bogdanm	0:9b334a45a8ff	888	/**
bogdanm	0:9b334a45a8ff	889	* @}
bogdanm	0:9b334a45a8ff	890	*/
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	893	* @{
bogdanm	0:9b334a45a8ff	894	*/
bogdanm	0:9b334a45a8ff	895
bogdanm	0:9b334a45a8ff	896	#define VLAN_TAG ETH_VLAN_TAG
bogdanm	0:9b334a45a8ff	897	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
bogdanm	0:9b334a45a8ff	898	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
bogdanm	0:9b334a45a8ff	899	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
bogdanm	0:9b334a45a8ff	900	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
bogdanm	0:9b334a45a8ff	901	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
bogdanm	0:9b334a45a8ff	902	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
bogdanm	0:9b334a45a8ff	903	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
bogdanm	0:9b334a45a8ff	904
mbed_official	124:6a4a5b7d7324	905	#define ETH_MMCCR ((uint32_t)0x00000100U)
mbed_official	124:6a4a5b7d7324	906	#define ETH_MMCRIR ((uint32_t)0x00000104U)
mbed_official	124:6a4a5b7d7324	907	#define ETH_MMCTIR ((uint32_t)0x00000108U)
mbed_official	124:6a4a5b7d7324	908	#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
mbed_official	124:6a4a5b7d7324	909	#define ETH_MMCTIMR ((uint32_t)0x00000110U)
mbed_official	124:6a4a5b7d7324	910	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
mbed_official	124:6a4a5b7d7324	911	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
mbed_official	124:6a4a5b7d7324	912	#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
mbed_official	124:6a4a5b7d7324	913	#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
mbed_official	124:6a4a5b7d7324	914	#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
mbed_official	124:6a4a5b7d7324	915	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
mbed_official	124:6a4a5b7d7324	916
mbed_official	124:6a4a5b7d7324	917	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
mbed_official	124:6a4a5b7d7324	918	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
mbed_official	124:6a4a5b7d7324	919	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
mbed_official	124:6a4a5b7d7324	920	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
mbed_official	124:6a4a5b7d7324	921	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
mbed_official	124:6a4a5b7d7324	922	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
mbed_official	124:6a4a5b7d7324	923	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
mbed_official	124:6a4a5b7d7324	924	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
mbed_official	124:6a4a5b7d7324	925	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
mbed_official	124:6a4a5b7d7324	926	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
mbed_official	124:6a4a5b7d7324	927	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
mbed_official	124:6a4a5b7d7324	928	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
mbed_official	124:6a4a5b7d7324	929	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
mbed_official	124:6a4a5b7d7324	930	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
mbed_official	124:6a4a5b7d7324	931	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
mbed_official	124:6a4a5b7d7324	932	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
mbed_official	124:6a4a5b7d7324	933	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
mbed_official	124:6a4a5b7d7324	934	#if defined(STM32F1)
mbed_official	124:6a4a5b7d7324	935	#else
mbed_official	124:6a4a5b7d7324	936	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
mbed_official	124:6a4a5b7d7324	937	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
mbed_official	124:6a4a5b7d7324	938	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
mbed_official	124:6a4a5b7d7324	939	#endif
mbed_official	124:6a4a5b7d7324	940	#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
mbed_official	124:6a4a5b7d7324	941	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
mbed_official	124:6a4a5b7d7324	942	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
mbed_official	124:6a4a5b7d7324	943	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
mbed_official	124:6a4a5b7d7324	944	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
mbed_official	124:6a4a5b7d7324	945	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
mbed_official	124:6a4a5b7d7324	946	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
bogdanm	0:9b334a45a8ff	947
bogdanm	0:9b334a45a8ff	948	/**
bogdanm	0:9b334a45a8ff	949	* @}
bogdanm	0:9b334a45a8ff	950	*/
mbed_official	124:6a4a5b7d7324	951
mbed_official	124:6a4a5b7d7324	952	/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
mbed_official	124:6a4a5b7d7324	953	* @{
mbed_official	124:6a4a5b7d7324	954	*/
mbed_official	124:6a4a5b7d7324	955	#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
mbed_official	124:6a4a5b7d7324	956	#define DCMI_IT_OVF DCMI_IT_OVR
mbed_official	124:6a4a5b7d7324	957	#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
mbed_official	124:6a4a5b7d7324	958	#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
mbed_official	124:6a4a5b7d7324	959
mbed_official	124:6a4a5b7d7324	960	#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
mbed_official	124:6a4a5b7d7324	961	#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
mbed_official	124:6a4a5b7d7324	962	#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
mbed_official	124:6a4a5b7d7324	963
mbed_official	124:6a4a5b7d7324	964	/**
mbed_official	124:6a4a5b7d7324	965	* @}
mbed_official	124:6a4a5b7d7324	966	*/
mbed_official	124:6a4a5b7d7324	967
mbed_official	124:6a4a5b7d7324	968	#if defined(STM32L4xx) \|\| defined(STM32F7) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\|\
mbed_official	124:6a4a5b7d7324	969	defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
mbed_official	124:6a4a5b7d7324	970	/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
mbed_official	124:6a4a5b7d7324	971	* @{
mbed_official	124:6a4a5b7d7324	972	*/
mbed_official	124:6a4a5b7d7324	973	#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
mbed_official	124:6a4a5b7d7324	974	#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
mbed_official	124:6a4a5b7d7324	975	#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
mbed_official	124:6a4a5b7d7324	976	#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
mbed_official	124:6a4a5b7d7324	977	#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
mbed_official	124:6a4a5b7d7324	978
mbed_official	124:6a4a5b7d7324	979	#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
mbed_official	124:6a4a5b7d7324	980	#define CM_RGB888 DMA2D_INPUT_RGB888
mbed_official	124:6a4a5b7d7324	981	#define CM_RGB565 DMA2D_INPUT_RGB565
mbed_official	124:6a4a5b7d7324	982	#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
mbed_official	124:6a4a5b7d7324	983	#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
mbed_official	124:6a4a5b7d7324	984	#define CM_L8 DMA2D_INPUT_L8
mbed_official	124:6a4a5b7d7324	985	#define CM_AL44 DMA2D_INPUT_AL44
mbed_official	124:6a4a5b7d7324	986	#define CM_AL88 DMA2D_INPUT_AL88
mbed_official	124:6a4a5b7d7324	987	#define CM_L4 DMA2D_INPUT_L4
mbed_official	124:6a4a5b7d7324	988	#define CM_A8 DMA2D_INPUT_A8
mbed_official	124:6a4a5b7d7324	989	#define CM_A4 DMA2D_INPUT_A4
mbed_official	124:6a4a5b7d7324	990	/**
mbed_official	124:6a4a5b7d7324	991	* @}
mbed_official	124:6a4a5b7d7324	992	*/
mbed_official	124:6a4a5b7d7324	993	#endif /* STM32L4xx \|\| STM32F7*/
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	996	* @{
bogdanm	0:9b334a45a8ff	997	*/
bogdanm	0:9b334a45a8ff	998
bogdanm	0:9b334a45a8ff	999	/**
bogdanm	0:9b334a45a8ff	1000	* @}
bogdanm	0:9b334a45a8ff	1001	*/
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1004
bogdanm	0:9b334a45a8ff	1005	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1006	* @{
bogdanm	0:9b334a45a8ff	1007	*/
bogdanm	0:9b334a45a8ff	1008	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
bogdanm	0:9b334a45a8ff	1009	/**
bogdanm	0:9b334a45a8ff	1010	* @}
bogdanm	0:9b334a45a8ff	1011	*/
bogdanm	0:9b334a45a8ff	1012
bogdanm	0:9b334a45a8ff	1013	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1014	* @{
bogdanm	0:9b334a45a8ff	1015	*/
mbed_official	124:6a4a5b7d7324	1016	#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
mbed_official	124:6a4a5b7d7324	1017	#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
bogdanm	0:9b334a45a8ff	1018	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
bogdanm	0:9b334a45a8ff	1019	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
bogdanm	0:9b334a45a8ff	1020	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
bogdanm	0:9b334a45a8ff	1021	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/HASH Algorithm Selection/
bogdanm	0:9b334a45a8ff	1024
bogdanm	0:9b334a45a8ff	1025	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
bogdanm	0:9b334a45a8ff	1026	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
bogdanm	0:9b334a45a8ff	1027	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
bogdanm	0:9b334a45a8ff	1028	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
bogdanm	0:9b334a45a8ff	1029
bogdanm	0:9b334a45a8ff	1030	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
bogdanm	0:9b334a45a8ff	1031	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
bogdanm	0:9b334a45a8ff	1032
bogdanm	0:9b334a45a8ff	1033	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
bogdanm	0:9b334a45a8ff	1034	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
bogdanm	0:9b334a45a8ff	1035	/**
bogdanm	0:9b334a45a8ff	1036	* @}
bogdanm	0:9b334a45a8ff	1037	*/
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1040	* @{
bogdanm	0:9b334a45a8ff	1041	*/
bogdanm	0:9b334a45a8ff	1042	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
bogdanm	0:9b334a45a8ff	1043	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
bogdanm	0:9b334a45a8ff	1044	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
bogdanm	0:9b334a45a8ff	1045	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
bogdanm	0:9b334a45a8ff	1046	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
bogdanm	0:9b334a45a8ff	1047	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
mbed_official	124:6a4a5b7d7324	1048	#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
bogdanm	0:9b334a45a8ff	1049	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
mbed_official	124:6a4a5b7d7324	1050	#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
mbed_official	124:6a4a5b7d7324	1051	#if defined(STM32L0)
mbed_official	124:6a4a5b7d7324	1052	#else
mbed_official	124:6a4a5b7d7324	1053	#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
mbed_official	124:6a4a5b7d7324	1054	#endif
mbed_official	124:6a4a5b7d7324	1055	#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
mbed_official	124:6a4a5b7d7324	1056	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
bogdanm	0:9b334a45a8ff	1057	/**
bogdanm	0:9b334a45a8ff	1058	* @}
bogdanm	0:9b334a45a8ff	1059	*/
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1062	* @{
bogdanm	0:9b334a45a8ff	1063	*/
bogdanm	0:9b334a45a8ff	1064	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
bogdanm	0:9b334a45a8ff	1065	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
bogdanm	0:9b334a45a8ff	1066	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
bogdanm	0:9b334a45a8ff	1067	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
bogdanm	0:9b334a45a8ff	1068	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
bogdanm	0:9b334a45a8ff	1069	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
bogdanm	0:9b334a45a8ff	1070	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
bogdanm	0:9b334a45a8ff	1071
bogdanm	0:9b334a45a8ff	1072	/**
bogdanm	0:9b334a45a8ff	1073	* @}
bogdanm	0:9b334a45a8ff	1074	*/
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1077	* @{
bogdanm	0:9b334a45a8ff	1078	*/
mbed_official	124:6a4a5b7d7324	1079	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
mbed_official	124:6a4a5b7d7324	1080	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
mbed_official	124:6a4a5b7d7324	1081	#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
mbed_official	124:6a4a5b7d7324	1082	#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
bogdanm	0:9b334a45a8ff	1083
mbed_official	124:6a4a5b7d7324	1084	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
bogdanm	0:9b334a45a8ff	1085	/**
bogdanm	0:9b334a45a8ff	1086	* @}
bogdanm	0:9b334a45a8ff	1087	*/
bogdanm	0:9b334a45a8ff	1088
bogdanm	0:9b334a45a8ff	1089	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1090	* @{
bogdanm	0:9b334a45a8ff	1091	*/
bogdanm	0:9b334a45a8ff	1092	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
bogdanm	0:9b334a45a8ff	1093	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
bogdanm	0:9b334a45a8ff	1094	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
bogdanm	0:9b334a45a8ff	1095	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
bogdanm	0:9b334a45a8ff	1096	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
bogdanm	0:9b334a45a8ff	1097	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
bogdanm	0:9b334a45a8ff	1098	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
bogdanm	0:9b334a45a8ff	1099	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
bogdanm	0:9b334a45a8ff	1100	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
bogdanm	0:9b334a45a8ff	1101	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
bogdanm	0:9b334a45a8ff	1102	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
bogdanm	0:9b334a45a8ff	1103	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
bogdanm	0:9b334a45a8ff	1104	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
bogdanm	0:9b334a45a8ff	1105	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
bogdanm	0:9b334a45a8ff	1106	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
bogdanm	0:9b334a45a8ff	1107	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
bogdanm	0:9b334a45a8ff	1110	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
bogdanm	0:9b334a45a8ff	1111	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
bogdanm	0:9b334a45a8ff	1112	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
bogdanm	0:9b334a45a8ff	1113	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
bogdanm	0:9b334a45a8ff	1114	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
bogdanm	0:9b334a45a8ff	1115	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
bogdanm	0:9b334a45a8ff	1118	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	#define DBP_BitNumber DBP_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1121	#define PVDE_BitNumber PVDE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1122	#define PMODE_BitNumber PMODE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1123	#define EWUP_BitNumber EWUP_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1124	#define FPDS_BitNumber FPDS_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1125	#define ODEN_BitNumber ODEN_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1126	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1127	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1128	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1129	#define BRE_BitNumber BRE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1130
bogdanm	0:9b334a45a8ff	1131	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
bogdanm	0:9b334a45a8ff	1132
bogdanm	0:9b334a45a8ff	1133	/**
bogdanm	0:9b334a45a8ff	1134	* @}
bogdanm	0:9b334a45a8ff	1135	*/
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1138	* @{
bogdanm	0:9b334a45a8ff	1139	*/
bogdanm	0:9b334a45a8ff	1140	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
bogdanm	0:9b334a45a8ff	1141	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
bogdanm	0:9b334a45a8ff	1142	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
bogdanm	0:9b334a45a8ff	1143	/**
bogdanm	0:9b334a45a8ff	1144	* @}
bogdanm	0:9b334a45a8ff	1145	*/
bogdanm	0:9b334a45a8ff	1146
bogdanm	0:9b334a45a8ff	1147	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1148	* @{
bogdanm	0:9b334a45a8ff	1149	*/
bogdanm	0:9b334a45a8ff	1150	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
bogdanm	0:9b334a45a8ff	1151	/**
bogdanm	0:9b334a45a8ff	1152	* @}
bogdanm	0:9b334a45a8ff	1153	*/
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1156	* @{
bogdanm	0:9b334a45a8ff	1157	*/
bogdanm	0:9b334a45a8ff	1158	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
bogdanm	0:9b334a45a8ff	1159	#define HAL_TIM_DMAError TIM_DMAError
bogdanm	0:9b334a45a8ff	1160	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
bogdanm	0:9b334a45a8ff	1161	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
bogdanm	0:9b334a45a8ff	1162	/**
bogdanm	0:9b334a45a8ff	1163	* @}
bogdanm	0:9b334a45a8ff	1164	*/
bogdanm	0:9b334a45a8ff	1165
bogdanm	0:9b334a45a8ff	1166	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1167	* @{
bogdanm	0:9b334a45a8ff	1168	*/
bogdanm	0:9b334a45a8ff	1169	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
bogdanm	0:9b334a45a8ff	1170	/**
bogdanm	0:9b334a45a8ff	1171	* @}
bogdanm	0:9b334a45a8ff	1172	*/
mbed_official	124:6a4a5b7d7324	1173
mbed_official	124:6a4a5b7d7324	1174	/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
mbed_official	124:6a4a5b7d7324	1175	* @{
mbed_official	124:6a4a5b7d7324	1176	*/
mbed_official	124:6a4a5b7d7324	1177	#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
mbed_official	124:6a4a5b7d7324	1178	/**
mbed_official	124:6a4a5b7d7324	1179	* @}
mbed_official	124:6a4a5b7d7324	1180	*/
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182
mbed_official	124:6a4a5b7d7324	1183	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1184	* @{
bogdanm	0:9b334a45a8ff	1185	*/
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	/**
bogdanm	0:9b334a45a8ff	1188	* @}
bogdanm	0:9b334a45a8ff	1189	*/
bogdanm	0:9b334a45a8ff	1190
bogdanm	0:9b334a45a8ff	1191	/* Exported macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1194	* @{
bogdanm	0:9b334a45a8ff	1195	*/
bogdanm	0:9b334a45a8ff	1196	#define AES_IT_CC CRYP_IT_CC
bogdanm	0:9b334a45a8ff	1197	#define AES_IT_ERR CRYP_IT_ERR
bogdanm	0:9b334a45a8ff	1198	#define AES_FLAG_CCF CRYP_FLAG_CCF
bogdanm	0:9b334a45a8ff	1199	/**
bogdanm	0:9b334a45a8ff	1200	* @}
bogdanm	0:9b334a45a8ff	1201	*/
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1204	* @{
bogdanm	0:9b334a45a8ff	1205	*/
bogdanm	0:9b334a45a8ff	1206	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
bogdanm	0:9b334a45a8ff	1207	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
bogdanm	0:9b334a45a8ff	1208	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
bogdanm	0:9b334a45a8ff	1209	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
bogdanm	0:9b334a45a8ff	1210	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
bogdanm	0:9b334a45a8ff	1211	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
mbed_official	124:6a4a5b7d7324	1212	#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
mbed_official	124:6a4a5b7d7324	1213	#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
bogdanm	0:9b334a45a8ff	1214	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
bogdanm	0:9b334a45a8ff	1215	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
bogdanm	0:9b334a45a8ff	1216	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
mbed_official	124:6a4a5b7d7324	1217	#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
mbed_official	124:6a4a5b7d7324	1218	#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
mbed_official	124:6a4a5b7d7324	1219
bogdanm	0:9b334a45a8ff	1220	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
bogdanm	0:9b334a45a8ff	1221	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
bogdanm	0:9b334a45a8ff	1222	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
bogdanm	0:9b334a45a8ff	1223	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1224	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1225
bogdanm	0:9b334a45a8ff	1226	/**
bogdanm	0:9b334a45a8ff	1227	* @}
bogdanm	0:9b334a45a8ff	1228	*/
bogdanm	0:9b334a45a8ff	1229
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1232	* @{
bogdanm	0:9b334a45a8ff	1233	*/
bogdanm	0:9b334a45a8ff	1234	#define __ADC_ENABLE __HAL_ADC_ENABLE
bogdanm	0:9b334a45a8ff	1235	#define __ADC_DISABLE __HAL_ADC_DISABLE
bogdanm	0:9b334a45a8ff	1236	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
bogdanm	0:9b334a45a8ff	1237	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
bogdanm	0:9b334a45a8ff	1238	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
bogdanm	0:9b334a45a8ff	1239	#define __ADC_IS_ENABLED ADC_IS_ENABLE
bogdanm	0:9b334a45a8ff	1240	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
bogdanm	0:9b334a45a8ff	1241	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
bogdanm	0:9b334a45a8ff	1242	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
bogdanm	0:9b334a45a8ff	1243	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
bogdanm	0:9b334a45a8ff	1244	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
bogdanm	0:9b334a45a8ff	1245	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
bogdanm	0:9b334a45a8ff	1246	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
bogdanm	0:9b334a45a8ff	1249	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
bogdanm	0:9b334a45a8ff	1250	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
bogdanm	0:9b334a45a8ff	1251	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
bogdanm	0:9b334a45a8ff	1252	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
bogdanm	0:9b334a45a8ff	1253	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
bogdanm	0:9b334a45a8ff	1254	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
bogdanm	0:9b334a45a8ff	1255	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
bogdanm	0:9b334a45a8ff	1256	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
bogdanm	0:9b334a45a8ff	1257	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
bogdanm	0:9b334a45a8ff	1258	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
bogdanm	0:9b334a45a8ff	1259	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
bogdanm	0:9b334a45a8ff	1260	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
bogdanm	0:9b334a45a8ff	1261	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
bogdanm	0:9b334a45a8ff	1262	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
bogdanm	0:9b334a45a8ff	1263	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
bogdanm	0:9b334a45a8ff	1264	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
bogdanm	0:9b334a45a8ff	1265	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
bogdanm	0:9b334a45a8ff	1266	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
bogdanm	0:9b334a45a8ff	1267	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
bogdanm	0:9b334a45a8ff	1270	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
bogdanm	0:9b334a45a8ff	1271	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
bogdanm	0:9b334a45a8ff	1272	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
bogdanm	0:9b334a45a8ff	1273	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
bogdanm	0:9b334a45a8ff	1274	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
bogdanm	0:9b334a45a8ff	1275	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
bogdanm	0:9b334a45a8ff	1276	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
bogdanm	0:9b334a45a8ff	1277	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
bogdanm	0:9b334a45a8ff	1278	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
bogdanm	0:9b334a45a8ff	1281	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
bogdanm	0:9b334a45a8ff	1282	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
bogdanm	0:9b334a45a8ff	1283	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
bogdanm	0:9b334a45a8ff	1284	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
bogdanm	0:9b334a45a8ff	1285	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
bogdanm	0:9b334a45a8ff	1286	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
bogdanm	0:9b334a45a8ff	1287	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	#define __HAL_ADC_SQR1 ADC_SQR1
bogdanm	0:9b334a45a8ff	1290	#define __HAL_ADC_SMPR1 ADC_SMPR1
bogdanm	0:9b334a45a8ff	1291	#define __HAL_ADC_SMPR2 ADC_SMPR2
bogdanm	0:9b334a45a8ff	1292	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
bogdanm	0:9b334a45a8ff	1293	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
bogdanm	0:9b334a45a8ff	1294	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
bogdanm	0:9b334a45a8ff	1295	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
bogdanm	0:9b334a45a8ff	1296	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
bogdanm	0:9b334a45a8ff	1297	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
bogdanm	0:9b334a45a8ff	1298	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
bogdanm	0:9b334a45a8ff	1299	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
bogdanm	0:9b334a45a8ff	1300	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
bogdanm	0:9b334a45a8ff	1301	#define __HAL_ADC_JSQR ADC_JSQR
bogdanm	0:9b334a45a8ff	1302
bogdanm	0:9b334a45a8ff	1303	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
bogdanm	0:9b334a45a8ff	1304	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
bogdanm	0:9b334a45a8ff	1305	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
bogdanm	0:9b334a45a8ff	1306	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
bogdanm	0:9b334a45a8ff	1307	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
bogdanm	0:9b334a45a8ff	1308	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
bogdanm	0:9b334a45a8ff	1309	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
bogdanm	0:9b334a45a8ff	1310	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/**
bogdanm	0:9b334a45a8ff	1313	* @}
bogdanm	0:9b334a45a8ff	1314	*/
bogdanm	0:9b334a45a8ff	1315
bogdanm	0:9b334a45a8ff	1316	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1317	* @{
bogdanm	0:9b334a45a8ff	1318	*/
bogdanm	0:9b334a45a8ff	1319	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
bogdanm	0:9b334a45a8ff	1320	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
bogdanm	0:9b334a45a8ff	1321	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
mbed_official	124:6a4a5b7d7324	1322	#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
mbed_official	124:6a4a5b7d7324	1323
bogdanm	0:9b334a45a8ff	1324	/**
bogdanm	0:9b334a45a8ff	1325	* @}
bogdanm	0:9b334a45a8ff	1326	*/
bogdanm	0:9b334a45a8ff	1327
bogdanm	0:9b334a45a8ff	1328	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1329	* @{
bogdanm	0:9b334a45a8ff	1330	*/
bogdanm	0:9b334a45a8ff	1331	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
bogdanm	0:9b334a45a8ff	1332	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
bogdanm	0:9b334a45a8ff	1333	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
bogdanm	0:9b334a45a8ff	1334	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
bogdanm	0:9b334a45a8ff	1335	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
bogdanm	0:9b334a45a8ff	1336	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
bogdanm	0:9b334a45a8ff	1337	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
bogdanm	0:9b334a45a8ff	1338	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
bogdanm	0:9b334a45a8ff	1339	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
bogdanm	0:9b334a45a8ff	1340	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
bogdanm	0:9b334a45a8ff	1341	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
bogdanm	0:9b334a45a8ff	1342	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
bogdanm	0:9b334a45a8ff	1343	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
bogdanm	0:9b334a45a8ff	1344	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
bogdanm	0:9b334a45a8ff	1345	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
bogdanm	0:9b334a45a8ff	1346	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
bogdanm	0:9b334a45a8ff	1347
bogdanm	0:9b334a45a8ff	1348	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
bogdanm	0:9b334a45a8ff	1349	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
bogdanm	0:9b334a45a8ff	1350	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
bogdanm	0:9b334a45a8ff	1351	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
bogdanm	0:9b334a45a8ff	1352	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
bogdanm	0:9b334a45a8ff	1353	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
bogdanm	0:9b334a45a8ff	1354	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
bogdanm	0:9b334a45a8ff	1355	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
bogdanm	0:9b334a45a8ff	1356	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
bogdanm	0:9b334a45a8ff	1357	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
bogdanm	0:9b334a45a8ff	1358	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
bogdanm	0:9b334a45a8ff	1359	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
bogdanm	0:9b334a45a8ff	1360	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
bogdanm	0:9b334a45a8ff	1361	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363
bogdanm	0:9b334a45a8ff	1364	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
bogdanm	0:9b334a45a8ff	1365	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
bogdanm	0:9b334a45a8ff	1366	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
bogdanm	0:9b334a45a8ff	1367	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
bogdanm	0:9b334a45a8ff	1368	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
bogdanm	0:9b334a45a8ff	1369	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
bogdanm	0:9b334a45a8ff	1370	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
bogdanm	0:9b334a45a8ff	1371	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
bogdanm	0:9b334a45a8ff	1372	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
bogdanm	0:9b334a45a8ff	1373	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
bogdanm	0:9b334a45a8ff	1374	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
bogdanm	0:9b334a45a8ff	1375	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
bogdanm	0:9b334a45a8ff	1376	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
bogdanm	0:9b334a45a8ff	1377	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
bogdanm	0:9b334a45a8ff	1378	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
bogdanm	0:9b334a45a8ff	1379	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
bogdanm	0:9b334a45a8ff	1380	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
bogdanm	0:9b334a45a8ff	1381	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
bogdanm	0:9b334a45a8ff	1382	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
bogdanm	0:9b334a45a8ff	1383	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
bogdanm	0:9b334a45a8ff	1384	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
bogdanm	0:9b334a45a8ff	1385	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
bogdanm	0:9b334a45a8ff	1386	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
bogdanm	0:9b334a45a8ff	1387	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
bogdanm	0:9b334a45a8ff	1388
bogdanm	0:9b334a45a8ff	1389	/**
bogdanm	0:9b334a45a8ff	1390	* @}
bogdanm	0:9b334a45a8ff	1391	*/
bogdanm	0:9b334a45a8ff	1392
bogdanm	0:9b334a45a8ff	1393	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1394	* @{
bogdanm	0:9b334a45a8ff	1395	*/
mbed_official	124:6a4a5b7d7324	1396	#if defined(STM32F3)
mbed_official	124:6a4a5b7d7324	1397	#define COMP_START __HAL_COMP_ENABLE
mbed_official	124:6a4a5b7d7324	1398	#define COMP_STOP __HAL_COMP_DISABLE
mbed_official	124:6a4a5b7d7324	1399	#define COMP_LOCK __HAL_COMP_LOCK
mbed_official	124:6a4a5b7d7324	1400
mbed_official	124:6a4a5b7d7324	1401	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	124:6a4a5b7d7324	1402	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1403	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1404	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
mbed_official	124:6a4a5b7d7324	1405	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1406	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1407	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
mbed_official	124:6a4a5b7d7324	1408	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1409	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1410	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
mbed_official	124:6a4a5b7d7324	1411	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1412	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1413	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
mbed_official	124:6a4a5b7d7324	1414	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1415	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1416	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
mbed_official	124:6a4a5b7d7324	1417	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1418	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1419	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
mbed_official	124:6a4a5b7d7324	1420	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1421	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1422	__HAL_COMP_COMP6_EXTI_GET_FLAG())
mbed_official	124:6a4a5b7d7324	1423	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1424	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1425	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
mbed_official	124:6a4a5b7d7324	1426	# endif
mbed_official	124:6a4a5b7d7324	1427	# if defined(STM32F302xE) \|\| defined(STM32F302xC)
mbed_official	124:6a4a5b7d7324	1428	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1429	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1430	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1431	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
mbed_official	124:6a4a5b7d7324	1432	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1433	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1434	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1435	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
mbed_official	124:6a4a5b7d7324	1436	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1437	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1438	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1439	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
mbed_official	124:6a4a5b7d7324	1440	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1441	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1442	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1443	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
mbed_official	124:6a4a5b7d7324	1444	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1445	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1446	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1447	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
mbed_official	124:6a4a5b7d7324	1448	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1449	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1450	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1451	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
mbed_official	124:6a4a5b7d7324	1452	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1453	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1454	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1455	__HAL_COMP_COMP6_EXTI_GET_FLAG())
mbed_official	124:6a4a5b7d7324	1456	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1457	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1458	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1459	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
mbed_official	124:6a4a5b7d7324	1460	# endif
mbed_official	124:6a4a5b7d7324	1461	# if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	124:6a4a5b7d7324	1462	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1463	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1464	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1465	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1466	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1467	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1468	__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
mbed_official	124:6a4a5b7d7324	1469	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1470	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1471	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1472	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1473	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1474	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1475	__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
mbed_official	124:6a4a5b7d7324	1476	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1477	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1478	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1479	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1480	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1481	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1482	__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
mbed_official	124:6a4a5b7d7324	1483	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1484	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1485	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1486	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1487	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1488	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1489	__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
mbed_official	124:6a4a5b7d7324	1490	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1491	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1492	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1493	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1494	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1495	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1496	__HAL_COMP_COMP7_EXTI_ENABLE_IT())
mbed_official	124:6a4a5b7d7324	1497	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1498	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1499	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1500	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1501	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1502	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1503	__HAL_COMP_COMP7_EXTI_DISABLE_IT())
mbed_official	124:6a4a5b7d7324	1504	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1505	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1506	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1507	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1508	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1509	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1510	__HAL_COMP_COMP7_EXTI_GET_FLAG())
mbed_official	124:6a4a5b7d7324	1511	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1512	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1513	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1514	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1515	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1516	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1517	__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
mbed_official	124:6a4a5b7d7324	1518	# endif
mbed_official	124:6a4a5b7d7324	1519	# if defined(STM32F373xC) \|\|defined(STM32F378xx)
bogdanm	0:9b334a45a8ff	1520	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
bogdanm	0:9b334a45a8ff	1521	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
mbed_official	124:6a4a5b7d7324	1522	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
bogdanm	0:9b334a45a8ff	1523	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
bogdanm	0:9b334a45a8ff	1524	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
bogdanm	0:9b334a45a8ff	1525	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
mbed_official	124:6a4a5b7d7324	1526	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
bogdanm	0:9b334a45a8ff	1527	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
mbed_official	124:6a4a5b7d7324	1528	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
bogdanm	0:9b334a45a8ff	1529	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
mbed_official	124:6a4a5b7d7324	1530	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
bogdanm	0:9b334a45a8ff	1531	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
mbed_official	124:6a4a5b7d7324	1532	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
bogdanm	0:9b334a45a8ff	1533	__HAL_COMP_COMP2_EXTI_GET_FLAG())
mbed_official	124:6a4a5b7d7324	1534	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
bogdanm	0:9b334a45a8ff	1535	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
mbed_official	124:6a4a5b7d7324	1536	# endif
mbed_official	124:6a4a5b7d7324	1537	#else
mbed_official	124:6a4a5b7d7324	1538	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1539	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
mbed_official	124:6a4a5b7d7324	1540	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1541	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
mbed_official	124:6a4a5b7d7324	1542	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1543	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
mbed_official	124:6a4a5b7d7324	1544	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
mbed_official	124:6a4a5b7d7324	1545	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
mbed_official	124:6a4a5b7d7324	1546	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1547	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
mbed_official	124:6a4a5b7d7324	1548	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	1549	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
mbed_official	124:6a4a5b7d7324	1550	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	1551	__HAL_COMP_COMP2_EXTI_GET_FLAG())
mbed_official	124:6a4a5b7d7324	1552	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	1553	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
mbed_official	124:6a4a5b7d7324	1554	#endif
mbed_official	124:6a4a5b7d7324	1555
bogdanm	0:9b334a45a8ff	1556	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
bogdanm	0:9b334a45a8ff	1557
mbed_official	124:6a4a5b7d7324	1558	#if defined(STM32L0) \|\| defined(STM32L4)
mbed_official	124:6a4a5b7d7324	1559	/* Note: On these STM32 families, the only argument of this macro */
mbed_official	124:6a4a5b7d7324	1560	/* is COMP_FLAG_LOCK. */
mbed_official	124:6a4a5b7d7324	1561	/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
mbed_official	124:6a4a5b7d7324	1562	/* argument. */
mbed_official	124:6a4a5b7d7324	1563	#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
mbed_official	124:6a4a5b7d7324	1564	#endif
mbed_official	124:6a4a5b7d7324	1565	/**
mbed_official	124:6a4a5b7d7324	1566	* @}
mbed_official	124:6a4a5b7d7324	1567	*/
mbed_official	124:6a4a5b7d7324	1568
mbed_official	124:6a4a5b7d7324	1569	#if defined(STM32L0) \|\| defined(STM32L4)
mbed_official	124:6a4a5b7d7324	1570	/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
mbed_official	124:6a4a5b7d7324	1571	* @{
mbed_official	124:6a4a5b7d7324	1572	*/
mbed_official	124:6a4a5b7d7324	1573	#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
mbed_official	124:6a4a5b7d7324	1574	#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
mbed_official	124:6a4a5b7d7324	1575	/**
mbed_official	124:6a4a5b7d7324	1576	* @}
mbed_official	124:6a4a5b7d7324	1577	*/
mbed_official	124:6a4a5b7d7324	1578	#endif
mbed_official	124:6a4a5b7d7324	1579
mbed_official	124:6a4a5b7d7324	1580	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
mbed_official	124:6a4a5b7d7324	1581	* @{
mbed_official	124:6a4a5b7d7324	1582	*/
mbed_official	124:6a4a5b7d7324	1583
mbed_official	124:6a4a5b7d7324	1584	#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) \|\| \
mbed_official	124:6a4a5b7d7324	1585	((WAVE) == DAC_WAVE_NOISE)\|\| \
mbed_official	124:6a4a5b7d7324	1586	((WAVE) == DAC_WAVE_TRIANGLE))
mbed_official	124:6a4a5b7d7324	1587
bogdanm	0:9b334a45a8ff	1588	/**
bogdanm	0:9b334a45a8ff	1589	* @}
bogdanm	0:9b334a45a8ff	1590	*/
bogdanm	0:9b334a45a8ff	1591
bogdanm	0:9b334a45a8ff	1592	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1593	* @{
bogdanm	0:9b334a45a8ff	1594	*/
bogdanm	0:9b334a45a8ff	1595
bogdanm	0:9b334a45a8ff	1596	#define IS_WRPAREA IS_OB_WRPAREA
bogdanm	0:9b334a45a8ff	1597	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
bogdanm	0:9b334a45a8ff	1598	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
bogdanm	0:9b334a45a8ff	1599	#define IS_TYPEERASE IS_FLASH_TYPEERASE
mbed_official	124:6a4a5b7d7324	1600	#define IS_NBSECTORS IS_FLASH_NBSECTORS
mbed_official	124:6a4a5b7d7324	1601	#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	/**
bogdanm	0:9b334a45a8ff	1604	* @}
bogdanm	0:9b334a45a8ff	1605	*/
bogdanm	0:9b334a45a8ff	1606
bogdanm	0:9b334a45a8ff	1607	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1608	* @{
bogdanm	0:9b334a45a8ff	1609	*/
bogdanm	0:9b334a45a8ff	1610
bogdanm	0:9b334a45a8ff	1611	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
bogdanm	0:9b334a45a8ff	1612	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
bogdanm	0:9b334a45a8ff	1613	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
bogdanm	0:9b334a45a8ff	1614	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
bogdanm	0:9b334a45a8ff	1615	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
bogdanm	0:9b334a45a8ff	1616	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
bogdanm	0:9b334a45a8ff	1617	#define __HAL_I2C_SPEED I2C_SPEED
bogdanm	0:9b334a45a8ff	1618	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
bogdanm	0:9b334a45a8ff	1619	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
bogdanm	0:9b334a45a8ff	1620	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
bogdanm	0:9b334a45a8ff	1621	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
bogdanm	0:9b334a45a8ff	1622	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
bogdanm	0:9b334a45a8ff	1623	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
bogdanm	0:9b334a45a8ff	1624	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
bogdanm	0:9b334a45a8ff	1625	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
bogdanm	0:9b334a45a8ff	1626	/**
bogdanm	0:9b334a45a8ff	1627	* @}
bogdanm	0:9b334a45a8ff	1628	*/
bogdanm	0:9b334a45a8ff	1629
bogdanm	0:9b334a45a8ff	1630	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1631	* @{
bogdanm	0:9b334a45a8ff	1632	*/
bogdanm	0:9b334a45a8ff	1633
bogdanm	0:9b334a45a8ff	1634	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
bogdanm	0:9b334a45a8ff	1635	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
bogdanm	0:9b334a45a8ff	1636
bogdanm	0:9b334a45a8ff	1637	/**
bogdanm	0:9b334a45a8ff	1638	* @}
bogdanm	0:9b334a45a8ff	1639	*/
bogdanm	0:9b334a45a8ff	1640
bogdanm	0:9b334a45a8ff	1641	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1642	* @{
bogdanm	0:9b334a45a8ff	1643	*/
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
bogdanm	0:9b334a45a8ff	1646	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
bogdanm	0:9b334a45a8ff	1647
bogdanm	0:9b334a45a8ff	1648	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1649	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	1650	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1651	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	1652
bogdanm	0:9b334a45a8ff	1653	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	1654
bogdanm	0:9b334a45a8ff	1655
bogdanm	0:9b334a45a8ff	1656	/**
bogdanm	0:9b334a45a8ff	1657	* @}
bogdanm	0:9b334a45a8ff	1658	*/
bogdanm	0:9b334a45a8ff	1659
bogdanm	0:9b334a45a8ff	1660
bogdanm	0:9b334a45a8ff	1661	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1662	* @{
bogdanm	0:9b334a45a8ff	1663	*/
bogdanm	0:9b334a45a8ff	1664	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
bogdanm	0:9b334a45a8ff	1665	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
bogdanm	0:9b334a45a8ff	1666	/**
bogdanm	0:9b334a45a8ff	1667	* @}
bogdanm	0:9b334a45a8ff	1668	*/
bogdanm	0:9b334a45a8ff	1669
bogdanm	0:9b334a45a8ff	1670
bogdanm	0:9b334a45a8ff	1671	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1672	* @{
bogdanm	0:9b334a45a8ff	1673	*/
bogdanm	0:9b334a45a8ff	1674
bogdanm	0:9b334a45a8ff	1675	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
bogdanm	0:9b334a45a8ff	1676	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
bogdanm	0:9b334a45a8ff	1677	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
bogdanm	0:9b334a45a8ff	1678
bogdanm	0:9b334a45a8ff	1679	/**
bogdanm	0:9b334a45a8ff	1680	* @}
bogdanm	0:9b334a45a8ff	1681	*/
mbed_official	124:6a4a5b7d7324	1682
mbed_official	124:6a4a5b7d7324	1683
mbed_official	124:6a4a5b7d7324	1684	/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
mbed_official	124:6a4a5b7d7324	1685	* @{
mbed_official	124:6a4a5b7d7324	1686	*/
mbed_official	124:6a4a5b7d7324	1687	#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
mbed_official	124:6a4a5b7d7324	1688	#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
mbed_official	124:6a4a5b7d7324	1689	#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
mbed_official	124:6a4a5b7d7324	1690	#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
mbed_official	124:6a4a5b7d7324	1691	#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
mbed_official	124:6a4a5b7d7324	1692	#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
mbed_official	124:6a4a5b7d7324	1693	#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
mbed_official	124:6a4a5b7d7324	1694	#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
mbed_official	124:6a4a5b7d7324	1695	#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
mbed_official	124:6a4a5b7d7324	1696	#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
mbed_official	124:6a4a5b7d7324	1697	#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
mbed_official	124:6a4a5b7d7324	1698	#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
mbed_official	124:6a4a5b7d7324	1699	#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
mbed_official	124:6a4a5b7d7324	1700
mbed_official	124:6a4a5b7d7324	1701	/**
mbed_official	124:6a4a5b7d7324	1702	* @}
mbed_official	124:6a4a5b7d7324	1703	*/
mbed_official	124:6a4a5b7d7324	1704
bogdanm	0:9b334a45a8ff	1705
bogdanm	0:9b334a45a8ff	1706	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1707	* @{
bogdanm	0:9b334a45a8ff	1708	*/
bogdanm	0:9b334a45a8ff	1709	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
bogdanm	0:9b334a45a8ff	1710	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
bogdanm	0:9b334a45a8ff	1711	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1712	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1713	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1714	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1715	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
bogdanm	0:9b334a45a8ff	1716	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
bogdanm	0:9b334a45a8ff	1717	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
bogdanm	0:9b334a45a8ff	1718	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
bogdanm	0:9b334a45a8ff	1719	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
bogdanm	0:9b334a45a8ff	1720	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
bogdanm	0:9b334a45a8ff	1721	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
bogdanm	0:9b334a45a8ff	1722	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
bogdanm	0:9b334a45a8ff	1723	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
bogdanm	0:9b334a45a8ff	1724	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
mbed_official	124:6a4a5b7d7324	1725	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
bogdanm	0:9b334a45a8ff	1726	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
bogdanm	0:9b334a45a8ff	1727	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
bogdanm	0:9b334a45a8ff	1728	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1729	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1730	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1731	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1732	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1733	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
mbed_official	124:6a4a5b7d7324	1734	#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
mbed_official	124:6a4a5b7d7324	1735	#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
bogdanm	0:9b334a45a8ff	1736	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
bogdanm	0:9b334a45a8ff	1737	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
bogdanm	0:9b334a45a8ff	1738	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
bogdanm	0:9b334a45a8ff	1739	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
bogdanm	0:9b334a45a8ff	1740	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1741	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1742	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
bogdanm	0:9b334a45a8ff	1743	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
bogdanm	0:9b334a45a8ff	1744
bogdanm	0:9b334a45a8ff	1745	#if defined (STM32F4)
bogdanm	0:9b334a45a8ff	1746	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
bogdanm	0:9b334a45a8ff	1747	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
bogdanm	0:9b334a45a8ff	1748	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
bogdanm	0:9b334a45a8ff	1749	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
bogdanm	0:9b334a45a8ff	1750	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
bogdanm	0:9b334a45a8ff	1751	#else
bogdanm	0:9b334a45a8ff	1752	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	1753	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	1754	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	1755	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
bogdanm	0:9b334a45a8ff	1756	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	1757	#endif /* STM32F4 */
bogdanm	0:9b334a45a8ff	1758	/**
bogdanm	0:9b334a45a8ff	1759	* @}
bogdanm	0:9b334a45a8ff	1760	*/
bogdanm	0:9b334a45a8ff	1761
bogdanm	0:9b334a45a8ff	1762
mbed_official	124:6a4a5b7d7324	1763	/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1764	* @{
bogdanm	0:9b334a45a8ff	1765	*/
mbed_official	124:6a4a5b7d7324	1766
mbed_official	124:6a4a5b7d7324	1767	#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
mbed_official	124:6a4a5b7d7324	1768	#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
mbed_official	124:6a4a5b7d7324	1769
mbed_official	124:6a4a5b7d7324	1770	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
mbed_official	124:6a4a5b7d7324	1771	#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
mbed_official	124:6a4a5b7d7324	1772
bogdanm	0:9b334a45a8ff	1773	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1774	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1775	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1776	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1777	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1778	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	1779	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	1780	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	1781	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
mbed_official	124:6a4a5b7d7324	1782	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	1783	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	1784	#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1785	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1786	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1787	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1788	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1789	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1790	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1791	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1792	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1793	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1794	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1795	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1796	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1797	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
bogdanm	0:9b334a45a8ff	1798	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1799	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1800	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1801	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1802	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1803	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
bogdanm	0:9b334a45a8ff	1804	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1805	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1806	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1807	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
bogdanm	0:9b334a45a8ff	1808	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1809	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
bogdanm	0:9b334a45a8ff	1810	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1811	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1812	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1813	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1814	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1815	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1816	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1817	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1818	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1819	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1820	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1821	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1822	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1823	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
bogdanm	0:9b334a45a8ff	1824	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1825	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1826	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1827	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1828	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1829	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1830	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	1831	#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	1832	#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	1833	#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
mbed_official	124:6a4a5b7d7324	1834	#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1835	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1836	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1837	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1838	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1839	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1840	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	1841	#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	1842	#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	1843	#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
mbed_official	124:6a4a5b7d7324	1844	#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	1845	#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	1846	#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1847	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1848	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1849	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1850	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1851	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1852	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1853	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1854	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1855	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1856	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1857	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1858	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1859	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1860	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1861	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1862	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1863	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1864	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	1865	#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	1866	#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	1867	#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
mbed_official	124:6a4a5b7d7324	1868	#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1869	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1870	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1871	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1872	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1873	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
bogdanm	0:9b334a45a8ff	1874	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1875	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1876	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1877	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1878	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1879	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1880	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1881	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1882	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1883	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1884	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1885	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1886	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1887	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1888	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1889	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1890	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1891	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1892	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1893	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1894	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1895	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1896	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1897	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1898	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1899	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1900	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1901	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
bogdanm	0:9b334a45a8ff	1902	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	1903	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	1904	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	1905	#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
mbed_official	124:6a4a5b7d7324	1906	#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	1907	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	1908	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1909	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1910	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1911	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1912	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1913	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1914	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1915	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1916	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1917	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1918	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1919	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1920	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1921	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
bogdanm	0:9b334a45a8ff	1922	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1923	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1924	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1925	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1926	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1927	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
bogdanm	0:9b334a45a8ff	1928	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1929	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1930	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1931	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1932	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1933	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1934	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1935	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1936	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1937	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1938	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1939	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
bogdanm	0:9b334a45a8ff	1940	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1941	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1942	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1943	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1944	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1945	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
bogdanm	0:9b334a45a8ff	1946	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1947	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1948	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1949	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1950	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1951	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
bogdanm	0:9b334a45a8ff	1952	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1953	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1954	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1955	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1956	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1957	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
bogdanm	0:9b334a45a8ff	1958	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1959	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1960	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1961	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1962	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1963	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
bogdanm	0:9b334a45a8ff	1964	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1965	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1966	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1967	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1968	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1969	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1970	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1971	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1972	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1973	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1974	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1975	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1976	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1977	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1978	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1979	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1980	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1981	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1982	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1983	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1984	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1985	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1986	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1987	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
bogdanm	0:9b334a45a8ff	1988	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1989	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1990	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1991	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1992	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1993	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1994	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1995	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1996	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1997	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1998	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1999	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
bogdanm	0:9b334a45a8ff	2000	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2001	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2002	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2003	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2004	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2005	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
bogdanm	0:9b334a45a8ff	2006	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2007	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2008	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2009	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2010	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2011	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
bogdanm	0:9b334a45a8ff	2012	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2013	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2014	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2015	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2016	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2017	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
bogdanm	0:9b334a45a8ff	2018	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2019	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2020	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2021	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2022	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2023	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
bogdanm	0:9b334a45a8ff	2024	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2025	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2026	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2027	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2028	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2029	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
bogdanm	0:9b334a45a8ff	2030	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2031	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2032	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2033	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2034	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2035	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
bogdanm	0:9b334a45a8ff	2036	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2037	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2038	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2039	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2040	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2041	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
bogdanm	0:9b334a45a8ff	2042	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2043	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2044	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2045	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2046	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2047	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
bogdanm	0:9b334a45a8ff	2048	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2049	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2050	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2051	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2052	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2053	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2054	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2055	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
bogdanm	0:9b334a45a8ff	2056	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2057	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2058	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2059	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2060	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2061	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
bogdanm	0:9b334a45a8ff	2062	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2063	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2064	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2065	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2066	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2067	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
bogdanm	0:9b334a45a8ff	2068	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2069	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2070	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2071	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2072	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2073	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
bogdanm	0:9b334a45a8ff	2074	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2075	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2076	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2077	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2078	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2079	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2080	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2081	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2082	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2083	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2084	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2085	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
bogdanm	0:9b334a45a8ff	2086	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2087	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2088	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2089	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2090	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2091	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
bogdanm	0:9b334a45a8ff	2092	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2093	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2094	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2095	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2096	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2097	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
bogdanm	0:9b334a45a8ff	2098	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2099	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2100	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2101	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
bogdanm	0:9b334a45a8ff	2102	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2103	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2104	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2105	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
bogdanm	0:9b334a45a8ff	2106	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2107	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2108	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2109	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
bogdanm	0:9b334a45a8ff	2110	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2111	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2112	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2113	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
bogdanm	0:9b334a45a8ff	2114	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2115	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2116	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2117	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
bogdanm	0:9b334a45a8ff	2118	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2119	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2120	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2121	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2122	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2123	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
bogdanm	0:9b334a45a8ff	2124	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2125	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2126	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2127	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2128	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2129	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
bogdanm	0:9b334a45a8ff	2130	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2131	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2132	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2133	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2134	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2135	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
bogdanm	0:9b334a45a8ff	2136	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2137	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2138	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2139	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2140	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2141	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
bogdanm	0:9b334a45a8ff	2142	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2143	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2144	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2145	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2146	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2147	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
bogdanm	0:9b334a45a8ff	2148	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2149	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2150	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2151	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2152	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2153	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
bogdanm	0:9b334a45a8ff	2154	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2155	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2156	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2157	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2158	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2159	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
bogdanm	0:9b334a45a8ff	2160	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2161	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2162	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2163	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2164	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2165	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
bogdanm	0:9b334a45a8ff	2166	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2167	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2168	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2169	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2170	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2171	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
bogdanm	0:9b334a45a8ff	2172	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2173	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2174	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2175	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2176	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2177	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
bogdanm	0:9b334a45a8ff	2178	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2179	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2180	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2181	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
bogdanm	0:9b334a45a8ff	2182	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2183	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2184	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2185	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2186	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2187	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
bogdanm	0:9b334a45a8ff	2188	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2189	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2190	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2191	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2192	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2193	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
bogdanm	0:9b334a45a8ff	2194	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2195	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2196	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2197	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2198	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2199	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
bogdanm	0:9b334a45a8ff	2200	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2201	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2202	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2203	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2204	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2205	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
bogdanm	0:9b334a45a8ff	2206	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2207	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2208	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2209	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2210	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2211	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
bogdanm	0:9b334a45a8ff	2212	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2213	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2214	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2215	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2216	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2217	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
bogdanm	0:9b334a45a8ff	2218	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2219	#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2220	#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2221	#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2222	#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2223	#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2224	#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2225	#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2226	#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2227	#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2228	#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2229	#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2230	#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2231	#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2232	#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2233	#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2234	#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2235	#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2236	#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2237	#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2238	#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2239	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2240	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2241	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2242	#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2243	#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2244	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2245	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2246	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2247	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2248	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2249	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2250	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2251	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
bogdanm	0:9b334a45a8ff	2252	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2253	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2254	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2255	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
bogdanm	0:9b334a45a8ff	2256	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2257	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2258	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2259	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2260	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2261	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
bogdanm	0:9b334a45a8ff	2262	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2263	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2264	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2265	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2266	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2267	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2268	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2269	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
bogdanm	0:9b334a45a8ff	2270	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2271	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
bogdanm	0:9b334a45a8ff	2272	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
bogdanm	0:9b334a45a8ff	2273
bogdanm	0:9b334a45a8ff	2274	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
bogdanm	0:9b334a45a8ff	2275	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2276	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2277	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2278	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2279	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2280	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2281	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2282	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2283	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2284	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2285	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2286	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2287	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2288	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2289	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2290	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2291	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2292	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2293	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
bogdanm	0:9b334a45a8ff	2294	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2295	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2296	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2297	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2298	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2299	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2300	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
bogdanm	0:9b334a45a8ff	2301	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2302	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2303	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2304	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2305	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2306	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
bogdanm	0:9b334a45a8ff	2307	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2308	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2309	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2310	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2311	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2312	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
bogdanm	0:9b334a45a8ff	2313	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2314	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2315	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2316	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2317	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2318	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2319	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2320	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2321	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2322	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2323	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2324	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2325	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2326	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2327	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2328	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2329	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2330	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2331	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2332	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2333	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2334	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2335	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
bogdanm	0:9b334a45a8ff	2336	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2337	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2338	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2339	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2340	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2341	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
bogdanm	0:9b334a45a8ff	2342	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2343	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2344	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2345	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2346	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2347	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
bogdanm	0:9b334a45a8ff	2348	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2349	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2350	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2351	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2352	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2353	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
bogdanm	0:9b334a45a8ff	2354	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2355	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2356	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2357	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2358	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2359	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2360	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2361	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2362	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2363	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2364	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2365	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2366	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
bogdanm	0:9b334a45a8ff	2367	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2368	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2369	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2370	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2371	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2372	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2373	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
bogdanm	0:9b334a45a8ff	2374	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2375	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2376	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
bogdanm	0:9b334a45a8ff	2377	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
bogdanm	0:9b334a45a8ff	2378	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
bogdanm	0:9b334a45a8ff	2379	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2380	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	2381	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2382	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2383	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2384	#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2385	#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2386	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2387	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2388	#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2389	#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2390	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
mbed_official	124:6a4a5b7d7324	2391	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
mbed_official	124:6a4a5b7d7324	2392	#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2393	#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2394	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2395	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2396	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
mbed_official	124:6a4a5b7d7324	2397	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
mbed_official	124:6a4a5b7d7324	2398	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2399	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2400	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2401	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2402	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2403	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2404	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2405	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2406	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2407	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2408	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2409	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2410	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2411	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2412	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2413	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2414	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2415	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2416	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2417	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2418	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
bogdanm	0:9b334a45a8ff	2419	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2420	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2421	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	2422
bogdanm	0:9b334a45a8ff	2423	/* alias define maintained for legacy */
bogdanm	0:9b334a45a8ff	2424	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
bogdanm	0:9b334a45a8ff	2425	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	2426
mbed_official	124:6a4a5b7d7324	2427	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2428	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2429	#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2430	#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2431	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2432	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2433	#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2434	#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2435	#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2436	#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2437	#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2438	#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2439	#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2440	#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2441	#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2442	#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2443	#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2444	#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2445	#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2446	#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2447	#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2448	#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2449
mbed_official	124:6a4a5b7d7324	2450	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2451	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2452	#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2453	#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2454	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2455	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2456	#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2457	#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2458	#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2459	#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2460	#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2461	#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2462	#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2463	#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2464	#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2465	#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2466	#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2467	#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2468	#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2469	#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2470	#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2471	#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2472
mbed_official	124:6a4a5b7d7324	2473	#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2474	#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2475	#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2476	#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2477	#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2478	#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2479	#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2480	#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2481	#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2482	#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2483	#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2484	#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2485	#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2486	#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2487	#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2488	#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2489	#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2490	#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2491	#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2492	#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2493	#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2494	#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2495	#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2496	#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2497	#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2498	#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2499	#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2500	#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2501	#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2502	#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2503	#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2504	#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2505	#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2506	#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2507	#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2508	#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2509	#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2510	#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2511	#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2512	#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2513	#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2514	#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2515	#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2516	#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2517	#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2518	#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2519	#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2520	#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2521	#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2522	#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2523	#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2524	#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2525	#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2526	#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2527	#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2528	#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2529	#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2530	#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2531	#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2532	#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2533	#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2534	#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2535	#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2536	#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2537	#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2538	#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2539	#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2540	#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2541	#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2542	#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2543	#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2544	#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2545	#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2546	#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2547	#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2548	#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2549	#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2550	#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2551	#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2552	#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2553	#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2554	#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2555	#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2556	#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2557	#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2558	#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2559	#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2560	#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2561	#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2562	#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2563	#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2564	#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2565	#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2566	#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2567	#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2568	#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2569	#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2570	#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2571	#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2572	#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2573	#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2574	#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2575	#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2576	#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2577	#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2578	#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2579	#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2580	#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2581	#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2582	#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2583	#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2584	#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2585	#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2586	#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2587	#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2588	#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2589
mbed_official	124:6a4a5b7d7324	2590	#if defined(STM32F4)
mbed_official	124:6a4a5b7d7324	2591	#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2592	#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2593	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2594	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2595	#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2596	#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2597	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2598	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2599	#define Sdmmc1ClockSelection SdioClockSelection
mbed_official	124:6a4a5b7d7324	2600	#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
mbed_official	124:6a4a5b7d7324	2601	#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
mbed_official	124:6a4a5b7d7324	2602	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
mbed_official	124:6a4a5b7d7324	2603	#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
mbed_official	124:6a4a5b7d7324	2604	#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
mbed_official	124:6a4a5b7d7324	2605	#endif
mbed_official	124:6a4a5b7d7324	2606
mbed_official	124:6a4a5b7d7324	2607	#if defined(STM32F7) \|\| defined(STM32L4)
mbed_official	124:6a4a5b7d7324	2608	#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2609	#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2610	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2611	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2612	#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2613	#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2614	#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2615	#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2616	#define SdioClockSelection Sdmmc1ClockSelection
mbed_official	124:6a4a5b7d7324	2617	#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
mbed_official	124:6a4a5b7d7324	2618	#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
mbed_official	124:6a4a5b7d7324	2619	#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
mbed_official	124:6a4a5b7d7324	2620	#endif
mbed_official	124:6a4a5b7d7324	2621
mbed_official	124:6a4a5b7d7324	2622	#if defined(STM32F7)
mbed_official	124:6a4a5b7d7324	2623	#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
mbed_official	124:6a4a5b7d7324	2624	#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
mbed_official	124:6a4a5b7d7324	2625	#endif
mbed_official	124:6a4a5b7d7324	2626
bogdanm	0:9b334a45a8ff	2627	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
bogdanm	0:9b334a45a8ff	2628	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
bogdanm	0:9b334a45a8ff	2629
mbed_official	124:6a4a5b7d7324	2630	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
mbed_official	124:6a4a5b7d7324	2631
mbed_official	124:6a4a5b7d7324	2632	#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
mbed_official	124:6a4a5b7d7324	2633	#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
mbed_official	124:6a4a5b7d7324	2634	#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
mbed_official	124:6a4a5b7d7324	2635	#define IS_RCC_HCLK_DIV IS_RCC_PCLK
mbed_official	124:6a4a5b7d7324	2636	#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
mbed_official	124:6a4a5b7d7324	2637
mbed_official	124:6a4a5b7d7324	2638	#define RCC_IT_HSI14 RCC_IT_HSI14RDY
mbed_official	124:6a4a5b7d7324	2639
mbed_official	124:6a4a5b7d7324	2640	#if defined(STM32L0)
mbed_official	124:6a4a5b7d7324	2641	#define RCC_IT_LSECSS RCC_IT_CSSLSE
mbed_official	124:6a4a5b7d7324	2642	#define RCC_IT_CSS RCC_IT_CSSHSE
mbed_official	124:6a4a5b7d7324	2643	#endif
mbed_official	124:6a4a5b7d7324	2644
mbed_official	124:6a4a5b7d7324	2645	#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
mbed_official	124:6a4a5b7d7324	2646	#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
mbed_official	124:6a4a5b7d7324	2647	#define RCC_MCO_NODIV RCC_MCODIV_1
mbed_official	124:6a4a5b7d7324	2648	#define RCC_MCO_DIV1 RCC_MCODIV_1
mbed_official	124:6a4a5b7d7324	2649	#define RCC_MCO_DIV2 RCC_MCODIV_2
mbed_official	124:6a4a5b7d7324	2650	#define RCC_MCO_DIV4 RCC_MCODIV_4
mbed_official	124:6a4a5b7d7324	2651	#define RCC_MCO_DIV8 RCC_MCODIV_8
mbed_official	124:6a4a5b7d7324	2652	#define RCC_MCO_DIV16 RCC_MCODIV_16
mbed_official	124:6a4a5b7d7324	2653	#define RCC_MCO_DIV32 RCC_MCODIV_32
mbed_official	124:6a4a5b7d7324	2654	#define RCC_MCO_DIV64 RCC_MCODIV_64
mbed_official	124:6a4a5b7d7324	2655	#define RCC_MCO_DIV128 RCC_MCODIV_128
mbed_official	124:6a4a5b7d7324	2656	#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
mbed_official	124:6a4a5b7d7324	2657	#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
mbed_official	124:6a4a5b7d7324	2658	#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
mbed_official	124:6a4a5b7d7324	2659	#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
mbed_official	124:6a4a5b7d7324	2660	#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
mbed_official	124:6a4a5b7d7324	2661	#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
mbed_official	124:6a4a5b7d7324	2662	#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
mbed_official	124:6a4a5b7d7324	2663	#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
mbed_official	124:6a4a5b7d7324	2664	#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
mbed_official	124:6a4a5b7d7324	2665	#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
mbed_official	124:6a4a5b7d7324	2666	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
mbed_official	124:6a4a5b7d7324	2667
mbed_official	124:6a4a5b7d7324	2668	#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
mbed_official	124:6a4a5b7d7324	2669
mbed_official	124:6a4a5b7d7324	2670	#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
mbed_official	124:6a4a5b7d7324	2671	#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
mbed_official	124:6a4a5b7d7324	2672	#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
mbed_official	124:6a4a5b7d7324	2673	#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
mbed_official	124:6a4a5b7d7324	2674	#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
mbed_official	124:6a4a5b7d7324	2675	#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
mbed_official	124:6a4a5b7d7324	2676	#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
mbed_official	124:6a4a5b7d7324	2677	#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
bogdanm	0:9b334a45a8ff	2678
bogdanm	0:9b334a45a8ff	2679	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2680	#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2681	#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2682	#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2683	#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2684	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2685	#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2686	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2687	#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2688	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2689	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2690	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2691	#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2692	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2693	#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2694	#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2695	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2696	#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2697	#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2698	#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2699	#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2700	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2701	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2702	#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2703	#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
mbed_official	124:6a4a5b7d7324	2704	#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
bogdanm	0:9b334a45a8ff	2705	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
bogdanm	0:9b334a45a8ff	2706	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
bogdanm	0:9b334a45a8ff	2707	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
bogdanm	0:9b334a45a8ff	2708	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
bogdanm	0:9b334a45a8ff	2709	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	2710	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	2711
bogdanm	0:9b334a45a8ff	2712	#define CR_HSION_BB RCC_CR_HSION_BB
bogdanm	0:9b334a45a8ff	2713	#define CR_CSSON_BB RCC_CR_CSSON_BB
bogdanm	0:9b334a45a8ff	2714	#define CR_PLLON_BB RCC_CR_PLLON_BB
bogdanm	0:9b334a45a8ff	2715	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
mbed_official	124:6a4a5b7d7324	2716	#define CR_MSION_BB RCC_CR_MSION_BB
mbed_official	124:6a4a5b7d7324	2717	#define CSR_LSION_BB RCC_CSR_LSION_BB
mbed_official	124:6a4a5b7d7324	2718	#define CSR_LSEON_BB RCC_CSR_LSEON_BB
mbed_official	124:6a4a5b7d7324	2719	#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
mbed_official	124:6a4a5b7d7324	2720	#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
mbed_official	124:6a4a5b7d7324	2721	#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
bogdanm	0:9b334a45a8ff	2722	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
bogdanm	0:9b334a45a8ff	2723	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
bogdanm	0:9b334a45a8ff	2724	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
mbed_official	124:6a4a5b7d7324	2725	#define CR_HSEON_BB RCC_CR_HSEON_BB
mbed_official	124:6a4a5b7d7324	2726	#define CSR_RMVF_BB RCC_CSR_RMVF_BB
bogdanm	0:9b334a45a8ff	2727	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
bogdanm	0:9b334a45a8ff	2728	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
bogdanm	0:9b334a45a8ff	2729
mbed_official	124:6a4a5b7d7324	2730	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
mbed_official	124:6a4a5b7d7324	2731	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
mbed_official	124:6a4a5b7d7324	2732	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
mbed_official	124:6a4a5b7d7324	2733	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
mbed_official	124:6a4a5b7d7324	2734	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
mbed_official	124:6a4a5b7d7324	2735
mbed_official	124:6a4a5b7d7324	2736	#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
mbed_official	124:6a4a5b7d7324	2737
mbed_official	124:6a4a5b7d7324	2738	#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
mbed_official	124:6a4a5b7d7324	2739	#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
mbed_official	124:6a4a5b7d7324	2740
mbed_official	124:6a4a5b7d7324	2741	#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
mbed_official	124:6a4a5b7d7324	2742	#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
mbed_official	124:6a4a5b7d7324	2743	#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
mbed_official	124:6a4a5b7d7324	2744	#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
mbed_official	124:6a4a5b7d7324	2745	#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
mbed_official	124:6a4a5b7d7324	2746	#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
mbed_official	124:6a4a5b7d7324	2747
mbed_official	124:6a4a5b7d7324	2748	#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
mbed_official	124:6a4a5b7d7324	2749	#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
mbed_official	124:6a4a5b7d7324	2750	#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
mbed_official	124:6a4a5b7d7324	2751	#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
mbed_official	124:6a4a5b7d7324	2752	#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
mbed_official	124:6a4a5b7d7324	2753	#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
mbed_official	124:6a4a5b7d7324	2754	#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
mbed_official	124:6a4a5b7d7324	2755	#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
mbed_official	124:6a4a5b7d7324	2756	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
mbed_official	124:6a4a5b7d7324	2757	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
mbed_official	124:6a4a5b7d7324	2758	#define DfsdmClockSelection Dfsdm1ClockSelection
mbed_official	124:6a4a5b7d7324	2759	#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
mbed_official	124:6a4a5b7d7324	2760	#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
mbed_official	124:6a4a5b7d7324	2761	#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
mbed_official	124:6a4a5b7d7324	2762	#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
mbed_official	124:6a4a5b7d7324	2763	#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
mbed_official	124:6a4a5b7d7324	2764
bogdanm	0:9b334a45a8ff	2765	/**
bogdanm	0:9b334a45a8ff	2766	* @}
bogdanm	0:9b334a45a8ff	2767	*/
bogdanm	0:9b334a45a8ff	2768
bogdanm	0:9b334a45a8ff	2769	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2770	* @{
bogdanm	0:9b334a45a8ff	2771	*/
mbed_official	124:6a4a5b7d7324	2772	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
bogdanm	0:9b334a45a8ff	2773
bogdanm	0:9b334a45a8ff	2774	/**
bogdanm	0:9b334a45a8ff	2775	* @}
bogdanm	0:9b334a45a8ff	2776	*/
bogdanm	0:9b334a45a8ff	2777
bogdanm	0:9b334a45a8ff	2778	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2779	* @{
bogdanm	0:9b334a45a8ff	2780	*/
bogdanm	0:9b334a45a8ff	2781
bogdanm	0:9b334a45a8ff	2782	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2783	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	2784	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	2785
mbed_official	124:6a4a5b7d7324	2786	#if defined (STM32F1)
bogdanm	0:9b334a45a8ff	2787	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
bogdanm	0:9b334a45a8ff	2788
bogdanm	0:9b334a45a8ff	2789	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
bogdanm	0:9b334a45a8ff	2790
bogdanm	0:9b334a45a8ff	2791	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
bogdanm	0:9b334a45a8ff	2792
bogdanm	0:9b334a45a8ff	2793	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
bogdanm	0:9b334a45a8ff	2794
bogdanm	0:9b334a45a8ff	2795	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
mbed_official	124:6a4a5b7d7324	2796	#else
mbed_official	124:6a4a5b7d7324	2797	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	2798	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
mbed_official	124:6a4a5b7d7324	2799	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
mbed_official	124:6a4a5b7d7324	2800	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	2801	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
mbed_official	124:6a4a5b7d7324	2802	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
mbed_official	124:6a4a5b7d7324	2803	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	2804	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
mbed_official	124:6a4a5b7d7324	2805	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
mbed_official	124:6a4a5b7d7324	2806	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	2807	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
mbed_official	124:6a4a5b7d7324	2808	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
mbed_official	124:6a4a5b7d7324	2809	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
mbed_official	124:6a4a5b7d7324	2810	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
mbed_official	124:6a4a5b7d7324	2811	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
mbed_official	124:6a4a5b7d7324	2812	#endif /* STM32F1 */
bogdanm	0:9b334a45a8ff	2813
bogdanm	0:9b334a45a8ff	2814	#define IS_ALARM IS_RTC_ALARM
bogdanm	0:9b334a45a8ff	2815	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
bogdanm	0:9b334a45a8ff	2816	#define IS_TAMPER IS_RTC_TAMPER
bogdanm	0:9b334a45a8ff	2817	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
bogdanm	0:9b334a45a8ff	2818	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
bogdanm	0:9b334a45a8ff	2819	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
bogdanm	0:9b334a45a8ff	2820	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
bogdanm	0:9b334a45a8ff	2821	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
bogdanm	0:9b334a45a8ff	2822	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
bogdanm	0:9b334a45a8ff	2823	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
bogdanm	0:9b334a45a8ff	2824	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
bogdanm	0:9b334a45a8ff	2825	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
bogdanm	0:9b334a45a8ff	2826	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
bogdanm	0:9b334a45a8ff	2827	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
bogdanm	0:9b334a45a8ff	2828
bogdanm	0:9b334a45a8ff	2829	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
bogdanm	0:9b334a45a8ff	2830	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
bogdanm	0:9b334a45a8ff	2831
bogdanm	0:9b334a45a8ff	2832	/**
bogdanm	0:9b334a45a8ff	2833	* @}
bogdanm	0:9b334a45a8ff	2834	*/
bogdanm	0:9b334a45a8ff	2835
bogdanm	0:9b334a45a8ff	2836	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2837	* @{
bogdanm	0:9b334a45a8ff	2838	*/
bogdanm	0:9b334a45a8ff	2839
bogdanm	0:9b334a45a8ff	2840	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
bogdanm	0:9b334a45a8ff	2841	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
mbed_official	124:6a4a5b7d7324	2842
mbed_official	124:6a4a5b7d7324	2843	#if defined(STM32F4)
mbed_official	124:6a4a5b7d7324	2844	#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
mbed_official	124:6a4a5b7d7324	2845	#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
mbed_official	124:6a4a5b7d7324	2846	#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
mbed_official	124:6a4a5b7d7324	2847	#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
mbed_official	124:6a4a5b7d7324	2848	#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
mbed_official	124:6a4a5b7d7324	2849	#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
mbed_official	124:6a4a5b7d7324	2850	#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
mbed_official	124:6a4a5b7d7324	2851	#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
mbed_official	124:6a4a5b7d7324	2852	#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
mbed_official	124:6a4a5b7d7324	2853	#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
mbed_official	124:6a4a5b7d7324	2854	#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
mbed_official	124:6a4a5b7d7324	2855	#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
mbed_official	124:6a4a5b7d7324	2856	#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
mbed_official	124:6a4a5b7d7324	2857	#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
mbed_official	124:6a4a5b7d7324	2858	#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
mbed_official	124:6a4a5b7d7324	2859	#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
mbed_official	124:6a4a5b7d7324	2860	#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
mbed_official	124:6a4a5b7d7324	2861	#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
mbed_official	124:6a4a5b7d7324	2862	#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
mbed_official	124:6a4a5b7d7324	2863	#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
mbed_official	124:6a4a5b7d7324	2864	/* alias CMSIS */
mbed_official	124:6a4a5b7d7324	2865	#define SDMMC1_IRQn SDIO_IRQn
mbed_official	124:6a4a5b7d7324	2866	#define SDMMC1_IRQHandler SDIO_IRQHandler
mbed_official	124:6a4a5b7d7324	2867	#endif
mbed_official	124:6a4a5b7d7324	2868
mbed_official	124:6a4a5b7d7324	2869	#if defined(STM32F7) \|\| defined(STM32L4)
mbed_official	124:6a4a5b7d7324	2870	#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
mbed_official	124:6a4a5b7d7324	2871	#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
mbed_official	124:6a4a5b7d7324	2872	#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
mbed_official	124:6a4a5b7d7324	2873	#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
mbed_official	124:6a4a5b7d7324	2874	#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
mbed_official	124:6a4a5b7d7324	2875	#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
mbed_official	124:6a4a5b7d7324	2876	#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
mbed_official	124:6a4a5b7d7324	2877	#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
mbed_official	124:6a4a5b7d7324	2878	#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
mbed_official	124:6a4a5b7d7324	2879	#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
mbed_official	124:6a4a5b7d7324	2880	#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
mbed_official	124:6a4a5b7d7324	2881	#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
mbed_official	124:6a4a5b7d7324	2882	#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
mbed_official	124:6a4a5b7d7324	2883	#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
mbed_official	124:6a4a5b7d7324	2884	#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
mbed_official	124:6a4a5b7d7324	2885	#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
mbed_official	124:6a4a5b7d7324	2886	#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
mbed_official	124:6a4a5b7d7324	2887	#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
mbed_official	124:6a4a5b7d7324	2888	#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
mbed_official	124:6a4a5b7d7324	2889	#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
mbed_official	124:6a4a5b7d7324	2890	/* alias CMSIS for compatibilities */
mbed_official	124:6a4a5b7d7324	2891	#define SDIO_IRQn SDMMC1_IRQn
mbed_official	124:6a4a5b7d7324	2892	#define SDIO_IRQHandler SDMMC1_IRQHandler
mbed_official	124:6a4a5b7d7324	2893	#endif
bogdanm	0:9b334a45a8ff	2894	/**
bogdanm	0:9b334a45a8ff	2895	* @}
bogdanm	0:9b334a45a8ff	2896	*/
bogdanm	0:9b334a45a8ff	2897
bogdanm	0:9b334a45a8ff	2898	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2899	* @{
bogdanm	0:9b334a45a8ff	2900	*/
bogdanm	0:9b334a45a8ff	2901
bogdanm	0:9b334a45a8ff	2902	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
bogdanm	0:9b334a45a8ff	2903	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
bogdanm	0:9b334a45a8ff	2904	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
bogdanm	0:9b334a45a8ff	2905	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
bogdanm	0:9b334a45a8ff	2906	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
bogdanm	0:9b334a45a8ff	2907	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
bogdanm	0:9b334a45a8ff	2908
bogdanm	0:9b334a45a8ff	2909	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2910	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2911
bogdanm	0:9b334a45a8ff	2912	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	2913
bogdanm	0:9b334a45a8ff	2914	/**
bogdanm	0:9b334a45a8ff	2915	* @}
bogdanm	0:9b334a45a8ff	2916	*/
bogdanm	0:9b334a45a8ff	2917
bogdanm	0:9b334a45a8ff	2918	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2919	* @{
bogdanm	0:9b334a45a8ff	2920	*/
bogdanm	0:9b334a45a8ff	2921	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
bogdanm	0:9b334a45a8ff	2922	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
bogdanm	0:9b334a45a8ff	2923	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
bogdanm	0:9b334a45a8ff	2924	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
bogdanm	0:9b334a45a8ff	2925	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
bogdanm	0:9b334a45a8ff	2926	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
bogdanm	0:9b334a45a8ff	2927	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
bogdanm	0:9b334a45a8ff	2928	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
bogdanm	0:9b334a45a8ff	2929	/**
bogdanm	0:9b334a45a8ff	2930	* @}
bogdanm	0:9b334a45a8ff	2931	*/
bogdanm	0:9b334a45a8ff	2932
bogdanm	0:9b334a45a8ff	2933	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2934	* @{
bogdanm	0:9b334a45a8ff	2935	*/
bogdanm	0:9b334a45a8ff	2936
bogdanm	0:9b334a45a8ff	2937	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
bogdanm	0:9b334a45a8ff	2938	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
bogdanm	0:9b334a45a8ff	2939	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
bogdanm	0:9b334a45a8ff	2940
bogdanm	0:9b334a45a8ff	2941	/**
bogdanm	0:9b334a45a8ff	2942	* @}
bogdanm	0:9b334a45a8ff	2943	*/
bogdanm	0:9b334a45a8ff	2944
bogdanm	0:9b334a45a8ff	2945	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2946	* @{
bogdanm	0:9b334a45a8ff	2947	*/
bogdanm	0:9b334a45a8ff	2948
bogdanm	0:9b334a45a8ff	2949	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2950	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	2951	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2952	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	2953
bogdanm	0:9b334a45a8ff	2954	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
bogdanm	0:9b334a45a8ff	2955
bogdanm	0:9b334a45a8ff	2956	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	2957	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	2958
bogdanm	0:9b334a45a8ff	2959	/**
bogdanm	0:9b334a45a8ff	2960	* @}
bogdanm	0:9b334a45a8ff	2961	*/
bogdanm	0:9b334a45a8ff	2962
bogdanm	0:9b334a45a8ff	2963
bogdanm	0:9b334a45a8ff	2964	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2965	* @{
bogdanm	0:9b334a45a8ff	2966	*/
bogdanm	0:9b334a45a8ff	2967
bogdanm	0:9b334a45a8ff	2968	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
bogdanm	0:9b334a45a8ff	2969	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
bogdanm	0:9b334a45a8ff	2970	#define __USART_ENABLE __HAL_USART_ENABLE
bogdanm	0:9b334a45a8ff	2971	#define __USART_DISABLE __HAL_USART_DISABLE
bogdanm	0:9b334a45a8ff	2972
bogdanm	0:9b334a45a8ff	2973	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2974	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	2975
bogdanm	0:9b334a45a8ff	2976	/**
bogdanm	0:9b334a45a8ff	2977	* @}
bogdanm	0:9b334a45a8ff	2978	*/
bogdanm	0:9b334a45a8ff	2979
bogdanm	0:9b334a45a8ff	2980	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2981	* @{
bogdanm	0:9b334a45a8ff	2982	*/
bogdanm	0:9b334a45a8ff	2983	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
bogdanm	0:9b334a45a8ff	2984
bogdanm	0:9b334a45a8ff	2985	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
bogdanm	0:9b334a45a8ff	2986	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2987	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2988	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
bogdanm	0:9b334a45a8ff	2989
bogdanm	0:9b334a45a8ff	2990	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
bogdanm	0:9b334a45a8ff	2991	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2992	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2993	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
bogdanm	0:9b334a45a8ff	2994
bogdanm	0:9b334a45a8ff	2995	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	2996	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	2997	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	2998	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2999	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	3000	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	3001	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	3002
bogdanm	0:9b334a45a8ff	3003	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	3004	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	3005	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	3006	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	3007	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	3008	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	3009	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	3010	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
bogdanm	0:9b334a45a8ff	3011
bogdanm	0:9b334a45a8ff	3012	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	3013	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	3014	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	3015	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	3016	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	3017	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	3018	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	3019	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
bogdanm	0:9b334a45a8ff	3020
bogdanm	0:9b334a45a8ff	3021	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
bogdanm	0:9b334a45a8ff	3022	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
bogdanm	0:9b334a45a8ff	3023
bogdanm	0:9b334a45a8ff	3024	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
bogdanm	0:9b334a45a8ff	3025	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
bogdanm	0:9b334a45a8ff	3026	/**
bogdanm	0:9b334a45a8ff	3027	* @}
bogdanm	0:9b334a45a8ff	3028	*/
bogdanm	0:9b334a45a8ff	3029
bogdanm	0:9b334a45a8ff	3030	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	3031	* @{
bogdanm	0:9b334a45a8ff	3032	*/
bogdanm	0:9b334a45a8ff	3033	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
bogdanm	0:9b334a45a8ff	3034	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
bogdanm	0:9b334a45a8ff	3035
bogdanm	0:9b334a45a8ff	3036	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
bogdanm	0:9b334a45a8ff	3037	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
bogdanm	0:9b334a45a8ff	3038
mbed_official	124:6a4a5b7d7324	3039	#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
mbed_official	124:6a4a5b7d7324	3040
bogdanm	0:9b334a45a8ff	3041	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
bogdanm	0:9b334a45a8ff	3042	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
bogdanm	0:9b334a45a8ff	3043	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
bogdanm	0:9b334a45a8ff	3044	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
bogdanm	0:9b334a45a8ff	3045	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
bogdanm	0:9b334a45a8ff	3046	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
bogdanm	0:9b334a45a8ff	3047	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
bogdanm	0:9b334a45a8ff	3048	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
bogdanm	0:9b334a45a8ff	3049	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
bogdanm	0:9b334a45a8ff	3050	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
bogdanm	0:9b334a45a8ff	3051	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
bogdanm	0:9b334a45a8ff	3052	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
bogdanm	0:9b334a45a8ff	3053
mbed_official	124:6a4a5b7d7324	3054	#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
bogdanm	0:9b334a45a8ff	3055	/**
bogdanm	0:9b334a45a8ff	3056	* @}
bogdanm	0:9b334a45a8ff	3057	*/
bogdanm	0:9b334a45a8ff	3058
bogdanm	0:9b334a45a8ff	3059	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	3060	* @{
bogdanm	0:9b334a45a8ff	3061	*/
bogdanm	0:9b334a45a8ff	3062
bogdanm	0:9b334a45a8ff	3063	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	3064	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	3065	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	3066	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	3067	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
bogdanm	0:9b334a45a8ff	3068	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
bogdanm	0:9b334a45a8ff	3069	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
bogdanm	0:9b334a45a8ff	3070
bogdanm	0:9b334a45a8ff	3071	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
bogdanm	0:9b334a45a8ff	3072	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
bogdanm	0:9b334a45a8ff	3073	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
bogdanm	0:9b334a45a8ff	3074	/**
bogdanm	0:9b334a45a8ff	3075	* @}
bogdanm	0:9b334a45a8ff	3076	*/
bogdanm	0:9b334a45a8ff	3077
bogdanm	0:9b334a45a8ff	3078	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	3079	* @{
bogdanm	0:9b334a45a8ff	3080	*/
bogdanm	0:9b334a45a8ff	3081	#define __HAL_LTDC_LAYER LTDC_LAYER
bogdanm	0:9b334a45a8ff	3082	/**
bogdanm	0:9b334a45a8ff	3083	* @}
bogdanm	0:9b334a45a8ff	3084	*/
bogdanm	0:9b334a45a8ff	3085
bogdanm	0:9b334a45a8ff	3086	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	3087	* @{
bogdanm	0:9b334a45a8ff	3088	*/
bogdanm	0:9b334a45a8ff	3089	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
bogdanm	0:9b334a45a8ff	3090	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
bogdanm	0:9b334a45a8ff	3091	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
bogdanm	0:9b334a45a8ff	3092	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
bogdanm	0:9b334a45a8ff	3093	#define SAI_STREOMODE SAI_STEREOMODE
mbed_official	124:6a4a5b7d7324	3094	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
mbed_official	124:6a4a5b7d7324	3095	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
mbed_official	124:6a4a5b7d7324	3096	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
mbed_official	124:6a4a5b7d7324	3097	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
mbed_official	124:6a4a5b7d7324	3098	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
mbed_official	124:6a4a5b7d7324	3099	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
mbed_official	124:6a4a5b7d7324	3100	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
mbed_official	124:6a4a5b7d7324	3101	#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
mbed_official	124:6a4a5b7d7324	3102	#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
bogdanm	0:9b334a45a8ff	3103	/**
bogdanm	0:9b334a45a8ff	3104	* @}
bogdanm	0:9b334a45a8ff	3105	*/
bogdanm	0:9b334a45a8ff	3106
bogdanm	0:9b334a45a8ff	3107
bogdanm	0:9b334a45a8ff	3108	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	3109	* @{
bogdanm	0:9b334a45a8ff	3110	*/
bogdanm	0:9b334a45a8ff	3111
bogdanm	0:9b334a45a8ff	3112	/**
bogdanm	0:9b334a45a8ff	3113	* @}
bogdanm	0:9b334a45a8ff	3114	*/
bogdanm	0:9b334a45a8ff	3115
bogdanm	0:9b334a45a8ff	3116	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	3117	}
bogdanm	0:9b334a45a8ff	3118	#endif
bogdanm	0:9b334a45a8ff	3119
bogdanm	0:9b334a45a8ff	3120	#endif /* ___STM32_HAL_LEGACY */
bogdanm	0:9b334a45a8ff	3121
bogdanm	0:9b334a45a8ff	3122	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	3123

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32_hal_legacy.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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