mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32_hal_legacy.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 124:6a4a5b7d7324

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32_hal_legacy.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 15-December-2014
bogdanm	0:9b334a45a8ff	7	* @brief This file contains aliases definition for the STM32Cube HAL constants
bogdanm	0:9b334a45a8ff	8	* macros and functions maintained for legacy purpose.
bogdanm	0:9b334a45a8ff	9	******************************************************************************
bogdanm	0:9b334a45a8ff	10	* @attention
bogdanm	0:9b334a45a8ff	11	*
bogdanm	0:9b334a45a8ff	12	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	13	*
bogdanm	0:9b334a45a8ff	14	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	15	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	16	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	17	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	19	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	20	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	22	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	23	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	24	*
bogdanm	0:9b334a45a8ff	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	33	UART * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	35	*
bogdanm	0:9b334a45a8ff	36	******************************************************************************
bogdanm	0:9b334a45a8ff	37	*/
bogdanm	0:9b334a45a8ff	38
bogdanm	0:9b334a45a8ff	39	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	40	#ifndef __STM32_HAL_LEGACY
bogdanm	0:9b334a45a8ff	41	#define __STM32_HAL_LEGACY
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	44	extern "C" {
bogdanm	0:9b334a45a8ff	45	#endif
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	48	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	49	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	50
bogdanm	0:9b334a45a8ff	51	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	52	* @{
bogdanm	0:9b334a45a8ff	53	*/
bogdanm	0:9b334a45a8ff	54	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
bogdanm	0:9b334a45a8ff	55	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
bogdanm	0:9b334a45a8ff	56	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
bogdanm	0:9b334a45a8ff	57	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
bogdanm	0:9b334a45a8ff	58	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	/**
bogdanm	0:9b334a45a8ff	61	* @}
bogdanm	0:9b334a45a8ff	62	*/
bogdanm	0:9b334a45a8ff	63
bogdanm	0:9b334a45a8ff	64	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	65	* @{
bogdanm	0:9b334a45a8ff	66	*/
bogdanm	0:9b334a45a8ff	67	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
bogdanm	0:9b334a45a8ff	68	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
bogdanm	0:9b334a45a8ff	69	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
bogdanm	0:9b334a45a8ff	70	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
bogdanm	0:9b334a45a8ff	71	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
bogdanm	0:9b334a45a8ff	72	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
bogdanm	0:9b334a45a8ff	73	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
bogdanm	0:9b334a45a8ff	74	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
bogdanm	0:9b334a45a8ff	75	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
bogdanm	0:9b334a45a8ff	76	#define REGULAR_GROUP ADC_REGULAR_GROUP
bogdanm	0:9b334a45a8ff	77	#define INJECTED_GROUP ADC_INJECTED_GROUP
bogdanm	0:9b334a45a8ff	78	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
bogdanm	0:9b334a45a8ff	79	#define AWD_EVENT ADC_AWD_EVENT
bogdanm	0:9b334a45a8ff	80	#define AWD1_EVENT ADC_AWD1_EVENT
bogdanm	0:9b334a45a8ff	81	#define AWD2_EVENT ADC_AWD2_EVENT
bogdanm	0:9b334a45a8ff	82	#define AWD3_EVENT ADC_AWD3_EVENT
bogdanm	0:9b334a45a8ff	83	#define OVR_EVENT ADC_OVR_EVENT
bogdanm	0:9b334a45a8ff	84	#define JQOVF_EVENT ADC_JQOVF_EVENT
bogdanm	0:9b334a45a8ff	85	#define ALL_CHANNELS ADC_ALL_CHANNELS
bogdanm	0:9b334a45a8ff	86	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
bogdanm	0:9b334a45a8ff	87	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
bogdanm	0:9b334a45a8ff	88	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
bogdanm	0:9b334a45a8ff	89	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
bogdanm	0:9b334a45a8ff	90	#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
bogdanm	0:9b334a45a8ff	91	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
bogdanm	0:9b334a45a8ff	92	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
bogdanm	0:9b334a45a8ff	93	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
bogdanm	0:9b334a45a8ff	94	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
bogdanm	0:9b334a45a8ff	95	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
bogdanm	0:9b334a45a8ff	96	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
bogdanm	0:9b334a45a8ff	97	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
bogdanm	0:9b334a45a8ff	98	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
bogdanm	0:9b334a45a8ff	99	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101
bogdanm	0:9b334a45a8ff	102	/**
bogdanm	0:9b334a45a8ff	103	* @}
bogdanm	0:9b334a45a8ff	104	*/
bogdanm	0:9b334a45a8ff	105
bogdanm	0:9b334a45a8ff	106	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	107	* @{
bogdanm	0:9b334a45a8ff	108	*/
bogdanm	0:9b334a45a8ff	109
bogdanm	0:9b334a45a8ff	110	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112	/**
bogdanm	0:9b334a45a8ff	113	* @}
bogdanm	0:9b334a45a8ff	114	*/
bogdanm	0:9b334a45a8ff	115
bogdanm	0:9b334a45a8ff	116	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	117	* @{
bogdanm	0:9b334a45a8ff	118	*/
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
bogdanm	0:9b334a45a8ff	121	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
bogdanm	0:9b334a45a8ff	122	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
bogdanm	0:9b334a45a8ff	123	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125	/**
bogdanm	0:9b334a45a8ff	126	* @}
bogdanm	0:9b334a45a8ff	127	*/
bogdanm	0:9b334a45a8ff	128
bogdanm	0:9b334a45a8ff	129	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	130	* @{
bogdanm	0:9b334a45a8ff	131	*/
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
bogdanm	0:9b334a45a8ff	134	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
bogdanm	0:9b334a45a8ff	135
bogdanm	0:9b334a45a8ff	136	/**
bogdanm	0:9b334a45a8ff	137	* @}
bogdanm	0:9b334a45a8ff	138	*/
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	141	* @{
bogdanm	0:9b334a45a8ff	142	*/
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
bogdanm	0:9b334a45a8ff	145	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
bogdanm	0:9b334a45a8ff	146	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148	/**
bogdanm	0:9b334a45a8ff	149	* @}
bogdanm	0:9b334a45a8ff	150	*/
bogdanm	0:9b334a45a8ff	151
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	154	* @{
bogdanm	0:9b334a45a8ff	155	*/
bogdanm	0:9b334a45a8ff	156
bogdanm	0:9b334a45a8ff	157	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
bogdanm	0:9b334a45a8ff	158	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
bogdanm	0:9b334a45a8ff	159	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
bogdanm	0:9b334a45a8ff	160	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
bogdanm	0:9b334a45a8ff	161	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
bogdanm	0:9b334a45a8ff	162	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
bogdanm	0:9b334a45a8ff	163	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
bogdanm	0:9b334a45a8ff	164	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
bogdanm	0:9b334a45a8ff	165	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
bogdanm	0:9b334a45a8ff	166	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
bogdanm	0:9b334a45a8ff	167	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	168	#define OBEX_PCROP OPTIONBYTE_PCROP
bogdanm	0:9b334a45a8ff	169	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
bogdanm	0:9b334a45a8ff	170	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
bogdanm	0:9b334a45a8ff	171	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
bogdanm	0:9b334a45a8ff	172	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
bogdanm	0:9b334a45a8ff	173	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
bogdanm	0:9b334a45a8ff	174	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
bogdanm	0:9b334a45a8ff	175	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
bogdanm	0:9b334a45a8ff	176	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
bogdanm	0:9b334a45a8ff	177	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
bogdanm	0:9b334a45a8ff	178	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
bogdanm	0:9b334a45a8ff	179	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
bogdanm	0:9b334a45a8ff	180	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
bogdanm	0:9b334a45a8ff	181	#define PAGESIZE FLASH_PAGE_SIZE
bogdanm	0:9b334a45a8ff	182	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
bogdanm	0:9b334a45a8ff	183	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
bogdanm	0:9b334a45a8ff	184	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
bogdanm	0:9b334a45a8ff	185	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
bogdanm	0:9b334a45a8ff	186	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
bogdanm	0:9b334a45a8ff	187	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
bogdanm	0:9b334a45a8ff	188	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
bogdanm	0:9b334a45a8ff	189	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
bogdanm	0:9b334a45a8ff	190	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
bogdanm	0:9b334a45a8ff	191	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
bogdanm	0:9b334a45a8ff	192	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
bogdanm	0:9b334a45a8ff	193	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
bogdanm	0:9b334a45a8ff	194	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
bogdanm	0:9b334a45a8ff	195	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
bogdanm	0:9b334a45a8ff	196	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
bogdanm	0:9b334a45a8ff	197	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
bogdanm	0:9b334a45a8ff	198	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
bogdanm	0:9b334a45a8ff	199	#define IS_NBSECTORS IS_FLASH_NBSECTORS
bogdanm	0:9b334a45a8ff	200	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
bogdanm	0:9b334a45a8ff	201	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
bogdanm	0:9b334a45a8ff	202	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
bogdanm	0:9b334a45a8ff	203	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
bogdanm	0:9b334a45a8ff	204	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
bogdanm	0:9b334a45a8ff	205	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
bogdanm	0:9b334a45a8ff	206	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
bogdanm	0:9b334a45a8ff	207	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
bogdanm	0:9b334a45a8ff	208	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
bogdanm	0:9b334a45a8ff	209	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
bogdanm	0:9b334a45a8ff	210	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
bogdanm	0:9b334a45a8ff	211	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
bogdanm	0:9b334a45a8ff	212	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
bogdanm	0:9b334a45a8ff	213	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
bogdanm	0:9b334a45a8ff	214	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
bogdanm	0:9b334a45a8ff	215	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
bogdanm	0:9b334a45a8ff	216	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
bogdanm	0:9b334a45a8ff	217	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
bogdanm	0:9b334a45a8ff	218	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
bogdanm	0:9b334a45a8ff	219
bogdanm	0:9b334a45a8ff	220	/**
bogdanm	0:9b334a45a8ff	221	* @}
bogdanm	0:9b334a45a8ff	222	*/
bogdanm	0:9b334a45a8ff	223
bogdanm	0:9b334a45a8ff	224	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	225	* @{
bogdanm	0:9b334a45a8ff	226	*/
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
bogdanm	0:9b334a45a8ff	229	#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
bogdanm	0:9b334a45a8ff	230	#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
bogdanm	0:9b334a45a8ff	231	#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
bogdanm	0:9b334a45a8ff	232	#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
bogdanm	0:9b334a45a8ff	233	#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
bogdanm	0:9b334a45a8ff	234	#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
bogdanm	0:9b334a45a8ff	235
bogdanm	0:9b334a45a8ff	236	/**
bogdanm	0:9b334a45a8ff	237	* @}
bogdanm	0:9b334a45a8ff	238	*/
bogdanm	0:9b334a45a8ff	239
bogdanm	0:9b334a45a8ff	240
bogdanm	0:9b334a45a8ff	241	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	242	* @{
bogdanm	0:9b334a45a8ff	243	*/
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
bogdanm	0:9b334a45a8ff	246	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
bogdanm	0:9b334a45a8ff	247	/**
bogdanm	0:9b334a45a8ff	248	* @}
bogdanm	0:9b334a45a8ff	249	*/
bogdanm	0:9b334a45a8ff	250
bogdanm	0:9b334a45a8ff	251	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	252	* @{
bogdanm	0:9b334a45a8ff	253	*/
bogdanm	0:9b334a45a8ff	254	#define GET_GPIO_SOURCE GPIO_GET_INDEX
bogdanm	0:9b334a45a8ff	255	#define GET_GPIO_INDEX GPIO_GET_INDEX
bogdanm	0:9b334a45a8ff	256	/**
bogdanm	0:9b334a45a8ff	257	* @}
bogdanm	0:9b334a45a8ff	258	*/
bogdanm	0:9b334a45a8ff	259
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	262	* @{
bogdanm	0:9b334a45a8ff	263	*/
bogdanm	0:9b334a45a8ff	264	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
bogdanm	0:9b334a45a8ff	265	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
bogdanm	0:9b334a45a8ff	266	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
bogdanm	0:9b334a45a8ff	267	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
bogdanm	0:9b334a45a8ff	268	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
bogdanm	0:9b334a45a8ff	269	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
bogdanm	0:9b334a45a8ff	270	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
bogdanm	0:9b334a45a8ff	271	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
bogdanm	0:9b334a45a8ff	272	/**
bogdanm	0:9b334a45a8ff	273	* @}
bogdanm	0:9b334a45a8ff	274	*/
bogdanm	0:9b334a45a8ff	275
bogdanm	0:9b334a45a8ff	276	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	277	* @{
bogdanm	0:9b334a45a8ff	278	*/
bogdanm	0:9b334a45a8ff	279	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	280	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282	/**
bogdanm	0:9b334a45a8ff	283	* @}
bogdanm	0:9b334a45a8ff	284	*/
bogdanm	0:9b334a45a8ff	285
bogdanm	0:9b334a45a8ff	286	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	287	* @{
bogdanm	0:9b334a45a8ff	288	*/
bogdanm	0:9b334a45a8ff	289	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
bogdanm	0:9b334a45a8ff	290	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
bogdanm	0:9b334a45a8ff	291	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
bogdanm	0:9b334a45a8ff	292	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
bogdanm	0:9b334a45a8ff	293	/**
bogdanm	0:9b334a45a8ff	294	* @}
bogdanm	0:9b334a45a8ff	295	*/
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	298	* @{
bogdanm	0:9b334a45a8ff	299	*/
bogdanm	0:9b334a45a8ff	300	#define NAND_AddressTypedef NAND_AddressTypeDef
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	/**
bogdanm	0:9b334a45a8ff	303	* @}
bogdanm	0:9b334a45a8ff	304	*/
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	307	* @{
bogdanm	0:9b334a45a8ff	308	*/
bogdanm	0:9b334a45a8ff	309	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
bogdanm	0:9b334a45a8ff	310	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
bogdanm	0:9b334a45a8ff	311	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
bogdanm	0:9b334a45a8ff	312	#define NOR_ERROR HAL_NOR_STATUS_ERROR
bogdanm	0:9b334a45a8ff	313	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/**
bogdanm	0:9b334a45a8ff	316	* @}
bogdanm	0:9b334a45a8ff	317	*/
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	320	* @{
bogdanm	0:9b334a45a8ff	321	*/
bogdanm	0:9b334a45a8ff	322
bogdanm	0:9b334a45a8ff	323	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	324	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	325	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
bogdanm	0:9b334a45a8ff	326	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
bogdanm	0:9b334a45a8ff	327
bogdanm	0:9b334a45a8ff	328	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	329	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	330	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
bogdanm	0:9b334a45a8ff	331	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	334	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	337	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	338
bogdanm	0:9b334a45a8ff	339	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	340	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
bogdanm	0:9b334a45a8ff	345	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
bogdanm	0:9b334a45a8ff	346	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	/**
bogdanm	0:9b334a45a8ff	349	* @}
bogdanm	0:9b334a45a8ff	350	*/
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	353	* @{
bogdanm	0:9b334a45a8ff	354	*/
bogdanm	0:9b334a45a8ff	355	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
bogdanm	0:9b334a45a8ff	356	/**
bogdanm	0:9b334a45a8ff	357	* @}
bogdanm	0:9b334a45a8ff	358	*/
bogdanm	0:9b334a45a8ff	359
bogdanm	0:9b334a45a8ff	360	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	361	* @{
bogdanm	0:9b334a45a8ff	362	*/
bogdanm	0:9b334a45a8ff	363
bogdanm	0:9b334a45a8ff	364	/* Compact Flash-ATA registers description */
bogdanm	0:9b334a45a8ff	365	#define CF_DATA ATA_DATA
bogdanm	0:9b334a45a8ff	366	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
bogdanm	0:9b334a45a8ff	367	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
bogdanm	0:9b334a45a8ff	368	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
bogdanm	0:9b334a45a8ff	369	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
bogdanm	0:9b334a45a8ff	370	#define CF_CARD_HEAD ATA_CARD_HEAD
bogdanm	0:9b334a45a8ff	371	#define CF_STATUS_CMD ATA_STATUS_CMD
bogdanm	0:9b334a45a8ff	372	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
bogdanm	0:9b334a45a8ff	373	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	/* Compact Flash-ATA commands */
bogdanm	0:9b334a45a8ff	376	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
bogdanm	0:9b334a45a8ff	377	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
bogdanm	0:9b334a45a8ff	378	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
bogdanm	0:9b334a45a8ff	379	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
bogdanm	0:9b334a45a8ff	382	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
bogdanm	0:9b334a45a8ff	383	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
bogdanm	0:9b334a45a8ff	384	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
bogdanm	0:9b334a45a8ff	385	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
bogdanm	0:9b334a45a8ff	386	/**
bogdanm	0:9b334a45a8ff	387	* @}
bogdanm	0:9b334a45a8ff	388	*/
bogdanm	0:9b334a45a8ff	389
bogdanm	0:9b334a45a8ff	390	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	391	* @{
bogdanm	0:9b334a45a8ff	392	*/
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	#define FORMAT_BIN RTC_FORMAT_BIN
bogdanm	0:9b334a45a8ff	395	#define FORMAT_BCD RTC_FORMAT_BCD
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
bogdanm	0:9b334a45a8ff	398	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
bogdanm	0:9b334a45a8ff	399	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
bogdanm	0:9b334a45a8ff	400	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
bogdanm	0:9b334a45a8ff	401	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
bogdanm	0:9b334a45a8ff	402
bogdanm	0:9b334a45a8ff	403	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
bogdanm	0:9b334a45a8ff	404	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
bogdanm	0:9b334a45a8ff	405	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
bogdanm	0:9b334a45a8ff	406	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
bogdanm	0:9b334a45a8ff	407	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
bogdanm	0:9b334a45a8ff	408	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
bogdanm	0:9b334a45a8ff	409	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
bogdanm	0:9b334a45a8ff	410	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	/**
bogdanm	0:9b334a45a8ff	413	* @}
bogdanm	0:9b334a45a8ff	414	*/
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416
bogdanm	0:9b334a45a8ff	417	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	418	* @{
bogdanm	0:9b334a45a8ff	419	*/
bogdanm	0:9b334a45a8ff	420	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
bogdanm	0:9b334a45a8ff	421	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	424	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	425	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	426	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	427
bogdanm	0:9b334a45a8ff	428	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
bogdanm	0:9b334a45a8ff	429	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
bogdanm	0:9b334a45a8ff	430
bogdanm	0:9b334a45a8ff	431	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
bogdanm	0:9b334a45a8ff	432	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
bogdanm	0:9b334a45a8ff	433	/**
bogdanm	0:9b334a45a8ff	434	* @}
bogdanm	0:9b334a45a8ff	435	*/
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437
bogdanm	0:9b334a45a8ff	438	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	439	* @{
bogdanm	0:9b334a45a8ff	440	*/
bogdanm	0:9b334a45a8ff	441	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
bogdanm	0:9b334a45a8ff	442	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
bogdanm	0:9b334a45a8ff	443	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
bogdanm	0:9b334a45a8ff	444	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
bogdanm	0:9b334a45a8ff	445	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
bogdanm	0:9b334a45a8ff	446	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
bogdanm	0:9b334a45a8ff	447	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
bogdanm	0:9b334a45a8ff	448	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
bogdanm	0:9b334a45a8ff	449	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
bogdanm	0:9b334a45a8ff	450	/**
bogdanm	0:9b334a45a8ff	451	* @}
bogdanm	0:9b334a45a8ff	452	*/
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	455	* @{
bogdanm	0:9b334a45a8ff	456	*/
bogdanm	0:9b334a45a8ff	457	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
bogdanm	0:9b334a45a8ff	458	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
bogdanm	0:9b334a45a8ff	459
bogdanm	0:9b334a45a8ff	460	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
bogdanm	0:9b334a45a8ff	461	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
bogdanm	0:9b334a45a8ff	462
bogdanm	0:9b334a45a8ff	463	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
bogdanm	0:9b334a45a8ff	464	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
bogdanm	0:9b334a45a8ff	465
bogdanm	0:9b334a45a8ff	466	/**
bogdanm	0:9b334a45a8ff	467	* @}
bogdanm	0:9b334a45a8ff	468	*/
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	471	* @{
bogdanm	0:9b334a45a8ff	472	*/
bogdanm	0:9b334a45a8ff	473	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
bogdanm	0:9b334a45a8ff	474	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
bogdanm	0:9b334a45a8ff	475
bogdanm	0:9b334a45a8ff	476	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	477	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	478	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	479	#define TIM_DMABase_DIER TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	480	#define TIM_DMABase_SR TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	481	#define TIM_DMABase_EGR TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	482	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	483	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	484	#define TIM_DMABase_CCER TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	485	#define TIM_DMABase_CNT TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	486	#define TIM_DMABase_PSC TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	487	#define TIM_DMABase_ARR TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	488	#define TIM_DMABase_RCR TIM_DMABASE_RCR
bogdanm	0:9b334a45a8ff	489	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	490	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	491	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	492	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	493	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
bogdanm	0:9b334a45a8ff	494	#define TIM_DMABase_DCR TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	495	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
bogdanm	0:9b334a45a8ff	496	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
bogdanm	0:9b334a45a8ff	497	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
bogdanm	0:9b334a45a8ff	498	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
bogdanm	0:9b334a45a8ff	499	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
bogdanm	0:9b334a45a8ff	500	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
bogdanm	0:9b334a45a8ff	501	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
bogdanm	0:9b334a45a8ff	504	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
bogdanm	0:9b334a45a8ff	505	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
bogdanm	0:9b334a45a8ff	506	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
bogdanm	0:9b334a45a8ff	507	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
bogdanm	0:9b334a45a8ff	508	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
bogdanm	0:9b334a45a8ff	509	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
bogdanm	0:9b334a45a8ff	510	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
bogdanm	0:9b334a45a8ff	511	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
bogdanm	0:9b334a45a8ff	512
bogdanm	0:9b334a45a8ff	513	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
bogdanm	0:9b334a45a8ff	514	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
bogdanm	0:9b334a45a8ff	515	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
bogdanm	0:9b334a45a8ff	516	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
bogdanm	0:9b334a45a8ff	517	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
bogdanm	0:9b334a45a8ff	518	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
bogdanm	0:9b334a45a8ff	519	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
bogdanm	0:9b334a45a8ff	520	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
bogdanm	0:9b334a45a8ff	521	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
bogdanm	0:9b334a45a8ff	522	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
bogdanm	0:9b334a45a8ff	523	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
bogdanm	0:9b334a45a8ff	524	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
bogdanm	0:9b334a45a8ff	525	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
bogdanm	0:9b334a45a8ff	526	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
bogdanm	0:9b334a45a8ff	527	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
bogdanm	0:9b334a45a8ff	528	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
bogdanm	0:9b334a45a8ff	529	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
bogdanm	0:9b334a45a8ff	530	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	/**
bogdanm	0:9b334a45a8ff	533	* @}
bogdanm	0:9b334a45a8ff	534	*/
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	537	* @{
bogdanm	0:9b334a45a8ff	538	*/
bogdanm	0:9b334a45a8ff	539	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	540	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	541	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	542	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
bogdanm	0:9b334a45a8ff	545	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
bogdanm	0:9b334a45a8ff	546
bogdanm	0:9b334a45a8ff	547	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
bogdanm	0:9b334a45a8ff	548	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
bogdanm	0:9b334a45a8ff	549	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
bogdanm	0:9b334a45a8ff	550	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
bogdanm	0:9b334a45a8ff	553	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
bogdanm	0:9b334a45a8ff	554	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
bogdanm	0:9b334a45a8ff	555	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
bogdanm	0:9b334a45a8ff	558	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	/**
bogdanm	0:9b334a45a8ff	561	* @}
bogdanm	0:9b334a45a8ff	562	*/
bogdanm	0:9b334a45a8ff	563
bogdanm	0:9b334a45a8ff	564
bogdanm	0:9b334a45a8ff	565	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	566	* @{
bogdanm	0:9b334a45a8ff	567	*/
bogdanm	0:9b334a45a8ff	568
bogdanm	0:9b334a45a8ff	569	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
bogdanm	0:9b334a45a8ff	570	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	#define USARTNACK_ENABLED USART_NACK_ENABLE
bogdanm	0:9b334a45a8ff	573	#define USARTNACK_DISABLED USART_NACK_DISABLE
bogdanm	0:9b334a45a8ff	574	/**
bogdanm	0:9b334a45a8ff	575	* @}
bogdanm	0:9b334a45a8ff	576	*/
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	579	* @{
bogdanm	0:9b334a45a8ff	580	*/
bogdanm	0:9b334a45a8ff	581	#define CFR_BASE WWDG_CFR_BASE
bogdanm	0:9b334a45a8ff	582
bogdanm	0:9b334a45a8ff	583	/**
bogdanm	0:9b334a45a8ff	584	* @}
bogdanm	0:9b334a45a8ff	585	*/
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	588	* @{
bogdanm	0:9b334a45a8ff	589	*/
bogdanm	0:9b334a45a8ff	590	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
bogdanm	0:9b334a45a8ff	591	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
bogdanm	0:9b334a45a8ff	592	#define CAN_IT_RQCP0 CAN_IT_TME
bogdanm	0:9b334a45a8ff	593	#define CAN_IT_RQCP1 CAN_IT_TME
bogdanm	0:9b334a45a8ff	594	#define CAN_IT_RQCP2 CAN_IT_TME
bogdanm	0:9b334a45a8ff	595	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	596	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	597	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	598	#define CAN_TXSTATUS_OK ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	599	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/**
bogdanm	0:9b334a45a8ff	602	* @}
bogdanm	0:9b334a45a8ff	603	*/
bogdanm	0:9b334a45a8ff	604
bogdanm	0:9b334a45a8ff	605	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	606	* @{
bogdanm	0:9b334a45a8ff	607	*/
bogdanm	0:9b334a45a8ff	608
bogdanm	0:9b334a45a8ff	609	#define VLAN_TAG ETH_VLAN_TAG
bogdanm	0:9b334a45a8ff	610	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
bogdanm	0:9b334a45a8ff	611	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
bogdanm	0:9b334a45a8ff	612	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
bogdanm	0:9b334a45a8ff	613	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
bogdanm	0:9b334a45a8ff	614	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
bogdanm	0:9b334a45a8ff	615	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
bogdanm	0:9b334a45a8ff	616	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
bogdanm	0:9b334a45a8ff	617
bogdanm	0:9b334a45a8ff	618	#define ETH_MMCCR ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	619	#define ETH_MMCRIR ((uint32_t)0x00000104)
bogdanm	0:9b334a45a8ff	620	#define ETH_MMCTIR ((uint32_t)0x00000108)
bogdanm	0:9b334a45a8ff	621	#define ETH_MMCRIMR ((uint32_t)0x0000010C)
bogdanm	0:9b334a45a8ff	622	#define ETH_MMCTIMR ((uint32_t)0x00000110)
bogdanm	0:9b334a45a8ff	623	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
bogdanm	0:9b334a45a8ff	624	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
bogdanm	0:9b334a45a8ff	625	#define ETH_MMCTGFCR ((uint32_t)0x00000168)
bogdanm	0:9b334a45a8ff	626	#define ETH_MMCRFCECR ((uint32_t)0x00000194)
bogdanm	0:9b334a45a8ff	627	#define ETH_MMCRFAECR ((uint32_t)0x00000198)
bogdanm	0:9b334a45a8ff	628	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
bogdanm	0:9b334a45a8ff	629
bogdanm	0:9b334a45a8ff	630	/**
bogdanm	0:9b334a45a8ff	631	* @}
bogdanm	0:9b334a45a8ff	632	*/
bogdanm	0:9b334a45a8ff	633
bogdanm	0:9b334a45a8ff	634	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
bogdanm	0:9b334a45a8ff	635	* @{
bogdanm	0:9b334a45a8ff	636	*/
bogdanm	0:9b334a45a8ff	637
bogdanm	0:9b334a45a8ff	638	/**
bogdanm	0:9b334a45a8ff	639	* @}
bogdanm	0:9b334a45a8ff	640	*/
bogdanm	0:9b334a45a8ff	641
bogdanm	0:9b334a45a8ff	642	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	645	* @{
bogdanm	0:9b334a45a8ff	646	*/
bogdanm	0:9b334a45a8ff	647	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
bogdanm	0:9b334a45a8ff	648	/**
bogdanm	0:9b334a45a8ff	649	* @}
bogdanm	0:9b334a45a8ff	650	*/
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	653	* @{
bogdanm	0:9b334a45a8ff	654	*/
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
bogdanm	0:9b334a45a8ff	657	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
bogdanm	0:9b334a45a8ff	658	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
bogdanm	0:9b334a45a8ff	659	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	/HASH Algorithm Selection/
bogdanm	0:9b334a45a8ff	662
bogdanm	0:9b334a45a8ff	663	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
bogdanm	0:9b334a45a8ff	664	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
bogdanm	0:9b334a45a8ff	665	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
bogdanm	0:9b334a45a8ff	666	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
bogdanm	0:9b334a45a8ff	669	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
bogdanm	0:9b334a45a8ff	672	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
bogdanm	0:9b334a45a8ff	673	/**
bogdanm	0:9b334a45a8ff	674	* @}
bogdanm	0:9b334a45a8ff	675	*/
bogdanm	0:9b334a45a8ff	676
bogdanm	0:9b334a45a8ff	677	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	678	* @{
bogdanm	0:9b334a45a8ff	679	*/
bogdanm	0:9b334a45a8ff	680	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
bogdanm	0:9b334a45a8ff	681	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
bogdanm	0:9b334a45a8ff	682	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
bogdanm	0:9b334a45a8ff	683	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
bogdanm	0:9b334a45a8ff	684	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
bogdanm	0:9b334a45a8ff	685	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
bogdanm	0:9b334a45a8ff	686	#define HAL_DBG_LowPowerConfig(Periph, cmd) ((cmd==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
bogdanm	0:9b334a45a8ff	687	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
bogdanm	0:9b334a45a8ff	688	#define HAL_Lock_Cmd(cmd) ((cmd==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
bogdanm	0:9b334a45a8ff	689	#define HAL_VREFINT_Cmd(cmd) ((cmd==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
bogdanm	0:9b334a45a8ff	690	#define HAL_ADC_EnableBuffer_Cmd(cmd) ((cmd==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
bogdanm	0:9b334a45a8ff	691	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) ((cmd==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
bogdanm	0:9b334a45a8ff	692	/**
bogdanm	0:9b334a45a8ff	693	* @}
bogdanm	0:9b334a45a8ff	694	*/
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	697	* @{
bogdanm	0:9b334a45a8ff	698	*/
bogdanm	0:9b334a45a8ff	699	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
bogdanm	0:9b334a45a8ff	700	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
bogdanm	0:9b334a45a8ff	701	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
bogdanm	0:9b334a45a8ff	702	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
bogdanm	0:9b334a45a8ff	703	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
bogdanm	0:9b334a45a8ff	704	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
bogdanm	0:9b334a45a8ff	705	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
bogdanm	0:9b334a45a8ff	706
bogdanm	0:9b334a45a8ff	707	/**
bogdanm	0:9b334a45a8ff	708	* @}
bogdanm	0:9b334a45a8ff	709	*/
bogdanm	0:9b334a45a8ff	710
bogdanm	0:9b334a45a8ff	711	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	712	* @{
bogdanm	0:9b334a45a8ff	713	*/
bogdanm	0:9b334a45a8ff	714	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
bogdanm	0:9b334a45a8ff	715	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
bogdanm	0:9b334a45a8ff	716
bogdanm	0:9b334a45a8ff	717	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
bogdanm	0:9b334a45a8ff	718	/**
bogdanm	0:9b334a45a8ff	719	* @}
bogdanm	0:9b334a45a8ff	720	*/
bogdanm	0:9b334a45a8ff	721
bogdanm	0:9b334a45a8ff	722	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
bogdanm	0:9b334a45a8ff	723	* @{
bogdanm	0:9b334a45a8ff	724	*/
bogdanm	0:9b334a45a8ff	725	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
bogdanm	0:9b334a45a8ff	726	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
bogdanm	0:9b334a45a8ff	727	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
bogdanm	0:9b334a45a8ff	728	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
bogdanm	0:9b334a45a8ff	729	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
bogdanm	0:9b334a45a8ff	730	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
bogdanm	0:9b334a45a8ff	731	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
bogdanm	0:9b334a45a8ff	732	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
bogdanm	0:9b334a45a8ff	733	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
bogdanm	0:9b334a45a8ff	734	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
bogdanm	0:9b334a45a8ff	735	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
bogdanm	0:9b334a45a8ff	736	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
bogdanm	0:9b334a45a8ff	737	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
bogdanm	0:9b334a45a8ff	738	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
bogdanm	0:9b334a45a8ff	739	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
bogdanm	0:9b334a45a8ff	740	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
bogdanm	0:9b334a45a8ff	741
bogdanm	0:9b334a45a8ff	742	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
bogdanm	0:9b334a45a8ff	743	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
bogdanm	0:9b334a45a8ff	744	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
bogdanm	0:9b334a45a8ff	745	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
bogdanm	0:9b334a45a8ff	746	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
bogdanm	0:9b334a45a8ff	747	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
bogdanm	0:9b334a45a8ff	748	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
bogdanm	0:9b334a45a8ff	749
bogdanm	0:9b334a45a8ff	750	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
bogdanm	0:9b334a45a8ff	751	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
bogdanm	0:9b334a45a8ff	752
bogdanm	0:9b334a45a8ff	753	#define DBP_BitNumber DBP_BIT_NUMBER
bogdanm	0:9b334a45a8ff	754	#define PVDE_BitNumber PVDE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	755	#define PMODE_BitNumber PMODE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	756	#define EWUP_BitNumber EWUP_BIT_NUMBER
bogdanm	0:9b334a45a8ff	757	#define FPDS_BitNumber FPDS_BIT_NUMBER
bogdanm	0:9b334a45a8ff	758	#define ODEN_BitNumber ODEN_BIT_NUMBER
bogdanm	0:9b334a45a8ff	759	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
bogdanm	0:9b334a45a8ff	760	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
bogdanm	0:9b334a45a8ff	761	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
bogdanm	0:9b334a45a8ff	762	#define BRE_BitNumber BRE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
bogdanm	0:9b334a45a8ff	765
bogdanm	0:9b334a45a8ff	766	/**
bogdanm	0:9b334a45a8ff	767	* @}
bogdanm	0:9b334a45a8ff	768	*/
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	/** @defgroup HAL_RCC_Aliased_Functions HAL RCC Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	771	* @{
bogdanm	0:9b334a45a8ff	772	*/
bogdanm	0:9b334a45a8ff	773	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
bogdanm	0:9b334a45a8ff	774	#define HAL_RC48_EnableBuffer_Cmd(cmd) ((cmd==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	/**
bogdanm	0:9b334a45a8ff	777	* @}
bogdanm	0:9b334a45a8ff	778	*/
bogdanm	0:9b334a45a8ff	779
bogdanm	0:9b334a45a8ff	780	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	781	* @{
bogdanm	0:9b334a45a8ff	782	*/
bogdanm	0:9b334a45a8ff	783	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
bogdanm	0:9b334a45a8ff	784	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
bogdanm	0:9b334a45a8ff	785	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
bogdanm	0:9b334a45a8ff	786	/**
bogdanm	0:9b334a45a8ff	787	* @}
bogdanm	0:9b334a45a8ff	788	*/
bogdanm	0:9b334a45a8ff	789
bogdanm	0:9b334a45a8ff	790	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	791	* @{
bogdanm	0:9b334a45a8ff	792	*/
bogdanm	0:9b334a45a8ff	793	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
bogdanm	0:9b334a45a8ff	794	/**
bogdanm	0:9b334a45a8ff	795	* @}
bogdanm	0:9b334a45a8ff	796	*/
bogdanm	0:9b334a45a8ff	797
bogdanm	0:9b334a45a8ff	798	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	799	* @{
bogdanm	0:9b334a45a8ff	800	*/
bogdanm	0:9b334a45a8ff	801	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
bogdanm	0:9b334a45a8ff	802	#define HAL_TIM_DMAError TIM_DMAError
bogdanm	0:9b334a45a8ff	803	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
bogdanm	0:9b334a45a8ff	804	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
bogdanm	0:9b334a45a8ff	805	/**
bogdanm	0:9b334a45a8ff	806	* @}
bogdanm	0:9b334a45a8ff	807	*/
bogdanm	0:9b334a45a8ff	808
bogdanm	0:9b334a45a8ff	809	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	810	* @{
bogdanm	0:9b334a45a8ff	811	*/
bogdanm	0:9b334a45a8ff	812	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
bogdanm	0:9b334a45a8ff	813	/**
bogdanm	0:9b334a45a8ff	814	* @}
bogdanm	0:9b334a45a8ff	815	*/
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817
bogdanm	0:9b334a45a8ff	818	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
bogdanm	0:9b334a45a8ff	819	* @{
bogdanm	0:9b334a45a8ff	820	*/
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822	/**
bogdanm	0:9b334a45a8ff	823	* @}
bogdanm	0:9b334a45a8ff	824	*/
bogdanm	0:9b334a45a8ff	825
bogdanm	0:9b334a45a8ff	826	/* Exported macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	829	* @{
bogdanm	0:9b334a45a8ff	830	*/
bogdanm	0:9b334a45a8ff	831	#define AES_IT_CC CRYP_IT_CC
bogdanm	0:9b334a45a8ff	832	#define AES_IT_ERR CRYP_IT_ERR
bogdanm	0:9b334a45a8ff	833	#define AES_FLAG_CCF CRYP_FLAG_CCF
bogdanm	0:9b334a45a8ff	834	/**
bogdanm	0:9b334a45a8ff	835	* @}
bogdanm	0:9b334a45a8ff	836	*/
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	839	* @{
bogdanm	0:9b334a45a8ff	840	*/
bogdanm	0:9b334a45a8ff	841	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
bogdanm	0:9b334a45a8ff	842	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
bogdanm	0:9b334a45a8ff	843	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
bogdanm	0:9b334a45a8ff	844	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
bogdanm	0:9b334a45a8ff	845	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
bogdanm	0:9b334a45a8ff	846	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
bogdanm	0:9b334a45a8ff	847	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
bogdanm	0:9b334a45a8ff	848	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
bogdanm	0:9b334a45a8ff	849	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	850	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
bogdanm	0:9b334a45a8ff	851	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
bogdanm	0:9b334a45a8ff	852	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
bogdanm	0:9b334a45a8ff	853	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	854	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	/**
bogdanm	0:9b334a45a8ff	857	* @}
bogdanm	0:9b334a45a8ff	858	*/
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860
bogdanm	0:9b334a45a8ff	861	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	862	* @{
bogdanm	0:9b334a45a8ff	863	*/
bogdanm	0:9b334a45a8ff	864	#define __ADC_ENABLE __HAL_ADC_ENABLE
bogdanm	0:9b334a45a8ff	865	#define __ADC_DISABLE __HAL_ADC_DISABLE
bogdanm	0:9b334a45a8ff	866	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
bogdanm	0:9b334a45a8ff	867	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
bogdanm	0:9b334a45a8ff	868	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
bogdanm	0:9b334a45a8ff	869	#define __ADC_IS_ENABLED ADC_IS_ENABLE
bogdanm	0:9b334a45a8ff	870	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
bogdanm	0:9b334a45a8ff	871	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
bogdanm	0:9b334a45a8ff	872	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
bogdanm	0:9b334a45a8ff	873	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
bogdanm	0:9b334a45a8ff	874	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
bogdanm	0:9b334a45a8ff	875	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
bogdanm	0:9b334a45a8ff	876	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
bogdanm	0:9b334a45a8ff	879	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
bogdanm	0:9b334a45a8ff	880	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
bogdanm	0:9b334a45a8ff	881	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
bogdanm	0:9b334a45a8ff	882	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
bogdanm	0:9b334a45a8ff	883	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
bogdanm	0:9b334a45a8ff	884	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
bogdanm	0:9b334a45a8ff	885	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
bogdanm	0:9b334a45a8ff	886	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
bogdanm	0:9b334a45a8ff	887	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
bogdanm	0:9b334a45a8ff	888	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
bogdanm	0:9b334a45a8ff	889	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
bogdanm	0:9b334a45a8ff	890	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
bogdanm	0:9b334a45a8ff	891	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
bogdanm	0:9b334a45a8ff	892	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
bogdanm	0:9b334a45a8ff	893	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
bogdanm	0:9b334a45a8ff	894	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
bogdanm	0:9b334a45a8ff	895	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
bogdanm	0:9b334a45a8ff	896	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
bogdanm	0:9b334a45a8ff	897	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
bogdanm	0:9b334a45a8ff	898
bogdanm	0:9b334a45a8ff	899	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
bogdanm	0:9b334a45a8ff	900	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
bogdanm	0:9b334a45a8ff	901	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
bogdanm	0:9b334a45a8ff	902	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
bogdanm	0:9b334a45a8ff	903	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
bogdanm	0:9b334a45a8ff	904	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
bogdanm	0:9b334a45a8ff	905	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
bogdanm	0:9b334a45a8ff	906	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
bogdanm	0:9b334a45a8ff	907	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
bogdanm	0:9b334a45a8ff	908	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
bogdanm	0:9b334a45a8ff	911	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
bogdanm	0:9b334a45a8ff	912	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
bogdanm	0:9b334a45a8ff	913	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
bogdanm	0:9b334a45a8ff	914	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
bogdanm	0:9b334a45a8ff	915	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
bogdanm	0:9b334a45a8ff	916	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
bogdanm	0:9b334a45a8ff	917	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
bogdanm	0:9b334a45a8ff	918
bogdanm	0:9b334a45a8ff	919	#define __HAL_ADC_SQR1 ADC_SQR1
bogdanm	0:9b334a45a8ff	920	#define __HAL_ADC_SMPR1 ADC_SMPR1
bogdanm	0:9b334a45a8ff	921	#define __HAL_ADC_SMPR2 ADC_SMPR2
bogdanm	0:9b334a45a8ff	922	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
bogdanm	0:9b334a45a8ff	923	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
bogdanm	0:9b334a45a8ff	924	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
bogdanm	0:9b334a45a8ff	925	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
bogdanm	0:9b334a45a8ff	926	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
bogdanm	0:9b334a45a8ff	927	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
bogdanm	0:9b334a45a8ff	928	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
bogdanm	0:9b334a45a8ff	929	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
bogdanm	0:9b334a45a8ff	930	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
bogdanm	0:9b334a45a8ff	931	#define __HAL_ADC_JSQR ADC_JSQR
bogdanm	0:9b334a45a8ff	932
bogdanm	0:9b334a45a8ff	933	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
bogdanm	0:9b334a45a8ff	934	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
bogdanm	0:9b334a45a8ff	935	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
bogdanm	0:9b334a45a8ff	936	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
bogdanm	0:9b334a45a8ff	937	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
bogdanm	0:9b334a45a8ff	938	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
bogdanm	0:9b334a45a8ff	939	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
bogdanm	0:9b334a45a8ff	940	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	/**
bogdanm	0:9b334a45a8ff	943	* @}
bogdanm	0:9b334a45a8ff	944	*/
bogdanm	0:9b334a45a8ff	945
bogdanm	0:9b334a45a8ff	946	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	947	* @{
bogdanm	0:9b334a45a8ff	948	*/
bogdanm	0:9b334a45a8ff	949	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
bogdanm	0:9b334a45a8ff	950	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
bogdanm	0:9b334a45a8ff	951	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
bogdanm	0:9b334a45a8ff	952
bogdanm	0:9b334a45a8ff	953	/**
bogdanm	0:9b334a45a8ff	954	* @}
bogdanm	0:9b334a45a8ff	955	*/
bogdanm	0:9b334a45a8ff	956
bogdanm	0:9b334a45a8ff	957	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	958	* @{
bogdanm	0:9b334a45a8ff	959	*/
bogdanm	0:9b334a45a8ff	960	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
bogdanm	0:9b334a45a8ff	961	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
bogdanm	0:9b334a45a8ff	962	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
bogdanm	0:9b334a45a8ff	963	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
bogdanm	0:9b334a45a8ff	964	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
bogdanm	0:9b334a45a8ff	965	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
bogdanm	0:9b334a45a8ff	966	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
bogdanm	0:9b334a45a8ff	967	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
bogdanm	0:9b334a45a8ff	968	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
bogdanm	0:9b334a45a8ff	969	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
bogdanm	0:9b334a45a8ff	970	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
bogdanm	0:9b334a45a8ff	971	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
bogdanm	0:9b334a45a8ff	972	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
bogdanm	0:9b334a45a8ff	973	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
bogdanm	0:9b334a45a8ff	974	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
bogdanm	0:9b334a45a8ff	975	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
bogdanm	0:9b334a45a8ff	976
bogdanm	0:9b334a45a8ff	977	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
bogdanm	0:9b334a45a8ff	978	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
bogdanm	0:9b334a45a8ff	979	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
bogdanm	0:9b334a45a8ff	980	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
bogdanm	0:9b334a45a8ff	981	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
bogdanm	0:9b334a45a8ff	982	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
bogdanm	0:9b334a45a8ff	983	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
bogdanm	0:9b334a45a8ff	984	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
bogdanm	0:9b334a45a8ff	985	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
bogdanm	0:9b334a45a8ff	986	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
bogdanm	0:9b334a45a8ff	987	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
bogdanm	0:9b334a45a8ff	988	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
bogdanm	0:9b334a45a8ff	989	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
bogdanm	0:9b334a45a8ff	990	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992
bogdanm	0:9b334a45a8ff	993	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
bogdanm	0:9b334a45a8ff	994	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
bogdanm	0:9b334a45a8ff	995	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
bogdanm	0:9b334a45a8ff	996	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
bogdanm	0:9b334a45a8ff	997	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
bogdanm	0:9b334a45a8ff	998	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
bogdanm	0:9b334a45a8ff	999	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
bogdanm	0:9b334a45a8ff	1000	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
bogdanm	0:9b334a45a8ff	1001	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
bogdanm	0:9b334a45a8ff	1002	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
bogdanm	0:9b334a45a8ff	1003	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
bogdanm	0:9b334a45a8ff	1004	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
bogdanm	0:9b334a45a8ff	1005	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
bogdanm	0:9b334a45a8ff	1006	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
bogdanm	0:9b334a45a8ff	1007	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
bogdanm	0:9b334a45a8ff	1008	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
bogdanm	0:9b334a45a8ff	1009	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
bogdanm	0:9b334a45a8ff	1010	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
bogdanm	0:9b334a45a8ff	1011	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
bogdanm	0:9b334a45a8ff	1012	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
bogdanm	0:9b334a45a8ff	1013	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
bogdanm	0:9b334a45a8ff	1014	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
bogdanm	0:9b334a45a8ff	1015	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
bogdanm	0:9b334a45a8ff	1016	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/**
bogdanm	0:9b334a45a8ff	1019	* @}
bogdanm	0:9b334a45a8ff	1020	*/
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1023	* @{
bogdanm	0:9b334a45a8ff	1024	*/
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
bogdanm	0:9b334a45a8ff	1027	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
bogdanm	0:9b334a45a8ff	1028	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
bogdanm	0:9b334a45a8ff	1029	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
bogdanm	0:9b334a45a8ff	1030	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
bogdanm	0:9b334a45a8ff	1031	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
bogdanm	0:9b334a45a8ff	1032	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
bogdanm	0:9b334a45a8ff	1033	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
bogdanm	0:9b334a45a8ff	1034	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
bogdanm	0:9b334a45a8ff	1035	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
bogdanm	0:9b334a45a8ff	1036	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
bogdanm	0:9b334a45a8ff	1037	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
bogdanm	0:9b334a45a8ff	1038	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
bogdanm	0:9b334a45a8ff	1039	__HAL_COMP_COMP2_EXTI_GET_FLAG())
bogdanm	0:9b334a45a8ff	1040	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
bogdanm	0:9b334a45a8ff	1041	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
bogdanm	0:9b334a45a8ff	1042	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
bogdanm	0:9b334a45a8ff	1043
bogdanm	0:9b334a45a8ff	1044	/**
bogdanm	0:9b334a45a8ff	1045	* @}
bogdanm	0:9b334a45a8ff	1046	*/
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1049	* @{
bogdanm	0:9b334a45a8ff	1050	*/
bogdanm	0:9b334a45a8ff	1051
bogdanm	0:9b334a45a8ff	1052	#define IS_WRPAREA IS_OB_WRPAREA
bogdanm	0:9b334a45a8ff	1053	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
bogdanm	0:9b334a45a8ff	1054	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
bogdanm	0:9b334a45a8ff	1055	#define IS_TYPEERASE IS_FLASH_TYPEERASE
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	/**
bogdanm	0:9b334a45a8ff	1058	* @}
bogdanm	0:9b334a45a8ff	1059	*/
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1062	* @{
bogdanm	0:9b334a45a8ff	1063	*/
bogdanm	0:9b334a45a8ff	1064
bogdanm	0:9b334a45a8ff	1065	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
bogdanm	0:9b334a45a8ff	1066	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
bogdanm	0:9b334a45a8ff	1067	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
bogdanm	0:9b334a45a8ff	1068	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
bogdanm	0:9b334a45a8ff	1069	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
bogdanm	0:9b334a45a8ff	1070	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
bogdanm	0:9b334a45a8ff	1071	#define __HAL_I2C_SPEED I2C_SPEED
bogdanm	0:9b334a45a8ff	1072	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
bogdanm	0:9b334a45a8ff	1073	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
bogdanm	0:9b334a45a8ff	1074	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
bogdanm	0:9b334a45a8ff	1075	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
bogdanm	0:9b334a45a8ff	1076	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
bogdanm	0:9b334a45a8ff	1077	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
bogdanm	0:9b334a45a8ff	1078	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
bogdanm	0:9b334a45a8ff	1079	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
bogdanm	0:9b334a45a8ff	1080	/**
bogdanm	0:9b334a45a8ff	1081	* @}
bogdanm	0:9b334a45a8ff	1082	*/
bogdanm	0:9b334a45a8ff	1083
bogdanm	0:9b334a45a8ff	1084	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1085	* @{
bogdanm	0:9b334a45a8ff	1086	*/
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
bogdanm	0:9b334a45a8ff	1089	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	/**
bogdanm	0:9b334a45a8ff	1092	* @}
bogdanm	0:9b334a45a8ff	1093	*/
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1096	* @{
bogdanm	0:9b334a45a8ff	1097	*/
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
bogdanm	0:9b334a45a8ff	1100	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
bogdanm	0:9b334a45a8ff	1101
bogdanm	0:9b334a45a8ff	1102	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1103	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	1104	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1105	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109
bogdanm	0:9b334a45a8ff	1110	/**
bogdanm	0:9b334a45a8ff	1111	* @}
bogdanm	0:9b334a45a8ff	1112	*/
bogdanm	0:9b334a45a8ff	1113
bogdanm	0:9b334a45a8ff	1114
bogdanm	0:9b334a45a8ff	1115	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1116	* @{
bogdanm	0:9b334a45a8ff	1117	*/
bogdanm	0:9b334a45a8ff	1118	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
bogdanm	0:9b334a45a8ff	1119	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
bogdanm	0:9b334a45a8ff	1120	/**
bogdanm	0:9b334a45a8ff	1121	* @}
bogdanm	0:9b334a45a8ff	1122	*/
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124
bogdanm	0:9b334a45a8ff	1125	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1126	* @{
bogdanm	0:9b334a45a8ff	1127	*/
bogdanm	0:9b334a45a8ff	1128
bogdanm	0:9b334a45a8ff	1129	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
bogdanm	0:9b334a45a8ff	1130	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
bogdanm	0:9b334a45a8ff	1131	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
bogdanm	0:9b334a45a8ff	1132
bogdanm	0:9b334a45a8ff	1133	/**
bogdanm	0:9b334a45a8ff	1134	* @}
bogdanm	0:9b334a45a8ff	1135	*/
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1138	* @{
bogdanm	0:9b334a45a8ff	1139	*/
bogdanm	0:9b334a45a8ff	1140	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
bogdanm	0:9b334a45a8ff	1141	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
bogdanm	0:9b334a45a8ff	1142	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1143	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1144	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1145	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1146	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
bogdanm	0:9b334a45a8ff	1147	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
bogdanm	0:9b334a45a8ff	1148	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
bogdanm	0:9b334a45a8ff	1149	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
bogdanm	0:9b334a45a8ff	1150	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
bogdanm	0:9b334a45a8ff	1151	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
bogdanm	0:9b334a45a8ff	1152	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
bogdanm	0:9b334a45a8ff	1153	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
bogdanm	0:9b334a45a8ff	1154	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
bogdanm	0:9b334a45a8ff	1155	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
bogdanm	0:9b334a45a8ff	1156	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
bogdanm	0:9b334a45a8ff	1157	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
bogdanm	0:9b334a45a8ff	1158	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
bogdanm	0:9b334a45a8ff	1159	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1160	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1161	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1162	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1163	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1164	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	1165	#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
bogdanm	0:9b334a45a8ff	1166	#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
bogdanm	0:9b334a45a8ff	1167	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
bogdanm	0:9b334a45a8ff	1168	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
bogdanm	0:9b334a45a8ff	1169	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
bogdanm	0:9b334a45a8ff	1170	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
bogdanm	0:9b334a45a8ff	1171	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1172	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	1173	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
bogdanm	0:9b334a45a8ff	1174	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	#if defined (STM32F4)
bogdanm	0:9b334a45a8ff	1177	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
bogdanm	0:9b334a45a8ff	1178	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
bogdanm	0:9b334a45a8ff	1179	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
bogdanm	0:9b334a45a8ff	1180	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
bogdanm	0:9b334a45a8ff	1181	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
bogdanm	0:9b334a45a8ff	1182	#else
bogdanm	0:9b334a45a8ff	1183	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	1184	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	1185	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	1186	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
bogdanm	0:9b334a45a8ff	1187	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	1188	#endif /* STM32F4 */
bogdanm	0:9b334a45a8ff	1189	/**
bogdanm	0:9b334a45a8ff	1190	* @}
bogdanm	0:9b334a45a8ff	1191	*/
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	/** @defgroup HAL_RCC_Aliased_Macros HAL RCC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1195	* @{
bogdanm	0:9b334a45a8ff	1196	*/
bogdanm	0:9b334a45a8ff	1197	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1198	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1199	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1200	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1201	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1202	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1203	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1204	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1205	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1206	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1207	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1208	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1209	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1210	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1211	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1212	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1213	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1214	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1215	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1216	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1217	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1218	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1219	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
bogdanm	0:9b334a45a8ff	1220	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1221	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1222	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1223	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1224	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1225	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
bogdanm	0:9b334a45a8ff	1226	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1227	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1228	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1229	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
bogdanm	0:9b334a45a8ff	1230	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1231	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
bogdanm	0:9b334a45a8ff	1232	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1233	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1234	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1235	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1236	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1237	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1238	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1239	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1240	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1241	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1242	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1243	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1244	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1245	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
bogdanm	0:9b334a45a8ff	1246	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1247	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1248	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1249	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1250	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1251	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1252	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1253	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1254	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1255	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1256	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1257	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1258	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1259	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1260	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1261	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1262	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1263	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1264	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1265	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1266	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1267	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1268	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1269	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1270	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1271	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1272	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1273	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1274	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1275	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1276	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1277	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1278	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1279	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1280	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1281	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
bogdanm	0:9b334a45a8ff	1282	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1283	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1284	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1285	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1286	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1287	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1288	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1289	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1290	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1291	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1292	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1293	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1294	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1295	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1296	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1297	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1298	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1299	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1300	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1301	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1302	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1303	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1304	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1305	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1306	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1307	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1308	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1309	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
bogdanm	0:9b334a45a8ff	1310	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1311	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1312	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1313	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1314	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1315	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1316	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1317	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1318	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1319	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1320	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1321	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1322	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1323	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1324	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1325	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
bogdanm	0:9b334a45a8ff	1326	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1327	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1328	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1329	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1330	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1331	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
bogdanm	0:9b334a45a8ff	1332	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1333	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1334	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1335	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1336	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1337	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1338	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1339	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1340	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1341	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1342	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1343	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
bogdanm	0:9b334a45a8ff	1344	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1345	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1346	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1347	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1348	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1349	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
bogdanm	0:9b334a45a8ff	1350	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1351	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1352	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1353	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1354	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1355	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
bogdanm	0:9b334a45a8ff	1356	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1357	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1358	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1359	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1360	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1361	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
bogdanm	0:9b334a45a8ff	1362	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1363	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1364	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1365	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1366	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1367	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
bogdanm	0:9b334a45a8ff	1368	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1369	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1370	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1371	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1372	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1373	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1374	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1375	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1376	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1377	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1378	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1379	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1380	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1381	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1382	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1383	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1384	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1385	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1386	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1387	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1388	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1389	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1390	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1391	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
bogdanm	0:9b334a45a8ff	1392	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1393	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1394	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1395	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1396	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1397	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1398	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1399	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1400	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1401	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1402	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1403	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1404	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1405	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1406	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1407	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1408	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1409	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1410	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1411	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1412	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1413	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1414	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1415	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
bogdanm	0:9b334a45a8ff	1416	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1417	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1418	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1419	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1420	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1421	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
bogdanm	0:9b334a45a8ff	1422	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1423	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1424	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1425	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1426	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1427	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
bogdanm	0:9b334a45a8ff	1428	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1429	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1430	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1431	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1432	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1433	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
bogdanm	0:9b334a45a8ff	1434	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1435	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1436	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1437	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1438	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1439	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
bogdanm	0:9b334a45a8ff	1440	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1441	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1442	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1443	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1444	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1445	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1446	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1447	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1448	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1449	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1450	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1451	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1452	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1453	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1454	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1455	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1456	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1457	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1458	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1459	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1460	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1461	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1462	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1463	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1464	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1465	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1466	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1467	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1468	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1469	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1470	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1471	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1472	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1473	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1474	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1475	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1476	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1477	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1478	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1479	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1480	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1481	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1482	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1483	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1484	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1485	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1486	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1487	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1488	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1489	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1490	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1491	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1492	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1493	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1494	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1495	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
bogdanm	0:9b334a45a8ff	1496	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1497	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1498	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1499	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1500	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1501	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1502	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1503	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1504	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1505	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
bogdanm	0:9b334a45a8ff	1506	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1507	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1508	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1509	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
bogdanm	0:9b334a45a8ff	1510	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1511	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1512	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1513	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
bogdanm	0:9b334a45a8ff	1514	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1515	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1516	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1517	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
bogdanm	0:9b334a45a8ff	1518	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1519	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1520	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1521	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
bogdanm	0:9b334a45a8ff	1522	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1523	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1524	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1525	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1526	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1527	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
bogdanm	0:9b334a45a8ff	1528	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1529	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1530	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1531	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1532	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1533	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
bogdanm	0:9b334a45a8ff	1534	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1535	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1536	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1537	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1538	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1539	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
bogdanm	0:9b334a45a8ff	1540	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1541	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1542	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1543	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1544	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1545	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1546	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1547	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1548	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1549	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1550	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1551	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1552	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1553	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1554	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1555	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1556	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1557	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
bogdanm	0:9b334a45a8ff	1558	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1559	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1560	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1561	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1562	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1563	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
bogdanm	0:9b334a45a8ff	1564	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1565	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1566	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1567	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1568	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1569	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
bogdanm	0:9b334a45a8ff	1570	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1571	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1572	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1573	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1574	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1575	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
bogdanm	0:9b334a45a8ff	1576	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1577	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1578	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1579	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1580	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1581	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
bogdanm	0:9b334a45a8ff	1582	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1583	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1584	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1585	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
bogdanm	0:9b334a45a8ff	1586	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1587	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1588	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1589	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1590	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1591	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1592	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1593	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1594	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1595	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1596	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1597	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
bogdanm	0:9b334a45a8ff	1598	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1599	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1600	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1601	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1602	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1603	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
bogdanm	0:9b334a45a8ff	1604	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1605	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1606	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1607	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1608	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1609	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
bogdanm	0:9b334a45a8ff	1610	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1611	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1612	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1613	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1614	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1615	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
bogdanm	0:9b334a45a8ff	1616	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1617	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1618	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1619	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1620	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1621	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
bogdanm	0:9b334a45a8ff	1622	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1623	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1624	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1625	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
bogdanm	0:9b334a45a8ff	1626	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1627	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1628	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1629	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1630	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1631	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1632	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1633	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
bogdanm	0:9b334a45a8ff	1634	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1635	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1636	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1637	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
bogdanm	0:9b334a45a8ff	1638	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1639	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1640	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1641	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1642	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1643	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
bogdanm	0:9b334a45a8ff	1644	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1645	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1646	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1647	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1648	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1649	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1650	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1651	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
bogdanm	0:9b334a45a8ff	1652	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1653	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
bogdanm	0:9b334a45a8ff	1654	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
bogdanm	0:9b334a45a8ff	1655
bogdanm	0:9b334a45a8ff	1656	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
bogdanm	0:9b334a45a8ff	1657	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1658	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1659	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1660	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1661	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1662	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1663	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1664	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1665	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1666	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1667	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1668	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1669	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1670	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1671	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1672	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1673	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1674	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1675	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1676	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1677	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1678	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
bogdanm	0:9b334a45a8ff	1679	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1680	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1681	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1682	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1683	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1684	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1685	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
bogdanm	0:9b334a45a8ff	1686	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1687	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1688	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1689	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1690	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1691	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
bogdanm	0:9b334a45a8ff	1692	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1693	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1694	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1695	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1696	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1697	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1698	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1699	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1700	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1701	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1702	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1703	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1704	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1705	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1706	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1707	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1708	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1709	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1710	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1711	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1712	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1713	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1714	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1715	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1716	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1717	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1718	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1719	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1720	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
bogdanm	0:9b334a45a8ff	1721	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1722	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1723	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1724	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1725	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1726	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
bogdanm	0:9b334a45a8ff	1727	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1728	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1729	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1730	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1731	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1732	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
bogdanm	0:9b334a45a8ff	1733	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1734	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1735	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1736	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1737	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1738	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
bogdanm	0:9b334a45a8ff	1739	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1740	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1741	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1742	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1743	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1744	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1745	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1746	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1747	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1748	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1749	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1750	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1751	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
bogdanm	0:9b334a45a8ff	1752	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1753	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1754	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1755	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1756	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1757	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1758	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
bogdanm	0:9b334a45a8ff	1759	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1760	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1761	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1762	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1763	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
bogdanm	0:9b334a45a8ff	1764	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1765	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1766	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1767	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1768	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1769	#define __OTGHS_FORCE_RESET __HAL_RCC_OTGHS_FORCE_RESET
bogdanm	0:9b334a45a8ff	1770	#define __OTGHS_RELEASE_RESET __HAL_RCC_OTGHS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1771	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1772	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1773	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
bogdanm	0:9b334a45a8ff	1774	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1775	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1776	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1777	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1778	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1779	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1780	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1781	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1782	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1783	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
bogdanm	0:9b334a45a8ff	1784	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1785	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1786	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1787	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
bogdanm	0:9b334a45a8ff	1788	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1789	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1790	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1791	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
bogdanm	0:9b334a45a8ff	1792	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
bogdanm	0:9b334a45a8ff	1793	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
bogdanm	0:9b334a45a8ff	1794	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1795	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
bogdanm	0:9b334a45a8ff	1796	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
bogdanm	0:9b334a45a8ff	1797
bogdanm	0:9b334a45a8ff	1798	/* alias define maintained for legacy */
bogdanm	0:9b334a45a8ff	1799	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
bogdanm	0:9b334a45a8ff	1800	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
bogdanm	0:9b334a45a8ff	1801
bogdanm	0:9b334a45a8ff	1802	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
bogdanm	0:9b334a45a8ff	1803	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
bogdanm	0:9b334a45a8ff	1804
bogdanm	0:9b334a45a8ff	1805	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
bogdanm	0:9b334a45a8ff	1806
bogdanm	0:9b334a45a8ff	1807	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1808	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1809	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1810	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1811	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1812	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1813	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1814	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1815	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1816	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
bogdanm	0:9b334a45a8ff	1817
bogdanm	0:9b334a45a8ff	1818	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
bogdanm	0:9b334a45a8ff	1819	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
bogdanm	0:9b334a45a8ff	1820	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
bogdanm	0:9b334a45a8ff	1821	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
bogdanm	0:9b334a45a8ff	1822	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	1823	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
bogdanm	0:9b334a45a8ff	1824
bogdanm	0:9b334a45a8ff	1825	#define CR_HSION_BB RCC_CR_HSION_BB
bogdanm	0:9b334a45a8ff	1826	#define CR_CSSON_BB RCC_CR_CSSON_BB
bogdanm	0:9b334a45a8ff	1827	#define CR_PLLON_BB RCC_CR_PLLON_BB
bogdanm	0:9b334a45a8ff	1828	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
bogdanm	0:9b334a45a8ff	1829	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
bogdanm	0:9b334a45a8ff	1830	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
bogdanm	0:9b334a45a8ff	1831	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
bogdanm	0:9b334a45a8ff	1832	#define CSR_LSION_BB RCC_CSR_LSION_BB
bogdanm	0:9b334a45a8ff	1833	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
bogdanm	0:9b334a45a8ff	1834	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
bogdanm	0:9b334a45a8ff	1835
bogdanm	0:9b334a45a8ff	1836	/**
bogdanm	0:9b334a45a8ff	1837	* @}
bogdanm	0:9b334a45a8ff	1838	*/
bogdanm	0:9b334a45a8ff	1839
bogdanm	0:9b334a45a8ff	1840	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1841	* @{
bogdanm	0:9b334a45a8ff	1842	*/
bogdanm	0:9b334a45a8ff	1843	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback(__HANDLE__, uint32_t random32bit)
bogdanm	0:9b334a45a8ff	1844
bogdanm	0:9b334a45a8ff	1845	/**
bogdanm	0:9b334a45a8ff	1846	* @}
bogdanm	0:9b334a45a8ff	1847	*/
bogdanm	0:9b334a45a8ff	1848
bogdanm	0:9b334a45a8ff	1849	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1850	* @{
bogdanm	0:9b334a45a8ff	1851	*/
bogdanm	0:9b334a45a8ff	1852
bogdanm	0:9b334a45a8ff	1853	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	1854	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	1855	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	1856	#if defined (RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
bogdanm	0:9b334a45a8ff	1857	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
bogdanm	0:9b334a45a8ff	1858	((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
bogdanm	0:9b334a45a8ff	1859	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
bogdanm	0:9b334a45a8ff	1860	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
bogdanm	0:9b334a45a8ff	1861	((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
bogdanm	0:9b334a45a8ff	1862	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
bogdanm	0:9b334a45a8ff	1863	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
bogdanm	0:9b334a45a8ff	1864	((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
bogdanm	0:9b334a45a8ff	1865	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
bogdanm	0:9b334a45a8ff	1866	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
bogdanm	0:9b334a45a8ff	1867	((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
bogdanm	0:9b334a45a8ff	1868	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
bogdanm	0:9b334a45a8ff	1869	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
bogdanm	0:9b334a45a8ff	1870	((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
bogdanm	0:9b334a45a8ff	1871	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
bogdanm	0:9b334a45a8ff	1872
bogdanm	0:9b334a45a8ff	1873	#else
bogdanm	0:9b334a45a8ff	1874	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
bogdanm	0:9b334a45a8ff	1875
bogdanm	0:9b334a45a8ff	1876	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
bogdanm	0:9b334a45a8ff	1877
bogdanm	0:9b334a45a8ff	1878	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
bogdanm	0:9b334a45a8ff	1879
bogdanm	0:9b334a45a8ff	1880	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
bogdanm	0:9b334a45a8ff	1881
bogdanm	0:9b334a45a8ff	1882	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
bogdanm	0:9b334a45a8ff	1883
bogdanm	0:9b334a45a8ff	1884	#endif
bogdanm	0:9b334a45a8ff	1885
bogdanm	0:9b334a45a8ff	1886	#define IS_ALARM IS_RTC_ALARM
bogdanm	0:9b334a45a8ff	1887	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
bogdanm	0:9b334a45a8ff	1888	#define IS_TAMPER IS_RTC_TAMPER
bogdanm	0:9b334a45a8ff	1889	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
bogdanm	0:9b334a45a8ff	1890	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
bogdanm	0:9b334a45a8ff	1891	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
bogdanm	0:9b334a45a8ff	1892	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
bogdanm	0:9b334a45a8ff	1893	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
bogdanm	0:9b334a45a8ff	1894	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
bogdanm	0:9b334a45a8ff	1895	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
bogdanm	0:9b334a45a8ff	1896	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
bogdanm	0:9b334a45a8ff	1897	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
bogdanm	0:9b334a45a8ff	1898	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
bogdanm	0:9b334a45a8ff	1899	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
bogdanm	0:9b334a45a8ff	1900
bogdanm	0:9b334a45a8ff	1901	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
bogdanm	0:9b334a45a8ff	1902	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
bogdanm	0:9b334a45a8ff	1903
bogdanm	0:9b334a45a8ff	1904	/**
bogdanm	0:9b334a45a8ff	1905	* @}
bogdanm	0:9b334a45a8ff	1906	*/
bogdanm	0:9b334a45a8ff	1907
bogdanm	0:9b334a45a8ff	1908	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1909	* @{
bogdanm	0:9b334a45a8ff	1910	*/
bogdanm	0:9b334a45a8ff	1911
bogdanm	0:9b334a45a8ff	1912	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
bogdanm	0:9b334a45a8ff	1913	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
bogdanm	0:9b334a45a8ff	1914
bogdanm	0:9b334a45a8ff	1915	/**
bogdanm	0:9b334a45a8ff	1916	* @}
bogdanm	0:9b334a45a8ff	1917	*/
bogdanm	0:9b334a45a8ff	1918
bogdanm	0:9b334a45a8ff	1919	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1920	* @{
bogdanm	0:9b334a45a8ff	1921	*/
bogdanm	0:9b334a45a8ff	1922
bogdanm	0:9b334a45a8ff	1923	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
bogdanm	0:9b334a45a8ff	1924	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
bogdanm	0:9b334a45a8ff	1925	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
bogdanm	0:9b334a45a8ff	1926	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
bogdanm	0:9b334a45a8ff	1927	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
bogdanm	0:9b334a45a8ff	1928	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
bogdanm	0:9b334a45a8ff	1929
bogdanm	0:9b334a45a8ff	1930	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1931	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1932
bogdanm	0:9b334a45a8ff	1933	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	1934
bogdanm	0:9b334a45a8ff	1935	/**
bogdanm	0:9b334a45a8ff	1936	* @}
bogdanm	0:9b334a45a8ff	1937	*/
bogdanm	0:9b334a45a8ff	1938
bogdanm	0:9b334a45a8ff	1939	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1940	* @{
bogdanm	0:9b334a45a8ff	1941	*/
bogdanm	0:9b334a45a8ff	1942	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
bogdanm	0:9b334a45a8ff	1943	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
bogdanm	0:9b334a45a8ff	1944	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
bogdanm	0:9b334a45a8ff	1945	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
bogdanm	0:9b334a45a8ff	1946	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
bogdanm	0:9b334a45a8ff	1947	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
bogdanm	0:9b334a45a8ff	1948	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
bogdanm	0:9b334a45a8ff	1949	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
bogdanm	0:9b334a45a8ff	1950	/**
bogdanm	0:9b334a45a8ff	1951	* @}
bogdanm	0:9b334a45a8ff	1952	*/
bogdanm	0:9b334a45a8ff	1953
bogdanm	0:9b334a45a8ff	1954	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1955	* @{
bogdanm	0:9b334a45a8ff	1956	*/
bogdanm	0:9b334a45a8ff	1957
bogdanm	0:9b334a45a8ff	1958	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
bogdanm	0:9b334a45a8ff	1959	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
bogdanm	0:9b334a45a8ff	1960	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
bogdanm	0:9b334a45a8ff	1961
bogdanm	0:9b334a45a8ff	1962	/**
bogdanm	0:9b334a45a8ff	1963	* @}
bogdanm	0:9b334a45a8ff	1964	*/
bogdanm	0:9b334a45a8ff	1965
bogdanm	0:9b334a45a8ff	1966	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1967	* @{
bogdanm	0:9b334a45a8ff	1968	*/
bogdanm	0:9b334a45a8ff	1969
bogdanm	0:9b334a45a8ff	1970	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1971	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	1972	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1973	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
bogdanm	0:9b334a45a8ff	1974
bogdanm	0:9b334a45a8ff	1975	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
bogdanm	0:9b334a45a8ff	1976
bogdanm	0:9b334a45a8ff	1977	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	1978	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
bogdanm	0:9b334a45a8ff	1979
bogdanm	0:9b334a45a8ff	1980	/**
bogdanm	0:9b334a45a8ff	1981	* @}
bogdanm	0:9b334a45a8ff	1982	*/
bogdanm	0:9b334a45a8ff	1983
bogdanm	0:9b334a45a8ff	1984
bogdanm	0:9b334a45a8ff	1985	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	1986	* @{
bogdanm	0:9b334a45a8ff	1987	*/
bogdanm	0:9b334a45a8ff	1988
bogdanm	0:9b334a45a8ff	1989	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
bogdanm	0:9b334a45a8ff	1990	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
bogdanm	0:9b334a45a8ff	1991	#define __USART_ENABLE __HAL_USART_ENABLE
bogdanm	0:9b334a45a8ff	1992	#define __USART_DISABLE __HAL_USART_DISABLE
bogdanm	0:9b334a45a8ff	1993
bogdanm	0:9b334a45a8ff	1994	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1995	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
bogdanm	0:9b334a45a8ff	1996
bogdanm	0:9b334a45a8ff	1997	/**
bogdanm	0:9b334a45a8ff	1998	* @}
bogdanm	0:9b334a45a8ff	1999	*/
bogdanm	0:9b334a45a8ff	2000
bogdanm	0:9b334a45a8ff	2001	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2002	* @{
bogdanm	0:9b334a45a8ff	2003	*/
bogdanm	0:9b334a45a8ff	2004	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
bogdanm	0:9b334a45a8ff	2005
bogdanm	0:9b334a45a8ff	2006	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
bogdanm	0:9b334a45a8ff	2007	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2008	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2009	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
bogdanm	0:9b334a45a8ff	2010
bogdanm	0:9b334a45a8ff	2011	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
bogdanm	0:9b334a45a8ff	2012	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2013	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2014	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
bogdanm	0:9b334a45a8ff	2015
bogdanm	0:9b334a45a8ff	2016	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	2017	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	2018	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	2019	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2020	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	2021	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2022	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2023
bogdanm	0:9b334a45a8ff	2024	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	2025	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	2026	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	2027	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2028	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	2029	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2030	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2031	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
bogdanm	0:9b334a45a8ff	2032
bogdanm	0:9b334a45a8ff	2033	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	2034	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	2035	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	2036	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2037	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
bogdanm	0:9b334a45a8ff	2038	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2039	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
bogdanm	0:9b334a45a8ff	2040	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
bogdanm	0:9b334a45a8ff	2041
bogdanm	0:9b334a45a8ff	2042	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
bogdanm	0:9b334a45a8ff	2043	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
bogdanm	0:9b334a45a8ff	2044
bogdanm	0:9b334a45a8ff	2045	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
bogdanm	0:9b334a45a8ff	2046	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
bogdanm	0:9b334a45a8ff	2047	/**
bogdanm	0:9b334a45a8ff	2048	* @}
bogdanm	0:9b334a45a8ff	2049	*/
bogdanm	0:9b334a45a8ff	2050
bogdanm	0:9b334a45a8ff	2051	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2052	* @{
bogdanm	0:9b334a45a8ff	2053	*/
bogdanm	0:9b334a45a8ff	2054	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
bogdanm	0:9b334a45a8ff	2055	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
bogdanm	0:9b334a45a8ff	2056
bogdanm	0:9b334a45a8ff	2057	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
bogdanm	0:9b334a45a8ff	2058	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
bogdanm	0:9b334a45a8ff	2059
bogdanm	0:9b334a45a8ff	2060	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
bogdanm	0:9b334a45a8ff	2061	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
bogdanm	0:9b334a45a8ff	2062	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
bogdanm	0:9b334a45a8ff	2063	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
bogdanm	0:9b334a45a8ff	2064	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
bogdanm	0:9b334a45a8ff	2065	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
bogdanm	0:9b334a45a8ff	2066	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
bogdanm	0:9b334a45a8ff	2067	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
bogdanm	0:9b334a45a8ff	2068	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
bogdanm	0:9b334a45a8ff	2069	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
bogdanm	0:9b334a45a8ff	2070	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
bogdanm	0:9b334a45a8ff	2071	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
bogdanm	0:9b334a45a8ff	2072
bogdanm	0:9b334a45a8ff	2073	#define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	2074	#define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm	0:9b334a45a8ff	2075	#define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm	0:9b334a45a8ff	2076	#define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm	0:9b334a45a8ff	2077	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	2078	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	2079	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	2080	((SELECTION) == TIM_TS_ITR3))
bogdanm	0:9b334a45a8ff	2081
bogdanm	0:9b334a45a8ff	2082	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	2083	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	2084	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	2085	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	2086
bogdanm	0:9b334a45a8ff	2087	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	2088	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm	0:9b334a45a8ff	2089
bogdanm	0:9b334a45a8ff	2090	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	2091	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
bogdanm	0:9b334a45a8ff	2092
bogdanm	0:9b334a45a8ff	2093	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	2094	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm	0:9b334a45a8ff	2095
bogdanm	0:9b334a45a8ff	2096	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	2097	((STATE) == TIM_OUTPUTSTATE_ENABLE))
bogdanm	0:9b334a45a8ff	2098	/**
bogdanm	0:9b334a45a8ff	2099	* @}
bogdanm	0:9b334a45a8ff	2100	*/
bogdanm	0:9b334a45a8ff	2101
bogdanm	0:9b334a45a8ff	2102	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2103	* @{
bogdanm	0:9b334a45a8ff	2104	*/
bogdanm	0:9b334a45a8ff	2105
bogdanm	0:9b334a45a8ff	2106	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
bogdanm	0:9b334a45a8ff	2107	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
bogdanm	0:9b334a45a8ff	2108	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
bogdanm	0:9b334a45a8ff	2109	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
bogdanm	0:9b334a45a8ff	2110	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
bogdanm	0:9b334a45a8ff	2111	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
bogdanm	0:9b334a45a8ff	2112	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
bogdanm	0:9b334a45a8ff	2113
bogdanm	0:9b334a45a8ff	2114	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
bogdanm	0:9b334a45a8ff	2115	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
bogdanm	0:9b334a45a8ff	2116	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
bogdanm	0:9b334a45a8ff	2117	/**
bogdanm	0:9b334a45a8ff	2118	* @}
bogdanm	0:9b334a45a8ff	2119	*/
bogdanm	0:9b334a45a8ff	2120
bogdanm	0:9b334a45a8ff	2121	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2122	* @{
bogdanm	0:9b334a45a8ff	2123	*/
bogdanm	0:9b334a45a8ff	2124	#define __HAL_LTDC_LAYER LTDC_LAYER
bogdanm	0:9b334a45a8ff	2125	/**
bogdanm	0:9b334a45a8ff	2126	* @}
bogdanm	0:9b334a45a8ff	2127	*/
bogdanm	0:9b334a45a8ff	2128
bogdanm	0:9b334a45a8ff	2129	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2130	* @{
bogdanm	0:9b334a45a8ff	2131	*/
bogdanm	0:9b334a45a8ff	2132	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
bogdanm	0:9b334a45a8ff	2133	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
bogdanm	0:9b334a45a8ff	2134	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
bogdanm	0:9b334a45a8ff	2135	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
bogdanm	0:9b334a45a8ff	2136	#define SAI_STREOMODE SAI_STEREOMODE
bogdanm	0:9b334a45a8ff	2137	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
bogdanm	0:9b334a45a8ff	2138	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
bogdanm	0:9b334a45a8ff	2139	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
bogdanm	0:9b334a45a8ff	2140	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
bogdanm	0:9b334a45a8ff	2141	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
bogdanm	0:9b334a45a8ff	2142	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
bogdanm	0:9b334a45a8ff	2143	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
bogdanm	0:9b334a45a8ff	2144
bogdanm	0:9b334a45a8ff	2145	/**
bogdanm	0:9b334a45a8ff	2146	* @}
bogdanm	0:9b334a45a8ff	2147	*/
bogdanm	0:9b334a45a8ff	2148
bogdanm	0:9b334a45a8ff	2149
bogdanm	0:9b334a45a8ff	2150	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
bogdanm	0:9b334a45a8ff	2151	* @{
bogdanm	0:9b334a45a8ff	2152	*/
bogdanm	0:9b334a45a8ff	2153
bogdanm	0:9b334a45a8ff	2154	/**
bogdanm	0:9b334a45a8ff	2155	* @}
bogdanm	0:9b334a45a8ff	2156	*/
bogdanm	0:9b334a45a8ff	2157
bogdanm	0:9b334a45a8ff	2158	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	2159	}
bogdanm	0:9b334a45a8ff	2160	#endif
bogdanm	0:9b334a45a8ff	2161
bogdanm	0:9b334a45a8ff	2162	#endif /* ___STM32_HAL_LEGACY */
bogdanm	0:9b334a45a8ff	2163
bogdanm	0:9b334a45a8ff	2164	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	2165

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32_hal_legacy.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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