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fix LPC812 PWM

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Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nor.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
124:6a4a5b7d7324
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_nor.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 15-December-2014
bogdanm 0:9b334a45a8ff 7 * @brief NOR HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive NOR memories mounted
bogdanm 0:9b334a45a8ff 9 * as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control NOR flash memories. It uses the FSMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with NOR devices. This driver is used as follows:
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
bogdanm 0:9b334a45a8ff 21 with control and timing parameters for both normal and extended mode.
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (+) Read NOR flash memory manufacturer code and device IDs using the function
bogdanm 0:9b334a45a8ff 24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
bogdanm 0:9b334a45a8ff 25 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 (+) Access NOR flash memory by read/write data unit operations using the functions
bogdanm 0:9b334a45a8ff 28 HAL_NOR_Read(), HAL_NOR_Program().
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 (+) Perform NOR flash erase block/chip operations using the functions
bogdanm 0:9b334a45a8ff 31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
bogdanm 0:9b334a45a8ff 34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
bogdanm 0:9b334a45a8ff 35 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
bogdanm 0:9b334a45a8ff 38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (+) You can monitor the NOR device HAL state by calling the function
bogdanm 0:9b334a45a8ff 41 HAL_NOR_GetState()
bogdanm 0:9b334a45a8ff 42 [..]
bogdanm 0:9b334a45a8ff 43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
bogdanm 0:9b334a45a8ff 44 If a NOR flash device contains different operations and/or implementations,
bogdanm 0:9b334a45a8ff 45 it should be implemented separately.
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 *** NOR HAL driver macros list ***
bogdanm 0:9b334a45a8ff 48 =============================================
bogdanm 0:9b334a45a8ff 49 [..]
bogdanm 0:9b334a45a8ff 50 Below the list of most used macros in NOR HAL driver.
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 (+) __NOR_WRITE : NOR memory write data to specified address
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 @endverbatim
bogdanm 0:9b334a45a8ff 55 ******************************************************************************
bogdanm 0:9b334a45a8ff 56 * @attention
bogdanm 0:9b334a45a8ff 57 *
bogdanm 0:9b334a45a8ff 58 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 59 *
bogdanm 0:9b334a45a8ff 60 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 61 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 62 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 63 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 65 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 66 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 68 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 69 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 81 *
bogdanm 0:9b334a45a8ff 82 ******************************************************************************
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 86 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 #ifdef HAL_NOR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 93 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 /** @defgroup NOR NOR
bogdanm 0:9b334a45a8ff 96 * @brief NOR driver modules
bogdanm 0:9b334a45a8ff 97 * @{
bogdanm 0:9b334a45a8ff 98 */
bogdanm 0:9b334a45a8ff 99 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 100 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 101 /** @defgroup NOR_Private_Constants NOR Private Constants
bogdanm 0:9b334a45a8ff 102 * @{
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /* Constants to define address to set to write a command */
bogdanm 0:9b334a45a8ff 106 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 107 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 108 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
bogdanm 0:9b334a45a8ff 109 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 110 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 111 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
bogdanm 0:9b334a45a8ff 112 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /* Constants to define data to program a command */
bogdanm 0:9b334a45a8ff 115 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
bogdanm 0:9b334a45a8ff 116 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
bogdanm 0:9b334a45a8ff 117 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 118 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
bogdanm 0:9b334a45a8ff 119 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
bogdanm 0:9b334a45a8ff 120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
bogdanm 0:9b334a45a8ff 121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
bogdanm 0:9b334a45a8ff 122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 123 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
bogdanm 0:9b334a45a8ff 124 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
bogdanm 0:9b334a45a8ff 127 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
bogdanm 0:9b334a45a8ff 128 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /* Mask on NOR STATUS REGISTER */
bogdanm 0:9b334a45a8ff 131 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
bogdanm 0:9b334a45a8ff 132 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /**
bogdanm 0:9b334a45a8ff 135 * @}
bogdanm 0:9b334a45a8ff 136 */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 139 /** @defgroup NOR_Private_Macros NOR Private Macros
bogdanm 0:9b334a45a8ff 140 * @{
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /**
bogdanm 0:9b334a45a8ff 144 * @}
bogdanm 0:9b334a45a8ff 145 */
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 /** @defgroup NOR_Private_Variables NOR Private Variables
bogdanm 0:9b334a45a8ff 150 * @{
bogdanm 0:9b334a45a8ff 151 */
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 /**
bogdanm 0:9b334a45a8ff 156 * @}
bogdanm 0:9b334a45a8ff 157 */
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 160 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /** @defgroup NOR_Exported_Functions NOR Exported Functions
bogdanm 0:9b334a45a8ff 163 * @{
bogdanm 0:9b334a45a8ff 164 */
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 167 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 168 *
bogdanm 0:9b334a45a8ff 169 @verbatim
bogdanm 0:9b334a45a8ff 170 ==============================================================================
bogdanm 0:9b334a45a8ff 171 ##### NOR Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 172 ==============================================================================
bogdanm 0:9b334a45a8ff 173 [..]
bogdanm 0:9b334a45a8ff 174 This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 175 the NOR memory
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 @endverbatim
bogdanm 0:9b334a45a8ff 178 * @{
bogdanm 0:9b334a45a8ff 179 */
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 /**
bogdanm 0:9b334a45a8ff 182 * @brief Perform the NOR memory Initialization sequence
bogdanm 0:9b334a45a8ff 183 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 184 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 185 * @param Timing: pointer to NOR control timing structure
bogdanm 0:9b334a45a8ff 186 * @param ExtTiming: pointer to NOR extended mode timing structure
bogdanm 0:9b334a45a8ff 187 * @retval HAL status
bogdanm 0:9b334a45a8ff 188 */
bogdanm 0:9b334a45a8ff 189 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
bogdanm 0:9b334a45a8ff 190 {
bogdanm 0:9b334a45a8ff 191 /* Check the NOR handle parameter */
bogdanm 0:9b334a45a8ff 192 if(hnor == NULL)
bogdanm 0:9b334a45a8ff 193 {
bogdanm 0:9b334a45a8ff 194 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 195 }
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 if(hnor->State == HAL_NOR_STATE_RESET)
bogdanm 0:9b334a45a8ff 198 {
bogdanm 0:9b334a45a8ff 199 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 200 hnor-> Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 203 HAL_NOR_MspInit(hnor);
bogdanm 0:9b334a45a8ff 204 }
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /* Initialize NOR control Interface */
bogdanm 0:9b334a45a8ff 207 FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /* Initialize NOR timing Interface */
bogdanm 0:9b334a45a8ff 210 FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 /* Initialize NOR extended mode timing Interface */
bogdanm 0:9b334a45a8ff 213 FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /* Enable the NORSRAM device */
bogdanm 0:9b334a45a8ff 216 __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /* Initialize NOR Memory Data Width*/
bogdanm 0:9b334a45a8ff 219 if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
bogdanm 0:9b334a45a8ff 220 {
bogdanm 0:9b334a45a8ff 221 uwNORMemoryDataWidth = NOR_MEMORY_8B;
bogdanm 0:9b334a45a8ff 222 }
bogdanm 0:9b334a45a8ff 223 else
bogdanm 0:9b334a45a8ff 224 {
bogdanm 0:9b334a45a8ff 225 uwNORMemoryDataWidth = NOR_MEMORY_16B;
bogdanm 0:9b334a45a8ff 226 }
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 229 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 return HAL_OK;
bogdanm 0:9b334a45a8ff 232 }
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 /**
bogdanm 0:9b334a45a8ff 235 * @brief Perform NOR memory De-Initialization sequence
bogdanm 0:9b334a45a8ff 236 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 237 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 238 * @retval HAL status
bogdanm 0:9b334a45a8ff 239 */
bogdanm 0:9b334a45a8ff 240 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 241 {
bogdanm 0:9b334a45a8ff 242 /* De-Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 243 HAL_NOR_MspDeInit(hnor);
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 /* Configure the NOR registers with their reset values */
bogdanm 0:9b334a45a8ff 246 FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 249 hnor->State = HAL_NOR_STATE_RESET;
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /* Release Lock */
bogdanm 0:9b334a45a8ff 252 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 return HAL_OK;
bogdanm 0:9b334a45a8ff 255 }
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /**
bogdanm 0:9b334a45a8ff 258 * @brief NOR MSP Init
bogdanm 0:9b334a45a8ff 259 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 260 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 261 * @retval None
bogdanm 0:9b334a45a8ff 262 */
bogdanm 0:9b334a45a8ff 263 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 264 {
bogdanm 0:9b334a45a8ff 265 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 266 the HAL_NOR_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 267 */
bogdanm 0:9b334a45a8ff 268 }
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /**
bogdanm 0:9b334a45a8ff 271 * @brief NOR MSP DeInit
bogdanm 0:9b334a45a8ff 272 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 273 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 274 * @retval None
bogdanm 0:9b334a45a8ff 275 */
bogdanm 0:9b334a45a8ff 276 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 277 {
bogdanm 0:9b334a45a8ff 278 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 279 the HAL_NOR_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 280 */
bogdanm 0:9b334a45a8ff 281 }
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /**
bogdanm 0:9b334a45a8ff 284 * @brief NOR MSP Wait fro Ready/Busy signal
bogdanm 0:9b334a45a8ff 285 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 286 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 287 * @param Timeout: Maximum timeout value
bogdanm 0:9b334a45a8ff 288 * @retval None
bogdanm 0:9b334a45a8ff 289 */
bogdanm 0:9b334a45a8ff 290 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 291 {
bogdanm 0:9b334a45a8ff 292 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 293 the HAL_NOR_MspWait could be implemented in the user file
bogdanm 0:9b334a45a8ff 294 */
bogdanm 0:9b334a45a8ff 295 }
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /**
bogdanm 0:9b334a45a8ff 298 * @}
bogdanm 0:9b334a45a8ff 299 */
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
bogdanm 0:9b334a45a8ff 302 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 303 *
bogdanm 0:9b334a45a8ff 304 @verbatim
bogdanm 0:9b334a45a8ff 305 ==============================================================================
bogdanm 0:9b334a45a8ff 306 ##### NOR Input and Output functions #####
bogdanm 0:9b334a45a8ff 307 ==============================================================================
bogdanm 0:9b334a45a8ff 308 [..]
bogdanm 0:9b334a45a8ff 309 This section provides functions allowing to use and control the NOR memory
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 @endverbatim
bogdanm 0:9b334a45a8ff 312 * @{
bogdanm 0:9b334a45a8ff 313 */
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 /**
bogdanm 0:9b334a45a8ff 316 * @brief Read NOR flash IDs
bogdanm 0:9b334a45a8ff 317 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 318 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 319 * @param pNOR_ID : pointer to NOR ID structure
bogdanm 0:9b334a45a8ff 320 * @retval HAL status
bogdanm 0:9b334a45a8ff 321 */
bogdanm 0:9b334a45a8ff 322 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
bogdanm 0:9b334a45a8ff 323 {
bogdanm 0:9b334a45a8ff 324 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /* Process Locked */
bogdanm 0:9b334a45a8ff 327 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 330 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 331 {
bogdanm 0:9b334a45a8ff 332 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 333 }
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 336 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 337 {
bogdanm 0:9b334a45a8ff 338 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 339 }
bogdanm 0:9b334a45a8ff 340 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 341 {
bogdanm 0:9b334a45a8ff 342 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 343 }
bogdanm 0:9b334a45a8ff 344 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 345 {
bogdanm 0:9b334a45a8ff 346 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 347 }
bogdanm 0:9b334a45a8ff 348 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 349 {
bogdanm 0:9b334a45a8ff 350 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 351 }
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 354 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 /* Send read ID command */
bogdanm 0:9b334a45a8ff 357 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 358 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 359 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /* Read the NOR IDs */
bogdanm 0:9b334a45a8ff 362 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
bogdanm 0:9b334a45a8ff 363 pNOR_ID->Device_Code1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
bogdanm 0:9b334a45a8ff 364 pNOR_ID->Device_Code2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
bogdanm 0:9b334a45a8ff 365 pNOR_ID->Device_Code3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 368 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /* Process unlocked */
bogdanm 0:9b334a45a8ff 371 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 return HAL_OK;
bogdanm 0:9b334a45a8ff 374 }
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /**
bogdanm 0:9b334a45a8ff 377 * @brief Returns the NOR memory to Read mode.
bogdanm 0:9b334a45a8ff 378 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 379 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 380 * @retval HAL status
bogdanm 0:9b334a45a8ff 381 */
bogdanm 0:9b334a45a8ff 382 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 383 {
bogdanm 0:9b334a45a8ff 384 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /* Process Locked */
bogdanm 0:9b334a45a8ff 387 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 390 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 391 {
bogdanm 0:9b334a45a8ff 392 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 393 }
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 396 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 397 {
bogdanm 0:9b334a45a8ff 398 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 399 }
bogdanm 0:9b334a45a8ff 400 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 401 {
bogdanm 0:9b334a45a8ff 402 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 403 }
bogdanm 0:9b334a45a8ff 404 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 405 {
bogdanm 0:9b334a45a8ff 406 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 407 }
bogdanm 0:9b334a45a8ff 408 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 409 {
bogdanm 0:9b334a45a8ff 410 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 411 }
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 __NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 414
bogdanm 0:9b334a45a8ff 415 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 416 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 /* Process unlocked */
bogdanm 0:9b334a45a8ff 419 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 return HAL_OK;
bogdanm 0:9b334a45a8ff 422 }
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /**
bogdanm 0:9b334a45a8ff 425 * @brief Read data from NOR memory
bogdanm 0:9b334a45a8ff 426 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 427 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 428 * @param pAddress: pointer to Device address
bogdanm 0:9b334a45a8ff 429 * @param pData : pointer to read data
bogdanm 0:9b334a45a8ff 430 * @retval HAL status
bogdanm 0:9b334a45a8ff 431 */
bogdanm 0:9b334a45a8ff 432 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
bogdanm 0:9b334a45a8ff 433 {
bogdanm 0:9b334a45a8ff 434 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 435
bogdanm 0:9b334a45a8ff 436 /* Process Locked */
bogdanm 0:9b334a45a8ff 437 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 440 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 441 {
bogdanm 0:9b334a45a8ff 442 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 443 }
bogdanm 0:9b334a45a8ff 444
bogdanm 0:9b334a45a8ff 445 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 446 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 447 {
bogdanm 0:9b334a45a8ff 448 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 449 }
bogdanm 0:9b334a45a8ff 450 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 451 {
bogdanm 0:9b334a45a8ff 452 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 453 }
bogdanm 0:9b334a45a8ff 454 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 455 {
bogdanm 0:9b334a45a8ff 456 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 457 }
bogdanm 0:9b334a45a8ff 458 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 459 {
bogdanm 0:9b334a45a8ff 460 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 461 }
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 464 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /* Send read data command */
bogdanm 0:9b334a45a8ff 467 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 468 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 469 __NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 470
bogdanm 0:9b334a45a8ff 471 /* Read the data */
bogdanm 0:9b334a45a8ff 472 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 475 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /* Process unlocked */
bogdanm 0:9b334a45a8ff 478 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 return HAL_OK;
bogdanm 0:9b334a45a8ff 481 }
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /**
bogdanm 0:9b334a45a8ff 484 * @brief Program data to NOR memory
bogdanm 0:9b334a45a8ff 485 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 486 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 487 * @param pAddress: Device address
bogdanm 0:9b334a45a8ff 488 * @param pData : pointer to the data to write
bogdanm 0:9b334a45a8ff 489 * @retval HAL status
bogdanm 0:9b334a45a8ff 490 */
bogdanm 0:9b334a45a8ff 491 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
bogdanm 0:9b334a45a8ff 492 {
bogdanm 0:9b334a45a8ff 493 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 /* Process Locked */
bogdanm 0:9b334a45a8ff 496 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 499 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 500 {
bogdanm 0:9b334a45a8ff 501 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 502 }
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 505 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 506 {
bogdanm 0:9b334a45a8ff 507 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 508 }
bogdanm 0:9b334a45a8ff 509 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 510 {
bogdanm 0:9b334a45a8ff 511 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 512 }
bogdanm 0:9b334a45a8ff 513 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 514 {
bogdanm 0:9b334a45a8ff 515 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 516 }
bogdanm 0:9b334a45a8ff 517 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 518 {
bogdanm 0:9b334a45a8ff 519 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 520 }
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 523 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /* Send program data command */
bogdanm 0:9b334a45a8ff 526 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 527 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 528 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /* Write the data */
bogdanm 0:9b334a45a8ff 531 __NOR_WRITE(pAddress, *pData);
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 534 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 /* Process unlocked */
bogdanm 0:9b334a45a8ff 537 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 return HAL_OK;
bogdanm 0:9b334a45a8ff 540 }
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /**
bogdanm 0:9b334a45a8ff 543 * @brief Reads a block of data from the FSMC NOR memory.
bogdanm 0:9b334a45a8ff 544 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 545 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 546 * @param uwAddress: NOR memory internal address to read from.
bogdanm 0:9b334a45a8ff 547 * @param pData: pointer to the buffer that receives the data read from the
bogdanm 0:9b334a45a8ff 548 * NOR memory.
bogdanm 0:9b334a45a8ff 549 * @param uwBufferSize : number of Half word to read.
bogdanm 0:9b334a45a8ff 550 * @retval HAL status
bogdanm 0:9b334a45a8ff 551 */
bogdanm 0:9b334a45a8ff 552 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
bogdanm 0:9b334a45a8ff 553 {
bogdanm 0:9b334a45a8ff 554 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 /* Process Locked */
bogdanm 0:9b334a45a8ff 557 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 560 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 561 {
bogdanm 0:9b334a45a8ff 562 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 563 }
bogdanm 0:9b334a45a8ff 564
bogdanm 0:9b334a45a8ff 565 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 566 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 567 {
bogdanm 0:9b334a45a8ff 568 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 571 {
bogdanm 0:9b334a45a8ff 572 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 573 }
bogdanm 0:9b334a45a8ff 574 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 575 {
bogdanm 0:9b334a45a8ff 576 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 577 }
bogdanm 0:9b334a45a8ff 578 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 579 {
bogdanm 0:9b334a45a8ff 580 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 581 }
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 584 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 585
bogdanm 0:9b334a45a8ff 586 /* Send read data command */
bogdanm 0:9b334a45a8ff 587 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 588 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 589 __NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /* Read buffer */
bogdanm 0:9b334a45a8ff 592 while( uwBufferSize > 0)
bogdanm 0:9b334a45a8ff 593 {
bogdanm 0:9b334a45a8ff 594 *pData++ = *(__IO uint16_t *)uwAddress;
bogdanm 0:9b334a45a8ff 595 uwAddress += 2;
bogdanm 0:9b334a45a8ff 596 uwBufferSize--;
bogdanm 0:9b334a45a8ff 597 }
bogdanm 0:9b334a45a8ff 598
bogdanm 0:9b334a45a8ff 599 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 600 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 /* Process unlocked */
bogdanm 0:9b334a45a8ff 603 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 604
bogdanm 0:9b334a45a8ff 605 return HAL_OK;
bogdanm 0:9b334a45a8ff 606 }
bogdanm 0:9b334a45a8ff 607
bogdanm 0:9b334a45a8ff 608 /**
bogdanm 0:9b334a45a8ff 609 * @brief Writes a half-word buffer to the FSMC NOR memory. This function
bogdanm 0:9b334a45a8ff 610 * must be used only with S29GL128P NOR memory.
bogdanm 0:9b334a45a8ff 611 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 612 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 613 * @param uwAddress: NOR memory internal address from which the data
bogdanm 0:9b334a45a8ff 614 * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
bogdanm 0:9b334a45a8ff 615 * 64 bytes boundary for example).
bogdanm 0:9b334a45a8ff 616 * @param pData: pointer to source data buffer.
bogdanm 0:9b334a45a8ff 617 * @param uwBufferSize: number of Half words to write.
bogdanm 0:9b334a45a8ff 618 * @note The maximum buffer size allowed is NOR memory dependent
bogdanm 0:9b334a45a8ff 619 * (can be 64 Bytes max for example).
bogdanm 0:9b334a45a8ff 620 * @retval HAL status
bogdanm 0:9b334a45a8ff 621 */
bogdanm 0:9b334a45a8ff 622 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
bogdanm 0:9b334a45a8ff 623 {
bogdanm 0:9b334a45a8ff 624 uint16_t * p_currentaddress = (uint16_t *)NULL;
bogdanm 0:9b334a45a8ff 625 uint16_t * p_endaddress = (uint16_t *)NULL;
bogdanm 0:9b334a45a8ff 626 uint32_t lastloadedaddress = 0, deviceaddress = 0;
bogdanm 0:9b334a45a8ff 627
bogdanm 0:9b334a45a8ff 628 /* Process Locked */
bogdanm 0:9b334a45a8ff 629 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 632 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 633 {
bogdanm 0:9b334a45a8ff 634 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 635 }
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 638 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 639 {
bogdanm 0:9b334a45a8ff 640 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 641 }
bogdanm 0:9b334a45a8ff 642 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 643 {
bogdanm 0:9b334a45a8ff 644 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 645 }
bogdanm 0:9b334a45a8ff 646 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 647 {
bogdanm 0:9b334a45a8ff 648 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 649 }
bogdanm 0:9b334a45a8ff 650 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 651 {
bogdanm 0:9b334a45a8ff 652 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 653 }
bogdanm 0:9b334a45a8ff 654
bogdanm 0:9b334a45a8ff 655 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 656 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 657
bogdanm 0:9b334a45a8ff 658 /* Initialize variables */
bogdanm 0:9b334a45a8ff 659 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
bogdanm 0:9b334a45a8ff 660 p_endaddress = p_currentaddress + (uwBufferSize-1);
bogdanm 0:9b334a45a8ff 661 lastloadedaddress = (uint32_t)(uwAddress);
bogdanm 0:9b334a45a8ff 662
bogdanm 0:9b334a45a8ff 663 /* Issue unlock command sequence */
bogdanm 0:9b334a45a8ff 664 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 665 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 666
bogdanm 0:9b334a45a8ff 667 /* Write Buffer Load Command */
bogdanm 0:9b334a45a8ff 668 __NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
bogdanm 0:9b334a45a8ff 669 __NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 /* Load Data into NOR Buffer */
bogdanm 0:9b334a45a8ff 672 while(p_currentaddress <= p_endaddress)
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 /* Store last loaded address & data value (for polling) */
bogdanm 0:9b334a45a8ff 675 lastloadedaddress = (uint32_t)p_currentaddress;
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 __NOR_WRITE(p_currentaddress, *pData++);
bogdanm 0:9b334a45a8ff 678
bogdanm 0:9b334a45a8ff 679 p_currentaddress++;
bogdanm 0:9b334a45a8ff 680 }
bogdanm 0:9b334a45a8ff 681
bogdanm 0:9b334a45a8ff 682 __NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 685 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 686
bogdanm 0:9b334a45a8ff 687 /* Process unlocked */
bogdanm 0:9b334a45a8ff 688 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 return HAL_OK;
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 }
bogdanm 0:9b334a45a8ff 693
bogdanm 0:9b334a45a8ff 694 /**
bogdanm 0:9b334a45a8ff 695 * @brief Erase the specified block of the NOR memory
bogdanm 0:9b334a45a8ff 696 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 697 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 698 * @param BlockAddress : Block to erase address
bogdanm 0:9b334a45a8ff 699 * @param Address: Device address
bogdanm 0:9b334a45a8ff 700 * @retval HAL status
bogdanm 0:9b334a45a8ff 701 */
bogdanm 0:9b334a45a8ff 702 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
bogdanm 0:9b334a45a8ff 703 {
bogdanm 0:9b334a45a8ff 704 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 /* Process Locked */
bogdanm 0:9b334a45a8ff 707 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 708
bogdanm 0:9b334a45a8ff 709 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 710 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 711 {
bogdanm 0:9b334a45a8ff 712 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 713 }
bogdanm 0:9b334a45a8ff 714
bogdanm 0:9b334a45a8ff 715 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 716 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 717 {
bogdanm 0:9b334a45a8ff 718 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 719 }
bogdanm 0:9b334a45a8ff 720 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 721 {
bogdanm 0:9b334a45a8ff 722 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 723 }
bogdanm 0:9b334a45a8ff 724 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 725 {
bogdanm 0:9b334a45a8ff 726 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 727 }
bogdanm 0:9b334a45a8ff 728 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 729 {
bogdanm 0:9b334a45a8ff 730 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 731 }
bogdanm 0:9b334a45a8ff 732
bogdanm 0:9b334a45a8ff 733 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 734 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 735
bogdanm 0:9b334a45a8ff 736 /* Send block erase command sequence */
bogdanm 0:9b334a45a8ff 737 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 738 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 739 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
bogdanm 0:9b334a45a8ff 740 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
bogdanm 0:9b334a45a8ff 741 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
bogdanm 0:9b334a45a8ff 742 __NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
bogdanm 0:9b334a45a8ff 743
bogdanm 0:9b334a45a8ff 744 /* Check the NOR memory status and update the controller state */
bogdanm 0:9b334a45a8ff 745 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 746
bogdanm 0:9b334a45a8ff 747 /* Process unlocked */
bogdanm 0:9b334a45a8ff 748 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 return HAL_OK;
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 }
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 /**
bogdanm 0:9b334a45a8ff 755 * @brief Erase the entire NOR chip.
bogdanm 0:9b334a45a8ff 756 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 757 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 758 * @param Address : Device address
bogdanm 0:9b334a45a8ff 759 * @retval HAL status
bogdanm 0:9b334a45a8ff 760 */
bogdanm 0:9b334a45a8ff 761 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
bogdanm 0:9b334a45a8ff 762 {
bogdanm 0:9b334a45a8ff 763 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 764
bogdanm 0:9b334a45a8ff 765 /* Process Locked */
bogdanm 0:9b334a45a8ff 766 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 767
bogdanm 0:9b334a45a8ff 768 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 769 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 770 {
bogdanm 0:9b334a45a8ff 771 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 772 }
bogdanm 0:9b334a45a8ff 773
bogdanm 0:9b334a45a8ff 774 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 775 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 776 {
bogdanm 0:9b334a45a8ff 777 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 778 }
bogdanm 0:9b334a45a8ff 779 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 780 {
bogdanm 0:9b334a45a8ff 781 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 782 }
bogdanm 0:9b334a45a8ff 783 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 784 {
bogdanm 0:9b334a45a8ff 785 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 786 }
bogdanm 0:9b334a45a8ff 787 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 788 {
bogdanm 0:9b334a45a8ff 789 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 790 }
bogdanm 0:9b334a45a8ff 791
bogdanm 0:9b334a45a8ff 792 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 793 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 794
bogdanm 0:9b334a45a8ff 795 /* Send NOR chip erase command sequence */
bogdanm 0:9b334a45a8ff 796 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 797 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 798 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
bogdanm 0:9b334a45a8ff 799 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
bogdanm 0:9b334a45a8ff 800 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
bogdanm 0:9b334a45a8ff 801 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
bogdanm 0:9b334a45a8ff 802
bogdanm 0:9b334a45a8ff 803 /* Check the NOR memory status and update the controller state */
bogdanm 0:9b334a45a8ff 804 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 805
bogdanm 0:9b334a45a8ff 806 /* Process unlocked */
bogdanm 0:9b334a45a8ff 807 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 808
bogdanm 0:9b334a45a8ff 809 return HAL_OK;
bogdanm 0:9b334a45a8ff 810 }
bogdanm 0:9b334a45a8ff 811
bogdanm 0:9b334a45a8ff 812 /**
bogdanm 0:9b334a45a8ff 813 * @brief Read NOR flash CFI IDs
bogdanm 0:9b334a45a8ff 814 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 815 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 816 * @param pNOR_CFI : pointer to NOR CFI IDs structure
bogdanm 0:9b334a45a8ff 817 * @retval HAL status
bogdanm 0:9b334a45a8ff 818 */
bogdanm 0:9b334a45a8ff 819 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
bogdanm 0:9b334a45a8ff 820 {
bogdanm 0:9b334a45a8ff 821 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 822
bogdanm 0:9b334a45a8ff 823 /* Process Locked */
bogdanm 0:9b334a45a8ff 824 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 825
bogdanm 0:9b334a45a8ff 826 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 827 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 828 {
bogdanm 0:9b334a45a8ff 829 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 830 }
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 833 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 834 {
bogdanm 0:9b334a45a8ff 835 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 836 }
bogdanm 0:9b334a45a8ff 837 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 838 {
bogdanm 0:9b334a45a8ff 839 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 840 }
bogdanm 0:9b334a45a8ff 841 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 842 {
bogdanm 0:9b334a45a8ff 843 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 844 }
bogdanm 0:9b334a45a8ff 845 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 846 {
bogdanm 0:9b334a45a8ff 847 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 848 }
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 851 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 852
bogdanm 0:9b334a45a8ff 853 /* Send read CFI query command */
bogdanm 0:9b334a45a8ff 854 __NOR_WRITE(__NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
bogdanm 0:9b334a45a8ff 855
bogdanm 0:9b334a45a8ff 856 /* read the NOR CFI information */
bogdanm 0:9b334a45a8ff 857 pNOR_CFI->CFI_1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
bogdanm 0:9b334a45a8ff 858 pNOR_CFI->CFI_2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
bogdanm 0:9b334a45a8ff 859 pNOR_CFI->CFI_3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
bogdanm 0:9b334a45a8ff 860 pNOR_CFI->CFI_4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
bogdanm 0:9b334a45a8ff 861
bogdanm 0:9b334a45a8ff 862 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 863 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 864
bogdanm 0:9b334a45a8ff 865 /* Process unlocked */
bogdanm 0:9b334a45a8ff 866 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 867
bogdanm 0:9b334a45a8ff 868 return HAL_OK;
bogdanm 0:9b334a45a8ff 869 }
bogdanm 0:9b334a45a8ff 870
bogdanm 0:9b334a45a8ff 871 /**
bogdanm 0:9b334a45a8ff 872 * @}
bogdanm 0:9b334a45a8ff 873 */
bogdanm 0:9b334a45a8ff 874
bogdanm 0:9b334a45a8ff 875 /** @defgroup NOR_Exported_Functions_Group3 Control functions
bogdanm 0:9b334a45a8ff 876 * @brief management functions
bogdanm 0:9b334a45a8ff 877 *
bogdanm 0:9b334a45a8ff 878 @verbatim
bogdanm 0:9b334a45a8ff 879 ==============================================================================
bogdanm 0:9b334a45a8ff 880 ##### NOR Control functions #####
bogdanm 0:9b334a45a8ff 881 ==============================================================================
bogdanm 0:9b334a45a8ff 882 [..]
bogdanm 0:9b334a45a8ff 883 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 884 the NOR interface.
bogdanm 0:9b334a45a8ff 885
bogdanm 0:9b334a45a8ff 886 @endverbatim
bogdanm 0:9b334a45a8ff 887 * @{
bogdanm 0:9b334a45a8ff 888 */
bogdanm 0:9b334a45a8ff 889
bogdanm 0:9b334a45a8ff 890 /**
bogdanm 0:9b334a45a8ff 891 * @brief Enables dynamically NOR write operation.
bogdanm 0:9b334a45a8ff 892 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 893 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 894 * @retval HAL status
bogdanm 0:9b334a45a8ff 895 */
bogdanm 0:9b334a45a8ff 896 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 897 {
bogdanm 0:9b334a45a8ff 898 /* Process Locked */
bogdanm 0:9b334a45a8ff 899 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 900
bogdanm 0:9b334a45a8ff 901 /* Enable write operation */
bogdanm 0:9b334a45a8ff 902 FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 903
bogdanm 0:9b334a45a8ff 904 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 905 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 906
bogdanm 0:9b334a45a8ff 907 /* Process unlocked */
bogdanm 0:9b334a45a8ff 908 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 909
bogdanm 0:9b334a45a8ff 910 return HAL_OK;
bogdanm 0:9b334a45a8ff 911 }
bogdanm 0:9b334a45a8ff 912
bogdanm 0:9b334a45a8ff 913 /**
bogdanm 0:9b334a45a8ff 914 * @brief Disables dynamically NOR write operation.
bogdanm 0:9b334a45a8ff 915 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 916 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 917 * @retval HAL status
bogdanm 0:9b334a45a8ff 918 */
bogdanm 0:9b334a45a8ff 919 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 920 {
bogdanm 0:9b334a45a8ff 921 /* Process Locked */
bogdanm 0:9b334a45a8ff 922 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 923
bogdanm 0:9b334a45a8ff 924 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 925 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 926
bogdanm 0:9b334a45a8ff 927 /* Disable write operation */
bogdanm 0:9b334a45a8ff 928 FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 929
bogdanm 0:9b334a45a8ff 930 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 931 hnor->State = HAL_NOR_STATE_PROTECTED;
bogdanm 0:9b334a45a8ff 932
bogdanm 0:9b334a45a8ff 933 /* Process unlocked */
bogdanm 0:9b334a45a8ff 934 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 935
bogdanm 0:9b334a45a8ff 936 return HAL_OK;
bogdanm 0:9b334a45a8ff 937 }
bogdanm 0:9b334a45a8ff 938
bogdanm 0:9b334a45a8ff 939 /**
bogdanm 0:9b334a45a8ff 940 * @}
bogdanm 0:9b334a45a8ff 941 */
bogdanm 0:9b334a45a8ff 942
bogdanm 0:9b334a45a8ff 943 /** @defgroup NOR_Exported_Functions_Group4 State functions
bogdanm 0:9b334a45a8ff 944 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 945 *
bogdanm 0:9b334a45a8ff 946 @verbatim
bogdanm 0:9b334a45a8ff 947 ==============================================================================
bogdanm 0:9b334a45a8ff 948 ##### NOR State functions #####
bogdanm 0:9b334a45a8ff 949 ==============================================================================
bogdanm 0:9b334a45a8ff 950 [..]
bogdanm 0:9b334a45a8ff 951 This subsection permits to get in run-time the status of the NOR controller
bogdanm 0:9b334a45a8ff 952 and the data flow.
bogdanm 0:9b334a45a8ff 953
bogdanm 0:9b334a45a8ff 954 @endverbatim
bogdanm 0:9b334a45a8ff 955 * @{
bogdanm 0:9b334a45a8ff 956 */
bogdanm 0:9b334a45a8ff 957
bogdanm 0:9b334a45a8ff 958 /**
bogdanm 0:9b334a45a8ff 959 * @brief return the NOR controller state
bogdanm 0:9b334a45a8ff 960 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 961 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 962 * @retval NOR controller state
bogdanm 0:9b334a45a8ff 963 */
bogdanm 0:9b334a45a8ff 964 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 965 {
bogdanm 0:9b334a45a8ff 966 return hnor->State;
bogdanm 0:9b334a45a8ff 967 }
bogdanm 0:9b334a45a8ff 968
bogdanm 0:9b334a45a8ff 969 /**
bogdanm 0:9b334a45a8ff 970 * @brief Returns the NOR operation status.
bogdanm 0:9b334a45a8ff 971 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 972 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 973 * @param Address: Device address
bogdanm 0:9b334a45a8ff 974 * @param Timeout: NOR progamming Timeout
bogdanm 0:9b334a45a8ff 975 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
bogdanm 0:9b334a45a8ff 976 * or HAL_NOR_STATUS_TIMEOUT
bogdanm 0:9b334a45a8ff 977 */
bogdanm 0:9b334a45a8ff 978 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 979 {
bogdanm 0:9b334a45a8ff 980 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
bogdanm 0:9b334a45a8ff 981 uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
bogdanm 0:9b334a45a8ff 982 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 983
bogdanm 0:9b334a45a8ff 984 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
bogdanm 0:9b334a45a8ff 985 HAL_NOR_MspWait(hnor, Timeout);
bogdanm 0:9b334a45a8ff 986
bogdanm 0:9b334a45a8ff 987 /* Get tick */
bogdanm 0:9b334a45a8ff 988 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 989 while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
bogdanm 0:9b334a45a8ff 990 {
bogdanm 0:9b334a45a8ff 991 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 992 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 993 {
bogdanm 0:9b334a45a8ff 994 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 995 {
bogdanm 0:9b334a45a8ff 996 status = HAL_NOR_STATUS_TIMEOUT;
bogdanm 0:9b334a45a8ff 997 }
bogdanm 0:9b334a45a8ff 998 }
bogdanm 0:9b334a45a8ff 999
bogdanm 0:9b334a45a8ff 1000 /* Read NOR status register (DQ6 and DQ5) */
bogdanm 0:9b334a45a8ff 1001 tmp_sr1 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1002 tmp_sr2 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1003
bogdanm 0:9b334a45a8ff 1004 /* If DQ6 did not toggle between the two reads then return NOR_Success */
bogdanm 0:9b334a45a8ff 1005 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
bogdanm 0:9b334a45a8ff 1006 {
bogdanm 0:9b334a45a8ff 1007 return HAL_NOR_STATUS_SUCCESS;
bogdanm 0:9b334a45a8ff 1008 }
bogdanm 0:9b334a45a8ff 1009
bogdanm 0:9b334a45a8ff 1010 if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
bogdanm 0:9b334a45a8ff 1011 {
bogdanm 0:9b334a45a8ff 1012 status = HAL_NOR_STATUS_ONGOING;
bogdanm 0:9b334a45a8ff 1013 }
bogdanm 0:9b334a45a8ff 1014
bogdanm 0:9b334a45a8ff 1015 tmp_sr1 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1016 tmp_sr2 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1017
bogdanm 0:9b334a45a8ff 1018 /* If DQ6 did not toggle between the two reads then return NOR_Success */
bogdanm 0:9b334a45a8ff 1019 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
bogdanm 0:9b334a45a8ff 1020 {
bogdanm 0:9b334a45a8ff 1021 return HAL_NOR_STATUS_SUCCESS;
bogdanm 0:9b334a45a8ff 1022 }
bogdanm 0:9b334a45a8ff 1023 else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
bogdanm 0:9b334a45a8ff 1024 {
bogdanm 0:9b334a45a8ff 1025 return HAL_NOR_STATUS_ERROR;
bogdanm 0:9b334a45a8ff 1026 }
bogdanm 0:9b334a45a8ff 1027 }
bogdanm 0:9b334a45a8ff 1028
bogdanm 0:9b334a45a8ff 1029 /* Return the operation status */
bogdanm 0:9b334a45a8ff 1030 return status;
bogdanm 0:9b334a45a8ff 1031 }
bogdanm 0:9b334a45a8ff 1032
bogdanm 0:9b334a45a8ff 1033 /**
bogdanm 0:9b334a45a8ff 1034 * @}
bogdanm 0:9b334a45a8ff 1035 */
bogdanm 0:9b334a45a8ff 1036
bogdanm 0:9b334a45a8ff 1037 /**
bogdanm 0:9b334a45a8ff 1038 * @}
bogdanm 0:9b334a45a8ff 1039 */
bogdanm 0:9b334a45a8ff 1040 /**
bogdanm 0:9b334a45a8ff 1041 * @}
bogdanm 0:9b334a45a8ff 1042 */
bogdanm 0:9b334a45a8ff 1043 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
bogdanm 0:9b334a45a8ff 1044 #endif /* HAL_NOR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1045
bogdanm 0:9b334a45a8ff 1046 /**
bogdanm 0:9b334a45a8ff 1047 * @}
bogdanm 0:9b334a45a8ff 1048 */
bogdanm 0:9b334a45a8ff 1049
bogdanm 0:9b334a45a8ff 1050 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/