en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nor.c@124:6a4a5b7d7324, 2016-05-09 (annotated)

Committer:
mbed_official
Date:
Mon May 09 18:30:12 2016 +0100
Revision:
124:6a4a5b7d7324
Parent:
0:9b334a45a8ff 
Synchronized with git revision ad75bdcde34d7da9d54b7669010c7fb968a99c7c



Full URL: https://github.com/mbedmicro/mbed/commit/ad75bdcde34d7da9d54b7669010c7fb968a99c7c/



[STMF1] Stm32f1_hal_cube update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_nor.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 124:6a4a5b7d7324 5 * @version V1.0.4
mbed_official 124:6a4a5b7d7324 6 * @date 29-April-2016
bogdanm 0:9b334a45a8ff 7 * @brief NOR HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive NOR memories mounted
bogdanm 0:9b334a45a8ff 9 * as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control NOR flash memories. It uses the FSMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with NOR devices. This driver is used as follows:
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
bogdanm 0:9b334a45a8ff 21 with control and timing parameters for both normal and extended mode.
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (+) Read NOR flash memory manufacturer code and device IDs using the function
bogdanm 0:9b334a45a8ff 24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
bogdanm 0:9b334a45a8ff 25 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 (+) Access NOR flash memory by read/write data unit operations using the functions
bogdanm 0:9b334a45a8ff 28 HAL_NOR_Read(), HAL_NOR_Program().
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 (+) Perform NOR flash erase block/chip operations using the functions
bogdanm 0:9b334a45a8ff 31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
bogdanm 0:9b334a45a8ff 34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
bogdanm 0:9b334a45a8ff 35 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
bogdanm 0:9b334a45a8ff 38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (+) You can monitor the NOR device HAL state by calling the function
bogdanm 0:9b334a45a8ff 41 HAL_NOR_GetState()
bogdanm 0:9b334a45a8ff 42 [..]
bogdanm 0:9b334a45a8ff 43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
bogdanm 0:9b334a45a8ff 44 If a NOR flash device contains different operations and/or implementations,
bogdanm 0:9b334a45a8ff 45 it should be implemented separately.
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 *** NOR HAL driver macros list ***
bogdanm 0:9b334a45a8ff 48 =============================================
bogdanm 0:9b334a45a8ff 49 [..]
bogdanm 0:9b334a45a8ff 50 Below the list of most used macros in NOR HAL driver.
bogdanm 0:9b334a45a8ff 51
mbed_official 124:6a4a5b7d7324 52 (+) NOR_WRITE : NOR memory write data to specified address
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 @endverbatim
bogdanm 0:9b334a45a8ff 55 ******************************************************************************
bogdanm 0:9b334a45a8ff 56 * @attention
bogdanm 0:9b334a45a8ff 57 *
mbed_official 124:6a4a5b7d7324 58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 59 *
bogdanm 0:9b334a45a8ff 60 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 61 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 62 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 63 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 65 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 66 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 68 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 69 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 81 *
bogdanm 0:9b334a45a8ff 82 ******************************************************************************
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 86 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 #ifdef HAL_NOR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 93 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 /** @defgroup NOR NOR
bogdanm 0:9b334a45a8ff 96 * @brief NOR driver modules
bogdanm 0:9b334a45a8ff 97 * @{
bogdanm 0:9b334a45a8ff 98 */
bogdanm 0:9b334a45a8ff 99 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 100 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 101 /** @defgroup NOR_Private_Constants NOR Private Constants
bogdanm 0:9b334a45a8ff 102 * @{
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /* Constants to define address to set to write a command */
bogdanm 0:9b334a45a8ff 106 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 107 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 108 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
bogdanm 0:9b334a45a8ff 109 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 110 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 111 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
bogdanm 0:9b334a45a8ff 112 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /* Constants to define data to program a command */
bogdanm 0:9b334a45a8ff 115 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
bogdanm 0:9b334a45a8ff 116 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
bogdanm 0:9b334a45a8ff 117 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 118 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
bogdanm 0:9b334a45a8ff 119 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
bogdanm 0:9b334a45a8ff 120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
bogdanm 0:9b334a45a8ff 121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
bogdanm 0:9b334a45a8ff 122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 123 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
bogdanm 0:9b334a45a8ff 124 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
bogdanm 0:9b334a45a8ff 127 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
bogdanm 0:9b334a45a8ff 128 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /* Mask on NOR STATUS REGISTER */
bogdanm 0:9b334a45a8ff 131 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
bogdanm 0:9b334a45a8ff 132 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /**
bogdanm 0:9b334a45a8ff 135 * @}
bogdanm 0:9b334a45a8ff 136 */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 139 /** @defgroup NOR_Private_Macros NOR Private Macros
bogdanm 0:9b334a45a8ff 140 * @{
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /**
bogdanm 0:9b334a45a8ff 144 * @}
bogdanm 0:9b334a45a8ff 145 */
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 /** @defgroup NOR_Private_Variables NOR Private Variables
bogdanm 0:9b334a45a8ff 150 * @{
bogdanm 0:9b334a45a8ff 151 */
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 /**
bogdanm 0:9b334a45a8ff 156 * @}
bogdanm 0:9b334a45a8ff 157 */
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 160 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /** @defgroup NOR_Exported_Functions NOR Exported Functions
bogdanm 0:9b334a45a8ff 163 * @{
bogdanm 0:9b334a45a8ff 164 */
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 167 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 168 *
bogdanm 0:9b334a45a8ff 169 @verbatim
bogdanm 0:9b334a45a8ff 170 ==============================================================================
bogdanm 0:9b334a45a8ff 171 ##### NOR Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 172 ==============================================================================
bogdanm 0:9b334a45a8ff 173 [..]
bogdanm 0:9b334a45a8ff 174 This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 175 the NOR memory
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 @endverbatim
bogdanm 0:9b334a45a8ff 178 * @{
bogdanm 0:9b334a45a8ff 179 */
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 /**
bogdanm 0:9b334a45a8ff 182 * @brief Perform the NOR memory Initialization sequence
bogdanm 0:9b334a45a8ff 183 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 184 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 185 * @param Timing: pointer to NOR control timing structure
bogdanm 0:9b334a45a8ff 186 * @param ExtTiming: pointer to NOR extended mode timing structure
bogdanm 0:9b334a45a8ff 187 * @retval HAL status
bogdanm 0:9b334a45a8ff 188 */
bogdanm 0:9b334a45a8ff 189 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
bogdanm 0:9b334a45a8ff 190 {
bogdanm 0:9b334a45a8ff 191 /* Check the NOR handle parameter */
bogdanm 0:9b334a45a8ff 192 if(hnor == NULL)
bogdanm 0:9b334a45a8ff 193 {
bogdanm 0:9b334a45a8ff 194 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 195 }
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 if(hnor->State == HAL_NOR_STATE_RESET)
bogdanm 0:9b334a45a8ff 198 {
bogdanm 0:9b334a45a8ff 199 /* Allocate lock resource and initialize it */
mbed_official 124:6a4a5b7d7324 200 hnor->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 203 HAL_NOR_MspInit(hnor);
bogdanm 0:9b334a45a8ff 204 }
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /* Initialize NOR control Interface */
bogdanm 0:9b334a45a8ff 207 FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /* Initialize NOR timing Interface */
bogdanm 0:9b334a45a8ff 210 FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 /* Initialize NOR extended mode timing Interface */
bogdanm 0:9b334a45a8ff 213 FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /* Enable the NORSRAM device */
bogdanm 0:9b334a45a8ff 216 __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /* Initialize NOR Memory Data Width*/
bogdanm 0:9b334a45a8ff 219 if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
bogdanm 0:9b334a45a8ff 220 {
bogdanm 0:9b334a45a8ff 221 uwNORMemoryDataWidth = NOR_MEMORY_8B;
bogdanm 0:9b334a45a8ff 222 }
bogdanm 0:9b334a45a8ff 223 else
bogdanm 0:9b334a45a8ff 224 {
bogdanm 0:9b334a45a8ff 225 uwNORMemoryDataWidth = NOR_MEMORY_16B;
bogdanm 0:9b334a45a8ff 226 }
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 229 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 return HAL_OK;
bogdanm 0:9b334a45a8ff 232 }
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 /**
bogdanm 0:9b334a45a8ff 235 * @brief Perform NOR memory De-Initialization sequence
bogdanm 0:9b334a45a8ff 236 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 237 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 238 * @retval HAL status
bogdanm 0:9b334a45a8ff 239 */
bogdanm 0:9b334a45a8ff 240 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 241 {
bogdanm 0:9b334a45a8ff 242 /* De-Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 243 HAL_NOR_MspDeInit(hnor);
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 /* Configure the NOR registers with their reset values */
bogdanm 0:9b334a45a8ff 246 FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 249 hnor->State = HAL_NOR_STATE_RESET;
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /* Release Lock */
bogdanm 0:9b334a45a8ff 252 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 return HAL_OK;
bogdanm 0:9b334a45a8ff 255 }
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /**
bogdanm 0:9b334a45a8ff 258 * @brief NOR MSP Init
bogdanm 0:9b334a45a8ff 259 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 260 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 261 * @retval None
bogdanm 0:9b334a45a8ff 262 */
bogdanm 0:9b334a45a8ff 263 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 264 {
mbed_official 124:6a4a5b7d7324 265 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 266 UNUSED(hnor);
bogdanm 0:9b334a45a8ff 267 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 268 the HAL_NOR_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 269 */
bogdanm 0:9b334a45a8ff 270 }
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 /**
bogdanm 0:9b334a45a8ff 273 * @brief NOR MSP DeInit
bogdanm 0:9b334a45a8ff 274 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 275 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 276 * @retval None
bogdanm 0:9b334a45a8ff 277 */
bogdanm 0:9b334a45a8ff 278 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 279 {
mbed_official 124:6a4a5b7d7324 280 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 281 UNUSED(hnor);
bogdanm 0:9b334a45a8ff 282 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 283 the HAL_NOR_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 284 */
bogdanm 0:9b334a45a8ff 285 }
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 /**
bogdanm 0:9b334a45a8ff 288 * @brief NOR MSP Wait fro Ready/Busy signal
bogdanm 0:9b334a45a8ff 289 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 290 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 291 * @param Timeout: Maximum timeout value
bogdanm 0:9b334a45a8ff 292 * @retval None
bogdanm 0:9b334a45a8ff 293 */
bogdanm 0:9b334a45a8ff 294 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 295 {
mbed_official 124:6a4a5b7d7324 296 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 297 UNUSED(hnor);
bogdanm 0:9b334a45a8ff 298 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 299 the HAL_NOR_MspWait could be implemented in the user file
bogdanm 0:9b334a45a8ff 300 */
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 /**
bogdanm 0:9b334a45a8ff 304 * @}
bogdanm 0:9b334a45a8ff 305 */
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
bogdanm 0:9b334a45a8ff 308 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 309 *
bogdanm 0:9b334a45a8ff 310 @verbatim
bogdanm 0:9b334a45a8ff 311 ==============================================================================
bogdanm 0:9b334a45a8ff 312 ##### NOR Input and Output functions #####
bogdanm 0:9b334a45a8ff 313 ==============================================================================
bogdanm 0:9b334a45a8ff 314 [..]
bogdanm 0:9b334a45a8ff 315 This section provides functions allowing to use and control the NOR memory
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 @endverbatim
bogdanm 0:9b334a45a8ff 318 * @{
bogdanm 0:9b334a45a8ff 319 */
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 /**
bogdanm 0:9b334a45a8ff 322 * @brief Read NOR flash IDs
bogdanm 0:9b334a45a8ff 323 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 324 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 325 * @param pNOR_ID : pointer to NOR ID structure
bogdanm 0:9b334a45a8ff 326 * @retval HAL status
bogdanm 0:9b334a45a8ff 327 */
bogdanm 0:9b334a45a8ff 328 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
bogdanm 0:9b334a45a8ff 329 {
bogdanm 0:9b334a45a8ff 330 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /* Process Locked */
bogdanm 0:9b334a45a8ff 333 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 336 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 337 {
bogdanm 0:9b334a45a8ff 338 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 339 }
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 342 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 343 {
bogdanm 0:9b334a45a8ff 344 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 345 }
bogdanm 0:9b334a45a8ff 346 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 347 {
bogdanm 0:9b334a45a8ff 348 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 351 {
bogdanm 0:9b334a45a8ff 352 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 353 }
bogdanm 0:9b334a45a8ff 354 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 355 {
bogdanm 0:9b334a45a8ff 356 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 357 }
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 360 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 /* Send read ID command */
mbed_official 124:6a4a5b7d7324 363 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
mbed_official 124:6a4a5b7d7324 364 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
mbed_official 124:6a4a5b7d7324 365 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 /* Read the NOR IDs */
mbed_official 124:6a4a5b7d7324 368 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
mbed_official 124:6a4a5b7d7324 369 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
mbed_official 124:6a4a5b7d7324 370 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
mbed_official 124:6a4a5b7d7324 371 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 374 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Process unlocked */
bogdanm 0:9b334a45a8ff 377 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 return HAL_OK;
bogdanm 0:9b334a45a8ff 380 }
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /**
bogdanm 0:9b334a45a8ff 383 * @brief Returns the NOR memory to Read mode.
bogdanm 0:9b334a45a8ff 384 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 385 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 386 * @retval HAL status
bogdanm 0:9b334a45a8ff 387 */
bogdanm 0:9b334a45a8ff 388 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 389 {
bogdanm 0:9b334a45a8ff 390 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 /* Process Locked */
bogdanm 0:9b334a45a8ff 393 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 396 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 397 {
bogdanm 0:9b334a45a8ff 398 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 399 }
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 402 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 403 {
bogdanm 0:9b334a45a8ff 404 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 405 }
bogdanm 0:9b334a45a8ff 406 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 407 {
bogdanm 0:9b334a45a8ff 408 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 409 }
bogdanm 0:9b334a45a8ff 410 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 411 {
bogdanm 0:9b334a45a8ff 412 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 413 }
bogdanm 0:9b334a45a8ff 414 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 415 {
bogdanm 0:9b334a45a8ff 416 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 417 }
bogdanm 0:9b334a45a8ff 418
mbed_official 124:6a4a5b7d7324 419 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 422 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /* Process unlocked */
bogdanm 0:9b334a45a8ff 425 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 return HAL_OK;
bogdanm 0:9b334a45a8ff 428 }
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /**
bogdanm 0:9b334a45a8ff 431 * @brief Read data from NOR memory
bogdanm 0:9b334a45a8ff 432 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 433 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 434 * @param pAddress: pointer to Device address
bogdanm 0:9b334a45a8ff 435 * @param pData : pointer to read data
bogdanm 0:9b334a45a8ff 436 * @retval HAL status
bogdanm 0:9b334a45a8ff 437 */
bogdanm 0:9b334a45a8ff 438 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
bogdanm 0:9b334a45a8ff 439 {
bogdanm 0:9b334a45a8ff 440 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 /* Process Locked */
bogdanm 0:9b334a45a8ff 443 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 444
bogdanm 0:9b334a45a8ff 445 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 446 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 447 {
bogdanm 0:9b334a45a8ff 448 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 449 }
bogdanm 0:9b334a45a8ff 450
bogdanm 0:9b334a45a8ff 451 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 452 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 453 {
bogdanm 0:9b334a45a8ff 454 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 455 }
bogdanm 0:9b334a45a8ff 456 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 457 {
bogdanm 0:9b334a45a8ff 458 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 459 }
bogdanm 0:9b334a45a8ff 460 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 461 {
bogdanm 0:9b334a45a8ff 462 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 463 }
bogdanm 0:9b334a45a8ff 464 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 465 {
bogdanm 0:9b334a45a8ff 466 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 467 }
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 470 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 /* Send read data command */
mbed_official 124:6a4a5b7d7324 473 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
mbed_official 124:6a4a5b7d7324 474 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
mbed_official 124:6a4a5b7d7324 475 NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /* Read the data */
bogdanm 0:9b334a45a8ff 478 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 481 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /* Process unlocked */
bogdanm 0:9b334a45a8ff 484 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 return HAL_OK;
bogdanm 0:9b334a45a8ff 487 }
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 /**
bogdanm 0:9b334a45a8ff 490 * @brief Program data to NOR memory
bogdanm 0:9b334a45a8ff 491 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 492 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 493 * @param pAddress: Device address
bogdanm 0:9b334a45a8ff 494 * @param pData : pointer to the data to write
bogdanm 0:9b334a45a8ff 495 * @retval HAL status
bogdanm 0:9b334a45a8ff 496 */
bogdanm 0:9b334a45a8ff 497 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
bogdanm 0:9b334a45a8ff 498 {
bogdanm 0:9b334a45a8ff 499 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 500
bogdanm 0:9b334a45a8ff 501 /* Process Locked */
bogdanm 0:9b334a45a8ff 502 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 505 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 506 {
bogdanm 0:9b334a45a8ff 507 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 508 }
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 511 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 512 {
bogdanm 0:9b334a45a8ff 513 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 514 }
bogdanm 0:9b334a45a8ff 515 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 516 {
bogdanm 0:9b334a45a8ff 517 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 518 }
bogdanm 0:9b334a45a8ff 519 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 520 {
bogdanm 0:9b334a45a8ff 521 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 522 }
bogdanm 0:9b334a45a8ff 523 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 524 {
bogdanm 0:9b334a45a8ff 525 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 526 }
bogdanm 0:9b334a45a8ff 527
bogdanm 0:9b334a45a8ff 528 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 529 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 /* Send program data command */
mbed_official 124:6a4a5b7d7324 532 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
mbed_official 124:6a4a5b7d7324 533 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
mbed_official 124:6a4a5b7d7324 534 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 /* Write the data */
mbed_official 124:6a4a5b7d7324 537 NOR_WRITE(pAddress, *pData);
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 540 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /* Process unlocked */
bogdanm 0:9b334a45a8ff 543 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 return HAL_OK;
bogdanm 0:9b334a45a8ff 546 }
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 /**
bogdanm 0:9b334a45a8ff 549 * @brief Reads a block of data from the FSMC NOR memory.
bogdanm 0:9b334a45a8ff 550 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 551 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 552 * @param uwAddress: NOR memory internal address to read from.
bogdanm 0:9b334a45a8ff 553 * @param pData: pointer to the buffer that receives the data read from the
bogdanm 0:9b334a45a8ff 554 * NOR memory.
bogdanm 0:9b334a45a8ff 555 * @param uwBufferSize : number of Half word to read.
bogdanm 0:9b334a45a8ff 556 * @retval HAL status
bogdanm 0:9b334a45a8ff 557 */
bogdanm 0:9b334a45a8ff 558 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
bogdanm 0:9b334a45a8ff 559 {
bogdanm 0:9b334a45a8ff 560 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562 /* Process Locked */
bogdanm 0:9b334a45a8ff 563 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 564
bogdanm 0:9b334a45a8ff 565 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 566 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 567 {
bogdanm 0:9b334a45a8ff 568 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 572 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 573 {
bogdanm 0:9b334a45a8ff 574 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 575 }
bogdanm 0:9b334a45a8ff 576 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 577 {
bogdanm 0:9b334a45a8ff 578 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 579 }
bogdanm 0:9b334a45a8ff 580 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 581 {
bogdanm 0:9b334a45a8ff 582 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 583 }
bogdanm 0:9b334a45a8ff 584 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 585 {
bogdanm 0:9b334a45a8ff 586 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 587 }
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 590 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 /* Send read data command */
mbed_official 124:6a4a5b7d7324 593 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
mbed_official 124:6a4a5b7d7324 594 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
mbed_official 124:6a4a5b7d7324 595 NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 /* Read buffer */
bogdanm 0:9b334a45a8ff 598 while( uwBufferSize > 0)
bogdanm 0:9b334a45a8ff 599 {
bogdanm 0:9b334a45a8ff 600 *pData++ = *(__IO uint16_t *)uwAddress;
bogdanm 0:9b334a45a8ff 601 uwAddress += 2;
bogdanm 0:9b334a45a8ff 602 uwBufferSize--;
bogdanm 0:9b334a45a8ff 603 }
bogdanm 0:9b334a45a8ff 604
bogdanm 0:9b334a45a8ff 605 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 606 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 607
bogdanm 0:9b334a45a8ff 608 /* Process unlocked */
bogdanm 0:9b334a45a8ff 609 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 610
bogdanm 0:9b334a45a8ff 611 return HAL_OK;
bogdanm 0:9b334a45a8ff 612 }
bogdanm 0:9b334a45a8ff 613
bogdanm 0:9b334a45a8ff 614 /**
bogdanm 0:9b334a45a8ff 615 * @brief Writes a half-word buffer to the FSMC NOR memory. This function
bogdanm 0:9b334a45a8ff 616 * must be used only with S29GL128P NOR memory.
bogdanm 0:9b334a45a8ff 617 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 618 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 619 * @param uwAddress: NOR memory internal address from which the data
bogdanm 0:9b334a45a8ff 620 * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
bogdanm 0:9b334a45a8ff 621 * 64 bytes boundary for example).
bogdanm 0:9b334a45a8ff 622 * @param pData: pointer to source data buffer.
bogdanm 0:9b334a45a8ff 623 * @param uwBufferSize: number of Half words to write.
bogdanm 0:9b334a45a8ff 624 * @note The maximum buffer size allowed is NOR memory dependent
bogdanm 0:9b334a45a8ff 625 * (can be 64 Bytes max for example).
bogdanm 0:9b334a45a8ff 626 * @retval HAL status
bogdanm 0:9b334a45a8ff 627 */
bogdanm 0:9b334a45a8ff 628 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
bogdanm 0:9b334a45a8ff 629 {
bogdanm 0:9b334a45a8ff 630 uint16_t * p_currentaddress = (uint16_t *)NULL;
bogdanm 0:9b334a45a8ff 631 uint16_t * p_endaddress = (uint16_t *)NULL;
bogdanm 0:9b334a45a8ff 632 uint32_t lastloadedaddress = 0, deviceaddress = 0;
bogdanm 0:9b334a45a8ff 633
bogdanm 0:9b334a45a8ff 634 /* Process Locked */
bogdanm 0:9b334a45a8ff 635 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 638 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 639 {
bogdanm 0:9b334a45a8ff 640 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 641 }
bogdanm 0:9b334a45a8ff 642
bogdanm 0:9b334a45a8ff 643 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 644 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 645 {
bogdanm 0:9b334a45a8ff 646 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 647 }
bogdanm 0:9b334a45a8ff 648 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 649 {
bogdanm 0:9b334a45a8ff 650 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 651 }
bogdanm 0:9b334a45a8ff 652 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 653 {
bogdanm 0:9b334a45a8ff 654 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 655 }
bogdanm 0:9b334a45a8ff 656 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 657 {
bogdanm 0:9b334a45a8ff 658 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 659 }
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 662 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 /* Initialize variables */
bogdanm 0:9b334a45a8ff 665 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
bogdanm 0:9b334a45a8ff 666 p_endaddress = p_currentaddress + (uwBufferSize-1);
bogdanm 0:9b334a45a8ff 667 lastloadedaddress = (uint32_t)(uwAddress);
bogdanm 0:9b334a45a8ff 668
bogdanm 0:9b334a45a8ff 669 /* Issue unlock command sequence */
mbed_official 124:6a4a5b7d7324 670 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
mbed_official 124:6a4a5b7d7324 671 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 672
bogdanm 0:9b334a45a8ff 673 /* Write Buffer Load Command */
mbed_official 124:6a4a5b7d7324 674 NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
mbed_official 124:6a4a5b7d7324 675 NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 /* Load Data into NOR Buffer */
bogdanm 0:9b334a45a8ff 678 while(p_currentaddress <= p_endaddress)
bogdanm 0:9b334a45a8ff 679 {
bogdanm 0:9b334a45a8ff 680 /* Store last loaded address & data value (for polling) */
bogdanm 0:9b334a45a8ff 681 lastloadedaddress = (uint32_t)p_currentaddress;
bogdanm 0:9b334a45a8ff 682
mbed_official 124:6a4a5b7d7324 683 NOR_WRITE(p_currentaddress, *pData++);
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 p_currentaddress++;
bogdanm 0:9b334a45a8ff 686 }
bogdanm 0:9b334a45a8ff 687
mbed_official 124:6a4a5b7d7324 688 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 691 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 692
bogdanm 0:9b334a45a8ff 693 /* Process unlocked */
bogdanm 0:9b334a45a8ff 694 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 return HAL_OK;
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698 }
bogdanm 0:9b334a45a8ff 699
bogdanm 0:9b334a45a8ff 700 /**
bogdanm 0:9b334a45a8ff 701 * @brief Erase the specified block of the NOR memory
bogdanm 0:9b334a45a8ff 702 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 703 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 704 * @param BlockAddress : Block to erase address
bogdanm 0:9b334a45a8ff 705 * @param Address: Device address
bogdanm 0:9b334a45a8ff 706 * @retval HAL status
bogdanm 0:9b334a45a8ff 707 */
bogdanm 0:9b334a45a8ff 708 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
bogdanm 0:9b334a45a8ff 709 {
bogdanm 0:9b334a45a8ff 710 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 711
bogdanm 0:9b334a45a8ff 712 /* Process Locked */
bogdanm 0:9b334a45a8ff 713 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 714
bogdanm 0:9b334a45a8ff 715 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 716 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 717 {
bogdanm 0:9b334a45a8ff 718 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 719 }
bogdanm 0:9b334a45a8ff 720
bogdanm 0:9b334a45a8ff 721 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 722 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 723 {
bogdanm 0:9b334a45a8ff 724 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 725 }
bogdanm 0:9b334a45a8ff 726 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 727 {
bogdanm 0:9b334a45a8ff 728 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 729 }
bogdanm 0:9b334a45a8ff 730 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 731 {
bogdanm 0:9b334a45a8ff 732 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 733 }
bogdanm 0:9b334a45a8ff 734 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 735 {
bogdanm 0:9b334a45a8ff 736 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 737 }
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 740 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 741
bogdanm 0:9b334a45a8ff 742 /* Send block erase command sequence */
mbed_official 124:6a4a5b7d7324 743 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
mbed_official 124:6a4a5b7d7324 744 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
mbed_official 124:6a4a5b7d7324 745 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
mbed_official 124:6a4a5b7d7324 746 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
mbed_official 124:6a4a5b7d7324 747 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
mbed_official 124:6a4a5b7d7324 748 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 /* Check the NOR memory status and update the controller state */
bogdanm 0:9b334a45a8ff 751 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 752
bogdanm 0:9b334a45a8ff 753 /* Process unlocked */
bogdanm 0:9b334a45a8ff 754 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 755
bogdanm 0:9b334a45a8ff 756 return HAL_OK;
bogdanm 0:9b334a45a8ff 757
bogdanm 0:9b334a45a8ff 758 }
bogdanm 0:9b334a45a8ff 759
bogdanm 0:9b334a45a8ff 760 /**
bogdanm 0:9b334a45a8ff 761 * @brief Erase the entire NOR chip.
bogdanm 0:9b334a45a8ff 762 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 763 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 764 * @param Address : Device address
bogdanm 0:9b334a45a8ff 765 * @retval HAL status
bogdanm 0:9b334a45a8ff 766 */
bogdanm 0:9b334a45a8ff 767 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
bogdanm 0:9b334a45a8ff 768 {
bogdanm 0:9b334a45a8ff 769 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 /* Process Locked */
bogdanm 0:9b334a45a8ff 772 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 773
bogdanm 0:9b334a45a8ff 774 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 775 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 776 {
bogdanm 0:9b334a45a8ff 777 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 778 }
bogdanm 0:9b334a45a8ff 779
bogdanm 0:9b334a45a8ff 780 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 781 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 782 {
bogdanm 0:9b334a45a8ff 783 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 784 }
bogdanm 0:9b334a45a8ff 785 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 786 {
bogdanm 0:9b334a45a8ff 787 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 788 }
bogdanm 0:9b334a45a8ff 789 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 790 {
bogdanm 0:9b334a45a8ff 791 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 792 }
bogdanm 0:9b334a45a8ff 793 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 794 {
bogdanm 0:9b334a45a8ff 795 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 796 }
bogdanm 0:9b334a45a8ff 797
bogdanm 0:9b334a45a8ff 798 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 799 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 800
bogdanm 0:9b334a45a8ff 801 /* Send NOR chip erase command sequence */
mbed_official 124:6a4a5b7d7324 802 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
mbed_official 124:6a4a5b7d7324 803 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
mbed_official 124:6a4a5b7d7324 804 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
mbed_official 124:6a4a5b7d7324 805 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
mbed_official 124:6a4a5b7d7324 806 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
mbed_official 124:6a4a5b7d7324 807 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
bogdanm 0:9b334a45a8ff 808
bogdanm 0:9b334a45a8ff 809 /* Check the NOR memory status and update the controller state */
bogdanm 0:9b334a45a8ff 810 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 811
bogdanm 0:9b334a45a8ff 812 /* Process unlocked */
bogdanm 0:9b334a45a8ff 813 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 814
bogdanm 0:9b334a45a8ff 815 return HAL_OK;
bogdanm 0:9b334a45a8ff 816 }
bogdanm 0:9b334a45a8ff 817
bogdanm 0:9b334a45a8ff 818 /**
bogdanm 0:9b334a45a8ff 819 * @brief Read NOR flash CFI IDs
bogdanm 0:9b334a45a8ff 820 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 821 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 822 * @param pNOR_CFI : pointer to NOR CFI IDs structure
bogdanm 0:9b334a45a8ff 823 * @retval HAL status
bogdanm 0:9b334a45a8ff 824 */
bogdanm 0:9b334a45a8ff 825 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
bogdanm 0:9b334a45a8ff 826 {
bogdanm 0:9b334a45a8ff 827 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 828
bogdanm 0:9b334a45a8ff 829 /* Process Locked */
bogdanm 0:9b334a45a8ff 830 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 833 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 834 {
bogdanm 0:9b334a45a8ff 835 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 836 }
bogdanm 0:9b334a45a8ff 837
bogdanm 0:9b334a45a8ff 838 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 839 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 840 {
bogdanm 0:9b334a45a8ff 841 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 842 }
bogdanm 0:9b334a45a8ff 843 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 844 {
bogdanm 0:9b334a45a8ff 845 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 846 }
bogdanm 0:9b334a45a8ff 847 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 848 {
bogdanm 0:9b334a45a8ff 849 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 850 }
bogdanm 0:9b334a45a8ff 851 else /* FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 852 {
bogdanm 0:9b334a45a8ff 853 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 854 }
bogdanm 0:9b334a45a8ff 855
bogdanm 0:9b334a45a8ff 856 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 857 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 858
bogdanm 0:9b334a45a8ff 859 /* Send read CFI query command */
mbed_official 124:6a4a5b7d7324 860 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
bogdanm 0:9b334a45a8ff 861
bogdanm 0:9b334a45a8ff 862 /* read the NOR CFI information */
mbed_official 124:6a4a5b7d7324 863 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
mbed_official 124:6a4a5b7d7324 864 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
mbed_official 124:6a4a5b7d7324 865 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
mbed_official 124:6a4a5b7d7324 866 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
bogdanm 0:9b334a45a8ff 867
bogdanm 0:9b334a45a8ff 868 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 869 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 870
bogdanm 0:9b334a45a8ff 871 /* Process unlocked */
bogdanm 0:9b334a45a8ff 872 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 873
bogdanm 0:9b334a45a8ff 874 return HAL_OK;
bogdanm 0:9b334a45a8ff 875 }
bogdanm 0:9b334a45a8ff 876
bogdanm 0:9b334a45a8ff 877 /**
bogdanm 0:9b334a45a8ff 878 * @}
bogdanm 0:9b334a45a8ff 879 */
bogdanm 0:9b334a45a8ff 880
bogdanm 0:9b334a45a8ff 881 /** @defgroup NOR_Exported_Functions_Group3 Control functions
bogdanm 0:9b334a45a8ff 882 * @brief management functions
bogdanm 0:9b334a45a8ff 883 *
bogdanm 0:9b334a45a8ff 884 @verbatim
bogdanm 0:9b334a45a8ff 885 ==============================================================================
bogdanm 0:9b334a45a8ff 886 ##### NOR Control functions #####
bogdanm 0:9b334a45a8ff 887 ==============================================================================
bogdanm 0:9b334a45a8ff 888 [..]
bogdanm 0:9b334a45a8ff 889 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 890 the NOR interface.
bogdanm 0:9b334a45a8ff 891
bogdanm 0:9b334a45a8ff 892 @endverbatim
bogdanm 0:9b334a45a8ff 893 * @{
bogdanm 0:9b334a45a8ff 894 */
bogdanm 0:9b334a45a8ff 895
bogdanm 0:9b334a45a8ff 896 /**
bogdanm 0:9b334a45a8ff 897 * @brief Enables dynamically NOR write operation.
bogdanm 0:9b334a45a8ff 898 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 899 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 900 * @retval HAL status
bogdanm 0:9b334a45a8ff 901 */
bogdanm 0:9b334a45a8ff 902 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 903 {
bogdanm 0:9b334a45a8ff 904 /* Process Locked */
bogdanm 0:9b334a45a8ff 905 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 906
bogdanm 0:9b334a45a8ff 907 /* Enable write operation */
bogdanm 0:9b334a45a8ff 908 FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 909
bogdanm 0:9b334a45a8ff 910 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 911 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 912
bogdanm 0:9b334a45a8ff 913 /* Process unlocked */
bogdanm 0:9b334a45a8ff 914 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 915
bogdanm 0:9b334a45a8ff 916 return HAL_OK;
bogdanm 0:9b334a45a8ff 917 }
bogdanm 0:9b334a45a8ff 918
bogdanm 0:9b334a45a8ff 919 /**
bogdanm 0:9b334a45a8ff 920 * @brief Disables dynamically NOR write operation.
bogdanm 0:9b334a45a8ff 921 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 922 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 923 * @retval HAL status
bogdanm 0:9b334a45a8ff 924 */
bogdanm 0:9b334a45a8ff 925 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 926 {
bogdanm 0:9b334a45a8ff 927 /* Process Locked */
bogdanm 0:9b334a45a8ff 928 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 929
bogdanm 0:9b334a45a8ff 930 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 931 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 932
bogdanm 0:9b334a45a8ff 933 /* Disable write operation */
bogdanm 0:9b334a45a8ff 934 FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 935
bogdanm 0:9b334a45a8ff 936 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 937 hnor->State = HAL_NOR_STATE_PROTECTED;
bogdanm 0:9b334a45a8ff 938
bogdanm 0:9b334a45a8ff 939 /* Process unlocked */
bogdanm 0:9b334a45a8ff 940 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 941
bogdanm 0:9b334a45a8ff 942 return HAL_OK;
bogdanm 0:9b334a45a8ff 943 }
bogdanm 0:9b334a45a8ff 944
bogdanm 0:9b334a45a8ff 945 /**
bogdanm 0:9b334a45a8ff 946 * @}
bogdanm 0:9b334a45a8ff 947 */
bogdanm 0:9b334a45a8ff 948
bogdanm 0:9b334a45a8ff 949 /** @defgroup NOR_Exported_Functions_Group4 State functions
bogdanm 0:9b334a45a8ff 950 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 951 *
bogdanm 0:9b334a45a8ff 952 @verbatim
bogdanm 0:9b334a45a8ff 953 ==============================================================================
bogdanm 0:9b334a45a8ff 954 ##### NOR State functions #####
bogdanm 0:9b334a45a8ff 955 ==============================================================================
bogdanm 0:9b334a45a8ff 956 [..]
bogdanm 0:9b334a45a8ff 957 This subsection permits to get in run-time the status of the NOR controller
bogdanm 0:9b334a45a8ff 958 and the data flow.
bogdanm 0:9b334a45a8ff 959
bogdanm 0:9b334a45a8ff 960 @endverbatim
bogdanm 0:9b334a45a8ff 961 * @{
bogdanm 0:9b334a45a8ff 962 */
bogdanm 0:9b334a45a8ff 963
bogdanm 0:9b334a45a8ff 964 /**
bogdanm 0:9b334a45a8ff 965 * @brief return the NOR controller state
bogdanm 0:9b334a45a8ff 966 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 967 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 968 * @retval NOR controller state
bogdanm 0:9b334a45a8ff 969 */
bogdanm 0:9b334a45a8ff 970 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 971 {
bogdanm 0:9b334a45a8ff 972 return hnor->State;
bogdanm 0:9b334a45a8ff 973 }
bogdanm 0:9b334a45a8ff 974
bogdanm 0:9b334a45a8ff 975 /**
bogdanm 0:9b334a45a8ff 976 * @brief Returns the NOR operation status.
bogdanm 0:9b334a45a8ff 977 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 978 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 979 * @param Address: Device address
bogdanm 0:9b334a45a8ff 980 * @param Timeout: NOR progamming Timeout
bogdanm 0:9b334a45a8ff 981 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
bogdanm 0:9b334a45a8ff 982 * or HAL_NOR_STATUS_TIMEOUT
bogdanm 0:9b334a45a8ff 983 */
bogdanm 0:9b334a45a8ff 984 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 985 {
bogdanm 0:9b334a45a8ff 986 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
bogdanm 0:9b334a45a8ff 987 uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
bogdanm 0:9b334a45a8ff 988 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 989
bogdanm 0:9b334a45a8ff 990 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
bogdanm 0:9b334a45a8ff 991 HAL_NOR_MspWait(hnor, Timeout);
bogdanm 0:9b334a45a8ff 992
bogdanm 0:9b334a45a8ff 993 /* Get tick */
bogdanm 0:9b334a45a8ff 994 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 995 while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
bogdanm 0:9b334a45a8ff 996 {
bogdanm 0:9b334a45a8ff 997 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 998 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 999 {
bogdanm 0:9b334a45a8ff 1000 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 1001 {
bogdanm 0:9b334a45a8ff 1002 status = HAL_NOR_STATUS_TIMEOUT;
bogdanm 0:9b334a45a8ff 1003 }
bogdanm 0:9b334a45a8ff 1004 }
bogdanm 0:9b334a45a8ff 1005
bogdanm 0:9b334a45a8ff 1006 /* Read NOR status register (DQ6 and DQ5) */
bogdanm 0:9b334a45a8ff 1007 tmp_sr1 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1008 tmp_sr2 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1009
bogdanm 0:9b334a45a8ff 1010 /* If DQ6 did not toggle between the two reads then return NOR_Success */
bogdanm 0:9b334a45a8ff 1011 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
bogdanm 0:9b334a45a8ff 1012 {
bogdanm 0:9b334a45a8ff 1013 return HAL_NOR_STATUS_SUCCESS;
bogdanm 0:9b334a45a8ff 1014 }
bogdanm 0:9b334a45a8ff 1015
bogdanm 0:9b334a45a8ff 1016 if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
bogdanm 0:9b334a45a8ff 1017 {
bogdanm 0:9b334a45a8ff 1018 status = HAL_NOR_STATUS_ONGOING;
bogdanm 0:9b334a45a8ff 1019 }
bogdanm 0:9b334a45a8ff 1020
bogdanm 0:9b334a45a8ff 1021 tmp_sr1 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1022 tmp_sr2 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 1023
bogdanm 0:9b334a45a8ff 1024 /* If DQ6 did not toggle between the two reads then return NOR_Success */
bogdanm 0:9b334a45a8ff 1025 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
bogdanm 0:9b334a45a8ff 1026 {
bogdanm 0:9b334a45a8ff 1027 return HAL_NOR_STATUS_SUCCESS;
bogdanm 0:9b334a45a8ff 1028 }
bogdanm 0:9b334a45a8ff 1029 else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
bogdanm 0:9b334a45a8ff 1030 {
bogdanm 0:9b334a45a8ff 1031 return HAL_NOR_STATUS_ERROR;
bogdanm 0:9b334a45a8ff 1032 }
bogdanm 0:9b334a45a8ff 1033 }
bogdanm 0:9b334a45a8ff 1034
bogdanm 0:9b334a45a8ff 1035 /* Return the operation status */
bogdanm 0:9b334a45a8ff 1036 return status;
bogdanm 0:9b334a45a8ff 1037 }
bogdanm 0:9b334a45a8ff 1038
bogdanm 0:9b334a45a8ff 1039 /**
bogdanm 0:9b334a45a8ff 1040 * @}
bogdanm 0:9b334a45a8ff 1041 */
bogdanm 0:9b334a45a8ff 1042
bogdanm 0:9b334a45a8ff 1043 /**
bogdanm 0:9b334a45a8ff 1044 * @}
bogdanm 0:9b334a45a8ff 1045 */
bogdanm 0:9b334a45a8ff 1046 /**
bogdanm 0:9b334a45a8ff 1047 * @}
bogdanm 0:9b334a45a8ff 1048 */
bogdanm 0:9b334a45a8ff 1049 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
bogdanm 0:9b334a45a8ff 1050 #endif /* HAL_NOR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1051
bogdanm 0:9b334a45a8ff 1052 /**
bogdanm 0:9b334a45a8ff 1053 * @}
bogdanm 0:9b334a45a8ff 1054 */
bogdanm 0:9b334a45a8ff 1055
bogdanm 0:9b334a45a8ff 1056 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/