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fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc_ex.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
124:6a4a5b7d7324
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_adc_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 15-December-2014
bogdanm 0:9b334a45a8ff 7 * @brief This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 8 * functionalities of the Analog to Digital Convertor (ADC)
bogdanm 0:9b334a45a8ff 9 * peripheral:
bogdanm 0:9b334a45a8ff 10 * + Operation functions
bogdanm 0:9b334a45a8ff 11 * ++ Start, stop, get result of conversions of injected
bogdanm 0:9b334a45a8ff 12 * group, using 2 possible modes: polling, interruption.
bogdanm 0:9b334a45a8ff 13 * ++ Multimode feature (available on devices with 2 ADCs or more)
bogdanm 0:9b334a45a8ff 14 * ++ Calibration (ADC automatic self-calibration)
bogdanm 0:9b334a45a8ff 15 * + Control functions
bogdanm 0:9b334a45a8ff 16 * ++ Channels configuration on injected group
bogdanm 0:9b334a45a8ff 17 * Other functions (generic functions) are available in file
bogdanm 0:9b334a45a8ff 18 * "stm32f1xx_hal_adc.c".
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 @verbatim
bogdanm 0:9b334a45a8ff 21 [..]
bogdanm 0:9b334a45a8ff 22 (@) Sections "ADC peripheral features" and "How to use this driver" are
bogdanm 0:9b334a45a8ff 23 available in file of generic functions "stm32f1xx_hal_adc.c".
bogdanm 0:9b334a45a8ff 24 [..]
bogdanm 0:9b334a45a8ff 25 @endverbatim
bogdanm 0:9b334a45a8ff 26 ******************************************************************************
bogdanm 0:9b334a45a8ff 27 * @attention
bogdanm 0:9b334a45a8ff 28 *
bogdanm 0:9b334a45a8ff 29 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 32 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 33 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 34 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 35 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 36 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 37 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 38 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 39 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 40 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 41 *
bogdanm 0:9b334a45a8ff 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 45 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 46 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 48 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 49 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 51 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 52 *
bogdanm 0:9b334a45a8ff 53 ******************************************************************************
bogdanm 0:9b334a45a8ff 54 */
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 57 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 60 * @{
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /** @defgroup ADCEx ADCEx
bogdanm 0:9b334a45a8ff 64 * @brief ADC Extension HAL module driver
bogdanm 0:9b334a45a8ff 65 * @{
bogdanm 0:9b334a45a8ff 66 */
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 #ifdef HAL_ADC_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 71 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 72 /** @defgroup ADCEx_Private_Constants ADCEx Private Constants
bogdanm 0:9b334a45a8ff 73 * @{
bogdanm 0:9b334a45a8ff 74 */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 /* Delay for ADC calibration: */
bogdanm 0:9b334a45a8ff 77 /* Hardware prerequisite before starting a calibration: the ADC must have */
bogdanm 0:9b334a45a8ff 78 /* been in power-on state for at least two ADC clock cycles. */
bogdanm 0:9b334a45a8ff 79 /* Unit: ADC clock cycles */
bogdanm 0:9b334a45a8ff 80 #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ((uint32_t) 2)
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 /* Timeout value for ADC calibration */
bogdanm 0:9b334a45a8ff 83 /* Value defined to be higher than worst cases: low clocks freq, */
bogdanm 0:9b334a45a8ff 84 /* maximum prescaler. */
bogdanm 0:9b334a45a8ff 85 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
bogdanm 0:9b334a45a8ff 86 /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
bogdanm 0:9b334a45a8ff 87 /* Unit: ms */
bogdanm 0:9b334a45a8ff 88 #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /* Delay for temperature sensor stabilization time. */
bogdanm 0:9b334a45a8ff 91 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
bogdanm 0:9b334a45a8ff 92 /* Unit: us */
bogdanm 0:9b334a45a8ff 93 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 /**
bogdanm 0:9b334a45a8ff 96 * @}
bogdanm 0:9b334a45a8ff 97 */
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 100 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 101 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 102 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
bogdanm 0:9b334a45a8ff 105 * @{
bogdanm 0:9b334a45a8ff 106 */
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions
bogdanm 0:9b334a45a8ff 109 * @brief Extended Extended Input and Output operation functions
bogdanm 0:9b334a45a8ff 110 *
bogdanm 0:9b334a45a8ff 111 @verbatim
bogdanm 0:9b334a45a8ff 112 ===============================================================================
bogdanm 0:9b334a45a8ff 113 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 114 ===============================================================================
bogdanm 0:9b334a45a8ff 115 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 116 (+) Start conversion of injected group.
bogdanm 0:9b334a45a8ff 117 (+) Stop conversion of injected group.
bogdanm 0:9b334a45a8ff 118 (+) Poll for conversion complete on injected group.
bogdanm 0:9b334a45a8ff 119 (+) Get result of injected channel conversion.
bogdanm 0:9b334a45a8ff 120 (+) Start conversion of injected group and enable interruptions.
bogdanm 0:9b334a45a8ff 121 (+) Stop conversion of injected group and disable interruptions.
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 (+) Start multimode and enable DMA transfer.
bogdanm 0:9b334a45a8ff 124 (+) Stop multimode and disable ADC DMA transfer.
bogdanm 0:9b334a45a8ff 125 (+) Get result of multimode conversion.
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 (+) Perform the ADC self-calibration for single or differential ending.
bogdanm 0:9b334a45a8ff 128 (+) Get calibration factors for single or differential ending.
bogdanm 0:9b334a45a8ff 129 (+) Set calibration factors for single or differential ending.
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 @endverbatim
bogdanm 0:9b334a45a8ff 132 * @{
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /**
bogdanm 0:9b334a45a8ff 136 * @brief Perform an ADC automatic self-calibration
bogdanm 0:9b334a45a8ff 137 * Calibration prerequisite: ADC must be disabled (execute this
bogdanm 0:9b334a45a8ff 138 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
bogdanm 0:9b334a45a8ff 139 * During calibration process, ADC is enabled. ADC is let enabled at
bogdanm 0:9b334a45a8ff 140 * the completion of this function.
bogdanm 0:9b334a45a8ff 141 * @param hadc: ADC handle
bogdanm 0:9b334a45a8ff 142 * @retval HAL status
bogdanm 0:9b334a45a8ff 143 */
bogdanm 0:9b334a45a8ff 144 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
bogdanm 0:9b334a45a8ff 145 {
bogdanm 0:9b334a45a8ff 146 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm 0:9b334a45a8ff 147 uint32_t tickstart;
bogdanm 0:9b334a45a8ff 148 __IO uint32_t wait_loop_index = 0;
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 /* Check the parameters */
bogdanm 0:9b334a45a8ff 151 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 /* Process locked */
bogdanm 0:9b334a45a8ff 154 __HAL_LOCK(hadc);
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /* 1. Calibration prerequisite: */
bogdanm 0:9b334a45a8ff 157 /* - ADC must be disabled for at least two ADC clock cycles in disable */
bogdanm 0:9b334a45a8ff 158 /* mode before ADC enable */
bogdanm 0:9b334a45a8ff 159 /* Stop potential conversion on going, on regular and injected groups */
bogdanm 0:9b334a45a8ff 160 /* Disable ADC peripheral */
bogdanm 0:9b334a45a8ff 161 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 /* Check if ADC is effectively disabled */
bogdanm 0:9b334a45a8ff 164 if (tmp_hal_status != HAL_ERROR)
bogdanm 0:9b334a45a8ff 165 {
bogdanm 0:9b334a45a8ff 166 /* Hardware prerequisite: delay before starting the calibration. */
bogdanm 0:9b334a45a8ff 167 /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */
bogdanm 0:9b334a45a8ff 168 /* - Wait for the expected ADC clock cycles delay */
bogdanm 0:9b334a45a8ff 169 wait_loop_index = ((SystemCoreClock
bogdanm 0:9b334a45a8ff 170 / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
bogdanm 0:9b334a45a8ff 171 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES );
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 while(wait_loop_index != 0)
bogdanm 0:9b334a45a8ff 174 {
bogdanm 0:9b334a45a8ff 175 wait_loop_index--;
bogdanm 0:9b334a45a8ff 176 }
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178 /* 2. Enable the ADC peripheral */
bogdanm 0:9b334a45a8ff 179 ADC_Enable(hadc);
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 /* 3. Resets ADC calibration registers */
bogdanm 0:9b334a45a8ff 183 SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 /* Wait for calibration reset completion */
bogdanm 0:9b334a45a8ff 188 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
bogdanm 0:9b334a45a8ff 189 {
bogdanm 0:9b334a45a8ff 190 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
bogdanm 0:9b334a45a8ff 191 {
bogdanm 0:9b334a45a8ff 192 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 193 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 /* Process unlocked */
bogdanm 0:9b334a45a8ff 196 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 199 }
bogdanm 0:9b334a45a8ff 200 }
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 /* 4. Start ADC calibration */
bogdanm 0:9b334a45a8ff 204 SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 /* Wait for calibration completion */
bogdanm 0:9b334a45a8ff 209 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
bogdanm 0:9b334a45a8ff 210 {
bogdanm 0:9b334a45a8ff 211 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
bogdanm 0:9b334a45a8ff 212 {
bogdanm 0:9b334a45a8ff 213 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 214 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /* Process unlocked */
bogdanm 0:9b334a45a8ff 217 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 220 }
bogdanm 0:9b334a45a8ff 221 }
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 }
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 /* Process unlocked */
bogdanm 0:9b334a45a8ff 226 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /* Return function status */
bogdanm 0:9b334a45a8ff 229 return tmp_hal_status;
bogdanm 0:9b334a45a8ff 230 }
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /**
bogdanm 0:9b334a45a8ff 233 * @brief Enables ADC, starts conversion of injected group.
bogdanm 0:9b334a45a8ff 234 * Interruptions enabled in this function: None.
bogdanm 0:9b334a45a8ff 235 * @param hadc: ADC handle
bogdanm 0:9b334a45a8ff 236 * @retval HAL status
bogdanm 0:9b334a45a8ff 237 */
bogdanm 0:9b334a45a8ff 238 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
bogdanm 0:9b334a45a8ff 239 {
bogdanm 0:9b334a45a8ff 240 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 /* Check the parameters */
bogdanm 0:9b334a45a8ff 243 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 /* Process locked */
bogdanm 0:9b334a45a8ff 246 __HAL_LOCK(hadc);
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /* Enable the ADC peripheral */
bogdanm 0:9b334a45a8ff 249 tmp_hal_status = ADC_Enable(hadc);
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /* Start conversion if ADC is effectively enabled */
bogdanm 0:9b334a45a8ff 252 if (tmp_hal_status != HAL_ERROR)
bogdanm 0:9b334a45a8ff 253 {
bogdanm 0:9b334a45a8ff 254 /* Check if a regular conversion is ongoing */
bogdanm 0:9b334a45a8ff 255 if(hadc->State == HAL_ADC_STATE_BUSY_REG)
bogdanm 0:9b334a45a8ff 256 {
bogdanm 0:9b334a45a8ff 257 /* Change ADC state */
bogdanm 0:9b334a45a8ff 258 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
bogdanm 0:9b334a45a8ff 259 }
bogdanm 0:9b334a45a8ff 260 else
bogdanm 0:9b334a45a8ff 261 {
bogdanm 0:9b334a45a8ff 262 /* Change ADC state */
bogdanm 0:9b334a45a8ff 263 hadc->State = HAL_ADC_STATE_BUSY_INJ;
bogdanm 0:9b334a45a8ff 264 }
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /* Process unlocked */
bogdanm 0:9b334a45a8ff 267 /* Unlock before starting ADC conversions: in case of potential */
bogdanm 0:9b334a45a8ff 268 /* interruption, to let the process to ADC IRQ Handler. */
bogdanm 0:9b334a45a8ff 269 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /* Set ADC error code to none */
bogdanm 0:9b334a45a8ff 272 ADC_CLEAR_ERRORCODE(hadc);
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /* Clear injected group conversion flag */
bogdanm 0:9b334a45a8ff 275 /* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm 0:9b334a45a8ff 276 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /* Enable conversion of injected group. */
bogdanm 0:9b334a45a8ff 279 /* If software start has been selected, conversion starts immediately. */
bogdanm 0:9b334a45a8ff 280 /* If external trigger has been selected, conversion will start at next */
bogdanm 0:9b334a45a8ff 281 /* trigger event. */
bogdanm 0:9b334a45a8ff 282 /* If automatic injected conversion is enabled, conversion will start */
bogdanm 0:9b334a45a8ff 283 /* after next regular group conversion. */
bogdanm 0:9b334a45a8ff 284 /* Case of multimode enabled (for devices with several ADCs): if ADC is */
bogdanm 0:9b334a45a8ff 285 /* slave, ADC is enabled only (conversion is not started). If ADC is */
bogdanm 0:9b334a45a8ff 286 /* master, ADC is enabled and conversion is started. */
bogdanm 0:9b334a45a8ff 287 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
bogdanm 0:9b334a45a8ff 288 {
bogdanm 0:9b334a45a8ff 289 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
bogdanm 0:9b334a45a8ff 290 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
bogdanm 0:9b334a45a8ff 291 {
bogdanm 0:9b334a45a8ff 292 /* Start ADC conversion on injected group with SW start */
bogdanm 0:9b334a45a8ff 293 SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
bogdanm 0:9b334a45a8ff 294 }
bogdanm 0:9b334a45a8ff 295 else
bogdanm 0:9b334a45a8ff 296 {
bogdanm 0:9b334a45a8ff 297 /* Start ADC conversion on injected group with external trigger */
bogdanm 0:9b334a45a8ff 298 SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
bogdanm 0:9b334a45a8ff 299 }
bogdanm 0:9b334a45a8ff 300 }
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302 else
bogdanm 0:9b334a45a8ff 303 {
bogdanm 0:9b334a45a8ff 304 /* Process unlocked */
bogdanm 0:9b334a45a8ff 305 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /* Return function status */
bogdanm 0:9b334a45a8ff 309 return tmp_hal_status;
bogdanm 0:9b334a45a8ff 310 }
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 /**
bogdanm 0:9b334a45a8ff 313 * @brief Stop conversion of injected channels. Disable ADC peripheral if
bogdanm 0:9b334a45a8ff 314 * no regular conversion is on going.
bogdanm 0:9b334a45a8ff 315 * @note If ADC must be disabled and if conversion is on going on
bogdanm 0:9b334a45a8ff 316 * regular group, function HAL_ADC_Stop must be used to stop both
bogdanm 0:9b334a45a8ff 317 * injected and regular groups, and disable the ADC.
bogdanm 0:9b334a45a8ff 318 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
bogdanm 0:9b334a45a8ff 319 * @param hadc: ADC handle
bogdanm 0:9b334a45a8ff 320 * @retval None
bogdanm 0:9b334a45a8ff 321 */
bogdanm 0:9b334a45a8ff 322 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
bogdanm 0:9b334a45a8ff 323 {
bogdanm 0:9b334a45a8ff 324 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /* Check the parameters */
bogdanm 0:9b334a45a8ff 327 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /* Process locked */
bogdanm 0:9b334a45a8ff 330 __HAL_LOCK(hadc);
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /* Stop potential conversion and disable ADC peripheral */
bogdanm 0:9b334a45a8ff 333 /* Conditioned to: */
bogdanm 0:9b334a45a8ff 334 /* - No conversion on the other group (regular group) is intended to */
bogdanm 0:9b334a45a8ff 335 /* continue (injected and regular groups stop conversion and ADC disable */
bogdanm 0:9b334a45a8ff 336 /* are common) */
bogdanm 0:9b334a45a8ff 337 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
bogdanm 0:9b334a45a8ff 338 if((hadc->State != HAL_ADC_STATE_BUSY_REG) &&
bogdanm 0:9b334a45a8ff 339 (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) &&
bogdanm 0:9b334a45a8ff 340 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
bogdanm 0:9b334a45a8ff 341 {
bogdanm 0:9b334a45a8ff 342 /* Stop potential conversion on going, on regular and injected groups */
bogdanm 0:9b334a45a8ff 343 /* Disable ADC peripheral */
bogdanm 0:9b334a45a8ff 344 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 /* Check if ADC is effectively disabled */
bogdanm 0:9b334a45a8ff 347 if (tmp_hal_status != HAL_ERROR)
bogdanm 0:9b334a45a8ff 348 {
bogdanm 0:9b334a45a8ff 349 /* Change ADC state */
bogdanm 0:9b334a45a8ff 350 hadc->State = HAL_ADC_STATE_READY;
bogdanm 0:9b334a45a8ff 351 }
bogdanm 0:9b334a45a8ff 352 }
bogdanm 0:9b334a45a8ff 353 else
bogdanm 0:9b334a45a8ff 354 {
bogdanm 0:9b334a45a8ff 355 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 356 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 tmp_hal_status = HAL_ERROR;
bogdanm 0:9b334a45a8ff 359 }
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /* Process unlocked */
bogdanm 0:9b334a45a8ff 362 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 /* Return function status */
bogdanm 0:9b334a45a8ff 365 return tmp_hal_status;
bogdanm 0:9b334a45a8ff 366 }
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 /**
bogdanm 0:9b334a45a8ff 369 * @brief Wait for injected group conversion to be completed.
bogdanm 0:9b334a45a8ff 370 * @param hadc: ADC handle
bogdanm 0:9b334a45a8ff 371 * @param Timeout: Timeout value in millisecond.
bogdanm 0:9b334a45a8ff 372 * @retval HAL status
bogdanm 0:9b334a45a8ff 373 */
bogdanm 0:9b334a45a8ff 374 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 375 {
bogdanm 0:9b334a45a8ff 376 uint32_t tickstart;
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 /* Variables for polling in case of scan mode enabled and polling for each */
bogdanm 0:9b334a45a8ff 379 /* conversion. */
bogdanm 0:9b334a45a8ff 380 __IO uint32_t Conversion_Timeout_CPU_cycles = 0;
bogdanm 0:9b334a45a8ff 381 uint32_t Conversion_Timeout_CPU_cycles_max = 0;
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 /* Check the parameters */
bogdanm 0:9b334a45a8ff 384 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /* Get timeout */
bogdanm 0:9b334a45a8ff 387 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 /* Polling for end of conversion: differentiation if single/sequence */
bogdanm 0:9b334a45a8ff 390 /* conversion. */
bogdanm 0:9b334a45a8ff 391 /* For injected group, flag JEOC is set only at the end of the sequence, */
bogdanm 0:9b334a45a8ff 392 /* not for each conversion within the sequence. */
bogdanm 0:9b334a45a8ff 393 /* - If single conversion for injected group (scan mode disabled or */
bogdanm 0:9b334a45a8ff 394 /* InjectedNbrOfConversion ==1), flag jEOC is used to determine the */
bogdanm 0:9b334a45a8ff 395 /* conversion completion. */
bogdanm 0:9b334a45a8ff 396 /* - If sequence conversion for injected group (scan mode enabled and */
bogdanm 0:9b334a45a8ff 397 /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
bogdanm 0:9b334a45a8ff 398 /* sequence. */
bogdanm 0:9b334a45a8ff 399 /* To poll for each conversion, the maximum conversion time is computed */
bogdanm 0:9b334a45a8ff 400 /* from ADC conversion time (selected sampling time + conversion time of */
bogdanm 0:9b334a45a8ff 401 /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
bogdanm 0:9b334a45a8ff 402 /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
bogdanm 0:9b334a45a8ff 403 if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
bogdanm 0:9b334a45a8ff 404 {
bogdanm 0:9b334a45a8ff 405 /* Wait until End of Conversion flag is raised */
bogdanm 0:9b334a45a8ff 406 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
bogdanm 0:9b334a45a8ff 407 {
bogdanm 0:9b334a45a8ff 408 /* Check if timeout is disabled (set to infinite wait) */
bogdanm 0:9b334a45a8ff 409 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 410 {
bogdanm 0:9b334a45a8ff 411 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 412 {
bogdanm 0:9b334a45a8ff 413 /* Update ADC state machine to timeout */
bogdanm 0:9b334a45a8ff 414 hadc->State = HAL_ADC_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 /* Process unlocked */
bogdanm 0:9b334a45a8ff 417 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 420 }
bogdanm 0:9b334a45a8ff 421 }
bogdanm 0:9b334a45a8ff 422 }
bogdanm 0:9b334a45a8ff 423 }
bogdanm 0:9b334a45a8ff 424 else
bogdanm 0:9b334a45a8ff 425 {
bogdanm 0:9b334a45a8ff 426 /* Poll with maximum conversion time */
bogdanm 0:9b334a45a8ff 427 /* - Computation of CPU clock cycles corresponding to ADC clock cycles */
bogdanm 0:9b334a45a8ff 428 /* and ADC maximum conversion cycles on all channels. */
bogdanm 0:9b334a45a8ff 429 /* - Wait for the expected ADC clock cycles delay */
bogdanm 0:9b334a45a8ff 430 Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
bogdanm 0:9b334a45a8ff 431 / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
bogdanm 0:9b334a45a8ff 432 * ADC_CONVCYCLES_MAX_RANGE(hadc) );
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
bogdanm 0:9b334a45a8ff 435 {
bogdanm 0:9b334a45a8ff 436 /* Check if timeout is disabled (set to infinite wait) */
bogdanm 0:9b334a45a8ff 437 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 438 {
bogdanm 0:9b334a45a8ff 439 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 440 {
bogdanm 0:9b334a45a8ff 441 /* Update ADC state machine to timeout */
bogdanm 0:9b334a45a8ff 442 hadc->State = HAL_ADC_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 /* Process unlocked */
bogdanm 0:9b334a45a8ff 445 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 448 }
bogdanm 0:9b334a45a8ff 449 }
bogdanm 0:9b334a45a8ff 450 Conversion_Timeout_CPU_cycles ++;
bogdanm 0:9b334a45a8ff 451 }
bogdanm 0:9b334a45a8ff 452 }
bogdanm 0:9b334a45a8ff 453
bogdanm 0:9b334a45a8ff 454 /* Clear injected group conversion flag (and regular conversion flag raised */
bogdanm 0:9b334a45a8ff 455 /* simultaneously) */
bogdanm 0:9b334a45a8ff 456 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 /* Update state machine on conversion status if not in error state */
bogdanm 0:9b334a45a8ff 459 if(hadc->State != HAL_ADC_STATE_ERROR)
bogdanm 0:9b334a45a8ff 460 {
bogdanm 0:9b334a45a8ff 461 /* Update ADC state machine */
bogdanm 0:9b334a45a8ff 462 if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
bogdanm 0:9b334a45a8ff 463 {
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 if(hadc->State == HAL_ADC_STATE_EOC_REG)
bogdanm 0:9b334a45a8ff 466 {
bogdanm 0:9b334a45a8ff 467 /* Change ADC state */
bogdanm 0:9b334a45a8ff 468 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm 0:9b334a45a8ff 469 }
bogdanm 0:9b334a45a8ff 470 else
bogdanm 0:9b334a45a8ff 471 {
bogdanm 0:9b334a45a8ff 472 /* Change ADC state */
bogdanm 0:9b334a45a8ff 473 hadc->State = HAL_ADC_STATE_EOC_INJ;
bogdanm 0:9b334a45a8ff 474 }
bogdanm 0:9b334a45a8ff 475 }
bogdanm 0:9b334a45a8ff 476 }
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 /* Return ADC state */
bogdanm 0:9b334a45a8ff 479 return HAL_OK;
bogdanm 0:9b334a45a8ff 480 }
bogdanm 0:9b334a45a8ff 481
bogdanm 0:9b334a45a8ff 482 /**
bogdanm 0:9b334a45a8ff 483 * @brief Enables ADC, starts conversion of injected group with interruption.
bogdanm 0:9b334a45a8ff 484 * - JEOC (end of conversion of injected group)
bogdanm 0:9b334a45a8ff 485 * Each of these interruptions has its dedicated callback function.
bogdanm 0:9b334a45a8ff 486 * @param hadc: ADC handle
bogdanm 0:9b334a45a8ff 487 * @retval HAL status.
bogdanm 0:9b334a45a8ff 488 */
bogdanm 0:9b334a45a8ff 489 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
bogdanm 0:9b334a45a8ff 490 {
bogdanm 0:9b334a45a8ff 491 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 /* Check the parameters */
bogdanm 0:9b334a45a8ff 494 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 /* Process locked */
bogdanm 0:9b334a45a8ff 497 __HAL_LOCK(hadc);
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499 /* Enable the ADC peripheral */
bogdanm 0:9b334a45a8ff 500 tmp_hal_status = ADC_Enable(hadc);
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /* Start conversion if ADC is effectively enabled */
bogdanm 0:9b334a45a8ff 503 if (tmp_hal_status != HAL_ERROR)
bogdanm 0:9b334a45a8ff 504 {
bogdanm 0:9b334a45a8ff 505 /* Check if a regular conversion is ongoing */
bogdanm 0:9b334a45a8ff 506 if(hadc->State == HAL_ADC_STATE_BUSY_REG)
bogdanm 0:9b334a45a8ff 507 {
bogdanm 0:9b334a45a8ff 508 /* Change ADC state */
bogdanm 0:9b334a45a8ff 509 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
bogdanm 0:9b334a45a8ff 510 }
bogdanm 0:9b334a45a8ff 511 else
bogdanm 0:9b334a45a8ff 512 {
bogdanm 0:9b334a45a8ff 513 /* Change ADC state */
bogdanm 0:9b334a45a8ff 514 hadc->State = HAL_ADC_STATE_BUSY_INJ;
bogdanm 0:9b334a45a8ff 515 }
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /* Process unlocked */
bogdanm 0:9b334a45a8ff 518 /* Unlock before starting ADC conversions: in case of potential */
bogdanm 0:9b334a45a8ff 519 /* interruption, to let the process to ADC IRQ Handler. */
bogdanm 0:9b334a45a8ff 520 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 /* Set ADC error code to none */
bogdanm 0:9b334a45a8ff 523 ADC_CLEAR_ERRORCODE(hadc);
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /* Clear injected group conversion flag */
bogdanm 0:9b334a45a8ff 526 /* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm 0:9b334a45a8ff 527 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
bogdanm 0:9b334a45a8ff 528
bogdanm 0:9b334a45a8ff 529 /* Enable end of conversion interrupt for injected channels */
bogdanm 0:9b334a45a8ff 530 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
bogdanm 0:9b334a45a8ff 531
bogdanm 0:9b334a45a8ff 532 /* Start conversion of injected group if software start has been selected */
bogdanm 0:9b334a45a8ff 533 /* and if automatic injected conversion is disabled. */
bogdanm 0:9b334a45a8ff 534 /* If external trigger has been selected, conversion will start at next */
bogdanm 0:9b334a45a8ff 535 /* trigger event. */
bogdanm 0:9b334a45a8ff 536 /* If automatic injected conversion is enabled, conversion will start */
bogdanm 0:9b334a45a8ff 537 /* after next regular group conversion. */
bogdanm 0:9b334a45a8ff 538 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
bogdanm 0:9b334a45a8ff 539 {
bogdanm 0:9b334a45a8ff 540 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
bogdanm 0:9b334a45a8ff 541 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
bogdanm 0:9b334a45a8ff 542 {
bogdanm 0:9b334a45a8ff 543 /* Start ADC conversion on injected group with SW start */
bogdanm 0:9b334a45a8ff 544 SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
bogdanm 0:9b334a45a8ff 545 }
bogdanm 0:9b334a45a8ff 546 else
bogdanm 0:9b334a45a8ff 547 {
bogdanm 0:9b334a45a8ff 548 /* Start ADC conversion on injected group with external trigger */
bogdanm 0:9b334a45a8ff 549 SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
bogdanm 0:9b334a45a8ff 550 }
bogdanm 0:9b334a45a8ff 551 }
bogdanm 0:9b334a45a8ff 552 }
bogdanm 0:9b334a45a8ff 553 else
bogdanm 0:9b334a45a8ff 554 {
bogdanm 0:9b334a45a8ff 555 /* Process unlocked */
bogdanm 0:9b334a45a8ff 556 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 557 }
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /* Return function status */
bogdanm 0:9b334a45a8ff 560 return tmp_hal_status;
bogdanm 0:9b334a45a8ff 561 }
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 /**
bogdanm 0:9b334a45a8ff 564 * @brief Stop conversion of injected channels, disable interruption of
bogdanm 0:9b334a45a8ff 565 * end-of-conversion. Disable ADC peripheral if no regular conversion
bogdanm 0:9b334a45a8ff 566 * is on going.
bogdanm 0:9b334a45a8ff 567 * @note If ADC must be disabled and if conversion is on going on
bogdanm 0:9b334a45a8ff 568 * regular group, function HAL_ADC_Stop must be used to stop both
bogdanm 0:9b334a45a8ff 569 * injected and regular groups, and disable the ADC.
bogdanm 0:9b334a45a8ff 570 * @param hadc: ADC handle
bogdanm 0:9b334a45a8ff 571 * @retval None
bogdanm 0:9b334a45a8ff 572 */
bogdanm 0:9b334a45a8ff 573 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
bogdanm 0:9b334a45a8ff 574 {
bogdanm 0:9b334a45a8ff 575 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 /* Check the parameters */
bogdanm 0:9b334a45a8ff 578 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 579
bogdanm 0:9b334a45a8ff 580 /* Process locked */
bogdanm 0:9b334a45a8ff 581 __HAL_LOCK(hadc);
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 /* Stop potential conversion and disable ADC peripheral */
bogdanm 0:9b334a45a8ff 584 /* Conditioned to: */
bogdanm 0:9b334a45a8ff 585 /* - No conversion on the other group (regular group) is intended to */
bogdanm 0:9b334a45a8ff 586 /* continue (injected and regular groups stop conversion and ADC disable */
bogdanm 0:9b334a45a8ff 587 /* are common) */
bogdanm 0:9b334a45a8ff 588 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
bogdanm 0:9b334a45a8ff 589 if((hadc->State != HAL_ADC_STATE_BUSY_REG) &&
bogdanm 0:9b334a45a8ff 590 (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) &&
bogdanm 0:9b334a45a8ff 591 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
bogdanm 0:9b334a45a8ff 592 {
bogdanm 0:9b334a45a8ff 593 /* Stop potential conversion on going, on regular and injected groups */
bogdanm 0:9b334a45a8ff 594 /* Disable ADC peripheral */
bogdanm 0:9b334a45a8ff 595 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 /* Check if ADC is effectively disabled */
bogdanm 0:9b334a45a8ff 598 if (tmp_hal_status != HAL_ERROR)
bogdanm 0:9b334a45a8ff 599 {
bogdanm 0:9b334a45a8ff 600 /* Disable ADC end of conversion interrupt for injected channels */
bogdanm 0:9b334a45a8ff 601 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 /* Change ADC state */
bogdanm 0:9b334a45a8ff 604 hadc->State = HAL_ADC_STATE_READY;
bogdanm 0:9b334a45a8ff 605 }
bogdanm 0:9b334a45a8ff 606 }
bogdanm 0:9b334a45a8ff 607 else
bogdanm 0:9b334a45a8ff 608 {
bogdanm 0:9b334a45a8ff 609 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 610 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 611
bogdanm 0:9b334a45a8ff 612 tmp_hal_status = HAL_ERROR;
bogdanm 0:9b334a45a8ff 613 }
bogdanm 0:9b334a45a8ff 614
bogdanm 0:9b334a45a8ff 615 /* Process unlocked */
bogdanm 0:9b334a45a8ff 616 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 617
bogdanm 0:9b334a45a8ff 618 /* Return function status */
bogdanm 0:9b334a45a8ff 619 return tmp_hal_status;
bogdanm 0:9b334a45a8ff 620 }
bogdanm 0:9b334a45a8ff 621
bogdanm 0:9b334a45a8ff 622 #if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
bogdanm 0:9b334a45a8ff 623 /**
bogdanm 0:9b334a45a8ff 624 * @brief Enables ADC, starts conversion of regular group and transfers result
bogdanm 0:9b334a45a8ff 625 * through DMA.
bogdanm 0:9b334a45a8ff 626 * Multimode must have been previously configured using
bogdanm 0:9b334a45a8ff 627 * HAL_ADCEx_MultiModeConfigChannel() function.
bogdanm 0:9b334a45a8ff 628 * Interruptions enabled in this function:
bogdanm 0:9b334a45a8ff 629 * - DMA transfer complete
bogdanm 0:9b334a45a8ff 630 * - DMA half transfer
bogdanm 0:9b334a45a8ff 631 * Each of these interruptions has its dedicated callback function.
bogdanm 0:9b334a45a8ff 632 * @note: On STM32F1 devices, ADC slave regular group must be configured
bogdanm 0:9b334a45a8ff 633 * with conversion trigger ADC_SOFTWARE_START.
bogdanm 0:9b334a45a8ff 634 * @note: ADC slave can be enabled preliminarily using single-mode
bogdanm 0:9b334a45a8ff 635 * HAL_ADC_Start() function.
bogdanm 0:9b334a45a8ff 636 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
bogdanm 0:9b334a45a8ff 637 * @param pData: The destination Buffer address.
bogdanm 0:9b334a45a8ff 638 * @param Length: The length of data to be transferred from ADC peripheral to memory.
bogdanm 0:9b334a45a8ff 639 * @retval None
bogdanm 0:9b334a45a8ff 640 */
bogdanm 0:9b334a45a8ff 641 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
bogdanm 0:9b334a45a8ff 642 {
bogdanm 0:9b334a45a8ff 643 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm 0:9b334a45a8ff 644 ADC_HandleTypeDef tmphadcSlave;
bogdanm 0:9b334a45a8ff 645
bogdanm 0:9b334a45a8ff 646 /* Check the parameters */
bogdanm 0:9b334a45a8ff 647 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 648 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650 /* Process locked */
bogdanm 0:9b334a45a8ff 651 __HAL_LOCK(hadc);
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 /* Set a temporary handle of the ADC slave associated to the ADC master */
bogdanm 0:9b334a45a8ff 654 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656 /* On STM32F1 devices, ADC slave regular group must be configured with */
bogdanm 0:9b334a45a8ff 657 /* conversion trigger ADC_SOFTWARE_START. */
bogdanm 0:9b334a45a8ff 658 /* Note: External trigger of ADC slave must be enabled, it is already done */
bogdanm 0:9b334a45a8ff 659 /* into function "HAL_ADC_Init()". */
bogdanm 0:9b334a45a8ff 660 if ((tmphadcSlave.Instance == NULL) ||
bogdanm 0:9b334a45a8ff 661 (! ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) )
bogdanm 0:9b334a45a8ff 662 {
bogdanm 0:9b334a45a8ff 663 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 664 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 665
bogdanm 0:9b334a45a8ff 666 /* Process unlocked */
bogdanm 0:9b334a45a8ff 667 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 668
bogdanm 0:9b334a45a8ff 669 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 670 }
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 /* Enable the ADC peripherals: master and slave (in case if not already */
bogdanm 0:9b334a45a8ff 673 /* enabled previously) */
bogdanm 0:9b334a45a8ff 674 tmp_hal_status = ADC_Enable(hadc);
bogdanm 0:9b334a45a8ff 675 if (tmp_hal_status != HAL_ERROR)
bogdanm 0:9b334a45a8ff 676 {
bogdanm 0:9b334a45a8ff 677 tmp_hal_status = ADC_Enable(&tmphadcSlave);
bogdanm 0:9b334a45a8ff 678 }
bogdanm 0:9b334a45a8ff 679
bogdanm 0:9b334a45a8ff 680 /* Start conversion all ADCs of multimode are effectively enabled */
bogdanm 0:9b334a45a8ff 681 if (tmp_hal_status != HAL_ERROR)
bogdanm 0:9b334a45a8ff 682 {
bogdanm 0:9b334a45a8ff 683 /* State machine update (ADC master): Check if an injected conversion is */
bogdanm 0:9b334a45a8ff 684 /* ongoing. */
bogdanm 0:9b334a45a8ff 685 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
bogdanm 0:9b334a45a8ff 686 {
bogdanm 0:9b334a45a8ff 687 /* Change ADC state */
bogdanm 0:9b334a45a8ff 688 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
bogdanm 0:9b334a45a8ff 689 }
bogdanm 0:9b334a45a8ff 690 else
bogdanm 0:9b334a45a8ff 691 {
bogdanm 0:9b334a45a8ff 692 /* Change ADC state */
bogdanm 0:9b334a45a8ff 693 hadc->State = HAL_ADC_STATE_BUSY_REG;
bogdanm 0:9b334a45a8ff 694 }
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 /* Process unlocked */
bogdanm 0:9b334a45a8ff 697 /* Unlock before starting ADC conversions: in case of potential */
bogdanm 0:9b334a45a8ff 698 /* interruption, to let the process to ADC IRQ Handler. */
bogdanm 0:9b334a45a8ff 699 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /* Set ADC error code to none */
bogdanm 0:9b334a45a8ff 702 ADC_CLEAR_ERRORCODE(hadc);
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704
bogdanm 0:9b334a45a8ff 705 /* Set the DMA transfer complete callback */
bogdanm 0:9b334a45a8ff 706 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
bogdanm 0:9b334a45a8ff 707
bogdanm 0:9b334a45a8ff 708 /* Set the DMA half transfer complete callback */
bogdanm 0:9b334a45a8ff 709 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
bogdanm 0:9b334a45a8ff 710
bogdanm 0:9b334a45a8ff 711 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 712 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
bogdanm 0:9b334a45a8ff 713
bogdanm 0:9b334a45a8ff 714
bogdanm 0:9b334a45a8ff 715 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
bogdanm 0:9b334a45a8ff 716 /* start (in case of SW start): */
bogdanm 0:9b334a45a8ff 717
bogdanm 0:9b334a45a8ff 718 /* Clear regular group conversion flag and overrun flag */
bogdanm 0:9b334a45a8ff 719 /* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm 0:9b334a45a8ff 720 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm 0:9b334a45a8ff 721
bogdanm 0:9b334a45a8ff 722 /* Enable ADC DMA mode of ADC master */
bogdanm 0:9b334a45a8ff 723 SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
bogdanm 0:9b334a45a8ff 724
bogdanm 0:9b334a45a8ff 725 /* Start the DMA channel */
bogdanm 0:9b334a45a8ff 726 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
bogdanm 0:9b334a45a8ff 727
bogdanm 0:9b334a45a8ff 728 /* Start conversion of regular group if software start has been selected. */
bogdanm 0:9b334a45a8ff 729 /* If external trigger has been selected, conversion will start at next */
bogdanm 0:9b334a45a8ff 730 /* trigger event. */
bogdanm 0:9b334a45a8ff 731 /* Note: Alternate trigger for single conversion could be to force an */
bogdanm 0:9b334a45a8ff 732 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
bogdanm 0:9b334a45a8ff 733 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
bogdanm 0:9b334a45a8ff 734 {
bogdanm 0:9b334a45a8ff 735 /* Start ADC conversion on regular group with SW start */
bogdanm 0:9b334a45a8ff 736 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
bogdanm 0:9b334a45a8ff 737 }
bogdanm 0:9b334a45a8ff 738 else
bogdanm 0:9b334a45a8ff 739 {
bogdanm 0:9b334a45a8ff 740 /* Start ADC conversion on regular group with external trigger */
bogdanm 0:9b334a45a8ff 741 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
bogdanm 0:9b334a45a8ff 742 }
bogdanm 0:9b334a45a8ff 743 }
bogdanm 0:9b334a45a8ff 744 else
bogdanm 0:9b334a45a8ff 745 {
bogdanm 0:9b334a45a8ff 746 /* Process unlocked */
bogdanm 0:9b334a45a8ff 747 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 748 }
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 /* Return function status */
bogdanm 0:9b334a45a8ff 751 return tmp_hal_status;
bogdanm 0:9b334a45a8ff 752 }
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 /**
bogdanm 0:9b334a45a8ff 755 * @brief Stop ADC conversion of regular group (and injected channels in
bogdanm 0:9b334a45a8ff 756 * case of auto_injection mode), disable ADC DMA transfer, disable
bogdanm 0:9b334a45a8ff 757 * ADC peripheral.
bogdanm 0:9b334a45a8ff 758 * @note Multimode is kept enabled after this function. To disable multimode
bogdanm 0:9b334a45a8ff 759 * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be
bogdanm 0:9b334a45a8ff 760 * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
bogdanm 0:9b334a45a8ff 761 * @note In case of DMA configured in circular mode, function
bogdanm 0:9b334a45a8ff 762 * HAL_ADC_Stop_DMA must be called after this function with handle of
bogdanm 0:9b334a45a8ff 763 * ADC slave, to properly disable the DMA channel.
bogdanm 0:9b334a45a8ff 764 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
bogdanm 0:9b334a45a8ff 765 * @retval None
bogdanm 0:9b334a45a8ff 766 */
bogdanm 0:9b334a45a8ff 767 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
bogdanm 0:9b334a45a8ff 768 {
bogdanm 0:9b334a45a8ff 769 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm 0:9b334a45a8ff 770 ADC_HandleTypeDef tmphadcSlave;
bogdanm 0:9b334a45a8ff 771
bogdanm 0:9b334a45a8ff 772 /* Check the parameters */
bogdanm 0:9b334a45a8ff 773 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 774
bogdanm 0:9b334a45a8ff 775 /* Process locked */
bogdanm 0:9b334a45a8ff 776 __HAL_LOCK(hadc);
bogdanm 0:9b334a45a8ff 777
bogdanm 0:9b334a45a8ff 778
bogdanm 0:9b334a45a8ff 779 /* Stop potential conversion on going, on regular and injected groups */
bogdanm 0:9b334a45a8ff 780 /* Disable ADC master peripheral */
bogdanm 0:9b334a45a8ff 781 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
bogdanm 0:9b334a45a8ff 782
bogdanm 0:9b334a45a8ff 783 /* Check if ADC is effectively disabled */
bogdanm 0:9b334a45a8ff 784 if (tmp_hal_status != HAL_ERROR)
bogdanm 0:9b334a45a8ff 785 {
bogdanm 0:9b334a45a8ff 786 /* Set a temporary handle of the ADC slave associated to the ADC master */
bogdanm 0:9b334a45a8ff 787 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
bogdanm 0:9b334a45a8ff 788
bogdanm 0:9b334a45a8ff 789 if (tmphadcSlave.Instance == NULL)
bogdanm 0:9b334a45a8ff 790 {
bogdanm 0:9b334a45a8ff 791 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 792 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 793
bogdanm 0:9b334a45a8ff 794 /* Process unlocked */
bogdanm 0:9b334a45a8ff 795 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 796
bogdanm 0:9b334a45a8ff 797 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 798 }
bogdanm 0:9b334a45a8ff 799 else
bogdanm 0:9b334a45a8ff 800 {
bogdanm 0:9b334a45a8ff 801 /* Disable ADC slave peripheral */
bogdanm 0:9b334a45a8ff 802 tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);
bogdanm 0:9b334a45a8ff 803
bogdanm 0:9b334a45a8ff 804 /* Check if ADC is effectively disabled */
bogdanm 0:9b334a45a8ff 805 if (tmp_hal_status != HAL_OK)
bogdanm 0:9b334a45a8ff 806 {
bogdanm 0:9b334a45a8ff 807 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 808 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 809
bogdanm 0:9b334a45a8ff 810 /* Process unlocked */
bogdanm 0:9b334a45a8ff 811 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 814 }
bogdanm 0:9b334a45a8ff 815 }
bogdanm 0:9b334a45a8ff 816
bogdanm 0:9b334a45a8ff 817 /* Disable ADC DMA mode */
bogdanm 0:9b334a45a8ff 818 CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
bogdanm 0:9b334a45a8ff 819
bogdanm 0:9b334a45a8ff 820 /* Reset configuration of ADC DMA continuous request for dual mode */
bogdanm 0:9b334a45a8ff 821 CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD);
bogdanm 0:9b334a45a8ff 822
bogdanm 0:9b334a45a8ff 823 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
bogdanm 0:9b334a45a8ff 824 /* while DMA transfer is on going) */
bogdanm 0:9b334a45a8ff 825 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
bogdanm 0:9b334a45a8ff 826
bogdanm 0:9b334a45a8ff 827
bogdanm 0:9b334a45a8ff 828 /* Check if DMA channel effectively disabled */
bogdanm 0:9b334a45a8ff 829 if (tmp_hal_status != HAL_ERROR)
bogdanm 0:9b334a45a8ff 830 {
bogdanm 0:9b334a45a8ff 831 /* Change ADC state (ADC master) */
bogdanm 0:9b334a45a8ff 832 hadc->State = HAL_ADC_STATE_READY;
bogdanm 0:9b334a45a8ff 833 }
bogdanm 0:9b334a45a8ff 834 else
bogdanm 0:9b334a45a8ff 835 {
bogdanm 0:9b334a45a8ff 836 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 837 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 838 }
bogdanm 0:9b334a45a8ff 839 }
bogdanm 0:9b334a45a8ff 840
bogdanm 0:9b334a45a8ff 841 /* Process unlocked */
bogdanm 0:9b334a45a8ff 842 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 /* Return function status */
bogdanm 0:9b334a45a8ff 845 return tmp_hal_status;
bogdanm 0:9b334a45a8ff 846 }
bogdanm 0:9b334a45a8ff 847 #endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
bogdanm 0:9b334a45a8ff 848
bogdanm 0:9b334a45a8ff 849 /**
bogdanm 0:9b334a45a8ff 850 * @brief Get ADC injected group conversion result.
bogdanm 0:9b334a45a8ff 851 * @param hadc: ADC handle
bogdanm 0:9b334a45a8ff 852 * @param InjectedRank: the converted ADC injected rank.
bogdanm 0:9b334a45a8ff 853 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 854 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
bogdanm 0:9b334a45a8ff 855 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
bogdanm 0:9b334a45a8ff 856 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
bogdanm 0:9b334a45a8ff 857 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
bogdanm 0:9b334a45a8ff 858 * @retval None
bogdanm 0:9b334a45a8ff 859 */
bogdanm 0:9b334a45a8ff 860 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
bogdanm 0:9b334a45a8ff 861 {
bogdanm 0:9b334a45a8ff 862 uint32_t tmp_jdr = 0;
bogdanm 0:9b334a45a8ff 863
bogdanm 0:9b334a45a8ff 864 /* Check the parameters */
bogdanm 0:9b334a45a8ff 865 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 866 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
bogdanm 0:9b334a45a8ff 867
bogdanm 0:9b334a45a8ff 868 /* Clear injected group conversion flag to have similar behaviour as */
bogdanm 0:9b334a45a8ff 869 /* regular group: reading data register also clears end of conversion flag. */
bogdanm 0:9b334a45a8ff 870 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
bogdanm 0:9b334a45a8ff 871
bogdanm 0:9b334a45a8ff 872 /* Get ADC converted value */
bogdanm 0:9b334a45a8ff 873 switch(InjectedRank)
bogdanm 0:9b334a45a8ff 874 {
bogdanm 0:9b334a45a8ff 875 case ADC_INJECTED_RANK_4:
bogdanm 0:9b334a45a8ff 876 tmp_jdr = hadc->Instance->JDR4;
bogdanm 0:9b334a45a8ff 877 break;
bogdanm 0:9b334a45a8ff 878 case ADC_INJECTED_RANK_3:
bogdanm 0:9b334a45a8ff 879 tmp_jdr = hadc->Instance->JDR3;
bogdanm 0:9b334a45a8ff 880 break;
bogdanm 0:9b334a45a8ff 881 case ADC_INJECTED_RANK_2:
bogdanm 0:9b334a45a8ff 882 tmp_jdr = hadc->Instance->JDR2;
bogdanm 0:9b334a45a8ff 883 break;
bogdanm 0:9b334a45a8ff 884 case ADC_INJECTED_RANK_1:
bogdanm 0:9b334a45a8ff 885 default:
bogdanm 0:9b334a45a8ff 886 tmp_jdr = hadc->Instance->JDR1;
bogdanm 0:9b334a45a8ff 887 break;
bogdanm 0:9b334a45a8ff 888 }
bogdanm 0:9b334a45a8ff 889
bogdanm 0:9b334a45a8ff 890 /* Return ADC converted value */
bogdanm 0:9b334a45a8ff 891 return tmp_jdr;
bogdanm 0:9b334a45a8ff 892 }
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 #if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
bogdanm 0:9b334a45a8ff 895 /**
bogdanm 0:9b334a45a8ff 896 * @brief Returns the last ADC Master&Slave regular conversions results data
bogdanm 0:9b334a45a8ff 897 * in the selected multi mode.
bogdanm 0:9b334a45a8ff 898 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
bogdanm 0:9b334a45a8ff 899 * @retval The converted data value.
bogdanm 0:9b334a45a8ff 900 */
bogdanm 0:9b334a45a8ff 901 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
bogdanm 0:9b334a45a8ff 902 {
bogdanm 0:9b334a45a8ff 903 uint32_t tmpDR = 0;
bogdanm 0:9b334a45a8ff 904
bogdanm 0:9b334a45a8ff 905 /* Check the parameters */
bogdanm 0:9b334a45a8ff 906 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 907
bogdanm 0:9b334a45a8ff 908 /* Check the parameters */
bogdanm 0:9b334a45a8ff 909 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 910
bogdanm 0:9b334a45a8ff 911 /* Note: EOC flag is not cleared here by software because automatically */
bogdanm 0:9b334a45a8ff 912 /* cleared by hardware when reading register DR. */
bogdanm 0:9b334a45a8ff 913
bogdanm 0:9b334a45a8ff 914 /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions */
bogdanm 0:9b334a45a8ff 915 /* only if ADC1 DMA mode is enabled. */
bogdanm 0:9b334a45a8ff 916 tmpDR = hadc->Instance->DR;
bogdanm 0:9b334a45a8ff 917
bogdanm 0:9b334a45a8ff 918 if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA))
bogdanm 0:9b334a45a8ff 919 {
bogdanm 0:9b334a45a8ff 920 tmpDR |= (ADC2->DR << 16);
bogdanm 0:9b334a45a8ff 921 }
bogdanm 0:9b334a45a8ff 922
bogdanm 0:9b334a45a8ff 923 /* Return ADC converted value */
bogdanm 0:9b334a45a8ff 924 return tmpDR;
bogdanm 0:9b334a45a8ff 925 }
bogdanm 0:9b334a45a8ff 926 #endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
bogdanm 0:9b334a45a8ff 927
bogdanm 0:9b334a45a8ff 928 /**
bogdanm 0:9b334a45a8ff 929 * @brief Injected conversion complete callback in non blocking mode
bogdanm 0:9b334a45a8ff 930 * @param hadc: ADC handle
bogdanm 0:9b334a45a8ff 931 * @retval None
bogdanm 0:9b334a45a8ff 932 */
bogdanm 0:9b334a45a8ff 933 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm 0:9b334a45a8ff 934 {
bogdanm 0:9b334a45a8ff 935 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 936 the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 937 */
bogdanm 0:9b334a45a8ff 938 }
bogdanm 0:9b334a45a8ff 939
bogdanm 0:9b334a45a8ff 940 /**
bogdanm 0:9b334a45a8ff 941 * @}
bogdanm 0:9b334a45a8ff 942 */
bogdanm 0:9b334a45a8ff 943
bogdanm 0:9b334a45a8ff 944 /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 945 * @brief Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 946 *
bogdanm 0:9b334a45a8ff 947 @verbatim
bogdanm 0:9b334a45a8ff 948 ===============================================================================
bogdanm 0:9b334a45a8ff 949 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 950 ===============================================================================
bogdanm 0:9b334a45a8ff 951 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 952 (+) Configure channels on injected group
bogdanm 0:9b334a45a8ff 953 (+) Configure multimode
bogdanm 0:9b334a45a8ff 954
bogdanm 0:9b334a45a8ff 955 @endverbatim
bogdanm 0:9b334a45a8ff 956 * @{
bogdanm 0:9b334a45a8ff 957 */
bogdanm 0:9b334a45a8ff 958
bogdanm 0:9b334a45a8ff 959 /**
bogdanm 0:9b334a45a8ff 960 * @brief Configures the ADC injected group and the selected channel to be
bogdanm 0:9b334a45a8ff 961 * linked to the injected group.
bogdanm 0:9b334a45a8ff 962 * @note Possibility to update parameters on the fly:
bogdanm 0:9b334a45a8ff 963 * This function initializes injected group, following calls to this
bogdanm 0:9b334a45a8ff 964 * function can be used to reconfigure some parameters of structure
bogdanm 0:9b334a45a8ff 965 * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
bogdanm 0:9b334a45a8ff 966 * The setting of these parameters is conditioned to ADC state:
bogdanm 0:9b334a45a8ff 967 * this function must be called when ADC is not under conversion.
bogdanm 0:9b334a45a8ff 968 * @param hadc: ADC handle
bogdanm 0:9b334a45a8ff 969 * @param sConfigInjected: Structure of ADC injected group and ADC channel for
bogdanm 0:9b334a45a8ff 970 * injected group.
bogdanm 0:9b334a45a8ff 971 * @retval None
bogdanm 0:9b334a45a8ff 972 */
bogdanm 0:9b334a45a8ff 973 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
bogdanm 0:9b334a45a8ff 974 {
bogdanm 0:9b334a45a8ff 975 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm 0:9b334a45a8ff 976 __IO uint32_t wait_loop_index = 0;
bogdanm 0:9b334a45a8ff 977
bogdanm 0:9b334a45a8ff 978 /* Check the parameters */
bogdanm 0:9b334a45a8ff 979 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 980 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
bogdanm 0:9b334a45a8ff 981 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
bogdanm 0:9b334a45a8ff 982 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
bogdanm 0:9b334a45a8ff 983 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
bogdanm 0:9b334a45a8ff 984 assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
bogdanm 0:9b334a45a8ff 985
bogdanm 0:9b334a45a8ff 986 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
bogdanm 0:9b334a45a8ff 987 {
bogdanm 0:9b334a45a8ff 988 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
bogdanm 0:9b334a45a8ff 989 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
bogdanm 0:9b334a45a8ff 990 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
bogdanm 0:9b334a45a8ff 991 }
bogdanm 0:9b334a45a8ff 992
bogdanm 0:9b334a45a8ff 993 /* Process locked */
bogdanm 0:9b334a45a8ff 994 __HAL_LOCK(hadc);
bogdanm 0:9b334a45a8ff 995
bogdanm 0:9b334a45a8ff 996 /* Configuration of injected group sequencer: */
bogdanm 0:9b334a45a8ff 997 /* - if scan mode is disabled, injected channels sequence length is set to */
bogdanm 0:9b334a45a8ff 998 /* 0x00: 1 channel converted (channel on regular rank 1) */
bogdanm 0:9b334a45a8ff 999 /* Parameter "InjectedNbrOfConversion" is discarded. */
bogdanm 0:9b334a45a8ff 1000 /* Note: Scan mode is present by hardware on this device and, if */
bogdanm 0:9b334a45a8ff 1001 /* disabled, discards automatically nb of conversions. Anyway, nb of */
bogdanm 0:9b334a45a8ff 1002 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
bogdanm 0:9b334a45a8ff 1003 /* - if scan mode is enabled, injected channels sequence length is set to */
bogdanm 0:9b334a45a8ff 1004 /* parameter "InjectedNbrOfConversion". */
bogdanm 0:9b334a45a8ff 1005 if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
bogdanm 0:9b334a45a8ff 1006 {
bogdanm 0:9b334a45a8ff 1007 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
bogdanm 0:9b334a45a8ff 1008 {
bogdanm 0:9b334a45a8ff 1009 /* Clear the old SQx bits for all injected ranks */
bogdanm 0:9b334a45a8ff 1010 MODIFY_REG(hadc->Instance->JSQR ,
bogdanm 0:9b334a45a8ff 1011 ADC_JSQR_JL |
bogdanm 0:9b334a45a8ff 1012 ADC_JSQR_JSQ4 |
bogdanm 0:9b334a45a8ff 1013 ADC_JSQR_JSQ3 |
bogdanm 0:9b334a45a8ff 1014 ADC_JSQR_JSQ2 |
bogdanm 0:9b334a45a8ff 1015 ADC_JSQR_JSQ1 ,
bogdanm 0:9b334a45a8ff 1016 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
bogdanm 0:9b334a45a8ff 1017 ADC_INJECTED_RANK_1,
bogdanm 0:9b334a45a8ff 1018 0x01) );
bogdanm 0:9b334a45a8ff 1019 }
bogdanm 0:9b334a45a8ff 1020 /* If another injected rank than rank1 was intended to be set, and could */
bogdanm 0:9b334a45a8ff 1021 /* not due to ScanConvMode disabled, error is reported. */
bogdanm 0:9b334a45a8ff 1022 else
bogdanm 0:9b334a45a8ff 1023 {
bogdanm 0:9b334a45a8ff 1024 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 1025 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 1026
bogdanm 0:9b334a45a8ff 1027 tmp_hal_status = HAL_ERROR;
bogdanm 0:9b334a45a8ff 1028 }
bogdanm 0:9b334a45a8ff 1029 }
bogdanm 0:9b334a45a8ff 1030 else
bogdanm 0:9b334a45a8ff 1031 {
bogdanm 0:9b334a45a8ff 1032 /* Since injected channels rank conv. order depends on total number of */
bogdanm 0:9b334a45a8ff 1033 /* injected conversions, selected rank must be below or equal to total */
bogdanm 0:9b334a45a8ff 1034 /* number of injected conversions to be updated. */
bogdanm 0:9b334a45a8ff 1035 if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
bogdanm 0:9b334a45a8ff 1036 {
bogdanm 0:9b334a45a8ff 1037 /* Clear the old SQx bits for the selected rank */
bogdanm 0:9b334a45a8ff 1038 /* Set the SQx bits for the selected rank */
bogdanm 0:9b334a45a8ff 1039 MODIFY_REG(hadc->Instance->JSQR ,
bogdanm 0:9b334a45a8ff 1040
bogdanm 0:9b334a45a8ff 1041 ADC_JSQR_JL |
bogdanm 0:9b334a45a8ff 1042 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
bogdanm 0:9b334a45a8ff 1043 sConfigInjected->InjectedRank,
bogdanm 0:9b334a45a8ff 1044 sConfigInjected->InjectedNbrOfConversion) ,
bogdanm 0:9b334a45a8ff 1045
bogdanm 0:9b334a45a8ff 1046 ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
bogdanm 0:9b334a45a8ff 1047 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
bogdanm 0:9b334a45a8ff 1048 sConfigInjected->InjectedRank,
bogdanm 0:9b334a45a8ff 1049 sConfigInjected->InjectedNbrOfConversion) );
bogdanm 0:9b334a45a8ff 1050 }
bogdanm 0:9b334a45a8ff 1051 else
bogdanm 0:9b334a45a8ff 1052 {
bogdanm 0:9b334a45a8ff 1053 /* Clear the old SQx bits for the selected rank */
bogdanm 0:9b334a45a8ff 1054 MODIFY_REG(hadc->Instance->JSQR ,
bogdanm 0:9b334a45a8ff 1055
bogdanm 0:9b334a45a8ff 1056 ADC_JSQR_JL |
bogdanm 0:9b334a45a8ff 1057 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
bogdanm 0:9b334a45a8ff 1058 sConfigInjected->InjectedRank,
bogdanm 0:9b334a45a8ff 1059 sConfigInjected->InjectedNbrOfConversion) ,
bogdanm 0:9b334a45a8ff 1060
bogdanm 0:9b334a45a8ff 1061 0x00000000 );
bogdanm 0:9b334a45a8ff 1062 }
bogdanm 0:9b334a45a8ff 1063 }
bogdanm 0:9b334a45a8ff 1064
bogdanm 0:9b334a45a8ff 1065 /* Configuration of injected group */
bogdanm 0:9b334a45a8ff 1066 /* Parameters update conditioned to ADC state: */
bogdanm 0:9b334a45a8ff 1067 /* Parameters that can be updated only when ADC is disabled: */
bogdanm 0:9b334a45a8ff 1068 /* - external trigger to start conversion */
bogdanm 0:9b334a45a8ff 1069 /* Parameters update not conditioned to ADC state: */
bogdanm 0:9b334a45a8ff 1070 /* - Automatic injected conversion */
bogdanm 0:9b334a45a8ff 1071 /* - Injected discontinuous mode */
bogdanm 0:9b334a45a8ff 1072 /* Note: In case of ADC already enabled, caution to not launch an unwanted */
bogdanm 0:9b334a45a8ff 1073 /* conversion while modifying register CR2 by writing 1 to bit ADON. */
bogdanm 0:9b334a45a8ff 1074 if (ADC_IS_ENABLE(hadc) == RESET)
bogdanm 0:9b334a45a8ff 1075 {
bogdanm 0:9b334a45a8ff 1076 MODIFY_REG(hadc->Instance->CR2 ,
bogdanm 0:9b334a45a8ff 1077 ADC_CR2_JEXTSEL |
bogdanm 0:9b334a45a8ff 1078 ADC_CR2_ADON ,
bogdanm 0:9b334a45a8ff 1079 ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) );
bogdanm 0:9b334a45a8ff 1080 }
bogdanm 0:9b334a45a8ff 1081
bogdanm 0:9b334a45a8ff 1082
bogdanm 0:9b334a45a8ff 1083 /* Configuration of injected group */
bogdanm 0:9b334a45a8ff 1084 /* - Automatic injected conversion */
bogdanm 0:9b334a45a8ff 1085 /* - Injected discontinuous mode */
bogdanm 0:9b334a45a8ff 1086
bogdanm 0:9b334a45a8ff 1087 /* Automatic injected conversion can be enabled if injected group */
bogdanm 0:9b334a45a8ff 1088 /* external triggers are disabled. */
bogdanm 0:9b334a45a8ff 1089 if (sConfigInjected->AutoInjectedConv == ENABLE)
bogdanm 0:9b334a45a8ff 1090 {
bogdanm 0:9b334a45a8ff 1091 if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
bogdanm 0:9b334a45a8ff 1092 {
bogdanm 0:9b334a45a8ff 1093 SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
bogdanm 0:9b334a45a8ff 1094 }
bogdanm 0:9b334a45a8ff 1095 else
bogdanm 0:9b334a45a8ff 1096 {
bogdanm 0:9b334a45a8ff 1097 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 1098 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 1099
bogdanm 0:9b334a45a8ff 1100 tmp_hal_status = HAL_ERROR;
bogdanm 0:9b334a45a8ff 1101 }
bogdanm 0:9b334a45a8ff 1102 }
bogdanm 0:9b334a45a8ff 1103
bogdanm 0:9b334a45a8ff 1104 /* Injected discontinuous can be enabled only if auto-injected mode is */
bogdanm 0:9b334a45a8ff 1105 /* disabled. */
bogdanm 0:9b334a45a8ff 1106 if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
bogdanm 0:9b334a45a8ff 1107 {
bogdanm 0:9b334a45a8ff 1108 if (sConfigInjected->AutoInjectedConv == DISABLE)
bogdanm 0:9b334a45a8ff 1109 {
bogdanm 0:9b334a45a8ff 1110 SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
bogdanm 0:9b334a45a8ff 1111 }
bogdanm 0:9b334a45a8ff 1112 else
bogdanm 0:9b334a45a8ff 1113 {
bogdanm 0:9b334a45a8ff 1114 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 1115 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 1116
bogdanm 0:9b334a45a8ff 1117 tmp_hal_status = HAL_ERROR;
bogdanm 0:9b334a45a8ff 1118 }
bogdanm 0:9b334a45a8ff 1119 }
bogdanm 0:9b334a45a8ff 1120
bogdanm 0:9b334a45a8ff 1121
bogdanm 0:9b334a45a8ff 1122 /* InjectedChannel sampling time configuration */
bogdanm 0:9b334a45a8ff 1123 /* For channels 10 to 17 */
bogdanm 0:9b334a45a8ff 1124 if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
bogdanm 0:9b334a45a8ff 1125 {
bogdanm 0:9b334a45a8ff 1126 MODIFY_REG(hadc->Instance->SMPR1 ,
bogdanm 0:9b334a45a8ff 1127 ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel) ,
bogdanm 0:9b334a45a8ff 1128 ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
bogdanm 0:9b334a45a8ff 1129 }
bogdanm 0:9b334a45a8ff 1130 else /* For channels 0 to 9 */
bogdanm 0:9b334a45a8ff 1131 {
bogdanm 0:9b334a45a8ff 1132 MODIFY_REG(hadc->Instance->SMPR2 ,
bogdanm 0:9b334a45a8ff 1133 ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel) ,
bogdanm 0:9b334a45a8ff 1134 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
bogdanm 0:9b334a45a8ff 1135 }
bogdanm 0:9b334a45a8ff 1136
bogdanm 0:9b334a45a8ff 1137 /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor */
bogdanm 0:9b334a45a8ff 1138 /* and VREFINT measurement path. */
bogdanm 0:9b334a45a8ff 1139 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
bogdanm 0:9b334a45a8ff 1140 (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
bogdanm 0:9b334a45a8ff 1141 {
bogdanm 0:9b334a45a8ff 1142 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
bogdanm 0:9b334a45a8ff 1143 }
bogdanm 0:9b334a45a8ff 1144
bogdanm 0:9b334a45a8ff 1145
bogdanm 0:9b334a45a8ff 1146 /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
bogdanm 0:9b334a45a8ff 1147 switch(sConfigInjected->InjectedRank)
bogdanm 0:9b334a45a8ff 1148 {
bogdanm 0:9b334a45a8ff 1149 case 1:
bogdanm 0:9b334a45a8ff 1150 /* Set injected channel 1 offset */
bogdanm 0:9b334a45a8ff 1151 MODIFY_REG(hadc->Instance->JOFR1,
bogdanm 0:9b334a45a8ff 1152 ADC_JOFR1_JOFFSET1,
bogdanm 0:9b334a45a8ff 1153 sConfigInjected->InjectedOffset);
bogdanm 0:9b334a45a8ff 1154 break;
bogdanm 0:9b334a45a8ff 1155 case 2:
bogdanm 0:9b334a45a8ff 1156 /* Set injected channel 2 offset */
bogdanm 0:9b334a45a8ff 1157 MODIFY_REG(hadc->Instance->JOFR2,
bogdanm 0:9b334a45a8ff 1158 ADC_JOFR2_JOFFSET2,
bogdanm 0:9b334a45a8ff 1159 sConfigInjected->InjectedOffset);
bogdanm 0:9b334a45a8ff 1160 break;
bogdanm 0:9b334a45a8ff 1161 case 3:
bogdanm 0:9b334a45a8ff 1162 /* Set injected channel 3 offset */
bogdanm 0:9b334a45a8ff 1163 MODIFY_REG(hadc->Instance->JOFR3,
bogdanm 0:9b334a45a8ff 1164 ADC_JOFR3_JOFFSET3,
bogdanm 0:9b334a45a8ff 1165 sConfigInjected->InjectedOffset);
bogdanm 0:9b334a45a8ff 1166 break;
bogdanm 0:9b334a45a8ff 1167 case 4:
bogdanm 0:9b334a45a8ff 1168 default:
bogdanm 0:9b334a45a8ff 1169 MODIFY_REG(hadc->Instance->JOFR4,
bogdanm 0:9b334a45a8ff 1170 ADC_JOFR4_JOFFSET4,
bogdanm 0:9b334a45a8ff 1171 sConfigInjected->InjectedOffset);
bogdanm 0:9b334a45a8ff 1172 break;
bogdanm 0:9b334a45a8ff 1173 }
bogdanm 0:9b334a45a8ff 1174
bogdanm 0:9b334a45a8ff 1175 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
bogdanm 0:9b334a45a8ff 1176 /* and VREFINT measurement path. */
bogdanm 0:9b334a45a8ff 1177 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
bogdanm 0:9b334a45a8ff 1178 (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
bogdanm 0:9b334a45a8ff 1179 {
bogdanm 0:9b334a45a8ff 1180 /* For STM32F1 devices with several ADC: Only ADC1 can access internal */
bogdanm 0:9b334a45a8ff 1181 /* measurement channels (VrefInt/TempSensor). If these channels are */
bogdanm 0:9b334a45a8ff 1182 /* intended to be set on other ADC instances, an error is reported. */
bogdanm 0:9b334a45a8ff 1183 if (hadc->Instance == ADC1)
bogdanm 0:9b334a45a8ff 1184 {
bogdanm 0:9b334a45a8ff 1185 if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
bogdanm 0:9b334a45a8ff 1186 {
bogdanm 0:9b334a45a8ff 1187 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
bogdanm 0:9b334a45a8ff 1188
bogdanm 0:9b334a45a8ff 1189 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
bogdanm 0:9b334a45a8ff 1190 {
bogdanm 0:9b334a45a8ff 1191 /* Delay for temperature sensor stabilization time */
bogdanm 0:9b334a45a8ff 1192 /* Compute number of CPU cycles to wait for */
bogdanm 0:9b334a45a8ff 1193 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
bogdanm 0:9b334a45a8ff 1194 while(wait_loop_index != 0)
bogdanm 0:9b334a45a8ff 1195 {
bogdanm 0:9b334a45a8ff 1196 wait_loop_index--;
bogdanm 0:9b334a45a8ff 1197 }
bogdanm 0:9b334a45a8ff 1198 }
bogdanm 0:9b334a45a8ff 1199 }
bogdanm 0:9b334a45a8ff 1200 }
bogdanm 0:9b334a45a8ff 1201 else
bogdanm 0:9b334a45a8ff 1202 {
bogdanm 0:9b334a45a8ff 1203 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 1204 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 1205
bogdanm 0:9b334a45a8ff 1206 tmp_hal_status = HAL_ERROR;
bogdanm 0:9b334a45a8ff 1207 }
bogdanm 0:9b334a45a8ff 1208 }
bogdanm 0:9b334a45a8ff 1209
bogdanm 0:9b334a45a8ff 1210 /* Process unlocked */
bogdanm 0:9b334a45a8ff 1211 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 1212
bogdanm 0:9b334a45a8ff 1213 /* Return function status */
bogdanm 0:9b334a45a8ff 1214 return tmp_hal_status;
bogdanm 0:9b334a45a8ff 1215 }
bogdanm 0:9b334a45a8ff 1216
bogdanm 0:9b334a45a8ff 1217 #if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
bogdanm 0:9b334a45a8ff 1218 /**
bogdanm 0:9b334a45a8ff 1219 * @brief Enable ADC multimode and configure multimode parameters
bogdanm 0:9b334a45a8ff 1220 * @note Possibility to update parameters on the fly:
bogdanm 0:9b334a45a8ff 1221 * This function initializes multimode parameters, following
bogdanm 0:9b334a45a8ff 1222 * calls to this function can be used to reconfigure some parameters
bogdanm 0:9b334a45a8ff 1223 * of structure "ADC_MultiModeTypeDef" on the fly, without reseting
bogdanm 0:9b334a45a8ff 1224 * the ADCs (both ADCs of the common group).
bogdanm 0:9b334a45a8ff 1225 * The setting of these parameters is conditioned to ADC state.
bogdanm 0:9b334a45a8ff 1226 * For parameters constraints, see comments of structure
bogdanm 0:9b334a45a8ff 1227 * "ADC_MultiModeTypeDef".
bogdanm 0:9b334a45a8ff 1228 * @note To change back configuration from multimode to single mode, ADC must
bogdanm 0:9b334a45a8ff 1229 * be reset (using function HAL_ADC_Init() ).
bogdanm 0:9b334a45a8ff 1230 * @param hadc: ADC handle
bogdanm 0:9b334a45a8ff 1231 * @param multimode: Structure of ADC multimode configuration
bogdanm 0:9b334a45a8ff 1232 * @retval HAL status
bogdanm 0:9b334a45a8ff 1233 */
bogdanm 0:9b334a45a8ff 1234 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
bogdanm 0:9b334a45a8ff 1235 {
bogdanm 0:9b334a45a8ff 1236 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
bogdanm 0:9b334a45a8ff 1237 ADC_HandleTypeDef tmphadcSlave;
bogdanm 0:9b334a45a8ff 1238
bogdanm 0:9b334a45a8ff 1239 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1240 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
bogdanm 0:9b334a45a8ff 1241 assert_param(IS_ADC_MODE(multimode->Mode));
bogdanm 0:9b334a45a8ff 1242
bogdanm 0:9b334a45a8ff 1243 /* Process locked */
bogdanm 0:9b334a45a8ff 1244 __HAL_LOCK(hadc);
bogdanm 0:9b334a45a8ff 1245
bogdanm 0:9b334a45a8ff 1246 /* Set a temporary handle of the ADC slave associated to the ADC master */
bogdanm 0:9b334a45a8ff 1247 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
bogdanm 0:9b334a45a8ff 1248
bogdanm 0:9b334a45a8ff 1249 /* Parameters update conditioned to ADC state: */
bogdanm 0:9b334a45a8ff 1250 /* Parameters that can be updated when ADC is disabled or enabled without */
bogdanm 0:9b334a45a8ff 1251 /* conversion on going on regular group: */
bogdanm 0:9b334a45a8ff 1252 /* - ADC master and ADC slave DMA configuration */
bogdanm 0:9b334a45a8ff 1253 /* Parameters that can be updated only when ADC is disabled: */
bogdanm 0:9b334a45a8ff 1254 /* - Multimode mode selection */
bogdanm 0:9b334a45a8ff 1255 /* To optimize code, all multimode settings can be set when both ADCs of */
bogdanm 0:9b334a45a8ff 1256 /* the common group are in state: disabled. */
bogdanm 0:9b334a45a8ff 1257 if ((ADC_IS_ENABLE(hadc) == RESET) &&
bogdanm 0:9b334a45a8ff 1258 (ADC_IS_ENABLE(&tmphadcSlave) == RESET) &&
bogdanm 0:9b334a45a8ff 1259 (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)) )
bogdanm 0:9b334a45a8ff 1260 {
bogdanm 0:9b334a45a8ff 1261 MODIFY_REG(hadc->Instance->CR1,
bogdanm 0:9b334a45a8ff 1262 ADC_CR1_DUALMOD ,
bogdanm 0:9b334a45a8ff 1263 multimode->Mode );
bogdanm 0:9b334a45a8ff 1264 }
bogdanm 0:9b334a45a8ff 1265 /* If one of the ADC sharing the same common group is enabled, no update */
bogdanm 0:9b334a45a8ff 1266 /* could be done on neither of the multimode structure parameters. */
bogdanm 0:9b334a45a8ff 1267 else
bogdanm 0:9b334a45a8ff 1268 {
bogdanm 0:9b334a45a8ff 1269 /* Update ADC state machine to error */
bogdanm 0:9b334a45a8ff 1270 hadc->State = HAL_ADC_STATE_ERROR;
bogdanm 0:9b334a45a8ff 1271
bogdanm 0:9b334a45a8ff 1272 tmp_hal_status = HAL_ERROR;
bogdanm 0:9b334a45a8ff 1273 }
bogdanm 0:9b334a45a8ff 1274
bogdanm 0:9b334a45a8ff 1275
bogdanm 0:9b334a45a8ff 1276 /* Process unlocked */
bogdanm 0:9b334a45a8ff 1277 __HAL_UNLOCK(hadc);
bogdanm 0:9b334a45a8ff 1278
bogdanm 0:9b334a45a8ff 1279 /* Return function status */
bogdanm 0:9b334a45a8ff 1280 return tmp_hal_status;
bogdanm 0:9b334a45a8ff 1281 }
bogdanm 0:9b334a45a8ff 1282 #endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
bogdanm 0:9b334a45a8ff 1283 /**
bogdanm 0:9b334a45a8ff 1284 * @}
bogdanm 0:9b334a45a8ff 1285 */
bogdanm 0:9b334a45a8ff 1286
bogdanm 0:9b334a45a8ff 1287 /**
bogdanm 0:9b334a45a8ff 1288 * @}
bogdanm 0:9b334a45a8ff 1289 */
bogdanm 0:9b334a45a8ff 1290
bogdanm 0:9b334a45a8ff 1291 #endif /* HAL_ADC_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1292 /**
bogdanm 0:9b334a45a8ff 1293 * @}
bogdanm 0:9b334a45a8ff 1294 */
bogdanm 0:9b334a45a8ff 1295
bogdanm 0:9b334a45a8ff 1296 /**
bogdanm 0:9b334a45a8ff 1297 * @}
bogdanm 0:9b334a45a8ff 1298 */
bogdanm 0:9b334a45a8ff 1299
bogdanm 0:9b334a45a8ff 1300 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/