mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 124:6a4a5b7d7324

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f100xb.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V4.0.0
bogdanm	0:9b334a45a8ff	6	* @date 16-December-2014
bogdanm	0:9b334a45a8ff	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
bogdanm	0:9b334a45a8ff	8	* This file contains all the peripheral register's definitions, bits
bogdanm	0:9b334a45a8ff	9	* definitions and memory mapping for STM32F1xx devices.
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* This file contains:
bogdanm	0:9b334a45a8ff	12	* - Data structures and the address mapping for all peripherals
bogdanm	0:9b334a45a8ff	13	* - Peripheral's registers declarations and bits definition
bogdanm	0:9b334a45a8ff	14	* - Macros to access peripherals registers hardware
bogdanm	0:9b334a45a8ff	15	*
bogdanm	0:9b334a45a8ff	16	******************************************************************************
bogdanm	0:9b334a45a8ff	17	* @attention
bogdanm	0:9b334a45a8ff	18	*
bogdanm	0:9b334a45a8ff	19	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	20	*
bogdanm	0:9b334a45a8ff	21	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	22	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	23	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	24	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	25	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	26	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	27	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	29	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	30	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	31	*
bogdanm	0:9b334a45a8ff	32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	42	*
bogdanm	0:9b334a45a8ff	43	******************************************************************************
bogdanm	0:9b334a45a8ff	44	*/
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47	/** @addtogroup CMSIS
bogdanm	0:9b334a45a8ff	48	* @{
bogdanm	0:9b334a45a8ff	49	*/
bogdanm	0:9b334a45a8ff	50
bogdanm	0:9b334a45a8ff	51	/** @addtogroup stm32f100xb
bogdanm	0:9b334a45a8ff	52	* @{
bogdanm	0:9b334a45a8ff	53	*/
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	#ifndef __STM32F100xB_H
bogdanm	0:9b334a45a8ff	56	#define __STM32F100xB_H
bogdanm	0:9b334a45a8ff	57
bogdanm	0:9b334a45a8ff	58	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	59	extern "C" {
bogdanm	0:9b334a45a8ff	60	#endif
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	/** @addtogroup Configuration_section_for_CMSIS
bogdanm	0:9b334a45a8ff	63	* @{
bogdanm	0:9b334a45a8ff	64	*/
bogdanm	0:9b334a45a8ff	65	/**
bogdanm	0:9b334a45a8ff	66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
bogdanm	0:9b334a45a8ff	67	*/
bogdanm	0:9b334a45a8ff	68	#define __MPU_PRESENT 0 /!< Other STM32 devices does not provide an MPU /
bogdanm	0:9b334a45a8ff	69	#define __CM3_REV 0x0200 /!< Core Revision r2p0 /
bogdanm	0:9b334a45a8ff	70	#define __NVIC_PRIO_BITS 4 /!< STM32 uses 4 Bits for the Priority Levels /
bogdanm	0:9b334a45a8ff	71	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	/**
bogdanm	0:9b334a45a8ff	74	* @}
bogdanm	0:9b334a45a8ff	75	*/
bogdanm	0:9b334a45a8ff	76
bogdanm	0:9b334a45a8ff	77	/** @addtogroup Peripheral_interrupt_number_definition
bogdanm	0:9b334a45a8ff	78	* @{
bogdanm	0:9b334a45a8ff	79	*/
bogdanm	0:9b334a45a8ff	80
bogdanm	0:9b334a45a8ff	81	/**
bogdanm	0:9b334a45a8ff	82	* @brief STM32F10x Interrupt Number Definition, according to the selected device
bogdanm	0:9b334a45a8ff	83	* in @ref Library_configuration_section
bogdanm	0:9b334a45a8ff	84	*/
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	/!< Interrupt Number Definition /
bogdanm	0:9b334a45a8ff	87	typedef enum
bogdanm	0:9b334a45a8ff	88	{
bogdanm	0:9b334a45a8ff	89	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
bogdanm	0:9b334a45a8ff	90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
bogdanm	0:9b334a45a8ff	91	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
bogdanm	0:9b334a45a8ff	92	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
bogdanm	0:9b334a45a8ff	93	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
bogdanm	0:9b334a45a8ff	94	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
bogdanm	0:9b334a45a8ff	95	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
bogdanm	0:9b334a45a8ff	96	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
bogdanm	0:9b334a45a8ff	97	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	/**** STM32 specific Interrupt Numbers *******************************************************/
bogdanm	0:9b334a45a8ff	100	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
bogdanm	0:9b334a45a8ff	101	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
bogdanm	0:9b334a45a8ff	102	TAMPER_IRQn = 2, /!< Tamper Interrupt /
bogdanm	0:9b334a45a8ff	103	RTC_IRQn = 3, /!< RTC global Interrupt /
bogdanm	0:9b334a45a8ff	104	FLASH_IRQn = 4, /!< FLASH global Interrupt /
bogdanm	0:9b334a45a8ff	105	RCC_IRQn = 5, /!< RCC global Interrupt /
bogdanm	0:9b334a45a8ff	106	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
bogdanm	0:9b334a45a8ff	107	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
bogdanm	0:9b334a45a8ff	108	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
bogdanm	0:9b334a45a8ff	109	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
bogdanm	0:9b334a45a8ff	110	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
bogdanm	0:9b334a45a8ff	111	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
bogdanm	0:9b334a45a8ff	112	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
bogdanm	0:9b334a45a8ff	113	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
bogdanm	0:9b334a45a8ff	114	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
bogdanm	0:9b334a45a8ff	115	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
bogdanm	0:9b334a45a8ff	116	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
bogdanm	0:9b334a45a8ff	117	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
bogdanm	0:9b334a45a8ff	118	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
bogdanm	0:9b334a45a8ff	119	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
bogdanm	0:9b334a45a8ff	120	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
bogdanm	0:9b334a45a8ff	121	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
bogdanm	0:9b334a45a8ff	122	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
bogdanm	0:9b334a45a8ff	123	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
bogdanm	0:9b334a45a8ff	124	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
bogdanm	0:9b334a45a8ff	125	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
bogdanm	0:9b334a45a8ff	126	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
bogdanm	0:9b334a45a8ff	127	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
bogdanm	0:9b334a45a8ff	128	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
bogdanm	0:9b334a45a8ff	129	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
bogdanm	0:9b334a45a8ff	130	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
bogdanm	0:9b334a45a8ff	131	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
bogdanm	0:9b334a45a8ff	132	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
bogdanm	0:9b334a45a8ff	133	USART1_IRQn = 37, /!< USART1 global Interrupt /
bogdanm	0:9b334a45a8ff	134	USART2_IRQn = 38, /!< USART2 global Interrupt /
bogdanm	0:9b334a45a8ff	135	USART3_IRQn = 39, /!< USART3 global Interrupt /
bogdanm	0:9b334a45a8ff	136	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
bogdanm	0:9b334a45a8ff	137	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
bogdanm	0:9b334a45a8ff	138	CEC_IRQn = 42, /!< HDMI-CEC Interrupt /
bogdanm	0:9b334a45a8ff	139	TIM6_DAC_IRQn = 54, /!< TIM6 and DAC underrun Interrupt /
bogdanm	0:9b334a45a8ff	140	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
bogdanm	0:9b334a45a8ff	141	} IRQn_Type;
bogdanm	0:9b334a45a8ff	142
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144	/**
bogdanm	0:9b334a45a8ff	145	* @}
bogdanm	0:9b334a45a8ff	146	*/
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148	#include "core_cm3.h"
bogdanm	0:9b334a45a8ff	149	#include "system_stm32f1xx.h"
bogdanm	0:9b334a45a8ff	150	#include <stdint.h>
bogdanm	0:9b334a45a8ff	151
bogdanm	0:9b334a45a8ff	152	/** @addtogroup Peripheral_registers_structures
bogdanm	0:9b334a45a8ff	153	* @{
bogdanm	0:9b334a45a8ff	154	*/
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	/**
bogdanm	0:9b334a45a8ff	157	* @brief Analog to Digital Converter
bogdanm	0:9b334a45a8ff	158	*/
bogdanm	0:9b334a45a8ff	159
bogdanm	0:9b334a45a8ff	160	typedef struct
bogdanm	0:9b334a45a8ff	161	{
bogdanm	0:9b334a45a8ff	162	__IO uint32_t SR;
bogdanm	0:9b334a45a8ff	163	__IO uint32_t CR1;
bogdanm	0:9b334a45a8ff	164	__IO uint32_t CR2;
bogdanm	0:9b334a45a8ff	165	__IO uint32_t SMPR1;
bogdanm	0:9b334a45a8ff	166	__IO uint32_t SMPR2;
bogdanm	0:9b334a45a8ff	167	__IO uint32_t JOFR1;
bogdanm	0:9b334a45a8ff	168	__IO uint32_t JOFR2;
bogdanm	0:9b334a45a8ff	169	__IO uint32_t JOFR3;
bogdanm	0:9b334a45a8ff	170	__IO uint32_t JOFR4;
bogdanm	0:9b334a45a8ff	171	__IO uint32_t HTR;
bogdanm	0:9b334a45a8ff	172	__IO uint32_t LTR;
bogdanm	0:9b334a45a8ff	173	__IO uint32_t SQR1;
bogdanm	0:9b334a45a8ff	174	__IO uint32_t SQR2;
bogdanm	0:9b334a45a8ff	175	__IO uint32_t SQR3;
bogdanm	0:9b334a45a8ff	176	__IO uint32_t JSQR;
bogdanm	0:9b334a45a8ff	177	__IO uint32_t JDR1;
bogdanm	0:9b334a45a8ff	178	__IO uint32_t JDR2;
bogdanm	0:9b334a45a8ff	179	__IO uint32_t JDR3;
bogdanm	0:9b334a45a8ff	180	__IO uint32_t JDR4;
bogdanm	0:9b334a45a8ff	181	__IO uint32_t DR;
bogdanm	0:9b334a45a8ff	182	} ADC_TypeDef;
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	/**
bogdanm	0:9b334a45a8ff	185	* @brief Backup Registers
bogdanm	0:9b334a45a8ff	186	*/
bogdanm	0:9b334a45a8ff	187
bogdanm	0:9b334a45a8ff	188	typedef struct
bogdanm	0:9b334a45a8ff	189	{
bogdanm	0:9b334a45a8ff	190	uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	191	__IO uint32_t DR1;
bogdanm	0:9b334a45a8ff	192	__IO uint32_t DR2;
bogdanm	0:9b334a45a8ff	193	__IO uint32_t DR3;
bogdanm	0:9b334a45a8ff	194	__IO uint32_t DR4;
bogdanm	0:9b334a45a8ff	195	__IO uint32_t DR5;
bogdanm	0:9b334a45a8ff	196	__IO uint32_t DR6;
bogdanm	0:9b334a45a8ff	197	__IO uint32_t DR7;
bogdanm	0:9b334a45a8ff	198	__IO uint32_t DR8;
bogdanm	0:9b334a45a8ff	199	__IO uint32_t DR9;
bogdanm	0:9b334a45a8ff	200	__IO uint32_t DR10;
bogdanm	0:9b334a45a8ff	201	__IO uint32_t RTCCR;
bogdanm	0:9b334a45a8ff	202	__IO uint32_t CR;
bogdanm	0:9b334a45a8ff	203	__IO uint32_t CSR;
bogdanm	0:9b334a45a8ff	204	} BKP_TypeDef;
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206
bogdanm	0:9b334a45a8ff	207	/**
bogdanm	0:9b334a45a8ff	208	* @brief Consumer Electronics Control (CEC)
bogdanm	0:9b334a45a8ff	209	*/
bogdanm	0:9b334a45a8ff	210	typedef struct
bogdanm	0:9b334a45a8ff	211	{
bogdanm	0:9b334a45a8ff	212	__IO uint32_t CFGR;
bogdanm	0:9b334a45a8ff	213	__IO uint32_t OAR;
bogdanm	0:9b334a45a8ff	214	__IO uint32_t PRES;
bogdanm	0:9b334a45a8ff	215	__IO uint32_t ESR;
bogdanm	0:9b334a45a8ff	216	__IO uint32_t CSR;
bogdanm	0:9b334a45a8ff	217	__IO uint32_t TXD;
bogdanm	0:9b334a45a8ff	218	__IO uint32_t RXD;
bogdanm	0:9b334a45a8ff	219	} CEC_TypeDef;
bogdanm	0:9b334a45a8ff	220
bogdanm	0:9b334a45a8ff	221	/**
bogdanm	0:9b334a45a8ff	222	* @brief CRC calculation unit
bogdanm	0:9b334a45a8ff	223	*/
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	typedef struct
bogdanm	0:9b334a45a8ff	226	{
bogdanm	0:9b334a45a8ff	227	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	228	__IO uint32_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	229	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	230	} CRC_TypeDef;
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	/**
bogdanm	0:9b334a45a8ff	233	* @brief Digital to Analog Converter
bogdanm	0:9b334a45a8ff	234	*/
bogdanm	0:9b334a45a8ff	235
bogdanm	0:9b334a45a8ff	236	typedef struct
bogdanm	0:9b334a45a8ff	237	{
bogdanm	0:9b334a45a8ff	238	__IO uint32_t CR;
bogdanm	0:9b334a45a8ff	239	__IO uint32_t SWTRIGR;
bogdanm	0:9b334a45a8ff	240	__IO uint32_t DHR12R1;
bogdanm	0:9b334a45a8ff	241	__IO uint32_t DHR12L1;
bogdanm	0:9b334a45a8ff	242	__IO uint32_t DHR8R1;
bogdanm	0:9b334a45a8ff	243	__IO uint32_t DHR12R2;
bogdanm	0:9b334a45a8ff	244	__IO uint32_t DHR12L2;
bogdanm	0:9b334a45a8ff	245	__IO uint32_t DHR8R2;
bogdanm	0:9b334a45a8ff	246	__IO uint32_t DHR12RD;
bogdanm	0:9b334a45a8ff	247	__IO uint32_t DHR12LD;
bogdanm	0:9b334a45a8ff	248	__IO uint32_t DHR8RD;
bogdanm	0:9b334a45a8ff	249	__IO uint32_t DOR1;
bogdanm	0:9b334a45a8ff	250	__IO uint32_t DOR2;
bogdanm	0:9b334a45a8ff	251	__IO uint32_t SR;
bogdanm	0:9b334a45a8ff	252	} DAC_TypeDef;
bogdanm	0:9b334a45a8ff	253
bogdanm	0:9b334a45a8ff	254	/**
bogdanm	0:9b334a45a8ff	255	* @brief Debug MCU
bogdanm	0:9b334a45a8ff	256	*/
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	typedef struct
bogdanm	0:9b334a45a8ff	259	{
bogdanm	0:9b334a45a8ff	260	__IO uint32_t IDCODE;
bogdanm	0:9b334a45a8ff	261	__IO uint32_t CR;
bogdanm	0:9b334a45a8ff	262	}DBGMCU_TypeDef;
bogdanm	0:9b334a45a8ff	263
bogdanm	0:9b334a45a8ff	264	/**
bogdanm	0:9b334a45a8ff	265	* @brief DMA Controller
bogdanm	0:9b334a45a8ff	266	*/
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	typedef struct
bogdanm	0:9b334a45a8ff	269	{
bogdanm	0:9b334a45a8ff	270	__IO uint32_t CCR;
bogdanm	0:9b334a45a8ff	271	__IO uint32_t CNDTR;
bogdanm	0:9b334a45a8ff	272	__IO uint32_t CPAR;
bogdanm	0:9b334a45a8ff	273	__IO uint32_t CMAR;
bogdanm	0:9b334a45a8ff	274	} DMA_Channel_TypeDef;
bogdanm	0:9b334a45a8ff	275
bogdanm	0:9b334a45a8ff	276	typedef struct
bogdanm	0:9b334a45a8ff	277	{
bogdanm	0:9b334a45a8ff	278	__IO uint32_t ISR;
bogdanm	0:9b334a45a8ff	279	__IO uint32_t IFCR;
bogdanm	0:9b334a45a8ff	280	} DMA_TypeDef;
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/**
bogdanm	0:9b334a45a8ff	285	* @brief External Interrupt/Event Controller
bogdanm	0:9b334a45a8ff	286	*/
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	typedef struct
bogdanm	0:9b334a45a8ff	289	{
bogdanm	0:9b334a45a8ff	290	__IO uint32_t IMR;
bogdanm	0:9b334a45a8ff	291	__IO uint32_t EMR;
bogdanm	0:9b334a45a8ff	292	__IO uint32_t RTSR;
bogdanm	0:9b334a45a8ff	293	__IO uint32_t FTSR;
bogdanm	0:9b334a45a8ff	294	__IO uint32_t SWIER;
bogdanm	0:9b334a45a8ff	295	__IO uint32_t PR;
bogdanm	0:9b334a45a8ff	296	} EXTI_TypeDef;
bogdanm	0:9b334a45a8ff	297
bogdanm	0:9b334a45a8ff	298	/**
bogdanm	0:9b334a45a8ff	299	* @brief FLASH Registers
bogdanm	0:9b334a45a8ff	300	*/
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	typedef struct
bogdanm	0:9b334a45a8ff	303	{
bogdanm	0:9b334a45a8ff	304	__IO uint32_t ACR;
bogdanm	0:9b334a45a8ff	305	__IO uint32_t KEYR;
bogdanm	0:9b334a45a8ff	306	__IO uint32_t OPTKEYR;
bogdanm	0:9b334a45a8ff	307	__IO uint32_t SR;
bogdanm	0:9b334a45a8ff	308	__IO uint32_t CR;
bogdanm	0:9b334a45a8ff	309	__IO uint32_t AR;
bogdanm	0:9b334a45a8ff	310	__IO uint32_t RESERVED;
bogdanm	0:9b334a45a8ff	311	__IO uint32_t OBR;
bogdanm	0:9b334a45a8ff	312	__IO uint32_t WRPR;
bogdanm	0:9b334a45a8ff	313	} FLASH_TypeDef;
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/**
bogdanm	0:9b334a45a8ff	316	* @brief Option Bytes Registers
bogdanm	0:9b334a45a8ff	317	*/
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	typedef struct
bogdanm	0:9b334a45a8ff	320	{
bogdanm	0:9b334a45a8ff	321	__IO uint16_t RDP;
bogdanm	0:9b334a45a8ff	322	__IO uint16_t USER;
bogdanm	0:9b334a45a8ff	323	__IO uint16_t Data0;
bogdanm	0:9b334a45a8ff	324	__IO uint16_t Data1;
bogdanm	0:9b334a45a8ff	325	__IO uint16_t WRP0;
bogdanm	0:9b334a45a8ff	326	__IO uint16_t WRP1;
bogdanm	0:9b334a45a8ff	327	__IO uint16_t WRP2;
bogdanm	0:9b334a45a8ff	328	__IO uint16_t WRP3;
bogdanm	0:9b334a45a8ff	329	} OB_TypeDef;
bogdanm	0:9b334a45a8ff	330
bogdanm	0:9b334a45a8ff	331	/**
bogdanm	0:9b334a45a8ff	332	* @brief General Purpose I/O
bogdanm	0:9b334a45a8ff	333	*/
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	typedef struct
bogdanm	0:9b334a45a8ff	336	{
bogdanm	0:9b334a45a8ff	337	__IO uint32_t CRL;
bogdanm	0:9b334a45a8ff	338	__IO uint32_t CRH;
bogdanm	0:9b334a45a8ff	339	__IO uint32_t IDR;
bogdanm	0:9b334a45a8ff	340	__IO uint32_t ODR;
bogdanm	0:9b334a45a8ff	341	__IO uint32_t BSRR;
bogdanm	0:9b334a45a8ff	342	__IO uint32_t BRR;
bogdanm	0:9b334a45a8ff	343	__IO uint32_t LCKR;
bogdanm	0:9b334a45a8ff	344	} GPIO_TypeDef;
bogdanm	0:9b334a45a8ff	345
bogdanm	0:9b334a45a8ff	346	/**
bogdanm	0:9b334a45a8ff	347	* @brief Alternate Function I/O
bogdanm	0:9b334a45a8ff	348	*/
bogdanm	0:9b334a45a8ff	349
bogdanm	0:9b334a45a8ff	350	typedef struct
bogdanm	0:9b334a45a8ff	351	{
bogdanm	0:9b334a45a8ff	352	__IO uint32_t EVCR;
bogdanm	0:9b334a45a8ff	353	__IO uint32_t MAPR;
bogdanm	0:9b334a45a8ff	354	__IO uint32_t EXTICR[4];
bogdanm	0:9b334a45a8ff	355	uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	356	__IO uint32_t MAPR2;
bogdanm	0:9b334a45a8ff	357	} AFIO_TypeDef;
bogdanm	0:9b334a45a8ff	358	/**
bogdanm	0:9b334a45a8ff	359	* @brief Inter Integrated Circuit Interface
bogdanm	0:9b334a45a8ff	360	*/
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	typedef struct
bogdanm	0:9b334a45a8ff	363	{
bogdanm	0:9b334a45a8ff	364	__IO uint32_t CR1;
bogdanm	0:9b334a45a8ff	365	__IO uint32_t CR2;
bogdanm	0:9b334a45a8ff	366	__IO uint32_t OAR1;
bogdanm	0:9b334a45a8ff	367	__IO uint32_t OAR2;
bogdanm	0:9b334a45a8ff	368	__IO uint32_t DR;
bogdanm	0:9b334a45a8ff	369	__IO uint32_t SR1;
bogdanm	0:9b334a45a8ff	370	__IO uint32_t SR2;
bogdanm	0:9b334a45a8ff	371	__IO uint32_t CCR;
bogdanm	0:9b334a45a8ff	372	__IO uint32_t TRISE;
bogdanm	0:9b334a45a8ff	373	} I2C_TypeDef;
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	/**
bogdanm	0:9b334a45a8ff	376	* @brief Independent WATCHDOG
bogdanm	0:9b334a45a8ff	377	*/
bogdanm	0:9b334a45a8ff	378
bogdanm	0:9b334a45a8ff	379	typedef struct
bogdanm	0:9b334a45a8ff	380	{
bogdanm	0:9b334a45a8ff	381	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	382	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	383	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	384	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	385	} IWDG_TypeDef;
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	/**
bogdanm	0:9b334a45a8ff	388	* @brief Power Control
bogdanm	0:9b334a45a8ff	389	*/
bogdanm	0:9b334a45a8ff	390
bogdanm	0:9b334a45a8ff	391	typedef struct
bogdanm	0:9b334a45a8ff	392	{
bogdanm	0:9b334a45a8ff	393	__IO uint32_t CR;
bogdanm	0:9b334a45a8ff	394	__IO uint32_t CSR;
bogdanm	0:9b334a45a8ff	395	} PWR_TypeDef;
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397	/**
bogdanm	0:9b334a45a8ff	398	* @brief Reset and Clock Control
bogdanm	0:9b334a45a8ff	399	*/
bogdanm	0:9b334a45a8ff	400
bogdanm	0:9b334a45a8ff	401	typedef struct
bogdanm	0:9b334a45a8ff	402	{
bogdanm	0:9b334a45a8ff	403	__IO uint32_t CR;
bogdanm	0:9b334a45a8ff	404	__IO uint32_t CFGR;
bogdanm	0:9b334a45a8ff	405	__IO uint32_t CIR;
bogdanm	0:9b334a45a8ff	406	__IO uint32_t APB2RSTR;
bogdanm	0:9b334a45a8ff	407	__IO uint32_t APB1RSTR;
bogdanm	0:9b334a45a8ff	408	__IO uint32_t AHBENR;
bogdanm	0:9b334a45a8ff	409	__IO uint32_t APB2ENR;
bogdanm	0:9b334a45a8ff	410	__IO uint32_t APB1ENR;
bogdanm	0:9b334a45a8ff	411	__IO uint32_t BDCR;
bogdanm	0:9b334a45a8ff	412	__IO uint32_t CSR;
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	416	__IO uint32_t CFGR2;
bogdanm	0:9b334a45a8ff	417	} RCC_TypeDef;
bogdanm	0:9b334a45a8ff	418
bogdanm	0:9b334a45a8ff	419	/**
bogdanm	0:9b334a45a8ff	420	* @brief Real-Time Clock
bogdanm	0:9b334a45a8ff	421	*/
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	typedef struct
bogdanm	0:9b334a45a8ff	424	{
bogdanm	0:9b334a45a8ff	425	__IO uint32_t CRH;
bogdanm	0:9b334a45a8ff	426	__IO uint32_t CRL;
bogdanm	0:9b334a45a8ff	427	__IO uint32_t PRLH;
bogdanm	0:9b334a45a8ff	428	__IO uint32_t PRLL;
bogdanm	0:9b334a45a8ff	429	__IO uint32_t DIVH;
bogdanm	0:9b334a45a8ff	430	__IO uint32_t DIVL;
bogdanm	0:9b334a45a8ff	431	__IO uint32_t CNTH;
bogdanm	0:9b334a45a8ff	432	__IO uint32_t CNTL;
bogdanm	0:9b334a45a8ff	433	__IO uint32_t ALRH;
bogdanm	0:9b334a45a8ff	434	__IO uint32_t ALRL;
bogdanm	0:9b334a45a8ff	435	} RTC_TypeDef;
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437	/**
bogdanm	0:9b334a45a8ff	438	* @brief SD host Interface
bogdanm	0:9b334a45a8ff	439	*/
bogdanm	0:9b334a45a8ff	440
bogdanm	0:9b334a45a8ff	441	typedef struct
bogdanm	0:9b334a45a8ff	442	{
bogdanm	0:9b334a45a8ff	443	__IO uint32_t POWER;
bogdanm	0:9b334a45a8ff	444	__IO uint32_t CLKCR;
bogdanm	0:9b334a45a8ff	445	__IO uint32_t ARG;
bogdanm	0:9b334a45a8ff	446	__IO uint32_t CMD;
bogdanm	0:9b334a45a8ff	447	__I uint32_t RESPCMD;
bogdanm	0:9b334a45a8ff	448	__I uint32_t RESP1;
bogdanm	0:9b334a45a8ff	449	__I uint32_t RESP2;
bogdanm	0:9b334a45a8ff	450	__I uint32_t RESP3;
bogdanm	0:9b334a45a8ff	451	__I uint32_t RESP4;
bogdanm	0:9b334a45a8ff	452	__IO uint32_t DTIMER;
bogdanm	0:9b334a45a8ff	453	__IO uint32_t DLEN;
bogdanm	0:9b334a45a8ff	454	__IO uint32_t DCTRL;
bogdanm	0:9b334a45a8ff	455	__I uint32_t DCOUNT;
bogdanm	0:9b334a45a8ff	456	__I uint32_t STA;
bogdanm	0:9b334a45a8ff	457	__IO uint32_t ICR;
bogdanm	0:9b334a45a8ff	458	__IO uint32_t MASK;
bogdanm	0:9b334a45a8ff	459	uint32_t RESERVED0[2];
bogdanm	0:9b334a45a8ff	460	__I uint32_t FIFOCNT;
bogdanm	0:9b334a45a8ff	461	uint32_t RESERVED1[13];
bogdanm	0:9b334a45a8ff	462	__IO uint32_t FIFO;
bogdanm	0:9b334a45a8ff	463	} SDIO_TypeDef;
bogdanm	0:9b334a45a8ff	464
bogdanm	0:9b334a45a8ff	465	/**
bogdanm	0:9b334a45a8ff	466	* @brief Serial Peripheral Interface
bogdanm	0:9b334a45a8ff	467	*/
bogdanm	0:9b334a45a8ff	468
bogdanm	0:9b334a45a8ff	469	typedef struct
bogdanm	0:9b334a45a8ff	470	{
bogdanm	0:9b334a45a8ff	471	__IO uint32_t CR1;
bogdanm	0:9b334a45a8ff	472	__IO uint32_t CR2;
bogdanm	0:9b334a45a8ff	473	__IO uint32_t SR;
bogdanm	0:9b334a45a8ff	474	__IO uint32_t DR;
bogdanm	0:9b334a45a8ff	475	__IO uint32_t CRCPR;
bogdanm	0:9b334a45a8ff	476	__IO uint32_t RXCRCR;
bogdanm	0:9b334a45a8ff	477	__IO uint32_t TXCRCR;
bogdanm	0:9b334a45a8ff	478	} SPI_TypeDef;
bogdanm	0:9b334a45a8ff	479
bogdanm	0:9b334a45a8ff	480	/**
bogdanm	0:9b334a45a8ff	481	* @brief TIM Timers
bogdanm	0:9b334a45a8ff	482	*/
bogdanm	0:9b334a45a8ff	483	typedef struct
bogdanm	0:9b334a45a8ff	484	{
bogdanm	0:9b334a45a8ff	485	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	486	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	487	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	488	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	489	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	490	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	491	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	492	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	493	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	494	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	495	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	496	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	497	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	498	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	499	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	500	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	501	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	502	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	503	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	504	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	505	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	506	}TIM_TypeDef;
bogdanm	0:9b334a45a8ff	507
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509	/**
bogdanm	0:9b334a45a8ff	510	* @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm	0:9b334a45a8ff	511	*/
bogdanm	0:9b334a45a8ff	512
bogdanm	0:9b334a45a8ff	513	typedef struct
bogdanm	0:9b334a45a8ff	514	{
bogdanm	0:9b334a45a8ff	515	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	516	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	517	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	518	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	519	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	520	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	521	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	522	} USART_TypeDef;
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	/**
bogdanm	0:9b334a45a8ff	527	* @brief Window WATCHDOG
bogdanm	0:9b334a45a8ff	528	*/
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	typedef struct
bogdanm	0:9b334a45a8ff	531	{
bogdanm	0:9b334a45a8ff	532	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	533	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	534	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	535	} WWDG_TypeDef;
bogdanm	0:9b334a45a8ff	536
bogdanm	0:9b334a45a8ff	537	/**
bogdanm	0:9b334a45a8ff	538	* @}
bogdanm	0:9b334a45a8ff	539	*/
bogdanm	0:9b334a45a8ff	540
bogdanm	0:9b334a45a8ff	541	/** @addtogroup Peripheral_memory_map
bogdanm	0:9b334a45a8ff	542	* @{
bogdanm	0:9b334a45a8ff	543	*/
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
bogdanm	0:9b334a45a8ff	547	#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /!< FLASH END address of bank1 /
bogdanm	0:9b334a45a8ff	548	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
bogdanm	0:9b334a45a8ff	549	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
bogdanm	0:9b334a45a8ff	552	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554
bogdanm	0:9b334a45a8ff	555	/!< Peripheral memory map /
bogdanm	0:9b334a45a8ff	556	#define APB1PERIPH_BASE PERIPH_BASE
bogdanm	0:9b334a45a8ff	557	#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
bogdanm	0:9b334a45a8ff	558	#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
bogdanm	0:9b334a45a8ff	561	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
bogdanm	0:9b334a45a8ff	562	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
bogdanm	0:9b334a45a8ff	563	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
bogdanm	0:9b334a45a8ff	564	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
bogdanm	0:9b334a45a8ff	565	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
bogdanm	0:9b334a45a8ff	566	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
bogdanm	0:9b334a45a8ff	567	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
bogdanm	0:9b334a45a8ff	568	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
bogdanm	0:9b334a45a8ff	569	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
bogdanm	0:9b334a45a8ff	570	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
bogdanm	0:9b334a45a8ff	571	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
bogdanm	0:9b334a45a8ff	572	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
bogdanm	0:9b334a45a8ff	573	#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
bogdanm	0:9b334a45a8ff	574	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
bogdanm	0:9b334a45a8ff	575	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
bogdanm	0:9b334a45a8ff	576	#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
bogdanm	0:9b334a45a8ff	577	#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
bogdanm	0:9b334a45a8ff	578	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
bogdanm	0:9b334a45a8ff	579	#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
bogdanm	0:9b334a45a8ff	580	#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
bogdanm	0:9b334a45a8ff	581	#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
bogdanm	0:9b334a45a8ff	582	#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
bogdanm	0:9b334a45a8ff	583	#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
bogdanm	0:9b334a45a8ff	584	#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
bogdanm	0:9b334a45a8ff	585	#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
bogdanm	0:9b334a45a8ff	586	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
bogdanm	0:9b334a45a8ff	587	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
bogdanm	0:9b334a45a8ff	588	#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
bogdanm	0:9b334a45a8ff	589	#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
bogdanm	0:9b334a45a8ff	590	#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	#define SDIO_BASE (PERIPH_BASE + 0x18000)
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594	#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
bogdanm	0:9b334a45a8ff	595	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
bogdanm	0:9b334a45a8ff	596	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
bogdanm	0:9b334a45a8ff	597	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
bogdanm	0:9b334a45a8ff	598	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
bogdanm	0:9b334a45a8ff	599	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
bogdanm	0:9b334a45a8ff	600	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
bogdanm	0:9b334a45a8ff	601	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
bogdanm	0:9b334a45a8ff	602	#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
bogdanm	0:9b334a45a8ff	603	#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
bogdanm	0:9b334a45a8ff	604
bogdanm	0:9b334a45a8ff	605	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /!< Flash registers base address /
bogdanm	0:9b334a45a8ff	606	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
bogdanm	0:9b334a45a8ff	607
bogdanm	0:9b334a45a8ff	608
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
bogdanm	0:9b334a45a8ff	611
bogdanm	0:9b334a45a8ff	612
bogdanm	0:9b334a45a8ff	613
bogdanm	0:9b334a45a8ff	614	/**
bogdanm	0:9b334a45a8ff	615	* @}
bogdanm	0:9b334a45a8ff	616	*/
bogdanm	0:9b334a45a8ff	617
bogdanm	0:9b334a45a8ff	618	/** @addtogroup Peripheral_declaration
bogdanm	0:9b334a45a8ff	619	* @{
bogdanm	0:9b334a45a8ff	620	*/
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm	0:9b334a45a8ff	623	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm	0:9b334a45a8ff	624	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
bogdanm	0:9b334a45a8ff	625	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm	0:9b334a45a8ff	626	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm	0:9b334a45a8ff	627	#define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm	0:9b334a45a8ff	628	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm	0:9b334a45a8ff	629	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm	0:9b334a45a8ff	630	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm	0:9b334a45a8ff	631	#define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm	0:9b334a45a8ff	632	#define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm	0:9b334a45a8ff	633	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm	0:9b334a45a8ff	634	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm	0:9b334a45a8ff	635	#define BKP ((BKP_TypeDef *) BKP_BASE)
bogdanm	0:9b334a45a8ff	636	#define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm	0:9b334a45a8ff	637	#define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm	0:9b334a45a8ff	638	#define CEC ((CEC_TypeDef *) CEC_BASE)
bogdanm	0:9b334a45a8ff	639	#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
bogdanm	0:9b334a45a8ff	640	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm	0:9b334a45a8ff	641	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm	0:9b334a45a8ff	642	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm	0:9b334a45a8ff	643	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm	0:9b334a45a8ff	644	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm	0:9b334a45a8ff	645	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm	0:9b334a45a8ff	646	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm	0:9b334a45a8ff	647	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm	0:9b334a45a8ff	648	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm	0:9b334a45a8ff	649	#define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm	0:9b334a45a8ff	650	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
bogdanm	0:9b334a45a8ff	651	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
bogdanm	0:9b334a45a8ff	652	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
bogdanm	0:9b334a45a8ff	653	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
bogdanm	0:9b334a45a8ff	654	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm	0:9b334a45a8ff	655	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm	0:9b334a45a8ff	656	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm	0:9b334a45a8ff	657	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm	0:9b334a45a8ff	658	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm	0:9b334a45a8ff	659	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm	0:9b334a45a8ff	660	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
bogdanm	0:9b334a45a8ff	661	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
bogdanm	0:9b334a45a8ff	662	#define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm	0:9b334a45a8ff	663	#define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm	0:9b334a45a8ff	664	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm	0:9b334a45a8ff	665	#define OB ((OB_TypeDef *) OB_BASE)
bogdanm	0:9b334a45a8ff	666	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668
bogdanm	0:9b334a45a8ff	669	/**
bogdanm	0:9b334a45a8ff	670	* @}
bogdanm	0:9b334a45a8ff	671	*/
bogdanm	0:9b334a45a8ff	672
bogdanm	0:9b334a45a8ff	673	/** @addtogroup Exported_constants
bogdanm	0:9b334a45a8ff	674	* @{
bogdanm	0:9b334a45a8ff	675	*/
bogdanm	0:9b334a45a8ff	676
bogdanm	0:9b334a45a8ff	677	/** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm	0:9b334a45a8ff	678	* @{
bogdanm	0:9b334a45a8ff	679	*/
bogdanm	0:9b334a45a8ff	680
bogdanm	0:9b334a45a8ff	681	/******************************************************************************/
bogdanm	0:9b334a45a8ff	682	/* Peripheral Registers_Bits_Definition */
bogdanm	0:9b334a45a8ff	683	/******************************************************************************/
bogdanm	0:9b334a45a8ff	684
bogdanm	0:9b334a45a8ff	685	/******************************************************************************/
bogdanm	0:9b334a45a8ff	686	/* */
bogdanm	0:9b334a45a8ff	687	/* CRC calculation unit (CRC) */
bogdanm	0:9b334a45a8ff	688	/* */
bogdanm	0:9b334a45a8ff	689	/******************************************************************************/
bogdanm	0:9b334a45a8ff	690
bogdanm	0:9b334a45a8ff	691	/***************** Bit definition for CRC_DR register *******************/
bogdanm	0:9b334a45a8ff	692	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	/***************** Bit definition for CRC_IDR register ******************/
bogdanm	0:9b334a45a8ff	695	#define CRC_IDR_IDR ((uint32_t)0x000000FF) /!< General-purpose 8-bit data register bits /
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	/****************** Bit definition for CRC_CR register ******************/
bogdanm	0:9b334a45a8ff	698	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET bit /
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/******************************************************************************/
bogdanm	0:9b334a45a8ff	701	/* */
bogdanm	0:9b334a45a8ff	702	/* Power Control */
bogdanm	0:9b334a45a8ff	703	/* */
bogdanm	0:9b334a45a8ff	704	/******************************************************************************/
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706	/****************** Bit definition for PWR_CR register ******************/
bogdanm	0:9b334a45a8ff	707	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-Power Deepsleep /
bogdanm	0:9b334a45a8ff	708	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
bogdanm	0:9b334a45a8ff	709	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
bogdanm	0:9b334a45a8ff	710	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
bogdanm	0:9b334a45a8ff	711	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
bogdanm	0:9b334a45a8ff	712
bogdanm	0:9b334a45a8ff	713	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
bogdanm	0:9b334a45a8ff	714	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	715	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	716	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	717
bogdanm	0:9b334a45a8ff	718	/!< PVD level configuration /
bogdanm	0:9b334a45a8ff	719	#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /!< PVD level 2.2V /
bogdanm	0:9b334a45a8ff	720	#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /!< PVD level 2.3V /
bogdanm	0:9b334a45a8ff	721	#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /!< PVD level 2.4V /
bogdanm	0:9b334a45a8ff	722	#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /!< PVD level 2.5V /
bogdanm	0:9b334a45a8ff	723	#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /!< PVD level 2.6V /
bogdanm	0:9b334a45a8ff	724	#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /!< PVD level 2.7V /
bogdanm	0:9b334a45a8ff	725	#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /!< PVD level 2.8V /
bogdanm	0:9b334a45a8ff	726	#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /!< PVD level 2.9V /
bogdanm	0:9b334a45a8ff	727
bogdanm	0:9b334a45a8ff	728	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
bogdanm	0:9b334a45a8ff	729
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731	/***************** Bit definition for PWR_CSR register ******************/
bogdanm	0:9b334a45a8ff	732	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
bogdanm	0:9b334a45a8ff	733	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
bogdanm	0:9b334a45a8ff	734	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
bogdanm	0:9b334a45a8ff	735	#define PWR_CSR_EWUP ((uint32_t)0x00000100) /!< Enable WKUP pin /
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737	/******************************************************************************/
bogdanm	0:9b334a45a8ff	738	/* */
bogdanm	0:9b334a45a8ff	739	/* Backup registers */
bogdanm	0:9b334a45a8ff	740	/* */
bogdanm	0:9b334a45a8ff	741	/******************************************************************************/
bogdanm	0:9b334a45a8ff	742
bogdanm	0:9b334a45a8ff	743	/***************** Bit definition for BKP_DR1 register ******************/
bogdanm	0:9b334a45a8ff	744	#define BKP_DR1_D ((uint32_t)0x0000FFFF) /!< Backup data /
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	/***************** Bit definition for BKP_DR2 register ******************/
bogdanm	0:9b334a45a8ff	747	#define BKP_DR2_D ((uint32_t)0x0000FFFF) /!< Backup data /
bogdanm	0:9b334a45a8ff	748
bogdanm	0:9b334a45a8ff	749	/***************** Bit definition for BKP_DR3 register ******************/
bogdanm	0:9b334a45a8ff	750	#define BKP_DR3_D ((uint32_t)0x0000FFFF) /!< Backup data /
bogdanm	0:9b334a45a8ff	751
bogdanm	0:9b334a45a8ff	752	/***************** Bit definition for BKP_DR4 register ******************/
bogdanm	0:9b334a45a8ff	753	#define BKP_DR4_D ((uint32_t)0x0000FFFF) /!< Backup data /
bogdanm	0:9b334a45a8ff	754
bogdanm	0:9b334a45a8ff	755	/***************** Bit definition for BKP_DR5 register ******************/
bogdanm	0:9b334a45a8ff	756	#define BKP_DR5_D ((uint32_t)0x0000FFFF) /!< Backup data /
bogdanm	0:9b334a45a8ff	757
bogdanm	0:9b334a45a8ff	758	/***************** Bit definition for BKP_DR6 register ******************/
bogdanm	0:9b334a45a8ff	759	#define BKP_DR6_D ((uint32_t)0x0000FFFF) /!< Backup data /
bogdanm	0:9b334a45a8ff	760
bogdanm	0:9b334a45a8ff	761	/***************** Bit definition for BKP_DR7 register ******************/
bogdanm	0:9b334a45a8ff	762	#define BKP_DR7_D ((uint32_t)0x0000FFFF) /!< Backup data /
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764	/***************** Bit definition for BKP_DR8 register ******************/
bogdanm	0:9b334a45a8ff	765	#define BKP_DR8_D ((uint32_t)0x0000FFFF) /!< Backup data /
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	/***************** Bit definition for BKP_DR9 register ******************/
bogdanm	0:9b334a45a8ff	768	#define BKP_DR9_D ((uint32_t)0x0000FFFF) /!< Backup data /
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	/***************** Bit definition for BKP_DR10 register *****************/
bogdanm	0:9b334a45a8ff	771	#define BKP_DR10_D ((uint32_t)0x0000FFFF) /!< Backup data /
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	#define RTC_BKP_NUMBER 10
bogdanm	0:9b334a45a8ff	774
bogdanm	0:9b334a45a8ff	775	/**************** Bit definition for BKP_RTCCR register *****************/
bogdanm	0:9b334a45a8ff	776	#define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /!< Calibration value /
bogdanm	0:9b334a45a8ff	777	#define BKP_RTCCR_CCO ((uint32_t)0x00000080) /!< Calibration Clock Output /
bogdanm	0:9b334a45a8ff	778	#define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /!< Alarm or Second Output Enable /
bogdanm	0:9b334a45a8ff	779	#define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /!< Alarm or Second Output Selection /
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	/****************** Bit definition for BKP_CR register ******************/
bogdanm	0:9b334a45a8ff	782	#define BKP_CR_TPE ((uint32_t)0x00000001) /!< TAMPER pin enable /
bogdanm	0:9b334a45a8ff	783	#define BKP_CR_TPAL ((uint32_t)0x00000002) /!< TAMPER pin active level /
bogdanm	0:9b334a45a8ff	784
bogdanm	0:9b334a45a8ff	785	/***************** Bit definition for BKP_CSR register ******************/
bogdanm	0:9b334a45a8ff	786	#define BKP_CSR_CTE ((uint32_t)0x00000001) /!< Clear Tamper event /
bogdanm	0:9b334a45a8ff	787	#define BKP_CSR_CTI ((uint32_t)0x00000002) /!< Clear Tamper Interrupt /
bogdanm	0:9b334a45a8ff	788	#define BKP_CSR_TPIE ((uint32_t)0x00000004) /!< TAMPER Pin interrupt enable /
bogdanm	0:9b334a45a8ff	789	#define BKP_CSR_TEF ((uint32_t)0x00000100) /!< Tamper Event Flag /
bogdanm	0:9b334a45a8ff	790	#define BKP_CSR_TIF ((uint32_t)0x00000200) /!< Tamper Interrupt Flag /
bogdanm	0:9b334a45a8ff	791
bogdanm	0:9b334a45a8ff	792	/******************************************************************************/
bogdanm	0:9b334a45a8ff	793	/* */
bogdanm	0:9b334a45a8ff	794	/* Reset and Clock Control */
bogdanm	0:9b334a45a8ff	795	/* */
bogdanm	0:9b334a45a8ff	796	/******************************************************************************/
bogdanm	0:9b334a45a8ff	797
bogdanm	0:9b334a45a8ff	798	/****************** Bit definition for RCC_CR register ******************/
bogdanm	0:9b334a45a8ff	799	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
bogdanm	0:9b334a45a8ff	800	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
bogdanm	0:9b334a45a8ff	801	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
bogdanm	0:9b334a45a8ff	802	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
bogdanm	0:9b334a45a8ff	803	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
bogdanm	0:9b334a45a8ff	804	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
bogdanm	0:9b334a45a8ff	805	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
bogdanm	0:9b334a45a8ff	806	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
bogdanm	0:9b334a45a8ff	807	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
bogdanm	0:9b334a45a8ff	808	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
bogdanm	0:9b334a45a8ff	809
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	/***************** Bit definition for RCC_CFGR register *****************/
bogdanm	0:9b334a45a8ff	812	/!< SW configuration /
bogdanm	0:9b334a45a8ff	813	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
bogdanm	0:9b334a45a8ff	814	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	815	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
bogdanm	0:9b334a45a8ff	818	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
bogdanm	0:9b334a45a8ff	819	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	/!< SWS configuration /
bogdanm	0:9b334a45a8ff	822	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
bogdanm	0:9b334a45a8ff	823	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	824	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	825
bogdanm	0:9b334a45a8ff	826	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
bogdanm	0:9b334a45a8ff	827	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
bogdanm	0:9b334a45a8ff	828	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	/!< HPRE configuration /
bogdanm	0:9b334a45a8ff	831	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
bogdanm	0:9b334a45a8ff	832	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	833	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	834	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	835	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	836
bogdanm	0:9b334a45a8ff	837	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
bogdanm	0:9b334a45a8ff	838	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
bogdanm	0:9b334a45a8ff	839	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
bogdanm	0:9b334a45a8ff	840	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
bogdanm	0:9b334a45a8ff	841	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
bogdanm	0:9b334a45a8ff	842	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
bogdanm	0:9b334a45a8ff	843	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
bogdanm	0:9b334a45a8ff	844	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
bogdanm	0:9b334a45a8ff	845	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
bogdanm	0:9b334a45a8ff	846
bogdanm	0:9b334a45a8ff	847	/!< PPRE1 configuration /
bogdanm	0:9b334a45a8ff	848	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
bogdanm	0:9b334a45a8ff	849	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	850	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	851	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	852
bogdanm	0:9b334a45a8ff	853	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
bogdanm	0:9b334a45a8ff	854	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
bogdanm	0:9b334a45a8ff	855	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
bogdanm	0:9b334a45a8ff	856	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
bogdanm	0:9b334a45a8ff	857	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	/!< PPRE2 configuration /
bogdanm	0:9b334a45a8ff	860	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
bogdanm	0:9b334a45a8ff	861	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	862	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	863	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
bogdanm	0:9b334a45a8ff	866	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
bogdanm	0:9b334a45a8ff	867	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
bogdanm	0:9b334a45a8ff	868	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
bogdanm	0:9b334a45a8ff	869	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
bogdanm	0:9b334a45a8ff	870
bogdanm	0:9b334a45a8ff	871	/!< ADCPPRE configuration /
bogdanm	0:9b334a45a8ff	872	#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /!< ADCPRE[1:0] bits (ADC prescaler) /
bogdanm	0:9b334a45a8ff	873	#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	874	#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	875
bogdanm	0:9b334a45a8ff	876	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK2 divided by 2 /
bogdanm	0:9b334a45a8ff	877	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK2 divided by 4 /
bogdanm	0:9b334a45a8ff	878	#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /!< PCLK2 divided by 6 /
bogdanm	0:9b334a45a8ff	879	#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /!< PCLK2 divided by 8 /
bogdanm	0:9b334a45a8ff	880
bogdanm	0:9b334a45a8ff	881	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
bogdanm	0:9b334a45a8ff	882
bogdanm	0:9b334a45a8ff	883	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	/!< PLLMUL configuration /
bogdanm	0:9b334a45a8ff	886	#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
bogdanm	0:9b334a45a8ff	887	#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	888	#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	889	#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	890	#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /!< PREDIV1 clock not divided for PLL entry /
bogdanm	0:9b334a45a8ff	893	#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /!< PREDIV1 clock divided by 2 for PLL entry /
bogdanm	0:9b334a45a8ff	894
bogdanm	0:9b334a45a8ff	895	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
bogdanm	0:9b334a45a8ff	896	#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
bogdanm	0:9b334a45a8ff	897	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
bogdanm	0:9b334a45a8ff	898	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
bogdanm	0:9b334a45a8ff	899	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
bogdanm	0:9b334a45a8ff	900	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
bogdanm	0:9b334a45a8ff	901	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
bogdanm	0:9b334a45a8ff	902	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
bogdanm	0:9b334a45a8ff	903	#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
bogdanm	0:9b334a45a8ff	904	#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
bogdanm	0:9b334a45a8ff	905	#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
bogdanm	0:9b334a45a8ff	906	#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
bogdanm	0:9b334a45a8ff	907	#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
bogdanm	0:9b334a45a8ff	908	#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
bogdanm	0:9b334a45a8ff	909	#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	/!< MCO configuration /
bogdanm	0:9b334a45a8ff	912	#define RCC_CFGR_MCO ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
bogdanm	0:9b334a45a8ff	913	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	914	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	915	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
bogdanm	0:9b334a45a8ff	918	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
bogdanm	0:9b334a45a8ff	919	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
bogdanm	0:9b334a45a8ff	920	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
bogdanm	0:9b334a45a8ff	921	#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	/!<*************** Bit definition for RCC_CIR register ******************/
bogdanm	0:9b334a45a8ff	924	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	925	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	926	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	927	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	928	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	929	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
bogdanm	0:9b334a45a8ff	930	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	931	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	932	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	933	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	934	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	935	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	936	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	937	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	938	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	939	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	940	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942
bogdanm	0:9b334a45a8ff	943	/*************** Bit definition for RCC_APB2RSTR register ***************/
bogdanm	0:9b334a45a8ff	944	#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /!< Alternate Function I/O reset /
bogdanm	0:9b334a45a8ff	945	#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /!< I/O port A reset /
bogdanm	0:9b334a45a8ff	946	#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /!< I/O port B reset /
bogdanm	0:9b334a45a8ff	947	#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /!< I/O port C reset /
bogdanm	0:9b334a45a8ff	948	#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /!< I/O port D reset /
bogdanm	0:9b334a45a8ff	949	#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /!< ADC 1 interface reset /
bogdanm	0:9b334a45a8ff	950
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 Timer reset /
bogdanm	0:9b334a45a8ff	953	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI 1 reset /
bogdanm	0:9b334a45a8ff	954	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 Timer reset /
bogdanm	0:9b334a45a8ff	957	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 Timer reset /
bogdanm	0:9b334a45a8ff	958	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 Timer reset /
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /!< I/O port E reset /
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963
bogdanm	0:9b334a45a8ff	964
bogdanm	0:9b334a45a8ff	965	/*************** Bit definition for RCC_APB1RSTR register ***************/
bogdanm	0:9b334a45a8ff	966	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
bogdanm	0:9b334a45a8ff	967	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
bogdanm	0:9b334a45a8ff	968	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
bogdanm	0:9b334a45a8ff	969	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
bogdanm	0:9b334a45a8ff	970	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972
bogdanm	0:9b334a45a8ff	973	#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /!< Backup interface reset /
bogdanm	0:9b334a45a8ff	974	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< Power interface reset /
bogdanm	0:9b334a45a8ff	975
bogdanm	0:9b334a45a8ff	976	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
bogdanm	0:9b334a45a8ff	977	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI 2 reset /
bogdanm	0:9b334a45a8ff	978	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
bogdanm	0:9b334a45a8ff	979	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
bogdanm	0:9b334a45a8ff	980
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982
bogdanm	0:9b334a45a8ff	983	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 reset /
bogdanm	0:9b334a45a8ff	984	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 reset /
bogdanm	0:9b334a45a8ff	985	#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /!< CEC interface reset /
bogdanm	0:9b334a45a8ff	986
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC interface reset /
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	/**************** Bit definition for RCC_AHBENR register ****************/
bogdanm	0:9b334a45a8ff	992	#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /!< DMA1 clock enable /
bogdanm	0:9b334a45a8ff	993	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
bogdanm	0:9b334a45a8ff	994	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
bogdanm	0:9b334a45a8ff	995	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998
bogdanm	0:9b334a45a8ff	999
bogdanm	0:9b334a45a8ff	1000	/**************** Bit definition for RCC_APB2ENR register ***************/
bogdanm	0:9b334a45a8ff	1001	#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /!< Alternate Function I/O clock enable /
bogdanm	0:9b334a45a8ff	1002	#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /!< I/O port A clock enable /
bogdanm	0:9b334a45a8ff	1003	#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /!< I/O port B clock enable /
bogdanm	0:9b334a45a8ff	1004	#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /!< I/O port C clock enable /
bogdanm	0:9b334a45a8ff	1005	#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /!< I/O port D clock enable /
bogdanm	0:9b334a45a8ff	1006	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /!< ADC 1 interface clock enable /
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008
bogdanm	0:9b334a45a8ff	1009	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 Timer clock enable /
bogdanm	0:9b334a45a8ff	1010	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI 1 clock enable /
bogdanm	0:9b334a45a8ff	1011	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
bogdanm	0:9b334a45a8ff	1012
bogdanm	0:9b334a45a8ff	1013	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 Timer clock enable /
bogdanm	0:9b334a45a8ff	1014	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 Timer clock enable /
bogdanm	0:9b334a45a8ff	1015	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 Timer clock enable /
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /!< I/O port E clock enable /
bogdanm	0:9b334a45a8ff	1018
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022	/*************** Bit definition for RCC_APB1ENR register ****************/
bogdanm	0:9b334a45a8ff	1023	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enabled/
bogdanm	0:9b334a45a8ff	1024	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
bogdanm	0:9b334a45a8ff	1025	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
bogdanm	0:9b334a45a8ff	1026	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
bogdanm	0:9b334a45a8ff	1027	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
bogdanm	0:9b334a45a8ff	1028
bogdanm	0:9b334a45a8ff	1029
bogdanm	0:9b334a45a8ff	1030	#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /!< Backup interface clock enable /
bogdanm	0:9b334a45a8ff	1031	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< Power interface clock enable /
bogdanm	0:9b334a45a8ff	1032
bogdanm	0:9b334a45a8ff	1033	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
bogdanm	0:9b334a45a8ff	1034	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI 2 clock enable /
bogdanm	0:9b334a45a8ff	1035	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
bogdanm	0:9b334a45a8ff	1036	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
bogdanm	0:9b334a45a8ff	1037
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
bogdanm	0:9b334a45a8ff	1041	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
bogdanm	0:9b334a45a8ff	1042	#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /!< CEC interface clock enable /
bogdanm	0:9b334a45a8ff	1043
bogdanm	0:9b334a45a8ff	1044
bogdanm	0:9b334a45a8ff	1045
bogdanm	0:9b334a45a8ff	1046	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC interface clock enable /
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	/***************** Bit definition for RCC_BDCR register *****************/
bogdanm	0:9b334a45a8ff	1049	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
bogdanm	0:9b334a45a8ff	1050	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
bogdanm	0:9b334a45a8ff	1051	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
bogdanm	0:9b334a45a8ff	1052
bogdanm	0:9b334a45a8ff	1053	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
bogdanm	0:9b334a45a8ff	1054	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1055	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	/!< RTC congiguration /
bogdanm	0:9b334a45a8ff	1058	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
bogdanm	0:9b334a45a8ff	1059	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	1060	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	1061	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
bogdanm	0:9b334a45a8ff	1064	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
bogdanm	0:9b334a45a8ff	1065
bogdanm	0:9b334a45a8ff	1066	/***************** Bit definition for RCC_CSR register ******************/
bogdanm	0:9b334a45a8ff	1067	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
bogdanm	0:9b334a45a8ff	1068	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
bogdanm	0:9b334a45a8ff	1069	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
bogdanm	0:9b334a45a8ff	1070	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
bogdanm	0:9b334a45a8ff	1071	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
bogdanm	0:9b334a45a8ff	1072	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
bogdanm	0:9b334a45a8ff	1073	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
bogdanm	0:9b334a45a8ff	1074	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
bogdanm	0:9b334a45a8ff	1075	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	/***************** Bit definition for RCC_CFGR2 register ****************/
bogdanm	0:9b334a45a8ff	1079	/!< PREDIV1 configuration /
bogdanm	0:9b334a45a8ff	1080	#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /!< PREDIV1[3:0] bits /
bogdanm	0:9b334a45a8ff	1081	#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1082	#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1083	#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1084	#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086	#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /!< PREDIV1 input clock not divided /
bogdanm	0:9b334a45a8ff	1087	#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /!< PREDIV1 input clock divided by 2 /
bogdanm	0:9b334a45a8ff	1088	#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /!< PREDIV1 input clock divided by 3 /
bogdanm	0:9b334a45a8ff	1089	#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /!< PREDIV1 input clock divided by 4 /
bogdanm	0:9b334a45a8ff	1090	#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /!< PREDIV1 input clock divided by 5 /
bogdanm	0:9b334a45a8ff	1091	#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /!< PREDIV1 input clock divided by 6 /
bogdanm	0:9b334a45a8ff	1092	#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /!< PREDIV1 input clock divided by 7 /
bogdanm	0:9b334a45a8ff	1093	#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /!< PREDIV1 input clock divided by 8 /
bogdanm	0:9b334a45a8ff	1094	#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /!< PREDIV1 input clock divided by 9 /
bogdanm	0:9b334a45a8ff	1095	#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /!< PREDIV1 input clock divided by 10 /
bogdanm	0:9b334a45a8ff	1096	#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /!< PREDIV1 input clock divided by 11 /
bogdanm	0:9b334a45a8ff	1097	#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /!< PREDIV1 input clock divided by 12 /
bogdanm	0:9b334a45a8ff	1098	#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /!< PREDIV1 input clock divided by 13 /
bogdanm	0:9b334a45a8ff	1099	#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /!< PREDIV1 input clock divided by 14 /
bogdanm	0:9b334a45a8ff	1100	#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /!< PREDIV1 input clock divided by 15 /
bogdanm	0:9b334a45a8ff	1101	#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /!< PREDIV1 input clock divided by 16 /
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1104	/* */
bogdanm	0:9b334a45a8ff	1105	/* General Purpose and Alternate Function I/O */
bogdanm	0:9b334a45a8ff	1106	/* */
bogdanm	0:9b334a45a8ff	1107	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	/***************** Bit definition for GPIO_CRL register *****************/
bogdanm	0:9b334a45a8ff	1110	#define GPIO_CRL_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112	#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
bogdanm	0:9b334a45a8ff	1113	#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1114	#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1115
bogdanm	0:9b334a45a8ff	1116	#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
bogdanm	0:9b334a45a8ff	1117	#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1118	#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
bogdanm	0:9b334a45a8ff	1121	#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1122	#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124	#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
bogdanm	0:9b334a45a8ff	1125	#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1126	#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1127
bogdanm	0:9b334a45a8ff	1128	#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
bogdanm	0:9b334a45a8ff	1129	#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1130	#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1131
bogdanm	0:9b334a45a8ff	1132	#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
bogdanm	0:9b334a45a8ff	1133	#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1134	#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1135
bogdanm	0:9b334a45a8ff	1136	#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
bogdanm	0:9b334a45a8ff	1137	#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1138	#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1139
bogdanm	0:9b334a45a8ff	1140	#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
bogdanm	0:9b334a45a8ff	1141	#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1142	#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1143
bogdanm	0:9b334a45a8ff	1144	#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
bogdanm	0:9b334a45a8ff	1147	#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1148	#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1149
bogdanm	0:9b334a45a8ff	1150	#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
bogdanm	0:9b334a45a8ff	1151	#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1152	#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
bogdanm	0:9b334a45a8ff	1155	#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1156	#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1157
bogdanm	0:9b334a45a8ff	1158	#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
bogdanm	0:9b334a45a8ff	1159	#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1160	#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1161
bogdanm	0:9b334a45a8ff	1162	#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
bogdanm	0:9b334a45a8ff	1163	#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1164	#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1165
bogdanm	0:9b334a45a8ff	1166	#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
bogdanm	0:9b334a45a8ff	1167	#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1168	#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1169
bogdanm	0:9b334a45a8ff	1170	#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
bogdanm	0:9b334a45a8ff	1171	#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1172	#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
bogdanm	0:9b334a45a8ff	1175	#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1176	#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	/***************** Bit definition for GPIO_CRH register *****************/
bogdanm	0:9b334a45a8ff	1179	#define GPIO_CRH_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
bogdanm	0:9b334a45a8ff	1180
bogdanm	0:9b334a45a8ff	1181	#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
bogdanm	0:9b334a45a8ff	1182	#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1183	#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
bogdanm	0:9b334a45a8ff	1186	#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1187	#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
bogdanm	0:9b334a45a8ff	1190	#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1191	#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
bogdanm	0:9b334a45a8ff	1194	#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1195	#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1196
bogdanm	0:9b334a45a8ff	1197	#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
bogdanm	0:9b334a45a8ff	1198	#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1199	#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
bogdanm	0:9b334a45a8ff	1202	#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1203	#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1204
bogdanm	0:9b334a45a8ff	1205	#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
bogdanm	0:9b334a45a8ff	1206	#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1207	#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209	#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
bogdanm	0:9b334a45a8ff	1210	#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1211	#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
bogdanm	0:9b334a45a8ff	1214
bogdanm	0:9b334a45a8ff	1215	#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
bogdanm	0:9b334a45a8ff	1216	#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1217	#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219	#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
bogdanm	0:9b334a45a8ff	1220	#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1221	#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1222
bogdanm	0:9b334a45a8ff	1223	#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
bogdanm	0:9b334a45a8ff	1224	#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1225	#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
bogdanm	0:9b334a45a8ff	1228	#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1229	#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231	#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
bogdanm	0:9b334a45a8ff	1232	#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1233	#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1234
bogdanm	0:9b334a45a8ff	1235	#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
bogdanm	0:9b334a45a8ff	1236	#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1237	#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1238
bogdanm	0:9b334a45a8ff	1239	#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
bogdanm	0:9b334a45a8ff	1240	#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1241	#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1242
bogdanm	0:9b334a45a8ff	1243	#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
bogdanm	0:9b334a45a8ff	1244	#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1245	#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1246
bogdanm	0:9b334a45a8ff	1247	/!<*************** Bit definition for GPIO_IDR register *****************/
bogdanm	0:9b334a45a8ff	1248	#define GPIO_IDR_IDR0 ((uint32_t)0x0001) /!< Port input data, bit 0 /
bogdanm	0:9b334a45a8ff	1249	#define GPIO_IDR_IDR1 ((uint32_t)0x0002) /!< Port input data, bit 1 /
bogdanm	0:9b334a45a8ff	1250	#define GPIO_IDR_IDR2 ((uint32_t)0x0004) /!< Port input data, bit 2 /
bogdanm	0:9b334a45a8ff	1251	#define GPIO_IDR_IDR3 ((uint32_t)0x0008) /!< Port input data, bit 3 /
bogdanm	0:9b334a45a8ff	1252	#define GPIO_IDR_IDR4 ((uint32_t)0x0010) /!< Port input data, bit 4 /
bogdanm	0:9b334a45a8ff	1253	#define GPIO_IDR_IDR5 ((uint32_t)0x0020) /!< Port input data, bit 5 /
bogdanm	0:9b334a45a8ff	1254	#define GPIO_IDR_IDR6 ((uint32_t)0x0040) /!< Port input data, bit 6 /
bogdanm	0:9b334a45a8ff	1255	#define GPIO_IDR_IDR7 ((uint32_t)0x0080) /!< Port input data, bit 7 /
bogdanm	0:9b334a45a8ff	1256	#define GPIO_IDR_IDR8 ((uint32_t)0x0100) /!< Port input data, bit 8 /
bogdanm	0:9b334a45a8ff	1257	#define GPIO_IDR_IDR9 ((uint32_t)0x0200) /!< Port input data, bit 9 /
bogdanm	0:9b334a45a8ff	1258	#define GPIO_IDR_IDR10 ((uint32_t)0x0400) /!< Port input data, bit 10 /
bogdanm	0:9b334a45a8ff	1259	#define GPIO_IDR_IDR11 ((uint32_t)0x0800) /!< Port input data, bit 11 /
bogdanm	0:9b334a45a8ff	1260	#define GPIO_IDR_IDR12 ((uint32_t)0x1000) /!< Port input data, bit 12 /
bogdanm	0:9b334a45a8ff	1261	#define GPIO_IDR_IDR13 ((uint32_t)0x2000) /!< Port input data, bit 13 /
bogdanm	0:9b334a45a8ff	1262	#define GPIO_IDR_IDR14 ((uint32_t)0x4000) /!< Port input data, bit 14 /
bogdanm	0:9b334a45a8ff	1263	#define GPIO_IDR_IDR15 ((uint32_t)0x8000) /!< Port input data, bit 15 /
bogdanm	0:9b334a45a8ff	1264
bogdanm	0:9b334a45a8ff	1265	/***************** Bit definition for GPIO_ODR register *****************/
bogdanm	0:9b334a45a8ff	1266	#define GPIO_ODR_ODR0 ((uint32_t)0x0001) /!< Port output data, bit 0 /
bogdanm	0:9b334a45a8ff	1267	#define GPIO_ODR_ODR1 ((uint32_t)0x0002) /!< Port output data, bit 1 /
bogdanm	0:9b334a45a8ff	1268	#define GPIO_ODR_ODR2 ((uint32_t)0x0004) /!< Port output data, bit 2 /
bogdanm	0:9b334a45a8ff	1269	#define GPIO_ODR_ODR3 ((uint32_t)0x0008) /!< Port output data, bit 3 /
bogdanm	0:9b334a45a8ff	1270	#define GPIO_ODR_ODR4 ((uint32_t)0x0010) /!< Port output data, bit 4 /
bogdanm	0:9b334a45a8ff	1271	#define GPIO_ODR_ODR5 ((uint32_t)0x0020) /!< Port output data, bit 5 /
bogdanm	0:9b334a45a8ff	1272	#define GPIO_ODR_ODR6 ((uint32_t)0x0040) /!< Port output data, bit 6 /
bogdanm	0:9b334a45a8ff	1273	#define GPIO_ODR_ODR7 ((uint32_t)0x0080) /!< Port output data, bit 7 /
bogdanm	0:9b334a45a8ff	1274	#define GPIO_ODR_ODR8 ((uint32_t)0x0100) /!< Port output data, bit 8 /
bogdanm	0:9b334a45a8ff	1275	#define GPIO_ODR_ODR9 ((uint32_t)0x0200) /!< Port output data, bit 9 /
bogdanm	0:9b334a45a8ff	1276	#define GPIO_ODR_ODR10 ((uint32_t)0x0400) /!< Port output data, bit 10 /
bogdanm	0:9b334a45a8ff	1277	#define GPIO_ODR_ODR11 ((uint32_t)0x0800) /!< Port output data, bit 11 /
bogdanm	0:9b334a45a8ff	1278	#define GPIO_ODR_ODR12 ((uint32_t)0x1000) /!< Port output data, bit 12 /
bogdanm	0:9b334a45a8ff	1279	#define GPIO_ODR_ODR13 ((uint32_t)0x2000) /!< Port output data, bit 13 /
bogdanm	0:9b334a45a8ff	1280	#define GPIO_ODR_ODR14 ((uint32_t)0x4000) /!< Port output data, bit 14 /
bogdanm	0:9b334a45a8ff	1281	#define GPIO_ODR_ODR15 ((uint32_t)0x8000) /!< Port output data, bit 15 /
bogdanm	0:9b334a45a8ff	1282
bogdanm	0:9b334a45a8ff	1283	/**************** Bit definition for GPIO_BSRR register *****************/
bogdanm	0:9b334a45a8ff	1284	#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /!< Port x Set bit 0 /
bogdanm	0:9b334a45a8ff	1285	#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /!< Port x Set bit 1 /
bogdanm	0:9b334a45a8ff	1286	#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /!< Port x Set bit 2 /
bogdanm	0:9b334a45a8ff	1287	#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /!< Port x Set bit 3 /
bogdanm	0:9b334a45a8ff	1288	#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /!< Port x Set bit 4 /
bogdanm	0:9b334a45a8ff	1289	#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /!< Port x Set bit 5 /
bogdanm	0:9b334a45a8ff	1290	#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /!< Port x Set bit 6 /
bogdanm	0:9b334a45a8ff	1291	#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /!< Port x Set bit 7 /
bogdanm	0:9b334a45a8ff	1292	#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /!< Port x Set bit 8 /
bogdanm	0:9b334a45a8ff	1293	#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /!< Port x Set bit 9 /
bogdanm	0:9b334a45a8ff	1294	#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /!< Port x Set bit 10 /
bogdanm	0:9b334a45a8ff	1295	#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /!< Port x Set bit 11 /
bogdanm	0:9b334a45a8ff	1296	#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /!< Port x Set bit 12 /
bogdanm	0:9b334a45a8ff	1297	#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /!< Port x Set bit 13 /
bogdanm	0:9b334a45a8ff	1298	#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /!< Port x Set bit 14 /
bogdanm	0:9b334a45a8ff	1299	#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /!< Port x Set bit 15 /
bogdanm	0:9b334a45a8ff	1300
bogdanm	0:9b334a45a8ff	1301	#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /!< Port x Reset bit 0 /
bogdanm	0:9b334a45a8ff	1302	#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /!< Port x Reset bit 1 /
bogdanm	0:9b334a45a8ff	1303	#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /!< Port x Reset bit 2 /
bogdanm	0:9b334a45a8ff	1304	#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /!< Port x Reset bit 3 /
bogdanm	0:9b334a45a8ff	1305	#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /!< Port x Reset bit 4 /
bogdanm	0:9b334a45a8ff	1306	#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /!< Port x Reset bit 5 /
bogdanm	0:9b334a45a8ff	1307	#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /!< Port x Reset bit 6 /
bogdanm	0:9b334a45a8ff	1308	#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /!< Port x Reset bit 7 /
bogdanm	0:9b334a45a8ff	1309	#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /!< Port x Reset bit 8 /
bogdanm	0:9b334a45a8ff	1310	#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /!< Port x Reset bit 9 /
bogdanm	0:9b334a45a8ff	1311	#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /!< Port x Reset bit 10 /
bogdanm	0:9b334a45a8ff	1312	#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /!< Port x Reset bit 11 /
bogdanm	0:9b334a45a8ff	1313	#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /!< Port x Reset bit 12 /
bogdanm	0:9b334a45a8ff	1314	#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /!< Port x Reset bit 13 /
bogdanm	0:9b334a45a8ff	1315	#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /!< Port x Reset bit 14 /
bogdanm	0:9b334a45a8ff	1316	#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /!< Port x Reset bit 15 /
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	/***************** Bit definition for GPIO_BRR register *****************/
bogdanm	0:9b334a45a8ff	1319	#define GPIO_BRR_BR0 ((uint32_t)0x0001) /!< Port x Reset bit 0 /
bogdanm	0:9b334a45a8ff	1320	#define GPIO_BRR_BR1 ((uint32_t)0x0002) /!< Port x Reset bit 1 /
bogdanm	0:9b334a45a8ff	1321	#define GPIO_BRR_BR2 ((uint32_t)0x0004) /!< Port x Reset bit 2 /
bogdanm	0:9b334a45a8ff	1322	#define GPIO_BRR_BR3 ((uint32_t)0x0008) /!< Port x Reset bit 3 /
bogdanm	0:9b334a45a8ff	1323	#define GPIO_BRR_BR4 ((uint32_t)0x0010) /!< Port x Reset bit 4 /
bogdanm	0:9b334a45a8ff	1324	#define GPIO_BRR_BR5 ((uint32_t)0x0020) /!< Port x Reset bit 5 /
bogdanm	0:9b334a45a8ff	1325	#define GPIO_BRR_BR6 ((uint32_t)0x0040) /!< Port x Reset bit 6 /
bogdanm	0:9b334a45a8ff	1326	#define GPIO_BRR_BR7 ((uint32_t)0x0080) /!< Port x Reset bit 7 /
bogdanm	0:9b334a45a8ff	1327	#define GPIO_BRR_BR8 ((uint32_t)0x0100) /!< Port x Reset bit 8 /
bogdanm	0:9b334a45a8ff	1328	#define GPIO_BRR_BR9 ((uint32_t)0x0200) /!< Port x Reset bit 9 /
bogdanm	0:9b334a45a8ff	1329	#define GPIO_BRR_BR10 ((uint32_t)0x0400) /!< Port x Reset bit 10 /
bogdanm	0:9b334a45a8ff	1330	#define GPIO_BRR_BR11 ((uint32_t)0x0800) /!< Port x Reset bit 11 /
bogdanm	0:9b334a45a8ff	1331	#define GPIO_BRR_BR12 ((uint32_t)0x1000) /!< Port x Reset bit 12 /
bogdanm	0:9b334a45a8ff	1332	#define GPIO_BRR_BR13 ((uint32_t)0x2000) /!< Port x Reset bit 13 /
bogdanm	0:9b334a45a8ff	1333	#define GPIO_BRR_BR14 ((uint32_t)0x4000) /!< Port x Reset bit 14 /
bogdanm	0:9b334a45a8ff	1334	#define GPIO_BRR_BR15 ((uint32_t)0x8000) /!< Port x Reset bit 15 /
bogdanm	0:9b334a45a8ff	1335
bogdanm	0:9b334a45a8ff	1336	/**************** Bit definition for GPIO_LCKR register *****************/
bogdanm	0:9b334a45a8ff	1337	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /!< Port x Lock bit 0 /
bogdanm	0:9b334a45a8ff	1338	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /!< Port x Lock bit 1 /
bogdanm	0:9b334a45a8ff	1339	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /!< Port x Lock bit 2 /
bogdanm	0:9b334a45a8ff	1340	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /!< Port x Lock bit 3 /
bogdanm	0:9b334a45a8ff	1341	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /!< Port x Lock bit 4 /
bogdanm	0:9b334a45a8ff	1342	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /!< Port x Lock bit 5 /
bogdanm	0:9b334a45a8ff	1343	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /!< Port x Lock bit 6 /
bogdanm	0:9b334a45a8ff	1344	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /!< Port x Lock bit 7 /
bogdanm	0:9b334a45a8ff	1345	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /!< Port x Lock bit 8 /
bogdanm	0:9b334a45a8ff	1346	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /!< Port x Lock bit 9 /
bogdanm	0:9b334a45a8ff	1347	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /!< Port x Lock bit 10 /
bogdanm	0:9b334a45a8ff	1348	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /!< Port x Lock bit 11 /
bogdanm	0:9b334a45a8ff	1349	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /!< Port x Lock bit 12 /
bogdanm	0:9b334a45a8ff	1350	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /!< Port x Lock bit 13 /
bogdanm	0:9b334a45a8ff	1351	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /!< Port x Lock bit 14 /
bogdanm	0:9b334a45a8ff	1352	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /!< Port x Lock bit 15 /
bogdanm	0:9b334a45a8ff	1353	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /!< Lock key /
bogdanm	0:9b334a45a8ff	1354
bogdanm	0:9b334a45a8ff	1355	/----------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	1356
bogdanm	0:9b334a45a8ff	1357	/**************** Bit definition for AFIO_EVCR register *****************/
bogdanm	0:9b334a45a8ff	1358	#define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /!< PIN[3:0] bits (Pin selection) /
bogdanm	0:9b334a45a8ff	1359	#define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1360	#define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1361	#define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1362	#define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	1363
bogdanm	0:9b334a45a8ff	1364	/!< PIN configuration /
bogdanm	0:9b334a45a8ff	1365	#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /!< Pin 0 selected /
bogdanm	0:9b334a45a8ff	1366	#define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /!< Pin 1 selected /
bogdanm	0:9b334a45a8ff	1367	#define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /!< Pin 2 selected /
bogdanm	0:9b334a45a8ff	1368	#define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /!< Pin 3 selected /
bogdanm	0:9b334a45a8ff	1369	#define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /!< Pin 4 selected /
bogdanm	0:9b334a45a8ff	1370	#define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /!< Pin 5 selected /
bogdanm	0:9b334a45a8ff	1371	#define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /!< Pin 6 selected /
bogdanm	0:9b334a45a8ff	1372	#define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /!< Pin 7 selected /
bogdanm	0:9b334a45a8ff	1373	#define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /!< Pin 8 selected /
bogdanm	0:9b334a45a8ff	1374	#define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /!< Pin 9 selected /
bogdanm	0:9b334a45a8ff	1375	#define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /!< Pin 10 selected /
bogdanm	0:9b334a45a8ff	1376	#define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /!< Pin 11 selected /
bogdanm	0:9b334a45a8ff	1377	#define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /!< Pin 12 selected /
bogdanm	0:9b334a45a8ff	1378	#define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /!< Pin 13 selected /
bogdanm	0:9b334a45a8ff	1379	#define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /!< Pin 14 selected /
bogdanm	0:9b334a45a8ff	1380	#define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /!< Pin 15 selected /
bogdanm	0:9b334a45a8ff	1381
bogdanm	0:9b334a45a8ff	1382	#define AFIO_EVCR_PORT ((uint32_t)0x00000070) /!< PORT[2:0] bits (Port selection) /
bogdanm	0:9b334a45a8ff	1383	#define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1384	#define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1385	#define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	/!< PORT configuration /
bogdanm	0:9b334a45a8ff	1388	#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /!< Port A selected /
bogdanm	0:9b334a45a8ff	1389	#define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /!< Port B selected /
bogdanm	0:9b334a45a8ff	1390	#define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /!< Port C selected /
bogdanm	0:9b334a45a8ff	1391	#define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /!< Port D selected /
bogdanm	0:9b334a45a8ff	1392	#define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /!< Port E selected /
bogdanm	0:9b334a45a8ff	1393
bogdanm	0:9b334a45a8ff	1394	#define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /!< Event Output Enable /
bogdanm	0:9b334a45a8ff	1395
bogdanm	0:9b334a45a8ff	1396	/**************** Bit definition for AFIO_MAPR register *****************/
bogdanm	0:9b334a45a8ff	1397	#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /!< SPI1 remapping /
bogdanm	0:9b334a45a8ff	1398	#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /!< I2C1 remapping /
bogdanm	0:9b334a45a8ff	1399	#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /!< USART1 remapping /
bogdanm	0:9b334a45a8ff	1400	#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /!< USART2 remapping /
bogdanm	0:9b334a45a8ff	1401
bogdanm	0:9b334a45a8ff	1402	#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /!< USART3_REMAP[1:0] bits (USART3 remapping) /
bogdanm	0:9b334a45a8ff	1403	#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1404	#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	/* USART3_REMAP configuration */
bogdanm	0:9b334a45a8ff	1407	#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
bogdanm	0:9b334a45a8ff	1408	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
bogdanm	0:9b334a45a8ff	1409	#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
bogdanm	0:9b334a45a8ff	1410
bogdanm	0:9b334a45a8ff	1411	#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
bogdanm	0:9b334a45a8ff	1412	#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1413	#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	/!< TIM1_REMAP configuration /
bogdanm	0:9b334a45a8ff	1416	#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
bogdanm	0:9b334a45a8ff	1417	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
bogdanm	0:9b334a45a8ff	1418	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
bogdanm	0:9b334a45a8ff	1419
bogdanm	0:9b334a45a8ff	1420	#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
bogdanm	0:9b334a45a8ff	1421	#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1422	#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1423
bogdanm	0:9b334a45a8ff	1424	/!< TIM2_REMAP configuration /
bogdanm	0:9b334a45a8ff	1425	#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
bogdanm	0:9b334a45a8ff	1426	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
bogdanm	0:9b334a45a8ff	1427	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
bogdanm	0:9b334a45a8ff	1428	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
bogdanm	0:9b334a45a8ff	1429
bogdanm	0:9b334a45a8ff	1430	#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
bogdanm	0:9b334a45a8ff	1431	#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1432	#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	/!< TIM3_REMAP configuration /
bogdanm	0:9b334a45a8ff	1435	#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
bogdanm	0:9b334a45a8ff	1436	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
bogdanm	0:9b334a45a8ff	1437	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
bogdanm	0:9b334a45a8ff	1438
bogdanm	0:9b334a45a8ff	1439	#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /!< TIM4_REMAP bit (TIM4 remapping) /
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441
bogdanm	0:9b334a45a8ff	1442	#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
bogdanm	0:9b334a45a8ff	1443
bogdanm	0:9b334a45a8ff	1444	/!< SWJ_CFG configuration /
bogdanm	0:9b334a45a8ff	1445	#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
bogdanm	0:9b334a45a8ff	1446	#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1447	#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1448	#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1449
bogdanm	0:9b334a45a8ff	1450	#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
bogdanm	0:9b334a45a8ff	1451	#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
bogdanm	0:9b334a45a8ff	1452	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /!< JTAG-DP Disabled and SW-DP Enabled /
bogdanm	0:9b334a45a8ff	1453	#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /!< JTAG-DP Disabled and SW-DP Disabled /
bogdanm	0:9b334a45a8ff	1454
bogdanm	0:9b334a45a8ff	1455
bogdanm	0:9b334a45a8ff	1456	/*************** Bit definition for AFIO_EXTICR1 register ***************/
bogdanm	0:9b334a45a8ff	1457	#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
bogdanm	0:9b334a45a8ff	1458	#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
bogdanm	0:9b334a45a8ff	1459	#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
bogdanm	0:9b334a45a8ff	1460	#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
bogdanm	0:9b334a45a8ff	1461
bogdanm	0:9b334a45a8ff	1462	/!< EXTI0 configuration /
bogdanm	0:9b334a45a8ff	1463	#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
bogdanm	0:9b334a45a8ff	1464	#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
bogdanm	0:9b334a45a8ff	1465	#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
bogdanm	0:9b334a45a8ff	1466	#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
bogdanm	0:9b334a45a8ff	1467	#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!< PE[0] pin /
bogdanm	0:9b334a45a8ff	1468	#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!< PF[0] pin /
bogdanm	0:9b334a45a8ff	1469	#define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /!< PG[0] pin /
bogdanm	0:9b334a45a8ff	1470
bogdanm	0:9b334a45a8ff	1471	/!< EXTI1 configuration /
bogdanm	0:9b334a45a8ff	1472	#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
bogdanm	0:9b334a45a8ff	1473	#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
bogdanm	0:9b334a45a8ff	1474	#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
bogdanm	0:9b334a45a8ff	1475	#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
bogdanm	0:9b334a45a8ff	1476	#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!< PE[1] pin /
bogdanm	0:9b334a45a8ff	1477	#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!< PF[1] pin /
bogdanm	0:9b334a45a8ff	1478	#define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /!< PG[1] pin /
bogdanm	0:9b334a45a8ff	1479
bogdanm	0:9b334a45a8ff	1480	/!< EXTI2 configuration /
bogdanm	0:9b334a45a8ff	1481	#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
bogdanm	0:9b334a45a8ff	1482	#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
bogdanm	0:9b334a45a8ff	1483	#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
bogdanm	0:9b334a45a8ff	1484	#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
bogdanm	0:9b334a45a8ff	1485	#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!< PE[2] pin /
bogdanm	0:9b334a45a8ff	1486	#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!< PF[2] pin /
bogdanm	0:9b334a45a8ff	1487	#define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /!< PG[2] pin /
bogdanm	0:9b334a45a8ff	1488
bogdanm	0:9b334a45a8ff	1489	/!< EXTI3 configuration /
bogdanm	0:9b334a45a8ff	1490	#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
bogdanm	0:9b334a45a8ff	1491	#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
bogdanm	0:9b334a45a8ff	1492	#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
bogdanm	0:9b334a45a8ff	1493	#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
bogdanm	0:9b334a45a8ff	1494	#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!< PE[3] pin /
bogdanm	0:9b334a45a8ff	1495	#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!< PF[3] pin /
bogdanm	0:9b334a45a8ff	1496	#define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /!< PG[3] pin /
bogdanm	0:9b334a45a8ff	1497
bogdanm	0:9b334a45a8ff	1498	/*************** Bit definition for AFIO_EXTICR2 register ***************/
bogdanm	0:9b334a45a8ff	1499	#define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
bogdanm	0:9b334a45a8ff	1500	#define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
bogdanm	0:9b334a45a8ff	1501	#define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
bogdanm	0:9b334a45a8ff	1502	#define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
bogdanm	0:9b334a45a8ff	1503
bogdanm	0:9b334a45a8ff	1504	/!< EXTI4 configuration /
bogdanm	0:9b334a45a8ff	1505	#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
bogdanm	0:9b334a45a8ff	1506	#define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
bogdanm	0:9b334a45a8ff	1507	#define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
bogdanm	0:9b334a45a8ff	1508	#define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
bogdanm	0:9b334a45a8ff	1509	#define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!< PE[4] pin /
bogdanm	0:9b334a45a8ff	1510	#define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!< PF[4] pin /
bogdanm	0:9b334a45a8ff	1511	#define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /!< PG[4] pin /
bogdanm	0:9b334a45a8ff	1512
bogdanm	0:9b334a45a8ff	1513	/* EXTI5 configuration */
bogdanm	0:9b334a45a8ff	1514	#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
bogdanm	0:9b334a45a8ff	1515	#define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
bogdanm	0:9b334a45a8ff	1516	#define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
bogdanm	0:9b334a45a8ff	1517	#define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
bogdanm	0:9b334a45a8ff	1518	#define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!< PE[5] pin /
bogdanm	0:9b334a45a8ff	1519	#define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!< PF[5] pin /
bogdanm	0:9b334a45a8ff	1520	#define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /!< PG[5] pin /
bogdanm	0:9b334a45a8ff	1521
bogdanm	0:9b334a45a8ff	1522	/!< EXTI6 configuration /
bogdanm	0:9b334a45a8ff	1523	#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
bogdanm	0:9b334a45a8ff	1524	#define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
bogdanm	0:9b334a45a8ff	1525	#define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
bogdanm	0:9b334a45a8ff	1526	#define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
bogdanm	0:9b334a45a8ff	1527	#define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!< PE[6] pin /
bogdanm	0:9b334a45a8ff	1528	#define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!< PF[6] pin /
bogdanm	0:9b334a45a8ff	1529	#define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /!< PG[6] pin /
bogdanm	0:9b334a45a8ff	1530
bogdanm	0:9b334a45a8ff	1531	/!< EXTI7 configuration /
bogdanm	0:9b334a45a8ff	1532	#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
bogdanm	0:9b334a45a8ff	1533	#define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
bogdanm	0:9b334a45a8ff	1534	#define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
bogdanm	0:9b334a45a8ff	1535	#define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
bogdanm	0:9b334a45a8ff	1536	#define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!< PE[7] pin /
bogdanm	0:9b334a45a8ff	1537	#define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!< PF[7] pin /
bogdanm	0:9b334a45a8ff	1538	#define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /!< PG[7] pin /
bogdanm	0:9b334a45a8ff	1539
bogdanm	0:9b334a45a8ff	1540	/*************** Bit definition for AFIO_EXTICR3 register ***************/
bogdanm	0:9b334a45a8ff	1541	#define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
bogdanm	0:9b334a45a8ff	1542	#define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
bogdanm	0:9b334a45a8ff	1543	#define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
bogdanm	0:9b334a45a8ff	1544	#define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
bogdanm	0:9b334a45a8ff	1545
bogdanm	0:9b334a45a8ff	1546	/!< EXTI8 configuration /
bogdanm	0:9b334a45a8ff	1547	#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
bogdanm	0:9b334a45a8ff	1548	#define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
bogdanm	0:9b334a45a8ff	1549	#define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
bogdanm	0:9b334a45a8ff	1550	#define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
bogdanm	0:9b334a45a8ff	1551	#define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!< PE[8] pin /
bogdanm	0:9b334a45a8ff	1552	#define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /!< PF[8] pin /
bogdanm	0:9b334a45a8ff	1553	#define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /!< PG[8] pin /
bogdanm	0:9b334a45a8ff	1554
bogdanm	0:9b334a45a8ff	1555	/!< EXTI9 configuration /
bogdanm	0:9b334a45a8ff	1556	#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
bogdanm	0:9b334a45a8ff	1557	#define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
bogdanm	0:9b334a45a8ff	1558	#define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
bogdanm	0:9b334a45a8ff	1559	#define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
bogdanm	0:9b334a45a8ff	1560	#define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!< PE[9] pin /
bogdanm	0:9b334a45a8ff	1561	#define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!< PF[9] pin /
bogdanm	0:9b334a45a8ff	1562	#define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /!< PG[9] pin /
bogdanm	0:9b334a45a8ff	1563
bogdanm	0:9b334a45a8ff	1564	/!< EXTI10 configuration /
bogdanm	0:9b334a45a8ff	1565	#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
bogdanm	0:9b334a45a8ff	1566	#define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
bogdanm	0:9b334a45a8ff	1567	#define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
bogdanm	0:9b334a45a8ff	1568	#define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PD[10] pin /
bogdanm	0:9b334a45a8ff	1569	#define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!< PE[10] pin /
bogdanm	0:9b334a45a8ff	1570	#define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!< PF[10] pin /
bogdanm	0:9b334a45a8ff	1571	#define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /!< PG[10] pin /
bogdanm	0:9b334a45a8ff	1572
bogdanm	0:9b334a45a8ff	1573	/!< EXTI11 configuration /
bogdanm	0:9b334a45a8ff	1574	#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
bogdanm	0:9b334a45a8ff	1575	#define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
bogdanm	0:9b334a45a8ff	1576	#define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
bogdanm	0:9b334a45a8ff	1577	#define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
bogdanm	0:9b334a45a8ff	1578	#define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!< PE[11] pin /
bogdanm	0:9b334a45a8ff	1579	#define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /!< PF[11] pin /
bogdanm	0:9b334a45a8ff	1580	#define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /!< PG[11] pin /
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582	/*************** Bit definition for AFIO_EXTICR4 register ***************/
bogdanm	0:9b334a45a8ff	1583	#define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
bogdanm	0:9b334a45a8ff	1584	#define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
bogdanm	0:9b334a45a8ff	1585	#define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
bogdanm	0:9b334a45a8ff	1586	#define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
bogdanm	0:9b334a45a8ff	1587
bogdanm	0:9b334a45a8ff	1588	/* EXTI12 configuration */
bogdanm	0:9b334a45a8ff	1589	#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
bogdanm	0:9b334a45a8ff	1590	#define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
bogdanm	0:9b334a45a8ff	1591	#define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
bogdanm	0:9b334a45a8ff	1592	#define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
bogdanm	0:9b334a45a8ff	1593	#define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!< PE[12] pin /
bogdanm	0:9b334a45a8ff	1594	#define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /!< PF[12] pin /
bogdanm	0:9b334a45a8ff	1595	#define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /!< PG[12] pin /
bogdanm	0:9b334a45a8ff	1596
bogdanm	0:9b334a45a8ff	1597	/* EXTI13 configuration */
bogdanm	0:9b334a45a8ff	1598	#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
bogdanm	0:9b334a45a8ff	1599	#define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
bogdanm	0:9b334a45a8ff	1600	#define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
bogdanm	0:9b334a45a8ff	1601	#define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
bogdanm	0:9b334a45a8ff	1602	#define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!< PE[13] pin /
bogdanm	0:9b334a45a8ff	1603	#define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /!< PF[13] pin /
bogdanm	0:9b334a45a8ff	1604	#define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /!< PG[13] pin /
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	/!< EXTI14 configuration /
bogdanm	0:9b334a45a8ff	1607	#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
bogdanm	0:9b334a45a8ff	1608	#define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
bogdanm	0:9b334a45a8ff	1609	#define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
bogdanm	0:9b334a45a8ff	1610	#define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
bogdanm	0:9b334a45a8ff	1611	#define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!< PE[14] pin /
bogdanm	0:9b334a45a8ff	1612	#define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /!< PF[14] pin /
bogdanm	0:9b334a45a8ff	1613	#define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /!< PG[14] pin /
bogdanm	0:9b334a45a8ff	1614
bogdanm	0:9b334a45a8ff	1615	/!< EXTI15 configuration /
bogdanm	0:9b334a45a8ff	1616	#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
bogdanm	0:9b334a45a8ff	1617	#define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
bogdanm	0:9b334a45a8ff	1618	#define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
bogdanm	0:9b334a45a8ff	1619	#define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
bogdanm	0:9b334a45a8ff	1620	#define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!< PE[15] pin /
bogdanm	0:9b334a45a8ff	1621	#define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /!< PF[15] pin /
bogdanm	0:9b334a45a8ff	1622	#define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /!< PG[15] pin /
bogdanm	0:9b334a45a8ff	1623
bogdanm	0:9b334a45a8ff	1624	/**************** Bit definition for AFIO_MAPR2 register ****************/
bogdanm	0:9b334a45a8ff	1625	#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /!< TIM15 remapping /
bogdanm	0:9b334a45a8ff	1626	#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /!< TIM16 remapping /
bogdanm	0:9b334a45a8ff	1627	#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /!< TIM17 remapping /
bogdanm	0:9b334a45a8ff	1628	#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /!< CEC remapping /
bogdanm	0:9b334a45a8ff	1629	#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /!< TIM1_DMA remapping /
bogdanm	0:9b334a45a8ff	1630
bogdanm	0:9b334a45a8ff	1631	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /!< TIM6/TIM7 and DAC DMA remapping /
bogdanm	0:9b334a45a8ff	1632
bogdanm	0:9b334a45a8ff	1633
bogdanm	0:9b334a45a8ff	1634	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1635	/* */
bogdanm	0:9b334a45a8ff	1636	/* SystemTick */
bogdanm	0:9b334a45a8ff	1637	/* */
bogdanm	0:9b334a45a8ff	1638	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1639
bogdanm	0:9b334a45a8ff	1640	/*************** Bit definition for SysTick_CTRL register ***************/
bogdanm	0:9b334a45a8ff	1641	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
bogdanm	0:9b334a45a8ff	1642	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
bogdanm	0:9b334a45a8ff	1643	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
bogdanm	0:9b334a45a8ff	1644	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
bogdanm	0:9b334a45a8ff	1645
bogdanm	0:9b334a45a8ff	1646	/*************** Bit definition for SysTick_LOAD register ***************/
bogdanm	0:9b334a45a8ff	1647	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
bogdanm	0:9b334a45a8ff	1648
bogdanm	0:9b334a45a8ff	1649	/*************** Bit definition for SysTick_VAL register ****************/
bogdanm	0:9b334a45a8ff	1650	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
bogdanm	0:9b334a45a8ff	1651
bogdanm	0:9b334a45a8ff	1652	/*************** Bit definition for SysTick_CALIB register **************/
bogdanm	0:9b334a45a8ff	1653	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
bogdanm	0:9b334a45a8ff	1654	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
bogdanm	0:9b334a45a8ff	1655	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
bogdanm	0:9b334a45a8ff	1656
bogdanm	0:9b334a45a8ff	1657	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1658	/* */
bogdanm	0:9b334a45a8ff	1659	/* Nested Vectored Interrupt Controller */
bogdanm	0:9b334a45a8ff	1660	/* */
bogdanm	0:9b334a45a8ff	1661	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1662
bogdanm	0:9b334a45a8ff	1663	/**************** Bit definition for NVIC_ISER register *****************/
bogdanm	0:9b334a45a8ff	1664	#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /!< Interrupt set enable bits /
bogdanm	0:9b334a45a8ff	1665	#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /!< bit 0 /
bogdanm	0:9b334a45a8ff	1666	#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /!< bit 1 /
bogdanm	0:9b334a45a8ff	1667	#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /!< bit 2 /
bogdanm	0:9b334a45a8ff	1668	#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /!< bit 3 /
bogdanm	0:9b334a45a8ff	1669	#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /!< bit 4 /
bogdanm	0:9b334a45a8ff	1670	#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /!< bit 5 /
bogdanm	0:9b334a45a8ff	1671	#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /!< bit 6 /
bogdanm	0:9b334a45a8ff	1672	#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /!< bit 7 /
bogdanm	0:9b334a45a8ff	1673	#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /!< bit 8 /
bogdanm	0:9b334a45a8ff	1674	#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /!< bit 9 /
bogdanm	0:9b334a45a8ff	1675	#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /!< bit 10 /
bogdanm	0:9b334a45a8ff	1676	#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /!< bit 11 /
bogdanm	0:9b334a45a8ff	1677	#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /!< bit 12 /
bogdanm	0:9b334a45a8ff	1678	#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /!< bit 13 /
bogdanm	0:9b334a45a8ff	1679	#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /!< bit 14 /
bogdanm	0:9b334a45a8ff	1680	#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /!< bit 15 /
bogdanm	0:9b334a45a8ff	1681	#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /!< bit 16 /
bogdanm	0:9b334a45a8ff	1682	#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /!< bit 17 /
bogdanm	0:9b334a45a8ff	1683	#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /!< bit 18 /
bogdanm	0:9b334a45a8ff	1684	#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /!< bit 19 /
bogdanm	0:9b334a45a8ff	1685	#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /!< bit 20 /
bogdanm	0:9b334a45a8ff	1686	#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /!< bit 21 /
bogdanm	0:9b334a45a8ff	1687	#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /!< bit 22 /
bogdanm	0:9b334a45a8ff	1688	#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /!< bit 23 /
bogdanm	0:9b334a45a8ff	1689	#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /!< bit 24 /
bogdanm	0:9b334a45a8ff	1690	#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /!< bit 25 /
bogdanm	0:9b334a45a8ff	1691	#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /!< bit 26 /
bogdanm	0:9b334a45a8ff	1692	#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /!< bit 27 /
bogdanm	0:9b334a45a8ff	1693	#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /!< bit 28 /
bogdanm	0:9b334a45a8ff	1694	#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /!< bit 29 /
bogdanm	0:9b334a45a8ff	1695	#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /!< bit 30 /
bogdanm	0:9b334a45a8ff	1696	#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /!< bit 31 /
bogdanm	0:9b334a45a8ff	1697
bogdanm	0:9b334a45a8ff	1698	/**************** Bit definition for NVIC_ICER register *****************/
bogdanm	0:9b334a45a8ff	1699	#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-enable bits /
bogdanm	0:9b334a45a8ff	1700	#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /!< bit 0 /
bogdanm	0:9b334a45a8ff	1701	#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /!< bit 1 /
bogdanm	0:9b334a45a8ff	1702	#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /!< bit 2 /
bogdanm	0:9b334a45a8ff	1703	#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /!< bit 3 /
bogdanm	0:9b334a45a8ff	1704	#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /!< bit 4 /
bogdanm	0:9b334a45a8ff	1705	#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /!< bit 5 /
bogdanm	0:9b334a45a8ff	1706	#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /!< bit 6 /
bogdanm	0:9b334a45a8ff	1707	#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /!< bit 7 /
bogdanm	0:9b334a45a8ff	1708	#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /!< bit 8 /
bogdanm	0:9b334a45a8ff	1709	#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /!< bit 9 /
bogdanm	0:9b334a45a8ff	1710	#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /!< bit 10 /
bogdanm	0:9b334a45a8ff	1711	#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /!< bit 11 /
bogdanm	0:9b334a45a8ff	1712	#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /!< bit 12 /
bogdanm	0:9b334a45a8ff	1713	#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /!< bit 13 /
bogdanm	0:9b334a45a8ff	1714	#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /!< bit 14 /
bogdanm	0:9b334a45a8ff	1715	#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /!< bit 15 /
bogdanm	0:9b334a45a8ff	1716	#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /!< bit 16 /
bogdanm	0:9b334a45a8ff	1717	#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /!< bit 17 /
bogdanm	0:9b334a45a8ff	1718	#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /!< bit 18 /
bogdanm	0:9b334a45a8ff	1719	#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /!< bit 19 /
bogdanm	0:9b334a45a8ff	1720	#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /!< bit 20 /
bogdanm	0:9b334a45a8ff	1721	#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /!< bit 21 /
bogdanm	0:9b334a45a8ff	1722	#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /!< bit 22 /
bogdanm	0:9b334a45a8ff	1723	#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /!< bit 23 /
bogdanm	0:9b334a45a8ff	1724	#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /!< bit 24 /
bogdanm	0:9b334a45a8ff	1725	#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /!< bit 25 /
bogdanm	0:9b334a45a8ff	1726	#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /!< bit 26 /
bogdanm	0:9b334a45a8ff	1727	#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /!< bit 27 /
bogdanm	0:9b334a45a8ff	1728	#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /!< bit 28 /
bogdanm	0:9b334a45a8ff	1729	#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /!< bit 29 /
bogdanm	0:9b334a45a8ff	1730	#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /!< bit 30 /
bogdanm	0:9b334a45a8ff	1731	#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /!< bit 31 /
bogdanm	0:9b334a45a8ff	1732
bogdanm	0:9b334a45a8ff	1733	/**************** Bit definition for NVIC_ISPR register *****************/
bogdanm	0:9b334a45a8ff	1734	#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt set-pending bits /
bogdanm	0:9b334a45a8ff	1735	#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
bogdanm	0:9b334a45a8ff	1736	#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
bogdanm	0:9b334a45a8ff	1737	#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
bogdanm	0:9b334a45a8ff	1738	#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
bogdanm	0:9b334a45a8ff	1739	#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
bogdanm	0:9b334a45a8ff	1740	#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
bogdanm	0:9b334a45a8ff	1741	#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
bogdanm	0:9b334a45a8ff	1742	#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
bogdanm	0:9b334a45a8ff	1743	#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
bogdanm	0:9b334a45a8ff	1744	#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
bogdanm	0:9b334a45a8ff	1745	#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
bogdanm	0:9b334a45a8ff	1746	#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
bogdanm	0:9b334a45a8ff	1747	#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
bogdanm	0:9b334a45a8ff	1748	#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
bogdanm	0:9b334a45a8ff	1749	#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
bogdanm	0:9b334a45a8ff	1750	#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
bogdanm	0:9b334a45a8ff	1751	#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
bogdanm	0:9b334a45a8ff	1752	#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
bogdanm	0:9b334a45a8ff	1753	#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
bogdanm	0:9b334a45a8ff	1754	#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
bogdanm	0:9b334a45a8ff	1755	#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
bogdanm	0:9b334a45a8ff	1756	#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
bogdanm	0:9b334a45a8ff	1757	#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
bogdanm	0:9b334a45a8ff	1758	#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
bogdanm	0:9b334a45a8ff	1759	#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
bogdanm	0:9b334a45a8ff	1760	#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
bogdanm	0:9b334a45a8ff	1761	#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
bogdanm	0:9b334a45a8ff	1762	#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
bogdanm	0:9b334a45a8ff	1763	#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
bogdanm	0:9b334a45a8ff	1764	#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
bogdanm	0:9b334a45a8ff	1765	#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
bogdanm	0:9b334a45a8ff	1766	#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
bogdanm	0:9b334a45a8ff	1767
bogdanm	0:9b334a45a8ff	1768	/**************** Bit definition for NVIC_ICPR register *****************/
bogdanm	0:9b334a45a8ff	1769	#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-pending bits /
bogdanm	0:9b334a45a8ff	1770	#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
bogdanm	0:9b334a45a8ff	1771	#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
bogdanm	0:9b334a45a8ff	1772	#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
bogdanm	0:9b334a45a8ff	1773	#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
bogdanm	0:9b334a45a8ff	1774	#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
bogdanm	0:9b334a45a8ff	1775	#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
bogdanm	0:9b334a45a8ff	1776	#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
bogdanm	0:9b334a45a8ff	1777	#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
bogdanm	0:9b334a45a8ff	1778	#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
bogdanm	0:9b334a45a8ff	1779	#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
bogdanm	0:9b334a45a8ff	1780	#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
bogdanm	0:9b334a45a8ff	1781	#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
bogdanm	0:9b334a45a8ff	1782	#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
bogdanm	0:9b334a45a8ff	1783	#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
bogdanm	0:9b334a45a8ff	1784	#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
bogdanm	0:9b334a45a8ff	1785	#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
bogdanm	0:9b334a45a8ff	1786	#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
bogdanm	0:9b334a45a8ff	1787	#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
bogdanm	0:9b334a45a8ff	1788	#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
bogdanm	0:9b334a45a8ff	1789	#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
bogdanm	0:9b334a45a8ff	1790	#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
bogdanm	0:9b334a45a8ff	1791	#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
bogdanm	0:9b334a45a8ff	1792	#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
bogdanm	0:9b334a45a8ff	1793	#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
bogdanm	0:9b334a45a8ff	1794	#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
bogdanm	0:9b334a45a8ff	1795	#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
bogdanm	0:9b334a45a8ff	1796	#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
bogdanm	0:9b334a45a8ff	1797	#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
bogdanm	0:9b334a45a8ff	1798	#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
bogdanm	0:9b334a45a8ff	1799	#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
bogdanm	0:9b334a45a8ff	1800	#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
bogdanm	0:9b334a45a8ff	1801	#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
bogdanm	0:9b334a45a8ff	1802
bogdanm	0:9b334a45a8ff	1803	/**************** Bit definition for NVIC_IABR register *****************/
bogdanm	0:9b334a45a8ff	1804	#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /!< Interrupt active flags /
bogdanm	0:9b334a45a8ff	1805	#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /!< bit 0 /
bogdanm	0:9b334a45a8ff	1806	#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /!< bit 1 /
bogdanm	0:9b334a45a8ff	1807	#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /!< bit 2 /
bogdanm	0:9b334a45a8ff	1808	#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /!< bit 3 /
bogdanm	0:9b334a45a8ff	1809	#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /!< bit 4 /
bogdanm	0:9b334a45a8ff	1810	#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /!< bit 5 /
bogdanm	0:9b334a45a8ff	1811	#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /!< bit 6 /
bogdanm	0:9b334a45a8ff	1812	#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /!< bit 7 /
bogdanm	0:9b334a45a8ff	1813	#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /!< bit 8 /
bogdanm	0:9b334a45a8ff	1814	#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /!< bit 9 /
bogdanm	0:9b334a45a8ff	1815	#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /!< bit 10 /
bogdanm	0:9b334a45a8ff	1816	#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /!< bit 11 /
bogdanm	0:9b334a45a8ff	1817	#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /!< bit 12 /
bogdanm	0:9b334a45a8ff	1818	#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /!< bit 13 /
bogdanm	0:9b334a45a8ff	1819	#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /!< bit 14 /
bogdanm	0:9b334a45a8ff	1820	#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /!< bit 15 /
bogdanm	0:9b334a45a8ff	1821	#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /!< bit 16 /
bogdanm	0:9b334a45a8ff	1822	#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /!< bit 17 /
bogdanm	0:9b334a45a8ff	1823	#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /!< bit 18 /
bogdanm	0:9b334a45a8ff	1824	#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /!< bit 19 /
bogdanm	0:9b334a45a8ff	1825	#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /!< bit 20 /
bogdanm	0:9b334a45a8ff	1826	#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /!< bit 21 /
bogdanm	0:9b334a45a8ff	1827	#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /!< bit 22 /
bogdanm	0:9b334a45a8ff	1828	#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /!< bit 23 /
bogdanm	0:9b334a45a8ff	1829	#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /!< bit 24 /
bogdanm	0:9b334a45a8ff	1830	#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /!< bit 25 /
bogdanm	0:9b334a45a8ff	1831	#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /!< bit 26 /
bogdanm	0:9b334a45a8ff	1832	#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /!< bit 27 /
bogdanm	0:9b334a45a8ff	1833	#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /!< bit 28 /
bogdanm	0:9b334a45a8ff	1834	#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /!< bit 29 /
bogdanm	0:9b334a45a8ff	1835	#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /!< bit 30 /
bogdanm	0:9b334a45a8ff	1836	#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /!< bit 31 /
bogdanm	0:9b334a45a8ff	1837
bogdanm	0:9b334a45a8ff	1838	/**************** Bit definition for NVIC_PRI0 register *****************/
bogdanm	0:9b334a45a8ff	1839	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
bogdanm	0:9b334a45a8ff	1840	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
bogdanm	0:9b334a45a8ff	1841	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
bogdanm	0:9b334a45a8ff	1842	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
bogdanm	0:9b334a45a8ff	1843
bogdanm	0:9b334a45a8ff	1844	/**************** Bit definition for NVIC_PRI1 register *****************/
bogdanm	0:9b334a45a8ff	1845	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
bogdanm	0:9b334a45a8ff	1846	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
bogdanm	0:9b334a45a8ff	1847	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
bogdanm	0:9b334a45a8ff	1848	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
bogdanm	0:9b334a45a8ff	1849
bogdanm	0:9b334a45a8ff	1850	/**************** Bit definition for NVIC_PRI2 register *****************/
bogdanm	0:9b334a45a8ff	1851	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
bogdanm	0:9b334a45a8ff	1852	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
bogdanm	0:9b334a45a8ff	1853	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
bogdanm	0:9b334a45a8ff	1854	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
bogdanm	0:9b334a45a8ff	1855
bogdanm	0:9b334a45a8ff	1856	/**************** Bit definition for NVIC_PRI3 register *****************/
bogdanm	0:9b334a45a8ff	1857	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
bogdanm	0:9b334a45a8ff	1858	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
bogdanm	0:9b334a45a8ff	1859	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
bogdanm	0:9b334a45a8ff	1860	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
bogdanm	0:9b334a45a8ff	1861
bogdanm	0:9b334a45a8ff	1862	/**************** Bit definition for NVIC_PRI4 register *****************/
bogdanm	0:9b334a45a8ff	1863	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
bogdanm	0:9b334a45a8ff	1864	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
bogdanm	0:9b334a45a8ff	1865	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
bogdanm	0:9b334a45a8ff	1866	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
bogdanm	0:9b334a45a8ff	1867
bogdanm	0:9b334a45a8ff	1868	/**************** Bit definition for NVIC_PRI5 register *****************/
bogdanm	0:9b334a45a8ff	1869	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
bogdanm	0:9b334a45a8ff	1870	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
bogdanm	0:9b334a45a8ff	1871	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
bogdanm	0:9b334a45a8ff	1872	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
bogdanm	0:9b334a45a8ff	1873
bogdanm	0:9b334a45a8ff	1874	/**************** Bit definition for NVIC_PRI6 register *****************/
bogdanm	0:9b334a45a8ff	1875	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
bogdanm	0:9b334a45a8ff	1876	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
bogdanm	0:9b334a45a8ff	1877	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
bogdanm	0:9b334a45a8ff	1878	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
bogdanm	0:9b334a45a8ff	1879
bogdanm	0:9b334a45a8ff	1880	/**************** Bit definition for NVIC_PRI7 register *****************/
bogdanm	0:9b334a45a8ff	1881	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
bogdanm	0:9b334a45a8ff	1882	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
bogdanm	0:9b334a45a8ff	1883	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
bogdanm	0:9b334a45a8ff	1884	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
bogdanm	0:9b334a45a8ff	1885
bogdanm	0:9b334a45a8ff	1886	/**************** Bit definition for SCB_CPUID register *****************/
bogdanm	0:9b334a45a8ff	1887	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
bogdanm	0:9b334a45a8ff	1888	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
bogdanm	0:9b334a45a8ff	1889	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
bogdanm	0:9b334a45a8ff	1890	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
bogdanm	0:9b334a45a8ff	1891	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
bogdanm	0:9b334a45a8ff	1892
bogdanm	0:9b334a45a8ff	1893	/***************** Bit definition for SCB_ICSR register *****************/
bogdanm	0:9b334a45a8ff	1894	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
bogdanm	0:9b334a45a8ff	1895	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
bogdanm	0:9b334a45a8ff	1896	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
bogdanm	0:9b334a45a8ff	1897	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
bogdanm	0:9b334a45a8ff	1898	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
bogdanm	0:9b334a45a8ff	1899	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
bogdanm	0:9b334a45a8ff	1900	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
bogdanm	0:9b334a45a8ff	1901	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
bogdanm	0:9b334a45a8ff	1902	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
bogdanm	0:9b334a45a8ff	1903	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
bogdanm	0:9b334a45a8ff	1904
bogdanm	0:9b334a45a8ff	1905	/***************** Bit definition for SCB_VTOR register *****************/
bogdanm	0:9b334a45a8ff	1906	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
bogdanm	0:9b334a45a8ff	1907	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
bogdanm	0:9b334a45a8ff	1908
bogdanm	0:9b334a45a8ff	1909	/!<************** Bit definition for SCB_AIRCR register *****************/
bogdanm	0:9b334a45a8ff	1910	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
bogdanm	0:9b334a45a8ff	1911	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
bogdanm	0:9b334a45a8ff	1912	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
bogdanm	0:9b334a45a8ff	1913
bogdanm	0:9b334a45a8ff	1914	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
bogdanm	0:9b334a45a8ff	1915	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	1916	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	1917	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	1918
bogdanm	0:9b334a45a8ff	1919	/* prority group configuration */
bogdanm	0:9b334a45a8ff	1920	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
bogdanm	0:9b334a45a8ff	1921	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
bogdanm	0:9b334a45a8ff	1922	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
bogdanm	0:9b334a45a8ff	1923	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
bogdanm	0:9b334a45a8ff	1924	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
bogdanm	0:9b334a45a8ff	1925	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
bogdanm	0:9b334a45a8ff	1926	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
bogdanm	0:9b334a45a8ff	1927	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
bogdanm	0:9b334a45a8ff	1928
bogdanm	0:9b334a45a8ff	1929	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
bogdanm	0:9b334a45a8ff	1930	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
bogdanm	0:9b334a45a8ff	1931
bogdanm	0:9b334a45a8ff	1932	/***************** Bit definition for SCB_SCR register ******************/
bogdanm	0:9b334a45a8ff	1933	#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /!< Sleep on exit bit /
bogdanm	0:9b334a45a8ff	1934	#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /!< Sleep deep bit /
bogdanm	0:9b334a45a8ff	1935	#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /!< Wake up from WFE /
bogdanm	0:9b334a45a8ff	1936
bogdanm	0:9b334a45a8ff	1937	/****************** Bit definition for SCB_CCR register *****************/
bogdanm	0:9b334a45a8ff	1938	#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
bogdanm	0:9b334a45a8ff	1939	#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
bogdanm	0:9b334a45a8ff	1940	#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /!< Trap for unaligned access /
bogdanm	0:9b334a45a8ff	1941	#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /!< Trap on Divide by 0 /
bogdanm	0:9b334a45a8ff	1942	#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /!< Handlers running at priority -1 and -2 /
bogdanm	0:9b334a45a8ff	1943	#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
bogdanm	0:9b334a45a8ff	1944
bogdanm	0:9b334a45a8ff	1945	/***************** Bit definition for SCB_SHPR register ******************/
bogdanm	0:9b334a45a8ff	1946	#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
bogdanm	0:9b334a45a8ff	1947	#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
bogdanm	0:9b334a45a8ff	1948	#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
bogdanm	0:9b334a45a8ff	1949	#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
bogdanm	0:9b334a45a8ff	1950
bogdanm	0:9b334a45a8ff	1951	/**************** Bit definition for SCB_SHCSR register *****************/
bogdanm	0:9b334a45a8ff	1952	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
bogdanm	0:9b334a45a8ff	1953	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
bogdanm	0:9b334a45a8ff	1954	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
bogdanm	0:9b334a45a8ff	1955	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
bogdanm	0:9b334a45a8ff	1956	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
bogdanm	0:9b334a45a8ff	1957	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
bogdanm	0:9b334a45a8ff	1958	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
bogdanm	0:9b334a45a8ff	1959	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
bogdanm	0:9b334a45a8ff	1960	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
bogdanm	0:9b334a45a8ff	1961	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
bogdanm	0:9b334a45a8ff	1962	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
bogdanm	0:9b334a45a8ff	1963	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
bogdanm	0:9b334a45a8ff	1964	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
bogdanm	0:9b334a45a8ff	1965	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
bogdanm	0:9b334a45a8ff	1966
bogdanm	0:9b334a45a8ff	1967	/***************** Bit definition for SCB_CFSR register *****************/
bogdanm	0:9b334a45a8ff	1968	/!< MFSR /
bogdanm	0:9b334a45a8ff	1969	#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /!< Instruction access violation /
bogdanm	0:9b334a45a8ff	1970	#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /!< Data access violation /
bogdanm	0:9b334a45a8ff	1971	#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /!< Unstacking error /
bogdanm	0:9b334a45a8ff	1972	#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /!< Stacking error /
bogdanm	0:9b334a45a8ff	1973	#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /!< Memory Manage Address Register address valid flag /
bogdanm	0:9b334a45a8ff	1974	/!< BFSR /
bogdanm	0:9b334a45a8ff	1975	#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /!< Instruction bus error flag /
bogdanm	0:9b334a45a8ff	1976	#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /!< Precise data bus error /
bogdanm	0:9b334a45a8ff	1977	#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /!< Imprecise data bus error /
bogdanm	0:9b334a45a8ff	1978	#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /!< Unstacking error /
bogdanm	0:9b334a45a8ff	1979	#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /!< Stacking error /
bogdanm	0:9b334a45a8ff	1980	#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /!< Bus Fault Address Register address valid flag /
bogdanm	0:9b334a45a8ff	1981	/!< UFSR /
bogdanm	0:9b334a45a8ff	1982	#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /!< The processor attempt to execute an undefined instruction /
bogdanm	0:9b334a45a8ff	1983	#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /!< Invalid combination of EPSR and instruction /
bogdanm	0:9b334a45a8ff	1984	#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /!< Attempt to load EXC_RETURN into pc illegally /
bogdanm	0:9b334a45a8ff	1985	#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /!< Attempt to use a coprocessor instruction /
bogdanm	0:9b334a45a8ff	1986	#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /!< Fault occurs when there is an attempt to make an unaligned memory access /
bogdanm	0:9b334a45a8ff	1987	#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
bogdanm	0:9b334a45a8ff	1988
bogdanm	0:9b334a45a8ff	1989	/***************** Bit definition for SCB_HFSR register *****************/
bogdanm	0:9b334a45a8ff	1990	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occurs because of vector table read on exception processing /
bogdanm	0:9b334a45a8ff	1991	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
bogdanm	0:9b334a45a8ff	1992	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
bogdanm	0:9b334a45a8ff	1993
bogdanm	0:9b334a45a8ff	1994	/***************** Bit definition for SCB_DFSR register *****************/
bogdanm	0:9b334a45a8ff	1995	#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /!< Halt request flag /
bogdanm	0:9b334a45a8ff	1996	#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /!< BKPT flag /
bogdanm	0:9b334a45a8ff	1997	#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /!< Data Watchpoint and Trace (DWT) flag /
bogdanm	0:9b334a45a8ff	1998	#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /!< Vector catch flag /
bogdanm	0:9b334a45a8ff	1999	#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /!< External debug request flag /
bogdanm	0:9b334a45a8ff	2000
bogdanm	0:9b334a45a8ff	2001	/***************** Bit definition for SCB_MMFAR register ****************/
bogdanm	0:9b334a45a8ff	2002	#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Mem Manage fault address field /
bogdanm	0:9b334a45a8ff	2003
bogdanm	0:9b334a45a8ff	2004	/***************** Bit definition for SCB_BFAR register *****************/
bogdanm	0:9b334a45a8ff	2005	#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Bus fault address field /
bogdanm	0:9b334a45a8ff	2006
bogdanm	0:9b334a45a8ff	2007	/***************** Bit definition for SCB_afsr register *****************/
bogdanm	0:9b334a45a8ff	2008	#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /!< Implementation defined /
bogdanm	0:9b334a45a8ff	2009
bogdanm	0:9b334a45a8ff	2010	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2011	/* */
bogdanm	0:9b334a45a8ff	2012	/* External Interrupt/Event Controller */
bogdanm	0:9b334a45a8ff	2013	/* */
bogdanm	0:9b334a45a8ff	2014	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2015
bogdanm	0:9b334a45a8ff	2016	/***************** Bit definition for EXTI_IMR register *****************/
bogdanm	0:9b334a45a8ff	2017	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
bogdanm	0:9b334a45a8ff	2018	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
bogdanm	0:9b334a45a8ff	2019	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
bogdanm	0:9b334a45a8ff	2020	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
bogdanm	0:9b334a45a8ff	2021	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
bogdanm	0:9b334a45a8ff	2022	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
bogdanm	0:9b334a45a8ff	2023	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
bogdanm	0:9b334a45a8ff	2024	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
bogdanm	0:9b334a45a8ff	2025	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
bogdanm	0:9b334a45a8ff	2026	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
bogdanm	0:9b334a45a8ff	2027	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
bogdanm	0:9b334a45a8ff	2028	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
bogdanm	0:9b334a45a8ff	2029	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
bogdanm	0:9b334a45a8ff	2030	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
bogdanm	0:9b334a45a8ff	2031	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
bogdanm	0:9b334a45a8ff	2032	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
bogdanm	0:9b334a45a8ff	2033	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
bogdanm	0:9b334a45a8ff	2034	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
bogdanm	0:9b334a45a8ff	2035	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
bogdanm	0:9b334a45a8ff	2036	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
bogdanm	0:9b334a45a8ff	2037
bogdanm	0:9b334a45a8ff	2038	/***************** Bit definition for EXTI_EMR register *****************/
bogdanm	0:9b334a45a8ff	2039	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
bogdanm	0:9b334a45a8ff	2040	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
bogdanm	0:9b334a45a8ff	2041	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
bogdanm	0:9b334a45a8ff	2042	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
bogdanm	0:9b334a45a8ff	2043	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
bogdanm	0:9b334a45a8ff	2044	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
bogdanm	0:9b334a45a8ff	2045	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
bogdanm	0:9b334a45a8ff	2046	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
bogdanm	0:9b334a45a8ff	2047	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
bogdanm	0:9b334a45a8ff	2048	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
bogdanm	0:9b334a45a8ff	2049	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
bogdanm	0:9b334a45a8ff	2050	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
bogdanm	0:9b334a45a8ff	2051	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
bogdanm	0:9b334a45a8ff	2052	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
bogdanm	0:9b334a45a8ff	2053	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
bogdanm	0:9b334a45a8ff	2054	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
bogdanm	0:9b334a45a8ff	2055	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
bogdanm	0:9b334a45a8ff	2056	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
bogdanm	0:9b334a45a8ff	2057	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
bogdanm	0:9b334a45a8ff	2058	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
bogdanm	0:9b334a45a8ff	2059
bogdanm	0:9b334a45a8ff	2060	/**************** Bit definition for EXTI_RTSR register *****************/
bogdanm	0:9b334a45a8ff	2061	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
bogdanm	0:9b334a45a8ff	2062	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
bogdanm	0:9b334a45a8ff	2063	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
bogdanm	0:9b334a45a8ff	2064	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
bogdanm	0:9b334a45a8ff	2065	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
bogdanm	0:9b334a45a8ff	2066	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
bogdanm	0:9b334a45a8ff	2067	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
bogdanm	0:9b334a45a8ff	2068	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
bogdanm	0:9b334a45a8ff	2069	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
bogdanm	0:9b334a45a8ff	2070	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
bogdanm	0:9b334a45a8ff	2071	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
bogdanm	0:9b334a45a8ff	2072	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
bogdanm	0:9b334a45a8ff	2073	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
bogdanm	0:9b334a45a8ff	2074	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
bogdanm	0:9b334a45a8ff	2075	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
bogdanm	0:9b334a45a8ff	2076	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
bogdanm	0:9b334a45a8ff	2077	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
bogdanm	0:9b334a45a8ff	2078	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
bogdanm	0:9b334a45a8ff	2079	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
bogdanm	0:9b334a45a8ff	2080	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
bogdanm	0:9b334a45a8ff	2081
bogdanm	0:9b334a45a8ff	2082	/**************** Bit definition for EXTI_FTSR register *****************/
bogdanm	0:9b334a45a8ff	2083	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
bogdanm	0:9b334a45a8ff	2084	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
bogdanm	0:9b334a45a8ff	2085	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
bogdanm	0:9b334a45a8ff	2086	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
bogdanm	0:9b334a45a8ff	2087	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
bogdanm	0:9b334a45a8ff	2088	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
bogdanm	0:9b334a45a8ff	2089	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
bogdanm	0:9b334a45a8ff	2090	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
bogdanm	0:9b334a45a8ff	2091	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
bogdanm	0:9b334a45a8ff	2092	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
bogdanm	0:9b334a45a8ff	2093	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
bogdanm	0:9b334a45a8ff	2094	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
bogdanm	0:9b334a45a8ff	2095	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
bogdanm	0:9b334a45a8ff	2096	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
bogdanm	0:9b334a45a8ff	2097	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
bogdanm	0:9b334a45a8ff	2098	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
bogdanm	0:9b334a45a8ff	2099	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
bogdanm	0:9b334a45a8ff	2100	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
bogdanm	0:9b334a45a8ff	2101	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
bogdanm	0:9b334a45a8ff	2102	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
bogdanm	0:9b334a45a8ff	2103
bogdanm	0:9b334a45a8ff	2104	/**************** Bit definition for EXTI_SWIER register ****************/
bogdanm	0:9b334a45a8ff	2105	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
bogdanm	0:9b334a45a8ff	2106	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
bogdanm	0:9b334a45a8ff	2107	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
bogdanm	0:9b334a45a8ff	2108	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
bogdanm	0:9b334a45a8ff	2109	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
bogdanm	0:9b334a45a8ff	2110	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
bogdanm	0:9b334a45a8ff	2111	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
bogdanm	0:9b334a45a8ff	2112	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
bogdanm	0:9b334a45a8ff	2113	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
bogdanm	0:9b334a45a8ff	2114	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
bogdanm	0:9b334a45a8ff	2115	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
bogdanm	0:9b334a45a8ff	2116	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
bogdanm	0:9b334a45a8ff	2117	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
bogdanm	0:9b334a45a8ff	2118	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
bogdanm	0:9b334a45a8ff	2119	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
bogdanm	0:9b334a45a8ff	2120	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
bogdanm	0:9b334a45a8ff	2121	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
bogdanm	0:9b334a45a8ff	2122	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
bogdanm	0:9b334a45a8ff	2123	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
bogdanm	0:9b334a45a8ff	2124	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
bogdanm	0:9b334a45a8ff	2125
bogdanm	0:9b334a45a8ff	2126	/***************** Bit definition for EXTI_PR register ******************/
bogdanm	0:9b334a45a8ff	2127	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
bogdanm	0:9b334a45a8ff	2128	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
bogdanm	0:9b334a45a8ff	2129	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
bogdanm	0:9b334a45a8ff	2130	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
bogdanm	0:9b334a45a8ff	2131	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
bogdanm	0:9b334a45a8ff	2132	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
bogdanm	0:9b334a45a8ff	2133	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
bogdanm	0:9b334a45a8ff	2134	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
bogdanm	0:9b334a45a8ff	2135	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
bogdanm	0:9b334a45a8ff	2136	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
bogdanm	0:9b334a45a8ff	2137	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
bogdanm	0:9b334a45a8ff	2138	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
bogdanm	0:9b334a45a8ff	2139	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
bogdanm	0:9b334a45a8ff	2140	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
bogdanm	0:9b334a45a8ff	2141	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
bogdanm	0:9b334a45a8ff	2142	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
bogdanm	0:9b334a45a8ff	2143	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
bogdanm	0:9b334a45a8ff	2144	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
bogdanm	0:9b334a45a8ff	2145	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
bogdanm	0:9b334a45a8ff	2146	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
bogdanm	0:9b334a45a8ff	2147
bogdanm	0:9b334a45a8ff	2148	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2149	/* */
bogdanm	0:9b334a45a8ff	2150	/* DMA Controller */
bogdanm	0:9b334a45a8ff	2151	/* */
bogdanm	0:9b334a45a8ff	2152	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2153
bogdanm	0:9b334a45a8ff	2154	/***************** Bit definition for DMA_ISR register ******************/
bogdanm	0:9b334a45a8ff	2155	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
bogdanm	0:9b334a45a8ff	2156	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	2157	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
bogdanm	0:9b334a45a8ff	2158	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
bogdanm	0:9b334a45a8ff	2159	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
bogdanm	0:9b334a45a8ff	2160	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	2161	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
bogdanm	0:9b334a45a8ff	2162	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
bogdanm	0:9b334a45a8ff	2163	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
bogdanm	0:9b334a45a8ff	2164	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	2165	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
bogdanm	0:9b334a45a8ff	2166	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
bogdanm	0:9b334a45a8ff	2167	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
bogdanm	0:9b334a45a8ff	2168	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	2169	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
bogdanm	0:9b334a45a8ff	2170	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
bogdanm	0:9b334a45a8ff	2171	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
bogdanm	0:9b334a45a8ff	2172	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	2173	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
bogdanm	0:9b334a45a8ff	2174	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
bogdanm	0:9b334a45a8ff	2175	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
bogdanm	0:9b334a45a8ff	2176	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	2177	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
bogdanm	0:9b334a45a8ff	2178	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
bogdanm	0:9b334a45a8ff	2179	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
bogdanm	0:9b334a45a8ff	2180	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	2181	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
bogdanm	0:9b334a45a8ff	2182	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
bogdanm	0:9b334a45a8ff	2183
bogdanm	0:9b334a45a8ff	2184	/***************** Bit definition for DMA_IFCR register *****************/
bogdanm	0:9b334a45a8ff	2185	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
bogdanm	0:9b334a45a8ff	2186	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	2187	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
bogdanm	0:9b334a45a8ff	2188	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
bogdanm	0:9b334a45a8ff	2189	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
bogdanm	0:9b334a45a8ff	2190	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	2191	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
bogdanm	0:9b334a45a8ff	2192	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
bogdanm	0:9b334a45a8ff	2193	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
bogdanm	0:9b334a45a8ff	2194	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	2195	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
bogdanm	0:9b334a45a8ff	2196	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
bogdanm	0:9b334a45a8ff	2197	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
bogdanm	0:9b334a45a8ff	2198	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	2199	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
bogdanm	0:9b334a45a8ff	2200	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
bogdanm	0:9b334a45a8ff	2201	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
bogdanm	0:9b334a45a8ff	2202	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	2203	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
bogdanm	0:9b334a45a8ff	2204	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
bogdanm	0:9b334a45a8ff	2205	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
bogdanm	0:9b334a45a8ff	2206	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	2207	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
bogdanm	0:9b334a45a8ff	2208	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
bogdanm	0:9b334a45a8ff	2209	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
bogdanm	0:9b334a45a8ff	2210	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	2211	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
bogdanm	0:9b334a45a8ff	2212	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
bogdanm	0:9b334a45a8ff	2213
bogdanm	0:9b334a45a8ff	2214	/***************** Bit definition for DMA_CCR register *****************/
bogdanm	0:9b334a45a8ff	2215	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
bogdanm	0:9b334a45a8ff	2216	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
bogdanm	0:9b334a45a8ff	2217	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
bogdanm	0:9b334a45a8ff	2218	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
bogdanm	0:9b334a45a8ff	2219	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
bogdanm	0:9b334a45a8ff	2220	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
bogdanm	0:9b334a45a8ff	2221	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
bogdanm	0:9b334a45a8ff	2222	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
bogdanm	0:9b334a45a8ff	2223
bogdanm	0:9b334a45a8ff	2224	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
bogdanm	0:9b334a45a8ff	2225	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2226	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2227
bogdanm	0:9b334a45a8ff	2228	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
bogdanm	0:9b334a45a8ff	2229	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2230	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2231
bogdanm	0:9b334a45a8ff	2232	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level) /
bogdanm	0:9b334a45a8ff	2233	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2234	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2235
bogdanm	0:9b334a45a8ff	2236	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
bogdanm	0:9b334a45a8ff	2237
bogdanm	0:9b334a45a8ff	2238	/**************** Bit definition for DMA_CNDTR register ****************/
bogdanm	0:9b334a45a8ff	2239	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
bogdanm	0:9b334a45a8ff	2240
bogdanm	0:9b334a45a8ff	2241	/**************** Bit definition for DMA_CPAR register *****************/
bogdanm	0:9b334a45a8ff	2242	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
bogdanm	0:9b334a45a8ff	2243
bogdanm	0:9b334a45a8ff	2244	/**************** Bit definition for DMA_CMAR register *****************/
bogdanm	0:9b334a45a8ff	2245	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
bogdanm	0:9b334a45a8ff	2246
bogdanm	0:9b334a45a8ff	2247	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2248	/* */
bogdanm	0:9b334a45a8ff	2249	/* Analog to Digital Converter */
bogdanm	0:9b334a45a8ff	2250	/* */
bogdanm	0:9b334a45a8ff	2251	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2252
bogdanm	0:9b334a45a8ff	2253	/****************** Bit definition for ADC_SR register ******************/
bogdanm	0:9b334a45a8ff	2254	#define ADC_SR_AWD ((uint32_t)0x00000001) /!< Analog watchdog flag /
bogdanm	0:9b334a45a8ff	2255	#define ADC_SR_EOC ((uint32_t)0x00000002) /!< End of conversion /
bogdanm	0:9b334a45a8ff	2256	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!< Injected channel end of conversion /
bogdanm	0:9b334a45a8ff	2257	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!< Injected channel Start flag /
bogdanm	0:9b334a45a8ff	2258	#define ADC_SR_STRT ((uint32_t)0x00000010) /!< Regular channel Start flag /
bogdanm	0:9b334a45a8ff	2259
bogdanm	0:9b334a45a8ff	2260	/***************** Bit definition for ADC_CR1 register ******************/
bogdanm	0:9b334a45a8ff	2261	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
bogdanm	0:9b334a45a8ff	2262	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2263	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2264	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2265	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2266	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2267
bogdanm	0:9b334a45a8ff	2268	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!< Interrupt enable for EOC /
bogdanm	0:9b334a45a8ff	2269	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!< Analog Watchdog interrupt enable /
bogdanm	0:9b334a45a8ff	2270	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!< Interrupt enable for injected channels /
bogdanm	0:9b334a45a8ff	2271	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!< Scan mode /
bogdanm	0:9b334a45a8ff	2272	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!< Enable the watchdog on a single channel in scan mode /
bogdanm	0:9b334a45a8ff	2273	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!< Automatic injected group conversion /
bogdanm	0:9b334a45a8ff	2274	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!< Discontinuous mode on regular channels /
bogdanm	0:9b334a45a8ff	2275	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!< Discontinuous mode on injected channels /
bogdanm	0:9b334a45a8ff	2276
bogdanm	0:9b334a45a8ff	2277	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!< DISCNUM[2:0] bits (Discontinuous mode channel count) /
bogdanm	0:9b334a45a8ff	2278	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2279	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2280	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2281
bogdanm	0:9b334a45a8ff	2282	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!< Analog watchdog enable on injected channels /
bogdanm	0:9b334a45a8ff	2283	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
bogdanm	0:9b334a45a8ff	2284
bogdanm	0:9b334a45a8ff	2285
bogdanm	0:9b334a45a8ff	2286	/***************** Bit definition for ADC_CR2 register ******************/
bogdanm	0:9b334a45a8ff	2287	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!< A/D Converter ON / OFF /
bogdanm	0:9b334a45a8ff	2288	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!< Continuous Conversion /
bogdanm	0:9b334a45a8ff	2289	#define ADC_CR2_CAL ((uint32_t)0x00000004) /!< A/D Calibration /
bogdanm	0:9b334a45a8ff	2290	#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /!< Reset Calibration /
bogdanm	0:9b334a45a8ff	2291	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!< Direct Memory access mode /
bogdanm	0:9b334a45a8ff	2292	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!< Data Alignment /
bogdanm	0:9b334a45a8ff	2293
bogdanm	0:9b334a45a8ff	2294	#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /!< JEXTSEL[2:0] bits (External event select for injected group) /
bogdanm	0:9b334a45a8ff	2295	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2296	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2297	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2298
bogdanm	0:9b334a45a8ff	2299	#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /!< External Trigger Conversion mode for injected channels /
bogdanm	0:9b334a45a8ff	2300
bogdanm	0:9b334a45a8ff	2301	#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
bogdanm	0:9b334a45a8ff	2302	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2303	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2304	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2305
bogdanm	0:9b334a45a8ff	2306	#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /!< External Trigger Conversion mode for regular channels /
bogdanm	0:9b334a45a8ff	2307	#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /!< Start Conversion of injected channels /
bogdanm	0:9b334a45a8ff	2308	#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /!< Start Conversion of regular channels /
bogdanm	0:9b334a45a8ff	2309	#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /!< Temperature Sensor and VREFINT Enable /
bogdanm	0:9b334a45a8ff	2310
bogdanm	0:9b334a45a8ff	2311	/**************** Bit definition for ADC_SMPR1 register *****************/
bogdanm	0:9b334a45a8ff	2312	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!< SMP10[2:0] bits (Channel 10 Sample time selection) /
bogdanm	0:9b334a45a8ff	2313	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2314	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2315	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2316
bogdanm	0:9b334a45a8ff	2317	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!< SMP11[2:0] bits (Channel 11 Sample time selection) /
bogdanm	0:9b334a45a8ff	2318	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2319	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2320	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2321
bogdanm	0:9b334a45a8ff	2322	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!< SMP12[2:0] bits (Channel 12 Sample time selection) /
bogdanm	0:9b334a45a8ff	2323	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2324	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2325	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2326
bogdanm	0:9b334a45a8ff	2327	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!< SMP13[2:0] bits (Channel 13 Sample time selection) /
bogdanm	0:9b334a45a8ff	2328	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2329	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2330	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2331
bogdanm	0:9b334a45a8ff	2332	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!< SMP14[2:0] bits (Channel 14 Sample time selection) /
bogdanm	0:9b334a45a8ff	2333	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2334	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2335	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2336
bogdanm	0:9b334a45a8ff	2337	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!< SMP15[2:0] bits (Channel 15 Sample time selection) /
bogdanm	0:9b334a45a8ff	2338	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2339	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2340	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2341
bogdanm	0:9b334a45a8ff	2342	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!< SMP16[2:0] bits (Channel 16 Sample time selection) /
bogdanm	0:9b334a45a8ff	2343	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2344	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2345	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2346
bogdanm	0:9b334a45a8ff	2347	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!< SMP17[2:0] bits (Channel 17 Sample time selection) /
bogdanm	0:9b334a45a8ff	2348	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2349	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2350	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2351
bogdanm	0:9b334a45a8ff	2352	/**************** Bit definition for ADC_SMPR2 register *****************/
bogdanm	0:9b334a45a8ff	2353	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!< SMP0[2:0] bits (Channel 0 Sample time selection) /
bogdanm	0:9b334a45a8ff	2354	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2355	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2356	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2357
bogdanm	0:9b334a45a8ff	2358	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!< SMP1[2:0] bits (Channel 1 Sample time selection) /
bogdanm	0:9b334a45a8ff	2359	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2360	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2361	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2362
bogdanm	0:9b334a45a8ff	2363	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!< SMP2[2:0] bits (Channel 2 Sample time selection) /
bogdanm	0:9b334a45a8ff	2364	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2365	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2366	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2367
bogdanm	0:9b334a45a8ff	2368	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!< SMP3[2:0] bits (Channel 3 Sample time selection) /
bogdanm	0:9b334a45a8ff	2369	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2370	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2371	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2372
bogdanm	0:9b334a45a8ff	2373	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!< SMP4[2:0] bits (Channel 4 Sample time selection) /
bogdanm	0:9b334a45a8ff	2374	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2375	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2376	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2377
bogdanm	0:9b334a45a8ff	2378	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!< SMP5[2:0] bits (Channel 5 Sample time selection) /
bogdanm	0:9b334a45a8ff	2379	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2380	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2381	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2382
bogdanm	0:9b334a45a8ff	2383	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!< SMP6[2:0] bits (Channel 6 Sample time selection) /
bogdanm	0:9b334a45a8ff	2384	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2385	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2386	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2387
bogdanm	0:9b334a45a8ff	2388	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!< SMP7[2:0] bits (Channel 7 Sample time selection) /
bogdanm	0:9b334a45a8ff	2389	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2390	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2391	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2392
bogdanm	0:9b334a45a8ff	2393	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!< SMP8[2:0] bits (Channel 8 Sample time selection) /
bogdanm	0:9b334a45a8ff	2394	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2395	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2396	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2397
bogdanm	0:9b334a45a8ff	2398	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!< SMP9[2:0] bits (Channel 9 Sample time selection) /
bogdanm	0:9b334a45a8ff	2399	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2400	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2401	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2402
bogdanm	0:9b334a45a8ff	2403	/**************** Bit definition for ADC_JOFR1 register *****************/
bogdanm	0:9b334a45a8ff	2404	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 1 /
bogdanm	0:9b334a45a8ff	2405
bogdanm	0:9b334a45a8ff	2406	/**************** Bit definition for ADC_JOFR2 register *****************/
bogdanm	0:9b334a45a8ff	2407	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 2 /
bogdanm	0:9b334a45a8ff	2408
bogdanm	0:9b334a45a8ff	2409	/**************** Bit definition for ADC_JOFR3 register *****************/
bogdanm	0:9b334a45a8ff	2410	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 3 /
bogdanm	0:9b334a45a8ff	2411
bogdanm	0:9b334a45a8ff	2412	/**************** Bit definition for ADC_JOFR4 register *****************/
bogdanm	0:9b334a45a8ff	2413	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 4 /
bogdanm	0:9b334a45a8ff	2414
bogdanm	0:9b334a45a8ff	2415	/***************** Bit definition for ADC_HTR register ******************/
bogdanm	0:9b334a45a8ff	2416	#define ADC_HTR_HT ((uint32_t)0x00000FFF) /!< Analog watchdog high threshold /
bogdanm	0:9b334a45a8ff	2417
bogdanm	0:9b334a45a8ff	2418	/***************** Bit definition for ADC_LTR register ******************/
bogdanm	0:9b334a45a8ff	2419	#define ADC_LTR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
bogdanm	0:9b334a45a8ff	2420
bogdanm	0:9b334a45a8ff	2421	/***************** Bit definition for ADC_SQR1 register *****************/
bogdanm	0:9b334a45a8ff	2422	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!< SQ13[4:0] bits (13th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2423	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2424	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2425	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2426	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2427	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2428
bogdanm	0:9b334a45a8ff	2429	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!< SQ14[4:0] bits (14th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2430	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2431	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2432	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2433	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2434	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2435
bogdanm	0:9b334a45a8ff	2436	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!< SQ15[4:0] bits (15th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2437	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2438	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2439	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2440	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2441	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2442
bogdanm	0:9b334a45a8ff	2443	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!< SQ16[4:0] bits (16th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2444	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2445	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2446	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2447	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2448	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2449
bogdanm	0:9b334a45a8ff	2450	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!< L[3:0] bits (Regular channel sequence length) /
bogdanm	0:9b334a45a8ff	2451	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2452	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2453	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2454	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2455
bogdanm	0:9b334a45a8ff	2456	/***************** Bit definition for ADC_SQR2 register *****************/
bogdanm	0:9b334a45a8ff	2457	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!< SQ7[4:0] bits (7th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2458	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2459	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2460	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2461	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2462	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2463
bogdanm	0:9b334a45a8ff	2464	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!< SQ8[4:0] bits (8th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2465	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2466	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2467	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2468	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2469	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2470
bogdanm	0:9b334a45a8ff	2471	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!< SQ9[4:0] bits (9th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2472	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2473	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2474	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2475	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2476	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2477
bogdanm	0:9b334a45a8ff	2478	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!< SQ10[4:0] bits (10th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2479	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2480	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2481	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2482	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2483	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2484
bogdanm	0:9b334a45a8ff	2485	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!< SQ11[4:0] bits (11th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2486	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2487	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2488	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2489	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2490	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2491
bogdanm	0:9b334a45a8ff	2492	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!< SQ12[4:0] bits (12th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2493	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2494	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2495	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2496	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2497	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2498
bogdanm	0:9b334a45a8ff	2499	/***************** Bit definition for ADC_SQR3 register *****************/
bogdanm	0:9b334a45a8ff	2500	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!< SQ1[4:0] bits (1st conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2501	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2502	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2503	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2504	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2505	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2506
bogdanm	0:9b334a45a8ff	2507	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!< SQ2[4:0] bits (2nd conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2508	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2509	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2510	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2511	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2512	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2513
bogdanm	0:9b334a45a8ff	2514	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!< SQ3[4:0] bits (3rd conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2515	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2516	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2517	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2518	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2519	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2520
bogdanm	0:9b334a45a8ff	2521	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!< SQ4[4:0] bits (4th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2522	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2523	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2524	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2525	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2526	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2527
bogdanm	0:9b334a45a8ff	2528	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!< SQ5[4:0] bits (5th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2529	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2530	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2531	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2532	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2533	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2534
bogdanm	0:9b334a45a8ff	2535	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!< SQ6[4:0] bits (6th conversion in regular sequence) /
bogdanm	0:9b334a45a8ff	2536	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2537	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2538	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2539	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2540	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2541
bogdanm	0:9b334a45a8ff	2542	/***************** Bit definition for ADC_JSQR register *****************/
bogdanm	0:9b334a45a8ff	2543	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!< JSQ1[4:0] bits (1st conversion in injected sequence) /
bogdanm	0:9b334a45a8ff	2544	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2545	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2546	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2547	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2548	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2549
bogdanm	0:9b334a45a8ff	2550	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!< JSQ2[4:0] bits (2nd conversion in injected sequence) /
bogdanm	0:9b334a45a8ff	2551	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2552	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2553	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2554	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2555	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2556
bogdanm	0:9b334a45a8ff	2557	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!< JSQ3[4:0] bits (3rd conversion in injected sequence) /
bogdanm	0:9b334a45a8ff	2558	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2559	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2560	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2561	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2562	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2563
bogdanm	0:9b334a45a8ff	2564	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!< JSQ4[4:0] bits (4th conversion in injected sequence) /
bogdanm	0:9b334a45a8ff	2565	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2566	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2567	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2568	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2569	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	2570
bogdanm	0:9b334a45a8ff	2571	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!< JL[1:0] bits (Injected Sequence length) /
bogdanm	0:9b334a45a8ff	2572	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2573	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2574
bogdanm	0:9b334a45a8ff	2575	/***************** Bit definition for ADC_JDR1 register *****************/
bogdanm	0:9b334a45a8ff	2576	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
bogdanm	0:9b334a45a8ff	2577
bogdanm	0:9b334a45a8ff	2578	/***************** Bit definition for ADC_JDR2 register *****************/
bogdanm	0:9b334a45a8ff	2579	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
bogdanm	0:9b334a45a8ff	2580
bogdanm	0:9b334a45a8ff	2581	/***************** Bit definition for ADC_JDR3 register *****************/
bogdanm	0:9b334a45a8ff	2582	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
bogdanm	0:9b334a45a8ff	2583
bogdanm	0:9b334a45a8ff	2584	/***************** Bit definition for ADC_JDR4 register *****************/
bogdanm	0:9b334a45a8ff	2585	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
bogdanm	0:9b334a45a8ff	2586
bogdanm	0:9b334a45a8ff	2587	/****************** Bit definition for ADC_DR register ******************/
bogdanm	0:9b334a45a8ff	2588	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
bogdanm	0:9b334a45a8ff	2589	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2590	/* */
bogdanm	0:9b334a45a8ff	2591	/* Digital to Analog Converter */
bogdanm	0:9b334a45a8ff	2592	/* */
bogdanm	0:9b334a45a8ff	2593	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2594
bogdanm	0:9b334a45a8ff	2595	/****************** Bit definition for DAC_CR register ******************/
bogdanm	0:9b334a45a8ff	2596	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!< DAC channel1 enable /
bogdanm	0:9b334a45a8ff	2597	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!< DAC channel1 output buffer disable /
bogdanm	0:9b334a45a8ff	2598	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!< DAC channel1 Trigger enable /
bogdanm	0:9b334a45a8ff	2599
bogdanm	0:9b334a45a8ff	2600	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
bogdanm	0:9b334a45a8ff	2601	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2602	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2603	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2604
bogdanm	0:9b334a45a8ff	2605	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
bogdanm	0:9b334a45a8ff	2606	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2607	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2608
bogdanm	0:9b334a45a8ff	2609	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
bogdanm	0:9b334a45a8ff	2610	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2611	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2612	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2613	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2614
bogdanm	0:9b334a45a8ff	2615	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!< DAC channel1 DMA enable /
bogdanm	0:9b334a45a8ff	2616	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!< DAC channel2 enable /
bogdanm	0:9b334a45a8ff	2617	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!< DAC channel2 output buffer disable /
bogdanm	0:9b334a45a8ff	2618	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!< DAC channel2 Trigger enable /
bogdanm	0:9b334a45a8ff	2619
bogdanm	0:9b334a45a8ff	2620	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
bogdanm	0:9b334a45a8ff	2621	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2622	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2623	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2624
bogdanm	0:9b334a45a8ff	2625	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
bogdanm	0:9b334a45a8ff	2626	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2627	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2628
bogdanm	0:9b334a45a8ff	2629	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
bogdanm	0:9b334a45a8ff	2630	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2631	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2632	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2633	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2634
bogdanm	0:9b334a45a8ff	2635	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!< DAC channel2 DMA enabled /
bogdanm	0:9b334a45a8ff	2636
bogdanm	0:9b334a45a8ff	2637	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /!< DAC channel1 DMA underrun interrupt enable /
bogdanm	0:9b334a45a8ff	2638	#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /!< DAC channel2 DMA underrun interrupt enable /
bogdanm	0:9b334a45a8ff	2639
bogdanm	0:9b334a45a8ff	2640	/*************** Bit definition for DAC_SWTRIGR register ****************/
bogdanm	0:9b334a45a8ff	2641	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!< DAC channel1 software trigger /
bogdanm	0:9b334a45a8ff	2642	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /!< DAC channel2 software trigger /
bogdanm	0:9b334a45a8ff	2643
bogdanm	0:9b334a45a8ff	2644	/*************** Bit definition for DAC_DHR12R1 register ****************/
bogdanm	0:9b334a45a8ff	2645	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	2646
bogdanm	0:9b334a45a8ff	2647	/*************** Bit definition for DAC_DHR12L1 register ****************/
bogdanm	0:9b334a45a8ff	2648	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	2649
bogdanm	0:9b334a45a8ff	2650	/**************** Bit definition for DAC_DHR8R1 register ****************/
bogdanm	0:9b334a45a8ff	2651	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	2652
bogdanm	0:9b334a45a8ff	2653	/*************** Bit definition for DAC_DHR12R2 register ****************/
bogdanm	0:9b334a45a8ff	2654	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /!< DAC channel2 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	2655
bogdanm	0:9b334a45a8ff	2656	/*************** Bit definition for DAC_DHR12L2 register ****************/
bogdanm	0:9b334a45a8ff	2657	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /!< DAC channel2 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	2658
bogdanm	0:9b334a45a8ff	2659	/**************** Bit definition for DAC_DHR8R2 register ****************/
bogdanm	0:9b334a45a8ff	2660	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /!< DAC channel2 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	2661
bogdanm	0:9b334a45a8ff	2662	/*************** Bit definition for DAC_DHR12RD register ****************/
bogdanm	0:9b334a45a8ff	2663	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	2664	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!< DAC channel2 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	2665
bogdanm	0:9b334a45a8ff	2666	/*************** Bit definition for DAC_DHR12LD register ****************/
bogdanm	0:9b334a45a8ff	2667	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	2668	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!< DAC channel2 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	2669
bogdanm	0:9b334a45a8ff	2670	/**************** Bit definition for DAC_DHR8RD register ****************/
bogdanm	0:9b334a45a8ff	2671	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	2672	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /!< DAC channel2 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	2673
bogdanm	0:9b334a45a8ff	2674	/***************** Bit definition for DAC_DOR1 register *****************/
bogdanm	0:9b334a45a8ff	2675	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!< DAC channel1 data output /
bogdanm	0:9b334a45a8ff	2676
bogdanm	0:9b334a45a8ff	2677	/***************** Bit definition for DAC_DOR2 register *****************/
bogdanm	0:9b334a45a8ff	2678	#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /!< DAC channel2 data output /
bogdanm	0:9b334a45a8ff	2679
bogdanm	0:9b334a45a8ff	2680	/****************** Bit definition for DAC_SR register ******************/
bogdanm	0:9b334a45a8ff	2681	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!< DAC channel1 DMA underrun flag /
bogdanm	0:9b334a45a8ff	2682	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!< DAC channel2 DMA underrun flag /
bogdanm	0:9b334a45a8ff	2683
bogdanm	0:9b334a45a8ff	2684	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2685	/* */
bogdanm	0:9b334a45a8ff	2686	/* CEC */
bogdanm	0:9b334a45a8ff	2687	/* */
bogdanm	0:9b334a45a8ff	2688	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2689	/****************** Bit definition for CEC_CFGR register ****************/
bogdanm	0:9b334a45a8ff	2690	#define CEC_CFGR_PE ((uint32_t)0x00000001) /!< Peripheral Enable /
bogdanm	0:9b334a45a8ff	2691	#define CEC_CFGR_IE ((uint32_t)0x00000002) /!< Interrupt Enable /
bogdanm	0:9b334a45a8ff	2692	#define CEC_CFGR_BTEM ((uint32_t)0x00000004) /!< Bit Timing Error Mode /
bogdanm	0:9b334a45a8ff	2693	#define CEC_CFGR_BPEM ((uint32_t)0x00000008) /!< Bit Period Error Mode /
bogdanm	0:9b334a45a8ff	2694
bogdanm	0:9b334a45a8ff	2695	/****************** Bit definition for CEC_OAR register ****************/
bogdanm	0:9b334a45a8ff	2696	#define CEC_OAR_OA ((uint32_t)0x0000000F) /!< OA[3:0]: Own Address /
bogdanm	0:9b334a45a8ff	2697	#define CEC_OAR_OA_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	2698	#define CEC_OAR_OA_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	2699	#define CEC_OAR_OA_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	2700	#define CEC_OAR_OA_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	2701
bogdanm	0:9b334a45a8ff	2702	/****************** Bit definition for CEC_PRES register ****************/
bogdanm	0:9b334a45a8ff	2703	#define CEC_PRES_PRES ((uint32_t)0x00003FFF) /!< Prescaler Counter Value /
bogdanm	0:9b334a45a8ff	2704
bogdanm	0:9b334a45a8ff	2705	/****************** Bit definition for CEC_ESR register ****************/
bogdanm	0:9b334a45a8ff	2706	#define CEC_ESR_BTE ((uint32_t)0x00000001) /!< Bit Timing Error /
bogdanm	0:9b334a45a8ff	2707	#define CEC_ESR_BPE ((uint32_t)0x00000002) /!< Bit Period Error /
bogdanm	0:9b334a45a8ff	2708	#define CEC_ESR_RBTFE ((uint32_t)0x00000004) /!< Rx Block Transfer Finished Error /
bogdanm	0:9b334a45a8ff	2709	#define CEC_ESR_SBE ((uint32_t)0x00000008) /!< Start Bit Error /
bogdanm	0:9b334a45a8ff	2710	#define CEC_ESR_ACKE ((uint32_t)0x00000010) /!< Block Acknowledge Error /
bogdanm	0:9b334a45a8ff	2711	#define CEC_ESR_LINE ((uint32_t)0x00000020) /!< Line Error /
bogdanm	0:9b334a45a8ff	2712	#define CEC_ESR_TBTFE ((uint32_t)0x00000040) /!< Tx Block Transfer Finished Error /
bogdanm	0:9b334a45a8ff	2713
bogdanm	0:9b334a45a8ff	2714	/****************** Bit definition for CEC_CSR register ****************/
bogdanm	0:9b334a45a8ff	2715	#define CEC_CSR_TSOM ((uint32_t)0x00000001) /!< Tx Start Of Message /
bogdanm	0:9b334a45a8ff	2716	#define CEC_CSR_TEOM ((uint32_t)0x00000002) /!< Tx End Of Message /
bogdanm	0:9b334a45a8ff	2717	#define CEC_CSR_TERR ((uint32_t)0x00000004) /!< Tx Error /
bogdanm	0:9b334a45a8ff	2718	#define CEC_CSR_TBTRF ((uint32_t)0x00000008) /!< Tx Byte Transfer Request or Block Transfer Finished /
bogdanm	0:9b334a45a8ff	2719	#define CEC_CSR_RSOM ((uint32_t)0x00000010) /!< Rx Start Of Message /
bogdanm	0:9b334a45a8ff	2720	#define CEC_CSR_REOM ((uint32_t)0x00000020) /!< Rx End Of Message /
bogdanm	0:9b334a45a8ff	2721	#define CEC_CSR_RERR ((uint32_t)0x00000040) /!< Rx Error /
bogdanm	0:9b334a45a8ff	2722	#define CEC_CSR_RBTF ((uint32_t)0x00000080) /!< Rx Block Transfer Finished /
bogdanm	0:9b334a45a8ff	2723
bogdanm	0:9b334a45a8ff	2724	/****************** Bit definition for CEC_TXD register ****************/
bogdanm	0:9b334a45a8ff	2725	#define CEC_TXD_TXD ((uint32_t)0x000000FF) /!< Tx Data register /
bogdanm	0:9b334a45a8ff	2726
bogdanm	0:9b334a45a8ff	2727	/****************** Bit definition for CEC_RXD register ****************/
bogdanm	0:9b334a45a8ff	2728	#define CEC_RXD_RXD ((uint32_t)0x000000FF) /!< Rx Data register /
bogdanm	0:9b334a45a8ff	2729
bogdanm	0:9b334a45a8ff	2730	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	2731	/* */
bogdanm	0:9b334a45a8ff	2732	/* Timers (TIM) */
bogdanm	0:9b334a45a8ff	2733	/* */
bogdanm	0:9b334a45a8ff	2734	/*****************************************************************************/
bogdanm	0:9b334a45a8ff	2735	/***************** Bit definition for TIM_CR1 register *****************/
bogdanm	0:9b334a45a8ff	2736	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
bogdanm	0:9b334a45a8ff	2737	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
bogdanm	0:9b334a45a8ff	2738	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
bogdanm	0:9b334a45a8ff	2739	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
bogdanm	0:9b334a45a8ff	2740	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
bogdanm	0:9b334a45a8ff	2741
bogdanm	0:9b334a45a8ff	2742	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
bogdanm	0:9b334a45a8ff	2743	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2744	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2745
bogdanm	0:9b334a45a8ff	2746	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
bogdanm	0:9b334a45a8ff	2747
bogdanm	0:9b334a45a8ff	2748	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
bogdanm	0:9b334a45a8ff	2749	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2750	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2751
bogdanm	0:9b334a45a8ff	2752	/***************** Bit definition for TIM_CR2 register *****************/
bogdanm	0:9b334a45a8ff	2753	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
bogdanm	0:9b334a45a8ff	2754	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
bogdanm	0:9b334a45a8ff	2755	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
bogdanm	0:9b334a45a8ff	2756
bogdanm	0:9b334a45a8ff	2757	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
bogdanm	0:9b334a45a8ff	2758	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2759	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2760	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2761
bogdanm	0:9b334a45a8ff	2762	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
bogdanm	0:9b334a45a8ff	2763	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
bogdanm	0:9b334a45a8ff	2764	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
bogdanm	0:9b334a45a8ff	2765	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
bogdanm	0:9b334a45a8ff	2766	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
bogdanm	0:9b334a45a8ff	2767	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
bogdanm	0:9b334a45a8ff	2768	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
bogdanm	0:9b334a45a8ff	2769	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
bogdanm	0:9b334a45a8ff	2770
bogdanm	0:9b334a45a8ff	2771	/***************** Bit definition for TIM_SMCR register ****************/
bogdanm	0:9b334a45a8ff	2772	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
bogdanm	0:9b334a45a8ff	2773	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2774	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2775	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2776
bogdanm	0:9b334a45a8ff	2777	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
bogdanm	0:9b334a45a8ff	2778
bogdanm	0:9b334a45a8ff	2779	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
bogdanm	0:9b334a45a8ff	2780	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2781	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2782	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2783
bogdanm	0:9b334a45a8ff	2784	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
bogdanm	0:9b334a45a8ff	2785
bogdanm	0:9b334a45a8ff	2786	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
bogdanm	0:9b334a45a8ff	2787	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2788	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2789	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2790	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2791
bogdanm	0:9b334a45a8ff	2792	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
bogdanm	0:9b334a45a8ff	2793	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2794	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2795
bogdanm	0:9b334a45a8ff	2796	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
bogdanm	0:9b334a45a8ff	2797	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
bogdanm	0:9b334a45a8ff	2798
bogdanm	0:9b334a45a8ff	2799	/***************** Bit definition for TIM_DIER register ****************/
bogdanm	0:9b334a45a8ff	2800	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
bogdanm	0:9b334a45a8ff	2801	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
bogdanm	0:9b334a45a8ff	2802	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
bogdanm	0:9b334a45a8ff	2803	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
bogdanm	0:9b334a45a8ff	2804	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
bogdanm	0:9b334a45a8ff	2805	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
bogdanm	0:9b334a45a8ff	2806	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
bogdanm	0:9b334a45a8ff	2807	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
bogdanm	0:9b334a45a8ff	2808	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
bogdanm	0:9b334a45a8ff	2809	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
bogdanm	0:9b334a45a8ff	2810	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
bogdanm	0:9b334a45a8ff	2811	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
bogdanm	0:9b334a45a8ff	2812	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
bogdanm	0:9b334a45a8ff	2813	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
bogdanm	0:9b334a45a8ff	2814	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
bogdanm	0:9b334a45a8ff	2815
bogdanm	0:9b334a45a8ff	2816	/****************** Bit definition for TIM_SR register *****************/
bogdanm	0:9b334a45a8ff	2817	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
bogdanm	0:9b334a45a8ff	2818	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
bogdanm	0:9b334a45a8ff	2819	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
bogdanm	0:9b334a45a8ff	2820	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
bogdanm	0:9b334a45a8ff	2821	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
bogdanm	0:9b334a45a8ff	2822	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
bogdanm	0:9b334a45a8ff	2823	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
bogdanm	0:9b334a45a8ff	2824	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
bogdanm	0:9b334a45a8ff	2825	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
bogdanm	0:9b334a45a8ff	2826	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
bogdanm	0:9b334a45a8ff	2827	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
bogdanm	0:9b334a45a8ff	2828	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
bogdanm	0:9b334a45a8ff	2829
bogdanm	0:9b334a45a8ff	2830	/***************** Bit definition for TIM_EGR register *****************/
bogdanm	0:9b334a45a8ff	2831	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
bogdanm	0:9b334a45a8ff	2832	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
bogdanm	0:9b334a45a8ff	2833	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
bogdanm	0:9b334a45a8ff	2834	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
bogdanm	0:9b334a45a8ff	2835	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
bogdanm	0:9b334a45a8ff	2836	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
bogdanm	0:9b334a45a8ff	2837	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
bogdanm	0:9b334a45a8ff	2838	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
bogdanm	0:9b334a45a8ff	2839
bogdanm	0:9b334a45a8ff	2840	/**************** Bit definition for TIM_CCMR1 register ****************/
bogdanm	0:9b334a45a8ff	2841	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
bogdanm	0:9b334a45a8ff	2842	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2843	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2844
bogdanm	0:9b334a45a8ff	2845	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
bogdanm	0:9b334a45a8ff	2846	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
bogdanm	0:9b334a45a8ff	2847
bogdanm	0:9b334a45a8ff	2848	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
bogdanm	0:9b334a45a8ff	2849	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2850	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2851	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2852
bogdanm	0:9b334a45a8ff	2853	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
bogdanm	0:9b334a45a8ff	2854
bogdanm	0:9b334a45a8ff	2855	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
bogdanm	0:9b334a45a8ff	2856	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2857	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2858
bogdanm	0:9b334a45a8ff	2859	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
bogdanm	0:9b334a45a8ff	2860	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
bogdanm	0:9b334a45a8ff	2861
bogdanm	0:9b334a45a8ff	2862	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
bogdanm	0:9b334a45a8ff	2863	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2864	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2865	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2866
bogdanm	0:9b334a45a8ff	2867	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
bogdanm	0:9b334a45a8ff	2868
bogdanm	0:9b334a45a8ff	2869	/---------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	2870
bogdanm	0:9b334a45a8ff	2871	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
bogdanm	0:9b334a45a8ff	2872	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2873	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2874
bogdanm	0:9b334a45a8ff	2875	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
bogdanm	0:9b334a45a8ff	2876	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2877	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2878	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2879	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2880
bogdanm	0:9b334a45a8ff	2881	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
bogdanm	0:9b334a45a8ff	2882	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2883	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2884
bogdanm	0:9b334a45a8ff	2885	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
bogdanm	0:9b334a45a8ff	2886	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2887	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2888	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2889	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2890
bogdanm	0:9b334a45a8ff	2891	/**************** Bit definition for TIM_CCMR2 register ****************/
bogdanm	0:9b334a45a8ff	2892	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
bogdanm	0:9b334a45a8ff	2893	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2894	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2895
bogdanm	0:9b334a45a8ff	2896	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
bogdanm	0:9b334a45a8ff	2897	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
bogdanm	0:9b334a45a8ff	2898
bogdanm	0:9b334a45a8ff	2899	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
bogdanm	0:9b334a45a8ff	2900	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2901	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2902	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2903
bogdanm	0:9b334a45a8ff	2904	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
bogdanm	0:9b334a45a8ff	2905
bogdanm	0:9b334a45a8ff	2906	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
bogdanm	0:9b334a45a8ff	2907	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2908	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2909
bogdanm	0:9b334a45a8ff	2910	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
bogdanm	0:9b334a45a8ff	2911	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
bogdanm	0:9b334a45a8ff	2912
bogdanm	0:9b334a45a8ff	2913	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
bogdanm	0:9b334a45a8ff	2914	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2915	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2916	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2917
bogdanm	0:9b334a45a8ff	2918	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
bogdanm	0:9b334a45a8ff	2919
bogdanm	0:9b334a45a8ff	2920	/---------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	2921
bogdanm	0:9b334a45a8ff	2922	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
bogdanm	0:9b334a45a8ff	2923	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2924	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2925
bogdanm	0:9b334a45a8ff	2926	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
bogdanm	0:9b334a45a8ff	2927	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2928	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2929	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2930	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2931
bogdanm	0:9b334a45a8ff	2932	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
bogdanm	0:9b334a45a8ff	2933	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2934	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2935
bogdanm	0:9b334a45a8ff	2936	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
bogdanm	0:9b334a45a8ff	2937	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2938	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2939	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2940	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2941
bogdanm	0:9b334a45a8ff	2942	/***************** Bit definition for TIM_CCER register ****************/
bogdanm	0:9b334a45a8ff	2943	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
bogdanm	0:9b334a45a8ff	2944	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
bogdanm	0:9b334a45a8ff	2945	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
bogdanm	0:9b334a45a8ff	2946	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	2947	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
bogdanm	0:9b334a45a8ff	2948	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
bogdanm	0:9b334a45a8ff	2949	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
bogdanm	0:9b334a45a8ff	2950	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	2951	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
bogdanm	0:9b334a45a8ff	2952	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
bogdanm	0:9b334a45a8ff	2953	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
bogdanm	0:9b334a45a8ff	2954	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	2955	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
bogdanm	0:9b334a45a8ff	2956	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
bogdanm	0:9b334a45a8ff	2957	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	2958
bogdanm	0:9b334a45a8ff	2959	/***************** Bit definition for TIM_CNT register *****************/
bogdanm	0:9b334a45a8ff	2960	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
bogdanm	0:9b334a45a8ff	2961
bogdanm	0:9b334a45a8ff	2962	/***************** Bit definition for TIM_PSC register *****************/
bogdanm	0:9b334a45a8ff	2963	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
bogdanm	0:9b334a45a8ff	2964
bogdanm	0:9b334a45a8ff	2965	/***************** Bit definition for TIM_ARR register *****************/
bogdanm	0:9b334a45a8ff	2966	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
bogdanm	0:9b334a45a8ff	2967
bogdanm	0:9b334a45a8ff	2968	/***************** Bit definition for TIM_RCR register *****************/
bogdanm	0:9b334a45a8ff	2969	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
bogdanm	0:9b334a45a8ff	2970
bogdanm	0:9b334a45a8ff	2971	/***************** Bit definition for TIM_CCR1 register ****************/
bogdanm	0:9b334a45a8ff	2972	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
bogdanm	0:9b334a45a8ff	2973
bogdanm	0:9b334a45a8ff	2974	/***************** Bit definition for TIM_CCR2 register ****************/
bogdanm	0:9b334a45a8ff	2975	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
bogdanm	0:9b334a45a8ff	2976
bogdanm	0:9b334a45a8ff	2977	/***************** Bit definition for TIM_CCR3 register ****************/
bogdanm	0:9b334a45a8ff	2978	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
bogdanm	0:9b334a45a8ff	2979
bogdanm	0:9b334a45a8ff	2980	/***************** Bit definition for TIM_CCR4 register ****************/
bogdanm	0:9b334a45a8ff	2981	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
bogdanm	0:9b334a45a8ff	2982
bogdanm	0:9b334a45a8ff	2983	/***************** Bit definition for TIM_BDTR register ****************/
bogdanm	0:9b334a45a8ff	2984	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
bogdanm	0:9b334a45a8ff	2985	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2986	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2987	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	2988	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	2989	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	2990	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	2991	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	2992	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	2993
bogdanm	0:9b334a45a8ff	2994	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
bogdanm	0:9b334a45a8ff	2995	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	2996	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	2997
bogdanm	0:9b334a45a8ff	2998	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
bogdanm	0:9b334a45a8ff	2999	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
bogdanm	0:9b334a45a8ff	3000	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
bogdanm	0:9b334a45a8ff	3001	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
bogdanm	0:9b334a45a8ff	3002	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
bogdanm	0:9b334a45a8ff	3003	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
bogdanm	0:9b334a45a8ff	3004
bogdanm	0:9b334a45a8ff	3005	/***************** Bit definition for TIM_DCR register *****************/
bogdanm	0:9b334a45a8ff	3006	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
bogdanm	0:9b334a45a8ff	3007	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	3008	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	3009	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	3010	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	3011	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	3012
bogdanm	0:9b334a45a8ff	3013	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
bogdanm	0:9b334a45a8ff	3014	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	3015	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	3016	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	3017	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	3018	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	3019
bogdanm	0:9b334a45a8ff	3020	/***************** Bit definition for TIM_DMAR register ****************/
bogdanm	0:9b334a45a8ff	3021	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
bogdanm	0:9b334a45a8ff	3022
bogdanm	0:9b334a45a8ff	3023	/***************** Bit definition for TIM_OR register ******************/
bogdanm	0:9b334a45a8ff	3024
bogdanm	0:9b334a45a8ff	3025	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3026	/* */
bogdanm	0:9b334a45a8ff	3027	/* Real-Time Clock */
bogdanm	0:9b334a45a8ff	3028	/* */
bogdanm	0:9b334a45a8ff	3029	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3030
bogdanm	0:9b334a45a8ff	3031	/***************** Bit definition for RTC_CRH register ******************/
bogdanm	0:9b334a45a8ff	3032	#define RTC_CRH_SECIE ((uint32_t)0x00000001) /!< Second Interrupt Enable /
bogdanm	0:9b334a45a8ff	3033	#define RTC_CRH_ALRIE ((uint32_t)0x00000002) /!< Alarm Interrupt Enable /
bogdanm	0:9b334a45a8ff	3034	#define RTC_CRH_OWIE ((uint32_t)0x00000004) /!< OverfloW Interrupt Enable /
bogdanm	0:9b334a45a8ff	3035
bogdanm	0:9b334a45a8ff	3036	/***************** Bit definition for RTC_CRL register ******************/
bogdanm	0:9b334a45a8ff	3037	#define RTC_CRL_SECF ((uint32_t)0x00000001) /!< Second Flag /
bogdanm	0:9b334a45a8ff	3038	#define RTC_CRL_ALRF ((uint32_t)0x00000002) /!< Alarm Flag /
bogdanm	0:9b334a45a8ff	3039	#define RTC_CRL_OWF ((uint32_t)0x00000004) /!< OverfloW Flag /
bogdanm	0:9b334a45a8ff	3040	#define RTC_CRL_RSF ((uint32_t)0x00000008) /!< Registers Synchronized Flag /
bogdanm	0:9b334a45a8ff	3041	#define RTC_CRL_CNF ((uint32_t)0x00000010) /!< Configuration Flag /
bogdanm	0:9b334a45a8ff	3042	#define RTC_CRL_RTOFF ((uint32_t)0x00000020) /!< RTC operation OFF /
bogdanm	0:9b334a45a8ff	3043
bogdanm	0:9b334a45a8ff	3044	/***************** Bit definition for RTC_PRLH register *****************/
bogdanm	0:9b334a45a8ff	3045	#define RTC_PRLH_PRL ((uint32_t)0x0000000F) /!< RTC Prescaler Reload Value High /
bogdanm	0:9b334a45a8ff	3046
bogdanm	0:9b334a45a8ff	3047	/***************** Bit definition for RTC_PRLL register *****************/
bogdanm	0:9b334a45a8ff	3048	#define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /!< RTC Prescaler Reload Value Low /
bogdanm	0:9b334a45a8ff	3049
bogdanm	0:9b334a45a8ff	3050	/***************** Bit definition for RTC_DIVH register *****************/
bogdanm	0:9b334a45a8ff	3051	#define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /!< RTC Clock Divider High /
bogdanm	0:9b334a45a8ff	3052
bogdanm	0:9b334a45a8ff	3053	/***************** Bit definition for RTC_DIVL register *****************/
bogdanm	0:9b334a45a8ff	3054	#define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /!< RTC Clock Divider Low /
bogdanm	0:9b334a45a8ff	3055
bogdanm	0:9b334a45a8ff	3056	/***************** Bit definition for RTC_CNTH register *****************/
bogdanm	0:9b334a45a8ff	3057	#define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter High /
bogdanm	0:9b334a45a8ff	3058
bogdanm	0:9b334a45a8ff	3059	/***************** Bit definition for RTC_CNTL register *****************/
bogdanm	0:9b334a45a8ff	3060	#define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter Low /
bogdanm	0:9b334a45a8ff	3061
bogdanm	0:9b334a45a8ff	3062	/***************** Bit definition for RTC_ALRH register *****************/
bogdanm	0:9b334a45a8ff	3063	#define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm High /
bogdanm	0:9b334a45a8ff	3064
bogdanm	0:9b334a45a8ff	3065	/***************** Bit definition for RTC_ALRL register *****************/
bogdanm	0:9b334a45a8ff	3066	#define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm Low /
bogdanm	0:9b334a45a8ff	3067
bogdanm	0:9b334a45a8ff	3068	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3069	/* */
bogdanm	0:9b334a45a8ff	3070	/* Independent WATCHDOG (IWDG) */
bogdanm	0:9b334a45a8ff	3071	/* */
bogdanm	0:9b334a45a8ff	3072	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3073
bogdanm	0:9b334a45a8ff	3074	/***************** Bit definition for IWDG_KR register ******************/
bogdanm	0:9b334a45a8ff	3075	#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /!< Key value (write only, read 0000h) /
bogdanm	0:9b334a45a8ff	3076
bogdanm	0:9b334a45a8ff	3077	/***************** Bit definition for IWDG_PR register ******************/
bogdanm	0:9b334a45a8ff	3078	#define IWDG_PR_PR ((uint32_t)0x00000007) /!< PR[2:0] (Prescaler divider) /
bogdanm	0:9b334a45a8ff	3079	#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3080	#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3081	#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3082
bogdanm	0:9b334a45a8ff	3083	/***************** Bit definition for IWDG_RLR register *****************/
bogdanm	0:9b334a45a8ff	3084	#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /!< Watchdog counter reload value /
bogdanm	0:9b334a45a8ff	3085
bogdanm	0:9b334a45a8ff	3086	/***************** Bit definition for IWDG_SR register ******************/
bogdanm	0:9b334a45a8ff	3087	#define IWDG_SR_PVU ((uint32_t)0x00000001) /!< Watchdog prescaler value update /
bogdanm	0:9b334a45a8ff	3088	#define IWDG_SR_RVU ((uint32_t)0x00000002) /!< Watchdog counter reload value update /
bogdanm	0:9b334a45a8ff	3089
bogdanm	0:9b334a45a8ff	3090	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3091	/* */
bogdanm	0:9b334a45a8ff	3092	/* Window WATCHDOG */
bogdanm	0:9b334a45a8ff	3093	/* */
bogdanm	0:9b334a45a8ff	3094	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3095
bogdanm	0:9b334a45a8ff	3096	/***************** Bit definition for WWDG_CR register ******************/
bogdanm	0:9b334a45a8ff	3097	#define WWDG_CR_T ((uint32_t)0x0000007F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
bogdanm	0:9b334a45a8ff	3098	#define WWDG_CR_T0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3099	#define WWDG_CR_T1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3100	#define WWDG_CR_T2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3101	#define WWDG_CR_T3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3102	#define WWDG_CR_T4 ((uint32_t)0x00000010) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	3103	#define WWDG_CR_T5 ((uint32_t)0x00000020) /!< Bit 5 /
bogdanm	0:9b334a45a8ff	3104	#define WWDG_CR_T6 ((uint32_t)0x00000040) /!< Bit 6 /
bogdanm	0:9b334a45a8ff	3105
bogdanm	0:9b334a45a8ff	3106	#define WWDG_CR_WDGA ((uint32_t)0x00000080) /!< Activation bit /
bogdanm	0:9b334a45a8ff	3107
bogdanm	0:9b334a45a8ff	3108	/***************** Bit definition for WWDG_CFR register *****************/
bogdanm	0:9b334a45a8ff	3109	#define WWDG_CFR_W ((uint32_t)0x0000007F) /!< W[6:0] bits (7-bit window value) /
bogdanm	0:9b334a45a8ff	3110	#define WWDG_CFR_W0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3111	#define WWDG_CFR_W1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3112	#define WWDG_CFR_W2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3113	#define WWDG_CFR_W3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3114	#define WWDG_CFR_W4 ((uint32_t)0x00000010) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	3115	#define WWDG_CFR_W5 ((uint32_t)0x00000020) /!< Bit 5 /
bogdanm	0:9b334a45a8ff	3116	#define WWDG_CFR_W6 ((uint32_t)0x00000040) /!< Bit 6 /
bogdanm	0:9b334a45a8ff	3117
bogdanm	0:9b334a45a8ff	3118	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /!< WDGTB[1:0] bits (Timer Base) /
bogdanm	0:9b334a45a8ff	3119	#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3120	#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3121
bogdanm	0:9b334a45a8ff	3122	#define WWDG_CFR_EWI ((uint32_t)0x00000200) /!< Early Wakeup Interrupt /
bogdanm	0:9b334a45a8ff	3123
bogdanm	0:9b334a45a8ff	3124	/***************** Bit definition for WWDG_SR register ******************/
bogdanm	0:9b334a45a8ff	3125	#define WWDG_SR_EWIF ((uint32_t)0x00000001) /!< Early Wakeup Interrupt Flag /
bogdanm	0:9b334a45a8ff	3126
bogdanm	0:9b334a45a8ff	3127
bogdanm	0:9b334a45a8ff	3128	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3129	/* */
bogdanm	0:9b334a45a8ff	3130	/* SD host Interface */
bogdanm	0:9b334a45a8ff	3131	/* */
bogdanm	0:9b334a45a8ff	3132	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3133
bogdanm	0:9b334a45a8ff	3134	/**************** Bit definition for SDIO_POWER register ****************/
bogdanm	0:9b334a45a8ff	3135	#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /!< PWRCTRL[1:0] bits (Power supply control bits) /
bogdanm	0:9b334a45a8ff	3136	#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3137	#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3138
bogdanm	0:9b334a45a8ff	3139	/**************** Bit definition for SDIO_CLKCR register ****************/
bogdanm	0:9b334a45a8ff	3140	#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /!< Clock divide factor /
bogdanm	0:9b334a45a8ff	3141	#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /!< Clock enable bit /
bogdanm	0:9b334a45a8ff	3142	#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /!< Power saving configuration bit /
bogdanm	0:9b334a45a8ff	3143	#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /!< Clock divider bypass enable bit /
bogdanm	0:9b334a45a8ff	3144
bogdanm	0:9b334a45a8ff	3145	#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
bogdanm	0:9b334a45a8ff	3146	#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3147	#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3148
bogdanm	0:9b334a45a8ff	3149	#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /!< SDIO_CK dephasing selection bit /
bogdanm	0:9b334a45a8ff	3150	#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /!< HW Flow Control enable /
bogdanm	0:9b334a45a8ff	3151
bogdanm	0:9b334a45a8ff	3152	/***************** Bit definition for SDIO_ARG register *****************/
bogdanm	0:9b334a45a8ff	3153	#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!< Command argument /
bogdanm	0:9b334a45a8ff	3154
bogdanm	0:9b334a45a8ff	3155	/***************** Bit definition for SDIO_CMD register *****************/
bogdanm	0:9b334a45a8ff	3156	#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /!< Command Index /
bogdanm	0:9b334a45a8ff	3157
bogdanm	0:9b334a45a8ff	3158	#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /!< WAITRESP[1:0] bits (Wait for response bits) /
bogdanm	0:9b334a45a8ff	3159	#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3160	#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3161
bogdanm	0:9b334a45a8ff	3162	#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /!< CPSM Waits for Interrupt Request /
bogdanm	0:9b334a45a8ff	3163	#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
bogdanm	0:9b334a45a8ff	3164	#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /!< Command path state machine (CPSM) Enable bit /
bogdanm	0:9b334a45a8ff	3165	#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /!< SD I/O suspend command /
bogdanm	0:9b334a45a8ff	3166	#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /!< Enable CMD completion /
bogdanm	0:9b334a45a8ff	3167	#define SDIO_CMD_NIEN ((uint32_t)0x2000) /!< Not Interrupt Enable /
bogdanm	0:9b334a45a8ff	3168	#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /!< CE-ATA command /
bogdanm	0:9b334a45a8ff	3169
bogdanm	0:9b334a45a8ff	3170	/*************** Bit definition for SDIO_RESPCMD register ***************/
bogdanm	0:9b334a45a8ff	3171	#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /!< Response command index /
bogdanm	0:9b334a45a8ff	3172
bogdanm	0:9b334a45a8ff	3173	/**************** Bit definition for SDIO_RESP0 register ****************/
bogdanm	0:9b334a45a8ff	3174	#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!< Card Status /
bogdanm	0:9b334a45a8ff	3175
bogdanm	0:9b334a45a8ff	3176	/**************** Bit definition for SDIO_RESP1 register ****************/
bogdanm	0:9b334a45a8ff	3177	#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!< Card Status /
bogdanm	0:9b334a45a8ff	3178
bogdanm	0:9b334a45a8ff	3179	/**************** Bit definition for SDIO_RESP2 register ****************/
bogdanm	0:9b334a45a8ff	3180	#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!< Card Status /
bogdanm	0:9b334a45a8ff	3181
bogdanm	0:9b334a45a8ff	3182	/**************** Bit definition for SDIO_RESP3 register ****************/
bogdanm	0:9b334a45a8ff	3183	#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!< Card Status /
bogdanm	0:9b334a45a8ff	3184
bogdanm	0:9b334a45a8ff	3185	/**************** Bit definition for SDIO_RESP4 register ****************/
bogdanm	0:9b334a45a8ff	3186	#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!< Card Status /
bogdanm	0:9b334a45a8ff	3187
bogdanm	0:9b334a45a8ff	3188	/**************** Bit definition for SDIO_DTIMER register ***************/
bogdanm	0:9b334a45a8ff	3189	#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!< Data timeout period. /
bogdanm	0:9b334a45a8ff	3190
bogdanm	0:9b334a45a8ff	3191	/**************** Bit definition for SDIO_DLEN register *****************/
bogdanm	0:9b334a45a8ff	3192	#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!< Data length value /
bogdanm	0:9b334a45a8ff	3193
bogdanm	0:9b334a45a8ff	3194	/**************** Bit definition for SDIO_DCTRL register ****************/
bogdanm	0:9b334a45a8ff	3195	#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /!< Data transfer enabled bit /
bogdanm	0:9b334a45a8ff	3196	#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /!< Data transfer direction selection /
bogdanm	0:9b334a45a8ff	3197	#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /!< Data transfer mode selection /
bogdanm	0:9b334a45a8ff	3198	#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /!< DMA enabled bit /
bogdanm	0:9b334a45a8ff	3199
bogdanm	0:9b334a45a8ff	3200	#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /!< DBLOCKSIZE[3:0] bits (Data block size) /
bogdanm	0:9b334a45a8ff	3201	#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3202	#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3203	#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3204	#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3205
bogdanm	0:9b334a45a8ff	3206	#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /!< Read wait start /
bogdanm	0:9b334a45a8ff	3207	#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /!< Read wait stop /
bogdanm	0:9b334a45a8ff	3208	#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /!< Read wait mode /
bogdanm	0:9b334a45a8ff	3209	#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /!< SD I/O enable functions /
bogdanm	0:9b334a45a8ff	3210
bogdanm	0:9b334a45a8ff	3211	/**************** Bit definition for SDIO_DCOUNT register ***************/
bogdanm	0:9b334a45a8ff	3212	#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!< Data count value /
bogdanm	0:9b334a45a8ff	3213
bogdanm	0:9b334a45a8ff	3214	/**************** Bit definition for SDIO_STA register ******************/
bogdanm	0:9b334a45a8ff	3215	#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /!< Command response received (CRC check failed) /
bogdanm	0:9b334a45a8ff	3216	#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /!< Data block sent/received (CRC check failed) /
bogdanm	0:9b334a45a8ff	3217	#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /!< Command response timeout /
bogdanm	0:9b334a45a8ff	3218	#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /!< Data timeout /
bogdanm	0:9b334a45a8ff	3219	#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /!< Transmit FIFO underrun error /
bogdanm	0:9b334a45a8ff	3220	#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /!< Received FIFO overrun error /
bogdanm	0:9b334a45a8ff	3221	#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /!< Command response received (CRC check passed) /
bogdanm	0:9b334a45a8ff	3222	#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /!< Command sent (no response required) /
bogdanm	0:9b334a45a8ff	3223	#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /!< Data end (data counter, SDIDCOUNT, is zero) /
bogdanm	0:9b334a45a8ff	3224	#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /!< Start bit not detected on all data signals in wide bus mode /
bogdanm	0:9b334a45a8ff	3225	#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /!< Data block sent/received (CRC check passed) /
bogdanm	0:9b334a45a8ff	3226	#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /!< Command transfer in progress /
bogdanm	0:9b334a45a8ff	3227	#define SDIO_STA_TXACT ((uint32_t)0x00001000) /!< Data transmit in progress /
bogdanm	0:9b334a45a8ff	3228	#define SDIO_STA_RXACT ((uint32_t)0x00002000) /!< Data receive in progress /
bogdanm	0:9b334a45a8ff	3229	#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
bogdanm	0:9b334a45a8ff	3230	#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
bogdanm	0:9b334a45a8ff	3231	#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /!< Transmit FIFO full /
bogdanm	0:9b334a45a8ff	3232	#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /!< Receive FIFO full /
bogdanm	0:9b334a45a8ff	3233	#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /!< Transmit FIFO empty /
bogdanm	0:9b334a45a8ff	3234	#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /!< Receive FIFO empty /
bogdanm	0:9b334a45a8ff	3235	#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /!< Data available in transmit FIFO /
bogdanm	0:9b334a45a8ff	3236	#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /!< Data available in receive FIFO /
bogdanm	0:9b334a45a8ff	3237	#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /!< SDIO interrupt received /
bogdanm	0:9b334a45a8ff	3238	#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /!< CE-ATA command completion signal received for CMD61 /
bogdanm	0:9b334a45a8ff	3239
bogdanm	0:9b334a45a8ff	3240	/***************** Bit definition for SDIO_ICR register *****************/
bogdanm	0:9b334a45a8ff	3241	#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /!< CCRCFAIL flag clear bit /
bogdanm	0:9b334a45a8ff	3242	#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /!< DCRCFAIL flag clear bit /
bogdanm	0:9b334a45a8ff	3243	#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!< CTIMEOUT flag clear bit /
bogdanm	0:9b334a45a8ff	3244	#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!< DTIMEOUT flag clear bit /
bogdanm	0:9b334a45a8ff	3245	#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /!< TXUNDERR flag clear bit /
bogdanm	0:9b334a45a8ff	3246	#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /!< RXOVERR flag clear bit /
bogdanm	0:9b334a45a8ff	3247	#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /!< CMDREND flag clear bit /
bogdanm	0:9b334a45a8ff	3248	#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /!< CMDSENT flag clear bit /
bogdanm	0:9b334a45a8ff	3249	#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /!< DATAEND flag clear bit /
bogdanm	0:9b334a45a8ff	3250	#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /!< STBITERR flag clear bit /
bogdanm	0:9b334a45a8ff	3251	#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /!< DBCKEND flag clear bit /
bogdanm	0:9b334a45a8ff	3252	#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /!< SDIOIT flag clear bit /
bogdanm	0:9b334a45a8ff	3253	#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /!< CEATAEND flag clear bit /
bogdanm	0:9b334a45a8ff	3254
bogdanm	0:9b334a45a8ff	3255	/**************** Bit definition for SDIO_MASK register *****************/
bogdanm	0:9b334a45a8ff	3256	#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!< Command CRC Fail Interrupt Enable /
bogdanm	0:9b334a45a8ff	3257	#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!< Data CRC Fail Interrupt Enable /
bogdanm	0:9b334a45a8ff	3258	#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!< Command TimeOut Interrupt Enable /
bogdanm	0:9b334a45a8ff	3259	#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!< Data TimeOut Interrupt Enable /
bogdanm	0:9b334a45a8ff	3260	#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!< Tx FIFO UnderRun Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	3261	#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /!< Rx FIFO OverRun Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	3262	#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /!< Command Response Received Interrupt Enable /
bogdanm	0:9b334a45a8ff	3263	#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /!< Command Sent Interrupt Enable /
bogdanm	0:9b334a45a8ff	3264	#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /!< Data End Interrupt Enable /
bogdanm	0:9b334a45a8ff	3265	#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /!< Start Bit Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	3266	#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /!< Data Block End Interrupt Enable /
bogdanm	0:9b334a45a8ff	3267	#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /!< Command Acting Interrupt Enable /
bogdanm	0:9b334a45a8ff	3268	#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /!< Data Transmit Acting Interrupt Enable /
bogdanm	0:9b334a45a8ff	3269	#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /!< Data receive acting interrupt enabled /
bogdanm	0:9b334a45a8ff	3270	#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!< Tx FIFO Half Empty interrupt Enable /
bogdanm	0:9b334a45a8ff	3271	#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!< Rx FIFO Half Full interrupt Enable /
bogdanm	0:9b334a45a8ff	3272	#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!< Tx FIFO Full interrupt Enable /
bogdanm	0:9b334a45a8ff	3273	#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!< Rx FIFO Full interrupt Enable /
bogdanm	0:9b334a45a8ff	3274	#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!< Tx FIFO Empty interrupt Enable /
bogdanm	0:9b334a45a8ff	3275	#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!< Rx FIFO Empty interrupt Enable /
bogdanm	0:9b334a45a8ff	3276	#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /!< Data available in Tx FIFO interrupt Enable /
bogdanm	0:9b334a45a8ff	3277	#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /!< Data available in Rx FIFO interrupt Enable /
bogdanm	0:9b334a45a8ff	3278	#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /!< SDIO Mode Interrupt Received interrupt Enable /
bogdanm	0:9b334a45a8ff	3279	#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /!< CE-ATA command completion signal received Interrupt Enable /
bogdanm	0:9b334a45a8ff	3280
bogdanm	0:9b334a45a8ff	3281	/*************** Bit definition for SDIO_FIFOCNT register ***************/
bogdanm	0:9b334a45a8ff	3282	#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!< Remaining number of words to be written to or read from the FIFO /
bogdanm	0:9b334a45a8ff	3283
bogdanm	0:9b334a45a8ff	3284	/**************** Bit definition for SDIO_FIFO register *****************/
bogdanm	0:9b334a45a8ff	3285	#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!< Receive and transmit FIFO data /
bogdanm	0:9b334a45a8ff	3286
bogdanm	0:9b334a45a8ff	3287
bogdanm	0:9b334a45a8ff	3288
bogdanm	0:9b334a45a8ff	3289	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3290	/* */
bogdanm	0:9b334a45a8ff	3291	/* Serial Peripheral Interface */
bogdanm	0:9b334a45a8ff	3292	/* */
bogdanm	0:9b334a45a8ff	3293	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3294
bogdanm	0:9b334a45a8ff	3295	/***************** Bit definition for SPI_CR1 register ******************/
bogdanm	0:9b334a45a8ff	3296	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
bogdanm	0:9b334a45a8ff	3297	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
bogdanm	0:9b334a45a8ff	3298	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
bogdanm	0:9b334a45a8ff	3299
bogdanm	0:9b334a45a8ff	3300	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
bogdanm	0:9b334a45a8ff	3301	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3302	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3303	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3304
bogdanm	0:9b334a45a8ff	3305	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
bogdanm	0:9b334a45a8ff	3306	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
bogdanm	0:9b334a45a8ff	3307	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
bogdanm	0:9b334a45a8ff	3308	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
bogdanm	0:9b334a45a8ff	3309	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
bogdanm	0:9b334a45a8ff	3310	#define SPI_CR1_DFF ((uint32_t)0x00000800) /!< Data Frame Format /
bogdanm	0:9b334a45a8ff	3311	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
bogdanm	0:9b334a45a8ff	3312	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
bogdanm	0:9b334a45a8ff	3313	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
bogdanm	0:9b334a45a8ff	3314	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
bogdanm	0:9b334a45a8ff	3315
bogdanm	0:9b334a45a8ff	3316	/***************** Bit definition for SPI_CR2 register ******************/
bogdanm	0:9b334a45a8ff	3317	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
bogdanm	0:9b334a45a8ff	3318	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
bogdanm	0:9b334a45a8ff	3319	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
bogdanm	0:9b334a45a8ff	3320	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	3321	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
bogdanm	0:9b334a45a8ff	3322	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
bogdanm	0:9b334a45a8ff	3323
bogdanm	0:9b334a45a8ff	3324	/****************** Bit definition for SPI_SR register ******************/
bogdanm	0:9b334a45a8ff	3325	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
bogdanm	0:9b334a45a8ff	3326	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
bogdanm	0:9b334a45a8ff	3327	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
bogdanm	0:9b334a45a8ff	3328	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
bogdanm	0:9b334a45a8ff	3329	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
bogdanm	0:9b334a45a8ff	3330	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
bogdanm	0:9b334a45a8ff	3331	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
bogdanm	0:9b334a45a8ff	3332	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
bogdanm	0:9b334a45a8ff	3333
bogdanm	0:9b334a45a8ff	3334	/****************** Bit definition for SPI_DR register ******************/
bogdanm	0:9b334a45a8ff	3335	#define SPI_DR_DR ((uint32_t)0x0000FFFF) /!< Data Register /
bogdanm	0:9b334a45a8ff	3336
bogdanm	0:9b334a45a8ff	3337	/***************** Bit definition for SPI_CRCPR register ****************/
bogdanm	0:9b334a45a8ff	3338	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /!< CRC polynomial register /
bogdanm	0:9b334a45a8ff	3339
bogdanm	0:9b334a45a8ff	3340	/**************** Bit definition for SPI_RXCRCR register ****************/
bogdanm	0:9b334a45a8ff	3341	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /!< Rx CRC Register /
bogdanm	0:9b334a45a8ff	3342
bogdanm	0:9b334a45a8ff	3343	/**************** Bit definition for SPI_TXCRCR register ****************/
bogdanm	0:9b334a45a8ff	3344	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /!< Tx CRC Register /
bogdanm	0:9b334a45a8ff	3345
bogdanm	0:9b334a45a8ff	3346
bogdanm	0:9b334a45a8ff	3347
bogdanm	0:9b334a45a8ff	3348	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3349	/* */
bogdanm	0:9b334a45a8ff	3350	/* Inter-integrated Circuit Interface */
bogdanm	0:9b334a45a8ff	3351	/* */
bogdanm	0:9b334a45a8ff	3352	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3353
bogdanm	0:9b334a45a8ff	3354	/***************** Bit definition for I2C_CR1 register ******************/
bogdanm	0:9b334a45a8ff	3355	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral Enable /
bogdanm	0:9b334a45a8ff	3356	#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /!< SMBus Mode /
bogdanm	0:9b334a45a8ff	3357	#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /!< SMBus Type /
bogdanm	0:9b334a45a8ff	3358	#define I2C_CR1_ENARP ((uint32_t)0x00000010) /!< ARP Enable /
bogdanm	0:9b334a45a8ff	3359	#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /!< PEC Enable /
bogdanm	0:9b334a45a8ff	3360	#define I2C_CR1_ENGC ((uint32_t)0x00000040) /!< General Call Enable /
bogdanm	0:9b334a45a8ff	3361	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /!< Clock Stretching Disable (Slave mode) /
bogdanm	0:9b334a45a8ff	3362	#define I2C_CR1_START ((uint32_t)0x00000100) /!< Start Generation /
bogdanm	0:9b334a45a8ff	3363	#define I2C_CR1_STOP ((uint32_t)0x00000200) /!< Stop Generation /
bogdanm	0:9b334a45a8ff	3364	#define I2C_CR1_ACK ((uint32_t)0x00000400) /!< Acknowledge Enable /
bogdanm	0:9b334a45a8ff	3365	#define I2C_CR1_POS ((uint32_t)0x00000800) /!< Acknowledge/PEC Position (for data reception) /
bogdanm	0:9b334a45a8ff	3366	#define I2C_CR1_PEC ((uint32_t)0x00001000) /!< Packet Error Checking /
bogdanm	0:9b334a45a8ff	3367	#define I2C_CR1_ALERT ((uint32_t)0x00002000) /!< SMBus Alert /
bogdanm	0:9b334a45a8ff	3368	#define I2C_CR1_SWRST ((uint32_t)0x00008000) /!< Software Reset /
bogdanm	0:9b334a45a8ff	3369
bogdanm	0:9b334a45a8ff	3370	/***************** Bit definition for I2C_CR2 register ******************/
bogdanm	0:9b334a45a8ff	3371	#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
bogdanm	0:9b334a45a8ff	3372	#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3373	#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3374	#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3375	#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3376	#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	3377	#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /!< Bit 5 /
bogdanm	0:9b334a45a8ff	3378
bogdanm	0:9b334a45a8ff	3379	#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	3380	#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /!< Event Interrupt Enable /
bogdanm	0:9b334a45a8ff	3381	#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /!< Buffer Interrupt Enable /
bogdanm	0:9b334a45a8ff	3382	#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /!< DMA Requests Enable /
bogdanm	0:9b334a45a8ff	3383	#define I2C_CR2_LAST ((uint32_t)0x00001000) /!< DMA Last Transfer /
bogdanm	0:9b334a45a8ff	3384
bogdanm	0:9b334a45a8ff	3385	/***************** Bit definition for I2C_OAR1 register *****************/
bogdanm	0:9b334a45a8ff	3386	#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /!< Interface Address /
bogdanm	0:9b334a45a8ff	3387	#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /!< Interface Address /
bogdanm	0:9b334a45a8ff	3388
bogdanm	0:9b334a45a8ff	3389	#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3390	#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3391	#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3392	#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3393	#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	3394	#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
bogdanm	0:9b334a45a8ff	3395	#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
bogdanm	0:9b334a45a8ff	3396	#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /!< Bit 7 /
bogdanm	0:9b334a45a8ff	3397	#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /!< Bit 8 /
bogdanm	0:9b334a45a8ff	3398	#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /!< Bit 9 /
bogdanm	0:9b334a45a8ff	3399
bogdanm	0:9b334a45a8ff	3400	#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /!< Addressing Mode (Slave mode) /
bogdanm	0:9b334a45a8ff	3401
bogdanm	0:9b334a45a8ff	3402	/***************** Bit definition for I2C_OAR2 register *****************/
bogdanm	0:9b334a45a8ff	3403	#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /!< Dual addressing mode enable /
bogdanm	0:9b334a45a8ff	3404	#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /!< Interface address /
bogdanm	0:9b334a45a8ff	3405
bogdanm	0:9b334a45a8ff	3406	/***************** Bit definition for I2C_SR1 register ******************/
bogdanm	0:9b334a45a8ff	3407	#define I2C_SR1_SB ((uint32_t)0x00000001) /!< Start Bit (Master mode) /
bogdanm	0:9b334a45a8ff	3408	#define I2C_SR1_ADDR ((uint32_t)0x00000002) /!< Address sent (master mode)/matched (slave mode) /
bogdanm	0:9b334a45a8ff	3409	#define I2C_SR1_BTF ((uint32_t)0x00000004) /!< Byte Transfer Finished /
bogdanm	0:9b334a45a8ff	3410	#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /!< 10-bit header sent (Master mode) /
bogdanm	0:9b334a45a8ff	3411	#define I2C_SR1_STOPF ((uint32_t)0x00000010) /!< Stop detection (Slave mode) /
bogdanm	0:9b334a45a8ff	3412	#define I2C_SR1_RXNE ((uint32_t)0x00000040) /!< Data Register not Empty (receivers) /
bogdanm	0:9b334a45a8ff	3413	#define I2C_SR1_TXE ((uint32_t)0x00000080) /!< Data Register Empty (transmitters) /
bogdanm	0:9b334a45a8ff	3414	#define I2C_SR1_BERR ((uint32_t)0x00000100) /!< Bus Error /
bogdanm	0:9b334a45a8ff	3415	#define I2C_SR1_ARLO ((uint32_t)0x00000200) /!< Arbitration Lost (master mode) /
bogdanm	0:9b334a45a8ff	3416	#define I2C_SR1_AF ((uint32_t)0x00000400) /!< Acknowledge Failure /
bogdanm	0:9b334a45a8ff	3417	#define I2C_SR1_OVR ((uint32_t)0x00000800) /!< Overrun/Underrun /
bogdanm	0:9b334a45a8ff	3418	#define I2C_SR1_PECERR ((uint32_t)0x00001000) /!< PEC Error in reception /
bogdanm	0:9b334a45a8ff	3419	#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /!< Timeout or Tlow Error /
bogdanm	0:9b334a45a8ff	3420	#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /!< SMBus Alert /
bogdanm	0:9b334a45a8ff	3421
bogdanm	0:9b334a45a8ff	3422	/***************** Bit definition for I2C_SR2 register ******************/
bogdanm	0:9b334a45a8ff	3423	#define I2C_SR2_MSL ((uint32_t)0x00000001) /!< Master/Slave /
bogdanm	0:9b334a45a8ff	3424	#define I2C_SR2_BUSY ((uint32_t)0x00000002) /!< Bus Busy /
bogdanm	0:9b334a45a8ff	3425	#define I2C_SR2_TRA ((uint32_t)0x00000004) /!< Transmitter/Receiver /
bogdanm	0:9b334a45a8ff	3426	#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /!< General Call Address (Slave mode) /
bogdanm	0:9b334a45a8ff	3427	#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /!< SMBus Device Default Address (Slave mode) /
bogdanm	0:9b334a45a8ff	3428	#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /!< SMBus Host Header (Slave mode) /
bogdanm	0:9b334a45a8ff	3429	#define I2C_SR2_DUALF ((uint32_t)0x00000080) /!< Dual Flag (Slave mode) /
bogdanm	0:9b334a45a8ff	3430	#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /!< Packet Error Checking Register /
bogdanm	0:9b334a45a8ff	3431
bogdanm	0:9b334a45a8ff	3432	/***************** Bit definition for I2C_CCR register ******************/
bogdanm	0:9b334a45a8ff	3433	#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /!< Clock Control Register in Fast/Standard mode (Master mode) /
bogdanm	0:9b334a45a8ff	3434	#define I2C_CCR_DUTY ((uint32_t)0x00004000) /!< Fast Mode Duty Cycle /
bogdanm	0:9b334a45a8ff	3435	#define I2C_CCR_FS ((uint32_t)0x00008000) /!< I2C Master Mode Selection /
bogdanm	0:9b334a45a8ff	3436
bogdanm	0:9b334a45a8ff	3437	/**************** Bit definition for I2C_TRISE register *****************/
bogdanm	0:9b334a45a8ff	3438	#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
bogdanm	0:9b334a45a8ff	3439
bogdanm	0:9b334a45a8ff	3440	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3441	/* */
bogdanm	0:9b334a45a8ff	3442	/* Universal Synchronous Asynchronous Receiver Transmitter */
bogdanm	0:9b334a45a8ff	3443	/* */
bogdanm	0:9b334a45a8ff	3444	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3445
bogdanm	0:9b334a45a8ff	3446	/***************** Bit definition for USART_SR register *****************/
bogdanm	0:9b334a45a8ff	3447	#define USART_SR_PE ((uint32_t)0x00000001) /!< Parity Error /
bogdanm	0:9b334a45a8ff	3448	#define USART_SR_FE ((uint32_t)0x00000002) /!< Framing Error /
bogdanm	0:9b334a45a8ff	3449	#define USART_SR_NE ((uint32_t)0x00000004) /!< Noise Error Flag /
bogdanm	0:9b334a45a8ff	3450	#define USART_SR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
bogdanm	0:9b334a45a8ff	3451	#define USART_SR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
bogdanm	0:9b334a45a8ff	3452	#define USART_SR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
bogdanm	0:9b334a45a8ff	3453	#define USART_SR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
bogdanm	0:9b334a45a8ff	3454	#define USART_SR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
bogdanm	0:9b334a45a8ff	3455	#define USART_SR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
bogdanm	0:9b334a45a8ff	3456	#define USART_SR_CTS ((uint32_t)0x00000200) /!< CTS Flag /
bogdanm	0:9b334a45a8ff	3457
bogdanm	0:9b334a45a8ff	3458	/***************** Bit definition for USART_DR register *****************/
bogdanm	0:9b334a45a8ff	3459	#define USART_DR_DR ((uint32_t)0x000001FF) /!< Data value /
bogdanm	0:9b334a45a8ff	3460
bogdanm	0:9b334a45a8ff	3461	/**************** Bit definition for USART_BRR register *****************/
bogdanm	0:9b334a45a8ff	3462	#define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
bogdanm	0:9b334a45a8ff	3463	#define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
bogdanm	0:9b334a45a8ff	3464
bogdanm	0:9b334a45a8ff	3465	/**************** Bit definition for USART_CR1 register *****************/
bogdanm	0:9b334a45a8ff	3466	#define USART_CR1_SBK ((uint32_t)0x00000001) /!< Send Break /
bogdanm	0:9b334a45a8ff	3467	#define USART_CR1_RWU ((uint32_t)0x00000002) /!< Receiver wakeup /
bogdanm	0:9b334a45a8ff	3468	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
bogdanm	0:9b334a45a8ff	3469	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
bogdanm	0:9b334a45a8ff	3470	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
bogdanm	0:9b334a45a8ff	3471	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
bogdanm	0:9b334a45a8ff	3472	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
bogdanm	0:9b334a45a8ff	3473	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< PE Interrupt Enable /
bogdanm	0:9b334a45a8ff	3474	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
bogdanm	0:9b334a45a8ff	3475	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
bogdanm	0:9b334a45a8ff	3476	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
bogdanm	0:9b334a45a8ff	3477	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Wakeup method /
bogdanm	0:9b334a45a8ff	3478	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
bogdanm	0:9b334a45a8ff	3479	#define USART_CR1_UE ((uint32_t)0x00002000) /!< USART Enable /
bogdanm	0:9b334a45a8ff	3480
bogdanm	0:9b334a45a8ff	3481	/**************** Bit definition for USART_CR2 register *****************/
bogdanm	0:9b334a45a8ff	3482	#define USART_CR2_ADD ((uint32_t)0x0000000F) /!< Address of the USART node /
bogdanm	0:9b334a45a8ff	3483	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
bogdanm	0:9b334a45a8ff	3484	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
bogdanm	0:9b334a45a8ff	3485	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
bogdanm	0:9b334a45a8ff	3486	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
bogdanm	0:9b334a45a8ff	3487	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
bogdanm	0:9b334a45a8ff	3488	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
bogdanm	0:9b334a45a8ff	3489
bogdanm	0:9b334a45a8ff	3490	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
bogdanm	0:9b334a45a8ff	3491	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3492	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3493
bogdanm	0:9b334a45a8ff	3494	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
bogdanm	0:9b334a45a8ff	3495
bogdanm	0:9b334a45a8ff	3496	/**************** Bit definition for USART_CR3 register *****************/
bogdanm	0:9b334a45a8ff	3497	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	3498	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
bogdanm	0:9b334a45a8ff	3499	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
bogdanm	0:9b334a45a8ff	3500	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
bogdanm	0:9b334a45a8ff	3501	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< Smartcard NACK enable /
bogdanm	0:9b334a45a8ff	3502	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< Smartcard mode enable /
bogdanm	0:9b334a45a8ff	3503	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
bogdanm	0:9b334a45a8ff	3504	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
bogdanm	0:9b334a45a8ff	3505	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
bogdanm	0:9b334a45a8ff	3506	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
bogdanm	0:9b334a45a8ff	3507	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
bogdanm	0:9b334a45a8ff	3508
bogdanm	0:9b334a45a8ff	3509	/**************** Bit definition for USART_GTPR register ****************/
bogdanm	0:9b334a45a8ff	3510	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
bogdanm	0:9b334a45a8ff	3511	#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3512	#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3513	#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3514	#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3515	#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	3516	#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /!< Bit 5 /
bogdanm	0:9b334a45a8ff	3517	#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /!< Bit 6 /
bogdanm	0:9b334a45a8ff	3518	#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /!< Bit 7 /
bogdanm	0:9b334a45a8ff	3519
bogdanm	0:9b334a45a8ff	3520	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< Guard time value /
bogdanm	0:9b334a45a8ff	3521
bogdanm	0:9b334a45a8ff	3522	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3523	/* */
bogdanm	0:9b334a45a8ff	3524	/* Debug MCU */
bogdanm	0:9b334a45a8ff	3525	/* */
bogdanm	0:9b334a45a8ff	3526	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3527
bogdanm	0:9b334a45a8ff	3528	/************** Bit definition for DBGMCU_IDCODE register ***************/
bogdanm	0:9b334a45a8ff	3529	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
bogdanm	0:9b334a45a8ff	3530
bogdanm	0:9b334a45a8ff	3531	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
bogdanm	0:9b334a45a8ff	3532	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3533	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3534	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3535	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3536	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	3537	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
bogdanm	0:9b334a45a8ff	3538	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
bogdanm	0:9b334a45a8ff	3539	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
bogdanm	0:9b334a45a8ff	3540	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
bogdanm	0:9b334a45a8ff	3541	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
bogdanm	0:9b334a45a8ff	3542	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
bogdanm	0:9b334a45a8ff	3543	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
bogdanm	0:9b334a45a8ff	3544	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
bogdanm	0:9b334a45a8ff	3545	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
bogdanm	0:9b334a45a8ff	3546	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
bogdanm	0:9b334a45a8ff	3547	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
bogdanm	0:9b334a45a8ff	3548
bogdanm	0:9b334a45a8ff	3549	/**************** Bit definition for DBGMCU_CR register *****************/
bogdanm	0:9b334a45a8ff	3550	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /!< Debug Sleep Mode /
bogdanm	0:9b334a45a8ff	3551	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
bogdanm	0:9b334a45a8ff	3552	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
bogdanm	0:9b334a45a8ff	3553	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /!< Trace Pin Assignment Control /
bogdanm	0:9b334a45a8ff	3554
bogdanm	0:9b334a45a8ff	3555	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
bogdanm	0:9b334a45a8ff	3556	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3557	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3558
bogdanm	0:9b334a45a8ff	3559	#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /!< Debug Independent Watchdog stopped when Core is halted /
bogdanm	0:9b334a45a8ff	3560	#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /!< Debug Window Watchdog stopped when Core is halted /
bogdanm	0:9b334a45a8ff	3561	#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /!< TIM1 counter stopped when core is halted /
bogdanm	0:9b334a45a8ff	3562	#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /!< TIM2 counter stopped when core is halted /
bogdanm	0:9b334a45a8ff	3563	#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /!< TIM3 counter stopped when core is halted /
bogdanm	0:9b334a45a8ff	3564	#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /!< TIM4 counter stopped when core is halted /
bogdanm	0:9b334a45a8ff	3565	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /!< SMBUS timeout mode stopped when Core is halted /
bogdanm	0:9b334a45a8ff	3566	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /!< SMBUS timeout mode stopped when Core is halted /
bogdanm	0:9b334a45a8ff	3567	#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /!< Debug TIM15 stopped when Core is halted /
bogdanm	0:9b334a45a8ff	3568	#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /!< Debug TIM16 stopped when Core is halted /
bogdanm	0:9b334a45a8ff	3569	#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /!< Debug TIM17 stopped when Core is halted /
bogdanm	0:9b334a45a8ff	3570
bogdanm	0:9b334a45a8ff	3571	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3572	/* */
bogdanm	0:9b334a45a8ff	3573	/* FLASH and Option Bytes Registers */
bogdanm	0:9b334a45a8ff	3574	/* */
bogdanm	0:9b334a45a8ff	3575	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3576	/***************** Bit definition for FLASH_ACR register ****************/
bogdanm	0:9b334a45a8ff	3577	#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /!< Flash Half Cycle Access Enable /
bogdanm	0:9b334a45a8ff	3578
bogdanm	0:9b334a45a8ff	3579	/**************** Bit definition for FLASH_KEYR register ****************/
bogdanm	0:9b334a45a8ff	3580	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
bogdanm	0:9b334a45a8ff	3581
bogdanm	0:9b334a45a8ff	3582	#define RDP_KEY ((uint32_t)0x000000A5) /!< RDP Key /
bogdanm	0:9b334a45a8ff	3583	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< FPEC Key1 /
bogdanm	0:9b334a45a8ff	3584	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /!< FPEC Key2 /
bogdanm	0:9b334a45a8ff	3585
bogdanm	0:9b334a45a8ff	3586	/*************** Bit definition for FLASH_OPTKEYR register **************/
bogdanm	0:9b334a45a8ff	3587	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
bogdanm	0:9b334a45a8ff	3588
bogdanm	0:9b334a45a8ff	3589	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
bogdanm	0:9b334a45a8ff	3590	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
bogdanm	0:9b334a45a8ff	3591
bogdanm	0:9b334a45a8ff	3592	/**************** Bit definition for FLASH_SR register ******************/
bogdanm	0:9b334a45a8ff	3593	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
bogdanm	0:9b334a45a8ff	3594	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
bogdanm	0:9b334a45a8ff	3595	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
bogdanm	0:9b334a45a8ff	3596	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
bogdanm	0:9b334a45a8ff	3597
bogdanm	0:9b334a45a8ff	3598	/***************** Bit definition for FLASH_CR register *****************/
bogdanm	0:9b334a45a8ff	3599	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
bogdanm	0:9b334a45a8ff	3600	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
bogdanm	0:9b334a45a8ff	3601	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
bogdanm	0:9b334a45a8ff	3602	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
bogdanm	0:9b334a45a8ff	3603	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
bogdanm	0:9b334a45a8ff	3604	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
bogdanm	0:9b334a45a8ff	3605	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
bogdanm	0:9b334a45a8ff	3606	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
bogdanm	0:9b334a45a8ff	3607	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	3608	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
bogdanm	0:9b334a45a8ff	3609
bogdanm	0:9b334a45a8ff	3610	/***************** Bit definition for FLASH_AR register *****************/
bogdanm	0:9b334a45a8ff	3611	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
bogdanm	0:9b334a45a8ff	3612
bogdanm	0:9b334a45a8ff	3613	/**************** Bit definition for FLASH_OBR register *****************/
bogdanm	0:9b334a45a8ff	3614	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
bogdanm	0:9b334a45a8ff	3615	#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /!< Read protection /
bogdanm	0:9b334a45a8ff	3616
bogdanm	0:9b334a45a8ff	3617	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /!< IWDG SW /
bogdanm	0:9b334a45a8ff	3618	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /!< nRST_STOP /
bogdanm	0:9b334a45a8ff	3619	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /!< nRST_STDBY /
bogdanm	0:9b334a45a8ff	3620	#define FLASH_OBR_USER ((uint32_t)0x0000001C) /!< User Option Bytes /
bogdanm	0:9b334a45a8ff	3621
bogdanm	0:9b334a45a8ff	3622	/**************** Bit definition for FLASH_WRPR register ****************/
bogdanm	0:9b334a45a8ff	3623	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
bogdanm	0:9b334a45a8ff	3624
bogdanm	0:9b334a45a8ff	3625	/----------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	3626
bogdanm	0:9b334a45a8ff	3627	/**************** Bit definition for FLASH_RDP register *****************/
bogdanm	0:9b334a45a8ff	3628	#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
bogdanm	0:9b334a45a8ff	3629	#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
bogdanm	0:9b334a45a8ff	3630
bogdanm	0:9b334a45a8ff	3631	/**************** Bit definition for FLASH_USER register ****************/
bogdanm	0:9b334a45a8ff	3632	#define FLASH_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
bogdanm	0:9b334a45a8ff	3633	#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
bogdanm	0:9b334a45a8ff	3634
bogdanm	0:9b334a45a8ff	3635	/**************** Bit definition for FLASH_Data0 register ***************/
bogdanm	0:9b334a45a8ff	3636	#define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /!< User data storage option byte /
bogdanm	0:9b334a45a8ff	3637	#define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /!< User data storage complemented option byte /
bogdanm	0:9b334a45a8ff	3638
bogdanm	0:9b334a45a8ff	3639	/**************** Bit definition for FLASH_Data1 register ***************/
bogdanm	0:9b334a45a8ff	3640	#define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /!< User data storage option byte /
bogdanm	0:9b334a45a8ff	3641	#define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /!< User data storage complemented option byte /
bogdanm	0:9b334a45a8ff	3642
bogdanm	0:9b334a45a8ff	3643	/**************** Bit definition for FLASH_WRP0 register ****************/
bogdanm	0:9b334a45a8ff	3644	#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
bogdanm	0:9b334a45a8ff	3645	#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
bogdanm	0:9b334a45a8ff	3646
bogdanm	0:9b334a45a8ff	3647	/**************** Bit definition for FLASH_WRP1 register ****************/
bogdanm	0:9b334a45a8ff	3648	#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
bogdanm	0:9b334a45a8ff	3649	#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
bogdanm	0:9b334a45a8ff	3650
bogdanm	0:9b334a45a8ff	3651	/**************** Bit definition for FLASH_WRP2 register ****************/
bogdanm	0:9b334a45a8ff	3652	#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
bogdanm	0:9b334a45a8ff	3653	#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
bogdanm	0:9b334a45a8ff	3654
bogdanm	0:9b334a45a8ff	3655	/**************** Bit definition for FLASH_WRP3 register ****************/
bogdanm	0:9b334a45a8ff	3656	#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
bogdanm	0:9b334a45a8ff	3657	#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
bogdanm	0:9b334a45a8ff	3658
bogdanm	0:9b334a45a8ff	3659
bogdanm	0:9b334a45a8ff	3660
bogdanm	0:9b334a45a8ff	3661	/**
bogdanm	0:9b334a45a8ff	3662	* @}
bogdanm	0:9b334a45a8ff	3663	*/
bogdanm	0:9b334a45a8ff	3664
bogdanm	0:9b334a45a8ff	3665	/**
bogdanm	0:9b334a45a8ff	3666	* @}
bogdanm	0:9b334a45a8ff	3667	*/
bogdanm	0:9b334a45a8ff	3668
bogdanm	0:9b334a45a8ff	3669	/** @addtogroup Exported_macro
bogdanm	0:9b334a45a8ff	3670	* @{
bogdanm	0:9b334a45a8ff	3671	*/
bogdanm	0:9b334a45a8ff	3672
bogdanm	0:9b334a45a8ff	3673	/**************************** ADC Instances *******************************/
bogdanm	0:9b334a45a8ff	3674	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
bogdanm	0:9b334a45a8ff	3675
bogdanm	0:9b334a45a8ff	3676	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
bogdanm	0:9b334a45a8ff	3677
bogdanm	0:9b334a45a8ff	3678	/**************************** CEC Instances *******************************/
bogdanm	0:9b334a45a8ff	3679	#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
bogdanm	0:9b334a45a8ff	3680
bogdanm	0:9b334a45a8ff	3681	/**************************** CRC Instances *******************************/
bogdanm	0:9b334a45a8ff	3682	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm	0:9b334a45a8ff	3683
bogdanm	0:9b334a45a8ff	3684	/**************************** DAC Instances *******************************/
bogdanm	0:9b334a45a8ff	3685	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
bogdanm	0:9b334a45a8ff	3686
bogdanm	0:9b334a45a8ff	3687	/**************************** DMA Instances *******************************/
bogdanm	0:9b334a45a8ff	3688	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
bogdanm	0:9b334a45a8ff	3689	((INSTANCE) == DMA1_Channel2) \|\| \
bogdanm	0:9b334a45a8ff	3690	((INSTANCE) == DMA1_Channel3) \|\| \
bogdanm	0:9b334a45a8ff	3691	((INSTANCE) == DMA1_Channel4) \|\| \
bogdanm	0:9b334a45a8ff	3692	((INSTANCE) == DMA1_Channel5) \|\| \
bogdanm	0:9b334a45a8ff	3693	((INSTANCE) == DMA1_Channel6) \|\| \
bogdanm	0:9b334a45a8ff	3694	((INSTANCE) == DMA1_Channel7))
bogdanm	0:9b334a45a8ff	3695
bogdanm	0:9b334a45a8ff	3696	/***************************** GPIO Instances *****************************/
bogdanm	0:9b334a45a8ff	3697	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
bogdanm	0:9b334a45a8ff	3698	((INSTANCE) == GPIOB) \|\| \
bogdanm	0:9b334a45a8ff	3699	((INSTANCE) == GPIOC) \|\| \
bogdanm	0:9b334a45a8ff	3700	((INSTANCE) == GPIOD) \|\| \
bogdanm	0:9b334a45a8ff	3701	((INSTANCE) == GPIOE))
bogdanm	0:9b334a45a8ff	3702
bogdanm	0:9b334a45a8ff	3703	/************************** GPIO Alternate Function Instances *************/
bogdanm	0:9b334a45a8ff	3704	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
bogdanm	0:9b334a45a8ff	3705
bogdanm	0:9b334a45a8ff	3706	/************************** GPIO Lock Instances ***************************/
bogdanm	0:9b334a45a8ff	3707	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
bogdanm	0:9b334a45a8ff	3708
bogdanm	0:9b334a45a8ff	3709	/****************************** I2C Instances *****************************/
bogdanm	0:9b334a45a8ff	3710	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
bogdanm	0:9b334a45a8ff	3711	((INSTANCE) == I2C2))
bogdanm	0:9b334a45a8ff	3712
bogdanm	0:9b334a45a8ff	3713	/**************************** IWDG Instances ******************************/
bogdanm	0:9b334a45a8ff	3714	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm	0:9b334a45a8ff	3715
bogdanm	0:9b334a45a8ff	3716	/****************************** SPI Instances *****************************/
bogdanm	0:9b334a45a8ff	3717	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
bogdanm	0:9b334a45a8ff	3718	((INSTANCE) == SPI2))
bogdanm	0:9b334a45a8ff	3719
bogdanm	0:9b334a45a8ff	3720	/**************************** START TIM Instances *************************/
bogdanm	0:9b334a45a8ff	3721	/**************************** TIM Instances *******************************/
bogdanm	0:9b334a45a8ff	3722	#define IS_TIM_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3723	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3724	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3725	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3726	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	3727	((INSTANCE) == TIM6) \|\| \
bogdanm	0:9b334a45a8ff	3728	((INSTANCE) == TIM7) \|\| \
bogdanm	0:9b334a45a8ff	3729	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	3730	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3731	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3732
bogdanm	0:9b334a45a8ff	3733	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3734	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3735	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3736	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3737	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	3738	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	3739	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3740	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3741
bogdanm	0:9b334a45a8ff	3742	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3743	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3744	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3745	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3746	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	3747	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	3748
bogdanm	0:9b334a45a8ff	3749	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3750	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3751	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3752	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3753	((INSTANCE) == TIM4))
bogdanm	0:9b334a45a8ff	3754
bogdanm	0:9b334a45a8ff	3755	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3756	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3757	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3758	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3759	((INSTANCE) == TIM4))
bogdanm	0:9b334a45a8ff	3760
bogdanm	0:9b334a45a8ff	3761	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3762	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3763	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3764	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3765	((INSTANCE) == TIM4))
bogdanm	0:9b334a45a8ff	3766
bogdanm	0:9b334a45a8ff	3767	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3768	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3769	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3770	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3771	((INSTANCE) == TIM4))
bogdanm	0:9b334a45a8ff	3772
bogdanm	0:9b334a45a8ff	3773	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3774	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3775	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3776	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3777	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	3778	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	3779
bogdanm	0:9b334a45a8ff	3780	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3781	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3782	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3783	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3784	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	3785	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	3786
bogdanm	0:9b334a45a8ff	3787	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3788	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3789	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3790	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3791	((INSTANCE) == TIM4))
bogdanm	0:9b334a45a8ff	3792
bogdanm	0:9b334a45a8ff	3793	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3794	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3795	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3796	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3797	((INSTANCE) == TIM4))
bogdanm	0:9b334a45a8ff	3798
bogdanm	0:9b334a45a8ff	3799	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3800	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3801	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3802	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3803	((INSTANCE) == TIM4))
bogdanm	0:9b334a45a8ff	3804
bogdanm	0:9b334a45a8ff	3805	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3806	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3807	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3808	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3809	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	3810	((INSTANCE) == TIM6) \|\| \
bogdanm	0:9b334a45a8ff	3811	((INSTANCE) == TIM7) \|\| \
bogdanm	0:9b334a45a8ff	3812	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	3813
bogdanm	0:9b334a45a8ff	3814	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3815	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3816	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3817	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3818	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	3819	((INSTANCE) == TIM15))
bogdanm	0:9b334a45a8ff	3820
bogdanm	0:9b334a45a8ff	3821	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3822	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3823	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3824	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3825	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	3826	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	3827	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3828	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3829
bogdanm	0:9b334a45a8ff	3830	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3831	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3832	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	3833	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3834	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3835
bogdanm	0:9b334a45a8ff	3836	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm	0:9b334a45a8ff	3837	((((INSTANCE) == TIM1) && \
bogdanm	0:9b334a45a8ff	3838	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	3839	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	3840	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	3841	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	0:9b334a45a8ff	3842	\|\| \
bogdanm	0:9b334a45a8ff	3843	(((INSTANCE) == TIM2) && \
bogdanm	0:9b334a45a8ff	3844	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	3845	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	3846	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	3847	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	0:9b334a45a8ff	3848	\|\| \
bogdanm	0:9b334a45a8ff	3849	(((INSTANCE) == TIM3) && \
bogdanm	0:9b334a45a8ff	3850	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	3851	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	3852	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	3853	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	0:9b334a45a8ff	3854	\|\| \
bogdanm	0:9b334a45a8ff	3855	(((INSTANCE) == TIM4) && \
bogdanm	0:9b334a45a8ff	3856	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	3857	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	3858	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	3859	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	0:9b334a45a8ff	3860	\|\| \
bogdanm	0:9b334a45a8ff	3861	(((INSTANCE) == TIM15) && \
bogdanm	0:9b334a45a8ff	3862	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	3863	((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm	0:9b334a45a8ff	3864	\|\| \
bogdanm	0:9b334a45a8ff	3865	(((INSTANCE) == TIM16) && \
bogdanm	0:9b334a45a8ff	3866	(((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm	0:9b334a45a8ff	3867	\|\| \
bogdanm	0:9b334a45a8ff	3868	(((INSTANCE) == TIM17) && \
bogdanm	0:9b334a45a8ff	3869	(((CHANNEL) == TIM_CHANNEL_1))))
bogdanm	0:9b334a45a8ff	3870
bogdanm	0:9b334a45a8ff	3871	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
bogdanm	0:9b334a45a8ff	3872	((((INSTANCE) == TIM1) && \
bogdanm	0:9b334a45a8ff	3873	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	3874	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	3875	((CHANNEL) == TIM_CHANNEL_3))) \
bogdanm	0:9b334a45a8ff	3876	\|\| \
bogdanm	0:9b334a45a8ff	3877	(((INSTANCE) == TIM15) && \
bogdanm	0:9b334a45a8ff	3878	((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm	0:9b334a45a8ff	3879	\|\| \
bogdanm	0:9b334a45a8ff	3880	(((INSTANCE) == TIM16) && \
bogdanm	0:9b334a45a8ff	3881	((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm	0:9b334a45a8ff	3882	\|\| \
bogdanm	0:9b334a45a8ff	3883	(((INSTANCE) == TIM17) && \
bogdanm	0:9b334a45a8ff	3884	((CHANNEL) == TIM_CHANNEL_1)))
bogdanm	0:9b334a45a8ff	3885
bogdanm	0:9b334a45a8ff	3886	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3887	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3888	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3889	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3890	((INSTANCE) == TIM4))
bogdanm	0:9b334a45a8ff	3891
bogdanm	0:9b334a45a8ff	3892	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3893	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3894	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	3895	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3896	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3897
bogdanm	0:9b334a45a8ff	3898	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3899	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3900	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3901	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3902	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	3903	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	3904	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3905	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3906
bogdanm	0:9b334a45a8ff	3907	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3908	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3909	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3910	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3911	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	3912	((INSTANCE) == TIM6) \|\| \
bogdanm	0:9b334a45a8ff	3913	((INSTANCE) == TIM7) \|\| \
bogdanm	0:9b334a45a8ff	3914	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	3915	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3916	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3917
bogdanm	0:9b334a45a8ff	3918	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3919	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3920	((INSTANCE) == TIM2) \|\| \
bogdanm	0:9b334a45a8ff	3921	((INSTANCE) == TIM3) \|\| \
bogdanm	0:9b334a45a8ff	3922	((INSTANCE) == TIM4) \|\| \
bogdanm	0:9b334a45a8ff	3923	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	3924	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3925	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3926
bogdanm	0:9b334a45a8ff	3927	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
bogdanm	0:9b334a45a8ff	3928	(((INSTANCE) == TIM1) \|\| \
bogdanm	0:9b334a45a8ff	3929	((INSTANCE) == TIM15) \|\| \
bogdanm	0:9b334a45a8ff	3930	((INSTANCE) == TIM16) \|\| \
bogdanm	0:9b334a45a8ff	3931	((INSTANCE) == TIM17))
bogdanm	0:9b334a45a8ff	3932
bogdanm	0:9b334a45a8ff	3933	/**************************** END TIM Instances ***************************/
bogdanm	0:9b334a45a8ff	3934
bogdanm	0:9b334a45a8ff	3935
bogdanm	0:9b334a45a8ff	3936	/****************** USART Instances : Synchronous mode ********************/
bogdanm	0:9b334a45a8ff	3937	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	3938	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	3939	((INSTANCE) == USART3))
bogdanm	0:9b334a45a8ff	3940
bogdanm	0:9b334a45a8ff	3941	/****************** UART Instances : Asynchronous mode ********************/
bogdanm	0:9b334a45a8ff	3942	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	3943	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	3944	((INSTANCE) == USART3))
bogdanm	0:9b334a45a8ff	3945
bogdanm	0:9b334a45a8ff	3946	/****************** UART Instances : Half-Duplex mode ********************/
bogdanm	0:9b334a45a8ff	3947	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	3948	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	3949	((INSTANCE) == USART3))
bogdanm	0:9b334a45a8ff	3950
bogdanm	0:9b334a45a8ff	3951	/****************** UART Instances : LIN mode ********************/
bogdanm	0:9b334a45a8ff	3952	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	3953	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	3954	((INSTANCE) == USART3))
bogdanm	0:9b334a45a8ff	3955
bogdanm	0:9b334a45a8ff	3956	/**************** UART Instances : Hardware Flow control ******************/
bogdanm	0:9b334a45a8ff	3957	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	3958	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	3959	((INSTANCE) == USART3))
bogdanm	0:9b334a45a8ff	3960
bogdanm	0:9b334a45a8ff	3961	/******************* UART Instances : Smard card mode *********************/
bogdanm	0:9b334a45a8ff	3962	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	3963	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	3964	((INSTANCE) == USART3))
bogdanm	0:9b334a45a8ff	3965
bogdanm	0:9b334a45a8ff	3966	/********************* UART Instances : IRDA mode *************************/
bogdanm	0:9b334a45a8ff	3967	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	3968	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	3969	((INSTANCE) == USART3))
bogdanm	0:9b334a45a8ff	3970
bogdanm	0:9b334a45a8ff	3971	/*************** UART Instances : Multi-Processor mode ********************/
bogdanm	0:9b334a45a8ff	3972	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	3973	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	3974	((INSTANCE) == USART3))
bogdanm	0:9b334a45a8ff	3975
bogdanm	0:9b334a45a8ff	3976	/*************** UART Instances : DMA mode available ********************/
bogdanm	0:9b334a45a8ff	3977	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	0:9b334a45a8ff	3978	((INSTANCE) == USART2) \|\| \
bogdanm	0:9b334a45a8ff	3979	((INSTANCE) == USART3))
bogdanm	0:9b334a45a8ff	3980
bogdanm	0:9b334a45a8ff	3981	/**************************** RTC Instances *******************************/
bogdanm	0:9b334a45a8ff	3982	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm	0:9b334a45a8ff	3983
bogdanm	0:9b334a45a8ff	3984	/************************** WWDG Instances ***************************/
bogdanm	0:9b334a45a8ff	3985	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm	0:9b334a45a8ff	3986
bogdanm	0:9b334a45a8ff	3987
bogdanm	0:9b334a45a8ff	3988
bogdanm	0:9b334a45a8ff	3989
bogdanm	0:9b334a45a8ff	3990
bogdanm	0:9b334a45a8ff	3991	/**
bogdanm	0:9b334a45a8ff	3992	* @}
bogdanm	0:9b334a45a8ff	3993	*/
bogdanm	0:9b334a45a8ff	3994	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3995	/* For a painless codes migration between the STM32F1xx device product */
bogdanm	0:9b334a45a8ff	3996	/* lines, the aliases defined below are put in place to overcome the */
bogdanm	0:9b334a45a8ff	3997	/* differences in the interrupt handlers and IRQn definitions. */
bogdanm	0:9b334a45a8ff	3998	/* No need to update developed interrupt code when moving across */
bogdanm	0:9b334a45a8ff	3999	/* product lines within the same STM32F1 Family */
bogdanm	0:9b334a45a8ff	4000	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4001
bogdanm	0:9b334a45a8ff	4002	/* Aliases for __IRQn */
bogdanm	0:9b334a45a8ff	4003	#define ADC1_2_IRQn ADC1_IRQn
bogdanm	0:9b334a45a8ff	4004
bogdanm	0:9b334a45a8ff	4005
bogdanm	0:9b334a45a8ff	4006
bogdanm	0:9b334a45a8ff	4007	#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
bogdanm	0:9b334a45a8ff	4008	#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
bogdanm	0:9b334a45a8ff	4009	#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
bogdanm	0:9b334a45a8ff	4010
bogdanm	0:9b334a45a8ff	4011	#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
bogdanm	0:9b334a45a8ff	4012	#define TIM10_IRQn TIM1_UP_TIM16_IRQn
bogdanm	0:9b334a45a8ff	4013	#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
bogdanm	0:9b334a45a8ff	4014
bogdanm	0:9b334a45a8ff	4015	#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
bogdanm	0:9b334a45a8ff	4016	#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
bogdanm	0:9b334a45a8ff	4017	#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
bogdanm	0:9b334a45a8ff	4018
bogdanm	0:9b334a45a8ff	4019
bogdanm	0:9b334a45a8ff	4020
bogdanm	0:9b334a45a8ff	4021	#define OTG_FS_WKUP_IRQn CEC_IRQn
bogdanm	0:9b334a45a8ff	4022	#define USBWakeUp_IRQn CEC_IRQn
bogdanm	0:9b334a45a8ff	4023
bogdanm	0:9b334a45a8ff	4024
bogdanm	0:9b334a45a8ff	4025
bogdanm	0:9b334a45a8ff	4026	#define TIM6_IRQn TIM6_DAC_IRQn
bogdanm	0:9b334a45a8ff	4027
bogdanm	0:9b334a45a8ff	4028
bogdanm	0:9b334a45a8ff	4029	/* Aliases for __IRQHandler */
bogdanm	0:9b334a45a8ff	4030	#define ADC1_2_IRQHandler ADC1_IRQHandler
bogdanm	0:9b334a45a8ff	4031
bogdanm	0:9b334a45a8ff	4032
bogdanm	0:9b334a45a8ff	4033
bogdanm	0:9b334a45a8ff	4034	#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
bogdanm	0:9b334a45a8ff	4035	#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
bogdanm	0:9b334a45a8ff	4036	#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
bogdanm	0:9b334a45a8ff	4037
bogdanm	0:9b334a45a8ff	4038	#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
bogdanm	0:9b334a45a8ff	4039	#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
bogdanm	0:9b334a45a8ff	4040	#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
bogdanm	0:9b334a45a8ff	4041
bogdanm	0:9b334a45a8ff	4042	#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
bogdanm	0:9b334a45a8ff	4043	#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
bogdanm	0:9b334a45a8ff	4044	#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
bogdanm	0:9b334a45a8ff	4045
bogdanm	0:9b334a45a8ff	4046
bogdanm	0:9b334a45a8ff	4047
bogdanm	0:9b334a45a8ff	4048	#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
bogdanm	0:9b334a45a8ff	4049	#define USBWakeUp_IRQHandler CEC_IRQHandler
bogdanm	0:9b334a45a8ff	4050
bogdanm	0:9b334a45a8ff	4051
bogdanm	0:9b334a45a8ff	4052
bogdanm	0:9b334a45a8ff	4053	#define TIM6_IRQHandler TIM6_DAC_IRQHandler
bogdanm	0:9b334a45a8ff	4054
bogdanm	0:9b334a45a8ff	4055
bogdanm	0:9b334a45a8ff	4056	/**
bogdanm	0:9b334a45a8ff	4057	* @}
bogdanm	0:9b334a45a8ff	4058	*/
bogdanm	0:9b334a45a8ff	4059
bogdanm	0:9b334a45a8ff	4060	/**
bogdanm	0:9b334a45a8ff	4061	* @}
bogdanm	0:9b334a45a8ff	4062	*/
bogdanm	0:9b334a45a8ff	4063
bogdanm	0:9b334a45a8ff	4064
bogdanm	0:9b334a45a8ff	4065	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	4066	}
bogdanm	0:9b334a45a8ff	4067	#endif /* __cplusplus */
bogdanm	0:9b334a45a8ff	4068
bogdanm	0:9b334a45a8ff	4069	#endif /* __STM32F100xB_H */
bogdanm	0:9b334a45a8ff	4070
bogdanm	0:9b334a45a8ff	4071
bogdanm	0:9b334a45a8ff	4072
bogdanm	0:9b334a45a8ff	4073	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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