en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
113:b3775bf36a83 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l0xx_hal_smbus.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 113:b3775bf36a83 5 * @version V1.5.0
mbed_official 113:b3775bf36a83 6 * @date 8-January-2016
bogdanm 0:9b334a45a8ff 7 * @brief SMBUS HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the System Management Bus (SMBus) peripheral,
bogdanm 0:9b334a45a8ff 11 * based on I2C principales of operation :
bogdanm 0:9b334a45a8ff 12 * + Initialization/de-initialization functions
bogdanm 0:9b334a45a8ff 13 * + I/O operation functions
bogdanm 0:9b334a45a8ff 14 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 15 * + Peripheral State functions
bogdanm 0:9b334a45a8ff 16 *
bogdanm 0:9b334a45a8ff 17 @verbatim
bogdanm 0:9b334a45a8ff 18 ==============================================================================
bogdanm 0:9b334a45a8ff 19 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 20 ==============================================================================
bogdanm 0:9b334a45a8ff 21 [..]
bogdanm 0:9b334a45a8ff 22 The SMBUS HAL driver can be used as follows:
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
bogdanm 0:9b334a45a8ff 25 SMBUS_HandleTypeDef hsmbus;
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 (#)Initialize the SMBUS low level resources by implement the HAL_SMBUS_MspInit ()API:
bogdanm 0:9b334a45a8ff 28 (##) Enable the SMBUSx interface clock
bogdanm 0:9b334a45a8ff 29 (##) SMBUS pins configuration
bogdanm 0:9b334a45a8ff 30 (+) Enable the clock for the SMBUS GPIOs
bogdanm 0:9b334a45a8ff 31 (+) Configure SMBUS pins as alternate function open-drain
bogdanm 0:9b334a45a8ff 32 (##) NVIC configuration if you need to use interrupt process
bogdanm 0:9b334a45a8ff 33 (+) Configure the SMBUSx interrupt priority
bogdanm 0:9b334a45a8ff 34 (+) Enable the NVIC SMBUS IRQ Channel
bogdanm 0:9b334a45a8ff 35
bogdanm 0:9b334a45a8ff 36 (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Adressing Mode,
bogdanm 0:9b334a45a8ff 37 Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
bogdanm 0:9b334a45a8ff 38 Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
mbed_official 113:b3775bf36a83 41 (+) These API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
bogdanm 0:9b334a45a8ff 42 by calling the customed HAL_SMBUS_MspInit(&hsmbus) API.
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 (#) For SMBUS IO operations, only one mode of operations is available within this driver :
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 *** Interrupt mode IO operation ***
bogdanm 0:9b334a45a8ff 49 ===================================
bogdanm 0:9b334a45a8ff 50 [..]
bogdanm 0:9b334a45a8ff 51 (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Transmit_IT()
bogdanm 0:9b334a45a8ff 52 (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 53 add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback
bogdanm 0:9b334a45a8ff 54 (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Receive_IT()
bogdanm 0:9b334a45a8ff 55 (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 56 add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback
bogdanm 0:9b334a45a8ff 57 (+) Abort a master/host SMBUS process commnunication with Interrupt using HAL_SMBUS_Master_Abort_IT()
bogdanm 0:9b334a45a8ff 58 (++) The associated previous transfer callback is called at the end of abort process
bogdanm 0:9b334a45a8ff 59 (++) mean HAL_SMBUS_MasterTxCpltCallback in case of previous state was master transmit
bogdanm 0:9b334a45a8ff 60 (++) mean HAL_SMBUS_MasterRxCpltCallback in case of previous state was master receive
bogdanm 0:9b334a45a8ff 61 (+) Enable the Address listen mode in slave/device SMBUS mode using HAL_SMBUS_EnableListen_IT()
bogdanm 0:9b334a45a8ff 62 (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback is executed and user can
bogdanm 0:9b334a45a8ff 63 add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
bogdanm 0:9b334a45a8ff 64 (++) At Listen mode end HAL_SMBUS_ListenCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 65 add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback
bogdanm 0:9b334a45a8ff 66 (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Transmit_IT()
bogdanm 0:9b334a45a8ff 67 (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 68 add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback
bogdanm 0:9b334a45a8ff 69 (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Receive_IT()
bogdanm 0:9b334a45a8ff 70 (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 71 add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback
bogdanm 0:9b334a45a8ff 72 (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
bogdanm 0:9b334a45a8ff 73 (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
bogdanm 0:9b334a45a8ff 74 add his own code by customization of function pointer HAL_SMBUS_ErrorCallback
bogdanm 0:9b334a45a8ff 75 to check the Alert Error Code using function HAL_SMBUS_GetError()
bogdanm 0:9b334a45a8ff 76 (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
bogdanm 0:9b334a45a8ff 77 (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
bogdanm 0:9b334a45a8ff 78 add his own code by customization of function pointer HAL_SMBUS_ErrorCallback
bogdanm 0:9b334a45a8ff 79 to check the Error Code using function HAL_SMBUS_GetError()
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 *** SMBUS HAL driver macros list ***
bogdanm 0:9b334a45a8ff 82 ==================================
bogdanm 0:9b334a45a8ff 83 [..]
bogdanm 0:9b334a45a8ff 84 Below the list of most used macros in SMBUS HAL driver.
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
bogdanm 0:9b334a45a8ff 87 (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
bogdanm 0:9b334a45a8ff 88 (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not
bogdanm 0:9b334a45a8ff 89 (+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag
bogdanm 0:9b334a45a8ff 90 (+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt
bogdanm 0:9b334a45a8ff 91 (+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 [..]
bogdanm 0:9b334a45a8ff 94 (@) You can refer to the SMBUS HAL driver header file for more useful macros
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 @endverbatim
bogdanm 0:9b334a45a8ff 98 ******************************************************************************
bogdanm 0:9b334a45a8ff 99 * @attention
bogdanm 0:9b334a45a8ff 100 *
mbed_official 113:b3775bf36a83 101 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 102 *
bogdanm 0:9b334a45a8ff 103 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 104 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 105 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 106 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 108 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 109 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 111 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 112 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 113 *
bogdanm 0:9b334a45a8ff 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 124 *
bogdanm 0:9b334a45a8ff 125 ******************************************************************************
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 129 #include "stm32l0xx_hal.h"
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 0:9b334a45a8ff 132 * @{
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134
mbed_official 113:b3775bf36a83 135
mbed_official 113:b3775bf36a83 136 #ifdef HAL_SMBUS_MODULE_ENABLED
mbed_official 113:b3775bf36a83 137
mbed_official 113:b3775bf36a83 138 /** @addtogroup SMBUS
bogdanm 0:9b334a45a8ff 139 * @brief SMBUS HAL module driver
bogdanm 0:9b334a45a8ff 140 * @{
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /* Private typedef -----------------------------------------------------------*/
mbed_official 113:b3775bf36a83 144 /** @addtogroup SMBUS_Private
mbed_official 113:b3775bf36a83 145 * @{
mbed_official 113:b3775bf36a83 146 */
bogdanm 0:9b334a45a8ff 147 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 148 #define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */
bogdanm 0:9b334a45a8ff 149 #define HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
bogdanm 0:9b334a45a8ff 150 #define HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 151 #define HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 152 #define HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 153 #define HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 154 #define HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 155 #define HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 156 #define HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
bogdanm 0:9b334a45a8ff 157 #define MAX_NBYTE_SIZE 255
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 160 #define __SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
bogdanm 0:9b334a45a8ff 161 #define __SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 164 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 165 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
bogdanm 0:9b334a45a8ff 168 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
bogdanm 0:9b334a45a8ff 169 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
bogdanm 0:9b334a45a8ff 170 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
mbed_official 113:b3775bf36a83 173 /**
mbed_official 113:b3775bf36a83 174 * @}
mbed_official 113:b3775bf36a83 175 */
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 178
mbed_official 113:b3775bf36a83 179 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
bogdanm 0:9b334a45a8ff 180 * @{
bogdanm 0:9b334a45a8ff 181 */
bogdanm 0:9b334a45a8ff 182
mbed_official 113:b3775bf36a83 183 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 184 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 185 *
bogdanm 0:9b334a45a8ff 186 @verbatim
bogdanm 0:9b334a45a8ff 187 ===============================================================================
bogdanm 0:9b334a45a8ff 188 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 189 ===============================================================================
bogdanm 0:9b334a45a8ff 190 [..] This subsection provides a set of functions allowing to initialize and
bogdanm 0:9b334a45a8ff 191 de-initialiaze the SMBUSx peripheral:
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
bogdanm 0:9b334a45a8ff 194 all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 (+) Call the function HAL_SMBUS_Init() to configure the selected device with
bogdanm 0:9b334a45a8ff 197 the selected configuration:
bogdanm 0:9b334a45a8ff 198 (++) Clock Timing
bogdanm 0:9b334a45a8ff 199 (++) Bus Timeout
bogdanm 0:9b334a45a8ff 200 (++) Analog Filer mode
bogdanm 0:9b334a45a8ff 201 (++) Own Address 1
bogdanm 0:9b334a45a8ff 202 (++) Addressing mode (Master, Slave)
bogdanm 0:9b334a45a8ff 203 (++) Dual Addressing mode
bogdanm 0:9b334a45a8ff 204 (++) Own Address 2
bogdanm 0:9b334a45a8ff 205 (++) Own Address 2 Mask
bogdanm 0:9b334a45a8ff 206 (++) General call mode
bogdanm 0:9b334a45a8ff 207 (++) Nostretch mode
bogdanm 0:9b334a45a8ff 208 (++) Packet Error Check mode
bogdanm 0:9b334a45a8ff 209 (++) Peripheral mode
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
bogdanm 0:9b334a45a8ff 212 of the selected SMBUSx periperal.
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 @endverbatim
bogdanm 0:9b334a45a8ff 215 * @{
bogdanm 0:9b334a45a8ff 216 */
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /**
bogdanm 0:9b334a45a8ff 219 * @brief Initializes the SMBUS according to the specified parameters
bogdanm 0:9b334a45a8ff 220 * in the SMBUS_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 221 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 222 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 223 * @retval HAL status
bogdanm 0:9b334a45a8ff 224 */
bogdanm 0:9b334a45a8ff 225 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 226 {
bogdanm 0:9b334a45a8ff 227 /* Check the SMBUS handle allocation */
bogdanm 0:9b334a45a8ff 228 if(hsmbus == NULL)
bogdanm 0:9b334a45a8ff 229 {
bogdanm 0:9b334a45a8ff 230 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 231 }
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /* Check the parameters */
bogdanm 0:9b334a45a8ff 234 assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
bogdanm 0:9b334a45a8ff 235 assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
bogdanm 0:9b334a45a8ff 236 assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
bogdanm 0:9b334a45a8ff 237 assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
bogdanm 0:9b334a45a8ff 238 assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
bogdanm 0:9b334a45a8ff 239 assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
bogdanm 0:9b334a45a8ff 240 assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
bogdanm 0:9b334a45a8ff 241 assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
bogdanm 0:9b334a45a8ff 242 assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
bogdanm 0:9b334a45a8ff 243 assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
bogdanm 0:9b334a45a8ff 244 assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 if(hsmbus->State == HAL_SMBUS_STATE_RESET)
bogdanm 0:9b334a45a8ff 247 {
mbed_official 113:b3775bf36a83 248 /* Allocate lock resource and initialize it */
mbed_official 113:b3775bf36a83 249 hsmbus->Lock = HAL_UNLOCKED;
mbed_official 113:b3775bf36a83 250
bogdanm 0:9b334a45a8ff 251 /* Init the low level hardware : GPIO, CLOCK, NVIC */
bogdanm 0:9b334a45a8ff 252 HAL_SMBUS_MspInit(hsmbus);
bogdanm 0:9b334a45a8ff 253 }
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 hsmbus->State = HAL_SMBUS_STATE_BUSY;
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* Disable the selected SMBUS peripheral */
bogdanm 0:9b334a45a8ff 258 __HAL_SMBUS_DISABLE(hsmbus);
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /*---------------------------- SMBUSx TIMINGR Configuration ----------------*/
bogdanm 0:9b334a45a8ff 261 /* Configure SMBUSx: Frequency range */
bogdanm 0:9b334a45a8ff 262 hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 /*---------------------------- SMBUSx TIMEOUTR Configuration ---------------*/
bogdanm 0:9b334a45a8ff 265 /* Configure SMBUSx: Bus Timeout */
bogdanm 0:9b334a45a8ff 266 hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 /*---------------------------- SMBUSx OAR1 Configuration -------------------*/
bogdanm 0:9b334a45a8ff 269 /* Configure SMBUSx: Own Address1 and ack own address1 mode */
bogdanm 0:9b334a45a8ff 270 hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
bogdanm 0:9b334a45a8ff 271 if(hsmbus->Init.OwnAddress1 != 0)
bogdanm 0:9b334a45a8ff 272 {
bogdanm 0:9b334a45a8ff 273 if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
bogdanm 0:9b334a45a8ff 274 {
bogdanm 0:9b334a45a8ff 275 hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
bogdanm 0:9b334a45a8ff 276 }
bogdanm 0:9b334a45a8ff 277 else /* SMBUS_ADDRESSINGMODE_10BIT */
bogdanm 0:9b334a45a8ff 278 {
bogdanm 0:9b334a45a8ff 279 hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
bogdanm 0:9b334a45a8ff 280 }
bogdanm 0:9b334a45a8ff 281 }
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /*---------------------------- SMBUSx CR2 Configuration --------------------*/
bogdanm 0:9b334a45a8ff 284 /* Configure SMBUSx: Addressing Master mode */
bogdanm 0:9b334a45a8ff 285 if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
bogdanm 0:9b334a45a8ff 286 {
bogdanm 0:9b334a45a8ff 287 hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
bogdanm 0:9b334a45a8ff 288 }
bogdanm 0:9b334a45a8ff 289 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
bogdanm 0:9b334a45a8ff 290 /* AUTOEND and NACK bit will be manage during Transfer process */
bogdanm 0:9b334a45a8ff 291 hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
bogdanm 0:9b334a45a8ff 294 /* Configure SMBUSx: Dual mode and Own Address2 */
bogdanm 0:9b334a45a8ff 295 hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8));
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 298 /* Configure SMBUSx: Generalcall and NoStretch mode */
bogdanm 0:9b334a45a8ff 299 hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
bogdanm 0:9b334a45a8ff 302 if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
bogdanm 0:9b334a45a8ff 303 && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
bogdanm 0:9b334a45a8ff 304 {
bogdanm 0:9b334a45a8ff 305 hsmbus->Instance->CR1 |= I2C_CR1_SBC;
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /* Enable the selected SMBUS peripheral */
bogdanm 0:9b334a45a8ff 309 __HAL_SMBUS_ENABLE(hsmbus);
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 312 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 313 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 return HAL_OK;
bogdanm 0:9b334a45a8ff 316 }
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 /**
bogdanm 0:9b334a45a8ff 319 * @brief DeInitializes the SMBUS peripheral.
bogdanm 0:9b334a45a8ff 320 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 321 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 322 * @retval HAL status
bogdanm 0:9b334a45a8ff 323 */
bogdanm 0:9b334a45a8ff 324 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 325 {
bogdanm 0:9b334a45a8ff 326 /* Check the SMBUS handle allocation */
bogdanm 0:9b334a45a8ff 327 if(hsmbus == NULL)
bogdanm 0:9b334a45a8ff 328 {
bogdanm 0:9b334a45a8ff 329 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 330 }
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /* Check the parameters */
bogdanm 0:9b334a45a8ff 333 assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 hsmbus->State = HAL_SMBUS_STATE_BUSY;
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 /* Disable the SMBUS Peripheral Clock */
bogdanm 0:9b334a45a8ff 338 __HAL_SMBUS_DISABLE(hsmbus);
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm 0:9b334a45a8ff 341 HAL_SMBUS_MspDeInit(hsmbus);
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 344 hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
bogdanm 0:9b334a45a8ff 345 hsmbus->State = HAL_SMBUS_STATE_RESET;
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /* Release Lock */
bogdanm 0:9b334a45a8ff 348 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 return HAL_OK;
bogdanm 0:9b334a45a8ff 351 }
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 /**
bogdanm 0:9b334a45a8ff 354 * @brief SMBUS MSP Init.
bogdanm 0:9b334a45a8ff 355 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 356 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 357 * @retval None
bogdanm 0:9b334a45a8ff 358 */
bogdanm 0:9b334a45a8ff 359 __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 360 {
mbed_official 113:b3775bf36a83 361 /* Prevent unused argument(s) compilation warning */
mbed_official 113:b3775bf36a83 362 UNUSED(hsmbus);
mbed_official 113:b3775bf36a83 363
bogdanm 0:9b334a45a8ff 364 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 365 the HAL_SMBUS_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 366 */
bogdanm 0:9b334a45a8ff 367 }
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 /**
bogdanm 0:9b334a45a8ff 370 * @brief SMBUS MSP DeInit
bogdanm 0:9b334a45a8ff 371 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 372 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 373 * @retval None
bogdanm 0:9b334a45a8ff 374 */
bogdanm 0:9b334a45a8ff 375 __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 376 {
mbed_official 113:b3775bf36a83 377 /* Prevent unused argument(s) compilation warning */
mbed_official 113:b3775bf36a83 378 UNUSED(hsmbus);
mbed_official 113:b3775bf36a83 379
bogdanm 0:9b334a45a8ff 380 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 381 the HAL_SMBUS_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 382 */
bogdanm 0:9b334a45a8ff 383 }
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 /**
bogdanm 0:9b334a45a8ff 386 * @}
bogdanm 0:9b334a45a8ff 387 */
bogdanm 0:9b334a45a8ff 388
mbed_official 113:b3775bf36a83 389 /** @addtogroup SMBUS_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 390 * @brief Data transfers functions
bogdanm 0:9b334a45a8ff 391 *
bogdanm 0:9b334a45a8ff 392 @verbatim
bogdanm 0:9b334a45a8ff 393 ===============================================================================
bogdanm 0:9b334a45a8ff 394 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 395 ===============================================================================
bogdanm 0:9b334a45a8ff 396 [..]
bogdanm 0:9b334a45a8ff 397 This subsection provides a set of functions allowing to manage the SMBUS data
bogdanm 0:9b334a45a8ff 398 transfers.
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400 (#) Blocking mode function to check if device is ready for usage is :
bogdanm 0:9b334a45a8ff 401 (++) HAL_SMBUS_IsDeviceReady()
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 (#) There is only one mode of transfer:
bogdanm 0:9b334a45a8ff 404 (++) No-Blocking mode : The communication is performed using Interrupts.
bogdanm 0:9b334a45a8ff 405 These functions return the status of the transfer startup.
bogdanm 0:9b334a45a8ff 406 The end of the data processing will be indicated through the
bogdanm 0:9b334a45a8ff 407 dedicated SMBUS IRQ when using Interrupt mode.
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 (#) No-Blocking mode functions with Interrupt are :
bogdanm 0:9b334a45a8ff 410 (++) HAL_SMBUS_Master_Transmit_IT()
bogdanm 0:9b334a45a8ff 411 (++) HAL_SMBUS_Master_Receive_IT()
bogdanm 0:9b334a45a8ff 412 (++) HAL_SMBUS_Slave_Transmit_IT()
bogdanm 0:9b334a45a8ff 413 (++) HAL_SMBUS_Slave_Receive_IT()
bogdanm 0:9b334a45a8ff 414 (++) HAL_SMBUS_EnableListen_IT()
bogdanm 0:9b334a45a8ff 415 (++) HAL_SMBUS_EnableAlert_IT()
bogdanm 0:9b334a45a8ff 416 (++) HAL_SMBUS_DisableAlert_IT()
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
bogdanm 0:9b334a45a8ff 419 (++) HAL_SMBUS_MasterTxCpltCallback()
bogdanm 0:9b334a45a8ff 420 (++) HAL_SMBUS_MasterRxCpltCallback()
bogdanm 0:9b334a45a8ff 421 (++) HAL_SMBUS_SlaveTxCpltCallback()
bogdanm 0:9b334a45a8ff 422 (++) HAL_SMBUS_SlaveRxCpltCallback()
bogdanm 0:9b334a45a8ff 423 (++) HAL_SMBUS_AddrCallback()
bogdanm 0:9b334a45a8ff 424 (++) HAL_SMBUS_ListenCpltCallback()
bogdanm 0:9b334a45a8ff 425 (++) HAL_SMBUS_ErrorCallback()
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 @endverbatim
bogdanm 0:9b334a45a8ff 428 * @{
bogdanm 0:9b334a45a8ff 429 */
bogdanm 0:9b334a45a8ff 430
bogdanm 0:9b334a45a8ff 431 /**
bogdanm 0:9b334a45a8ff 432 * @brief Transmit in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 433 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 434 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 435 * @param DevAddress: Target device address
bogdanm 0:9b334a45a8ff 436 * @param pData: Pointer to data buffer
bogdanm 0:9b334a45a8ff 437 * @param Size: Amount of data to be sent
bogdanm 0:9b334a45a8ff 438 * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm 0:9b334a45a8ff 439 * @retval HAL status
bogdanm 0:9b334a45a8ff 440 */
bogdanm 0:9b334a45a8ff 441 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
bogdanm 0:9b334a45a8ff 442 {
bogdanm 0:9b334a45a8ff 443 /* Check the parameters */
bogdanm 0:9b334a45a8ff 444 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm 0:9b334a45a8ff 447 {
bogdanm 0:9b334a45a8ff 448 /* Process Locked */
bogdanm 0:9b334a45a8ff 449 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 450
bogdanm 0:9b334a45a8ff 451 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
bogdanm 0:9b334a45a8ff 452 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 453 /* Prepare transfer parameters */
bogdanm 0:9b334a45a8ff 454 hsmbus->pBuffPtr = pData;
bogdanm 0:9b334a45a8ff 455 hsmbus->XferCount = Size;
bogdanm 0:9b334a45a8ff 456 hsmbus->XferOptions = XferOptions;
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 /* In case of Quick command, remove autoend mode */
bogdanm 0:9b334a45a8ff 459 /* Manage the stop generation by software */
bogdanm 0:9b334a45a8ff 460 if(hsmbus->pBuffPtr == NULL)
bogdanm 0:9b334a45a8ff 461 {
bogdanm 0:9b334a45a8ff 462 hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
bogdanm 0:9b334a45a8ff 463 }
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 if(Size > MAX_NBYTE_SIZE)
bogdanm 0:9b334a45a8ff 466 {
bogdanm 0:9b334a45a8ff 467 hsmbus->XferSize = MAX_NBYTE_SIZE;
bogdanm 0:9b334a45a8ff 468 }
bogdanm 0:9b334a45a8ff 469 else
bogdanm 0:9b334a45a8ff 470 {
bogdanm 0:9b334a45a8ff 471 hsmbus->XferSize = Size;
bogdanm 0:9b334a45a8ff 472 }
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 /* Send Slave Address */
bogdanm 0:9b334a45a8ff 475 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
bogdanm 0:9b334a45a8ff 476 if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
bogdanm 0:9b334a45a8ff 477 {
bogdanm 0:9b334a45a8ff 478 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE, SMBUS_GENERATE_START_WRITE);
bogdanm 0:9b334a45a8ff 479 }
bogdanm 0:9b334a45a8ff 480 else
bogdanm 0:9b334a45a8ff 481 {
bogdanm 0:9b334a45a8ff 482 /* If transfer direction not change, do not generate Restart Condition */
bogdanm 0:9b334a45a8ff 483 /* Mean Previous state is same as current state */
bogdanm 0:9b334a45a8ff 484 if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 485 {
bogdanm 0:9b334a45a8ff 486 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 487 }
bogdanm 0:9b334a45a8ff 488 /* Else transfer direction change, so generate Restart with new transfer direction */
bogdanm 0:9b334a45a8ff 489 else
bogdanm 0:9b334a45a8ff 490 {
bogdanm 0:9b334a45a8ff 491 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
bogdanm 0:9b334a45a8ff 492 }
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
bogdanm 0:9b334a45a8ff 495 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
bogdanm 0:9b334a45a8ff 496 if(__SMBUS_GET_PEC_MODE(hsmbus) != RESET)
bogdanm 0:9b334a45a8ff 497 {
bogdanm 0:9b334a45a8ff 498 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 499 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 500 }
bogdanm 0:9b334a45a8ff 501 }
bogdanm 0:9b334a45a8ff 502
bogdanm 0:9b334a45a8ff 503 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 504 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 /* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm 0:9b334a45a8ff 507 to avoid the risk of SMBUS interrupt handle execution before current
bogdanm 0:9b334a45a8ff 508 process unlock */
bogdanm 0:9b334a45a8ff 509 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 return HAL_OK;
bogdanm 0:9b334a45a8ff 512 }
bogdanm 0:9b334a45a8ff 513 else
bogdanm 0:9b334a45a8ff 514 {
bogdanm 0:9b334a45a8ff 515 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 516 }
bogdanm 0:9b334a45a8ff 517 }
bogdanm 0:9b334a45a8ff 518
bogdanm 0:9b334a45a8ff 519 /**
bogdanm 0:9b334a45a8ff 520 * @brief Receive in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 521 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 522 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 523 * @param DevAddress: Target device address
bogdanm 0:9b334a45a8ff 524 * @param pData: Pointer to data buffer
bogdanm 0:9b334a45a8ff 525 * @param Size: Amount of data to be sent
bogdanm 0:9b334a45a8ff 526 * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm 0:9b334a45a8ff 527 * @retval HAL status
bogdanm 0:9b334a45a8ff 528 */
bogdanm 0:9b334a45a8ff 529 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
bogdanm 0:9b334a45a8ff 530 {
bogdanm 0:9b334a45a8ff 531 /* Check the parameters */
bogdanm 0:9b334a45a8ff 532 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm 0:9b334a45a8ff 535 {
bogdanm 0:9b334a45a8ff 536 /* Process Locked */
bogdanm 0:9b334a45a8ff 537 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
bogdanm 0:9b334a45a8ff 540 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /* Prepare transfer parameters */
bogdanm 0:9b334a45a8ff 543 hsmbus->pBuffPtr = pData;
bogdanm 0:9b334a45a8ff 544 hsmbus->XferCount = Size;
bogdanm 0:9b334a45a8ff 545 hsmbus->XferOptions = XferOptions;
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 /* In case of Quick command, remove autoend mode */
bogdanm 0:9b334a45a8ff 548 /* Manage the stop generation by software */
bogdanm 0:9b334a45a8ff 549 if(hsmbus->pBuffPtr == NULL)
bogdanm 0:9b334a45a8ff 550 {
bogdanm 0:9b334a45a8ff 551 hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
bogdanm 0:9b334a45a8ff 552 }
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 if(Size > MAX_NBYTE_SIZE)
bogdanm 0:9b334a45a8ff 555 {
bogdanm 0:9b334a45a8ff 556 hsmbus->XferSize = MAX_NBYTE_SIZE;
bogdanm 0:9b334a45a8ff 557 }
bogdanm 0:9b334a45a8ff 558 else
bogdanm 0:9b334a45a8ff 559 {
bogdanm 0:9b334a45a8ff 560 hsmbus->XferSize = Size;
bogdanm 0:9b334a45a8ff 561 }
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 /* Send Slave Address */
bogdanm 0:9b334a45a8ff 564 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
bogdanm 0:9b334a45a8ff 565 if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
bogdanm 0:9b334a45a8ff 566 {
bogdanm 0:9b334a45a8ff 567 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE, SMBUS_GENERATE_START_READ);
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569 else
bogdanm 0:9b334a45a8ff 570 {
bogdanm 0:9b334a45a8ff 571 /* If transfer direction not change, do not generate Restart Condition */
bogdanm 0:9b334a45a8ff 572 /* Mean Previous state is same as current state */
bogdanm 0:9b334a45a8ff 573 if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 574 {
bogdanm 0:9b334a45a8ff 575 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 576 }
bogdanm 0:9b334a45a8ff 577 /* Else transfer direction change, so generate Restart with new transfer direction */
bogdanm 0:9b334a45a8ff 578 else
bogdanm 0:9b334a45a8ff 579 {
bogdanm 0:9b334a45a8ff 580 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
bogdanm 0:9b334a45a8ff 581 }
bogdanm 0:9b334a45a8ff 582 }
bogdanm 0:9b334a45a8ff 583
bogdanm 0:9b334a45a8ff 584 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 585 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 586
bogdanm 0:9b334a45a8ff 587 /* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm 0:9b334a45a8ff 588 to avoid the risk of SMBUS interrupt handle execution before current
bogdanm 0:9b334a45a8ff 589 process unlock */
bogdanm 0:9b334a45a8ff 590 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 return HAL_OK;
bogdanm 0:9b334a45a8ff 593 }
bogdanm 0:9b334a45a8ff 594 else
bogdanm 0:9b334a45a8ff 595 {
bogdanm 0:9b334a45a8ff 596 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 597 }
bogdanm 0:9b334a45a8ff 598 }
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 /**
bogdanm 0:9b334a45a8ff 601 * @brief Abort a master/host SMBUS process commnunication with Interrupt
bogdanm 0:9b334a45a8ff 602 * @note : This abort can be called only if state is ready
bogdanm 0:9b334a45a8ff 603 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 604 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 605 * @param DevAddress: Target device address
bogdanm 0:9b334a45a8ff 606 * @retval HAL status
bogdanm 0:9b334a45a8ff 607 */
bogdanm 0:9b334a45a8ff 608 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
bogdanm 0:9b334a45a8ff 609 {
bogdanm 0:9b334a45a8ff 610 if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm 0:9b334a45a8ff 611 {
bogdanm 0:9b334a45a8ff 612 /* Process Locked */
bogdanm 0:9b334a45a8ff 613 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 614
bogdanm 0:9b334a45a8ff 615 /* Keep the same state as previous */
bogdanm 0:9b334a45a8ff 616 /* to perform as well the call of the corresponding end of transfer callback */
bogdanm 0:9b334a45a8ff 617 if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 618 {
bogdanm 0:9b334a45a8ff 619 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
bogdanm 0:9b334a45a8ff 620 }
bogdanm 0:9b334a45a8ff 621 else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 622 {
bogdanm 0:9b334a45a8ff 623 hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
bogdanm 0:9b334a45a8ff 624 }
bogdanm 0:9b334a45a8ff 625 else
bogdanm 0:9b334a45a8ff 626 {
bogdanm 0:9b334a45a8ff 627 /* Wrong usage of abort function */
bogdanm 0:9b334a45a8ff 628 /* This function should be used only in case of abort monitored by master device */
bogdanm 0:9b334a45a8ff 629 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 630 }
bogdanm 0:9b334a45a8ff 631 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 632
bogdanm 0:9b334a45a8ff 633 /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
bogdanm 0:9b334a45a8ff 634 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
bogdanm 0:9b334a45a8ff 635 SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 638 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 /* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm 0:9b334a45a8ff 641 to avoid the risk of SMBUS interrupt handle execution before current
bogdanm 0:9b334a45a8ff 642 process unlock */
bogdanm 0:9b334a45a8ff 643 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 644 {
bogdanm 0:9b334a45a8ff 645 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 646 }
bogdanm 0:9b334a45a8ff 647 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 648 {
bogdanm 0:9b334a45a8ff 649 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 650 }
bogdanm 0:9b334a45a8ff 651
bogdanm 0:9b334a45a8ff 652 return HAL_OK;
bogdanm 0:9b334a45a8ff 653 }
bogdanm 0:9b334a45a8ff 654 else
bogdanm 0:9b334a45a8ff 655 {
bogdanm 0:9b334a45a8ff 656 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 657 }
bogdanm 0:9b334a45a8ff 658 }
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660 /**
bogdanm 0:9b334a45a8ff 661 * @brief Transmit in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 662 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 663 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 664 * @param pData: Pointer to data buffer
bogdanm 0:9b334a45a8ff 665 * @param Size: Amount of data to be sent
bogdanm 0:9b334a45a8ff 666 * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm 0:9b334a45a8ff 667 * @retval HAL status
bogdanm 0:9b334a45a8ff 668 */
bogdanm 0:9b334a45a8ff 669 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
bogdanm 0:9b334a45a8ff 670 {
bogdanm 0:9b334a45a8ff 671 /* Check the parameters */
bogdanm 0:9b334a45a8ff 672 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 675 {
bogdanm 0:9b334a45a8ff 676 if((pData == NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 677 {
bogdanm 0:9b334a45a8ff 678 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 679 }
bogdanm 0:9b334a45a8ff 680
bogdanm 0:9b334a45a8ff 681 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
bogdanm 0:9b334a45a8ff 682 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 /* Process Locked */
bogdanm 0:9b334a45a8ff 685 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 686
bogdanm 0:9b334a45a8ff 687 hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
bogdanm 0:9b334a45a8ff 688 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 /* Enable Address Acknowledge */
bogdanm 0:9b334a45a8ff 691 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm 0:9b334a45a8ff 692
bogdanm 0:9b334a45a8ff 693 /* Prepare transfer parameters */
bogdanm 0:9b334a45a8ff 694 hsmbus->pBuffPtr = pData;
bogdanm 0:9b334a45a8ff 695 hsmbus->XferSize = Size;
bogdanm 0:9b334a45a8ff 696 hsmbus->XferCount = Size;
bogdanm 0:9b334a45a8ff 697 hsmbus->XferOptions = XferOptions;
bogdanm 0:9b334a45a8ff 698
bogdanm 0:9b334a45a8ff 699 /* Set NBYTE to transmit */
bogdanm 0:9b334a45a8ff 700 SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 701
bogdanm 0:9b334a45a8ff 702 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
bogdanm 0:9b334a45a8ff 703 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
bogdanm 0:9b334a45a8ff 704 if(__SMBUS_GET_PEC_MODE(hsmbus) != RESET)
bogdanm 0:9b334a45a8ff 705 {
bogdanm 0:9b334a45a8ff 706 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 707 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 708 }
bogdanm 0:9b334a45a8ff 709
bogdanm 0:9b334a45a8ff 710 /* Clear ADDR flag after prepare the transfer parameters */
bogdanm 0:9b334a45a8ff 711 /* This action will generate an acknowledge to the HOST */
bogdanm 0:9b334a45a8ff 712 __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
bogdanm 0:9b334a45a8ff 713
bogdanm 0:9b334a45a8ff 714 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 715 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 716
bogdanm 0:9b334a45a8ff 717 /* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm 0:9b334a45a8ff 718 to avoid the risk of SMBUS interrupt handle execution before current
bogdanm 0:9b334a45a8ff 719 process unlock */
bogdanm 0:9b334a45a8ff 720 /* REnable ADDR interrupt */
bogdanm 0:9b334a45a8ff 721 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
bogdanm 0:9b334a45a8ff 722
bogdanm 0:9b334a45a8ff 723 return HAL_OK;
bogdanm 0:9b334a45a8ff 724 }
bogdanm 0:9b334a45a8ff 725 else
bogdanm 0:9b334a45a8ff 726 {
bogdanm 0:9b334a45a8ff 727 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 728 }
bogdanm 0:9b334a45a8ff 729 }
bogdanm 0:9b334a45a8ff 730
bogdanm 0:9b334a45a8ff 731 /**
bogdanm 0:9b334a45a8ff 732 * @brief Receive in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 733 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 734 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 735 * @param pData: Pointer to data buffer
bogdanm 0:9b334a45a8ff 736 * @param Size: Amount of data to be sent
bogdanm 0:9b334a45a8ff 737 * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm 0:9b334a45a8ff 738 * @retval HAL status
bogdanm 0:9b334a45a8ff 739 */
bogdanm 0:9b334a45a8ff 740 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
bogdanm 0:9b334a45a8ff 741 {
bogdanm 0:9b334a45a8ff 742 /* Check the parameters */
bogdanm 0:9b334a45a8ff 743 assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 746 {
bogdanm 0:9b334a45a8ff 747 if((pData == NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 748 {
bogdanm 0:9b334a45a8ff 749 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 750 }
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
bogdanm 0:9b334a45a8ff 753 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 754
bogdanm 0:9b334a45a8ff 755 /* Process Locked */
bogdanm 0:9b334a45a8ff 756 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 757
bogdanm 0:9b334a45a8ff 758 hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
bogdanm 0:9b334a45a8ff 759 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 760
bogdanm 0:9b334a45a8ff 761 /* Enable Address Acknowledge */
bogdanm 0:9b334a45a8ff 762 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm 0:9b334a45a8ff 763
bogdanm 0:9b334a45a8ff 764 /* Prepare transfer parameters */
bogdanm 0:9b334a45a8ff 765 hsmbus->pBuffPtr = pData;
bogdanm 0:9b334a45a8ff 766 hsmbus->XferSize = Size;
bogdanm 0:9b334a45a8ff 767 hsmbus->XferCount = Size;
bogdanm 0:9b334a45a8ff 768 hsmbus->XferOptions = XferOptions;
bogdanm 0:9b334a45a8ff 769
bogdanm 0:9b334a45a8ff 770 /* Set NBYTE to receive */
bogdanm 0:9b334a45a8ff 771 /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
bogdanm 0:9b334a45a8ff 772 /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
bogdanm 0:9b334a45a8ff 773 /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
bogdanm 0:9b334a45a8ff 774 /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
bogdanm 0:9b334a45a8ff 775 if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (__SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
bogdanm 0:9b334a45a8ff 776 {
bogdanm 0:9b334a45a8ff 777 SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 778 }
bogdanm 0:9b334a45a8ff 779 else
bogdanm 0:9b334a45a8ff 780 {
bogdanm 0:9b334a45a8ff 781 SMBUS_TransferConfig(hsmbus,0,/*hsmbus->XferSize*/1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 782 }
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 /* Clear ADDR flag after prepare the transfer parameters */
bogdanm 0:9b334a45a8ff 785 /* This action will generate an acknowledge to the HOST */
bogdanm 0:9b334a45a8ff 786 __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
bogdanm 0:9b334a45a8ff 787
bogdanm 0:9b334a45a8ff 788 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 789 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 790
bogdanm 0:9b334a45a8ff 791 /* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm 0:9b334a45a8ff 792 to avoid the risk of SMBUS interrupt handle execution before current
bogdanm 0:9b334a45a8ff 793 process unlock */
bogdanm 0:9b334a45a8ff 794 /* REnable ADDR interrupt */
bogdanm 0:9b334a45a8ff 795 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
bogdanm 0:9b334a45a8ff 796
bogdanm 0:9b334a45a8ff 797 return HAL_OK;
bogdanm 0:9b334a45a8ff 798 }
bogdanm 0:9b334a45a8ff 799 else
bogdanm 0:9b334a45a8ff 800 {
bogdanm 0:9b334a45a8ff 801 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 802 }
bogdanm 0:9b334a45a8ff 803 }
bogdanm 0:9b334a45a8ff 804 /**
bogdanm 0:9b334a45a8ff 805 * @brief This function enable the Address listen mode in Slave mode
bogdanm 0:9b334a45a8ff 806 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 807 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 808 * @retval HAL status
bogdanm 0:9b334a45a8ff 809 */
bogdanm 0:9b334a45a8ff 810 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 811 {
bogdanm 0:9b334a45a8ff 812 hsmbus->State = HAL_SMBUS_STATE_LISTEN;
bogdanm 0:9b334a45a8ff 813
bogdanm 0:9b334a45a8ff 814 /* Enable the Address Match interrupt */
bogdanm 0:9b334a45a8ff 815 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
bogdanm 0:9b334a45a8ff 816
bogdanm 0:9b334a45a8ff 817 return HAL_OK;
bogdanm 0:9b334a45a8ff 818 }
bogdanm 0:9b334a45a8ff 819
bogdanm 0:9b334a45a8ff 820 /**
bogdanm 0:9b334a45a8ff 821 * @brief This function disable the Address listen mode
bogdanm 0:9b334a45a8ff 822 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 823 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 824 * @retval HAL status
bogdanm 0:9b334a45a8ff 825 */
bogdanm 0:9b334a45a8ff 826 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 827 {
bogdanm 0:9b334a45a8ff 828 /* Disable Address listen mode only if a transfer is not ongoing */
bogdanm 0:9b334a45a8ff 829 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 830 {
bogdanm 0:9b334a45a8ff 831 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 832
bogdanm 0:9b334a45a8ff 833 /* Disable the Address Match interrupt */
bogdanm 0:9b334a45a8ff 834 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
bogdanm 0:9b334a45a8ff 835
bogdanm 0:9b334a45a8ff 836 return HAL_OK;
bogdanm 0:9b334a45a8ff 837 }
bogdanm 0:9b334a45a8ff 838 else
bogdanm 0:9b334a45a8ff 839 {
bogdanm 0:9b334a45a8ff 840 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 841 }
bogdanm 0:9b334a45a8ff 842 }
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 /**
bogdanm 0:9b334a45a8ff 845 * @brief Enable SMBUS alert.
bogdanm 0:9b334a45a8ff 846 * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 847 * the configuration information for the specified SMBUSx peripheral.
bogdanm 0:9b334a45a8ff 848 * @retval HAL status
bogdanm 0:9b334a45a8ff 849 */
bogdanm 0:9b334a45a8ff 850 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 851 {
bogdanm 0:9b334a45a8ff 852 /* Enable SMBus alert */
bogdanm 0:9b334a45a8ff 853 hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
bogdanm 0:9b334a45a8ff 854
bogdanm 0:9b334a45a8ff 855 /* Clear ALERT flag */
bogdanm 0:9b334a45a8ff 856 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
bogdanm 0:9b334a45a8ff 857
bogdanm 0:9b334a45a8ff 858 /* Enable Alert Interrupt */
bogdanm 0:9b334a45a8ff 859 SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
bogdanm 0:9b334a45a8ff 860
bogdanm 0:9b334a45a8ff 861 return HAL_OK;
bogdanm 0:9b334a45a8ff 862 }
bogdanm 0:9b334a45a8ff 863 /**
bogdanm 0:9b334a45a8ff 864 * @brief Disable SMBUS alert.
bogdanm 0:9b334a45a8ff 865 * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 866 * the configuration information for the specified SMBUSx peripheral.
bogdanm 0:9b334a45a8ff 867 * @retval HAL status
bogdanm 0:9b334a45a8ff 868 */
bogdanm 0:9b334a45a8ff 869 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 870 {
bogdanm 0:9b334a45a8ff 871 /* Enable SMBus alert */
bogdanm 0:9b334a45a8ff 872 hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
bogdanm 0:9b334a45a8ff 873
bogdanm 0:9b334a45a8ff 874 /* Disable Alert Interrupt */
bogdanm 0:9b334a45a8ff 875 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
bogdanm 0:9b334a45a8ff 876
bogdanm 0:9b334a45a8ff 877 return HAL_OK;
bogdanm 0:9b334a45a8ff 878 }
bogdanm 0:9b334a45a8ff 879 /**
bogdanm 0:9b334a45a8ff 880 * @brief Checks if target device is ready for communication.
bogdanm 0:9b334a45a8ff 881 * @note This function is used with Memory devices
bogdanm 0:9b334a45a8ff 882 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 883 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 884 * @param DevAddress: Target device address
bogdanm 0:9b334a45a8ff 885 * @param Trials: Number of trials
bogdanm 0:9b334a45a8ff 886 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 887 * @retval HAL status
bogdanm 0:9b334a45a8ff 888 */
bogdanm 0:9b334a45a8ff 889 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 890 {
bogdanm 0:9b334a45a8ff 891 uint32_t tickstart = 0x00;
bogdanm 0:9b334a45a8ff 892 __IO uint32_t SMBUS_Trials = 0x00;
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm 0:9b334a45a8ff 895 {
bogdanm 0:9b334a45a8ff 896 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
bogdanm 0:9b334a45a8ff 897 {
bogdanm 0:9b334a45a8ff 898 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 899 }
bogdanm 0:9b334a45a8ff 900
bogdanm 0:9b334a45a8ff 901 /* Process Locked */
bogdanm 0:9b334a45a8ff 902 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 903
bogdanm 0:9b334a45a8ff 904 hsmbus->State = HAL_SMBUS_STATE_BUSY;
bogdanm 0:9b334a45a8ff 905 hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm 0:9b334a45a8ff 906
bogdanm 0:9b334a45a8ff 907 do
bogdanm 0:9b334a45a8ff 908 {
bogdanm 0:9b334a45a8ff 909 /* Generate Start */
bogdanm 0:9b334a45a8ff 910 hsmbus->Instance->CR2 = __SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
bogdanm 0:9b334a45a8ff 911
bogdanm 0:9b334a45a8ff 912 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm 0:9b334a45a8ff 913 /* Wait until STOPF flag is set or a NACK flag is set*/
bogdanm 0:9b334a45a8ff 914 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 915 while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
bogdanm 0:9b334a45a8ff 916 {
bogdanm 0:9b334a45a8ff 917 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 918 {
bogdanm 0:9b334a45a8ff 919 hsmbus->State = HAL_SMBUS_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 920 }
bogdanm 0:9b334a45a8ff 921 }
bogdanm 0:9b334a45a8ff 922
bogdanm 0:9b334a45a8ff 923 /* Check if the NACKF flag has not been set */
bogdanm 0:9b334a45a8ff 924 if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
bogdanm 0:9b334a45a8ff 925 {
bogdanm 0:9b334a45a8ff 926 /* Wait until STOPF flag is reset */
bogdanm 0:9b334a45a8ff 927 if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 928 {
bogdanm 0:9b334a45a8ff 929 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 930 }
bogdanm 0:9b334a45a8ff 931
bogdanm 0:9b334a45a8ff 932 /* Clear STOP Flag */
bogdanm 0:9b334a45a8ff 933 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 934
bogdanm 0:9b334a45a8ff 935 /* Device is ready */
bogdanm 0:9b334a45a8ff 936 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 937
bogdanm 0:9b334a45a8ff 938 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 939 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 940
bogdanm 0:9b334a45a8ff 941 return HAL_OK;
bogdanm 0:9b334a45a8ff 942 }
bogdanm 0:9b334a45a8ff 943 else
bogdanm 0:9b334a45a8ff 944 {
bogdanm 0:9b334a45a8ff 945 /* Wait until STOPF flag is reset */
bogdanm 0:9b334a45a8ff 946 if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 947 {
bogdanm 0:9b334a45a8ff 948 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 949 }
bogdanm 0:9b334a45a8ff 950
bogdanm 0:9b334a45a8ff 951 /* Clear NACK Flag */
bogdanm 0:9b334a45a8ff 952 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm 0:9b334a45a8ff 953
bogdanm 0:9b334a45a8ff 954 /* Clear STOP Flag, auto generated with autoend*/
bogdanm 0:9b334a45a8ff 955 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 956 }
bogdanm 0:9b334a45a8ff 957
bogdanm 0:9b334a45a8ff 958 /* Check if the maximum allowed numbe of trials has bee reached */
bogdanm 0:9b334a45a8ff 959 if (SMBUS_Trials++ == Trials)
bogdanm 0:9b334a45a8ff 960 {
bogdanm 0:9b334a45a8ff 961 /* Generate Stop */
bogdanm 0:9b334a45a8ff 962 hsmbus->Instance->CR2 |= I2C_CR2_STOP;
bogdanm 0:9b334a45a8ff 963
bogdanm 0:9b334a45a8ff 964 /* Wait until STOPF flag is reset */
bogdanm 0:9b334a45a8ff 965 if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 966 {
bogdanm 0:9b334a45a8ff 967 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 968 }
bogdanm 0:9b334a45a8ff 969
bogdanm 0:9b334a45a8ff 970 /* Clear STOP Flag */
bogdanm 0:9b334a45a8ff 971 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 972 }
bogdanm 0:9b334a45a8ff 973 }while(SMBUS_Trials++ < Trials);
bogdanm 0:9b334a45a8ff 974
bogdanm 0:9b334a45a8ff 975 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 976
bogdanm 0:9b334a45a8ff 977 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 978 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 979
bogdanm 0:9b334a45a8ff 980 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 981 }
bogdanm 0:9b334a45a8ff 982 else
bogdanm 0:9b334a45a8ff 983 {
bogdanm 0:9b334a45a8ff 984 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 985 }
bogdanm 0:9b334a45a8ff 986 }
bogdanm 0:9b334a45a8ff 987
bogdanm 0:9b334a45a8ff 988 /**
bogdanm 0:9b334a45a8ff 989 * @brief This function handles SMBUS event interrupt request.
bogdanm 0:9b334a45a8ff 990 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 991 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 992 * @retval None
bogdanm 0:9b334a45a8ff 993 */
bogdanm 0:9b334a45a8ff 994 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 995 {
bogdanm 0:9b334a45a8ff 996 uint32_t tmpisrvalue = 0;
bogdanm 0:9b334a45a8ff 997
bogdanm 0:9b334a45a8ff 998 /* Use a local variable to store the current ISR flags */
bogdanm 0:9b334a45a8ff 999 /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
bogdanm 0:9b334a45a8ff 1000 tmpisrvalue = __SMBUS_GET_ISR_REG(hsmbus);
bogdanm 0:9b334a45a8ff 1001
bogdanm 0:9b334a45a8ff 1002 /* SMBUS in mode Transmitter ---------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1003 if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
bogdanm 0:9b334a45a8ff 1004 {
bogdanm 0:9b334a45a8ff 1005 /* Slave mode selected */
bogdanm 0:9b334a45a8ff 1006 if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
bogdanm 0:9b334a45a8ff 1007 {
bogdanm 0:9b334a45a8ff 1008 SMBUS_Slave_ISR(hsmbus);
bogdanm 0:9b334a45a8ff 1009 }
bogdanm 0:9b334a45a8ff 1010 /* Master mode selected */
bogdanm 0:9b334a45a8ff 1011 else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 1012 {
bogdanm 0:9b334a45a8ff 1013 SMBUS_Master_ISR(hsmbus);
bogdanm 0:9b334a45a8ff 1014 }
bogdanm 0:9b334a45a8ff 1015 }
bogdanm 0:9b334a45a8ff 1016
bogdanm 0:9b334a45a8ff 1017 /* SMBUS in mode Receiver ----------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1018 if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
bogdanm 0:9b334a45a8ff 1019 {
bogdanm 0:9b334a45a8ff 1020 /* Slave mode selected */
bogdanm 0:9b334a45a8ff 1021 if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
bogdanm 0:9b334a45a8ff 1022 {
bogdanm 0:9b334a45a8ff 1023 SMBUS_Slave_ISR(hsmbus);
bogdanm 0:9b334a45a8ff 1024 }
bogdanm 0:9b334a45a8ff 1025 /* Master mode selected */
bogdanm 0:9b334a45a8ff 1026 else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 1027 {
bogdanm 0:9b334a45a8ff 1028 SMBUS_Master_ISR(hsmbus);
bogdanm 0:9b334a45a8ff 1029 }
bogdanm 0:9b334a45a8ff 1030 }
bogdanm 0:9b334a45a8ff 1031
bogdanm 0:9b334a45a8ff 1032 /* SMBUS in mode Listener Only --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1033 /* Slave mode selected */
bogdanm 0:9b334a45a8ff 1034 if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
bogdanm 0:9b334a45a8ff 1035 && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
bogdanm 0:9b334a45a8ff 1036 {
bogdanm 0:9b334a45a8ff 1037 if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 1038 {
bogdanm 0:9b334a45a8ff 1039 SMBUS_Slave_ISR(hsmbus);
bogdanm 0:9b334a45a8ff 1040 }
bogdanm 0:9b334a45a8ff 1041 }
bogdanm 0:9b334a45a8ff 1042 }
bogdanm 0:9b334a45a8ff 1043
bogdanm 0:9b334a45a8ff 1044 /**
bogdanm 0:9b334a45a8ff 1045 * @brief This function handles SMBUS error interrupt request.
bogdanm 0:9b334a45a8ff 1046 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1047 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1048 * @retval None
bogdanm 0:9b334a45a8ff 1049 */
bogdanm 0:9b334a45a8ff 1050 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1051 {
bogdanm 0:9b334a45a8ff 1052 /* SMBUS Bus error interrupt occurred ------------------------------------*/
bogdanm 0:9b334a45a8ff 1053 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1054 {
bogdanm 0:9b334a45a8ff 1055 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
bogdanm 0:9b334a45a8ff 1056
bogdanm 0:9b334a45a8ff 1057 /* Clear BERR flag */
bogdanm 0:9b334a45a8ff 1058 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
bogdanm 0:9b334a45a8ff 1059 }
bogdanm 0:9b334a45a8ff 1060
bogdanm 0:9b334a45a8ff 1061 /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
bogdanm 0:9b334a45a8ff 1062 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1063 {
bogdanm 0:9b334a45a8ff 1064 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
bogdanm 0:9b334a45a8ff 1065
bogdanm 0:9b334a45a8ff 1066 /* Clear OVR flag */
bogdanm 0:9b334a45a8ff 1067 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
bogdanm 0:9b334a45a8ff 1068 }
bogdanm 0:9b334a45a8ff 1069
bogdanm 0:9b334a45a8ff 1070 /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
bogdanm 0:9b334a45a8ff 1071 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1072 {
bogdanm 0:9b334a45a8ff 1073 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
bogdanm 0:9b334a45a8ff 1074
bogdanm 0:9b334a45a8ff 1075 /* Clear ARLO flag */
bogdanm 0:9b334a45a8ff 1076 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
bogdanm 0:9b334a45a8ff 1077 }
bogdanm 0:9b334a45a8ff 1078
bogdanm 0:9b334a45a8ff 1079 /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
bogdanm 0:9b334a45a8ff 1080 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1081 {
bogdanm 0:9b334a45a8ff 1082 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
bogdanm 0:9b334a45a8ff 1083
bogdanm 0:9b334a45a8ff 1084 /* Clear TIMEOUT flag */
bogdanm 0:9b334a45a8ff 1085 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
bogdanm 0:9b334a45a8ff 1086 }
bogdanm 0:9b334a45a8ff 1087
bogdanm 0:9b334a45a8ff 1088 /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1089 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1090 {
bogdanm 0:9b334a45a8ff 1091 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
bogdanm 0:9b334a45a8ff 1092
bogdanm 0:9b334a45a8ff 1093 /* Clear ALERT flag */
bogdanm 0:9b334a45a8ff 1094 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
bogdanm 0:9b334a45a8ff 1095 }
bogdanm 0:9b334a45a8ff 1096
bogdanm 0:9b334a45a8ff 1097 /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
bogdanm 0:9b334a45a8ff 1098 if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm 0:9b334a45a8ff 1099 {
bogdanm 0:9b334a45a8ff 1100 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
bogdanm 0:9b334a45a8ff 1101
bogdanm 0:9b334a45a8ff 1102 /* Clear PEC error flag */
bogdanm 0:9b334a45a8ff 1103 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
bogdanm 0:9b334a45a8ff 1104 }
bogdanm 0:9b334a45a8ff 1105
bogdanm 0:9b334a45a8ff 1106 /* Call the Error Callback in case of Error detected */
bogdanm 0:9b334a45a8ff 1107 if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
bogdanm 0:9b334a45a8ff 1108 {
bogdanm 0:9b334a45a8ff 1109 /* Do not Reset the the HAL state in case of ALERT error */
bogdanm 0:9b334a45a8ff 1110 if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
bogdanm 0:9b334a45a8ff 1111 {
bogdanm 0:9b334a45a8ff 1112 /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX and HAL_SMBUS_STATE_MASTER_BUSY_XX */
bogdanm 0:9b334a45a8ff 1113 /* keep HAL_SMBUS_STATE_LISTEN if set */
bogdanm 0:9b334a45a8ff 1114 hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_MASTER_BUSY_RX | HAL_SMBUS_STATE_MASTER_BUSY_TX | HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_SLAVE_BUSY_TX);
bogdanm 0:9b334a45a8ff 1115 }
bogdanm 0:9b334a45a8ff 1116
bogdanm 0:9b334a45a8ff 1117 /* Call the Error callback to prevent upper layer */
bogdanm 0:9b334a45a8ff 1118 HAL_SMBUS_ErrorCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1119 }
bogdanm 0:9b334a45a8ff 1120 }
bogdanm 0:9b334a45a8ff 1121
bogdanm 0:9b334a45a8ff 1122 /**
bogdanm 0:9b334a45a8ff 1123 * @brief Master Tx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 1124 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1125 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1126 * @retval None
bogdanm 0:9b334a45a8ff 1127 */
bogdanm 0:9b334a45a8ff 1128 __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1129 {
mbed_official 113:b3775bf36a83 1130 /* Prevent unused argument(s) compilation warning */
mbed_official 113:b3775bf36a83 1131 UNUSED(hsmbus);
mbed_official 113:b3775bf36a83 1132
bogdanm 0:9b334a45a8ff 1133 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1134 the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1135 */
bogdanm 0:9b334a45a8ff 1136 }
bogdanm 0:9b334a45a8ff 1137
bogdanm 0:9b334a45a8ff 1138 /**
bogdanm 0:9b334a45a8ff 1139 * @brief Master Rx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 1140 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1141 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1142 * @retval None
bogdanm 0:9b334a45a8ff 1143 */
bogdanm 0:9b334a45a8ff 1144 __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1145 {
mbed_official 113:b3775bf36a83 1146 /* Prevent unused argument(s) compilation warning */
mbed_official 113:b3775bf36a83 1147 UNUSED(hsmbus);
mbed_official 113:b3775bf36a83 1148
bogdanm 0:9b334a45a8ff 1149 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1150 the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1151 */
bogdanm 0:9b334a45a8ff 1152 }
bogdanm 0:9b334a45a8ff 1153
bogdanm 0:9b334a45a8ff 1154 /** @brief Slave Tx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 1155 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1156 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1157 * @retval None
bogdanm 0:9b334a45a8ff 1158 */
bogdanm 0:9b334a45a8ff 1159 __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1160 {
mbed_official 113:b3775bf36a83 1161 /* Prevent unused argument(s) compilation warning */
mbed_official 113:b3775bf36a83 1162 UNUSED(hsmbus);
mbed_official 113:b3775bf36a83 1163
bogdanm 0:9b334a45a8ff 1164 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1165 the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1166 */
bogdanm 0:9b334a45a8ff 1167 }
bogdanm 0:9b334a45a8ff 1168
bogdanm 0:9b334a45a8ff 1169 /**
bogdanm 0:9b334a45a8ff 1170 * @brief Slave Rx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 1171 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1172 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1173 * @retval None
bogdanm 0:9b334a45a8ff 1174 */
bogdanm 0:9b334a45a8ff 1175 __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1176 {
mbed_official 113:b3775bf36a83 1177 /* Prevent unused argument(s) compilation warning */
mbed_official 113:b3775bf36a83 1178 UNUSED(hsmbus);
mbed_official 113:b3775bf36a83 1179
bogdanm 0:9b334a45a8ff 1180 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1181 the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1182 */
bogdanm 0:9b334a45a8ff 1183 }
bogdanm 0:9b334a45a8ff 1184
bogdanm 0:9b334a45a8ff 1185 /**
bogdanm 0:9b334a45a8ff 1186 * @brief Slave Address Match callbacks.
bogdanm 0:9b334a45a8ff 1187 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1188 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1189 * @param TransferDirection: Master request Transfer Direction (Write/Read)
bogdanm 0:9b334a45a8ff 1190 * @param AddrMatchCode: Address Match Code
bogdanm 0:9b334a45a8ff 1191 * @retval None
bogdanm 0:9b334a45a8ff 1192 */
bogdanm 0:9b334a45a8ff 1193 __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
bogdanm 0:9b334a45a8ff 1194 {
mbed_official 113:b3775bf36a83 1195 /* Prevent unused argument(s) compilation warning */
mbed_official 113:b3775bf36a83 1196 UNUSED(hsmbus);
mbed_official 113:b3775bf36a83 1197 UNUSED(TransferDirection);
mbed_official 113:b3775bf36a83 1198 UNUSED(AddrMatchCode);
mbed_official 113:b3775bf36a83 1199
bogdanm 0:9b334a45a8ff 1200 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1201 the HAL_SMBUS_AddrCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1202 */
bogdanm 0:9b334a45a8ff 1203 }
bogdanm 0:9b334a45a8ff 1204
bogdanm 0:9b334a45a8ff 1205 /**
bogdanm 0:9b334a45a8ff 1206 * @brief Slave Listen Complete callbacks.
bogdanm 0:9b334a45a8ff 1207 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1208 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1209 * @retval None
bogdanm 0:9b334a45a8ff 1210 */
bogdanm 0:9b334a45a8ff 1211 __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1212 {
mbed_official 113:b3775bf36a83 1213 /* Prevent unused argument(s) compilation warning */
mbed_official 113:b3775bf36a83 1214 UNUSED(hsmbus);
mbed_official 113:b3775bf36a83 1215
mbed_official 113:b3775bf36a83 1216 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1217 the HAL_SMBUS_ListenCpltCallback could be implemented in the user file
mbed_official 113:b3775bf36a83 1218 */
bogdanm 0:9b334a45a8ff 1219 }
bogdanm 0:9b334a45a8ff 1220
bogdanm 0:9b334a45a8ff 1221 /**
bogdanm 0:9b334a45a8ff 1222 * @brief SMBUS error callbacks.
bogdanm 0:9b334a45a8ff 1223 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1224 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1225 * @retval None
bogdanm 0:9b334a45a8ff 1226 */
bogdanm 0:9b334a45a8ff 1227 __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1228 {
mbed_official 113:b3775bf36a83 1229 /* Prevent unused argument(s) compilation warning */
mbed_official 113:b3775bf36a83 1230 UNUSED(hsmbus);
mbed_official 113:b3775bf36a83 1231
bogdanm 0:9b334a45a8ff 1232 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1233 the HAL_SMBUS_ErrorCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1234 */
bogdanm 0:9b334a45a8ff 1235 }
bogdanm 0:9b334a45a8ff 1236
bogdanm 0:9b334a45a8ff 1237 /**
bogdanm 0:9b334a45a8ff 1238 * @}
bogdanm 0:9b334a45a8ff 1239 */
bogdanm 0:9b334a45a8ff 1240
mbed_official 113:b3775bf36a83 1241 /** @addtogroup SMBUS_Exported_Functions_Group3
bogdanm 0:9b334a45a8ff 1242 * @brief Peripheral State and Errors functions
bogdanm 0:9b334a45a8ff 1243 *
bogdanm 0:9b334a45a8ff 1244 @verbatim
bogdanm 0:9b334a45a8ff 1245 ===============================================================================
bogdanm 0:9b334a45a8ff 1246 ##### Peripheral State and Errors functions #####
bogdanm 0:9b334a45a8ff 1247 ===============================================================================
bogdanm 0:9b334a45a8ff 1248 [..]
bogdanm 0:9b334a45a8ff 1249 This subsection permit to get in run-time the status of the peripheral
bogdanm 0:9b334a45a8ff 1250 and the data flow.
bogdanm 0:9b334a45a8ff 1251
bogdanm 0:9b334a45a8ff 1252 @endverbatim
bogdanm 0:9b334a45a8ff 1253 * @{
bogdanm 0:9b334a45a8ff 1254 */
bogdanm 0:9b334a45a8ff 1255
bogdanm 0:9b334a45a8ff 1256 /**
bogdanm 0:9b334a45a8ff 1257 * @brief Returns the SMBUS state.
bogdanm 0:9b334a45a8ff 1258 * @param hsmbus : SMBUS handle
bogdanm 0:9b334a45a8ff 1259 * @retval HAL state
bogdanm 0:9b334a45a8ff 1260 */
bogdanm 0:9b334a45a8ff 1261 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1262 {
bogdanm 0:9b334a45a8ff 1263 return hsmbus->State;
bogdanm 0:9b334a45a8ff 1264 }
bogdanm 0:9b334a45a8ff 1265
bogdanm 0:9b334a45a8ff 1266 /**
bogdanm 0:9b334a45a8ff 1267 * @brief Return the SMBUS error code
bogdanm 0:9b334a45a8ff 1268 * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1269 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1270 * @retval SMBUS Error Code
bogdanm 0:9b334a45a8ff 1271 */
bogdanm 0:9b334a45a8ff 1272 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1273 {
bogdanm 0:9b334a45a8ff 1274 return hsmbus->ErrorCode;
bogdanm 0:9b334a45a8ff 1275 }
bogdanm 0:9b334a45a8ff 1276
bogdanm 0:9b334a45a8ff 1277 /**
bogdanm 0:9b334a45a8ff 1278 * @}
bogdanm 0:9b334a45a8ff 1279 */
bogdanm 0:9b334a45a8ff 1280
bogdanm 0:9b334a45a8ff 1281 /**
mbed_official 113:b3775bf36a83 1282 * @}
mbed_official 113:b3775bf36a83 1283 */
mbed_official 113:b3775bf36a83 1284
mbed_official 113:b3775bf36a83 1285 /** @addtogroup SMBUS_Private
mbed_official 113:b3775bf36a83 1286 * @{
mbed_official 113:b3775bf36a83 1287 */
mbed_official 113:b3775bf36a83 1288
mbed_official 113:b3775bf36a83 1289 /**
bogdanm 0:9b334a45a8ff 1290 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode
bogdanm 0:9b334a45a8ff 1291 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1292 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1293 * @retval HAL status
bogdanm 0:9b334a45a8ff 1294 */
bogdanm 0:9b334a45a8ff 1295 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1296 {
bogdanm 0:9b334a45a8ff 1297 uint16_t DevAddress;
bogdanm 0:9b334a45a8ff 1298
bogdanm 0:9b334a45a8ff 1299 /* Process Locked */
bogdanm 0:9b334a45a8ff 1300 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1301
bogdanm 0:9b334a45a8ff 1302 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
bogdanm 0:9b334a45a8ff 1303 {
bogdanm 0:9b334a45a8ff 1304 /* Clear NACK Flag */
bogdanm 0:9b334a45a8ff 1305 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm 0:9b334a45a8ff 1306
bogdanm 0:9b334a45a8ff 1307 /* Set corresponding Error Code */
bogdanm 0:9b334a45a8ff 1308 /* No need to generate STOP, it is automatically done */
bogdanm 0:9b334a45a8ff 1309 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
bogdanm 0:9b334a45a8ff 1310
bogdanm 0:9b334a45a8ff 1311 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1312 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1313
bogdanm 0:9b334a45a8ff 1314 /* Call the Error callback to prevent upper layer */
bogdanm 0:9b334a45a8ff 1315 HAL_SMBUS_ErrorCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1316 }
bogdanm 0:9b334a45a8ff 1317 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
bogdanm 0:9b334a45a8ff 1318 {
bogdanm 0:9b334a45a8ff 1319
bogdanm 0:9b334a45a8ff 1320 /* Call the corresponding callback to inform upper layer of End of Transfer */
bogdanm 0:9b334a45a8ff 1321 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 1322 {
bogdanm 0:9b334a45a8ff 1323 /* Disable Interrupt */
bogdanm 0:9b334a45a8ff 1324 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1325
bogdanm 0:9b334a45a8ff 1326 /* Clear STOP Flag */
bogdanm 0:9b334a45a8ff 1327 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 1328
bogdanm 0:9b334a45a8ff 1329 /* Clear Configuration Register 2 */
bogdanm 0:9b334a45a8ff 1330 __SMBUS_RESET_CR2(hsmbus);
bogdanm 0:9b334a45a8ff 1331
bogdanm 0:9b334a45a8ff 1332
bogdanm 0:9b334a45a8ff 1333 /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
bogdanm 0:9b334a45a8ff 1334 /* Disable the selected SMBUS peripheral */
bogdanm 0:9b334a45a8ff 1335 __HAL_SMBUS_DISABLE(hsmbus);
bogdanm 0:9b334a45a8ff 1336
bogdanm 0:9b334a45a8ff 1337 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1338 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1339
bogdanm 0:9b334a45a8ff 1340 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1341 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1342
bogdanm 0:9b334a45a8ff 1343 /* REenable the selected SMBUS peripheral */
bogdanm 0:9b334a45a8ff 1344 __HAL_SMBUS_ENABLE(hsmbus);
bogdanm 0:9b334a45a8ff 1345
bogdanm 0:9b334a45a8ff 1346 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1347 }
bogdanm 0:9b334a45a8ff 1348 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 1349 {
bogdanm 0:9b334a45a8ff 1350 /* Disable Interrupt */
bogdanm 0:9b334a45a8ff 1351 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 1352
bogdanm 0:9b334a45a8ff 1353 /* Clear STOP Flag */
bogdanm 0:9b334a45a8ff 1354 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 1355
bogdanm 0:9b334a45a8ff 1356 /* Clear Configuration Register 2 */
bogdanm 0:9b334a45a8ff 1357 __SMBUS_RESET_CR2(hsmbus);
bogdanm 0:9b334a45a8ff 1358
bogdanm 0:9b334a45a8ff 1359 hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1360 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1361
bogdanm 0:9b334a45a8ff 1362 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1363 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1364
bogdanm 0:9b334a45a8ff 1365 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1366 }
bogdanm 0:9b334a45a8ff 1367 }
bogdanm 0:9b334a45a8ff 1368 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
bogdanm 0:9b334a45a8ff 1369 {
bogdanm 0:9b334a45a8ff 1370 /* Read data from RXDR */
bogdanm 0:9b334a45a8ff 1371 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
bogdanm 0:9b334a45a8ff 1372 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 1373 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 1374 }
bogdanm 0:9b334a45a8ff 1375 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
bogdanm 0:9b334a45a8ff 1376 {
bogdanm 0:9b334a45a8ff 1377 /* Write data to TXDR */
bogdanm 0:9b334a45a8ff 1378 hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
bogdanm 0:9b334a45a8ff 1379 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 1380 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 1381 }
bogdanm 0:9b334a45a8ff 1382 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
bogdanm 0:9b334a45a8ff 1383 {
bogdanm 0:9b334a45a8ff 1384 if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
bogdanm 0:9b334a45a8ff 1385 {
bogdanm 0:9b334a45a8ff 1386 DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
bogdanm 0:9b334a45a8ff 1387
bogdanm 0:9b334a45a8ff 1388 if(hsmbus->XferCount > MAX_NBYTE_SIZE)
bogdanm 0:9b334a45a8ff 1389 {
bogdanm 0:9b334a45a8ff 1390 SMBUS_TransferConfig(hsmbus,DevAddress,MAX_NBYTE_SIZE, SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 1391 hsmbus->XferSize = MAX_NBYTE_SIZE;
bogdanm 0:9b334a45a8ff 1392 }
bogdanm 0:9b334a45a8ff 1393 else
bogdanm 0:9b334a45a8ff 1394 {
bogdanm 0:9b334a45a8ff 1395 SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_AUTOEND_MODE, SMBUS_GENERATE_START_WRITE);
bogdanm 0:9b334a45a8ff 1396 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
bogdanm 0:9b334a45a8ff 1397 /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
bogdanm 0:9b334a45a8ff 1398 if(__SMBUS_GET_PEC_MODE(hsmbus) != RESET)
bogdanm 0:9b334a45a8ff 1399 {
bogdanm 0:9b334a45a8ff 1400 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 1401 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 1402 }
bogdanm 0:9b334a45a8ff 1403 hsmbus->XferSize = hsmbus->XferCount;
bogdanm 0:9b334a45a8ff 1404 }
bogdanm 0:9b334a45a8ff 1405 }
bogdanm 0:9b334a45a8ff 1406 else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0))
bogdanm 0:9b334a45a8ff 1407 {
bogdanm 0:9b334a45a8ff 1408 /* Call TxCpltCallback if no stop mode is set */
bogdanm 0:9b334a45a8ff 1409 if(__SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
bogdanm 0:9b334a45a8ff 1410 {
bogdanm 0:9b334a45a8ff 1411 /* Call the corresponding callback to inform upper layer of End of Transfer */
bogdanm 0:9b334a45a8ff 1412 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 1413 {
bogdanm 0:9b334a45a8ff 1414 /* Disable Interrupt */
bogdanm 0:9b334a45a8ff 1415 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1416 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1417 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1418
bogdanm 0:9b334a45a8ff 1419 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1420 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1421
bogdanm 0:9b334a45a8ff 1422 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1423 }
bogdanm 0:9b334a45a8ff 1424 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 1425 {
bogdanm 0:9b334a45a8ff 1426 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 1427 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1428 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1429
bogdanm 0:9b334a45a8ff 1430 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1431 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1432
bogdanm 0:9b334a45a8ff 1433 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1434 }
bogdanm 0:9b334a45a8ff 1435 }
bogdanm 0:9b334a45a8ff 1436 }
bogdanm 0:9b334a45a8ff 1437 }
bogdanm 0:9b334a45a8ff 1438 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
bogdanm 0:9b334a45a8ff 1439 {
bogdanm 0:9b334a45a8ff 1440 if(hsmbus->XferCount == 0)
bogdanm 0:9b334a45a8ff 1441 {
bogdanm 0:9b334a45a8ff 1442 /* Specific use case for Quick command */
bogdanm 0:9b334a45a8ff 1443 if(hsmbus->pBuffPtr == NULL)
bogdanm 0:9b334a45a8ff 1444 {
bogdanm 0:9b334a45a8ff 1445 /* Generate a Stop command */
bogdanm 0:9b334a45a8ff 1446 hsmbus->Instance->CR2 |= I2C_CR2_STOP;
bogdanm 0:9b334a45a8ff 1447 }
bogdanm 0:9b334a45a8ff 1448 /* Call TxCpltCallback if no stop mode is set */
bogdanm 0:9b334a45a8ff 1449 else if(__SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
bogdanm 0:9b334a45a8ff 1450 {
bogdanm 0:9b334a45a8ff 1451 /* No Generate Stop, to permit restart mode */
bogdanm 0:9b334a45a8ff 1452 /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
bogdanm 0:9b334a45a8ff 1453
bogdanm 0:9b334a45a8ff 1454 /* Call the corresponding callback to inform upper layer of End of Transfer */
bogdanm 0:9b334a45a8ff 1455 if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm 0:9b334a45a8ff 1456 {
bogdanm 0:9b334a45a8ff 1457 /* Disable Interrupt */
bogdanm 0:9b334a45a8ff 1458 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1459 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1460 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1461
bogdanm 0:9b334a45a8ff 1462 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1463 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1464
bogdanm 0:9b334a45a8ff 1465 HAL_SMBUS_MasterTxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1466 }
bogdanm 0:9b334a45a8ff 1467 else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm 0:9b334a45a8ff 1468 {
bogdanm 0:9b334a45a8ff 1469 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 1470 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1471 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1472
bogdanm 0:9b334a45a8ff 1473 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1474 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1475
bogdanm 0:9b334a45a8ff 1476 HAL_SMBUS_MasterRxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1477 }
bogdanm 0:9b334a45a8ff 1478 }
bogdanm 0:9b334a45a8ff 1479 }
bogdanm 0:9b334a45a8ff 1480 }
bogdanm 0:9b334a45a8ff 1481
bogdanm 0:9b334a45a8ff 1482 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1483 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1484
bogdanm 0:9b334a45a8ff 1485 return HAL_OK;
bogdanm 0:9b334a45a8ff 1486 }
bogdanm 0:9b334a45a8ff 1487
bogdanm 0:9b334a45a8ff 1488 /**
bogdanm 0:9b334a45a8ff 1489 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode
bogdanm 0:9b334a45a8ff 1490 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1491 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1492 * @retval HAL status
bogdanm 0:9b334a45a8ff 1493 */
bogdanm 0:9b334a45a8ff 1494 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
bogdanm 0:9b334a45a8ff 1495 {
bogdanm 0:9b334a45a8ff 1496 uint8_t TransferDirection = 0;
bogdanm 0:9b334a45a8ff 1497 uint16_t SlaveAddrCode = 0;
bogdanm 0:9b334a45a8ff 1498
bogdanm 0:9b334a45a8ff 1499 /* Process Locked */
bogdanm 0:9b334a45a8ff 1500 __HAL_LOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1501
bogdanm 0:9b334a45a8ff 1502 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
bogdanm 0:9b334a45a8ff 1503 {
bogdanm 0:9b334a45a8ff 1504 /* Check that SMBUS transfer finished */
bogdanm 0:9b334a45a8ff 1505 /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
bogdanm 0:9b334a45a8ff 1506 /* Mean XferCount == 0*/
bogdanm 0:9b334a45a8ff 1507 /* So clear Flag NACKF only */
bogdanm 0:9b334a45a8ff 1508 if(hsmbus->XferCount == 0)
bogdanm 0:9b334a45a8ff 1509 {
bogdanm 0:9b334a45a8ff 1510 /* Clear NACK Flag */
bogdanm 0:9b334a45a8ff 1511 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm 0:9b334a45a8ff 1512
bogdanm 0:9b334a45a8ff 1513 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1514 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1515 }
bogdanm 0:9b334a45a8ff 1516 else
bogdanm 0:9b334a45a8ff 1517 {
bogdanm 0:9b334a45a8ff 1518 /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
bogdanm 0:9b334a45a8ff 1519 /* Clear NACK Flag */
bogdanm 0:9b334a45a8ff 1520 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm 0:9b334a45a8ff 1521
bogdanm 0:9b334a45a8ff 1522 /* Set HAL State to "Idle" State, mean to LISTEN state */
bogdanm 0:9b334a45a8ff 1523 /* So reset Slave Busy state */
bogdanm 0:9b334a45a8ff 1524 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1525 hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
bogdanm 0:9b334a45a8ff 1526 hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
bogdanm 0:9b334a45a8ff 1527
bogdanm 0:9b334a45a8ff 1528 /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
bogdanm 0:9b334a45a8ff 1529 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1530
bogdanm 0:9b334a45a8ff 1531 /* Set ErrorCode corresponding to a Non-Acknowledge */
bogdanm 0:9b334a45a8ff 1532 hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
bogdanm 0:9b334a45a8ff 1533
bogdanm 0:9b334a45a8ff 1534 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1535 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1536
bogdanm 0:9b334a45a8ff 1537 /* Call the Error callback to prevent upper layer */
bogdanm 0:9b334a45a8ff 1538 HAL_SMBUS_ErrorCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1539 }
bogdanm 0:9b334a45a8ff 1540 }
bogdanm 0:9b334a45a8ff 1541 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
bogdanm 0:9b334a45a8ff 1542 {
bogdanm 0:9b334a45a8ff 1543 TransferDirection = __SMBUS_GET_DIR(hsmbus);
bogdanm 0:9b334a45a8ff 1544 SlaveAddrCode = __SMBUS_GET_ADDR_MATCH(hsmbus);
bogdanm 0:9b334a45a8ff 1545
bogdanm 0:9b334a45a8ff 1546 /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
bogdanm 0:9b334a45a8ff 1547 /* Other ADDRInterrupt will be treat in next Listen usecase */
bogdanm 0:9b334a45a8ff 1548 __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
bogdanm 0:9b334a45a8ff 1549
bogdanm 0:9b334a45a8ff 1550 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1551 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1552
bogdanm 0:9b334a45a8ff 1553 /* Call Slave Addr callback */
bogdanm 0:9b334a45a8ff 1554 HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
bogdanm 0:9b334a45a8ff 1555 }
bogdanm 0:9b334a45a8ff 1556 else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
bogdanm 0:9b334a45a8ff 1557 {
bogdanm 0:9b334a45a8ff 1558 /* Read data from RXDR */
bogdanm 0:9b334a45a8ff 1559 (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
bogdanm 0:9b334a45a8ff 1560 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 1561 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 1562
bogdanm 0:9b334a45a8ff 1563 if(hsmbus->XferCount == 1)
bogdanm 0:9b334a45a8ff 1564 {
bogdanm 0:9b334a45a8ff 1565 /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
bogdanm 0:9b334a45a8ff 1566 /* or only the last Byte of Transfer */
bogdanm 0:9b334a45a8ff 1567 /* So reset the RELOAD bit mode */
bogdanm 0:9b334a45a8ff 1568 hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
bogdanm 0:9b334a45a8ff 1569 SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 1570 }
bogdanm 0:9b334a45a8ff 1571 else if(hsmbus->XferCount == 0)
bogdanm 0:9b334a45a8ff 1572 {
bogdanm 0:9b334a45a8ff 1573 /* Last Byte is received, disable Interrupt */
bogdanm 0:9b334a45a8ff 1574 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm 0:9b334a45a8ff 1575
bogdanm 0:9b334a45a8ff 1576 /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
bogdanm 0:9b334a45a8ff 1577 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1578 hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
bogdanm 0:9b334a45a8ff 1579
bogdanm 0:9b334a45a8ff 1580 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1581 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1582
bogdanm 0:9b334a45a8ff 1583 /* Call the Rx complete callback to inform upper layer of the end of receive process */
bogdanm 0:9b334a45a8ff 1584 HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1585 }
bogdanm 0:9b334a45a8ff 1586 else
bogdanm 0:9b334a45a8ff 1587 {
bogdanm 0:9b334a45a8ff 1588 /* Set Reload for next Bytes */
bogdanm 0:9b334a45a8ff 1589 SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
bogdanm 0:9b334a45a8ff 1590
bogdanm 0:9b334a45a8ff 1591 /* Ack last Byte Read */
bogdanm 0:9b334a45a8ff 1592 hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm 0:9b334a45a8ff 1593 }
bogdanm 0:9b334a45a8ff 1594 }
bogdanm 0:9b334a45a8ff 1595 else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
bogdanm 0:9b334a45a8ff 1596 {
bogdanm 0:9b334a45a8ff 1597 /* Write data to TXDR only if XferCount not reach "0" */
bogdanm 0:9b334a45a8ff 1598 /* A TXIS flag can be set, during STOP treatment */
bogdanm 0:9b334a45a8ff 1599
bogdanm 0:9b334a45a8ff 1600 /* Check if all Datas have already been sent */
bogdanm 0:9b334a45a8ff 1601 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
bogdanm 0:9b334a45a8ff 1602 if(hsmbus->XferCount > 0)
bogdanm 0:9b334a45a8ff 1603 {
bogdanm 0:9b334a45a8ff 1604 /* Write data to TXDR */
bogdanm 0:9b334a45a8ff 1605 hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
bogdanm 0:9b334a45a8ff 1606 hsmbus->XferCount--;
bogdanm 0:9b334a45a8ff 1607 hsmbus->XferSize--;
bogdanm 0:9b334a45a8ff 1608 }
bogdanm 0:9b334a45a8ff 1609
bogdanm 0:9b334a45a8ff 1610 if(hsmbus->XferSize == 0)
bogdanm 0:9b334a45a8ff 1611 {
bogdanm 0:9b334a45a8ff 1612 /* Last Byte is Transmitted */
bogdanm 0:9b334a45a8ff 1613 /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
bogdanm 0:9b334a45a8ff 1614 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1615 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1616 hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
bogdanm 0:9b334a45a8ff 1617
bogdanm 0:9b334a45a8ff 1618 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1619 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1620
bogdanm 0:9b334a45a8ff 1621 /* Call the Tx complete callback to inform upper layer of the end of transmit process */
bogdanm 0:9b334a45a8ff 1622 HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1623 }
bogdanm 0:9b334a45a8ff 1624 }
bogdanm 0:9b334a45a8ff 1625
bogdanm 0:9b334a45a8ff 1626 /* Check if STOPF is set */
bogdanm 0:9b334a45a8ff 1627 if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
bogdanm 0:9b334a45a8ff 1628 {
bogdanm 0:9b334a45a8ff 1629 if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 1630 {
bogdanm 0:9b334a45a8ff 1631 /* Disable RX and TX Interrupts */
bogdanm 0:9b334a45a8ff 1632 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
bogdanm 0:9b334a45a8ff 1633
bogdanm 0:9b334a45a8ff 1634 /* Disable ADDR Interrupt */
bogdanm 0:9b334a45a8ff 1635 SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
bogdanm 0:9b334a45a8ff 1636
bogdanm 0:9b334a45a8ff 1637 /* Disable Address Acknowledge */
bogdanm 0:9b334a45a8ff 1638 hsmbus->Instance->CR2 |= I2C_CR2_NACK;
bogdanm 0:9b334a45a8ff 1639
bogdanm 0:9b334a45a8ff 1640 /* Clear Configuration Register 2 */
bogdanm 0:9b334a45a8ff 1641 __SMBUS_RESET_CR2(hsmbus);
bogdanm 0:9b334a45a8ff 1642
bogdanm 0:9b334a45a8ff 1643 /* Clear STOP Flag */
bogdanm 0:9b334a45a8ff 1644 __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm 0:9b334a45a8ff 1645
bogdanm 0:9b334a45a8ff 1646 /* Clear ADDR flag */
bogdanm 0:9b334a45a8ff 1647 __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
bogdanm 0:9b334a45a8ff 1648
bogdanm 0:9b334a45a8ff 1649 hsmbus->XferOptions = 0;
bogdanm 0:9b334a45a8ff 1650 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1651 hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1652
bogdanm 0:9b334a45a8ff 1653 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1654 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1655
bogdanm 0:9b334a45a8ff 1656 /* Call the Slave Complete callback, to prevent upper layer of the end of slave usecase */
bogdanm 0:9b334a45a8ff 1657 HAL_SMBUS_ListenCpltCallback(hsmbus);
bogdanm 0:9b334a45a8ff 1658 }
bogdanm 0:9b334a45a8ff 1659 }
bogdanm 0:9b334a45a8ff 1660
bogdanm 0:9b334a45a8ff 1661 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1662 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1663
bogdanm 0:9b334a45a8ff 1664 return HAL_OK;
bogdanm 0:9b334a45a8ff 1665 }
bogdanm 0:9b334a45a8ff 1666
bogdanm 0:9b334a45a8ff 1667 /**
bogdanm 0:9b334a45a8ff 1668 * @brief Manage the enabling of Interrupts
bogdanm 0:9b334a45a8ff 1669 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1670 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1671 * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
bogdanm 0:9b334a45a8ff 1672 * @retval HAL status
bogdanm 0:9b334a45a8ff 1673 */
bogdanm 0:9b334a45a8ff 1674 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
bogdanm 0:9b334a45a8ff 1675 {
bogdanm 0:9b334a45a8ff 1676 uint32_t tmpisr = 0;
bogdanm 0:9b334a45a8ff 1677
bogdanm 0:9b334a45a8ff 1678 if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
bogdanm 0:9b334a45a8ff 1679 {
bogdanm 0:9b334a45a8ff 1680 /* Enable ERR interrupt */
bogdanm 0:9b334a45a8ff 1681 tmpisr |= SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1682 }
bogdanm 0:9b334a45a8ff 1683
bogdanm 0:9b334a45a8ff 1684 if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
bogdanm 0:9b334a45a8ff 1685 {
bogdanm 0:9b334a45a8ff 1686 /* Enable ADDR, STOP interrupt */
bogdanm 0:9b334a45a8ff 1687 tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1688 }
bogdanm 0:9b334a45a8ff 1689
bogdanm 0:9b334a45a8ff 1690 if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
bogdanm 0:9b334a45a8ff 1691 {
bogdanm 0:9b334a45a8ff 1692 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
bogdanm 0:9b334a45a8ff 1693 tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
bogdanm 0:9b334a45a8ff 1694 }
bogdanm 0:9b334a45a8ff 1695
bogdanm 0:9b334a45a8ff 1696 if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
bogdanm 0:9b334a45a8ff 1697 {
bogdanm 0:9b334a45a8ff 1698 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
bogdanm 0:9b334a45a8ff 1699 tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
bogdanm 0:9b334a45a8ff 1700 }
bogdanm 0:9b334a45a8ff 1701
bogdanm 0:9b334a45a8ff 1702 /* Enable interrupts only at the end */
bogdanm 0:9b334a45a8ff 1703 /* to avoid the risk of SMBUS interrupt handle execution before */
bogdanm 0:9b334a45a8ff 1704 /* all interrupts requested done */
bogdanm 0:9b334a45a8ff 1705 __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
bogdanm 0:9b334a45a8ff 1706
bogdanm 0:9b334a45a8ff 1707 return HAL_OK;
bogdanm 0:9b334a45a8ff 1708 }
bogdanm 0:9b334a45a8ff 1709 /**
bogdanm 0:9b334a45a8ff 1710 * @brief Manage the disabling of Interrupts
bogdanm 0:9b334a45a8ff 1711 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1712 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1713 * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
bogdanm 0:9b334a45a8ff 1714 * @retval HAL status
bogdanm 0:9b334a45a8ff 1715 */
bogdanm 0:9b334a45a8ff 1716 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
bogdanm 0:9b334a45a8ff 1717 {
bogdanm 0:9b334a45a8ff 1718 uint32_t tmpisr = 0;
bogdanm 0:9b334a45a8ff 1719
bogdanm 0:9b334a45a8ff 1720 if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
bogdanm 0:9b334a45a8ff 1721 {
bogdanm 0:9b334a45a8ff 1722 /* Disable ERR interrupt */
bogdanm 0:9b334a45a8ff 1723 tmpisr |= SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1724 }
bogdanm 0:9b334a45a8ff 1725
bogdanm 0:9b334a45a8ff 1726 if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
bogdanm 0:9b334a45a8ff 1727 {
bogdanm 0:9b334a45a8ff 1728 /* Disable TC, STOP, NACK, TXI interrupt */
bogdanm 0:9b334a45a8ff 1729 tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
bogdanm 0:9b334a45a8ff 1730
bogdanm 0:9b334a45a8ff 1731 if((__SMBUS_GET_ALERT_ENABLE(hsmbus) == RESET)
bogdanm 0:9b334a45a8ff 1732 && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
bogdanm 0:9b334a45a8ff 1733 {
bogdanm 0:9b334a45a8ff 1734 /* Disable ERR interrupt */
bogdanm 0:9b334a45a8ff 1735 tmpisr |= SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1736 }
bogdanm 0:9b334a45a8ff 1737
bogdanm 0:9b334a45a8ff 1738 if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 1739 {
bogdanm 0:9b334a45a8ff 1740 /* Disable STOPI, NACKI */
bogdanm 0:9b334a45a8ff 1741 tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
bogdanm 0:9b334a45a8ff 1742 }
bogdanm 0:9b334a45a8ff 1743 }
bogdanm 0:9b334a45a8ff 1744
bogdanm 0:9b334a45a8ff 1745 if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
bogdanm 0:9b334a45a8ff 1746 {
bogdanm 0:9b334a45a8ff 1747 /* Disable TC, STOP, NACK, RXI interrupt */
bogdanm 0:9b334a45a8ff 1748 tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
bogdanm 0:9b334a45a8ff 1749
bogdanm 0:9b334a45a8ff 1750 if((__SMBUS_GET_ALERT_ENABLE(hsmbus) == RESET)
bogdanm 0:9b334a45a8ff 1751 && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
bogdanm 0:9b334a45a8ff 1752 {
bogdanm 0:9b334a45a8ff 1753 /* Disable ERR interrupt */
bogdanm 0:9b334a45a8ff 1754 tmpisr |= SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1755 }
bogdanm 0:9b334a45a8ff 1756
bogdanm 0:9b334a45a8ff 1757 if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
bogdanm 0:9b334a45a8ff 1758 {
bogdanm 0:9b334a45a8ff 1759 /* Disable STOPI, NACKI */
bogdanm 0:9b334a45a8ff 1760 tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
bogdanm 0:9b334a45a8ff 1761 }
bogdanm 0:9b334a45a8ff 1762 }
bogdanm 0:9b334a45a8ff 1763
bogdanm 0:9b334a45a8ff 1764 if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
bogdanm 0:9b334a45a8ff 1765 {
bogdanm 0:9b334a45a8ff 1766 /* Enable ADDR, STOP interrupt */
bogdanm 0:9b334a45a8ff 1767 tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
bogdanm 0:9b334a45a8ff 1768
bogdanm 0:9b334a45a8ff 1769 if(__SMBUS_GET_ALERT_ENABLE(hsmbus) == RESET)
bogdanm 0:9b334a45a8ff 1770 {
bogdanm 0:9b334a45a8ff 1771 /* Disable ERR interrupt */
bogdanm 0:9b334a45a8ff 1772 tmpisr |= SMBUS_IT_ERRI;
bogdanm 0:9b334a45a8ff 1773 }
bogdanm 0:9b334a45a8ff 1774 }
bogdanm 0:9b334a45a8ff 1775
bogdanm 0:9b334a45a8ff 1776 /* Disable interrupts only at the end */
bogdanm 0:9b334a45a8ff 1777 /* to avoid a breaking situation like at "t" time */
bogdanm 0:9b334a45a8ff 1778 /* all disable interrupts request are not done */
bogdanm 0:9b334a45a8ff 1779 __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
bogdanm 0:9b334a45a8ff 1780
bogdanm 0:9b334a45a8ff 1781 return HAL_OK;
bogdanm 0:9b334a45a8ff 1782 }
bogdanm 0:9b334a45a8ff 1783 /**
bogdanm 0:9b334a45a8ff 1784 * @brief This function handles SMBUS Communication Timeout.
bogdanm 0:9b334a45a8ff 1785 * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1786 * the configuration information for the specified SMBUS.
bogdanm 0:9b334a45a8ff 1787 * @param Flag: specifies the SMBUS flag to check.
bogdanm 0:9b334a45a8ff 1788 * @param Status: The new Flag status (SET or RESET).
bogdanm 0:9b334a45a8ff 1789 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 1790 * @retval HAL status
bogdanm 0:9b334a45a8ff 1791 */
bogdanm 0:9b334a45a8ff 1792 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 1793 {
bogdanm 0:9b334a45a8ff 1794 uint32_t tickstart = 0x00;
bogdanm 0:9b334a45a8ff 1795 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1796
bogdanm 0:9b334a45a8ff 1797 /* Wait until flag is set */
bogdanm 0:9b334a45a8ff 1798 if(Status == RESET)
bogdanm 0:9b334a45a8ff 1799 {
bogdanm 0:9b334a45a8ff 1800 while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
bogdanm 0:9b334a45a8ff 1801 {
bogdanm 0:9b334a45a8ff 1802 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 1803 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 1804 {
bogdanm 0:9b334a45a8ff 1805 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 1806 {
bogdanm 0:9b334a45a8ff 1807 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1808 hsmbus->State= HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1809
bogdanm 0:9b334a45a8ff 1810 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1811 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1812
bogdanm 0:9b334a45a8ff 1813 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1814 }
bogdanm 0:9b334a45a8ff 1815 }
bogdanm 0:9b334a45a8ff 1816 }
bogdanm 0:9b334a45a8ff 1817 }
bogdanm 0:9b334a45a8ff 1818 else
bogdanm 0:9b334a45a8ff 1819 {
bogdanm 0:9b334a45a8ff 1820 while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
bogdanm 0:9b334a45a8ff 1821 {
bogdanm 0:9b334a45a8ff 1822 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 1823 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 1824 {
bogdanm 0:9b334a45a8ff 1825 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 1826 {
bogdanm 0:9b334a45a8ff 1827 hsmbus->PreviousState = hsmbus->State;
bogdanm 0:9b334a45a8ff 1828 hsmbus->State= HAL_SMBUS_STATE_READY;
bogdanm 0:9b334a45a8ff 1829
bogdanm 0:9b334a45a8ff 1830 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1831 __HAL_UNLOCK(hsmbus);
bogdanm 0:9b334a45a8ff 1832
bogdanm 0:9b334a45a8ff 1833 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1834 }
bogdanm 0:9b334a45a8ff 1835 }
bogdanm 0:9b334a45a8ff 1836 }
bogdanm 0:9b334a45a8ff 1837 }
bogdanm 0:9b334a45a8ff 1838 return HAL_OK;
bogdanm 0:9b334a45a8ff 1839 }
bogdanm 0:9b334a45a8ff 1840
bogdanm 0:9b334a45a8ff 1841 /**
bogdanm 0:9b334a45a8ff 1842 * @brief Handles SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
bogdanm 0:9b334a45a8ff 1843 * @param hsmbus: SMBUS handle.
bogdanm 0:9b334a45a8ff 1844 * @param DevAddress: specifies the slave address to be programmed.
bogdanm 0:9b334a45a8ff 1845 * @param Size: specifies the number of bytes to be programmed.
bogdanm 0:9b334a45a8ff 1846 * This parameter must be a value between 0 and 255.
bogdanm 0:9b334a45a8ff 1847 * @param Mode: new state of the SMBUS START condition generation.
bogdanm 0:9b334a45a8ff 1848 * This parameter can be one or a combination of the following values:
bogdanm 0:9b334a45a8ff 1849 * @arg SMBUS_NO_MODE: No specific mode enabled.
bogdanm 0:9b334a45a8ff 1850 * @arg SMBUS_RELOAD_MODE: Enable Reload mode.
bogdanm 0:9b334a45a8ff 1851 * @arg SMBUS_AUTOEND_MODE: Enable Automatic end mode.
bogdanm 0:9b334a45a8ff 1852 * @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode.
bogdanm 0:9b334a45a8ff 1853 * @param Request: new state of the SMBUS START condition generation.
bogdanm 0:9b334a45a8ff 1854 * This parameter can be one of the following values:
mbed_official 113:b3775bf36a83 1855 * @arg SMBUS_NO_STARTSTOP: Do not Generate stop and start condition.
bogdanm 0:9b334a45a8ff 1856 * @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0).
bogdanm 0:9b334a45a8ff 1857 * @arg SMBUS_GENERATE_START_READ: Generate Restart for read request.
bogdanm 0:9b334a45a8ff 1858 * @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request.
bogdanm 0:9b334a45a8ff 1859 * @retval None
bogdanm 0:9b334a45a8ff 1860 */
bogdanm 0:9b334a45a8ff 1861 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
bogdanm 0:9b334a45a8ff 1862 {
bogdanm 0:9b334a45a8ff 1863 uint32_t tmpreg = 0;
bogdanm 0:9b334a45a8ff 1864
bogdanm 0:9b334a45a8ff 1865 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1866 assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
bogdanm 0:9b334a45a8ff 1867 assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
bogdanm 0:9b334a45a8ff 1868 assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
bogdanm 0:9b334a45a8ff 1869
bogdanm 0:9b334a45a8ff 1870 /* Get the CR2 register value */
bogdanm 0:9b334a45a8ff 1871 tmpreg = hsmbus->Instance->CR2;
bogdanm 0:9b334a45a8ff 1872
bogdanm 0:9b334a45a8ff 1873 /* clear tmpreg specific bits */
bogdanm 0:9b334a45a8ff 1874 tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
bogdanm 0:9b334a45a8ff 1875
bogdanm 0:9b334a45a8ff 1876 /* update tmpreg */
bogdanm 0:9b334a45a8ff 1877 tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
bogdanm 0:9b334a45a8ff 1878 (uint32_t)Mode | (uint32_t)Request);
bogdanm 0:9b334a45a8ff 1879
bogdanm 0:9b334a45a8ff 1880 /* update CR2 register */
bogdanm 0:9b334a45a8ff 1881 hsmbus->Instance->CR2 = tmpreg;
bogdanm 0:9b334a45a8ff 1882 }
bogdanm 0:9b334a45a8ff 1883
bogdanm 0:9b334a45a8ff 1884
bogdanm 0:9b334a45a8ff 1885 /**
bogdanm 0:9b334a45a8ff 1886 * @}
bogdanm 0:9b334a45a8ff 1887 */
bogdanm 0:9b334a45a8ff 1888
bogdanm 0:9b334a45a8ff 1889 /**
bogdanm 0:9b334a45a8ff 1890 * @}
bogdanm 0:9b334a45a8ff 1891 */
bogdanm 0:9b334a45a8ff 1892
mbed_official 113:b3775bf36a83 1893 #endif /* HAL_SMBUS_MODULE_ENABLED */
mbed_official 113:b3775bf36a83 1894
mbed_official 113:b3775bf36a83 1895 /**
mbed_official 113:b3775bf36a83 1896 * @}
mbed_official 113:b3775bf36a83 1897 */
mbed_official 113:b3775bf36a83 1898
bogdanm 0:9b334a45a8ff 1899 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 0:9b334a45a8ff 1900