mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 113:b3775bf36a83

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_smbus.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.2.0
bogdanm	0:9b334a45a8ff	6	* @date 06-February-2015
bogdanm	0:9b334a45a8ff	7	* @brief SMBUS HAL module driver.
bogdanm	0:9b334a45a8ff	8	*
bogdanm	0:9b334a45a8ff	9	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	10	* functionalities of the System Management Bus (SMBus) peripheral,
bogdanm	0:9b334a45a8ff	11	* based on I2C principales of operation :
bogdanm	0:9b334a45a8ff	12	* + Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	13	* + I/O operation functions
bogdanm	0:9b334a45a8ff	14	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	15	* + Peripheral State functions
bogdanm	0:9b334a45a8ff	16	*
bogdanm	0:9b334a45a8ff	17	@verbatim
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	20	==============================================================================
bogdanm	0:9b334a45a8ff	21	[..]
bogdanm	0:9b334a45a8ff	22	The SMBUS HAL driver can be used as follows:
bogdanm	0:9b334a45a8ff	23
bogdanm	0:9b334a45a8ff	24	(#) Declare a SMBUS_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	25	SMBUS_HandleTypeDef hsmbus;
bogdanm	0:9b334a45a8ff	26
bogdanm	0:9b334a45a8ff	27	(#)Initialize the SMBUS low level resources by implement the HAL_SMBUS_MspInit ()API:
bogdanm	0:9b334a45a8ff	28	(##) Enable the SMBUSx interface clock
bogdanm	0:9b334a45a8ff	29	(##) SMBUS pins configuration
bogdanm	0:9b334a45a8ff	30	(+) Enable the clock for the SMBUS GPIOs
bogdanm	0:9b334a45a8ff	31	(+) Configure SMBUS pins as alternate function open-drain
bogdanm	0:9b334a45a8ff	32	(##) NVIC configuration if you need to use interrupt process
bogdanm	0:9b334a45a8ff	33	(+) Configure the SMBUSx interrupt priority
bogdanm	0:9b334a45a8ff	34	(+) Enable the NVIC SMBUS IRQ Channel
bogdanm	0:9b334a45a8ff	35
bogdanm	0:9b334a45a8ff	36	(#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Adressing Mode,
bogdanm	0:9b334a45a8ff	37	Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
bogdanm	0:9b334a45a8ff	38	Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
bogdanm	0:9b334a45a8ff	39
bogdanm	0:9b334a45a8ff	40	(#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
bogdanm	0:9b334a45a8ff	41	(+) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
bogdanm	0:9b334a45a8ff	42	by calling the customed HAL_SMBUS_MspInit(&hsmbus) API.
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	(#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	(#) For SMBUS IO operations, only one mode of operations is available within this driver :
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	* Interrupt mode IO operation *
bogdanm	0:9b334a45a8ff	49	===================================
bogdanm	0:9b334a45a8ff	50	[..]
bogdanm	0:9b334a45a8ff	51	(+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Transmit_IT()
bogdanm	0:9b334a45a8ff	52	(++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	53	add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback
bogdanm	0:9b334a45a8ff	54	(+) Receive in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Receive_IT()
bogdanm	0:9b334a45a8ff	55	(++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	56	add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback
bogdanm	0:9b334a45a8ff	57	(+) Abort a master/host SMBUS process commnunication with Interrupt using HAL_SMBUS_Master_Abort_IT()
bogdanm	0:9b334a45a8ff	58	(++) The associated previous transfer callback is called at the end of abort process
bogdanm	0:9b334a45a8ff	59	(++) mean HAL_SMBUS_MasterTxCpltCallback in case of previous state was master transmit
bogdanm	0:9b334a45a8ff	60	(++) mean HAL_SMBUS_MasterRxCpltCallback in case of previous state was master receive
bogdanm	0:9b334a45a8ff	61	(+) Enable the Address listen mode in slave/device SMBUS mode using HAL_SMBUS_EnableListen_IT()
bogdanm	0:9b334a45a8ff	62	(++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback is executed and user can
bogdanm	0:9b334a45a8ff	63	add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
bogdanm	0:9b334a45a8ff	64	(++) At Listen mode end HAL_SMBUS_ListenCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	65	add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback
bogdanm	0:9b334a45a8ff	66	(+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Transmit_IT()
bogdanm	0:9b334a45a8ff	67	(++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	68	add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback
bogdanm	0:9b334a45a8ff	69	(+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Receive_IT()
bogdanm	0:9b334a45a8ff	70	(++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	71	add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback
bogdanm	0:9b334a45a8ff	72	(+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
bogdanm	0:9b334a45a8ff	73	(++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
bogdanm	0:9b334a45a8ff	74	add his own code by customization of function pointer HAL_SMBUS_ErrorCallback
bogdanm	0:9b334a45a8ff	75	to check the Alert Error Code using function HAL_SMBUS_GetError()
bogdanm	0:9b334a45a8ff	76	(+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
bogdanm	0:9b334a45a8ff	77	(+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	78	add his own code by customization of function pointer HAL_SMBUS_ErrorCallback
bogdanm	0:9b334a45a8ff	79	to check the Error Code using function HAL_SMBUS_GetError()
bogdanm	0:9b334a45a8ff	80
bogdanm	0:9b334a45a8ff	81	* SMBUS HAL driver macros list *
bogdanm	0:9b334a45a8ff	82	==================================
bogdanm	0:9b334a45a8ff	83	[..]
bogdanm	0:9b334a45a8ff	84	Below the list of most used macros in SMBUS HAL driver.
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	(+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
bogdanm	0:9b334a45a8ff	87	(+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
bogdanm	0:9b334a45a8ff	88	(+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not
bogdanm	0:9b334a45a8ff	89	(+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag
bogdanm	0:9b334a45a8ff	90	(+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt
bogdanm	0:9b334a45a8ff	91	(+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	[..]
bogdanm	0:9b334a45a8ff	94	(@) You can refer to the SMBUS HAL driver header file for more useful macros
bogdanm	0:9b334a45a8ff	95
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97	@endverbatim
bogdanm	0:9b334a45a8ff	98	******************************************************************************
bogdanm	0:9b334a45a8ff	99	* @attention
bogdanm	0:9b334a45a8ff	100	*
bogdanm	0:9b334a45a8ff	101	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	102	*
bogdanm	0:9b334a45a8ff	103	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	104	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	105	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	106	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	108	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	109	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	111	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	112	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	113	*
bogdanm	0:9b334a45a8ff	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	124	*
bogdanm	0:9b334a45a8ff	125	******************************************************************************
bogdanm	0:9b334a45a8ff	126	*/
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	129	#include "stm32l0xx_hal.h"
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	132	* @{
bogdanm	0:9b334a45a8ff	133	*/
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	/** @defgroup SMBUS
bogdanm	0:9b334a45a8ff	136	* @brief SMBUS HAL module driver
bogdanm	0:9b334a45a8ff	137	* @{
bogdanm	0:9b334a45a8ff	138	*/
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	#ifdef HAL_SMBUS_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	143	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	144	#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /<! SMBUS TIMING clear register Mask /
bogdanm	0:9b334a45a8ff	145	#define HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
bogdanm	0:9b334a45a8ff	146	#define HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	147	#define HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	148	#define HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	149	#define HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	150	#define HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	151	#define HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	152	#define HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	153	#define MAX_NBYTE_SIZE 255
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	156	#define __SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
bogdanm	0:9b334a45a8ff	157	#define __SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	160	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	161	static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	162
bogdanm	0:9b334a45a8ff	163	static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
bogdanm	0:9b334a45a8ff	164	static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
bogdanm	0:9b334a45a8ff	165	static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
bogdanm	0:9b334a45a8ff	166	static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
bogdanm	0:9b334a45a8ff	167
bogdanm	0:9b334a45a8ff	168	static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
bogdanm	0:9b334a45a8ff	169
bogdanm	0:9b334a45a8ff	170	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	/** @defgroup SMBUS_Private_Functions
bogdanm	0:9b334a45a8ff	173	* @{
bogdanm	0:9b334a45a8ff	174	*/
bogdanm	0:9b334a45a8ff	175
bogdanm	0:9b334a45a8ff	176	/** @defgroup SMBUS_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	177	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	178	*
bogdanm	0:9b334a45a8ff	179	@verbatim
bogdanm	0:9b334a45a8ff	180	===============================================================================
bogdanm	0:9b334a45a8ff	181	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	182	===============================================================================
bogdanm	0:9b334a45a8ff	183	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	184	de-initialiaze the SMBUSx peripheral:
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	(+) User must Implement HAL_SMBUS_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	187	all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
bogdanm	0:9b334a45a8ff	188
bogdanm	0:9b334a45a8ff	189	(+) Call the function HAL_SMBUS_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	190	the selected configuration:
bogdanm	0:9b334a45a8ff	191	(++) Clock Timing
bogdanm	0:9b334a45a8ff	192	(++) Bus Timeout
bogdanm	0:9b334a45a8ff	193	(++) Analog Filer mode
bogdanm	0:9b334a45a8ff	194	(++) Own Address 1
bogdanm	0:9b334a45a8ff	195	(++) Addressing mode (Master, Slave)
bogdanm	0:9b334a45a8ff	196	(++) Dual Addressing mode
bogdanm	0:9b334a45a8ff	197	(++) Own Address 2
bogdanm	0:9b334a45a8ff	198	(++) Own Address 2 Mask
bogdanm	0:9b334a45a8ff	199	(++) General call mode
bogdanm	0:9b334a45a8ff	200	(++) Nostretch mode
bogdanm	0:9b334a45a8ff	201	(++) Packet Error Check mode
bogdanm	0:9b334a45a8ff	202	(++) Peripheral mode
bogdanm	0:9b334a45a8ff	203
bogdanm	0:9b334a45a8ff	204	(+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	205	of the selected SMBUSx periperal.
bogdanm	0:9b334a45a8ff	206
bogdanm	0:9b334a45a8ff	207	@endverbatim
bogdanm	0:9b334a45a8ff	208	* @{
bogdanm	0:9b334a45a8ff	209	*/
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211	/**
bogdanm	0:9b334a45a8ff	212	* @brief Initializes the SMBUS according to the specified parameters
bogdanm	0:9b334a45a8ff	213	* in the SMBUS_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	214	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	215	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	216	* @retval HAL status
bogdanm	0:9b334a45a8ff	217	*/
bogdanm	0:9b334a45a8ff	218	HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	219	{
bogdanm	0:9b334a45a8ff	220	/* Check the SMBUS handle allocation */
bogdanm	0:9b334a45a8ff	221	if(hsmbus == NULL)
bogdanm	0:9b334a45a8ff	222	{
bogdanm	0:9b334a45a8ff	223	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	224	}
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	/* Check the parameters */
bogdanm	0:9b334a45a8ff	227	assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
bogdanm	0:9b334a45a8ff	228	assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
bogdanm	0:9b334a45a8ff	229	assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
bogdanm	0:9b334a45a8ff	230	assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
bogdanm	0:9b334a45a8ff	231	assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
bogdanm	0:9b334a45a8ff	232	assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
bogdanm	0:9b334a45a8ff	233	assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
bogdanm	0:9b334a45a8ff	234	assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
bogdanm	0:9b334a45a8ff	235	assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
bogdanm	0:9b334a45a8ff	236	assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
bogdanm	0:9b334a45a8ff	237	assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	if(hsmbus->State == HAL_SMBUS_STATE_RESET)
bogdanm	0:9b334a45a8ff	240	{
bogdanm	0:9b334a45a8ff	241	/* Init the low level hardware : GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	242	HAL_SMBUS_MspInit(hsmbus);
bogdanm	0:9b334a45a8ff	243	}
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	hsmbus->State = HAL_SMBUS_STATE_BUSY;
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	/* Disable the selected SMBUS peripheral */
bogdanm	0:9b334a45a8ff	248	__HAL_SMBUS_DISABLE(hsmbus);
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	/---------------------------- SMBUSx TIMINGR Configuration ----------------/
bogdanm	0:9b334a45a8ff	251	/* Configure SMBUSx: Frequency range */
bogdanm	0:9b334a45a8ff	252	hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	253
bogdanm	0:9b334a45a8ff	254	/---------------------------- SMBUSx TIMEOUTR Configuration ---------------/
bogdanm	0:9b334a45a8ff	255	/* Configure SMBUSx: Bus Timeout */
bogdanm	0:9b334a45a8ff	256	hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	/---------------------------- SMBUSx OAR1 Configuration -------------------/
bogdanm	0:9b334a45a8ff	259	/* Configure SMBUSx: Own Address1 and ack own address1 mode */
bogdanm	0:9b334a45a8ff	260	hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
bogdanm	0:9b334a45a8ff	261	if(hsmbus->Init.OwnAddress1 != 0)
bogdanm	0:9b334a45a8ff	262	{
bogdanm	0:9b334a45a8ff	263	if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
bogdanm	0:9b334a45a8ff	264	{
bogdanm	0:9b334a45a8ff	265	hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN \| hsmbus->Init.OwnAddress1);
bogdanm	0:9b334a45a8ff	266	}
bogdanm	0:9b334a45a8ff	267	else /* SMBUS_ADDRESSINGMODE_10BIT */
bogdanm	0:9b334a45a8ff	268	{
bogdanm	0:9b334a45a8ff	269	hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN \| I2C_OAR1_OA1MODE \| hsmbus->Init.OwnAddress1);
bogdanm	0:9b334a45a8ff	270	}
bogdanm	0:9b334a45a8ff	271	}
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/---------------------------- SMBUSx CR2 Configuration --------------------/
bogdanm	0:9b334a45a8ff	274	/* Configure SMBUSx: Addressing Master mode */
bogdanm	0:9b334a45a8ff	275	if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
bogdanm	0:9b334a45a8ff	276	{
bogdanm	0:9b334a45a8ff	277	hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
bogdanm	0:9b334a45a8ff	278	}
bogdanm	0:9b334a45a8ff	279	/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
bogdanm	0:9b334a45a8ff	280	/* AUTOEND and NACK bit will be manage during Transfer process */
bogdanm	0:9b334a45a8ff	281	hsmbus->Instance->CR2 \|= (I2C_CR2_AUTOEND \| I2C_CR2_NACK);
bogdanm	0:9b334a45a8ff	282
bogdanm	0:9b334a45a8ff	283	/---------------------------- SMBUSx OAR2 Configuration -----------------------/
bogdanm	0:9b334a45a8ff	284	/* Configure SMBUSx: Dual mode and Own Address2 */
bogdanm	0:9b334a45a8ff	285	hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode \| hsmbus->Init.OwnAddress2 \| (hsmbus->Init.OwnAddress2Masks << 8));
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287	/---------------------------- SMBUSx CR1 Configuration ------------------------/
bogdanm	0:9b334a45a8ff	288	/* Configure SMBUSx: Generalcall and NoStretch mode */
bogdanm	0:9b334a45a8ff	289	hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode \| hsmbus->Init.NoStretchMode \| hsmbus->Init.PacketErrorCheckMode \| hsmbus->Init.PeripheralMode \| hsmbus->Init.AnalogFilter);
bogdanm	0:9b334a45a8ff	290
bogdanm	0:9b334a45a8ff	291	/* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
bogdanm	0:9b334a45a8ff	292	if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
bogdanm	0:9b334a45a8ff	293	&& ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) \|\| (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
bogdanm	0:9b334a45a8ff	294	{
bogdanm	0:9b334a45a8ff	295	hsmbus->Instance->CR1 \|= I2C_CR1_SBC;
bogdanm	0:9b334a45a8ff	296	}
bogdanm	0:9b334a45a8ff	297
bogdanm	0:9b334a45a8ff	298	/* Enable the selected SMBUS peripheral */
bogdanm	0:9b334a45a8ff	299	__HAL_SMBUS_ENABLE(hsmbus);
bogdanm	0:9b334a45a8ff	300
bogdanm	0:9b334a45a8ff	301	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm	0:9b334a45a8ff	302	hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	303	hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	return HAL_OK;
bogdanm	0:9b334a45a8ff	306	}
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308	/**
bogdanm	0:9b334a45a8ff	309	* @brief DeInitializes the SMBUS peripheral.
bogdanm	0:9b334a45a8ff	310	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	311	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	312	* @retval HAL status
bogdanm	0:9b334a45a8ff	313	*/
bogdanm	0:9b334a45a8ff	314	HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	315	{
bogdanm	0:9b334a45a8ff	316	/* Check the SMBUS handle allocation */
bogdanm	0:9b334a45a8ff	317	if(hsmbus == NULL)
bogdanm	0:9b334a45a8ff	318	{
bogdanm	0:9b334a45a8ff	319	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	320	}
bogdanm	0:9b334a45a8ff	321
bogdanm	0:9b334a45a8ff	322	/* Check the parameters */
bogdanm	0:9b334a45a8ff	323	assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	hsmbus->State = HAL_SMBUS_STATE_BUSY;
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	/* Disable the SMBUS Peripheral Clock */
bogdanm	0:9b334a45a8ff	328	__HAL_SMBUS_DISABLE(hsmbus);
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	331	HAL_SMBUS_MspDeInit(hsmbus);
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm	0:9b334a45a8ff	334	hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
bogdanm	0:9b334a45a8ff	335	hsmbus->State = HAL_SMBUS_STATE_RESET;
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	/* Release Lock */
bogdanm	0:9b334a45a8ff	338	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	return HAL_OK;
bogdanm	0:9b334a45a8ff	341	}
bogdanm	0:9b334a45a8ff	342
bogdanm	0:9b334a45a8ff	343	/**
bogdanm	0:9b334a45a8ff	344	* @brief SMBUS MSP Init.
bogdanm	0:9b334a45a8ff	345	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	346	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	347	* @retval None
bogdanm	0:9b334a45a8ff	348	*/
bogdanm	0:9b334a45a8ff	349	__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	350	{
bogdanm	0:9b334a45a8ff	351	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	352	the HAL_SMBUS_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	353	*/
bogdanm	0:9b334a45a8ff	354	}
bogdanm	0:9b334a45a8ff	355
bogdanm	0:9b334a45a8ff	356	/**
bogdanm	0:9b334a45a8ff	357	* @brief SMBUS MSP DeInit
bogdanm	0:9b334a45a8ff	358	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	359	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	360	* @retval None
bogdanm	0:9b334a45a8ff	361	*/
bogdanm	0:9b334a45a8ff	362	__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	363	{
bogdanm	0:9b334a45a8ff	364	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	365	the HAL_SMBUS_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367	}
bogdanm	0:9b334a45a8ff	368
bogdanm	0:9b334a45a8ff	369	/**
bogdanm	0:9b334a45a8ff	370	* @}
bogdanm	0:9b334a45a8ff	371	*/
bogdanm	0:9b334a45a8ff	372
bogdanm	0:9b334a45a8ff	373	/** @defgroup SMBUS_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	374	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	375	*
bogdanm	0:9b334a45a8ff	376	@verbatim
bogdanm	0:9b334a45a8ff	377	===============================================================================
bogdanm	0:9b334a45a8ff	378	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	379	===============================================================================
bogdanm	0:9b334a45a8ff	380	[..]
bogdanm	0:9b334a45a8ff	381	This subsection provides a set of functions allowing to manage the SMBUS data
bogdanm	0:9b334a45a8ff	382	transfers.
bogdanm	0:9b334a45a8ff	383
bogdanm	0:9b334a45a8ff	384	(#) Blocking mode function to check if device is ready for usage is :
bogdanm	0:9b334a45a8ff	385	(++) HAL_SMBUS_IsDeviceReady()
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	(#) There is only one mode of transfer:
bogdanm	0:9b334a45a8ff	388	(++) No-Blocking mode : The communication is performed using Interrupts.
bogdanm	0:9b334a45a8ff	389	These functions return the status of the transfer startup.
bogdanm	0:9b334a45a8ff	390	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	391	dedicated SMBUS IRQ when using Interrupt mode.
bogdanm	0:9b334a45a8ff	392
bogdanm	0:9b334a45a8ff	393	(#) No-Blocking mode functions with Interrupt are :
bogdanm	0:9b334a45a8ff	394	(++) HAL_SMBUS_Master_Transmit_IT()
bogdanm	0:9b334a45a8ff	395	(++) HAL_SMBUS_Master_Receive_IT()
bogdanm	0:9b334a45a8ff	396	(++) HAL_SMBUS_Slave_Transmit_IT()
bogdanm	0:9b334a45a8ff	397	(++) HAL_SMBUS_Slave_Receive_IT()
bogdanm	0:9b334a45a8ff	398	(++) HAL_SMBUS_EnableListen_IT()
bogdanm	0:9b334a45a8ff	399	(++) HAL_SMBUS_EnableAlert_IT()
bogdanm	0:9b334a45a8ff	400	(++) HAL_SMBUS_DisableAlert_IT()
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
bogdanm	0:9b334a45a8ff	403	(++) HAL_SMBUS_MasterTxCpltCallback()
bogdanm	0:9b334a45a8ff	404	(++) HAL_SMBUS_MasterRxCpltCallback()
bogdanm	0:9b334a45a8ff	405	(++) HAL_SMBUS_SlaveTxCpltCallback()
bogdanm	0:9b334a45a8ff	406	(++) HAL_SMBUS_SlaveRxCpltCallback()
bogdanm	0:9b334a45a8ff	407	(++) HAL_SMBUS_AddrCallback()
bogdanm	0:9b334a45a8ff	408	(++) HAL_SMBUS_ListenCpltCallback()
bogdanm	0:9b334a45a8ff	409	(++) HAL_SMBUS_ErrorCallback()
bogdanm	0:9b334a45a8ff	410
bogdanm	0:9b334a45a8ff	411	@endverbatim
bogdanm	0:9b334a45a8ff	412	* @{
bogdanm	0:9b334a45a8ff	413	*/
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/**
bogdanm	0:9b334a45a8ff	416	* @brief Transmit in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	417	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	418	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	419	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	420	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	421	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	422	* @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm	0:9b334a45a8ff	423	* @retval HAL status
bogdanm	0:9b334a45a8ff	424	*/
bogdanm	0:9b334a45a8ff	425	HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef hsmbus, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
bogdanm	0:9b334a45a8ff	426	{
bogdanm	0:9b334a45a8ff	427	/* Check the parameters */
bogdanm	0:9b334a45a8ff	428	assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm	0:9b334a45a8ff	431	{
bogdanm	0:9b334a45a8ff	432	/* Process Locked */
bogdanm	0:9b334a45a8ff	433	__HAL_LOCK(hsmbus);
bogdanm	0:9b334a45a8ff	434
bogdanm	0:9b334a45a8ff	435	hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
bogdanm	0:9b334a45a8ff	436	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm	0:9b334a45a8ff	437	/* Prepare transfer parameters */
bogdanm	0:9b334a45a8ff	438	hsmbus->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	439	hsmbus->XferCount = Size;
bogdanm	0:9b334a45a8ff	440	hsmbus->XferOptions = XferOptions;
bogdanm	0:9b334a45a8ff	441
bogdanm	0:9b334a45a8ff	442	/* In case of Quick command, remove autoend mode */
bogdanm	0:9b334a45a8ff	443	/* Manage the stop generation by software */
bogdanm	0:9b334a45a8ff	444	if(hsmbus->pBuffPtr == NULL)
bogdanm	0:9b334a45a8ff	445	{
bogdanm	0:9b334a45a8ff	446	hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
bogdanm	0:9b334a45a8ff	447	}
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	if(Size > MAX_NBYTE_SIZE)
bogdanm	0:9b334a45a8ff	450	{
bogdanm	0:9b334a45a8ff	451	hsmbus->XferSize = MAX_NBYTE_SIZE;
bogdanm	0:9b334a45a8ff	452	}
bogdanm	0:9b334a45a8ff	453	else
bogdanm	0:9b334a45a8ff	454	{
bogdanm	0:9b334a45a8ff	455	hsmbus->XferSize = Size;
bogdanm	0:9b334a45a8ff	456	}
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	459	/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
bogdanm	0:9b334a45a8ff	460	if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
bogdanm	0:9b334a45a8ff	461	{
bogdanm	0:9b334a45a8ff	462	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE, SMBUS_GENERATE_START_WRITE);
bogdanm	0:9b334a45a8ff	463	}
bogdanm	0:9b334a45a8ff	464	else
bogdanm	0:9b334a45a8ff	465	{
bogdanm	0:9b334a45a8ff	466	/* If transfer direction not change, do not generate Restart Condition */
bogdanm	0:9b334a45a8ff	467	/* Mean Previous state is same as current state */
bogdanm	0:9b334a45a8ff	468	if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm	0:9b334a45a8ff	469	{
bogdanm	0:9b334a45a8ff	470	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	471	}
bogdanm	0:9b334a45a8ff	472	/* Else transfer direction change, so generate Restart with new transfer direction */
bogdanm	0:9b334a45a8ff	473	else
bogdanm	0:9b334a45a8ff	474	{
bogdanm	0:9b334a45a8ff	475	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
bogdanm	0:9b334a45a8ff	476	}
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	/* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
bogdanm	0:9b334a45a8ff	479	/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
bogdanm	0:9b334a45a8ff	480	if(__SMBUS_GET_PEC_MODE(hsmbus) != RESET)
bogdanm	0:9b334a45a8ff	481	{
bogdanm	0:9b334a45a8ff	482	hsmbus->XferSize--;
bogdanm	0:9b334a45a8ff	483	hsmbus->XferCount--;
bogdanm	0:9b334a45a8ff	484	}
bogdanm	0:9b334a45a8ff	485	}
bogdanm	0:9b334a45a8ff	486
bogdanm	0:9b334a45a8ff	487	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	488	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	489
bogdanm	0:9b334a45a8ff	490	/* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	491	to avoid the risk of SMBUS interrupt handle execution before current
bogdanm	0:9b334a45a8ff	492	process unlock */
bogdanm	0:9b334a45a8ff	493	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	return HAL_OK;
bogdanm	0:9b334a45a8ff	496	}
bogdanm	0:9b334a45a8ff	497	else
bogdanm	0:9b334a45a8ff	498	{
bogdanm	0:9b334a45a8ff	499	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	500	}
bogdanm	0:9b334a45a8ff	501	}
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/**
bogdanm	0:9b334a45a8ff	504	* @brief Receive in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	505	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	506	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	507	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	508	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	509	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	510	* @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm	0:9b334a45a8ff	511	* @retval HAL status
bogdanm	0:9b334a45a8ff	512	*/
bogdanm	0:9b334a45a8ff	513	HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef hsmbus, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
bogdanm	0:9b334a45a8ff	514	{
bogdanm	0:9b334a45a8ff	515	/* Check the parameters */
bogdanm	0:9b334a45a8ff	516	assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm	0:9b334a45a8ff	519	{
bogdanm	0:9b334a45a8ff	520	/* Process Locked */
bogdanm	0:9b334a45a8ff	521	__HAL_LOCK(hsmbus);
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
bogdanm	0:9b334a45a8ff	524	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	/* Prepare transfer parameters */
bogdanm	0:9b334a45a8ff	527	hsmbus->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	528	hsmbus->XferCount = Size;
bogdanm	0:9b334a45a8ff	529	hsmbus->XferOptions = XferOptions;
bogdanm	0:9b334a45a8ff	530
bogdanm	0:9b334a45a8ff	531	/* In case of Quick command, remove autoend mode */
bogdanm	0:9b334a45a8ff	532	/* Manage the stop generation by software */
bogdanm	0:9b334a45a8ff	533	if(hsmbus->pBuffPtr == NULL)
bogdanm	0:9b334a45a8ff	534	{
bogdanm	0:9b334a45a8ff	535	hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
bogdanm	0:9b334a45a8ff	536	}
bogdanm	0:9b334a45a8ff	537
bogdanm	0:9b334a45a8ff	538	if(Size > MAX_NBYTE_SIZE)
bogdanm	0:9b334a45a8ff	539	{
bogdanm	0:9b334a45a8ff	540	hsmbus->XferSize = MAX_NBYTE_SIZE;
bogdanm	0:9b334a45a8ff	541	}
bogdanm	0:9b334a45a8ff	542	else
bogdanm	0:9b334a45a8ff	543	{
bogdanm	0:9b334a45a8ff	544	hsmbus->XferSize = Size;
bogdanm	0:9b334a45a8ff	545	}
bogdanm	0:9b334a45a8ff	546
bogdanm	0:9b334a45a8ff	547	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	548	/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
bogdanm	0:9b334a45a8ff	549	if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
bogdanm	0:9b334a45a8ff	550	{
bogdanm	0:9b334a45a8ff	551	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE, SMBUS_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	552	}
bogdanm	0:9b334a45a8ff	553	else
bogdanm	0:9b334a45a8ff	554	{
bogdanm	0:9b334a45a8ff	555	/* If transfer direction not change, do not generate Restart Condition */
bogdanm	0:9b334a45a8ff	556	/* Mean Previous state is same as current state */
bogdanm	0:9b334a45a8ff	557	if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm	0:9b334a45a8ff	558	{
bogdanm	0:9b334a45a8ff	559	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	560	}
bogdanm	0:9b334a45a8ff	561	/* Else transfer direction change, so generate Restart with new transfer direction */
bogdanm	0:9b334a45a8ff	562	else
bogdanm	0:9b334a45a8ff	563	{
bogdanm	0:9b334a45a8ff	564	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	565	}
bogdanm	0:9b334a45a8ff	566	}
bogdanm	0:9b334a45a8ff	567
bogdanm	0:9b334a45a8ff	568	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	569	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	570
bogdanm	0:9b334a45a8ff	571	/* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	572	to avoid the risk of SMBUS interrupt handle execution before current
bogdanm	0:9b334a45a8ff	573	process unlock */
bogdanm	0:9b334a45a8ff	574	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm	0:9b334a45a8ff	575
bogdanm	0:9b334a45a8ff	576	return HAL_OK;
bogdanm	0:9b334a45a8ff	577	}
bogdanm	0:9b334a45a8ff	578	else
bogdanm	0:9b334a45a8ff	579	{
bogdanm	0:9b334a45a8ff	580	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	581	}
bogdanm	0:9b334a45a8ff	582	}
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584	/**
bogdanm	0:9b334a45a8ff	585	* @brief Abort a master/host SMBUS process commnunication with Interrupt
bogdanm	0:9b334a45a8ff	586	* @note : This abort can be called only if state is ready
bogdanm	0:9b334a45a8ff	587	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	588	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	589	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	590	* @retval HAL status
bogdanm	0:9b334a45a8ff	591	*/
bogdanm	0:9b334a45a8ff	592	HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
bogdanm	0:9b334a45a8ff	593	{
bogdanm	0:9b334a45a8ff	594	if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm	0:9b334a45a8ff	595	{
bogdanm	0:9b334a45a8ff	596	/* Process Locked */
bogdanm	0:9b334a45a8ff	597	__HAL_LOCK(hsmbus);
bogdanm	0:9b334a45a8ff	598
bogdanm	0:9b334a45a8ff	599	/* Keep the same state as previous */
bogdanm	0:9b334a45a8ff	600	/* to perform as well the call of the corresponding end of transfer callback */
bogdanm	0:9b334a45a8ff	601	if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm	0:9b334a45a8ff	602	{
bogdanm	0:9b334a45a8ff	603	hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
bogdanm	0:9b334a45a8ff	604	}
bogdanm	0:9b334a45a8ff	605	else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm	0:9b334a45a8ff	606	{
bogdanm	0:9b334a45a8ff	607	hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
bogdanm	0:9b334a45a8ff	608	}
bogdanm	0:9b334a45a8ff	609	else
bogdanm	0:9b334a45a8ff	610	{
bogdanm	0:9b334a45a8ff	611	/* Wrong usage of abort function */
bogdanm	0:9b334a45a8ff	612	/* This function should be used only in case of abort monitored by master device */
bogdanm	0:9b334a45a8ff	613	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	614	}
bogdanm	0:9b334a45a8ff	615	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	/* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
bogdanm	0:9b334a45a8ff	618	/* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
bogdanm	0:9b334a45a8ff	619	SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	620
bogdanm	0:9b334a45a8ff	621	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	622	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	623
bogdanm	0:9b334a45a8ff	624	/* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	625	to avoid the risk of SMBUS interrupt handle execution before current
bogdanm	0:9b334a45a8ff	626	process unlock */
bogdanm	0:9b334a45a8ff	627	if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm	0:9b334a45a8ff	628	{
bogdanm	0:9b334a45a8ff	629	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm	0:9b334a45a8ff	630	}
bogdanm	0:9b334a45a8ff	631	else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm	0:9b334a45a8ff	632	{
bogdanm	0:9b334a45a8ff	633	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm	0:9b334a45a8ff	634	}
bogdanm	0:9b334a45a8ff	635
bogdanm	0:9b334a45a8ff	636	return HAL_OK;
bogdanm	0:9b334a45a8ff	637	}
bogdanm	0:9b334a45a8ff	638	else
bogdanm	0:9b334a45a8ff	639	{
bogdanm	0:9b334a45a8ff	640	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	641	}
bogdanm	0:9b334a45a8ff	642	}
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	/**
bogdanm	0:9b334a45a8ff	645	* @brief Transmit in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	646	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	647	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	648	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	649	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	650	* @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm	0:9b334a45a8ff	651	* @retval HAL status
bogdanm	0:9b334a45a8ff	652	*/
bogdanm	0:9b334a45a8ff	653	HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef hsmbus, uint8_t pData, uint16_t Size, uint32_t XferOptions)
bogdanm	0:9b334a45a8ff	654	{
bogdanm	0:9b334a45a8ff	655	/* Check the parameters */
bogdanm	0:9b334a45a8ff	656	assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm	0:9b334a45a8ff	657
bogdanm	0:9b334a45a8ff	658	if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm	0:9b334a45a8ff	659	{
bogdanm	0:9b334a45a8ff	660	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	661	{
bogdanm	0:9b334a45a8ff	662	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	663	}
bogdanm	0:9b334a45a8ff	664
bogdanm	0:9b334a45a8ff	665	/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
bogdanm	0:9b334a45a8ff	666	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR \| SMBUS_IT_TX);
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668	/* Process Locked */
bogdanm	0:9b334a45a8ff	669	__HAL_LOCK(hsmbus);
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	hsmbus->State \|= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
bogdanm	0:9b334a45a8ff	672	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm	0:9b334a45a8ff	673
bogdanm	0:9b334a45a8ff	674	/* Enable Address Acknowledge */
bogdanm	0:9b334a45a8ff	675	hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	676
bogdanm	0:9b334a45a8ff	677	/* Prepare transfer parameters */
bogdanm	0:9b334a45a8ff	678	hsmbus->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	679	hsmbus->XferSize = Size;
bogdanm	0:9b334a45a8ff	680	hsmbus->XferCount = Size;
bogdanm	0:9b334a45a8ff	681	hsmbus->XferOptions = XferOptions;
bogdanm	0:9b334a45a8ff	682
bogdanm	0:9b334a45a8ff	683	/* Set NBYTE to transmit */
bogdanm	0:9b334a45a8ff	684	SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	685
bogdanm	0:9b334a45a8ff	686	/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
bogdanm	0:9b334a45a8ff	687	/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
bogdanm	0:9b334a45a8ff	688	if(__SMBUS_GET_PEC_MODE(hsmbus) != RESET)
bogdanm	0:9b334a45a8ff	689	{
bogdanm	0:9b334a45a8ff	690	hsmbus->XferSize--;
bogdanm	0:9b334a45a8ff	691	hsmbus->XferCount--;
bogdanm	0:9b334a45a8ff	692	}
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	/* Clear ADDR flag after prepare the transfer parameters */
bogdanm	0:9b334a45a8ff	695	/* This action will generate an acknowledge to the HOST */
bogdanm	0:9b334a45a8ff	696	__HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
bogdanm	0:9b334a45a8ff	697
bogdanm	0:9b334a45a8ff	698	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	699	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	700
bogdanm	0:9b334a45a8ff	701	/* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	702	to avoid the risk of SMBUS interrupt handle execution before current
bogdanm	0:9b334a45a8ff	703	process unlock */
bogdanm	0:9b334a45a8ff	704	/* REnable ADDR interrupt */
bogdanm	0:9b334a45a8ff	705	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX \| SMBUS_IT_ADDR);
bogdanm	0:9b334a45a8ff	706
bogdanm	0:9b334a45a8ff	707	return HAL_OK;
bogdanm	0:9b334a45a8ff	708	}
bogdanm	0:9b334a45a8ff	709	else
bogdanm	0:9b334a45a8ff	710	{
bogdanm	0:9b334a45a8ff	711	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	712	}
bogdanm	0:9b334a45a8ff	713	}
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	/**
bogdanm	0:9b334a45a8ff	716	* @brief Receive in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	717	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	718	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	719	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	720	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	721	* @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
bogdanm	0:9b334a45a8ff	722	* @retval HAL status
bogdanm	0:9b334a45a8ff	723	*/
bogdanm	0:9b334a45a8ff	724	HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef hsmbus, uint8_t pData, uint16_t Size, uint32_t XferOptions)
bogdanm	0:9b334a45a8ff	725	{
bogdanm	0:9b334a45a8ff	726	/* Check the parameters */
bogdanm	0:9b334a45a8ff	727	assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
bogdanm	0:9b334a45a8ff	728
bogdanm	0:9b334a45a8ff	729	if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm	0:9b334a45a8ff	730	{
bogdanm	0:9b334a45a8ff	731	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	732	{
bogdanm	0:9b334a45a8ff	733	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	734	}
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736	/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
bogdanm	0:9b334a45a8ff	737	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR \| SMBUS_IT_RX);
bogdanm	0:9b334a45a8ff	738
bogdanm	0:9b334a45a8ff	739	/* Process Locked */
bogdanm	0:9b334a45a8ff	740	__HAL_LOCK(hsmbus);
bogdanm	0:9b334a45a8ff	741
bogdanm	0:9b334a45a8ff	742	hsmbus->State \|= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
bogdanm	0:9b334a45a8ff	743	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm	0:9b334a45a8ff	744
bogdanm	0:9b334a45a8ff	745	/* Enable Address Acknowledge */
bogdanm	0:9b334a45a8ff	746	hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	747
bogdanm	0:9b334a45a8ff	748	/* Prepare transfer parameters */
bogdanm	0:9b334a45a8ff	749	hsmbus->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	750	hsmbus->XferSize = Size;
bogdanm	0:9b334a45a8ff	751	hsmbus->XferCount = Size;
bogdanm	0:9b334a45a8ff	752	hsmbus->XferOptions = XferOptions;
bogdanm	0:9b334a45a8ff	753
bogdanm	0:9b334a45a8ff	754	/* Set NBYTE to receive */
bogdanm	0:9b334a45a8ff	755	/* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
bogdanm	0:9b334a45a8ff	756	/* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
bogdanm	0:9b334a45a8ff	757	/* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
bogdanm	0:9b334a45a8ff	758	/* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
bogdanm	0:9b334a45a8ff	759	if((hsmbus->XferSize == 1) \|\| ((hsmbus->XferSize == 2) && (__SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
bogdanm	0:9b334a45a8ff	760	{
bogdanm	0:9b334a45a8ff	761	SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	762	}
bogdanm	0:9b334a45a8ff	763	else
bogdanm	0:9b334a45a8ff	764	{
bogdanm	0:9b334a45a8ff	765	SMBUS_TransferConfig(hsmbus,0,/hsmbus->XferSize/1, hsmbus->XferOptions \| SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	766	}
bogdanm	0:9b334a45a8ff	767
bogdanm	0:9b334a45a8ff	768	/* Clear ADDR flag after prepare the transfer parameters */
bogdanm	0:9b334a45a8ff	769	/* This action will generate an acknowledge to the HOST */
bogdanm	0:9b334a45a8ff	770	__HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
bogdanm	0:9b334a45a8ff	771
bogdanm	0:9b334a45a8ff	772	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	773	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	774
bogdanm	0:9b334a45a8ff	775	/* Note : The SMBUS interrupts must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	776	to avoid the risk of SMBUS interrupt handle execution before current
bogdanm	0:9b334a45a8ff	777	process unlock */
bogdanm	0:9b334a45a8ff	778	/* REnable ADDR interrupt */
bogdanm	0:9b334a45a8ff	779	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX \| SMBUS_IT_ADDR);
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	return HAL_OK;
bogdanm	0:9b334a45a8ff	782	}
bogdanm	0:9b334a45a8ff	783	else
bogdanm	0:9b334a45a8ff	784	{
bogdanm	0:9b334a45a8ff	785	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	786	}
bogdanm	0:9b334a45a8ff	787	}
bogdanm	0:9b334a45a8ff	788	/**
bogdanm	0:9b334a45a8ff	789	* @brief This function enable the Address listen mode in Slave mode
bogdanm	0:9b334a45a8ff	790	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	791	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	792	* @retval HAL status
bogdanm	0:9b334a45a8ff	793	*/
bogdanm	0:9b334a45a8ff	794	HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	795	{
bogdanm	0:9b334a45a8ff	796	hsmbus->State = HAL_SMBUS_STATE_LISTEN;
bogdanm	0:9b334a45a8ff	797
bogdanm	0:9b334a45a8ff	798	/* Enable the Address Match interrupt */
bogdanm	0:9b334a45a8ff	799	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
bogdanm	0:9b334a45a8ff	800
bogdanm	0:9b334a45a8ff	801	return HAL_OK;
bogdanm	0:9b334a45a8ff	802	}
bogdanm	0:9b334a45a8ff	803
bogdanm	0:9b334a45a8ff	804	/**
bogdanm	0:9b334a45a8ff	805	* @brief This function disable the Address listen mode
bogdanm	0:9b334a45a8ff	806	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	807	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	808	* @retval HAL status
bogdanm	0:9b334a45a8ff	809	*/
bogdanm	0:9b334a45a8ff	810	HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	811	{
bogdanm	0:9b334a45a8ff	812	/* Disable Address listen mode only if a transfer is not ongoing */
bogdanm	0:9b334a45a8ff	813	if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm	0:9b334a45a8ff	814	{
bogdanm	0:9b334a45a8ff	815	hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	/* Disable the Address Match interrupt */
bogdanm	0:9b334a45a8ff	818	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820	return HAL_OK;
bogdanm	0:9b334a45a8ff	821	}
bogdanm	0:9b334a45a8ff	822	else
bogdanm	0:9b334a45a8ff	823	{
bogdanm	0:9b334a45a8ff	824	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	825	}
bogdanm	0:9b334a45a8ff	826	}
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	/**
bogdanm	0:9b334a45a8ff	829	* @brief Enable SMBUS alert.
bogdanm	0:9b334a45a8ff	830	* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	831	* the configuration information for the specified SMBUSx peripheral.
bogdanm	0:9b334a45a8ff	832	* @retval HAL status
bogdanm	0:9b334a45a8ff	833	*/
bogdanm	0:9b334a45a8ff	834	HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	835	{
bogdanm	0:9b334a45a8ff	836	/* Enable SMBus alert */
bogdanm	0:9b334a45a8ff	837	hsmbus->Instance->CR1 \|= I2C_CR1_ALERTEN;
bogdanm	0:9b334a45a8ff	838
bogdanm	0:9b334a45a8ff	839	/* Clear ALERT flag */
bogdanm	0:9b334a45a8ff	840	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
bogdanm	0:9b334a45a8ff	841
bogdanm	0:9b334a45a8ff	842	/* Enable Alert Interrupt */
bogdanm	0:9b334a45a8ff	843	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	return HAL_OK;
bogdanm	0:9b334a45a8ff	846	}
bogdanm	0:9b334a45a8ff	847	/**
bogdanm	0:9b334a45a8ff	848	* @brief Disable SMBUS alert.
bogdanm	0:9b334a45a8ff	849	* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	850	* the configuration information for the specified SMBUSx peripheral.
bogdanm	0:9b334a45a8ff	851	* @retval HAL status
bogdanm	0:9b334a45a8ff	852	*/
bogdanm	0:9b334a45a8ff	853	HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	854	{
bogdanm	0:9b334a45a8ff	855	/* Enable SMBus alert */
bogdanm	0:9b334a45a8ff	856	hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858	/* Disable Alert Interrupt */
bogdanm	0:9b334a45a8ff	859	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
bogdanm	0:9b334a45a8ff	860
bogdanm	0:9b334a45a8ff	861	return HAL_OK;
bogdanm	0:9b334a45a8ff	862	}
bogdanm	0:9b334a45a8ff	863	/**
bogdanm	0:9b334a45a8ff	864	* @brief Checks if target device is ready for communication.
bogdanm	0:9b334a45a8ff	865	* @note This function is used with Memory devices
bogdanm	0:9b334a45a8ff	866	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	867	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	868	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	869	* @param Trials: Number of trials
bogdanm	0:9b334a45a8ff	870	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	871	* @retval HAL status
bogdanm	0:9b334a45a8ff	872	*/
bogdanm	0:9b334a45a8ff	873	HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	874	{
bogdanm	0:9b334a45a8ff	875	uint32_t tickstart = 0x00;
bogdanm	0:9b334a45a8ff	876	__IO uint32_t SMBUS_Trials = 0x00;
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878	if(hsmbus->State == HAL_SMBUS_STATE_READY)
bogdanm	0:9b334a45a8ff	879	{
bogdanm	0:9b334a45a8ff	880	if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
bogdanm	0:9b334a45a8ff	881	{
bogdanm	0:9b334a45a8ff	882	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	883	}
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	/* Process Locked */
bogdanm	0:9b334a45a8ff	886	__HAL_LOCK(hsmbus);
bogdanm	0:9b334a45a8ff	887
bogdanm	0:9b334a45a8ff	888	hsmbus->State = HAL_SMBUS_STATE_BUSY;
bogdanm	0:9b334a45a8ff	889	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
bogdanm	0:9b334a45a8ff	890
bogdanm	0:9b334a45a8ff	891	do
bogdanm	0:9b334a45a8ff	892	{
bogdanm	0:9b334a45a8ff	893	/* Generate Start */
bogdanm	0:9b334a45a8ff	894	hsmbus->Instance->CR2 = __SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
bogdanm	0:9b334a45a8ff	895
bogdanm	0:9b334a45a8ff	896	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	897	/* Wait until STOPF flag is set or a NACK flag is set*/
bogdanm	0:9b334a45a8ff	898	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	899	while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
bogdanm	0:9b334a45a8ff	900	{
bogdanm	0:9b334a45a8ff	901	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	902	{
bogdanm	0:9b334a45a8ff	903	hsmbus->State = HAL_SMBUS_STATE_TIMEOUT;
bogdanm	0:9b334a45a8ff	904	}
bogdanm	0:9b334a45a8ff	905	}
bogdanm	0:9b334a45a8ff	906
bogdanm	0:9b334a45a8ff	907	/* Check if the NACKF flag has not been set */
bogdanm	0:9b334a45a8ff	908	if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
bogdanm	0:9b334a45a8ff	909	{
bogdanm	0:9b334a45a8ff	910	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	911	if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	912	{
bogdanm	0:9b334a45a8ff	913	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	914	}
bogdanm	0:9b334a45a8ff	915
bogdanm	0:9b334a45a8ff	916	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	917	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	918
bogdanm	0:9b334a45a8ff	919	/* Device is ready */
bogdanm	0:9b334a45a8ff	920	hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	921
bogdanm	0:9b334a45a8ff	922	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	923	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	924
bogdanm	0:9b334a45a8ff	925	return HAL_OK;
bogdanm	0:9b334a45a8ff	926	}
bogdanm	0:9b334a45a8ff	927	else
bogdanm	0:9b334a45a8ff	928	{
bogdanm	0:9b334a45a8ff	929	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	930	if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	931	{
bogdanm	0:9b334a45a8ff	932	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	933	}
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	/* Clear NACK Flag */
bogdanm	0:9b334a45a8ff	936	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938	/* Clear STOP Flag, auto generated with autoend*/
bogdanm	0:9b334a45a8ff	939	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	940	}
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	/* Check if the maximum allowed numbe of trials has bee reached */
bogdanm	0:9b334a45a8ff	943	if (SMBUS_Trials++ == Trials)
bogdanm	0:9b334a45a8ff	944	{
bogdanm	0:9b334a45a8ff	945	/* Generate Stop */
bogdanm	0:9b334a45a8ff	946	hsmbus->Instance->CR2 \|= I2C_CR2_STOP;
bogdanm	0:9b334a45a8ff	947
bogdanm	0:9b334a45a8ff	948	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	949	if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	950	{
bogdanm	0:9b334a45a8ff	951	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	952	}
bogdanm	0:9b334a45a8ff	953
bogdanm	0:9b334a45a8ff	954	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	955	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	956	}
bogdanm	0:9b334a45a8ff	957	}while(SMBUS_Trials++ < Trials);
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	960
bogdanm	0:9b334a45a8ff	961	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	962	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	963
bogdanm	0:9b334a45a8ff	964	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	965	}
bogdanm	0:9b334a45a8ff	966	else
bogdanm	0:9b334a45a8ff	967	{
bogdanm	0:9b334a45a8ff	968	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	969	}
bogdanm	0:9b334a45a8ff	970	}
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/**
bogdanm	0:9b334a45a8ff	973	* @brief This function handles SMBUS event interrupt request.
bogdanm	0:9b334a45a8ff	974	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	975	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	976	* @retval None
bogdanm	0:9b334a45a8ff	977	*/
bogdanm	0:9b334a45a8ff	978	void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	979	{
bogdanm	0:9b334a45a8ff	980	uint32_t tmpisrvalue = 0;
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982	/* Use a local variable to store the current ISR flags */
bogdanm	0:9b334a45a8ff	983	/* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
bogdanm	0:9b334a45a8ff	984	tmpisrvalue = __SMBUS_GET_ISR_REG(hsmbus);
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/* SMBUS in mode Transmitter ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	987	if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) \|\| (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) \|\| (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) \|\| (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) \|\| (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI\| SMBUS_IT_STOPI\| SMBUS_IT_NACKI \| SMBUS_IT_TXI)) != RESET))
bogdanm	0:9b334a45a8ff	988	{
bogdanm	0:9b334a45a8ff	989	/* Slave mode selected */
bogdanm	0:9b334a45a8ff	990	if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
bogdanm	0:9b334a45a8ff	991	{
bogdanm	0:9b334a45a8ff	992	SMBUS_Slave_ISR(hsmbus);
bogdanm	0:9b334a45a8ff	993	}
bogdanm	0:9b334a45a8ff	994	/* Master mode selected */
bogdanm	0:9b334a45a8ff	995	else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm	0:9b334a45a8ff	996	{
bogdanm	0:9b334a45a8ff	997	SMBUS_Master_ISR(hsmbus);
bogdanm	0:9b334a45a8ff	998	}
bogdanm	0:9b334a45a8ff	999	}
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001	/* SMBUS in mode Receiver ----------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1002	if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) \|\| (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) \|\| (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) \|\| (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) \|\| (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI\| SMBUS_IT_STOPI\| SMBUS_IT_NACKI \| SMBUS_IT_RXI)) != RESET))
bogdanm	0:9b334a45a8ff	1003	{
bogdanm	0:9b334a45a8ff	1004	/* Slave mode selected */
bogdanm	0:9b334a45a8ff	1005	if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1006	{
bogdanm	0:9b334a45a8ff	1007	SMBUS_Slave_ISR(hsmbus);
bogdanm	0:9b334a45a8ff	1008	}
bogdanm	0:9b334a45a8ff	1009	/* Master mode selected */
bogdanm	0:9b334a45a8ff	1010	else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm	0:9b334a45a8ff	1011	{
bogdanm	0:9b334a45a8ff	1012	SMBUS_Master_ISR(hsmbus);
bogdanm	0:9b334a45a8ff	1013	}
bogdanm	0:9b334a45a8ff	1014	}
bogdanm	0:9b334a45a8ff	1015
bogdanm	0:9b334a45a8ff	1016	/* SMBUS in mode Listener Only --------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1017	/* Slave mode selected */
bogdanm	0:9b334a45a8ff	1018	if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) \|\| (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) \|\| (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
bogdanm	0:9b334a45a8ff	1019	&& ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) \|\| (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) \|\| (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
bogdanm	0:9b334a45a8ff	1020	{
bogdanm	0:9b334a45a8ff	1021	if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
bogdanm	0:9b334a45a8ff	1022	{
bogdanm	0:9b334a45a8ff	1023	SMBUS_Slave_ISR(hsmbus);
bogdanm	0:9b334a45a8ff	1024	}
bogdanm	0:9b334a45a8ff	1025	}
bogdanm	0:9b334a45a8ff	1026	}
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	/**
bogdanm	0:9b334a45a8ff	1029	* @brief This function handles SMBUS error interrupt request.
bogdanm	0:9b334a45a8ff	1030	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1031	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1032	* @retval None
bogdanm	0:9b334a45a8ff	1033	*/
bogdanm	0:9b334a45a8ff	1034	void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	1035	{
bogdanm	0:9b334a45a8ff	1036	/* SMBUS Bus error interrupt occurred ------------------------------------*/
bogdanm	0:9b334a45a8ff	1037	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm	0:9b334a45a8ff	1038	{
bogdanm	0:9b334a45a8ff	1039	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_BERR;
bogdanm	0:9b334a45a8ff	1040
bogdanm	0:9b334a45a8ff	1041	/* Clear BERR flag */
bogdanm	0:9b334a45a8ff	1042	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
bogdanm	0:9b334a45a8ff	1043	}
bogdanm	0:9b334a45a8ff	1044
bogdanm	0:9b334a45a8ff	1045	/* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
bogdanm	0:9b334a45a8ff	1046	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm	0:9b334a45a8ff	1047	{
bogdanm	0:9b334a45a8ff	1048	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_OVR;
bogdanm	0:9b334a45a8ff	1049
bogdanm	0:9b334a45a8ff	1050	/* Clear OVR flag */
bogdanm	0:9b334a45a8ff	1051	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
bogdanm	0:9b334a45a8ff	1052	}
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
bogdanm	0:9b334a45a8ff	1055	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm	0:9b334a45a8ff	1056	{
bogdanm	0:9b334a45a8ff	1057	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_ARLO;
bogdanm	0:9b334a45a8ff	1058
bogdanm	0:9b334a45a8ff	1059	/* Clear ARLO flag */
bogdanm	0:9b334a45a8ff	1060	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
bogdanm	0:9b334a45a8ff	1061	}
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	/* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
bogdanm	0:9b334a45a8ff	1064	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm	0:9b334a45a8ff	1065	{
bogdanm	0:9b334a45a8ff	1066	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_BUSTIMEOUT;
bogdanm	0:9b334a45a8ff	1067
bogdanm	0:9b334a45a8ff	1068	/* Clear TIMEOUT flag */
bogdanm	0:9b334a45a8ff	1069	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
bogdanm	0:9b334a45a8ff	1070	}
bogdanm	0:9b334a45a8ff	1071
bogdanm	0:9b334a45a8ff	1072	/* SMBUS Alert error interrupt occurred -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1073	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm	0:9b334a45a8ff	1074	{
bogdanm	0:9b334a45a8ff	1075	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_ALERT;
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	/* Clear ALERT flag */
bogdanm	0:9b334a45a8ff	1078	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
bogdanm	0:9b334a45a8ff	1079	}
bogdanm	0:9b334a45a8ff	1080
bogdanm	0:9b334a45a8ff	1081	/* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
bogdanm	0:9b334a45a8ff	1082	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
bogdanm	0:9b334a45a8ff	1083	{
bogdanm	0:9b334a45a8ff	1084	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_PECERR;
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086	/* Clear PEC error flag */
bogdanm	0:9b334a45a8ff	1087	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
bogdanm	0:9b334a45a8ff	1088	}
bogdanm	0:9b334a45a8ff	1089
bogdanm	0:9b334a45a8ff	1090	/* Call the Error Callback in case of Error detected */
bogdanm	0:9b334a45a8ff	1091	if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
bogdanm	0:9b334a45a8ff	1092	{
bogdanm	0:9b334a45a8ff	1093	/* Do not Reset the the HAL state in case of ALERT error */
bogdanm	0:9b334a45a8ff	1094	if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
bogdanm	0:9b334a45a8ff	1095	{
bogdanm	0:9b334a45a8ff	1096	/* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX and HAL_SMBUS_STATE_MASTER_BUSY_XX */
bogdanm	0:9b334a45a8ff	1097	/* keep HAL_SMBUS_STATE_LISTEN if set */
bogdanm	0:9b334a45a8ff	1098	hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_MASTER_BUSY_RX \| HAL_SMBUS_STATE_MASTER_BUSY_TX \| HAL_SMBUS_STATE_SLAVE_BUSY_RX \| HAL_SMBUS_STATE_SLAVE_BUSY_TX);
bogdanm	0:9b334a45a8ff	1099	}
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	/* Call the Error callback to prevent upper layer */
bogdanm	0:9b334a45a8ff	1102	HAL_SMBUS_ErrorCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1103	}
bogdanm	0:9b334a45a8ff	1104	}
bogdanm	0:9b334a45a8ff	1105
bogdanm	0:9b334a45a8ff	1106	/**
bogdanm	0:9b334a45a8ff	1107	* @brief Master Tx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1108	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1109	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1110	* @retval None
bogdanm	0:9b334a45a8ff	1111	*/
bogdanm	0:9b334a45a8ff	1112	__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	1113	{
bogdanm	0:9b334a45a8ff	1114	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1115	the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1116	*/
bogdanm	0:9b334a45a8ff	1117	}
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119	/**
bogdanm	0:9b334a45a8ff	1120	* @brief Master Rx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1121	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1122	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1123	* @retval None
bogdanm	0:9b334a45a8ff	1124	*/
bogdanm	0:9b334a45a8ff	1125	__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	1126	{
bogdanm	0:9b334a45a8ff	1127	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1128	the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1129	*/
bogdanm	0:9b334a45a8ff	1130	}
bogdanm	0:9b334a45a8ff	1131
bogdanm	0:9b334a45a8ff	1132	/** @brief Slave Tx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1133	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1134	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1135	* @retval None
bogdanm	0:9b334a45a8ff	1136	*/
bogdanm	0:9b334a45a8ff	1137	__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	1138	{
bogdanm	0:9b334a45a8ff	1139	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1140	the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1141	*/
bogdanm	0:9b334a45a8ff	1142	}
bogdanm	0:9b334a45a8ff	1143
bogdanm	0:9b334a45a8ff	1144	/**
bogdanm	0:9b334a45a8ff	1145	* @brief Slave Rx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1146	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1147	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1148	* @retval None
bogdanm	0:9b334a45a8ff	1149	*/
bogdanm	0:9b334a45a8ff	1150	__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	1151	{
bogdanm	0:9b334a45a8ff	1152	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1153	the HAL_SMBUS_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1154	*/
bogdanm	0:9b334a45a8ff	1155	}
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	/**
bogdanm	0:9b334a45a8ff	1158	* @brief Slave Address Match callbacks.
bogdanm	0:9b334a45a8ff	1159	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1160	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1161	* @param TransferDirection: Master request Transfer Direction (Write/Read)
bogdanm	0:9b334a45a8ff	1162	* @param AddrMatchCode: Address Match Code
bogdanm	0:9b334a45a8ff	1163	* @retval None
bogdanm	0:9b334a45a8ff	1164	*/
bogdanm	0:9b334a45a8ff	1165	__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
bogdanm	0:9b334a45a8ff	1166	{
bogdanm	0:9b334a45a8ff	1167	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1168	the HAL_SMBUS_AddrCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1169	*/
bogdanm	0:9b334a45a8ff	1170	}
bogdanm	0:9b334a45a8ff	1171
bogdanm	0:9b334a45a8ff	1172	/**
bogdanm	0:9b334a45a8ff	1173	* @brief Slave Listen Complete callbacks.
bogdanm	0:9b334a45a8ff	1174	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1175	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1176	* @retval None
bogdanm	0:9b334a45a8ff	1177	*/
bogdanm	0:9b334a45a8ff	1178	__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	1179	{
bogdanm	0:9b334a45a8ff	1180	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1181	the HAL_SMBUS_ListenCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1182	*/
bogdanm	0:9b334a45a8ff	1183	}
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	/**
bogdanm	0:9b334a45a8ff	1186	* @brief SMBUS error callbacks.
bogdanm	0:9b334a45a8ff	1187	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1188	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1189	* @retval None
bogdanm	0:9b334a45a8ff	1190	*/
bogdanm	0:9b334a45a8ff	1191	__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	1192	{
bogdanm	0:9b334a45a8ff	1193	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1194	the HAL_SMBUS_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1195	*/
bogdanm	0:9b334a45a8ff	1196	}
bogdanm	0:9b334a45a8ff	1197
bogdanm	0:9b334a45a8ff	1198	/**
bogdanm	0:9b334a45a8ff	1199	* @}
bogdanm	0:9b334a45a8ff	1200	*/
bogdanm	0:9b334a45a8ff	1201
bogdanm	0:9b334a45a8ff	1202	/** @defgroup SMBUS_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1203	* @brief Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1204	*
bogdanm	0:9b334a45a8ff	1205	@verbatim
bogdanm	0:9b334a45a8ff	1206	===============================================================================
bogdanm	0:9b334a45a8ff	1207	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1208	===============================================================================
bogdanm	0:9b334a45a8ff	1209	[..]
bogdanm	0:9b334a45a8ff	1210	This subsection permit to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	1211	and the data flow.
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	@endverbatim
bogdanm	0:9b334a45a8ff	1214	* @{
bogdanm	0:9b334a45a8ff	1215	*/
bogdanm	0:9b334a45a8ff	1216
bogdanm	0:9b334a45a8ff	1217	/**
bogdanm	0:9b334a45a8ff	1218	* @brief Returns the SMBUS state.
bogdanm	0:9b334a45a8ff	1219	* @param hsmbus : SMBUS handle
bogdanm	0:9b334a45a8ff	1220	* @retval HAL state
bogdanm	0:9b334a45a8ff	1221	*/
bogdanm	0:9b334a45a8ff	1222	uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	1223	{
bogdanm	0:9b334a45a8ff	1224	return hsmbus->State;
bogdanm	0:9b334a45a8ff	1225	}
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	/**
bogdanm	0:9b334a45a8ff	1228	* @brief Return the SMBUS error code
bogdanm	0:9b334a45a8ff	1229	* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1230	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1231	* @retval SMBUS Error Code
bogdanm	0:9b334a45a8ff	1232	*/
bogdanm	0:9b334a45a8ff	1233	uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	1234	{
bogdanm	0:9b334a45a8ff	1235	return hsmbus->ErrorCode;
bogdanm	0:9b334a45a8ff	1236	}
bogdanm	0:9b334a45a8ff	1237
bogdanm	0:9b334a45a8ff	1238	/**
bogdanm	0:9b334a45a8ff	1239	* @}
bogdanm	0:9b334a45a8ff	1240	*/
bogdanm	0:9b334a45a8ff	1241
bogdanm	0:9b334a45a8ff	1242	/**
bogdanm	0:9b334a45a8ff	1243	* @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode
bogdanm	0:9b334a45a8ff	1244	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1245	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1246	* @retval HAL status
bogdanm	0:9b334a45a8ff	1247	*/
bogdanm	0:9b334a45a8ff	1248	static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	1249	{
bogdanm	0:9b334a45a8ff	1250	uint16_t DevAddress;
bogdanm	0:9b334a45a8ff	1251
bogdanm	0:9b334a45a8ff	1252	/* Process Locked */
bogdanm	0:9b334a45a8ff	1253	__HAL_LOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1254
bogdanm	0:9b334a45a8ff	1255	if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
bogdanm	0:9b334a45a8ff	1256	{
bogdanm	0:9b334a45a8ff	1257	/* Clear NACK Flag */
bogdanm	0:9b334a45a8ff	1258	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm	0:9b334a45a8ff	1259
bogdanm	0:9b334a45a8ff	1260	/* Set corresponding Error Code */
bogdanm	0:9b334a45a8ff	1261	/* No need to generate STOP, it is automatically done */
bogdanm	0:9b334a45a8ff	1262	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_ACKF;
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1265	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267	/* Call the Error callback to prevent upper layer */
bogdanm	0:9b334a45a8ff	1268	HAL_SMBUS_ErrorCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1269	}
bogdanm	0:9b334a45a8ff	1270	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
bogdanm	0:9b334a45a8ff	1271	{
bogdanm	0:9b334a45a8ff	1272
bogdanm	0:9b334a45a8ff	1273	/* Call the corresponding callback to inform upper layer of End of Transfer */
bogdanm	0:9b334a45a8ff	1274	if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm	0:9b334a45a8ff	1275	{
bogdanm	0:9b334a45a8ff	1276	/* Disable Interrupt */
bogdanm	0:9b334a45a8ff	1277	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm	0:9b334a45a8ff	1278
bogdanm	0:9b334a45a8ff	1279	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	1280	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	1281
bogdanm	0:9b334a45a8ff	1282	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	1283	__SMBUS_RESET_CR2(hsmbus);
bogdanm	0:9b334a45a8ff	1284
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286	/* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
bogdanm	0:9b334a45a8ff	1287	/* Disable the selected SMBUS peripheral */
bogdanm	0:9b334a45a8ff	1288	__HAL_SMBUS_DISABLE(hsmbus);
bogdanm	0:9b334a45a8ff	1289
bogdanm	0:9b334a45a8ff	1290	hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	1291	hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1294	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	/* REenable the selected SMBUS peripheral */
bogdanm	0:9b334a45a8ff	1297	__HAL_SMBUS_ENABLE(hsmbus);
bogdanm	0:9b334a45a8ff	1298
bogdanm	0:9b334a45a8ff	1299	HAL_SMBUS_MasterTxCpltCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1300	}
bogdanm	0:9b334a45a8ff	1301	else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm	0:9b334a45a8ff	1302	{
bogdanm	0:9b334a45a8ff	1303	/* Disable Interrupt */
bogdanm	0:9b334a45a8ff	1304	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm	0:9b334a45a8ff	1305
bogdanm	0:9b334a45a8ff	1306	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	1307	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	1308
bogdanm	0:9b334a45a8ff	1309	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	1310	__SMBUS_RESET_CR2(hsmbus);
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	1313	hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1316	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	HAL_SMBUS_MasterRxCpltCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1319	}
bogdanm	0:9b334a45a8ff	1320	}
bogdanm	0:9b334a45a8ff	1321	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
bogdanm	0:9b334a45a8ff	1322	{
bogdanm	0:9b334a45a8ff	1323	/* Read data from RXDR */
bogdanm	0:9b334a45a8ff	1324	(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
bogdanm	0:9b334a45a8ff	1325	hsmbus->XferSize--;
bogdanm	0:9b334a45a8ff	1326	hsmbus->XferCount--;
bogdanm	0:9b334a45a8ff	1327	}
bogdanm	0:9b334a45a8ff	1328	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
bogdanm	0:9b334a45a8ff	1329	{
bogdanm	0:9b334a45a8ff	1330	/* Write data to TXDR */
bogdanm	0:9b334a45a8ff	1331	hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
bogdanm	0:9b334a45a8ff	1332	hsmbus->XferSize--;
bogdanm	0:9b334a45a8ff	1333	hsmbus->XferCount--;
bogdanm	0:9b334a45a8ff	1334	}
bogdanm	0:9b334a45a8ff	1335	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
bogdanm	0:9b334a45a8ff	1336	{
bogdanm	0:9b334a45a8ff	1337	if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
bogdanm	0:9b334a45a8ff	1338	{
bogdanm	0:9b334a45a8ff	1339	DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
bogdanm	0:9b334a45a8ff	1340
bogdanm	0:9b334a45a8ff	1341	if(hsmbus->XferCount > MAX_NBYTE_SIZE)
bogdanm	0:9b334a45a8ff	1342	{
bogdanm	0:9b334a45a8ff	1343	SMBUS_TransferConfig(hsmbus,DevAddress,MAX_NBYTE_SIZE, SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	1344	hsmbus->XferSize = MAX_NBYTE_SIZE;
bogdanm	0:9b334a45a8ff	1345	}
bogdanm	0:9b334a45a8ff	1346	else
bogdanm	0:9b334a45a8ff	1347	{
bogdanm	0:9b334a45a8ff	1348	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_AUTOEND_MODE, SMBUS_GENERATE_START_WRITE);
bogdanm	0:9b334a45a8ff	1349	/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
bogdanm	0:9b334a45a8ff	1350	/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
bogdanm	0:9b334a45a8ff	1351	if(__SMBUS_GET_PEC_MODE(hsmbus) != RESET)
bogdanm	0:9b334a45a8ff	1352	{
bogdanm	0:9b334a45a8ff	1353	hsmbus->XferSize--;
bogdanm	0:9b334a45a8ff	1354	hsmbus->XferCount--;
bogdanm	0:9b334a45a8ff	1355	}
bogdanm	0:9b334a45a8ff	1356	hsmbus->XferSize = hsmbus->XferCount;
bogdanm	0:9b334a45a8ff	1357	}
bogdanm	0:9b334a45a8ff	1358	}
bogdanm	0:9b334a45a8ff	1359	else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0))
bogdanm	0:9b334a45a8ff	1360	{
bogdanm	0:9b334a45a8ff	1361	/* Call TxCpltCallback if no stop mode is set */
bogdanm	0:9b334a45a8ff	1362	if(__SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
bogdanm	0:9b334a45a8ff	1363	{
bogdanm	0:9b334a45a8ff	1364	/* Call the corresponding callback to inform upper layer of End of Transfer */
bogdanm	0:9b334a45a8ff	1365	if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm	0:9b334a45a8ff	1366	{
bogdanm	0:9b334a45a8ff	1367	/* Disable Interrupt */
bogdanm	0:9b334a45a8ff	1368	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm	0:9b334a45a8ff	1369	hsmbus->PreviousState = hsmbus->State;
bogdanm	0:9b334a45a8ff	1370	hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1373	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	HAL_SMBUS_MasterTxCpltCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1376	}
bogdanm	0:9b334a45a8ff	1377	else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm	0:9b334a45a8ff	1378	{
bogdanm	0:9b334a45a8ff	1379	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm	0:9b334a45a8ff	1380	hsmbus->PreviousState = hsmbus->State;
bogdanm	0:9b334a45a8ff	1381	hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1384	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	HAL_SMBUS_MasterRxCpltCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1387	}
bogdanm	0:9b334a45a8ff	1388	}
bogdanm	0:9b334a45a8ff	1389	}
bogdanm	0:9b334a45a8ff	1390	}
bogdanm	0:9b334a45a8ff	1391	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
bogdanm	0:9b334a45a8ff	1392	{
bogdanm	0:9b334a45a8ff	1393	if(hsmbus->XferCount == 0)
bogdanm	0:9b334a45a8ff	1394	{
bogdanm	0:9b334a45a8ff	1395	/* Specific use case for Quick command */
bogdanm	0:9b334a45a8ff	1396	if(hsmbus->pBuffPtr == NULL)
bogdanm	0:9b334a45a8ff	1397	{
bogdanm	0:9b334a45a8ff	1398	/* Generate a Stop command */
bogdanm	0:9b334a45a8ff	1399	hsmbus->Instance->CR2 \|= I2C_CR2_STOP;
bogdanm	0:9b334a45a8ff	1400	}
bogdanm	0:9b334a45a8ff	1401	/* Call TxCpltCallback if no stop mode is set */
bogdanm	0:9b334a45a8ff	1402	else if(__SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
bogdanm	0:9b334a45a8ff	1403	{
bogdanm	0:9b334a45a8ff	1404	/* No Generate Stop, to permit restart mode */
bogdanm	0:9b334a45a8ff	1405	/* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
bogdanm	0:9b334a45a8ff	1406
bogdanm	0:9b334a45a8ff	1407	/* Call the corresponding callback to inform upper layer of End of Transfer */
bogdanm	0:9b334a45a8ff	1408	if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
bogdanm	0:9b334a45a8ff	1409	{
bogdanm	0:9b334a45a8ff	1410	/* Disable Interrupt */
bogdanm	0:9b334a45a8ff	1411	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm	0:9b334a45a8ff	1412	hsmbus->PreviousState = hsmbus->State;
bogdanm	0:9b334a45a8ff	1413	hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1416	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1417
bogdanm	0:9b334a45a8ff	1418	HAL_SMBUS_MasterTxCpltCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1419	}
bogdanm	0:9b334a45a8ff	1420	else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
bogdanm	0:9b334a45a8ff	1421	{
bogdanm	0:9b334a45a8ff	1422	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm	0:9b334a45a8ff	1423	hsmbus->PreviousState = hsmbus->State;
bogdanm	0:9b334a45a8ff	1424	hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	1425
bogdanm	0:9b334a45a8ff	1426	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1427	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1428
bogdanm	0:9b334a45a8ff	1429	HAL_SMBUS_MasterRxCpltCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1430	}
bogdanm	0:9b334a45a8ff	1431	}
bogdanm	0:9b334a45a8ff	1432	}
bogdanm	0:9b334a45a8ff	1433	}
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1436	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	return HAL_OK;
bogdanm	0:9b334a45a8ff	1439	}
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441	/**
bogdanm	0:9b334a45a8ff	1442	* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode
bogdanm	0:9b334a45a8ff	1443	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1444	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1445	* @retval HAL status
bogdanm	0:9b334a45a8ff	1446	*/
bogdanm	0:9b334a45a8ff	1447	static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
bogdanm	0:9b334a45a8ff	1448	{
bogdanm	0:9b334a45a8ff	1449	uint8_t TransferDirection = 0;
bogdanm	0:9b334a45a8ff	1450	uint16_t SlaveAddrCode = 0;
bogdanm	0:9b334a45a8ff	1451
bogdanm	0:9b334a45a8ff	1452	/* Process Locked */
bogdanm	0:9b334a45a8ff	1453	__HAL_LOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1454
bogdanm	0:9b334a45a8ff	1455	if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
bogdanm	0:9b334a45a8ff	1456	{
bogdanm	0:9b334a45a8ff	1457	/* Check that SMBUS transfer finished */
bogdanm	0:9b334a45a8ff	1458	/* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
bogdanm	0:9b334a45a8ff	1459	/* Mean XferCount == 0*/
bogdanm	0:9b334a45a8ff	1460	/* So clear Flag NACKF only */
bogdanm	0:9b334a45a8ff	1461	if(hsmbus->XferCount == 0)
bogdanm	0:9b334a45a8ff	1462	{
bogdanm	0:9b334a45a8ff	1463	/* Clear NACK Flag */
bogdanm	0:9b334a45a8ff	1464	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm	0:9b334a45a8ff	1465
bogdanm	0:9b334a45a8ff	1466	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1467	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1468	}
bogdanm	0:9b334a45a8ff	1469	else
bogdanm	0:9b334a45a8ff	1470	{
bogdanm	0:9b334a45a8ff	1471	/* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
bogdanm	0:9b334a45a8ff	1472	/* Clear NACK Flag */
bogdanm	0:9b334a45a8ff	1473	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
bogdanm	0:9b334a45a8ff	1474
bogdanm	0:9b334a45a8ff	1475	/* Set HAL State to "Idle" State, mean to LISTEN state */
bogdanm	0:9b334a45a8ff	1476	/* So reset Slave Busy state */
bogdanm	0:9b334a45a8ff	1477	hsmbus->PreviousState = hsmbus->State;
bogdanm	0:9b334a45a8ff	1478	hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
bogdanm	0:9b334a45a8ff	1479	hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
bogdanm	0:9b334a45a8ff	1480
bogdanm	0:9b334a45a8ff	1481	/* Disable RX/TX Interrupts, keep only ADDR Interrupt */
bogdanm	0:9b334a45a8ff	1482	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX \| SMBUS_IT_TX);
bogdanm	0:9b334a45a8ff	1483
bogdanm	0:9b334a45a8ff	1484	/* Set ErrorCode corresponding to a Non-Acknowledge */
bogdanm	0:9b334a45a8ff	1485	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_ACKF;
bogdanm	0:9b334a45a8ff	1486
bogdanm	0:9b334a45a8ff	1487	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1488	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1489
bogdanm	0:9b334a45a8ff	1490	/* Call the Error callback to prevent upper layer */
bogdanm	0:9b334a45a8ff	1491	HAL_SMBUS_ErrorCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1492	}
bogdanm	0:9b334a45a8ff	1493	}
bogdanm	0:9b334a45a8ff	1494	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
bogdanm	0:9b334a45a8ff	1495	{
bogdanm	0:9b334a45a8ff	1496	TransferDirection = __SMBUS_GET_DIR(hsmbus);
bogdanm	0:9b334a45a8ff	1497	SlaveAddrCode = __SMBUS_GET_ADDR_MATCH(hsmbus);
bogdanm	0:9b334a45a8ff	1498
bogdanm	0:9b334a45a8ff	1499	/* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
bogdanm	0:9b334a45a8ff	1500	/* Other ADDRInterrupt will be treat in next Listen usecase */
bogdanm	0:9b334a45a8ff	1501	__HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
bogdanm	0:9b334a45a8ff	1502
bogdanm	0:9b334a45a8ff	1503	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1504	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	/* Call Slave Addr callback */
bogdanm	0:9b334a45a8ff	1507	HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
bogdanm	0:9b334a45a8ff	1508	}
bogdanm	0:9b334a45a8ff	1509	else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) \|\| (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
bogdanm	0:9b334a45a8ff	1510	{
bogdanm	0:9b334a45a8ff	1511	/* Read data from RXDR */
bogdanm	0:9b334a45a8ff	1512	(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
bogdanm	0:9b334a45a8ff	1513	hsmbus->XferSize--;
bogdanm	0:9b334a45a8ff	1514	hsmbus->XferCount--;
bogdanm	0:9b334a45a8ff	1515
bogdanm	0:9b334a45a8ff	1516	if(hsmbus->XferCount == 1)
bogdanm	0:9b334a45a8ff	1517	{
bogdanm	0:9b334a45a8ff	1518	/* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
bogdanm	0:9b334a45a8ff	1519	/* or only the last Byte of Transfer */
bogdanm	0:9b334a45a8ff	1520	/* So reset the RELOAD bit mode */
bogdanm	0:9b334a45a8ff	1521	hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
bogdanm	0:9b334a45a8ff	1522	SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	1523	}
bogdanm	0:9b334a45a8ff	1524	else if(hsmbus->XferCount == 0)
bogdanm	0:9b334a45a8ff	1525	{
bogdanm	0:9b334a45a8ff	1526	/* Last Byte is received, disable Interrupt */
bogdanm	0:9b334a45a8ff	1527	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
bogdanm	0:9b334a45a8ff	1528
bogdanm	0:9b334a45a8ff	1529	/* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
bogdanm	0:9b334a45a8ff	1530	hsmbus->PreviousState = hsmbus->State;
bogdanm	0:9b334a45a8ff	1531	hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
bogdanm	0:9b334a45a8ff	1532
bogdanm	0:9b334a45a8ff	1533	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1534	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1535
bogdanm	0:9b334a45a8ff	1536	/* Call the Rx complete callback to inform upper layer of the end of receive process */
bogdanm	0:9b334a45a8ff	1537	HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1538	}
bogdanm	0:9b334a45a8ff	1539	else
bogdanm	0:9b334a45a8ff	1540	{
bogdanm	0:9b334a45a8ff	1541	/* Set Reload for next Bytes */
bogdanm	0:9b334a45a8ff	1542	SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	1543
bogdanm	0:9b334a45a8ff	1544	/* Ack last Byte Read */
bogdanm	0:9b334a45a8ff	1545	hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1546	}
bogdanm	0:9b334a45a8ff	1547	}
bogdanm	0:9b334a45a8ff	1548	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
bogdanm	0:9b334a45a8ff	1549	{
bogdanm	0:9b334a45a8ff	1550	/* Write data to TXDR only if XferCount not reach "0" */
bogdanm	0:9b334a45a8ff	1551	/* A TXIS flag can be set, during STOP treatment */
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553	/* Check if all Datas have already been sent */
bogdanm	0:9b334a45a8ff	1554	/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
bogdanm	0:9b334a45a8ff	1555	if(hsmbus->XferCount > 0)
bogdanm	0:9b334a45a8ff	1556	{
bogdanm	0:9b334a45a8ff	1557	/* Write data to TXDR */
bogdanm	0:9b334a45a8ff	1558	hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
bogdanm	0:9b334a45a8ff	1559	hsmbus->XferCount--;
bogdanm	0:9b334a45a8ff	1560	hsmbus->XferSize--;
bogdanm	0:9b334a45a8ff	1561	}
bogdanm	0:9b334a45a8ff	1562
bogdanm	0:9b334a45a8ff	1563	if(hsmbus->XferSize == 0)
bogdanm	0:9b334a45a8ff	1564	{
bogdanm	0:9b334a45a8ff	1565	/* Last Byte is Transmitted */
bogdanm	0:9b334a45a8ff	1566	/* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
bogdanm	0:9b334a45a8ff	1567	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
bogdanm	0:9b334a45a8ff	1568	hsmbus->PreviousState = hsmbus->State;
bogdanm	0:9b334a45a8ff	1569	hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
bogdanm	0:9b334a45a8ff	1570
bogdanm	0:9b334a45a8ff	1571	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1572	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1573
bogdanm	0:9b334a45a8ff	1574	/* Call the Tx complete callback to inform upper layer of the end of transmit process */
bogdanm	0:9b334a45a8ff	1575	HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1576	}
bogdanm	0:9b334a45a8ff	1577	}
bogdanm	0:9b334a45a8ff	1578
bogdanm	0:9b334a45a8ff	1579	/* Check if STOPF is set */
bogdanm	0:9b334a45a8ff	1580	if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
bogdanm	0:9b334a45a8ff	1581	{
bogdanm	0:9b334a45a8ff	1582	if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
bogdanm	0:9b334a45a8ff	1583	{
bogdanm	0:9b334a45a8ff	1584	/* Disable RX and TX Interrupts */
bogdanm	0:9b334a45a8ff	1585	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX \| SMBUS_IT_TX);
bogdanm	0:9b334a45a8ff	1586
bogdanm	0:9b334a45a8ff	1587	/* Disable ADDR Interrupt */
bogdanm	0:9b334a45a8ff	1588	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	1591	hsmbus->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1592
bogdanm	0:9b334a45a8ff	1593	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	1594	__SMBUS_RESET_CR2(hsmbus);
bogdanm	0:9b334a45a8ff	1595
bogdanm	0:9b334a45a8ff	1596	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	1597	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	1598
bogdanm	0:9b334a45a8ff	1599	/* Clear ADDR flag */
bogdanm	0:9b334a45a8ff	1600	__HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
bogdanm	0:9b334a45a8ff	1601
bogdanm	0:9b334a45a8ff	1602	hsmbus->XferOptions = 0;
bogdanm	0:9b334a45a8ff	1603	hsmbus->PreviousState = hsmbus->State;
bogdanm	0:9b334a45a8ff	1604	hsmbus->State = HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1607	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/* Call the Slave Complete callback, to prevent upper layer of the end of slave usecase */
bogdanm	0:9b334a45a8ff	1610	HAL_SMBUS_ListenCpltCallback(hsmbus);
bogdanm	0:9b334a45a8ff	1611	}
bogdanm	0:9b334a45a8ff	1612	}
bogdanm	0:9b334a45a8ff	1613
bogdanm	0:9b334a45a8ff	1614	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1615	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1616
bogdanm	0:9b334a45a8ff	1617	return HAL_OK;
bogdanm	0:9b334a45a8ff	1618	}
bogdanm	0:9b334a45a8ff	1619
bogdanm	0:9b334a45a8ff	1620	/**
bogdanm	0:9b334a45a8ff	1621	* @brief Manage the enabling of Interrupts
bogdanm	0:9b334a45a8ff	1622	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1623	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1624	* @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
bogdanm	0:9b334a45a8ff	1625	* @retval HAL status
bogdanm	0:9b334a45a8ff	1626	*/
bogdanm	0:9b334a45a8ff	1627	static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
bogdanm	0:9b334a45a8ff	1628	{
bogdanm	0:9b334a45a8ff	1629	uint32_t tmpisr = 0;
bogdanm	0:9b334a45a8ff	1630
bogdanm	0:9b334a45a8ff	1631	if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
bogdanm	0:9b334a45a8ff	1632	{
bogdanm	0:9b334a45a8ff	1633	/* Enable ERR interrupt */
bogdanm	0:9b334a45a8ff	1634	tmpisr \|= SMBUS_IT_ERRI;
bogdanm	0:9b334a45a8ff	1635	}
bogdanm	0:9b334a45a8ff	1636
bogdanm	0:9b334a45a8ff	1637	if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
bogdanm	0:9b334a45a8ff	1638	{
bogdanm	0:9b334a45a8ff	1639	/* Enable ADDR, STOP interrupt */
bogdanm	0:9b334a45a8ff	1640	tmpisr \|= SMBUS_IT_ADDRI \| SMBUS_IT_STOPI \| SMBUS_IT_NACKI \| SMBUS_IT_ERRI;
bogdanm	0:9b334a45a8ff	1641	}
bogdanm	0:9b334a45a8ff	1642
bogdanm	0:9b334a45a8ff	1643	if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
bogdanm	0:9b334a45a8ff	1644	{
bogdanm	0:9b334a45a8ff	1645	/* Enable ERR, TC, STOP, NACK, RXI interrupt */
bogdanm	0:9b334a45a8ff	1646	tmpisr \|= SMBUS_IT_ERRI \| SMBUS_IT_TCI \| SMBUS_IT_STOPI \| SMBUS_IT_NACKI \| SMBUS_IT_TXI;
bogdanm	0:9b334a45a8ff	1647	}
bogdanm	0:9b334a45a8ff	1648
bogdanm	0:9b334a45a8ff	1649	if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
bogdanm	0:9b334a45a8ff	1650	{
bogdanm	0:9b334a45a8ff	1651	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
bogdanm	0:9b334a45a8ff	1652	tmpisr \|= SMBUS_IT_ERRI \| SMBUS_IT_TCI \| SMBUS_IT_STOPI \| SMBUS_IT_NACKI \| SMBUS_IT_RXI;
bogdanm	0:9b334a45a8ff	1653	}
bogdanm	0:9b334a45a8ff	1654
bogdanm	0:9b334a45a8ff	1655	/* Enable interrupts only at the end */
bogdanm	0:9b334a45a8ff	1656	/* to avoid the risk of SMBUS interrupt handle execution before */
bogdanm	0:9b334a45a8ff	1657	/* all interrupts requested done */
bogdanm	0:9b334a45a8ff	1658	__HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
bogdanm	0:9b334a45a8ff	1659
bogdanm	0:9b334a45a8ff	1660	return HAL_OK;
bogdanm	0:9b334a45a8ff	1661	}
bogdanm	0:9b334a45a8ff	1662	/**
bogdanm	0:9b334a45a8ff	1663	* @brief Manage the disabling of Interrupts
bogdanm	0:9b334a45a8ff	1664	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1665	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1666	* @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
bogdanm	0:9b334a45a8ff	1667	* @retval HAL status
bogdanm	0:9b334a45a8ff	1668	*/
bogdanm	0:9b334a45a8ff	1669	static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
bogdanm	0:9b334a45a8ff	1670	{
bogdanm	0:9b334a45a8ff	1671	uint32_t tmpisr = 0;
bogdanm	0:9b334a45a8ff	1672
bogdanm	0:9b334a45a8ff	1673	if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
bogdanm	0:9b334a45a8ff	1674	{
bogdanm	0:9b334a45a8ff	1675	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	1676	tmpisr \|= SMBUS_IT_ERRI;
bogdanm	0:9b334a45a8ff	1677	}
bogdanm	0:9b334a45a8ff	1678
bogdanm	0:9b334a45a8ff	1679	if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
bogdanm	0:9b334a45a8ff	1680	{
bogdanm	0:9b334a45a8ff	1681	/* Disable TC, STOP, NACK, TXI interrupt */
bogdanm	0:9b334a45a8ff	1682	tmpisr \|= SMBUS_IT_TCI \| SMBUS_IT_TXI;
bogdanm	0:9b334a45a8ff	1683
bogdanm	0:9b334a45a8ff	1684	if((__SMBUS_GET_ALERT_ENABLE(hsmbus) == RESET)
bogdanm	0:9b334a45a8ff	1685	&& ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
bogdanm	0:9b334a45a8ff	1686	{
bogdanm	0:9b334a45a8ff	1687	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	1688	tmpisr \|= SMBUS_IT_ERRI;
bogdanm	0:9b334a45a8ff	1689	}
bogdanm	0:9b334a45a8ff	1690
bogdanm	0:9b334a45a8ff	1691	if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
bogdanm	0:9b334a45a8ff	1692	{
bogdanm	0:9b334a45a8ff	1693	/* Disable STOPI, NACKI */
bogdanm	0:9b334a45a8ff	1694	tmpisr \|= SMBUS_IT_STOPI \| SMBUS_IT_NACKI;
bogdanm	0:9b334a45a8ff	1695	}
bogdanm	0:9b334a45a8ff	1696	}
bogdanm	0:9b334a45a8ff	1697
bogdanm	0:9b334a45a8ff	1698	if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
bogdanm	0:9b334a45a8ff	1699	{
bogdanm	0:9b334a45a8ff	1700	/* Disable TC, STOP, NACK, RXI interrupt */
bogdanm	0:9b334a45a8ff	1701	tmpisr \|= SMBUS_IT_TCI \| SMBUS_IT_RXI;
bogdanm	0:9b334a45a8ff	1702
bogdanm	0:9b334a45a8ff	1703	if((__SMBUS_GET_ALERT_ENABLE(hsmbus) == RESET)
bogdanm	0:9b334a45a8ff	1704	&& ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
bogdanm	0:9b334a45a8ff	1705	{
bogdanm	0:9b334a45a8ff	1706	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	1707	tmpisr \|= SMBUS_IT_ERRI;
bogdanm	0:9b334a45a8ff	1708	}
bogdanm	0:9b334a45a8ff	1709
bogdanm	0:9b334a45a8ff	1710	if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
bogdanm	0:9b334a45a8ff	1711	{
bogdanm	0:9b334a45a8ff	1712	/* Disable STOPI, NACKI */
bogdanm	0:9b334a45a8ff	1713	tmpisr \|= SMBUS_IT_STOPI \| SMBUS_IT_NACKI;
bogdanm	0:9b334a45a8ff	1714	}
bogdanm	0:9b334a45a8ff	1715	}
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
bogdanm	0:9b334a45a8ff	1718	{
bogdanm	0:9b334a45a8ff	1719	/* Enable ADDR, STOP interrupt */
bogdanm	0:9b334a45a8ff	1720	tmpisr \|= SMBUS_IT_ADDRI \| SMBUS_IT_STOPI \| SMBUS_IT_NACKI;
bogdanm	0:9b334a45a8ff	1721
bogdanm	0:9b334a45a8ff	1722	if(__SMBUS_GET_ALERT_ENABLE(hsmbus) == RESET)
bogdanm	0:9b334a45a8ff	1723	{
bogdanm	0:9b334a45a8ff	1724	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	1725	tmpisr \|= SMBUS_IT_ERRI;
bogdanm	0:9b334a45a8ff	1726	}
bogdanm	0:9b334a45a8ff	1727	}
bogdanm	0:9b334a45a8ff	1728
bogdanm	0:9b334a45a8ff	1729	/* Disable interrupts only at the end */
bogdanm	0:9b334a45a8ff	1730	/* to avoid a breaking situation like at "t" time */
bogdanm	0:9b334a45a8ff	1731	/* all disable interrupts request are not done */
bogdanm	0:9b334a45a8ff	1732	__HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
bogdanm	0:9b334a45a8ff	1733
bogdanm	0:9b334a45a8ff	1734	return HAL_OK;
bogdanm	0:9b334a45a8ff	1735	}
bogdanm	0:9b334a45a8ff	1736	/**
bogdanm	0:9b334a45a8ff	1737	* @brief This function handles SMBUS Communication Timeout.
bogdanm	0:9b334a45a8ff	1738	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1739	* the configuration information for the specified SMBUS.
bogdanm	0:9b334a45a8ff	1740	* @param Flag: specifies the SMBUS flag to check.
bogdanm	0:9b334a45a8ff	1741	* @param Status: The new Flag status (SET or RESET).
bogdanm	0:9b334a45a8ff	1742	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	1743	* @retval HAL status
bogdanm	0:9b334a45a8ff	1744	*/
bogdanm	0:9b334a45a8ff	1745	static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1746	{
bogdanm	0:9b334a45a8ff	1747	uint32_t tickstart = 0x00;
bogdanm	0:9b334a45a8ff	1748	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1749
bogdanm	0:9b334a45a8ff	1750	/* Wait until flag is set */
bogdanm	0:9b334a45a8ff	1751	if(Status == RESET)
bogdanm	0:9b334a45a8ff	1752	{
bogdanm	0:9b334a45a8ff	1753	while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
bogdanm	0:9b334a45a8ff	1754	{
bogdanm	0:9b334a45a8ff	1755	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	1756	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1757	{
bogdanm	0:9b334a45a8ff	1758	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	1759	{
bogdanm	0:9b334a45a8ff	1760	hsmbus->PreviousState = hsmbus->State;
bogdanm	0:9b334a45a8ff	1761	hsmbus->State= HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	1762
bogdanm	0:9b334a45a8ff	1763	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1764	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1765
bogdanm	0:9b334a45a8ff	1766	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1767	}
bogdanm	0:9b334a45a8ff	1768	}
bogdanm	0:9b334a45a8ff	1769	}
bogdanm	0:9b334a45a8ff	1770	}
bogdanm	0:9b334a45a8ff	1771	else
bogdanm	0:9b334a45a8ff	1772	{
bogdanm	0:9b334a45a8ff	1773	while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
bogdanm	0:9b334a45a8ff	1774	{
bogdanm	0:9b334a45a8ff	1775	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	1776	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1777	{
bogdanm	0:9b334a45a8ff	1778	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	1779	{
bogdanm	0:9b334a45a8ff	1780	hsmbus->PreviousState = hsmbus->State;
bogdanm	0:9b334a45a8ff	1781	hsmbus->State= HAL_SMBUS_STATE_READY;
bogdanm	0:9b334a45a8ff	1782
bogdanm	0:9b334a45a8ff	1783	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1784	__HAL_UNLOCK(hsmbus);
bogdanm	0:9b334a45a8ff	1785
bogdanm	0:9b334a45a8ff	1786	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1787	}
bogdanm	0:9b334a45a8ff	1788	}
bogdanm	0:9b334a45a8ff	1789	}
bogdanm	0:9b334a45a8ff	1790	}
bogdanm	0:9b334a45a8ff	1791	return HAL_OK;
bogdanm	0:9b334a45a8ff	1792	}
bogdanm	0:9b334a45a8ff	1793
bogdanm	0:9b334a45a8ff	1794	/**
bogdanm	0:9b334a45a8ff	1795	* @brief Handles SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
bogdanm	0:9b334a45a8ff	1796	* @param hsmbus: SMBUS handle.
bogdanm	0:9b334a45a8ff	1797	* @param DevAddress: specifies the slave address to be programmed.
bogdanm	0:9b334a45a8ff	1798	* @param Size: specifies the number of bytes to be programmed.
bogdanm	0:9b334a45a8ff	1799	* This parameter must be a value between 0 and 255.
bogdanm	0:9b334a45a8ff	1800	* @param Mode: new state of the SMBUS START condition generation.
bogdanm	0:9b334a45a8ff	1801	* This parameter can be one or a combination of the following values:
bogdanm	0:9b334a45a8ff	1802	* @arg SMBUS_NO_MODE: No specific mode enabled.
bogdanm	0:9b334a45a8ff	1803	* @arg SMBUS_RELOAD_MODE: Enable Reload mode.
bogdanm	0:9b334a45a8ff	1804	* @arg SMBUS_AUTOEND_MODE: Enable Automatic end mode.
bogdanm	0:9b334a45a8ff	1805	* @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode.
bogdanm	0:9b334a45a8ff	1806	* @param Request: new state of the SMBUS START condition generation.
bogdanm	0:9b334a45a8ff	1807	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1808	* @arg SMBUS_NO_STARTSTOP: Don't Generate stop and start condition.
bogdanm	0:9b334a45a8ff	1809	* @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0).
bogdanm	0:9b334a45a8ff	1810	* @arg SMBUS_GENERATE_START_READ: Generate Restart for read request.
bogdanm	0:9b334a45a8ff	1811	* @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request.
bogdanm	0:9b334a45a8ff	1812	* @retval None
bogdanm	0:9b334a45a8ff	1813	*/
bogdanm	0:9b334a45a8ff	1814	static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
bogdanm	0:9b334a45a8ff	1815	{
bogdanm	0:9b334a45a8ff	1816	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1817
bogdanm	0:9b334a45a8ff	1818	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1819	assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
bogdanm	0:9b334a45a8ff	1820	assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
bogdanm	0:9b334a45a8ff	1821	assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
bogdanm	0:9b334a45a8ff	1822
bogdanm	0:9b334a45a8ff	1823	/* Get the CR2 register value */
bogdanm	0:9b334a45a8ff	1824	tmpreg = hsmbus->Instance->CR2;
bogdanm	0:9b334a45a8ff	1825
bogdanm	0:9b334a45a8ff	1826	/* clear tmpreg specific bits */
bogdanm	0:9b334a45a8ff	1827	tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD \| I2C_CR2_NBYTES \| I2C_CR2_RELOAD \| I2C_CR2_AUTOEND \| I2C_CR2_RD_WRN \| I2C_CR2_START \| I2C_CR2_STOP \| I2C_CR2_PECBYTE));
bogdanm	0:9b334a45a8ff	1828
bogdanm	0:9b334a45a8ff	1829	/* update tmpreg */
bogdanm	0:9b334a45a8ff	1830	tmpreg \|= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) \| (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) \| \
bogdanm	0:9b334a45a8ff	1831	(uint32_t)Mode \| (uint32_t)Request);
bogdanm	0:9b334a45a8ff	1832
bogdanm	0:9b334a45a8ff	1833	/* update CR2 register */
bogdanm	0:9b334a45a8ff	1834	hsmbus->Instance->CR2 = tmpreg;
bogdanm	0:9b334a45a8ff	1835	}
bogdanm	0:9b334a45a8ff	1836
bogdanm	0:9b334a45a8ff	1837	/**
bogdanm	0:9b334a45a8ff	1838	* @}
bogdanm	0:9b334a45a8ff	1839	*/
bogdanm	0:9b334a45a8ff	1840
bogdanm	0:9b334a45a8ff	1841	#endif /* HAL_SMBUS_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1842	/**
bogdanm	0:9b334a45a8ff	1843	* @}
bogdanm	0:9b334a45a8ff	1844	*/
bogdanm	0:9b334a45a8ff	1845
bogdanm	0:9b334a45a8ff	1846	/**
bogdanm	0:9b334a45a8ff	1847	* @}
bogdanm	0:9b334a45a8ff	1848	*/
bogdanm	0:9b334a45a8ff	1849
bogdanm	0:9b334a45a8ff	1850	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	1851

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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