en 129
fix LPC812 PWM
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mbed official
targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 113:b3775bf36a83
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l0xx_hal_rcc_ex.c |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| mbed_official | 113:b3775bf36a83 | 5 | * @version V1.5.0 |
| mbed_official | 113:b3775bf36a83 | 6 | * @date 8-January-2016 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Extended RCC HAL module driver. |
| bogdanm | 0:9b334a45a8ff | 8 | * |
| bogdanm | 0:9b334a45a8ff | 9 | * This file provides firmware functions to manage the following |
| bogdanm | 0:9b334a45a8ff | 10 | * functionalities RCC extension peripheral: |
| bogdanm | 0:9b334a45a8ff | 11 | * + Extended Peripheral Control functions |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 14 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 15 | ##### RCC specific features ##### |
| bogdanm | 0:9b334a45a8ff | 16 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 17 | For CRS, RCC Extension HAL driver can be used as follows: |
| bogdanm | 0:9b334a45a8ff | 18 | |
| bogdanm | 0:9b334a45a8ff | 19 | (#) In System clock configuration, HSI48 need to be enabled |
| bogdanm | 0:9b334a45a8ff | 20 | |
| bogdanm | 0:9b334a45a8ff | 21 | (#] Enable CRS clock in IP MSP init which will use CRS functions |
| bogdanm | 0:9b334a45a8ff | 22 | |
| bogdanm | 0:9b334a45a8ff | 23 | (#) Call CRS functions like this |
| bogdanm | 0:9b334a45a8ff | 24 | (##) Prepare synchronization configuration necessary for HSI48 calibration |
| bogdanm | 0:9b334a45a8ff | 25 | (+++) Default values can be set for frequency Error Measurement (reload and error limit) |
| bogdanm | 0:9b334a45a8ff | 26 | and also HSI48 oscillator smooth trimming. |
| mbed_official | 113:b3775bf36a83 | 27 | (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate |
| bogdanm | 0:9b334a45a8ff | 28 | directly reload value with target and synchronization frequencies values |
| bogdanm | 0:9b334a45a8ff | 29 | (##) Call function HAL_RCCEx_CRSConfig which |
| bogdanm | 0:9b334a45a8ff | 30 | (+++) Reset CRS registers to their default values. |
| bogdanm | 0:9b334a45a8ff | 31 | (+++) Configure CRS registers with synchronization configuration |
| bogdanm | 0:9b334a45a8ff | 32 | (+++) Enable automatic calibration and frequency error counter feature |
| bogdanm | 0:9b334a45a8ff | 33 | |
| bogdanm | 0:9b334a45a8ff | 34 | (##) A polling function is provided to wait for complete Synchronization |
| bogdanm | 0:9b334a45a8ff | 35 | (+++) Call function 'HAL_RCCEx_CRSWaitSynchronization()' |
| bogdanm | 0:9b334a45a8ff | 36 | (+++) According to CRS status, user can decide to adjust again the calibration or continue |
| bogdanm | 0:9b334a45a8ff | 37 | application if synchronization is OK |
| bogdanm | 0:9b334a45a8ff | 38 | |
| bogdanm | 0:9b334a45a8ff | 39 | (#) User can retrieve information related to synchronization in calling function |
| bogdanm | 0:9b334a45a8ff | 40 | HAL_RCCEx_CRSGetSynchronizationInfo() |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | (#) Regarding synchronization status and synchronization information, user can try a new calibration |
| bogdanm | 0:9b334a45a8ff | 43 | in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. |
| bogdanm | 0:9b334a45a8ff | 44 | Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), |
| bogdanm | 0:9b334a45a8ff | 45 | it means that the actual frequency is lower than the target (and so, that the TRIM value should be |
| bogdanm | 0:9b334a45a8ff | 46 | incremented), while when it is detected during the upcounting phase it means that the actual frequency |
| bogdanm | 0:9b334a45a8ff | 47 | is higher (and that the TRIM value should be decremented). |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | (#) To use IT mode, user needs to handle it in calling different macros available to do it |
| bogdanm | 0:9b334a45a8ff | 50 | (__HAL_RCC_CRS_XXX_IT). Interruptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler) |
| bogdanm | 0:9b334a45a8ff | 51 | (+++) Call function HAL_RCCEx_CRSConfig() |
| bogdanm | 0:9b334a45a8ff | 52 | (+++) Enable RCC_IRQn (thnaks to NVIC functions) |
| bogdanm | 0:9b334a45a8ff | 53 | (+++) Enable CRS IT (__HAL_RCC_CRS_ENABLE_IT) |
| bogdanm | 0:9b334a45a8ff | 54 | [+++) Implement CRS status management in RCC_CRS_IRQHandler |
| bogdanm | 0:9b334a45a8ff | 55 | |
| bogdanm | 0:9b334a45a8ff | 56 | (#) To force a SYNC EVENT, user can use function 'HAL_RCCEx_CRSSoftwareSynchronizationGenerate()'. Function can be |
| bogdanm | 0:9b334a45a8ff | 57 | called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) |
| bogdanm | 0:9b334a45a8ff | 58 | |
| bogdanm | 0:9b334a45a8ff | 59 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 60 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 61 | * @attention |
| bogdanm | 0:9b334a45a8ff | 62 | * |
| mbed_official | 113:b3775bf36a83 | 63 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 64 | * |
| bogdanm | 0:9b334a45a8ff | 65 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 66 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 67 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 68 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 69 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 70 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 71 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 72 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 73 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 74 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 75 | * |
| bogdanm | 0:9b334a45a8ff | 76 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 77 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 78 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 79 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 80 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 81 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 82 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 83 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 84 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 85 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 86 | * |
| bogdanm | 0:9b334a45a8ff | 87 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 88 | */ |
| bogdanm | 0:9b334a45a8ff | 89 | |
| bogdanm | 0:9b334a45a8ff | 90 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 91 | #include "stm32l0xx_hal.h" |
| bogdanm | 0:9b334a45a8ff | 92 | |
| bogdanm | 0:9b334a45a8ff | 93 | /** @addtogroup STM32L0xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 94 | * @{ |
| bogdanm | 0:9b334a45a8ff | 95 | */ |
| bogdanm | 0:9b334a45a8ff | 96 | |
| mbed_official | 113:b3775bf36a83 | 97 | #ifdef HAL_RCC_MODULE_ENABLED |
| mbed_official | 113:b3775bf36a83 | 98 | |
| bogdanm | 0:9b334a45a8ff | 99 | /** @addtogroup RCCEx |
| bogdanm | 0:9b334a45a8ff | 100 | * @brief RCC Extension HAL module driver |
| bogdanm | 0:9b334a45a8ff | 101 | * @{ |
| bogdanm | 0:9b334a45a8ff | 102 | */ |
| bogdanm | 0:9b334a45a8ff | 103 | |
| mbed_official | 113:b3775bf36a83 | 104 | /** @addtogroup RCCEx_Private |
| bogdanm | 0:9b334a45a8ff | 105 | * @{ |
| bogdanm | 0:9b334a45a8ff | 106 | */ |
| bogdanm | 0:9b334a45a8ff | 107 | /* Bit position in register */ |
| bogdanm | 0:9b334a45a8ff | 108 | #define CRS_CFGR_FELIM_BITNUMBER 16 |
| bogdanm | 0:9b334a45a8ff | 109 | #define CRS_CR_TRIM_BITNUMBER 8 |
| bogdanm | 0:9b334a45a8ff | 110 | #define CRS_ISR_FECAP_BITNUMBER 16 |
| bogdanm | 0:9b334a45a8ff | 111 | |
| mbed_official | 113:b3775bf36a83 | 112 | #if defined(USB) |
| mbed_official | 113:b3775bf36a83 | 113 | extern const uint8_t PLLMulTable[]; |
| mbed_official | 113:b3775bf36a83 | 114 | #endif //USB |
| bogdanm | 0:9b334a45a8ff | 115 | /** |
| bogdanm | 0:9b334a45a8ff | 116 | * @} |
| bogdanm | 0:9b334a45a8ff | 117 | */ |
| bogdanm | 0:9b334a45a8ff | 118 | |
| bogdanm | 0:9b334a45a8ff | 119 | /** @addtogroup RCCEx_Exported_Functions |
| bogdanm | 0:9b334a45a8ff | 120 | * @{ |
| bogdanm | 0:9b334a45a8ff | 121 | */ |
| bogdanm | 0:9b334a45a8ff | 122 | |
| bogdanm | 0:9b334a45a8ff | 123 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
| bogdanm | 0:9b334a45a8ff | 124 | * @brief Extended Peripheral Initialization and Control functions |
| bogdanm | 0:9b334a45a8ff | 125 | * |
| bogdanm | 0:9b334a45a8ff | 126 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 127 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 128 | ##### Extended Peripheral Control functions ##### |
| bogdanm | 0:9b334a45a8ff | 129 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 130 | [..] |
| bogdanm | 0:9b334a45a8ff | 131 | This subsection provides a set of functions allowing to control the RCC Clocks |
| bogdanm | 0:9b334a45a8ff | 132 | frequencies. |
| bogdanm | 0:9b334a45a8ff | 133 | |
| bogdanm | 0:9b334a45a8ff | 134 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 135 | * @{ |
| bogdanm | 0:9b334a45a8ff | 136 | */ |
| bogdanm | 0:9b334a45a8ff | 137 | |
| bogdanm | 0:9b334a45a8ff | 138 | /** |
| bogdanm | 0:9b334a45a8ff | 139 | * @brief Resets the RCC clock configuration to the default reset state. |
| bogdanm | 0:9b334a45a8ff | 140 | * @note The default reset state of the clock configuration is given below: |
| bogdanm | 0:9b334a45a8ff | 141 | * - MSI ON and used as system clock source (MSI range is not modified |
| bogdanm | 0:9b334a45a8ff | 142 | * - by this function, it keep the value configured by user application) |
| bogdanm | 0:9b334a45a8ff | 143 | * - HSI, HSI_OUT, HSE and PLL OFF |
| bogdanm | 0:9b334a45a8ff | 144 | * - AHB, APB1 and APB2 prescaler set to 1. |
| bogdanm | 0:9b334a45a8ff | 145 | * - CSS and MCO OFF |
| bogdanm | 0:9b334a45a8ff | 146 | * - All interrupts disabled |
| bogdanm | 0:9b334a45a8ff | 147 | * @note This function does not modify the configuration of the |
| bogdanm | 0:9b334a45a8ff | 148 | * @note -Peripheral clocks |
| bogdanm | 0:9b334a45a8ff | 149 | * @note -HSI48, LSI, LSE and RTC clocks |
| bogdanm | 0:9b334a45a8ff | 150 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 151 | */ |
| bogdanm | 0:9b334a45a8ff | 152 | void HAL_RCC_DeInit(void) |
| bogdanm | 0:9b334a45a8ff | 153 | { |
| mbed_official | 113:b3775bf36a83 | 154 | __IO uint32_t tmpreg; |
| mbed_official | 113:b3775bf36a83 | 155 | |
| bogdanm | 0:9b334a45a8ff | 156 | /* Set MSION bit */ |
| bogdanm | 0:9b334a45a8ff | 157 | SET_BIT(RCC->CR, RCC_CR_MSION); |
| bogdanm | 0:9b334a45a8ff | 158 | |
| bogdanm | 0:9b334a45a8ff | 159 | #if defined(STM32L073xx) || defined(STM32L083xx) || \ |
| bogdanm | 0:9b334a45a8ff | 160 | defined(STM32L072xx) || defined(STM32L082xx) || \ |
| mbed_official | 113:b3775bf36a83 | 161 | defined(STM32L071xx) || defined(STM32L081xx) || \ |
| mbed_official | 113:b3775bf36a83 | 162 | defined(STM32L031xx) || defined(STM32L041xx) |
| bogdanm | 0:9b334a45a8ff | 163 | /* Reset HSE, HSI, CSS, PLL */ |
| bogdanm | 0:9b334a45a8ff | 164 | CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ |
| bogdanm | 0:9b334a45a8ff | 165 | RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); |
| mbed_official | 113:b3775bf36a83 | 166 | #elif defined(STM32L011xx) || defined(STM32L021xx) |
| mbed_official | 113:b3775bf36a83 | 167 | CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ |
| mbed_official | 113:b3775bf36a83 | 168 | RCC_CR_HSEON | RCC_CR_PLLON); |
| bogdanm | 0:9b334a45a8ff | 169 | #else |
| bogdanm | 0:9b334a45a8ff | 170 | CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \ |
| bogdanm | 0:9b334a45a8ff | 171 | RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); |
| bogdanm | 0:9b334a45a8ff | 172 | #endif |
| bogdanm | 0:9b334a45a8ff | 173 | |
| mbed_official | 113:b3775bf36a83 | 174 | /* Delay after an RCC peripheral clock */ \ |
| mbed_official | 113:b3775bf36a83 | 175 | tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \ |
| mbed_official | 113:b3775bf36a83 | 176 | UNUSED(tmpreg); |
| mbed_official | 113:b3775bf36a83 | 177 | |
| bogdanm | 0:9b334a45a8ff | 178 | /* Reset HSEBYP bit */ |
| bogdanm | 0:9b334a45a8ff | 179 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
| bogdanm | 0:9b334a45a8ff | 180 | |
| bogdanm | 0:9b334a45a8ff | 181 | /* Reset CFGR register */ |
| bogdanm | 0:9b334a45a8ff | 182 | CLEAR_REG(RCC->CFGR); |
| bogdanm | 0:9b334a45a8ff | 183 | |
| bogdanm | 0:9b334a45a8ff | 184 | /* Disable all interrupts */ |
| bogdanm | 0:9b334a45a8ff | 185 | CLEAR_REG(RCC->CIER); |
| bogdanm | 0:9b334a45a8ff | 186 | } |
| bogdanm | 0:9b334a45a8ff | 187 | |
| bogdanm | 0:9b334a45a8ff | 188 | /** |
| bogdanm | 0:9b334a45a8ff | 189 | * @brief Initializes the RCC extended peripherals clocks |
| bogdanm | 0:9b334a45a8ff | 190 | * @note Initializes the RCC extended peripherals clocks according to the specified parameters in the |
| bogdanm | 0:9b334a45a8ff | 191 | * RCC_PeriphCLKInitTypeDef. |
| mbed_official | 113:b3775bf36a83 | 192 | * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with HAL_RCC_OscConfig() |
| mbed_official | 113:b3775bf36a83 | 193 | * to possibly update HSE divider. |
| bogdanm | 0:9b334a45a8ff | 194 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
| bogdanm | 0:9b334a45a8ff | 195 | * contains the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1, |
| bogdanm | 0:9b334a45a8ff | 196 | * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks). |
| bogdanm | 0:9b334a45a8ff | 197 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 198 | */ |
| bogdanm | 0:9b334a45a8ff | 199 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| bogdanm | 0:9b334a45a8ff | 200 | { |
| mbed_official | 113:b3775bf36a83 | 201 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 202 | uint32_t tmpreg = 0; |
| bogdanm | 0:9b334a45a8ff | 203 | |
| bogdanm | 0:9b334a45a8ff | 204 | /* Check the parameters */ |
| mbed_official | 113:b3775bf36a83 | 205 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
| mbed_official | 113:b3775bf36a83 | 206 | |
| mbed_official | 113:b3775bf36a83 | 207 | /*---------------------------- RTC/LCD configuration -------------------------------*/ |
| mbed_official | 113:b3775bf36a83 | 208 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) |
| mbed_official | 113:b3775bf36a83 | 209 | #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) |
| mbed_official | 113:b3775bf36a83 | 210 | || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) |
| mbed_official | 113:b3775bf36a83 | 211 | #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ |
| mbed_official | 113:b3775bf36a83 | 212 | ) |
| mbed_official | 113:b3775bf36a83 | 213 | { |
| mbed_official | 113:b3775bf36a83 | 214 | /* Reset the Backup domain only if the RTC Clock source selection is modified */ |
| mbed_official | 113:b3775bf36a83 | 215 | if( ((RCC->CR & RCC_CR_RTCPRE) != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) |
| mbed_official | 113:b3775bf36a83 | 216 | #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) |
| mbed_official | 113:b3775bf36a83 | 217 | || ((RCC->CR & RCC_CR_RTCPRE) != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE)) |
| mbed_official | 113:b3775bf36a83 | 218 | #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ |
| mbed_official | 113:b3775bf36a83 | 219 | ) |
| mbed_official | 113:b3775bf36a83 | 220 | { /* Check HSE State */ |
| mbed_official | 113:b3775bf36a83 | 221 | if (((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) && HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) |
| mbed_official | 113:b3775bf36a83 | 222 | { |
| mbed_official | 113:b3775bf36a83 | 223 | /*To update HSE divider, first switch-OFF HSE clock oscillator*/ |
| mbed_official | 113:b3775bf36a83 | 224 | return HAL_ERROR; |
| mbed_official | 113:b3775bf36a83 | 225 | } |
| mbed_official | 113:b3775bf36a83 | 226 | } |
| mbed_official | 113:b3775bf36a83 | 227 | |
| mbed_official | 113:b3775bf36a83 | 228 | /* Enable Power Clock*/ |
| mbed_official | 113:b3775bf36a83 | 229 | __HAL_RCC_PWR_CLK_ENABLE(); |
| mbed_official | 113:b3775bf36a83 | 230 | |
| mbed_official | 113:b3775bf36a83 | 231 | /* Enable write access to Backup domain */ |
| mbed_official | 113:b3775bf36a83 | 232 | SET_BIT(PWR->CR, PWR_CR_DBP); |
| mbed_official | 113:b3775bf36a83 | 233 | |
| mbed_official | 113:b3775bf36a83 | 234 | /* Wait for Backup domain Write protection disable */ |
| mbed_official | 113:b3775bf36a83 | 235 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 236 | |
| mbed_official | 113:b3775bf36a83 | 237 | while((PWR->CR & PWR_CR_DBP) == RESET) |
| mbed_official | 113:b3775bf36a83 | 238 | { |
| mbed_official | 113:b3775bf36a83 | 239 | if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) |
| mbed_official | 113:b3775bf36a83 | 240 | { |
| mbed_official | 113:b3775bf36a83 | 241 | return HAL_TIMEOUT; |
| mbed_official | 113:b3775bf36a83 | 242 | } |
| mbed_official | 113:b3775bf36a83 | 243 | } |
| mbed_official | 113:b3775bf36a83 | 244 | |
| mbed_official | 113:b3775bf36a83 | 245 | /* Reset the Backup domain only if the RTC Clock source selection is modified */ |
| mbed_official | 113:b3775bf36a83 | 246 | if( ((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) |
| mbed_official | 113:b3775bf36a83 | 247 | #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) |
| mbed_official | 113:b3775bf36a83 | 248 | || ((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) |
| mbed_official | 113:b3775bf36a83 | 249 | #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ |
| mbed_official | 113:b3775bf36a83 | 250 | ) |
| mbed_official | 113:b3775bf36a83 | 251 | { |
| mbed_official | 113:b3775bf36a83 | 252 | /* Store the content of CSR register before the reset of Backup Domain */ |
| mbed_official | 113:b3775bf36a83 | 253 | tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); |
| mbed_official | 113:b3775bf36a83 | 254 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
| mbed_official | 113:b3775bf36a83 | 255 | __HAL_RCC_BACKUPRESET_FORCE(); |
| mbed_official | 113:b3775bf36a83 | 256 | __HAL_RCC_BACKUPRESET_RELEASE(); |
| mbed_official | 113:b3775bf36a83 | 257 | /* Restore the Content of CSR register */ |
| mbed_official | 113:b3775bf36a83 | 258 | RCC->CSR = tmpreg; |
| mbed_official | 113:b3775bf36a83 | 259 | |
| mbed_official | 113:b3775bf36a83 | 260 | /* Wait for LSERDY if LSE was enabled */ |
| mbed_official | 113:b3775bf36a83 | 261 | if (HAL_IS_BIT_SET(tmpreg, RCC_CSR_LSERDY)) |
| mbed_official | 113:b3775bf36a83 | 262 | { |
| mbed_official | 113:b3775bf36a83 | 263 | /* Get timeout */ |
| mbed_official | 113:b3775bf36a83 | 264 | tickstart = HAL_GetTick(); |
| mbed_official | 113:b3775bf36a83 | 265 | |
| mbed_official | 113:b3775bf36a83 | 266 | /* Wait till LSE is ready */ |
| mbed_official | 113:b3775bf36a83 | 267 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
| mbed_official | 113:b3775bf36a83 | 268 | { |
| mbed_official | 113:b3775bf36a83 | 269 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
| mbed_official | 113:b3775bf36a83 | 270 | { |
| mbed_official | 113:b3775bf36a83 | 271 | return HAL_TIMEOUT; |
| mbed_official | 113:b3775bf36a83 | 272 | } |
| mbed_official | 113:b3775bf36a83 | 273 | } |
| mbed_official | 113:b3775bf36a83 | 274 | } |
| mbed_official | 113:b3775bf36a83 | 275 | |
| mbed_official | 113:b3775bf36a83 | 276 | /* RTC Clock update*/ |
| mbed_official | 113:b3775bf36a83 | 277 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
| mbed_official | 113:b3775bf36a83 | 278 | |
| mbed_official | 113:b3775bf36a83 | 279 | } |
| mbed_official | 113:b3775bf36a83 | 280 | } |
| mbed_official | 113:b3775bf36a83 | 281 | |
| mbed_official | 113:b3775bf36a83 | 282 | #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) |
| bogdanm | 0:9b334a45a8ff | 283 | /*------------------------------- USART1 Configuration ------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 284 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) |
| bogdanm | 0:9b334a45a8ff | 285 | { |
| bogdanm | 0:9b334a45a8ff | 286 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 287 | assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 288 | |
| bogdanm | 0:9b334a45a8ff | 289 | /* Configure the USART1 clock source */ |
| bogdanm | 0:9b334a45a8ff | 290 | __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 291 | } |
| bogdanm | 0:9b334a45a8ff | 292 | #endif |
| bogdanm | 0:9b334a45a8ff | 293 | |
| bogdanm | 0:9b334a45a8ff | 294 | /*----------------------------- USART2 Configuration --------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 295 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) |
| bogdanm | 0:9b334a45a8ff | 296 | { |
| bogdanm | 0:9b334a45a8ff | 297 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 298 | assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 299 | |
| bogdanm | 0:9b334a45a8ff | 300 | /* Configure the USART2 clock source */ |
| bogdanm | 0:9b334a45a8ff | 301 | __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 302 | } |
| bogdanm | 0:9b334a45a8ff | 303 | |
| bogdanm | 0:9b334a45a8ff | 304 | /*------------------------------ LPUART1 Configuration ------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 305 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) |
| bogdanm | 0:9b334a45a8ff | 306 | { |
| bogdanm | 0:9b334a45a8ff | 307 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 308 | assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 309 | |
| bogdanm | 0:9b334a45a8ff | 310 | /* Configure the LPUAR1 clock source */ |
| bogdanm | 0:9b334a45a8ff | 311 | __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 312 | } |
| bogdanm | 0:9b334a45a8ff | 313 | |
| bogdanm | 0:9b334a45a8ff | 314 | /*------------------------------ I2C1 Configuration ------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 315 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) |
| bogdanm | 0:9b334a45a8ff | 316 | { |
| bogdanm | 0:9b334a45a8ff | 317 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 318 | assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 319 | |
| bogdanm | 0:9b334a45a8ff | 320 | /* Configure the I2C1 clock source */ |
| bogdanm | 0:9b334a45a8ff | 321 | __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 322 | } |
| bogdanm | 0:9b334a45a8ff | 323 | |
| bogdanm | 0:9b334a45a8ff | 324 | #if defined (STM32L071xx) || (STM32L072xx) || defined(STM32L073xx) || \ |
| bogdanm | 0:9b334a45a8ff | 325 | defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 326 | /*------------------------------ I2C3 Configuration ------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 327 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) |
| bogdanm | 0:9b334a45a8ff | 328 | { |
| bogdanm | 0:9b334a45a8ff | 329 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 330 | assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 331 | |
| bogdanm | 0:9b334a45a8ff | 332 | /* Configure the I2C3 clock source */ |
| bogdanm | 0:9b334a45a8ff | 333 | __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 334 | } |
| bogdanm | 0:9b334a45a8ff | 335 | #endif /* defined (STM32L071xx) (STM32L072xx)|| (STM32L073xx)|| (STM32L081xx)|| (STM32L082xx) || (STM32L083xx) */ |
| bogdanm | 0:9b334a45a8ff | 336 | |
| mbed_official | 113:b3775bf36a83 | 337 | #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) |
| bogdanm | 0:9b334a45a8ff | 338 | /*---------------------------- USB and RNG configuration --------------------*/ |
| bogdanm | 0:9b334a45a8ff | 339 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) |
| bogdanm | 0:9b334a45a8ff | 340 | { |
| bogdanm | 0:9b334a45a8ff | 341 | assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 342 | __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); |
| bogdanm | 0:9b334a45a8ff | 343 | } |
| bogdanm | 0:9b334a45a8ff | 344 | #endif |
| bogdanm | 0:9b334a45a8ff | 345 | |
| bogdanm | 0:9b334a45a8ff | 346 | /*---------------------------- LPTIM1 configuration ------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 347 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) |
| bogdanm | 0:9b334a45a8ff | 348 | { |
| bogdanm | 0:9b334a45a8ff | 349 | assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 350 | __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection); |
| bogdanm | 0:9b334a45a8ff | 351 | } |
| bogdanm | 0:9b334a45a8ff | 352 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 353 | } |
| bogdanm | 0:9b334a45a8ff | 354 | |
| bogdanm | 0:9b334a45a8ff | 355 | |
| bogdanm | 0:9b334a45a8ff | 356 | |
| bogdanm | 0:9b334a45a8ff | 357 | /** |
| bogdanm | 0:9b334a45a8ff | 358 | * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. |
| bogdanm | 0:9b334a45a8ff | 359 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
| bogdanm | 0:9b334a45a8ff | 360 | * returns the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1, |
| bogdanm | 0:9b334a45a8ff | 361 | * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks). |
| bogdanm | 0:9b334a45a8ff | 362 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 363 | */ |
| bogdanm | 0:9b334a45a8ff | 364 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| bogdanm | 0:9b334a45a8ff | 365 | { |
| bogdanm | 0:9b334a45a8ff | 366 | /* Set all possible values for the extended clock type parameter -----------*/ |
| bogdanm | 0:9b334a45a8ff | 367 | /* Common part first */ |
| mbed_official | 113:b3775bf36a83 | 368 | #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) |
| bogdanm | 0:9b334a45a8ff | 369 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \ |
| bogdanm | 0:9b334a45a8ff | 370 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1; |
| bogdanm | 0:9b334a45a8ff | 371 | #endif |
| bogdanm | 0:9b334a45a8ff | 372 | #if defined(STM32L052xx) || defined(STM32L062xx) |
| bogdanm | 0:9b334a45a8ff | 373 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 374 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \ |
| bogdanm | 0:9b334a45a8ff | 375 | RCC_PERIPHCLK_LPTIM1 ; |
| bogdanm | 0:9b334a45a8ff | 376 | #endif |
| bogdanm | 0:9b334a45a8ff | 377 | #if defined(STM32L053xx) || defined(STM32L063xx) |
| bogdanm | 0:9b334a45a8ff | 378 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 379 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \ |
| bogdanm | 0:9b334a45a8ff | 380 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD; |
| bogdanm | 0:9b334a45a8ff | 381 | #endif |
| bogdanm | 0:9b334a45a8ff | 382 | #if defined(STM32L072xx) || defined(STM32L082xx) |
| bogdanm | 0:9b334a45a8ff | 383 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 384 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \ |
| bogdanm | 0:9b334a45a8ff | 385 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 ; |
| bogdanm | 0:9b334a45a8ff | 386 | #endif |
| bogdanm | 0:9b334a45a8ff | 387 | #if defined(STM32L073xx) || defined(STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 388 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 389 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \ |
| bogdanm | 0:9b334a45a8ff | 390 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD; |
| bogdanm | 0:9b334a45a8ff | 391 | |
| bogdanm | 0:9b334a45a8ff | 392 | #endif |
| bogdanm | 0:9b334a45a8ff | 393 | #if defined(STM32L051xx) || defined(STM32L061xx) |
| bogdanm | 0:9b334a45a8ff | 394 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 395 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1; |
| bogdanm | 0:9b334a45a8ff | 396 | #endif |
| bogdanm | 0:9b334a45a8ff | 397 | #if defined(STM32L071xx) || defined(STM32L081xx) |
| bogdanm | 0:9b334a45a8ff | 398 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 399 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \ |
| bogdanm | 0:9b334a45a8ff | 400 | RCC_PERIPHCLK_LPTIM1; |
| bogdanm | 0:9b334a45a8ff | 401 | #endif |
| bogdanm | 0:9b334a45a8ff | 402 | |
| mbed_official | 113:b3775bf36a83 | 403 | #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) |
| bogdanm | 0:9b334a45a8ff | 404 | /* Get the USART1 configuration --------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 405 | PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 406 | #endif |
| bogdanm | 0:9b334a45a8ff | 407 | /* Get the USART2 clock source ---------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 408 | PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 409 | /* Get the LPUART1 clock source ---------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 410 | PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 411 | /* Get the I2C1 clock source -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 412 | PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 413 | #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || \ |
| bogdanm | 0:9b334a45a8ff | 414 | defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 415 | /* Get the I2C3 clock source -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 416 | PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 417 | #endif /* defined (STM32L071xx) || (STM32L073xx) || (STM32L082xx) || (STM32L082xx) || (STM32L083xx) */ |
| bogdanm | 0:9b334a45a8ff | 418 | /* Get the LPTIM1 clock source -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 419 | PeriphClkInit->LptimClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 420 | /* Get the RTC clock source -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 421 | PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 422 | #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 423 | PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection; |
| bogdanm | 0:9b334a45a8ff | 424 | #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ |
| bogdanm | 0:9b334a45a8ff | 425 | |
| mbed_official | 113:b3775bf36a83 | 426 | #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) |
| bogdanm | 0:9b334a45a8ff | 427 | /* Get the USB/RNG clock source -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 428 | PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 429 | #endif |
| bogdanm | 0:9b334a45a8ff | 430 | } |
| bogdanm | 0:9b334a45a8ff | 431 | |
| bogdanm | 0:9b334a45a8ff | 432 | /** |
| mbed_official | 113:b3775bf36a83 | 433 | * @brief Return the peripheral clock frequency for some peripherals |
| mbed_official | 113:b3775bf36a83 | 434 | * @note Return 0 if peripheral clock identifier not managed by this API |
| mbed_official | 113:b3775bf36a83 | 435 | * @param PeriphClk: Peripheral clock identifier |
| mbed_official | 113:b3775bf36a83 | 436 | * This parameter can be one of the following values: |
| mbed_official | 113:b3775bf36a83 | 437 | * @arg RCC_PERIPHCLK_RTC: RTC peripheral clock |
| mbed_official | 113:b3775bf36a83 | 438 | * @arg RCC_PERIPHCLK_LCD: LCD peripheral clock (*) |
| mbed_official | 113:b3775bf36a83 | 439 | * @arg RCC_PERIPHCLK_USB: USB or RNG peripheral clock (*) |
| mbed_official | 113:b3775bf36a83 | 440 | * @arg RCC_PERIPHCLK_USART1: USART1 peripheral clock (*) |
| mbed_official | 113:b3775bf36a83 | 441 | * @arg RCC_PERIPHCLK_USART2: USART2 peripheral clock |
| mbed_official | 113:b3775bf36a83 | 442 | * @arg RCC_PERIPHCLK_LPUART1: LPUART1 peripheral clock |
| mbed_official | 113:b3775bf36a83 | 443 | * @arg RCC_PERIPHCLK_I2C1: I2C1 peripheral clock |
| mbed_official | 113:b3775bf36a83 | 444 | * @arg RCC_PERIPHCLK_I2C2: I2C2 peripheral clock (*) |
| mbed_official | 113:b3775bf36a83 | 445 | * @arg RCC_PERIPHCLK_I2C3: I2C3 peripheral clock (*) |
| mbed_official | 113:b3775bf36a83 | 446 | * @note (*) means that this peripheral is not present on all the STM32L0xx devices |
| mbed_official | 113:b3775bf36a83 | 447 | * @retval Frequency in Hz (0: means that no available frequency for the peripheral) |
| mbed_official | 113:b3775bf36a83 | 448 | */ |
| mbed_official | 113:b3775bf36a83 | 449 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) |
| mbed_official | 113:b3775bf36a83 | 450 | { |
| mbed_official | 113:b3775bf36a83 | 451 | uint32_t srcclk = 0, clkprediv = 0, frequency = 0; |
| mbed_official | 113:b3775bf36a83 | 452 | #if defined(USB) |
| mbed_official | 113:b3775bf36a83 | 453 | uint32_t pllmul = 0, plldiv = 0, pllvco = 0; |
| mbed_official | 113:b3775bf36a83 | 454 | #endif /* USB */ |
| mbed_official | 113:b3775bf36a83 | 455 | |
| mbed_official | 113:b3775bf36a83 | 456 | /* Check the parameters */ |
| mbed_official | 113:b3775bf36a83 | 457 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); |
| mbed_official | 113:b3775bf36a83 | 458 | |
| mbed_official | 113:b3775bf36a83 | 459 | switch(PeriphClk) |
| mbed_official | 113:b3775bf36a83 | 460 | { |
| mbed_official | 113:b3775bf36a83 | 461 | case RCC_PERIPHCLK_RTC: |
| mbed_official | 113:b3775bf36a83 | 462 | { |
| mbed_official | 113:b3775bf36a83 | 463 | /* Get the current RTC source */ |
| mbed_official | 113:b3775bf36a83 | 464 | srcclk = __HAL_RCC_GET_RTC_SOURCE(); |
| mbed_official | 113:b3775bf36a83 | 465 | |
| mbed_official | 113:b3775bf36a83 | 466 | /* Check if LSE is ready and if RTC clock selection is LSE */ |
| mbed_official | 113:b3775bf36a83 | 467 | if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))) |
| mbed_official | 113:b3775bf36a83 | 468 | { |
| mbed_official | 113:b3775bf36a83 | 469 | frequency = LSE_VALUE; |
| mbed_official | 113:b3775bf36a83 | 470 | } |
| mbed_official | 113:b3775bf36a83 | 471 | /* Check if LSI is ready and if RTC clock selection is LSI */ |
| mbed_official | 113:b3775bf36a83 | 472 | else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) |
| mbed_official | 113:b3775bf36a83 | 473 | { |
| mbed_official | 113:b3775bf36a83 | 474 | frequency = LSI_VALUE; |
| mbed_official | 113:b3775bf36a83 | 475 | } |
| mbed_official | 113:b3775bf36a83 | 476 | /* Check if HSE is ready and if RTC clock selection is HSE*/ |
| mbed_official | 113:b3775bf36a83 | 477 | else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) |
| mbed_official | 113:b3775bf36a83 | 478 | { |
| mbed_official | 113:b3775bf36a83 | 479 | /* Get the current HSE clock divider*/ |
| mbed_official | 113:b3775bf36a83 | 480 | clkprediv=__HAL_RCC_GET_RTC_HSE_PRESCALER(); |
| mbed_official | 113:b3775bf36a83 | 481 | |
| mbed_official | 113:b3775bf36a83 | 482 | switch (clkprediv) |
| mbed_official | 113:b3775bf36a83 | 483 | { |
| mbed_official | 113:b3775bf36a83 | 484 | case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */ |
| mbed_official | 113:b3775bf36a83 | 485 | { |
| mbed_official | 113:b3775bf36a83 | 486 | frequency = HSE_VALUE / 16; |
| mbed_official | 113:b3775bf36a83 | 487 | break; |
| mbed_official | 113:b3775bf36a83 | 488 | } |
| mbed_official | 113:b3775bf36a83 | 489 | case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */ |
| mbed_official | 113:b3775bf36a83 | 490 | { |
| mbed_official | 113:b3775bf36a83 | 491 | frequency = HSE_VALUE / 8; |
| mbed_official | 113:b3775bf36a83 | 492 | break; |
| mbed_official | 113:b3775bf36a83 | 493 | } |
| mbed_official | 113:b3775bf36a83 | 494 | case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */ |
| mbed_official | 113:b3775bf36a83 | 495 | { |
| mbed_official | 113:b3775bf36a83 | 496 | frequency = HSE_VALUE / 4; |
| mbed_official | 113:b3775bf36a83 | 497 | break; |
| mbed_official | 113:b3775bf36a83 | 498 | } |
| mbed_official | 113:b3775bf36a83 | 499 | default: |
| mbed_official | 113:b3775bf36a83 | 500 | { |
| mbed_official | 113:b3775bf36a83 | 501 | frequency = HSE_VALUE / 2; |
| mbed_official | 113:b3775bf36a83 | 502 | break; |
| mbed_official | 113:b3775bf36a83 | 503 | } |
| mbed_official | 113:b3775bf36a83 | 504 | } |
| mbed_official | 113:b3775bf36a83 | 505 | } |
| mbed_official | 113:b3775bf36a83 | 506 | /* Clock not enabled for RTC*/ |
| mbed_official | 113:b3775bf36a83 | 507 | else |
| mbed_official | 113:b3775bf36a83 | 508 | { |
| mbed_official | 113:b3775bf36a83 | 509 | frequency = 0; |
| mbed_official | 113:b3775bf36a83 | 510 | } |
| mbed_official | 113:b3775bf36a83 | 511 | break; |
| mbed_official | 113:b3775bf36a83 | 512 | } |
| mbed_official | 113:b3775bf36a83 | 513 | |
| mbed_official | 113:b3775bf36a83 | 514 | #if defined(LCD) |
| mbed_official | 113:b3775bf36a83 | 515 | |
| mbed_official | 113:b3775bf36a83 | 516 | case RCC_PERIPHCLK_LCD: |
| mbed_official | 113:b3775bf36a83 | 517 | { |
| mbed_official | 113:b3775bf36a83 | 518 | /* Get the current LCD source */ |
| mbed_official | 113:b3775bf36a83 | 519 | srcclk = __HAL_RCC_GET_LCD_SOURCE(); |
| mbed_official | 113:b3775bf36a83 | 520 | |
| mbed_official | 113:b3775bf36a83 | 521 | /* Check if LSE is ready and if LCD clock selection is LSE */ |
| mbed_official | 113:b3775bf36a83 | 522 | if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))) |
| mbed_official | 113:b3775bf36a83 | 523 | { |
| mbed_official | 113:b3775bf36a83 | 524 | frequency = LSE_VALUE; |
| mbed_official | 113:b3775bf36a83 | 525 | } |
| mbed_official | 113:b3775bf36a83 | 526 | /* Check if LSI is ready and if LCD clock selection is LSI */ |
| mbed_official | 113:b3775bf36a83 | 527 | else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) |
| mbed_official | 113:b3775bf36a83 | 528 | { |
| mbed_official | 113:b3775bf36a83 | 529 | frequency = LSI_VALUE; |
| mbed_official | 113:b3775bf36a83 | 530 | } |
| mbed_official | 113:b3775bf36a83 | 531 | /* Check if HSE is ready and if LCD clock selection is HSE*/ |
| mbed_official | 113:b3775bf36a83 | 532 | else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) |
| mbed_official | 113:b3775bf36a83 | 533 | { |
| mbed_official | 113:b3775bf36a83 | 534 | /* Get the current HSE clock divider*/ |
| mbed_official | 113:b3775bf36a83 | 535 | clkprediv=__HAL_RCC_GET_RTC_HSE_PRESCALER(); |
| mbed_official | 113:b3775bf36a83 | 536 | |
| mbed_official | 113:b3775bf36a83 | 537 | switch (clkprediv) |
| mbed_official | 113:b3775bf36a83 | 538 | { |
| mbed_official | 113:b3775bf36a83 | 539 | case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */ |
| mbed_official | 113:b3775bf36a83 | 540 | { |
| mbed_official | 113:b3775bf36a83 | 541 | frequency = HSE_VALUE / 16; |
| mbed_official | 113:b3775bf36a83 | 542 | break; |
| mbed_official | 113:b3775bf36a83 | 543 | } |
| mbed_official | 113:b3775bf36a83 | 544 | case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */ |
| mbed_official | 113:b3775bf36a83 | 545 | { |
| mbed_official | 113:b3775bf36a83 | 546 | frequency = HSE_VALUE / 8; |
| mbed_official | 113:b3775bf36a83 | 547 | break; |
| mbed_official | 113:b3775bf36a83 | 548 | } |
| mbed_official | 113:b3775bf36a83 | 549 | case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */ |
| mbed_official | 113:b3775bf36a83 | 550 | { |
| mbed_official | 113:b3775bf36a83 | 551 | frequency = HSE_VALUE / 4; |
| mbed_official | 113:b3775bf36a83 | 552 | break; |
| mbed_official | 113:b3775bf36a83 | 553 | } |
| mbed_official | 113:b3775bf36a83 | 554 | default: |
| mbed_official | 113:b3775bf36a83 | 555 | { |
| mbed_official | 113:b3775bf36a83 | 556 | frequency = HSE_VALUE / 2; |
| mbed_official | 113:b3775bf36a83 | 557 | break; |
| mbed_official | 113:b3775bf36a83 | 558 | } |
| mbed_official | 113:b3775bf36a83 | 559 | } |
| mbed_official | 113:b3775bf36a83 | 560 | } |
| mbed_official | 113:b3775bf36a83 | 561 | /* Clock not enabled for LCD*/ |
| mbed_official | 113:b3775bf36a83 | 562 | else |
| mbed_official | 113:b3775bf36a83 | 563 | { |
| mbed_official | 113:b3775bf36a83 | 564 | frequency = 0; |
| mbed_official | 113:b3775bf36a83 | 565 | } |
| mbed_official | 113:b3775bf36a83 | 566 | break; |
| mbed_official | 113:b3775bf36a83 | 567 | } |
| mbed_official | 113:b3775bf36a83 | 568 | #endif /* LCD */ |
| mbed_official | 113:b3775bf36a83 | 569 | |
| mbed_official | 113:b3775bf36a83 | 570 | #if defined(USB) |
| mbed_official | 113:b3775bf36a83 | 571 | case RCC_PERIPHCLK_USB: |
| mbed_official | 113:b3775bf36a83 | 572 | { |
| mbed_official | 113:b3775bf36a83 | 573 | /* Get the current USB source */ |
| mbed_official | 113:b3775bf36a83 | 574 | srcclk = __HAL_RCC_GET_USB_SOURCE(); |
| mbed_official | 113:b3775bf36a83 | 575 | |
| mbed_official | 113:b3775bf36a83 | 576 | if((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) |
| mbed_official | 113:b3775bf36a83 | 577 | { |
| mbed_official | 113:b3775bf36a83 | 578 | /* Get PLL clock source and multiplication factor ----------------------*/ |
| mbed_official | 113:b3775bf36a83 | 579 | pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; |
| mbed_official | 113:b3775bf36a83 | 580 | plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; |
| mbed_official | 113:b3775bf36a83 | 581 | pllmul = PLLMulTable[(pllmul >> 18)]; |
| mbed_official | 113:b3775bf36a83 | 582 | plldiv = (plldiv >> 22) + 1; |
| mbed_official | 113:b3775bf36a83 | 583 | |
| mbed_official | 113:b3775bf36a83 | 584 | /* Compute PLL clock input */ |
| mbed_official | 113:b3775bf36a83 | 585 | if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) |
| mbed_official | 113:b3775bf36a83 | 586 | { |
| mbed_official | 113:b3775bf36a83 | 587 | if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0) |
| mbed_official | 113:b3775bf36a83 | 588 | { |
| mbed_official | 113:b3775bf36a83 | 589 | pllvco = (HSI_VALUE >> 2); |
| mbed_official | 113:b3775bf36a83 | 590 | } |
| mbed_official | 113:b3775bf36a83 | 591 | else |
| mbed_official | 113:b3775bf36a83 | 592 | { |
| mbed_official | 113:b3775bf36a83 | 593 | pllvco = HSI_VALUE; |
| mbed_official | 113:b3775bf36a83 | 594 | } |
| mbed_official | 113:b3775bf36a83 | 595 | } |
| mbed_official | 113:b3775bf36a83 | 596 | else /* HSE source */ |
| mbed_official | 113:b3775bf36a83 | 597 | { |
| mbed_official | 113:b3775bf36a83 | 598 | pllvco = HSE_VALUE; |
| mbed_official | 113:b3775bf36a83 | 599 | } |
| mbed_official | 113:b3775bf36a83 | 600 | /* pllvco * pllmul / plldiv */ |
| mbed_official | 113:b3775bf36a83 | 601 | pllvco = (pllvco * pllmul); |
| mbed_official | 113:b3775bf36a83 | 602 | frequency = (pllvco/ plldiv); |
| mbed_official | 113:b3775bf36a83 | 603 | |
| mbed_official | 113:b3775bf36a83 | 604 | } |
| mbed_official | 113:b3775bf36a83 | 605 | else if((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) |
| mbed_official | 113:b3775bf36a83 | 606 | { |
| mbed_official | 113:b3775bf36a83 | 607 | frequency = HSI48_VALUE; |
| mbed_official | 113:b3775bf36a83 | 608 | } |
| mbed_official | 113:b3775bf36a83 | 609 | else /* RCC_USBCLKSOURCE_NONE */ |
| mbed_official | 113:b3775bf36a83 | 610 | { |
| mbed_official | 113:b3775bf36a83 | 611 | frequency = 0; |
| mbed_official | 113:b3775bf36a83 | 612 | } |
| mbed_official | 113:b3775bf36a83 | 613 | break; |
| mbed_official | 113:b3775bf36a83 | 614 | } |
| mbed_official | 113:b3775bf36a83 | 615 | #endif /* USB */ |
| mbed_official | 113:b3775bf36a83 | 616 | #if defined(USART1) |
| mbed_official | 113:b3775bf36a83 | 617 | case RCC_PERIPHCLK_USART1: |
| mbed_official | 113:b3775bf36a83 | 618 | { |
| mbed_official | 113:b3775bf36a83 | 619 | /* Get the current USART1 source */ |
| mbed_official | 113:b3775bf36a83 | 620 | srcclk = __HAL_RCC_GET_USART1_SOURCE(); |
| mbed_official | 113:b3775bf36a83 | 621 | |
| mbed_official | 113:b3775bf36a83 | 622 | /* Check if USART1 clock selection is PCLK2 */ |
| mbed_official | 113:b3775bf36a83 | 623 | if (srcclk == RCC_USART1CLKSOURCE_PCLK2) |
| mbed_official | 113:b3775bf36a83 | 624 | { |
| mbed_official | 113:b3775bf36a83 | 625 | frequency = HAL_RCC_GetPCLK2Freq(); |
| mbed_official | 113:b3775bf36a83 | 626 | } |
| mbed_official | 113:b3775bf36a83 | 627 | /* Check if HSI is ready and if USART1 clock selection is HSI */ |
| mbed_official | 113:b3775bf36a83 | 628 | else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) |
| mbed_official | 113:b3775bf36a83 | 629 | { |
| mbed_official | 113:b3775bf36a83 | 630 | frequency = HSI_VALUE; |
| mbed_official | 113:b3775bf36a83 | 631 | } |
| mbed_official | 113:b3775bf36a83 | 632 | /* Check if USART1 clock selection is SYSCLK */ |
| mbed_official | 113:b3775bf36a83 | 633 | else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) |
| mbed_official | 113:b3775bf36a83 | 634 | { |
| mbed_official | 113:b3775bf36a83 | 635 | frequency = HAL_RCC_GetSysClockFreq(); |
| mbed_official | 113:b3775bf36a83 | 636 | } |
| mbed_official | 113:b3775bf36a83 | 637 | /* Check if LSE is ready and if USART1 clock selection is LSE */ |
| mbed_official | 113:b3775bf36a83 | 638 | else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))) |
| mbed_official | 113:b3775bf36a83 | 639 | { |
| mbed_official | 113:b3775bf36a83 | 640 | frequency = LSE_VALUE; |
| mbed_official | 113:b3775bf36a83 | 641 | } |
| mbed_official | 113:b3775bf36a83 | 642 | /* Clock not enabled for USART1*/ |
| mbed_official | 113:b3775bf36a83 | 643 | else |
| mbed_official | 113:b3775bf36a83 | 644 | { |
| mbed_official | 113:b3775bf36a83 | 645 | frequency = 0; |
| mbed_official | 113:b3775bf36a83 | 646 | } |
| mbed_official | 113:b3775bf36a83 | 647 | break; |
| mbed_official | 113:b3775bf36a83 | 648 | } |
| mbed_official | 113:b3775bf36a83 | 649 | #endif /* USART1 */ |
| mbed_official | 113:b3775bf36a83 | 650 | case RCC_PERIPHCLK_USART2: |
| mbed_official | 113:b3775bf36a83 | 651 | { |
| mbed_official | 113:b3775bf36a83 | 652 | /* Get the current USART2 source */ |
| mbed_official | 113:b3775bf36a83 | 653 | srcclk = __HAL_RCC_GET_USART2_SOURCE(); |
| mbed_official | 113:b3775bf36a83 | 654 | |
| mbed_official | 113:b3775bf36a83 | 655 | /* Check if USART2 clock selection is PCLK1 */ |
| mbed_official | 113:b3775bf36a83 | 656 | if (srcclk == RCC_USART2CLKSOURCE_PCLK1) |
| mbed_official | 113:b3775bf36a83 | 657 | { |
| mbed_official | 113:b3775bf36a83 | 658 | frequency = HAL_RCC_GetPCLK1Freq(); |
| mbed_official | 113:b3775bf36a83 | 659 | } |
| mbed_official | 113:b3775bf36a83 | 660 | /* Check if HSI is ready and if USART2 clock selection is HSI */ |
| mbed_official | 113:b3775bf36a83 | 661 | else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) |
| mbed_official | 113:b3775bf36a83 | 662 | { |
| mbed_official | 113:b3775bf36a83 | 663 | frequency = HSI_VALUE; |
| mbed_official | 113:b3775bf36a83 | 664 | } |
| mbed_official | 113:b3775bf36a83 | 665 | /* Check if USART2 clock selection is SYSCLK */ |
| mbed_official | 113:b3775bf36a83 | 666 | else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) |
| mbed_official | 113:b3775bf36a83 | 667 | { |
| mbed_official | 113:b3775bf36a83 | 668 | frequency = HAL_RCC_GetSysClockFreq(); |
| mbed_official | 113:b3775bf36a83 | 669 | } |
| mbed_official | 113:b3775bf36a83 | 670 | /* Check if LSE is ready and if USART2 clock selection is LSE */ |
| mbed_official | 113:b3775bf36a83 | 671 | else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))) |
| mbed_official | 113:b3775bf36a83 | 672 | { |
| mbed_official | 113:b3775bf36a83 | 673 | frequency = LSE_VALUE; |
| mbed_official | 113:b3775bf36a83 | 674 | } |
| mbed_official | 113:b3775bf36a83 | 675 | /* Clock not enabled for USART2*/ |
| mbed_official | 113:b3775bf36a83 | 676 | else |
| mbed_official | 113:b3775bf36a83 | 677 | { |
| mbed_official | 113:b3775bf36a83 | 678 | frequency = 0; |
| mbed_official | 113:b3775bf36a83 | 679 | } |
| mbed_official | 113:b3775bf36a83 | 680 | break; |
| mbed_official | 113:b3775bf36a83 | 681 | } |
| mbed_official | 113:b3775bf36a83 | 682 | case RCC_PERIPHCLK_LPUART1: |
| mbed_official | 113:b3775bf36a83 | 683 | { |
| mbed_official | 113:b3775bf36a83 | 684 | /* Get the current LPUART1 source */ |
| mbed_official | 113:b3775bf36a83 | 685 | srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); |
| mbed_official | 113:b3775bf36a83 | 686 | |
| mbed_official | 113:b3775bf36a83 | 687 | /* Check if LPUART1 clock selection is PCLK1 */ |
| mbed_official | 113:b3775bf36a83 | 688 | if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1) |
| mbed_official | 113:b3775bf36a83 | 689 | { |
| mbed_official | 113:b3775bf36a83 | 690 | frequency = HAL_RCC_GetPCLK1Freq(); |
| mbed_official | 113:b3775bf36a83 | 691 | } |
| mbed_official | 113:b3775bf36a83 | 692 | /* Check if HSI is ready and if LPUART1 clock selection is HSI */ |
| mbed_official | 113:b3775bf36a83 | 693 | else if ((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) |
| mbed_official | 113:b3775bf36a83 | 694 | { |
| mbed_official | 113:b3775bf36a83 | 695 | frequency = HSI_VALUE; |
| mbed_official | 113:b3775bf36a83 | 696 | } |
| mbed_official | 113:b3775bf36a83 | 697 | /* Check if LPUART1 clock selection is SYSCLK */ |
| mbed_official | 113:b3775bf36a83 | 698 | else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) |
| mbed_official | 113:b3775bf36a83 | 699 | { |
| mbed_official | 113:b3775bf36a83 | 700 | frequency = HAL_RCC_GetSysClockFreq(); |
| mbed_official | 113:b3775bf36a83 | 701 | } |
| mbed_official | 113:b3775bf36a83 | 702 | /* Check if LSE is ready and if LPUART1 clock selection is LSE */ |
| mbed_official | 113:b3775bf36a83 | 703 | else if ((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))) |
| mbed_official | 113:b3775bf36a83 | 704 | { |
| mbed_official | 113:b3775bf36a83 | 705 | frequency = LSE_VALUE; |
| mbed_official | 113:b3775bf36a83 | 706 | } |
| mbed_official | 113:b3775bf36a83 | 707 | /* Clock not enabled for LPUART1*/ |
| mbed_official | 113:b3775bf36a83 | 708 | else |
| mbed_official | 113:b3775bf36a83 | 709 | { |
| mbed_official | 113:b3775bf36a83 | 710 | frequency = 0; |
| mbed_official | 113:b3775bf36a83 | 711 | } |
| mbed_official | 113:b3775bf36a83 | 712 | break; |
| mbed_official | 113:b3775bf36a83 | 713 | } |
| mbed_official | 113:b3775bf36a83 | 714 | case RCC_PERIPHCLK_I2C1: |
| mbed_official | 113:b3775bf36a83 | 715 | { |
| mbed_official | 113:b3775bf36a83 | 716 | /* Get the current I2C1 source */ |
| mbed_official | 113:b3775bf36a83 | 717 | srcclk = __HAL_RCC_GET_I2C1_SOURCE(); |
| mbed_official | 113:b3775bf36a83 | 718 | |
| mbed_official | 113:b3775bf36a83 | 719 | /* Check if I2C1 clock selection is PCLK1 */ |
| mbed_official | 113:b3775bf36a83 | 720 | if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) |
| mbed_official | 113:b3775bf36a83 | 721 | { |
| mbed_official | 113:b3775bf36a83 | 722 | frequency = HAL_RCC_GetPCLK1Freq(); |
| mbed_official | 113:b3775bf36a83 | 723 | } |
| mbed_official | 113:b3775bf36a83 | 724 | /* Check if HSI is ready and if I2C1 clock selection is HSI */ |
| mbed_official | 113:b3775bf36a83 | 725 | else if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) |
| mbed_official | 113:b3775bf36a83 | 726 | { |
| mbed_official | 113:b3775bf36a83 | 727 | frequency = HSI_VALUE; |
| mbed_official | 113:b3775bf36a83 | 728 | } |
| mbed_official | 113:b3775bf36a83 | 729 | /* Check if I2C1 clock selection is SYSCLK */ |
| mbed_official | 113:b3775bf36a83 | 730 | else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) |
| mbed_official | 113:b3775bf36a83 | 731 | { |
| mbed_official | 113:b3775bf36a83 | 732 | frequency = HAL_RCC_GetSysClockFreq(); |
| mbed_official | 113:b3775bf36a83 | 733 | } |
| mbed_official | 113:b3775bf36a83 | 734 | /* Clock not enabled for I2C1*/ |
| mbed_official | 113:b3775bf36a83 | 735 | else |
| mbed_official | 113:b3775bf36a83 | 736 | { |
| mbed_official | 113:b3775bf36a83 | 737 | frequency = 0; |
| mbed_official | 113:b3775bf36a83 | 738 | } |
| mbed_official | 113:b3775bf36a83 | 739 | break; |
| mbed_official | 113:b3775bf36a83 | 740 | } |
| mbed_official | 113:b3775bf36a83 | 741 | #if defined(I2C2) |
| mbed_official | 113:b3775bf36a83 | 742 | case RCC_PERIPHCLK_I2C2: |
| mbed_official | 113:b3775bf36a83 | 743 | { |
| mbed_official | 113:b3775bf36a83 | 744 | |
| mbed_official | 113:b3775bf36a83 | 745 | /* Check if I2C2 on APB1 clock enabled*/ |
| mbed_official | 113:b3775bf36a83 | 746 | if (READ_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))==RCC_APB1ENR_I2C2EN) |
| mbed_official | 113:b3775bf36a83 | 747 | { |
| mbed_official | 113:b3775bf36a83 | 748 | frequency = HAL_RCC_GetPCLK1Freq(); |
| mbed_official | 113:b3775bf36a83 | 749 | } |
| mbed_official | 113:b3775bf36a83 | 750 | else |
| mbed_official | 113:b3775bf36a83 | 751 | { |
| mbed_official | 113:b3775bf36a83 | 752 | frequency = 0; |
| mbed_official | 113:b3775bf36a83 | 753 | } |
| mbed_official | 113:b3775bf36a83 | 754 | break; |
| mbed_official | 113:b3775bf36a83 | 755 | } |
| mbed_official | 113:b3775bf36a83 | 756 | #endif /* I2C2 */ |
| mbed_official | 113:b3775bf36a83 | 757 | |
| mbed_official | 113:b3775bf36a83 | 758 | #if defined(I2C3) |
| mbed_official | 113:b3775bf36a83 | 759 | case RCC_PERIPHCLK_I2C3: |
| mbed_official | 113:b3775bf36a83 | 760 | { |
| mbed_official | 113:b3775bf36a83 | 761 | /* Get the current I2C1 source */ |
| mbed_official | 113:b3775bf36a83 | 762 | srcclk = __HAL_RCC_GET_I2C3_SOURCE(); |
| mbed_official | 113:b3775bf36a83 | 763 | |
| mbed_official | 113:b3775bf36a83 | 764 | /* Check if I2C3 clock selection is PCLK1 */ |
| mbed_official | 113:b3775bf36a83 | 765 | if (srcclk == RCC_I2C3CLKSOURCE_PCLK1) |
| mbed_official | 113:b3775bf36a83 | 766 | { |
| mbed_official | 113:b3775bf36a83 | 767 | frequency = HAL_RCC_GetPCLK1Freq(); |
| mbed_official | 113:b3775bf36a83 | 768 | } |
| mbed_official | 113:b3775bf36a83 | 769 | /* Check if HSI is ready and if I2C3 clock selection is HSI */ |
| mbed_official | 113:b3775bf36a83 | 770 | else if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) |
| mbed_official | 113:b3775bf36a83 | 771 | { |
| mbed_official | 113:b3775bf36a83 | 772 | frequency = HSI_VALUE; |
| mbed_official | 113:b3775bf36a83 | 773 | } |
| mbed_official | 113:b3775bf36a83 | 774 | /* Check if I2C3 clock selection is SYSCLK */ |
| mbed_official | 113:b3775bf36a83 | 775 | else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK) |
| mbed_official | 113:b3775bf36a83 | 776 | { |
| mbed_official | 113:b3775bf36a83 | 777 | frequency = HAL_RCC_GetSysClockFreq(); |
| mbed_official | 113:b3775bf36a83 | 778 | } |
| mbed_official | 113:b3775bf36a83 | 779 | /* Clock not enabled for I2C3*/ |
| mbed_official | 113:b3775bf36a83 | 780 | else |
| mbed_official | 113:b3775bf36a83 | 781 | { |
| mbed_official | 113:b3775bf36a83 | 782 | frequency = 0; |
| mbed_official | 113:b3775bf36a83 | 783 | } |
| mbed_official | 113:b3775bf36a83 | 784 | break; |
| mbed_official | 113:b3775bf36a83 | 785 | } |
| mbed_official | 113:b3775bf36a83 | 786 | #endif /* I2C3 */ |
| mbed_official | 113:b3775bf36a83 | 787 | } |
| mbed_official | 113:b3775bf36a83 | 788 | return(frequency); |
| mbed_official | 113:b3775bf36a83 | 789 | } |
| mbed_official | 113:b3775bf36a83 | 790 | |
| mbed_official | 113:b3775bf36a83 | 791 | /** |
| bogdanm | 0:9b334a45a8ff | 792 | * @brief Enables the LSE Clock Security System. |
| bogdanm | 0:9b334a45a8ff | 793 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 794 | */ |
| bogdanm | 0:9b334a45a8ff | 795 | void HAL_RCCEx_EnableLSECSS(void) |
| bogdanm | 0:9b334a45a8ff | 796 | { |
| bogdanm | 0:9b334a45a8ff | 797 | SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ; |
| bogdanm | 0:9b334a45a8ff | 798 | } |
| bogdanm | 0:9b334a45a8ff | 799 | |
| bogdanm | 0:9b334a45a8ff | 800 | /** |
| bogdanm | 0:9b334a45a8ff | 801 | * @brief Disables the LSE Clock Security System. |
| bogdanm | 0:9b334a45a8ff | 802 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 803 | */ |
| bogdanm | 0:9b334a45a8ff | 804 | void HAL_RCCEx_DisableLSECSS(void) |
| bogdanm | 0:9b334a45a8ff | 805 | { |
| mbed_official | 113:b3775bf36a83 | 806 | /* Disable LSE CSS */ |
| bogdanm | 0:9b334a45a8ff | 807 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ; |
| mbed_official | 113:b3775bf36a83 | 808 | |
| mbed_official | 113:b3775bf36a83 | 809 | /* Disable LSE CSS IT */ |
| mbed_official | 113:b3775bf36a83 | 810 | __HAL_RCC_DISABLE_IT(RCC_IT_CSSLSE); |
| mbed_official | 113:b3775bf36a83 | 811 | } |
| mbed_official | 113:b3775bf36a83 | 812 | |
| mbed_official | 113:b3775bf36a83 | 813 | /** |
| mbed_official | 113:b3775bf36a83 | 814 | * @brief Enable the LSE Clock Security System IT & corresponding EXTI line. |
| mbed_official | 113:b3775bf36a83 | 815 | * @note LSE Clock Security System IT is mapped on RTC EXTI line 19 |
| mbed_official | 113:b3775bf36a83 | 816 | * @retval None |
| mbed_official | 113:b3775bf36a83 | 817 | */ |
| mbed_official | 113:b3775bf36a83 | 818 | void HAL_RCCEx_EnableLSECSS_IT(void) |
| mbed_official | 113:b3775bf36a83 | 819 | { |
| mbed_official | 113:b3775bf36a83 | 820 | /* Enable LSE CSS */ |
| mbed_official | 113:b3775bf36a83 | 821 | SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ; |
| mbed_official | 113:b3775bf36a83 | 822 | |
| mbed_official | 113:b3775bf36a83 | 823 | /* Enable LSE CSS IT */ |
| mbed_official | 113:b3775bf36a83 | 824 | __HAL_RCC_ENABLE_IT(RCC_IT_CSSLSE); |
| mbed_official | 113:b3775bf36a83 | 825 | |
| mbed_official | 113:b3775bf36a83 | 826 | /* Enable IT on EXTI Line 19 */ |
| mbed_official | 113:b3775bf36a83 | 827 | __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); |
| mbed_official | 113:b3775bf36a83 | 828 | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); |
| bogdanm | 0:9b334a45a8ff | 829 | } |
| bogdanm | 0:9b334a45a8ff | 830 | |
| mbed_official | 113:b3775bf36a83 | 831 | /** |
| mbed_official | 113:b3775bf36a83 | 832 | * @brief Handle the RCC LSE Clock Security System interrupt request. |
| mbed_official | 113:b3775bf36a83 | 833 | * @retval None |
| mbed_official | 113:b3775bf36a83 | 834 | */ |
| mbed_official | 113:b3775bf36a83 | 835 | void HAL_RCCEx_LSECSS_IRQHandler(void) |
| mbed_official | 113:b3775bf36a83 | 836 | { |
| mbed_official | 113:b3775bf36a83 | 837 | /* Check RCC LSE CSSF flag */ |
| mbed_official | 113:b3775bf36a83 | 838 | if(__HAL_RCC_GET_IT(RCC_IT_CSSLSE)) |
| mbed_official | 113:b3775bf36a83 | 839 | { |
| mbed_official | 113:b3775bf36a83 | 840 | /* RCC LSE Clock Security System interrupt user callback */ |
| mbed_official | 113:b3775bf36a83 | 841 | HAL_RCCEx_LSECSS_Callback(); |
| mbed_official | 113:b3775bf36a83 | 842 | |
| mbed_official | 113:b3775bf36a83 | 843 | /* Clear RCC LSE CSS pending bit */ |
| mbed_official | 113:b3775bf36a83 | 844 | __HAL_RCC_CLEAR_IT(RCC_IT_CSSLSE); |
| mbed_official | 113:b3775bf36a83 | 845 | } |
| mbed_official | 113:b3775bf36a83 | 846 | } |
| mbed_official | 113:b3775bf36a83 | 847 | |
| mbed_official | 113:b3775bf36a83 | 848 | /** |
| mbed_official | 113:b3775bf36a83 | 849 | * @brief RCCEx LSE Clock Security System interrupt callback. |
| mbed_official | 113:b3775bf36a83 | 850 | * @retval none |
| mbed_official | 113:b3775bf36a83 | 851 | */ |
| mbed_official | 113:b3775bf36a83 | 852 | __weak void HAL_RCCEx_LSECSS_Callback(void) |
| mbed_official | 113:b3775bf36a83 | 853 | { |
| mbed_official | 113:b3775bf36a83 | 854 | /* NOTE : This function should not be modified, when the callback is needed, |
| mbed_official | 113:b3775bf36a83 | 855 | the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file |
| mbed_official | 113:b3775bf36a83 | 856 | */ |
| mbed_official | 113:b3775bf36a83 | 857 | } |
| mbed_official | 113:b3775bf36a83 | 858 | |
| mbed_official | 113:b3775bf36a83 | 859 | #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) |
| bogdanm | 0:9b334a45a8ff | 860 | |
| bogdanm | 0:9b334a45a8ff | 861 | /** |
| bogdanm | 0:9b334a45a8ff | 862 | * @brief Start automatic synchronization using polling mode |
| bogdanm | 0:9b334a45a8ff | 863 | * @param pInit Pointer on RCC_CRSInitTypeDef structure |
| bogdanm | 0:9b334a45a8ff | 864 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 865 | */ |
| bogdanm | 0:9b334a45a8ff | 866 | void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) |
| bogdanm | 0:9b334a45a8ff | 867 | { |
| bogdanm | 0:9b334a45a8ff | 868 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 869 | assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); |
| bogdanm | 0:9b334a45a8ff | 870 | assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); |
| bogdanm | 0:9b334a45a8ff | 871 | assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); |
| bogdanm | 0:9b334a45a8ff | 872 | assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); |
| bogdanm | 0:9b334a45a8ff | 873 | assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); |
| bogdanm | 0:9b334a45a8ff | 874 | assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); |
| bogdanm | 0:9b334a45a8ff | 875 | |
| bogdanm | 0:9b334a45a8ff | 876 | |
| bogdanm | 0:9b334a45a8ff | 877 | /* CONFIGURATION */ |
| bogdanm | 0:9b334a45a8ff | 878 | |
| bogdanm | 0:9b334a45a8ff | 879 | /* Before configuration, reset CRS registers to their default values*/ |
| bogdanm | 0:9b334a45a8ff | 880 | __HAL_RCC_CRS_FORCE_RESET(); |
| bogdanm | 0:9b334a45a8ff | 881 | __HAL_RCC_CRS_RELEASE_RESET(); |
| bogdanm | 0:9b334a45a8ff | 882 | |
| bogdanm | 0:9b334a45a8ff | 883 | /* Configure Synchronization input */ |
| bogdanm | 0:9b334a45a8ff | 884 | /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */ |
| bogdanm | 0:9b334a45a8ff | 885 | CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL); |
| bogdanm | 0:9b334a45a8ff | 886 | |
| bogdanm | 0:9b334a45a8ff | 887 | /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */ |
| bogdanm | 0:9b334a45a8ff | 888 | CRS->CFGR |= pInit->Prescaler; |
| bogdanm | 0:9b334a45a8ff | 889 | |
| bogdanm | 0:9b334a45a8ff | 890 | /* Set the SYNCSRC[1:0] bits according to Source value */ |
| bogdanm | 0:9b334a45a8ff | 891 | CRS->CFGR |= pInit->Source; |
| bogdanm | 0:9b334a45a8ff | 892 | |
| bogdanm | 0:9b334a45a8ff | 893 | /* Set the SYNCSPOL bits according to Polarity value */ |
| bogdanm | 0:9b334a45a8ff | 894 | CRS->CFGR |= pInit->Polarity; |
| bogdanm | 0:9b334a45a8ff | 895 | |
| bogdanm | 0:9b334a45a8ff | 896 | /* Configure Frequency Error Measurement */ |
| bogdanm | 0:9b334a45a8ff | 897 | /* Clear RELOAD[15:0] & FELIM[7:0] bits*/ |
| bogdanm | 0:9b334a45a8ff | 898 | CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM); |
| bogdanm | 0:9b334a45a8ff | 899 | |
| bogdanm | 0:9b334a45a8ff | 900 | /* Set the RELOAD[15:0] bits according to ReloadValue value */ |
| bogdanm | 0:9b334a45a8ff | 901 | CRS->CFGR |= pInit->ReloadValue; |
| bogdanm | 0:9b334a45a8ff | 902 | |
| bogdanm | 0:9b334a45a8ff | 903 | /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ |
| bogdanm | 0:9b334a45a8ff | 904 | CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); |
| bogdanm | 0:9b334a45a8ff | 905 | |
| bogdanm | 0:9b334a45a8ff | 906 | /* Adjust HSI48 oscillator smooth trimming */ |
| bogdanm | 0:9b334a45a8ff | 907 | /* Clear TRIM[5:0] bits */ |
| bogdanm | 0:9b334a45a8ff | 908 | CRS->CR &= ~CRS_CR_TRIM; |
| bogdanm | 0:9b334a45a8ff | 909 | |
| bogdanm | 0:9b334a45a8ff | 910 | /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ |
| bogdanm | 0:9b334a45a8ff | 911 | CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER); |
| bogdanm | 0:9b334a45a8ff | 912 | |
| bogdanm | 0:9b334a45a8ff | 913 | |
| bogdanm | 0:9b334a45a8ff | 914 | /* START AUTOMATIC SYNCHRONIZATION*/ |
| bogdanm | 0:9b334a45a8ff | 915 | |
| bogdanm | 0:9b334a45a8ff | 916 | /* Enable Automatic trimming */ |
| mbed_official | 113:b3775bf36a83 | 917 | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 918 | |
| bogdanm | 0:9b334a45a8ff | 919 | /* Enable Frequency error counter */ |
| mbed_official | 113:b3775bf36a83 | 920 | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 921 | |
| bogdanm | 0:9b334a45a8ff | 922 | } |
| bogdanm | 0:9b334a45a8ff | 923 | |
| bogdanm | 0:9b334a45a8ff | 924 | /** |
| bogdanm | 0:9b334a45a8ff | 925 | * @brief Generate the software synchronization event |
| bogdanm | 0:9b334a45a8ff | 926 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 927 | */ |
| bogdanm | 0:9b334a45a8ff | 928 | void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) |
| bogdanm | 0:9b334a45a8ff | 929 | { |
| bogdanm | 0:9b334a45a8ff | 930 | CRS->CR |= CRS_CR_SWSYNC; |
| bogdanm | 0:9b334a45a8ff | 931 | } |
| bogdanm | 0:9b334a45a8ff | 932 | |
| bogdanm | 0:9b334a45a8ff | 933 | |
| bogdanm | 0:9b334a45a8ff | 934 | /** |
| bogdanm | 0:9b334a45a8ff | 935 | * @brief Function to return synchronization info |
| bogdanm | 0:9b334a45a8ff | 936 | * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure |
| bogdanm | 0:9b334a45a8ff | 937 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 938 | */ |
| bogdanm | 0:9b334a45a8ff | 939 | void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) |
| bogdanm | 0:9b334a45a8ff | 940 | { |
| bogdanm | 0:9b334a45a8ff | 941 | /* Check the parameter */ |
| bogdanm | 0:9b334a45a8ff | 942 | assert_param(pSynchroInfo != NULL); |
| bogdanm | 0:9b334a45a8ff | 943 | |
| bogdanm | 0:9b334a45a8ff | 944 | /* Get the reload value */ |
| bogdanm | 0:9b334a45a8ff | 945 | pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD); |
| bogdanm | 0:9b334a45a8ff | 946 | |
| bogdanm | 0:9b334a45a8ff | 947 | /* Get HSI48 oscillator smooth trimming */ |
| bogdanm | 0:9b334a45a8ff | 948 | pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); |
| bogdanm | 0:9b334a45a8ff | 949 | |
| bogdanm | 0:9b334a45a8ff | 950 | /* Get Frequency error capture */ |
| bogdanm | 0:9b334a45a8ff | 951 | pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); |
| bogdanm | 0:9b334a45a8ff | 952 | |
| bogdanm | 0:9b334a45a8ff | 953 | /* Get Frequency error direction */ |
| bogdanm | 0:9b334a45a8ff | 954 | pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR); |
| bogdanm | 0:9b334a45a8ff | 955 | |
| bogdanm | 0:9b334a45a8ff | 956 | |
| bogdanm | 0:9b334a45a8ff | 957 | } |
| bogdanm | 0:9b334a45a8ff | 958 | |
| bogdanm | 0:9b334a45a8ff | 959 | /** |
| bogdanm | 0:9b334a45a8ff | 960 | * @brief This function handles CRS Synchronization Timeout. |
| bogdanm | 0:9b334a45a8ff | 961 | * @param Timeout: Duration of the timeout |
| bogdanm | 0:9b334a45a8ff | 962 | * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization |
| bogdanm | 0:9b334a45a8ff | 963 | * frequency. |
| bogdanm | 0:9b334a45a8ff | 964 | * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. |
| bogdanm | 0:9b334a45a8ff | 965 | * @retval Combination of Synchronization status |
| bogdanm | 0:9b334a45a8ff | 966 | * This parameter can be a combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 967 | * @arg RCC_CRS_TIMEOUT |
| bogdanm | 0:9b334a45a8ff | 968 | * @arg RCC_CRS_SYNCOK |
| bogdanm | 0:9b334a45a8ff | 969 | * @arg RCC_CRS_SYNCWARM |
| bogdanm | 0:9b334a45a8ff | 970 | * @arg RCC_CRS_SYNCERR |
| bogdanm | 0:9b334a45a8ff | 971 | * @arg RCC_CRS_SYNCMISS |
| bogdanm | 0:9b334a45a8ff | 972 | * @arg RCC_CRS_TRIMOV |
| bogdanm | 0:9b334a45a8ff | 973 | */ |
| bogdanm | 0:9b334a45a8ff | 974 | uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) |
| bogdanm | 0:9b334a45a8ff | 975 | { |
| bogdanm | 0:9b334a45a8ff | 976 | uint32_t crsstatus = RCC_CRS_NONE; |
| bogdanm | 0:9b334a45a8ff | 977 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 978 | |
| bogdanm | 0:9b334a45a8ff | 979 | /* Get timeout */ |
| bogdanm | 0:9b334a45a8ff | 980 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 981 | |
| bogdanm | 0:9b334a45a8ff | 982 | /* Check that if one of CRS flags have been set */ |
| bogdanm | 0:9b334a45a8ff | 983 | while(RCC_CRS_NONE == crsstatus) |
| bogdanm | 0:9b334a45a8ff | 984 | { |
| bogdanm | 0:9b334a45a8ff | 985 | if(Timeout != HAL_MAX_DELAY) |
| bogdanm | 0:9b334a45a8ff | 986 | { |
| bogdanm | 0:9b334a45a8ff | 987 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| bogdanm | 0:9b334a45a8ff | 988 | { |
| bogdanm | 0:9b334a45a8ff | 989 | crsstatus = RCC_CRS_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 990 | } |
| bogdanm | 0:9b334a45a8ff | 991 | } |
| bogdanm | 0:9b334a45a8ff | 992 | /* Check CRS SYNCOK flag */ |
| bogdanm | 0:9b334a45a8ff | 993 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) |
| bogdanm | 0:9b334a45a8ff | 994 | { |
| bogdanm | 0:9b334a45a8ff | 995 | /* CRS SYNC event OK */ |
| bogdanm | 0:9b334a45a8ff | 996 | crsstatus |= RCC_CRS_SYNCOK; |
| bogdanm | 0:9b334a45a8ff | 997 | |
| bogdanm | 0:9b334a45a8ff | 998 | /* Clear CRS SYNC event OK bit */ |
| bogdanm | 0:9b334a45a8ff | 999 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); |
| bogdanm | 0:9b334a45a8ff | 1000 | } |
| bogdanm | 0:9b334a45a8ff | 1001 | |
| bogdanm | 0:9b334a45a8ff | 1002 | /* Check CRS SYNCWARN flag */ |
| bogdanm | 0:9b334a45a8ff | 1003 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) |
| bogdanm | 0:9b334a45a8ff | 1004 | { |
| bogdanm | 0:9b334a45a8ff | 1005 | /* CRS SYNC warning */ |
| bogdanm | 0:9b334a45a8ff | 1006 | crsstatus |= RCC_CRS_SYNCWARM; |
| bogdanm | 0:9b334a45a8ff | 1007 | |
| bogdanm | 0:9b334a45a8ff | 1008 | /* Clear CRS SYNCWARN bit */ |
| bogdanm | 0:9b334a45a8ff | 1009 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); |
| bogdanm | 0:9b334a45a8ff | 1010 | } |
| bogdanm | 0:9b334a45a8ff | 1011 | |
| bogdanm | 0:9b334a45a8ff | 1012 | /* Check CRS TRIM overflow flag */ |
| bogdanm | 0:9b334a45a8ff | 1013 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) |
| bogdanm | 0:9b334a45a8ff | 1014 | { |
| bogdanm | 0:9b334a45a8ff | 1015 | /* CRS SYNC Error */ |
| bogdanm | 0:9b334a45a8ff | 1016 | crsstatus |= RCC_CRS_TRIMOV; |
| bogdanm | 0:9b334a45a8ff | 1017 | |
| bogdanm | 0:9b334a45a8ff | 1018 | /* Clear CRS Error bit */ |
| bogdanm | 0:9b334a45a8ff | 1019 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); |
| bogdanm | 0:9b334a45a8ff | 1020 | } |
| bogdanm | 0:9b334a45a8ff | 1021 | |
| bogdanm | 0:9b334a45a8ff | 1022 | /* Check CRS Error flag */ |
| bogdanm | 0:9b334a45a8ff | 1023 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) |
| bogdanm | 0:9b334a45a8ff | 1024 | { |
| bogdanm | 0:9b334a45a8ff | 1025 | /* CRS SYNC Error */ |
| bogdanm | 0:9b334a45a8ff | 1026 | crsstatus |= RCC_CRS_SYNCERR; |
| bogdanm | 0:9b334a45a8ff | 1027 | |
| bogdanm | 0:9b334a45a8ff | 1028 | /* Clear CRS Error bit */ |
| bogdanm | 0:9b334a45a8ff | 1029 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); |
| bogdanm | 0:9b334a45a8ff | 1030 | } |
| bogdanm | 0:9b334a45a8ff | 1031 | |
| bogdanm | 0:9b334a45a8ff | 1032 | /* Check CRS SYNC Missed flag */ |
| bogdanm | 0:9b334a45a8ff | 1033 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) |
| bogdanm | 0:9b334a45a8ff | 1034 | { |
| bogdanm | 0:9b334a45a8ff | 1035 | /* CRS SYNC Missed */ |
| bogdanm | 0:9b334a45a8ff | 1036 | crsstatus |= RCC_CRS_SYNCMISS; |
| bogdanm | 0:9b334a45a8ff | 1037 | |
| bogdanm | 0:9b334a45a8ff | 1038 | /* Clear CRS SYNC Missed bit */ |
| bogdanm | 0:9b334a45a8ff | 1039 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); |
| bogdanm | 0:9b334a45a8ff | 1040 | } |
| bogdanm | 0:9b334a45a8ff | 1041 | |
| bogdanm | 0:9b334a45a8ff | 1042 | /* Check CRS Expected SYNC flag */ |
| bogdanm | 0:9b334a45a8ff | 1043 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) |
| bogdanm | 0:9b334a45a8ff | 1044 | { |
| bogdanm | 0:9b334a45a8ff | 1045 | /* frequency error counter reached a zero value */ |
| bogdanm | 0:9b334a45a8ff | 1046 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); |
| bogdanm | 0:9b334a45a8ff | 1047 | } |
| bogdanm | 0:9b334a45a8ff | 1048 | } |
| bogdanm | 0:9b334a45a8ff | 1049 | |
| bogdanm | 0:9b334a45a8ff | 1050 | return crsstatus; |
| bogdanm | 0:9b334a45a8ff | 1051 | } |
| bogdanm | 0:9b334a45a8ff | 1052 | /** |
| bogdanm | 0:9b334a45a8ff | 1053 | * @brief Enables Vrefint for the HSI48. |
| bogdanm | 0:9b334a45a8ff | 1054 | * @note This is functional only if the LOCK is not set |
| bogdanm | 0:9b334a45a8ff | 1055 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 1056 | */ |
| bogdanm | 0:9b334a45a8ff | 1057 | void HAL_RCCEx_EnableHSI48_VREFINT(void) |
| bogdanm | 0:9b334a45a8ff | 1058 | { |
| bogdanm | 0:9b334a45a8ff | 1059 | /* Enable the Buffer for the ADC by setting EN_VREFINT bit */ |
| bogdanm | 0:9b334a45a8ff | 1060 | /* and the SYSCFG_CFGR3_ENREF_HSI48 in the CFGR3 register */ |
| bogdanm | 0:9b334a45a8ff | 1061 | SET_BIT (SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); |
| bogdanm | 0:9b334a45a8ff | 1062 | } |
| bogdanm | 0:9b334a45a8ff | 1063 | |
| bogdanm | 0:9b334a45a8ff | 1064 | /** |
| bogdanm | 0:9b334a45a8ff | 1065 | * @brief Disables the Vrefint for the HSI48. |
| bogdanm | 0:9b334a45a8ff | 1066 | * @note This is functional only if the LOCK is not set |
| bogdanm | 0:9b334a45a8ff | 1067 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 1068 | */ |
| bogdanm | 0:9b334a45a8ff | 1069 | void HAL_RCCEx_DisableHSI48_VREFINT(void) |
| bogdanm | 0:9b334a45a8ff | 1070 | { |
| bogdanm | 0:9b334a45a8ff | 1071 | /* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit */ |
| bogdanm | 0:9b334a45a8ff | 1072 | /* and the EN_VREFINT bit in the CFGR3 register */ |
| bogdanm | 0:9b334a45a8ff | 1073 | CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); |
| bogdanm | 0:9b334a45a8ff | 1074 | } |
| mbed_official | 113:b3775bf36a83 | 1075 | #endif /* !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */ |
| bogdanm | 0:9b334a45a8ff | 1076 | |
| mbed_official | 113:b3775bf36a83 | 1077 | /** |
| mbed_official | 113:b3775bf36a83 | 1078 | * @} |
| mbed_official | 113:b3775bf36a83 | 1079 | */ |
| mbed_official | 113:b3775bf36a83 | 1080 | |
| mbed_official | 113:b3775bf36a83 | 1081 | /** |
| mbed_official | 113:b3775bf36a83 | 1082 | * @} |
| mbed_official | 113:b3775bf36a83 | 1083 | */ |
| bogdanm | 0:9b334a45a8ff | 1084 | |
| bogdanm | 0:9b334a45a8ff | 1085 | /** |
| bogdanm | 0:9b334a45a8ff | 1086 | * @} |
| bogdanm | 0:9b334a45a8ff | 1087 | */ |
| bogdanm | 0:9b334a45a8ff | 1088 | |
| bogdanm | 0:9b334a45a8ff | 1089 | /** |
| bogdanm | 0:9b334a45a8ff | 1090 | * @} |
| bogdanm | 0:9b334a45a8ff | 1091 | */ |
| bogdanm | 0:9b334a45a8ff | 1092 | |
| bogdanm | 0:9b334a45a8ff | 1093 | #endif /* HAL_RCC_MODULE_ENABLED */ |
| bogdanm | 0:9b334a45a8ff | 1094 | |
| bogdanm | 0:9b334a45a8ff | 1095 | /** |
| bogdanm | 0:9b334a45a8ff | 1096 | * @} |
| bogdanm | 0:9b334a45a8ff | 1097 | */ |
| bogdanm | 0:9b334a45a8ff | 1098 | |
| bogdanm | 0:9b334a45a8ff | 1099 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| bogdanm | 0:9b334a45a8ff | 1100 |