en 129
fix LPC812 PWM
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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 113:b3775bf36a83
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l0xx_hal_rcc_ex.c |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.2.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 06-February-2015 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Extended RCC HAL module driver. |
| bogdanm | 0:9b334a45a8ff | 8 | * |
| bogdanm | 0:9b334a45a8ff | 9 | * This file provides firmware functions to manage the following |
| bogdanm | 0:9b334a45a8ff | 10 | * functionalities RCC extension peripheral: |
| bogdanm | 0:9b334a45a8ff | 11 | * + Extended Peripheral Control functions |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 14 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 15 | ##### RCC specific features ##### |
| bogdanm | 0:9b334a45a8ff | 16 | ============================================================================== |
| bogdanm | 0:9b334a45a8ff | 17 | For CRS, RCC Extension HAL driver can be used as follows: |
| bogdanm | 0:9b334a45a8ff | 18 | |
| bogdanm | 0:9b334a45a8ff | 19 | (#) In System clock configuration, HSI48 need to be enabled |
| bogdanm | 0:9b334a45a8ff | 20 | |
| bogdanm | 0:9b334a45a8ff | 21 | (#] Enable CRS clock in IP MSP init which will use CRS functions |
| bogdanm | 0:9b334a45a8ff | 22 | |
| bogdanm | 0:9b334a45a8ff | 23 | (#) Call CRS functions like this |
| bogdanm | 0:9b334a45a8ff | 24 | (##) Prepare synchronization configuration necessary for HSI48 calibration |
| bogdanm | 0:9b334a45a8ff | 25 | (+++) Default values can be set for frequency Error Measurement (reload and error limit) |
| bogdanm | 0:9b334a45a8ff | 26 | and also HSI48 oscillator smooth trimming. |
| bogdanm | 0:9b334a45a8ff | 27 | (+++) Macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE can be also used to calculate |
| bogdanm | 0:9b334a45a8ff | 28 | directly reload value with target and synchronization frequencies values |
| bogdanm | 0:9b334a45a8ff | 29 | (##) Call function HAL_RCCEx_CRSConfig which |
| bogdanm | 0:9b334a45a8ff | 30 | (+++) Reset CRS registers to their default values. |
| bogdanm | 0:9b334a45a8ff | 31 | (+++) Configure CRS registers with synchronization configuration |
| bogdanm | 0:9b334a45a8ff | 32 | (+++) Enable automatic calibration and frequency error counter feature |
| bogdanm | 0:9b334a45a8ff | 33 | |
| bogdanm | 0:9b334a45a8ff | 34 | (##) A polling function is provided to wait for complete Synchronization |
| bogdanm | 0:9b334a45a8ff | 35 | (+++) Call function 'HAL_RCCEx_CRSWaitSynchronization()' |
| bogdanm | 0:9b334a45a8ff | 36 | (+++) According to CRS status, user can decide to adjust again the calibration or continue |
| bogdanm | 0:9b334a45a8ff | 37 | application if synchronization is OK |
| bogdanm | 0:9b334a45a8ff | 38 | |
| bogdanm | 0:9b334a45a8ff | 39 | (#) User can retrieve information related to synchronization in calling function |
| bogdanm | 0:9b334a45a8ff | 40 | HAL_RCCEx_CRSGetSynchronizationInfo() |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | (#) Regarding synchronization status and synchronization information, user can try a new calibration |
| bogdanm | 0:9b334a45a8ff | 43 | in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. |
| bogdanm | 0:9b334a45a8ff | 44 | Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), |
| bogdanm | 0:9b334a45a8ff | 45 | it means that the actual frequency is lower than the target (and so, that the TRIM value should be |
| bogdanm | 0:9b334a45a8ff | 46 | incremented), while when it is detected during the upcounting phase it means that the actual frequency |
| bogdanm | 0:9b334a45a8ff | 47 | is higher (and that the TRIM value should be decremented). |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | (#) To use IT mode, user needs to handle it in calling different macros available to do it |
| bogdanm | 0:9b334a45a8ff | 50 | (__HAL_RCC_CRS_XXX_IT). Interruptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler) |
| bogdanm | 0:9b334a45a8ff | 51 | (+++) Call function HAL_RCCEx_CRSConfig() |
| bogdanm | 0:9b334a45a8ff | 52 | (+++) Enable RCC_IRQn (thnaks to NVIC functions) |
| bogdanm | 0:9b334a45a8ff | 53 | (+++) Enable CRS IT (__HAL_RCC_CRS_ENABLE_IT) |
| bogdanm | 0:9b334a45a8ff | 54 | [+++) Implement CRS status management in RCC_CRS_IRQHandler |
| bogdanm | 0:9b334a45a8ff | 55 | |
| bogdanm | 0:9b334a45a8ff | 56 | (#) To force a SYNC EVENT, user can use function 'HAL_RCCEx_CRSSoftwareSynchronizationGenerate()'. Function can be |
| bogdanm | 0:9b334a45a8ff | 57 | called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) |
| bogdanm | 0:9b334a45a8ff | 58 | |
| bogdanm | 0:9b334a45a8ff | 59 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 60 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 61 | * @attention |
| bogdanm | 0:9b334a45a8ff | 62 | * |
| bogdanm | 0:9b334a45a8ff | 63 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 64 | * |
| bogdanm | 0:9b334a45a8ff | 65 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 66 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 67 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 68 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 69 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 70 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 71 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 72 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 73 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 74 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 75 | * |
| bogdanm | 0:9b334a45a8ff | 76 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 77 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 78 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 79 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 80 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 81 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 82 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 83 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 84 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 85 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 86 | * |
| bogdanm | 0:9b334a45a8ff | 87 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 88 | */ |
| bogdanm | 0:9b334a45a8ff | 89 | |
| bogdanm | 0:9b334a45a8ff | 90 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 91 | #include "stm32l0xx_hal.h" |
| bogdanm | 0:9b334a45a8ff | 92 | |
| bogdanm | 0:9b334a45a8ff | 93 | /** @addtogroup STM32L0xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 94 | * @{ |
| bogdanm | 0:9b334a45a8ff | 95 | */ |
| bogdanm | 0:9b334a45a8ff | 96 | |
| bogdanm | 0:9b334a45a8ff | 97 | /** @addtogroup RCCEx |
| bogdanm | 0:9b334a45a8ff | 98 | * @brief RCC Extension HAL module driver |
| bogdanm | 0:9b334a45a8ff | 99 | * @{ |
| bogdanm | 0:9b334a45a8ff | 100 | */ |
| bogdanm | 0:9b334a45a8ff | 101 | |
| bogdanm | 0:9b334a45a8ff | 102 | #ifdef HAL_RCC_MODULE_ENABLED |
| bogdanm | 0:9b334a45a8ff | 103 | |
| bogdanm | 0:9b334a45a8ff | 104 | /** @defgroup RCCEx_Private_Constants |
| bogdanm | 0:9b334a45a8ff | 105 | * @{ |
| bogdanm | 0:9b334a45a8ff | 106 | */ |
| bogdanm | 0:9b334a45a8ff | 107 | /* Bit position in register */ |
| bogdanm | 0:9b334a45a8ff | 108 | #define CRS_CFGR_FELIM_BITNUMBER 16 |
| bogdanm | 0:9b334a45a8ff | 109 | #define CRS_CR_TRIM_BITNUMBER 8 |
| bogdanm | 0:9b334a45a8ff | 110 | #define CRS_ISR_FECAP_BITNUMBER 16 |
| bogdanm | 0:9b334a45a8ff | 111 | |
| bogdanm | 0:9b334a45a8ff | 112 | /** |
| bogdanm | 0:9b334a45a8ff | 113 | * @} |
| bogdanm | 0:9b334a45a8ff | 114 | */ |
| bogdanm | 0:9b334a45a8ff | 115 | |
| bogdanm | 0:9b334a45a8ff | 116 | /** @addtogroup RCCEx_Exported_Functions |
| bogdanm | 0:9b334a45a8ff | 117 | * @{ |
| bogdanm | 0:9b334a45a8ff | 118 | */ |
| bogdanm | 0:9b334a45a8ff | 119 | |
| bogdanm | 0:9b334a45a8ff | 120 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
| bogdanm | 0:9b334a45a8ff | 121 | * @brief Extended Peripheral Initialization and Control functions |
| bogdanm | 0:9b334a45a8ff | 122 | * |
| bogdanm | 0:9b334a45a8ff | 123 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 124 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 125 | ##### Extended Peripheral Control functions ##### |
| bogdanm | 0:9b334a45a8ff | 126 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 127 | [..] |
| bogdanm | 0:9b334a45a8ff | 128 | This subsection provides a set of functions allowing to control the RCC Clocks |
| bogdanm | 0:9b334a45a8ff | 129 | frequencies. |
| bogdanm | 0:9b334a45a8ff | 130 | |
| bogdanm | 0:9b334a45a8ff | 131 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 132 | * @{ |
| bogdanm | 0:9b334a45a8ff | 133 | */ |
| bogdanm | 0:9b334a45a8ff | 134 | |
| bogdanm | 0:9b334a45a8ff | 135 | /** |
| bogdanm | 0:9b334a45a8ff | 136 | * @brief Resets the RCC clock configuration to the default reset state. |
| bogdanm | 0:9b334a45a8ff | 137 | * @note The default reset state of the clock configuration is given below: |
| bogdanm | 0:9b334a45a8ff | 138 | * - MSI ON and used as system clock source (MSI range is not modified |
| bogdanm | 0:9b334a45a8ff | 139 | * - by this function, it keep the value configured by user application) |
| bogdanm | 0:9b334a45a8ff | 140 | * - HSI, HSI_OUT, HSE and PLL OFF |
| bogdanm | 0:9b334a45a8ff | 141 | * - AHB, APB1 and APB2 prescaler set to 1. |
| bogdanm | 0:9b334a45a8ff | 142 | * - CSS and MCO OFF |
| bogdanm | 0:9b334a45a8ff | 143 | * - All interrupts disabled |
| bogdanm | 0:9b334a45a8ff | 144 | * @note This function does not modify the configuration of the |
| bogdanm | 0:9b334a45a8ff | 145 | * @note -Peripheral clocks |
| bogdanm | 0:9b334a45a8ff | 146 | * @note -HSI48, LSI, LSE and RTC clocks |
| bogdanm | 0:9b334a45a8ff | 147 | * @param None |
| bogdanm | 0:9b334a45a8ff | 148 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 149 | */ |
| bogdanm | 0:9b334a45a8ff | 150 | void HAL_RCC_DeInit(void) |
| bogdanm | 0:9b334a45a8ff | 151 | { |
| bogdanm | 0:9b334a45a8ff | 152 | /* Set MSION bit */ |
| bogdanm | 0:9b334a45a8ff | 153 | SET_BIT(RCC->CR, RCC_CR_MSION); |
| bogdanm | 0:9b334a45a8ff | 154 | |
| bogdanm | 0:9b334a45a8ff | 155 | #if defined(STM32L073xx) || defined(STM32L083xx) || \ |
| bogdanm | 0:9b334a45a8ff | 156 | defined(STM32L072xx) || defined(STM32L082xx) || \ |
| bogdanm | 0:9b334a45a8ff | 157 | defined(STM32L071xx) || defined(STM32L081xx) |
| bogdanm | 0:9b334a45a8ff | 158 | /* Reset HSE, HSI, CSS, PLL */ |
| bogdanm | 0:9b334a45a8ff | 159 | CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ |
| bogdanm | 0:9b334a45a8ff | 160 | RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); |
| bogdanm | 0:9b334a45a8ff | 161 | #else |
| bogdanm | 0:9b334a45a8ff | 162 | CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \ |
| bogdanm | 0:9b334a45a8ff | 163 | RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); |
| bogdanm | 0:9b334a45a8ff | 164 | #endif |
| bogdanm | 0:9b334a45a8ff | 165 | |
| bogdanm | 0:9b334a45a8ff | 166 | /* Reset HSEBYP bit */ |
| bogdanm | 0:9b334a45a8ff | 167 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
| bogdanm | 0:9b334a45a8ff | 168 | |
| bogdanm | 0:9b334a45a8ff | 169 | /* Reset CFGR register */ |
| bogdanm | 0:9b334a45a8ff | 170 | CLEAR_REG(RCC->CFGR); |
| bogdanm | 0:9b334a45a8ff | 171 | |
| bogdanm | 0:9b334a45a8ff | 172 | /* Disable all interrupts */ |
| bogdanm | 0:9b334a45a8ff | 173 | CLEAR_REG(RCC->CIER); |
| bogdanm | 0:9b334a45a8ff | 174 | } |
| bogdanm | 0:9b334a45a8ff | 175 | |
| bogdanm | 0:9b334a45a8ff | 176 | /** |
| bogdanm | 0:9b334a45a8ff | 177 | * @brief Initializes the RCC extended peripherals clocks |
| bogdanm | 0:9b334a45a8ff | 178 | * @note Initializes the RCC extended peripherals clocks according to the specified parameters in the |
| bogdanm | 0:9b334a45a8ff | 179 | * RCC_PeriphCLKInitTypeDef. |
| bogdanm | 0:9b334a45a8ff | 180 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
| bogdanm | 0:9b334a45a8ff | 181 | * contains the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1, |
| bogdanm | 0:9b334a45a8ff | 182 | * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks). |
| bogdanm | 0:9b334a45a8ff | 183 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 184 | */ |
| bogdanm | 0:9b334a45a8ff | 185 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| bogdanm | 0:9b334a45a8ff | 186 | { |
| bogdanm | 0:9b334a45a8ff | 187 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 188 | uint32_t tmpreg = 0; |
| bogdanm | 0:9b334a45a8ff | 189 | |
| bogdanm | 0:9b334a45a8ff | 190 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 191 | assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 192 | |
| bogdanm | 0:9b334a45a8ff | 193 | #if !defined (STM32L031xx) && !defined (STM32L041xx) |
| bogdanm | 0:9b334a45a8ff | 194 | /*------------------------------- USART1 Configuration ------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 195 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) |
| bogdanm | 0:9b334a45a8ff | 196 | { |
| bogdanm | 0:9b334a45a8ff | 197 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 198 | assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 199 | |
| bogdanm | 0:9b334a45a8ff | 200 | /* Configure the USART1 clock source */ |
| bogdanm | 0:9b334a45a8ff | 201 | __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 202 | } |
| bogdanm | 0:9b334a45a8ff | 203 | #endif |
| bogdanm | 0:9b334a45a8ff | 204 | |
| bogdanm | 0:9b334a45a8ff | 205 | /*----------------------------- USART2 Configuration --------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 206 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) |
| bogdanm | 0:9b334a45a8ff | 207 | { |
| bogdanm | 0:9b334a45a8ff | 208 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 209 | assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 210 | |
| bogdanm | 0:9b334a45a8ff | 211 | /* Configure the USART2 clock source */ |
| bogdanm | 0:9b334a45a8ff | 212 | __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 213 | } |
| bogdanm | 0:9b334a45a8ff | 214 | |
| bogdanm | 0:9b334a45a8ff | 215 | /*------------------------------ LPUART1 Configuration ------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 216 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) |
| bogdanm | 0:9b334a45a8ff | 217 | { |
| bogdanm | 0:9b334a45a8ff | 218 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 219 | assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 220 | |
| bogdanm | 0:9b334a45a8ff | 221 | /* Configure the LPUAR1 clock source */ |
| bogdanm | 0:9b334a45a8ff | 222 | __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 223 | } |
| bogdanm | 0:9b334a45a8ff | 224 | |
| bogdanm | 0:9b334a45a8ff | 225 | /*------------------------------ I2C1 Configuration ------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 226 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) |
| bogdanm | 0:9b334a45a8ff | 227 | { |
| bogdanm | 0:9b334a45a8ff | 228 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 229 | assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 230 | |
| bogdanm | 0:9b334a45a8ff | 231 | /* Configure the I2C1 clock source */ |
| bogdanm | 0:9b334a45a8ff | 232 | __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 233 | } |
| bogdanm | 0:9b334a45a8ff | 234 | |
| bogdanm | 0:9b334a45a8ff | 235 | #if defined (STM32L071xx) || (STM32L072xx) || defined(STM32L073xx) || \ |
| bogdanm | 0:9b334a45a8ff | 236 | defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 237 | /*------------------------------ I2C3 Configuration ------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 238 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) |
| bogdanm | 0:9b334a45a8ff | 239 | { |
| bogdanm | 0:9b334a45a8ff | 240 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 241 | assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 242 | |
| bogdanm | 0:9b334a45a8ff | 243 | /* Configure the I2C3 clock source */ |
| bogdanm | 0:9b334a45a8ff | 244 | __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); |
| bogdanm | 0:9b334a45a8ff | 245 | } |
| bogdanm | 0:9b334a45a8ff | 246 | #endif /* defined (STM32L071xx) (STM32L072xx)|| (STM32L073xx)|| (STM32L081xx)|| (STM32L082xx) || (STM32L083xx) */ |
| bogdanm | 0:9b334a45a8ff | 247 | |
| bogdanm | 0:9b334a45a8ff | 248 | /*---------------------------- RTC/LCD configuration -------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 249 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) |
| bogdanm | 0:9b334a45a8ff | 250 | #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 251 | || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) |
| bogdanm | 0:9b334a45a8ff | 252 | #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ |
| bogdanm | 0:9b334a45a8ff | 253 | ) |
| bogdanm | 0:9b334a45a8ff | 254 | { |
| bogdanm | 0:9b334a45a8ff | 255 | /* Enable Power Clock*/ |
| bogdanm | 0:9b334a45a8ff | 256 | __HAL_RCC_PWR_CLK_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 257 | |
| bogdanm | 0:9b334a45a8ff | 258 | /* Enable write access to Backup domain */ |
| bogdanm | 0:9b334a45a8ff | 259 | PWR->CR |= PWR_CR_DBP; |
| bogdanm | 0:9b334a45a8ff | 260 | |
| bogdanm | 0:9b334a45a8ff | 261 | /* Wait for Backup domain Write protection disable */ |
| bogdanm | 0:9b334a45a8ff | 262 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 263 | |
| bogdanm | 0:9b334a45a8ff | 264 | while((PWR->CR & PWR_CR_DBP) == RESET) |
| bogdanm | 0:9b334a45a8ff | 265 | { |
| bogdanm | 0:9b334a45a8ff | 266 | if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 267 | { |
| bogdanm | 0:9b334a45a8ff | 268 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 269 | } |
| bogdanm | 0:9b334a45a8ff | 270 | } |
| bogdanm | 0:9b334a45a8ff | 271 | |
| bogdanm | 0:9b334a45a8ff | 272 | /* Reset the Backup domain only if the RTC Clock source selection is modified */ |
| bogdanm | 0:9b334a45a8ff | 273 | if(((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) |
| bogdanm | 0:9b334a45a8ff | 274 | #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 275 | || (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) |
| bogdanm | 0:9b334a45a8ff | 276 | #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ |
| bogdanm | 0:9b334a45a8ff | 277 | ) |
| bogdanm | 0:9b334a45a8ff | 278 | { |
| bogdanm | 0:9b334a45a8ff | 279 | /* Store the content of CSR register before the reset of Backup Domain */ |
| bogdanm | 0:9b334a45a8ff | 280 | tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); |
| bogdanm | 0:9b334a45a8ff | 281 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
| bogdanm | 0:9b334a45a8ff | 282 | __HAL_RCC_BACKUPRESET_FORCE(); |
| bogdanm | 0:9b334a45a8ff | 283 | __HAL_RCC_BACKUPRESET_RELEASE(); |
| bogdanm | 0:9b334a45a8ff | 284 | /* Restore the Content of CSR register */ |
| bogdanm | 0:9b334a45a8ff | 285 | RCC->CSR = tmpreg; |
| bogdanm | 0:9b334a45a8ff | 286 | } |
| bogdanm | 0:9b334a45a8ff | 287 | |
| bogdanm | 0:9b334a45a8ff | 288 | /* If LSE is selected as RTC clock source, wait for LSE reactivation */ |
| bogdanm | 0:9b334a45a8ff | 289 | if((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) |
| bogdanm | 0:9b334a45a8ff | 290 | #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 291 | || (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE) |
| bogdanm | 0:9b334a45a8ff | 292 | #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ |
| bogdanm | 0:9b334a45a8ff | 293 | ) |
| bogdanm | 0:9b334a45a8ff | 294 | { |
| bogdanm | 0:9b334a45a8ff | 295 | /* Get timeout */ |
| bogdanm | 0:9b334a45a8ff | 296 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 297 | |
| bogdanm | 0:9b334a45a8ff | 298 | /* Wait till LSE is ready */ |
| bogdanm | 0:9b334a45a8ff | 299 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
| bogdanm | 0:9b334a45a8ff | 300 | { |
| bogdanm | 0:9b334a45a8ff | 301 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 302 | { |
| bogdanm | 0:9b334a45a8ff | 303 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 304 | } |
| bogdanm | 0:9b334a45a8ff | 305 | } |
| bogdanm | 0:9b334a45a8ff | 306 | } |
| bogdanm | 0:9b334a45a8ff | 307 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
| bogdanm | 0:9b334a45a8ff | 308 | } |
| bogdanm | 0:9b334a45a8ff | 309 | #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) |
| bogdanm | 0:9b334a45a8ff | 310 | /*---------------------------- USB and RNG configuration --------------------*/ |
| bogdanm | 0:9b334a45a8ff | 311 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) |
| bogdanm | 0:9b334a45a8ff | 312 | { |
| bogdanm | 0:9b334a45a8ff | 313 | assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 314 | __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); |
| bogdanm | 0:9b334a45a8ff | 315 | } |
| bogdanm | 0:9b334a45a8ff | 316 | #endif |
| bogdanm | 0:9b334a45a8ff | 317 | |
| bogdanm | 0:9b334a45a8ff | 318 | /*---------------------------- LPTIM1 configuration ------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 319 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) |
| bogdanm | 0:9b334a45a8ff | 320 | { |
| bogdanm | 0:9b334a45a8ff | 321 | assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection)); |
| bogdanm | 0:9b334a45a8ff | 322 | __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection); |
| bogdanm | 0:9b334a45a8ff | 323 | } |
| bogdanm | 0:9b334a45a8ff | 324 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 325 | } |
| bogdanm | 0:9b334a45a8ff | 326 | |
| bogdanm | 0:9b334a45a8ff | 327 | |
| bogdanm | 0:9b334a45a8ff | 328 | |
| bogdanm | 0:9b334a45a8ff | 329 | /** |
| bogdanm | 0:9b334a45a8ff | 330 | * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. |
| bogdanm | 0:9b334a45a8ff | 331 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
| bogdanm | 0:9b334a45a8ff | 332 | * returns the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1, |
| bogdanm | 0:9b334a45a8ff | 333 | * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks). |
| bogdanm | 0:9b334a45a8ff | 334 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 335 | */ |
| bogdanm | 0:9b334a45a8ff | 336 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| bogdanm | 0:9b334a45a8ff | 337 | { |
| bogdanm | 0:9b334a45a8ff | 338 | /* Set all possible values for the extended clock type parameter -----------*/ |
| bogdanm | 0:9b334a45a8ff | 339 | /* Common part first */ |
| bogdanm | 0:9b334a45a8ff | 340 | #if defined(STM32L031xx) || defined(STM32L041xx) |
| bogdanm | 0:9b334a45a8ff | 341 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \ |
| bogdanm | 0:9b334a45a8ff | 342 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1; |
| bogdanm | 0:9b334a45a8ff | 343 | #endif |
| bogdanm | 0:9b334a45a8ff | 344 | #if defined(STM32L052xx) || defined(STM32L062xx) |
| bogdanm | 0:9b334a45a8ff | 345 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 346 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \ |
| bogdanm | 0:9b334a45a8ff | 347 | RCC_PERIPHCLK_LPTIM1 ; |
| bogdanm | 0:9b334a45a8ff | 348 | #endif |
| bogdanm | 0:9b334a45a8ff | 349 | #if defined(STM32L053xx) || defined(STM32L063xx) |
| bogdanm | 0:9b334a45a8ff | 350 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 351 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \ |
| bogdanm | 0:9b334a45a8ff | 352 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD; |
| bogdanm | 0:9b334a45a8ff | 353 | #endif |
| bogdanm | 0:9b334a45a8ff | 354 | #if defined(STM32L072xx) || defined(STM32L082xx) |
| bogdanm | 0:9b334a45a8ff | 355 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 356 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \ |
| bogdanm | 0:9b334a45a8ff | 357 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 ; |
| bogdanm | 0:9b334a45a8ff | 358 | #endif |
| bogdanm | 0:9b334a45a8ff | 359 | #if defined(STM32L073xx) || defined(STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 360 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 361 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \ |
| bogdanm | 0:9b334a45a8ff | 362 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD; |
| bogdanm | 0:9b334a45a8ff | 363 | |
| bogdanm | 0:9b334a45a8ff | 364 | #endif |
| bogdanm | 0:9b334a45a8ff | 365 | #if defined(STM32L051xx) || defined(STM32L061xx) |
| bogdanm | 0:9b334a45a8ff | 366 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 367 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1; |
| bogdanm | 0:9b334a45a8ff | 368 | #endif |
| bogdanm | 0:9b334a45a8ff | 369 | #if defined(STM32L071xx) || defined(STM32L081xx) |
| bogdanm | 0:9b334a45a8ff | 370 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ |
| bogdanm | 0:9b334a45a8ff | 371 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \ |
| bogdanm | 0:9b334a45a8ff | 372 | RCC_PERIPHCLK_LPTIM1; |
| bogdanm | 0:9b334a45a8ff | 373 | #endif |
| bogdanm | 0:9b334a45a8ff | 374 | |
| bogdanm | 0:9b334a45a8ff | 375 | #if !defined (STM32L031xx) && !defined (STM32L041xx) |
| bogdanm | 0:9b334a45a8ff | 376 | /* Get the USART1 configuration --------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 377 | PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 378 | #endif |
| bogdanm | 0:9b334a45a8ff | 379 | /* Get the USART2 clock source ---------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 380 | PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 381 | /* Get the LPUART1 clock source ---------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 382 | PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 383 | /* Get the I2C1 clock source -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 384 | PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 385 | #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || \ |
| bogdanm | 0:9b334a45a8ff | 386 | defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 387 | /* Get the I2C3 clock source -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 388 | PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 389 | #endif /* defined (STM32L071xx) || (STM32L073xx) || (STM32L082xx) || (STM32L082xx) || (STM32L083xx) */ |
| bogdanm | 0:9b334a45a8ff | 390 | /* Get the LPTIM1 clock source -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 391 | PeriphClkInit->LptimClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 392 | /* Get the RTC clock source -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 393 | PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 394 | #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) |
| bogdanm | 0:9b334a45a8ff | 395 | PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection; |
| bogdanm | 0:9b334a45a8ff | 396 | #endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ |
| bogdanm | 0:9b334a45a8ff | 397 | |
| bogdanm | 0:9b334a45a8ff | 398 | #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) |
| bogdanm | 0:9b334a45a8ff | 399 | /* Get the USB/RNG clock source -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 400 | PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); |
| bogdanm | 0:9b334a45a8ff | 401 | #endif |
| bogdanm | 0:9b334a45a8ff | 402 | } |
| bogdanm | 0:9b334a45a8ff | 403 | |
| bogdanm | 0:9b334a45a8ff | 404 | /** |
| bogdanm | 0:9b334a45a8ff | 405 | * @brief Enables the LSE Clock Security System. |
| bogdanm | 0:9b334a45a8ff | 406 | * @param None |
| bogdanm | 0:9b334a45a8ff | 407 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 408 | */ |
| bogdanm | 0:9b334a45a8ff | 409 | void HAL_RCCEx_EnableLSECSS(void) |
| bogdanm | 0:9b334a45a8ff | 410 | { |
| bogdanm | 0:9b334a45a8ff | 411 | SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ; |
| bogdanm | 0:9b334a45a8ff | 412 | } |
| bogdanm | 0:9b334a45a8ff | 413 | |
| bogdanm | 0:9b334a45a8ff | 414 | /** |
| bogdanm | 0:9b334a45a8ff | 415 | * @brief Disables the LSE Clock Security System. |
| bogdanm | 0:9b334a45a8ff | 416 | * @param None |
| bogdanm | 0:9b334a45a8ff | 417 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 418 | */ |
| bogdanm | 0:9b334a45a8ff | 419 | void HAL_RCCEx_DisableLSECSS(void) |
| bogdanm | 0:9b334a45a8ff | 420 | { |
| bogdanm | 0:9b334a45a8ff | 421 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ; |
| bogdanm | 0:9b334a45a8ff | 422 | } |
| bogdanm | 0:9b334a45a8ff | 423 | |
| bogdanm | 0:9b334a45a8ff | 424 | #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) |
| bogdanm | 0:9b334a45a8ff | 425 | |
| bogdanm | 0:9b334a45a8ff | 426 | /** |
| bogdanm | 0:9b334a45a8ff | 427 | * @brief Start automatic synchronization using polling mode |
| bogdanm | 0:9b334a45a8ff | 428 | * @param pInit Pointer on RCC_CRSInitTypeDef structure |
| bogdanm | 0:9b334a45a8ff | 429 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 430 | */ |
| bogdanm | 0:9b334a45a8ff | 431 | void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) |
| bogdanm | 0:9b334a45a8ff | 432 | { |
| bogdanm | 0:9b334a45a8ff | 433 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 434 | assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); |
| bogdanm | 0:9b334a45a8ff | 435 | assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); |
| bogdanm | 0:9b334a45a8ff | 436 | assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); |
| bogdanm | 0:9b334a45a8ff | 437 | assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); |
| bogdanm | 0:9b334a45a8ff | 438 | assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); |
| bogdanm | 0:9b334a45a8ff | 439 | assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); |
| bogdanm | 0:9b334a45a8ff | 440 | |
| bogdanm | 0:9b334a45a8ff | 441 | |
| bogdanm | 0:9b334a45a8ff | 442 | /* CONFIGURATION */ |
| bogdanm | 0:9b334a45a8ff | 443 | |
| bogdanm | 0:9b334a45a8ff | 444 | /* Before configuration, reset CRS registers to their default values*/ |
| bogdanm | 0:9b334a45a8ff | 445 | __HAL_RCC_CRS_FORCE_RESET(); |
| bogdanm | 0:9b334a45a8ff | 446 | __HAL_RCC_CRS_RELEASE_RESET(); |
| bogdanm | 0:9b334a45a8ff | 447 | |
| bogdanm | 0:9b334a45a8ff | 448 | /* Configure Synchronization input */ |
| bogdanm | 0:9b334a45a8ff | 449 | /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */ |
| bogdanm | 0:9b334a45a8ff | 450 | CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL); |
| bogdanm | 0:9b334a45a8ff | 451 | |
| bogdanm | 0:9b334a45a8ff | 452 | /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */ |
| bogdanm | 0:9b334a45a8ff | 453 | CRS->CFGR |= pInit->Prescaler; |
| bogdanm | 0:9b334a45a8ff | 454 | |
| bogdanm | 0:9b334a45a8ff | 455 | /* Set the SYNCSRC[1:0] bits according to Source value */ |
| bogdanm | 0:9b334a45a8ff | 456 | CRS->CFGR |= pInit->Source; |
| bogdanm | 0:9b334a45a8ff | 457 | |
| bogdanm | 0:9b334a45a8ff | 458 | /* Set the SYNCSPOL bits according to Polarity value */ |
| bogdanm | 0:9b334a45a8ff | 459 | CRS->CFGR |= pInit->Polarity; |
| bogdanm | 0:9b334a45a8ff | 460 | |
| bogdanm | 0:9b334a45a8ff | 461 | /* Configure Frequency Error Measurement */ |
| bogdanm | 0:9b334a45a8ff | 462 | /* Clear RELOAD[15:0] & FELIM[7:0] bits*/ |
| bogdanm | 0:9b334a45a8ff | 463 | CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM); |
| bogdanm | 0:9b334a45a8ff | 464 | |
| bogdanm | 0:9b334a45a8ff | 465 | /* Set the RELOAD[15:0] bits according to ReloadValue value */ |
| bogdanm | 0:9b334a45a8ff | 466 | CRS->CFGR |= pInit->ReloadValue; |
| bogdanm | 0:9b334a45a8ff | 467 | |
| bogdanm | 0:9b334a45a8ff | 468 | /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ |
| bogdanm | 0:9b334a45a8ff | 469 | CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); |
| bogdanm | 0:9b334a45a8ff | 470 | |
| bogdanm | 0:9b334a45a8ff | 471 | /* Adjust HSI48 oscillator smooth trimming */ |
| bogdanm | 0:9b334a45a8ff | 472 | /* Clear TRIM[5:0] bits */ |
| bogdanm | 0:9b334a45a8ff | 473 | CRS->CR &= ~CRS_CR_TRIM; |
| bogdanm | 0:9b334a45a8ff | 474 | |
| bogdanm | 0:9b334a45a8ff | 475 | /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ |
| bogdanm | 0:9b334a45a8ff | 476 | CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER); |
| bogdanm | 0:9b334a45a8ff | 477 | |
| bogdanm | 0:9b334a45a8ff | 478 | |
| bogdanm | 0:9b334a45a8ff | 479 | /* START AUTOMATIC SYNCHRONIZATION*/ |
| bogdanm | 0:9b334a45a8ff | 480 | |
| bogdanm | 0:9b334a45a8ff | 481 | /* Enable Automatic trimming */ |
| bogdanm | 0:9b334a45a8ff | 482 | __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB(); |
| bogdanm | 0:9b334a45a8ff | 483 | |
| bogdanm | 0:9b334a45a8ff | 484 | /* Enable Frequency error counter */ |
| bogdanm | 0:9b334a45a8ff | 485 | __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER(); |
| bogdanm | 0:9b334a45a8ff | 486 | |
| bogdanm | 0:9b334a45a8ff | 487 | } |
| bogdanm | 0:9b334a45a8ff | 488 | |
| bogdanm | 0:9b334a45a8ff | 489 | /** |
| bogdanm | 0:9b334a45a8ff | 490 | * @brief Generate the software synchronization event |
| bogdanm | 0:9b334a45a8ff | 491 | * @param None |
| bogdanm | 0:9b334a45a8ff | 492 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 493 | */ |
| bogdanm | 0:9b334a45a8ff | 494 | void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) |
| bogdanm | 0:9b334a45a8ff | 495 | { |
| bogdanm | 0:9b334a45a8ff | 496 | CRS->CR |= CRS_CR_SWSYNC; |
| bogdanm | 0:9b334a45a8ff | 497 | } |
| bogdanm | 0:9b334a45a8ff | 498 | |
| bogdanm | 0:9b334a45a8ff | 499 | |
| bogdanm | 0:9b334a45a8ff | 500 | /** |
| bogdanm | 0:9b334a45a8ff | 501 | * @brief Function to return synchronization info |
| bogdanm | 0:9b334a45a8ff | 502 | * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure |
| bogdanm | 0:9b334a45a8ff | 503 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 504 | */ |
| bogdanm | 0:9b334a45a8ff | 505 | void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) |
| bogdanm | 0:9b334a45a8ff | 506 | { |
| bogdanm | 0:9b334a45a8ff | 507 | /* Check the parameter */ |
| bogdanm | 0:9b334a45a8ff | 508 | assert_param(pSynchroInfo != NULL); |
| bogdanm | 0:9b334a45a8ff | 509 | |
| bogdanm | 0:9b334a45a8ff | 510 | /* Get the reload value */ |
| bogdanm | 0:9b334a45a8ff | 511 | pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD); |
| bogdanm | 0:9b334a45a8ff | 512 | |
| bogdanm | 0:9b334a45a8ff | 513 | /* Get HSI48 oscillator smooth trimming */ |
| bogdanm | 0:9b334a45a8ff | 514 | pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); |
| bogdanm | 0:9b334a45a8ff | 515 | |
| bogdanm | 0:9b334a45a8ff | 516 | /* Get Frequency error capture */ |
| bogdanm | 0:9b334a45a8ff | 517 | pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); |
| bogdanm | 0:9b334a45a8ff | 518 | |
| bogdanm | 0:9b334a45a8ff | 519 | /* Get Frequency error direction */ |
| bogdanm | 0:9b334a45a8ff | 520 | pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR); |
| bogdanm | 0:9b334a45a8ff | 521 | |
| bogdanm | 0:9b334a45a8ff | 522 | |
| bogdanm | 0:9b334a45a8ff | 523 | } |
| bogdanm | 0:9b334a45a8ff | 524 | |
| bogdanm | 0:9b334a45a8ff | 525 | /** |
| bogdanm | 0:9b334a45a8ff | 526 | * @brief This function handles CRS Synchronization Timeout. |
| bogdanm | 0:9b334a45a8ff | 527 | * @param Timeout: Duration of the timeout |
| bogdanm | 0:9b334a45a8ff | 528 | * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization |
| bogdanm | 0:9b334a45a8ff | 529 | * frequency. |
| bogdanm | 0:9b334a45a8ff | 530 | * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. |
| bogdanm | 0:9b334a45a8ff | 531 | * @retval Combination of Synchronization status |
| bogdanm | 0:9b334a45a8ff | 532 | * This parameter can be a combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 533 | * @arg RCC_CRS_TIMEOUT |
| bogdanm | 0:9b334a45a8ff | 534 | * @arg RCC_CRS_SYNCOK |
| bogdanm | 0:9b334a45a8ff | 535 | * @arg RCC_CRS_SYNCWARM |
| bogdanm | 0:9b334a45a8ff | 536 | * @arg RCC_CRS_SYNCERR |
| bogdanm | 0:9b334a45a8ff | 537 | * @arg RCC_CRS_SYNCMISS |
| bogdanm | 0:9b334a45a8ff | 538 | * @arg RCC_CRS_TRIMOV |
| bogdanm | 0:9b334a45a8ff | 539 | */ |
| bogdanm | 0:9b334a45a8ff | 540 | uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) |
| bogdanm | 0:9b334a45a8ff | 541 | { |
| bogdanm | 0:9b334a45a8ff | 542 | uint32_t crsstatus = RCC_CRS_NONE; |
| bogdanm | 0:9b334a45a8ff | 543 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 544 | |
| bogdanm | 0:9b334a45a8ff | 545 | /* Get timeout */ |
| bogdanm | 0:9b334a45a8ff | 546 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 547 | |
| bogdanm | 0:9b334a45a8ff | 548 | /* Check that if one of CRS flags have been set */ |
| bogdanm | 0:9b334a45a8ff | 549 | while(RCC_CRS_NONE == crsstatus) |
| bogdanm | 0:9b334a45a8ff | 550 | { |
| bogdanm | 0:9b334a45a8ff | 551 | if(Timeout != HAL_MAX_DELAY) |
| bogdanm | 0:9b334a45a8ff | 552 | { |
| bogdanm | 0:9b334a45a8ff | 553 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| bogdanm | 0:9b334a45a8ff | 554 | { |
| bogdanm | 0:9b334a45a8ff | 555 | crsstatus = RCC_CRS_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 556 | } |
| bogdanm | 0:9b334a45a8ff | 557 | } |
| bogdanm | 0:9b334a45a8ff | 558 | /* Check CRS SYNCOK flag */ |
| bogdanm | 0:9b334a45a8ff | 559 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) |
| bogdanm | 0:9b334a45a8ff | 560 | { |
| bogdanm | 0:9b334a45a8ff | 561 | /* CRS SYNC event OK */ |
| bogdanm | 0:9b334a45a8ff | 562 | crsstatus |= RCC_CRS_SYNCOK; |
| bogdanm | 0:9b334a45a8ff | 563 | |
| bogdanm | 0:9b334a45a8ff | 564 | /* Clear CRS SYNC event OK bit */ |
| bogdanm | 0:9b334a45a8ff | 565 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); |
| bogdanm | 0:9b334a45a8ff | 566 | } |
| bogdanm | 0:9b334a45a8ff | 567 | |
| bogdanm | 0:9b334a45a8ff | 568 | /* Check CRS SYNCWARN flag */ |
| bogdanm | 0:9b334a45a8ff | 569 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) |
| bogdanm | 0:9b334a45a8ff | 570 | { |
| bogdanm | 0:9b334a45a8ff | 571 | /* CRS SYNC warning */ |
| bogdanm | 0:9b334a45a8ff | 572 | crsstatus |= RCC_CRS_SYNCWARM; |
| bogdanm | 0:9b334a45a8ff | 573 | |
| bogdanm | 0:9b334a45a8ff | 574 | /* Clear CRS SYNCWARN bit */ |
| bogdanm | 0:9b334a45a8ff | 575 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); |
| bogdanm | 0:9b334a45a8ff | 576 | } |
| bogdanm | 0:9b334a45a8ff | 577 | |
| bogdanm | 0:9b334a45a8ff | 578 | /* Check CRS TRIM overflow flag */ |
| bogdanm | 0:9b334a45a8ff | 579 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) |
| bogdanm | 0:9b334a45a8ff | 580 | { |
| bogdanm | 0:9b334a45a8ff | 581 | /* CRS SYNC Error */ |
| bogdanm | 0:9b334a45a8ff | 582 | crsstatus |= RCC_CRS_TRIMOV; |
| bogdanm | 0:9b334a45a8ff | 583 | |
| bogdanm | 0:9b334a45a8ff | 584 | /* Clear CRS Error bit */ |
| bogdanm | 0:9b334a45a8ff | 585 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); |
| bogdanm | 0:9b334a45a8ff | 586 | } |
| bogdanm | 0:9b334a45a8ff | 587 | |
| bogdanm | 0:9b334a45a8ff | 588 | /* Check CRS Error flag */ |
| bogdanm | 0:9b334a45a8ff | 589 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) |
| bogdanm | 0:9b334a45a8ff | 590 | { |
| bogdanm | 0:9b334a45a8ff | 591 | /* CRS SYNC Error */ |
| bogdanm | 0:9b334a45a8ff | 592 | crsstatus |= RCC_CRS_SYNCERR; |
| bogdanm | 0:9b334a45a8ff | 593 | |
| bogdanm | 0:9b334a45a8ff | 594 | /* Clear CRS Error bit */ |
| bogdanm | 0:9b334a45a8ff | 595 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); |
| bogdanm | 0:9b334a45a8ff | 596 | } |
| bogdanm | 0:9b334a45a8ff | 597 | |
| bogdanm | 0:9b334a45a8ff | 598 | /* Check CRS SYNC Missed flag */ |
| bogdanm | 0:9b334a45a8ff | 599 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) |
| bogdanm | 0:9b334a45a8ff | 600 | { |
| bogdanm | 0:9b334a45a8ff | 601 | /* CRS SYNC Missed */ |
| bogdanm | 0:9b334a45a8ff | 602 | crsstatus |= RCC_CRS_SYNCMISS; |
| bogdanm | 0:9b334a45a8ff | 603 | |
| bogdanm | 0:9b334a45a8ff | 604 | /* Clear CRS SYNC Missed bit */ |
| bogdanm | 0:9b334a45a8ff | 605 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); |
| bogdanm | 0:9b334a45a8ff | 606 | } |
| bogdanm | 0:9b334a45a8ff | 607 | |
| bogdanm | 0:9b334a45a8ff | 608 | /* Check CRS Expected SYNC flag */ |
| bogdanm | 0:9b334a45a8ff | 609 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) |
| bogdanm | 0:9b334a45a8ff | 610 | { |
| bogdanm | 0:9b334a45a8ff | 611 | /* frequency error counter reached a zero value */ |
| bogdanm | 0:9b334a45a8ff | 612 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); |
| bogdanm | 0:9b334a45a8ff | 613 | } |
| bogdanm | 0:9b334a45a8ff | 614 | } |
| bogdanm | 0:9b334a45a8ff | 615 | |
| bogdanm | 0:9b334a45a8ff | 616 | return crsstatus; |
| bogdanm | 0:9b334a45a8ff | 617 | } |
| bogdanm | 0:9b334a45a8ff | 618 | /** |
| bogdanm | 0:9b334a45a8ff | 619 | * @brief Enables Vrefint for the HSI48. |
| bogdanm | 0:9b334a45a8ff | 620 | * @param None |
| bogdanm | 0:9b334a45a8ff | 621 | * @note This is functional only if the LOCK is not set |
| bogdanm | 0:9b334a45a8ff | 622 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 623 | */ |
| bogdanm | 0:9b334a45a8ff | 624 | void HAL_RCCEx_EnableHSI48_VREFINT(void) |
| bogdanm | 0:9b334a45a8ff | 625 | { |
| bogdanm | 0:9b334a45a8ff | 626 | /* Enable the Buffer for the ADC by setting EN_VREFINT bit */ |
| bogdanm | 0:9b334a45a8ff | 627 | /* and the SYSCFG_CFGR3_ENREF_HSI48 in the CFGR3 register */ |
| bogdanm | 0:9b334a45a8ff | 628 | SET_BIT (SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); |
| bogdanm | 0:9b334a45a8ff | 629 | } |
| bogdanm | 0:9b334a45a8ff | 630 | |
| bogdanm | 0:9b334a45a8ff | 631 | /** |
| bogdanm | 0:9b334a45a8ff | 632 | * @brief Disables the Vrefint for the HSI48. |
| bogdanm | 0:9b334a45a8ff | 633 | * @param None. |
| bogdanm | 0:9b334a45a8ff | 634 | * @note This is functional only if the LOCK is not set |
| bogdanm | 0:9b334a45a8ff | 635 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 636 | */ |
| bogdanm | 0:9b334a45a8ff | 637 | void HAL_RCCEx_DisableHSI48_VREFINT(void) |
| bogdanm | 0:9b334a45a8ff | 638 | { |
| bogdanm | 0:9b334a45a8ff | 639 | /* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit */ |
| bogdanm | 0:9b334a45a8ff | 640 | /* and the EN_VREFINT bit in the CFGR3 register */ |
| bogdanm | 0:9b334a45a8ff | 641 | CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); |
| bogdanm | 0:9b334a45a8ff | 642 | } |
| bogdanm | 0:9b334a45a8ff | 643 | #endif /* !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */ |
| bogdanm | 0:9b334a45a8ff | 644 | |
| bogdanm | 0:9b334a45a8ff | 645 | |
| bogdanm | 0:9b334a45a8ff | 646 | /** |
| bogdanm | 0:9b334a45a8ff | 647 | * @} |
| bogdanm | 0:9b334a45a8ff | 648 | */ |
| bogdanm | 0:9b334a45a8ff | 649 | |
| bogdanm | 0:9b334a45a8ff | 650 | /** |
| bogdanm | 0:9b334a45a8ff | 651 | * @} |
| bogdanm | 0:9b334a45a8ff | 652 | */ |
| bogdanm | 0:9b334a45a8ff | 653 | |
| bogdanm | 0:9b334a45a8ff | 654 | #endif /* HAL_RCC_MODULE_ENABLED */ |
| bogdanm | 0:9b334a45a8ff | 655 | /** |
| bogdanm | 0:9b334a45a8ff | 656 | * @} |
| bogdanm | 0:9b334a45a8ff | 657 | */ |
| bogdanm | 0:9b334a45a8ff | 658 | |
| bogdanm | 0:9b334a45a8ff | 659 | /** |
| bogdanm | 0:9b334a45a8ff | 660 | * @} |
| bogdanm | 0:9b334a45a8ff | 661 | */ |
| bogdanm | 0:9b334a45a8ff | 662 | |
| bogdanm | 0:9b334a45a8ff | 663 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| bogdanm | 0:9b334a45a8ff | 664 |