mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 83:a036322b8637

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f7xx_hal_tim.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	83:a036322b8637	5	* @version V1.0.4
mbed_official	83:a036322b8637	6	* @date 09-December-2015
bogdanm	0:9b334a45a8ff	7	* @brief TIM HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Timer (TIM) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Time Base Initialization
bogdanm	0:9b334a45a8ff	11	* + Time Base Start
bogdanm	0:9b334a45a8ff	12	* + Time Base Start Interruption
bogdanm	0:9b334a45a8ff	13	* + Time Base Start DMA
bogdanm	0:9b334a45a8ff	14	* + Time Output Compare/PWM Initialization
bogdanm	0:9b334a45a8ff	15	* + Time Output Compare/PWM Channel Configuration
bogdanm	0:9b334a45a8ff	16	* + Time Output Compare/PWM Start
bogdanm	0:9b334a45a8ff	17	* + Time Output Compare/PWM Start Interruption
bogdanm	0:9b334a45a8ff	18	* + Time Output Compare/PWM Start DMA
bogdanm	0:9b334a45a8ff	19	* + Time Input Capture Initialization
bogdanm	0:9b334a45a8ff	20	* + Time Input Capture Channel Configuration
bogdanm	0:9b334a45a8ff	21	* + Time Input Capture Start
bogdanm	0:9b334a45a8ff	22	* + Time Input Capture Start Interruption
bogdanm	0:9b334a45a8ff	23	* + Time Input Capture Start DMA
bogdanm	0:9b334a45a8ff	24	* + Time One Pulse Initialization
bogdanm	0:9b334a45a8ff	25	* + Time One Pulse Channel Configuration
bogdanm	0:9b334a45a8ff	26	* + Time One Pulse Start
bogdanm	0:9b334a45a8ff	27	* + Time Encoder Interface Initialization
bogdanm	0:9b334a45a8ff	28	* + Time Encoder Interface Start
bogdanm	0:9b334a45a8ff	29	* + Time Encoder Interface Start Interruption
bogdanm	0:9b334a45a8ff	30	* + Time Encoder Interface Start DMA
bogdanm	0:9b334a45a8ff	31	* + Commutation Event configuration with Interruption and DMA
bogdanm	0:9b334a45a8ff	32	* + Time OCRef clear configuration
bogdanm	0:9b334a45a8ff	33	* + Time External Clock configuration
bogdanm	0:9b334a45a8ff	34	@verbatim
bogdanm	0:9b334a45a8ff	35	==============================================================================
bogdanm	0:9b334a45a8ff	36	##### TIMER Generic features #####
bogdanm	0:9b334a45a8ff	37	==============================================================================
bogdanm	0:9b334a45a8ff	38	[..] The Timer features include:
bogdanm	0:9b334a45a8ff	39	(#) 16-bit up, down, up/down auto-reload counter.
bogdanm	0:9b334a45a8ff	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
bogdanm	0:9b334a45a8ff	41	counter clock frequency either by any factor between 1 and 65536.
bogdanm	0:9b334a45a8ff	42	(#) Up to 4 independent channels for:
bogdanm	0:9b334a45a8ff	43	(++) Input Capture
bogdanm	0:9b334a45a8ff	44	(++) Output Compare
bogdanm	0:9b334a45a8ff	45	(++) PWM generation (Edge and Center-aligned Mode)
bogdanm	0:9b334a45a8ff	46	(++) One-pulse mode output
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	49	==============================================================================
bogdanm	0:9b334a45a8ff	50	[..]
bogdanm	0:9b334a45a8ff	51	(#) Initialize the TIM low level resources by implementing the following functions
bogdanm	0:9b334a45a8ff	52	depending from feature used :
bogdanm	0:9b334a45a8ff	53	(++) Time Base : HAL_TIM_Base_MspInit()
bogdanm	0:9b334a45a8ff	54	(++) Input Capture : HAL_TIM_IC_MspInit()
bogdanm	0:9b334a45a8ff	55	(++) Output Compare : HAL_TIM_OC_MspInit()
bogdanm	0:9b334a45a8ff	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
bogdanm	0:9b334a45a8ff	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
bogdanm	0:9b334a45a8ff	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	(#) Initialize the TIM low level resources :
bogdanm	0:9b334a45a8ff	61	(##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	62	(##) TIM pins configuration
bogdanm	0:9b334a45a8ff	63	(+++) Enable the clock for the TIM GPIOs using the following function:
bogdanm	0:9b334a45a8ff	64	__GPIOx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	(#) The external Clock can be configured, if needed (the default clock is the
bogdanm	0:9b334a45a8ff	68	internal clock from the APBx), using the following function:
bogdanm	0:9b334a45a8ff	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
bogdanm	0:9b334a45a8ff	70	any start function.
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	(#) Configure the TIM in the desired functioning mode using one of the
bogdanm	0:9b334a45a8ff	73	initialization function of this driver:
bogdanm	0:9b334a45a8ff	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
bogdanm	0:9b334a45a8ff	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
bogdanm	0:9b334a45a8ff	76	Output Compare signal.
bogdanm	0:9b334a45a8ff	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
bogdanm	0:9b334a45a8ff	78	PWM signal.
bogdanm	0:9b334a45a8ff	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
bogdanm	0:9b334a45a8ff	80	external signal.
bogdanm	0:9b334a45a8ff	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
bogdanm	0:9b334a45a8ff	82	in One Pulse Mode.
bogdanm	0:9b334a45a8ff	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
bogdanm	0:9b334a45a8ff	84
bogdanm	0:9b334a45a8ff	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
bogdanm	0:9b334a45a8ff	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
bogdanm	0:9b334a45a8ff	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
bogdanm	0:9b334a45a8ff	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
bogdanm	0:9b334a45a8ff	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
bogdanm	0:9b334a45a8ff	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
bogdanm	0:9b334a45a8ff	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	(#) The DMA Burst is managed with the two following functions:
bogdanm	0:9b334a45a8ff	94	HAL_TIM_DMABurst_WriteStart()
bogdanm	0:9b334a45a8ff	95	HAL_TIM_DMABurst_ReadStart()
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97	@endverbatim
bogdanm	0:9b334a45a8ff	98	******************************************************************************
bogdanm	0:9b334a45a8ff	99	* @attention
bogdanm	0:9b334a45a8ff	100	*
bogdanm	0:9b334a45a8ff	101	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	102	*
bogdanm	0:9b334a45a8ff	103	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	104	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	105	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	106	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	108	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	109	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	111	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	112	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	113	*
bogdanm	0:9b334a45a8ff	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	124	*
bogdanm	0:9b334a45a8ff	125	******************************************************************************
bogdanm	0:9b334a45a8ff	126	*/
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	129	#include "stm32f7xx_hal.h"
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	/** @addtogroup STM32F7xx_HAL_Driver
bogdanm	0:9b334a45a8ff	132	* @{
bogdanm	0:9b334a45a8ff	133	*/
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	/** @defgroup TIM TIM
bogdanm	0:9b334a45a8ff	136	* @brief TIM HAL module driver
bogdanm	0:9b334a45a8ff	137	* @{
bogdanm	0:9b334a45a8ff	138	*/
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	#ifdef HAL_TIM_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	143	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	144	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	145	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	146	/** @addtogroup TIM_Private_Functions
bogdanm	0:9b334a45a8ff	147	* @{
bogdanm	0:9b334a45a8ff	148	*/
bogdanm	0:9b334a45a8ff	149	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	150	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	151	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	152	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	153	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	154	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	155	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	156	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	157	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
bogdanm	0:9b334a45a8ff	160	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	161	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	162	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	163	TIM_SlaveConfigTypeDef * sSlaveConfig);
bogdanm	0:9b334a45a8ff	164	/**
bogdanm	0:9b334a45a8ff	165	* @}
bogdanm	0:9b334a45a8ff	166	*/
bogdanm	0:9b334a45a8ff	167
bogdanm	0:9b334a45a8ff	168	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	169	/** @defgroup TIM_Exported_Functions TIM Exported Functions
bogdanm	0:9b334a45a8ff	170	* @{
bogdanm	0:9b334a45a8ff	171	*/
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
bogdanm	0:9b334a45a8ff	174	* @brief Time Base functions
bogdanm	0:9b334a45a8ff	175	*
bogdanm	0:9b334a45a8ff	176	@verbatim
bogdanm	0:9b334a45a8ff	177	==============================================================================
bogdanm	0:9b334a45a8ff	178	##### Time Base functions #####
bogdanm	0:9b334a45a8ff	179	==============================================================================
bogdanm	0:9b334a45a8ff	180	[..]
bogdanm	0:9b334a45a8ff	181	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	182	(+) Initialize and configure the TIM base.
bogdanm	0:9b334a45a8ff	183	(+) De-initialize the TIM base.
bogdanm	0:9b334a45a8ff	184	(+) Start the Time Base.
bogdanm	0:9b334a45a8ff	185	(+) Stop the Time Base.
bogdanm	0:9b334a45a8ff	186	(+) Start the Time Base and enable interrupt.
bogdanm	0:9b334a45a8ff	187	(+) Stop the Time Base and disable interrupt.
bogdanm	0:9b334a45a8ff	188	(+) Start the Time Base and enable DMA transfer.
bogdanm	0:9b334a45a8ff	189	(+) Stop the Time Base and disable DMA transfer.
bogdanm	0:9b334a45a8ff	190
bogdanm	0:9b334a45a8ff	191	@endverbatim
bogdanm	0:9b334a45a8ff	192	* @{
bogdanm	0:9b334a45a8ff	193	*/
bogdanm	0:9b334a45a8ff	194	/**
bogdanm	0:9b334a45a8ff	195	* @brief Initializes the TIM Time base Unit according to the specified
bogdanm	0:9b334a45a8ff	196	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	197	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	198	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	199	* @retval HAL status
bogdanm	0:9b334a45a8ff	200	*/
bogdanm	0:9b334a45a8ff	201	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	202	{
bogdanm	0:9b334a45a8ff	203	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	204	if(htim == NULL)
bogdanm	0:9b334a45a8ff	205	{
bogdanm	0:9b334a45a8ff	206	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	207	}
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	/* Check the parameters */
bogdanm	0:9b334a45a8ff	210	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	211	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	212	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	215	{
bogdanm	0:9b334a45a8ff	216	/* Init the low level hardware : GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	217	HAL_TIM_Base_MspInit(htim);
bogdanm	0:9b334a45a8ff	218	}
bogdanm	0:9b334a45a8ff	219
bogdanm	0:9b334a45a8ff	220	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	221	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	/* Set the Time Base configuration */
bogdanm	0:9b334a45a8ff	224	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	227	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	return HAL_OK;
bogdanm	0:9b334a45a8ff	230	}
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	/**
bogdanm	0:9b334a45a8ff	233	* @brief DeInitializes the TIM Base peripheral
bogdanm	0:9b334a45a8ff	234	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	235	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	236	* @retval HAL status
bogdanm	0:9b334a45a8ff	237	*/
bogdanm	0:9b334a45a8ff	238	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	239	{
bogdanm	0:9b334a45a8ff	240	/* Check the parameters */
bogdanm	0:9b334a45a8ff	241	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	246	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	249	HAL_TIM_Base_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	250
bogdanm	0:9b334a45a8ff	251	/* Change TIM state */
bogdanm	0:9b334a45a8ff	252	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	253
bogdanm	0:9b334a45a8ff	254	/* Release Lock */
bogdanm	0:9b334a45a8ff	255	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	256
bogdanm	0:9b334a45a8ff	257	return HAL_OK;
bogdanm	0:9b334a45a8ff	258	}
bogdanm	0:9b334a45a8ff	259
bogdanm	0:9b334a45a8ff	260	/**
bogdanm	0:9b334a45a8ff	261	* @brief Initializes the TIM Base MSP.
bogdanm	0:9b334a45a8ff	262	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	263	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	264	* @retval None
bogdanm	0:9b334a45a8ff	265	*/
bogdanm	0:9b334a45a8ff	266	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	267	{
mbed_official	83:a036322b8637	268	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	269	UNUSED(htim);
mbed_official	83:a036322b8637	270
bogdanm	0:9b334a45a8ff	271	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	272	the HAL_TIM_Base_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	273	*/
bogdanm	0:9b334a45a8ff	274	}
bogdanm	0:9b334a45a8ff	275
bogdanm	0:9b334a45a8ff	276	/**
bogdanm	0:9b334a45a8ff	277	* @brief DeInitializes TIM Base MSP.
bogdanm	0:9b334a45a8ff	278	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	279	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	280	* @retval None
bogdanm	0:9b334a45a8ff	281	*/
bogdanm	0:9b334a45a8ff	282	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	283	{
mbed_official	83:a036322b8637	284	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	285	UNUSED(htim);
mbed_official	83:a036322b8637	286
bogdanm	0:9b334a45a8ff	287	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	288	the HAL_TIM_Base_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	289	*/
bogdanm	0:9b334a45a8ff	290	}
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/**
bogdanm	0:9b334a45a8ff	293	* @brief Starts the TIM Base generation.
bogdanm	0:9b334a45a8ff	294	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	295	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	296	* @retval HAL status
bogdanm	0:9b334a45a8ff	297	*/
bogdanm	0:9b334a45a8ff	298	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	299	{
bogdanm	0:9b334a45a8ff	300	/* Check the parameters */
bogdanm	0:9b334a45a8ff	301	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	304	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	307	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	310	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	/* Return function status */
bogdanm	0:9b334a45a8ff	313	return HAL_OK;
bogdanm	0:9b334a45a8ff	314	}
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	/**
bogdanm	0:9b334a45a8ff	317	* @brief Stops the TIM Base generation.
bogdanm	0:9b334a45a8ff	318	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	319	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	320	* @retval HAL status
bogdanm	0:9b334a45a8ff	321	*/
bogdanm	0:9b334a45a8ff	322	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	323	{
bogdanm	0:9b334a45a8ff	324	/* Check the parameters */
bogdanm	0:9b334a45a8ff	325	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	328	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	331	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	334	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	/* Return function status */
bogdanm	0:9b334a45a8ff	337	return HAL_OK;
bogdanm	0:9b334a45a8ff	338	}
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/**
bogdanm	0:9b334a45a8ff	341	* @brief Starts the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	342	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	343	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	344	* @retval HAL status
bogdanm	0:9b334a45a8ff	345	*/
bogdanm	0:9b334a45a8ff	346	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	347	{
bogdanm	0:9b334a45a8ff	348	/* Check the parameters */
bogdanm	0:9b334a45a8ff	349	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	/* Enable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	352	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	353
bogdanm	0:9b334a45a8ff	354	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	355	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	/* Return function status */
bogdanm	0:9b334a45a8ff	358	return HAL_OK;
bogdanm	0:9b334a45a8ff	359	}
bogdanm	0:9b334a45a8ff	360
bogdanm	0:9b334a45a8ff	361	/**
bogdanm	0:9b334a45a8ff	362	* @brief Stops the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	363	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	364	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	365	* @retval HAL status
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	368	{
bogdanm	0:9b334a45a8ff	369	/* Check the parameters */
bogdanm	0:9b334a45a8ff	370	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	371	/* Disable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	372	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	375	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	376
bogdanm	0:9b334a45a8ff	377	/* Return function status */
bogdanm	0:9b334a45a8ff	378	return HAL_OK;
bogdanm	0:9b334a45a8ff	379	}
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	/**
bogdanm	0:9b334a45a8ff	382	* @brief Starts the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	383	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	384	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	385	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	386	* @param Length: The length of data to be transferred from memory to peripheral.
bogdanm	0:9b334a45a8ff	387	* @retval HAL status
bogdanm	0:9b334a45a8ff	388	*/
bogdanm	0:9b334a45a8ff	389	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	390	{
bogdanm	0:9b334a45a8ff	391	/* Check the parameters */
bogdanm	0:9b334a45a8ff	392	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	395	{
bogdanm	0:9b334a45a8ff	396	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	397	}
bogdanm	0:9b334a45a8ff	398	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	399	{
bogdanm	0:9b334a45a8ff	400	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	401	{
bogdanm	0:9b334a45a8ff	402	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	403	}
bogdanm	0:9b334a45a8ff	404	else
bogdanm	0:9b334a45a8ff	405	{
bogdanm	0:9b334a45a8ff	406	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	407	}
bogdanm	0:9b334a45a8ff	408	}
bogdanm	0:9b334a45a8ff	409	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	410	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	413	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	416	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	/* Enable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	419	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	422	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	/* Return function status */
bogdanm	0:9b334a45a8ff	425	return HAL_OK;
bogdanm	0:9b334a45a8ff	426	}
bogdanm	0:9b334a45a8ff	427
bogdanm	0:9b334a45a8ff	428	/**
bogdanm	0:9b334a45a8ff	429	* @brief Stops the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	430	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	431	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	432	* @retval HAL status
bogdanm	0:9b334a45a8ff	433	*/
bogdanm	0:9b334a45a8ff	434	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	435	{
bogdanm	0:9b334a45a8ff	436	/* Check the parameters */
bogdanm	0:9b334a45a8ff	437	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	440	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	441
bogdanm	0:9b334a45a8ff	442	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	443	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	/* Change the htim state */
bogdanm	0:9b334a45a8ff	446	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	/* Return function status */
bogdanm	0:9b334a45a8ff	449	return HAL_OK;
bogdanm	0:9b334a45a8ff	450	}
bogdanm	0:9b334a45a8ff	451
bogdanm	0:9b334a45a8ff	452	/**
bogdanm	0:9b334a45a8ff	453	* @}
bogdanm	0:9b334a45a8ff	454	*/
bogdanm	0:9b334a45a8ff	455
bogdanm	0:9b334a45a8ff	456	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
bogdanm	0:9b334a45a8ff	457	* @brief Time Output Compare functions
bogdanm	0:9b334a45a8ff	458	*
bogdanm	0:9b334a45a8ff	459	@verbatim
bogdanm	0:9b334a45a8ff	460	==============================================================================
bogdanm	0:9b334a45a8ff	461	##### Time Output Compare functions #####
bogdanm	0:9b334a45a8ff	462	==============================================================================
bogdanm	0:9b334a45a8ff	463	[..]
bogdanm	0:9b334a45a8ff	464	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	465	(+) Initialize and configure the TIM Output Compare.
bogdanm	0:9b334a45a8ff	466	(+) De-initialize the TIM Output Compare.
bogdanm	0:9b334a45a8ff	467	(+) Start the Time Output Compare.
bogdanm	0:9b334a45a8ff	468	(+) Stop the Time Output Compare.
bogdanm	0:9b334a45a8ff	469	(+) Start the Time Output Compare and enable interrupt.
bogdanm	0:9b334a45a8ff	470	(+) Stop the Time Output Compare and disable interrupt.
bogdanm	0:9b334a45a8ff	471	(+) Start the Time Output Compare and enable DMA transfer.
bogdanm	0:9b334a45a8ff	472	(+) Stop the Time Output Compare and disable DMA transfer.
bogdanm	0:9b334a45a8ff	473
bogdanm	0:9b334a45a8ff	474	@endverbatim
bogdanm	0:9b334a45a8ff	475	* @{
bogdanm	0:9b334a45a8ff	476	*/
bogdanm	0:9b334a45a8ff	477	/**
bogdanm	0:9b334a45a8ff	478	* @brief Initializes the TIM Output Compare according to the specified
bogdanm	0:9b334a45a8ff	479	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	480	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	481	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	482	* @retval HAL status
bogdanm	0:9b334a45a8ff	483	*/
bogdanm	0:9b334a45a8ff	484	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
bogdanm	0:9b334a45a8ff	485	{
bogdanm	0:9b334a45a8ff	486	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	487	if(htim == NULL)
bogdanm	0:9b334a45a8ff	488	{
bogdanm	0:9b334a45a8ff	489	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	490	}
bogdanm	0:9b334a45a8ff	491
bogdanm	0:9b334a45a8ff	492	/* Check the parameters */
bogdanm	0:9b334a45a8ff	493	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	494	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	495	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	496
bogdanm	0:9b334a45a8ff	497	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	498	{
bogdanm	0:9b334a45a8ff	499	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	500	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	501	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	502	HAL_TIM_OC_MspInit(htim);
bogdanm	0:9b334a45a8ff	503	}
bogdanm	0:9b334a45a8ff	504
bogdanm	0:9b334a45a8ff	505	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	506	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	507
bogdanm	0:9b334a45a8ff	508	/* Init the base time for the Output Compare */
bogdanm	0:9b334a45a8ff	509	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	512	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	513
bogdanm	0:9b334a45a8ff	514	return HAL_OK;
bogdanm	0:9b334a45a8ff	515	}
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	/**
bogdanm	0:9b334a45a8ff	518	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	519	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	520	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	521	* @retval HAL status
bogdanm	0:9b334a45a8ff	522	*/
bogdanm	0:9b334a45a8ff	523	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	524	{
bogdanm	0:9b334a45a8ff	525	/* Check the parameters */
bogdanm	0:9b334a45a8ff	526	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	527
bogdanm	0:9b334a45a8ff	528	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	531	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	532
bogdanm	0:9b334a45a8ff	533	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	534	HAL_TIM_OC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	/* Change TIM state */
bogdanm	0:9b334a45a8ff	537	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	/* Release Lock */
bogdanm	0:9b334a45a8ff	540	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	return HAL_OK;
bogdanm	0:9b334a45a8ff	543	}
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545	/**
bogdanm	0:9b334a45a8ff	546	* @brief Initializes the TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	547	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	548	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	549	* @retval None
bogdanm	0:9b334a45a8ff	550	*/
bogdanm	0:9b334a45a8ff	551	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	552	{
mbed_official	83:a036322b8637	553	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	554	UNUSED(htim);
mbed_official	83:a036322b8637	555
bogdanm	0:9b334a45a8ff	556	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	557	the HAL_TIM_OC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	558	*/
bogdanm	0:9b334a45a8ff	559	}
bogdanm	0:9b334a45a8ff	560
bogdanm	0:9b334a45a8ff	561	/**
bogdanm	0:9b334a45a8ff	562	* @brief DeInitializes TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	563	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	564	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	565	* @retval None
bogdanm	0:9b334a45a8ff	566	*/
bogdanm	0:9b334a45a8ff	567	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	568	{
mbed_official	83:a036322b8637	569	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	570	UNUSED(htim);
mbed_official	83:a036322b8637	571
bogdanm	0:9b334a45a8ff	572	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	573	the HAL_TIM_OC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	574	*/
bogdanm	0:9b334a45a8ff	575	}
bogdanm	0:9b334a45a8ff	576
bogdanm	0:9b334a45a8ff	577	/**
bogdanm	0:9b334a45a8ff	578	* @brief Starts the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	579	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	580	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	581	* @param Channel: TIM Channel to be enabled.
bogdanm	0:9b334a45a8ff	582	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	583	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	584	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	585	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	586	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	587	* @retval HAL status
bogdanm	0:9b334a45a8ff	588	*/
bogdanm	0:9b334a45a8ff	589	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	590	{
bogdanm	0:9b334a45a8ff	591	/* Check the parameters */
bogdanm	0:9b334a45a8ff	592	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	595	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	596
bogdanm	0:9b334a45a8ff	597	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	598	{
bogdanm	0:9b334a45a8ff	599	/* Enable the main output */
bogdanm	0:9b334a45a8ff	600	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	601	}
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	604	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	605
bogdanm	0:9b334a45a8ff	606	/* Return function status */
bogdanm	0:9b334a45a8ff	607	return HAL_OK;
bogdanm	0:9b334a45a8ff	608	}
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	/**
bogdanm	0:9b334a45a8ff	611	* @brief Stops the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	612	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	613	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	614	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	615	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	616	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	617	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	618	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	619	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	620	* @retval HAL status
bogdanm	0:9b334a45a8ff	621	*/
bogdanm	0:9b334a45a8ff	622	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	623	{
bogdanm	0:9b334a45a8ff	624	/* Check the parameters */
bogdanm	0:9b334a45a8ff	625	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	628	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	629
bogdanm	0:9b334a45a8ff	630	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	631	{
bogdanm	0:9b334a45a8ff	632	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	633	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	634	}
bogdanm	0:9b334a45a8ff	635
bogdanm	0:9b334a45a8ff	636	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	637	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	638
bogdanm	0:9b334a45a8ff	639	/* Return function status */
bogdanm	0:9b334a45a8ff	640	return HAL_OK;
bogdanm	0:9b334a45a8ff	641	}
bogdanm	0:9b334a45a8ff	642
bogdanm	0:9b334a45a8ff	643	/**
bogdanm	0:9b334a45a8ff	644	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	645	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	646	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	647	* @param Channel: TIM Channel to be enabled.
bogdanm	0:9b334a45a8ff	648	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	649	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	650	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	651	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	652	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	653	* @retval HAL status
bogdanm	0:9b334a45a8ff	654	*/
bogdanm	0:9b334a45a8ff	655	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	656	{
bogdanm	0:9b334a45a8ff	657	/* Check the parameters */
bogdanm	0:9b334a45a8ff	658	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	659
bogdanm	0:9b334a45a8ff	660	switch (Channel)
bogdanm	0:9b334a45a8ff	661	{
bogdanm	0:9b334a45a8ff	662	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	663	{
bogdanm	0:9b334a45a8ff	664	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	665	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	666	}
bogdanm	0:9b334a45a8ff	667	break;
bogdanm	0:9b334a45a8ff	668
bogdanm	0:9b334a45a8ff	669	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	670	{
bogdanm	0:9b334a45a8ff	671	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	672	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	673	}
bogdanm	0:9b334a45a8ff	674	break;
bogdanm	0:9b334a45a8ff	675
bogdanm	0:9b334a45a8ff	676	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	677	{
bogdanm	0:9b334a45a8ff	678	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	679	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	680	}
bogdanm	0:9b334a45a8ff	681	break;
bogdanm	0:9b334a45a8ff	682
bogdanm	0:9b334a45a8ff	683	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	684	{
bogdanm	0:9b334a45a8ff	685	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	686	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	687	}
bogdanm	0:9b334a45a8ff	688	break;
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	default:
bogdanm	0:9b334a45a8ff	691	break;
bogdanm	0:9b334a45a8ff	692	}
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	695	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	698	{
bogdanm	0:9b334a45a8ff	699	/* Enable the main output */
bogdanm	0:9b334a45a8ff	700	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	701	}
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	704	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706	/* Return function status */
bogdanm	0:9b334a45a8ff	707	return HAL_OK;
bogdanm	0:9b334a45a8ff	708	}
bogdanm	0:9b334a45a8ff	709
bogdanm	0:9b334a45a8ff	710	/**
bogdanm	0:9b334a45a8ff	711	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	712	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	713	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	714	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	715	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	716	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	717	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	718	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	719	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	720	* @retval HAL status
bogdanm	0:9b334a45a8ff	721	*/
bogdanm	0:9b334a45a8ff	722	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	723	{
bogdanm	0:9b334a45a8ff	724	/* Check the parameters */
bogdanm	0:9b334a45a8ff	725	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727	switch (Channel)
bogdanm	0:9b334a45a8ff	728	{
bogdanm	0:9b334a45a8ff	729	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	730	{
bogdanm	0:9b334a45a8ff	731	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	732	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	733	}
bogdanm	0:9b334a45a8ff	734	break;
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	737	{
bogdanm	0:9b334a45a8ff	738	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	739	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	740	}
bogdanm	0:9b334a45a8ff	741	break;
bogdanm	0:9b334a45a8ff	742
bogdanm	0:9b334a45a8ff	743	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	744	{
bogdanm	0:9b334a45a8ff	745	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	746	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	747	}
bogdanm	0:9b334a45a8ff	748	break;
bogdanm	0:9b334a45a8ff	749
bogdanm	0:9b334a45a8ff	750	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	753	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	754	}
bogdanm	0:9b334a45a8ff	755	break;
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	default:
bogdanm	0:9b334a45a8ff	758	break;
bogdanm	0:9b334a45a8ff	759	}
bogdanm	0:9b334a45a8ff	760
bogdanm	0:9b334a45a8ff	761	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	762	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	765	{
bogdanm	0:9b334a45a8ff	766	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	767	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	768	}
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	771	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	/* Return function status */
bogdanm	0:9b334a45a8ff	774	return HAL_OK;
bogdanm	0:9b334a45a8ff	775	}
bogdanm	0:9b334a45a8ff	776
bogdanm	0:9b334a45a8ff	777	/**
bogdanm	0:9b334a45a8ff	778	* @brief Starts the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	779	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	780	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	781	* @param Channel: TIM Channel to be enabled.
bogdanm	0:9b334a45a8ff	782	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	783	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	784	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	785	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	786	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	787	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	788	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	789	* @retval HAL status
bogdanm	0:9b334a45a8ff	790	*/
bogdanm	0:9b334a45a8ff	791	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	792	{
bogdanm	0:9b334a45a8ff	793	/* Check the parameters */
bogdanm	0:9b334a45a8ff	794	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	795
bogdanm	0:9b334a45a8ff	796	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	797	{
bogdanm	0:9b334a45a8ff	798	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	799	}
bogdanm	0:9b334a45a8ff	800	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	801	{
bogdanm	0:9b334a45a8ff	802	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	803	{
bogdanm	0:9b334a45a8ff	804	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	805	}
bogdanm	0:9b334a45a8ff	806	else
bogdanm	0:9b334a45a8ff	807	{
bogdanm	0:9b334a45a8ff	808	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	809	}
bogdanm	0:9b334a45a8ff	810	}
bogdanm	0:9b334a45a8ff	811	switch (Channel)
bogdanm	0:9b334a45a8ff	812	{
bogdanm	0:9b334a45a8ff	813	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	814	{
bogdanm	0:9b334a45a8ff	815	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	816	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	817
bogdanm	0:9b334a45a8ff	818	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	819	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	822	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	825	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	826	}
bogdanm	0:9b334a45a8ff	827	break;
bogdanm	0:9b334a45a8ff	828
bogdanm	0:9b334a45a8ff	829	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	830	{
bogdanm	0:9b334a45a8ff	831	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	832	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	833
bogdanm	0:9b334a45a8ff	834	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	835	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	836
bogdanm	0:9b334a45a8ff	837	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	838	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	841	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	842	}
bogdanm	0:9b334a45a8ff	843	break;
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	846	{
bogdanm	0:9b334a45a8ff	847	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	848	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	849
bogdanm	0:9b334a45a8ff	850	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	851	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	852
bogdanm	0:9b334a45a8ff	853	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	854	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	857	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	858	}
bogdanm	0:9b334a45a8ff	859	break;
bogdanm	0:9b334a45a8ff	860
bogdanm	0:9b334a45a8ff	861	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	862	{
bogdanm	0:9b334a45a8ff	863	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	864	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	865
bogdanm	0:9b334a45a8ff	866	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	867	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	868
bogdanm	0:9b334a45a8ff	869	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	870	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	871
bogdanm	0:9b334a45a8ff	872	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	873	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	874	}
bogdanm	0:9b334a45a8ff	875	break;
bogdanm	0:9b334a45a8ff	876
bogdanm	0:9b334a45a8ff	877	default:
bogdanm	0:9b334a45a8ff	878	break;
bogdanm	0:9b334a45a8ff	879	}
bogdanm	0:9b334a45a8ff	880
bogdanm	0:9b334a45a8ff	881	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	882	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	883
bogdanm	0:9b334a45a8ff	884	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	885	{
bogdanm	0:9b334a45a8ff	886	/* Enable the main output */
bogdanm	0:9b334a45a8ff	887	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	888	}
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	891	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	892
bogdanm	0:9b334a45a8ff	893	/* Return function status */
bogdanm	0:9b334a45a8ff	894	return HAL_OK;
bogdanm	0:9b334a45a8ff	895	}
bogdanm	0:9b334a45a8ff	896
bogdanm	0:9b334a45a8ff	897	/**
bogdanm	0:9b334a45a8ff	898	* @brief Stops the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	899	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	900	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	901	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	902	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	903	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	904	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	905	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	906	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	907	* @retval HAL status
bogdanm	0:9b334a45a8ff	908	*/
bogdanm	0:9b334a45a8ff	909	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	910	{
bogdanm	0:9b334a45a8ff	911	/* Check the parameters */
bogdanm	0:9b334a45a8ff	912	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	913
bogdanm	0:9b334a45a8ff	914	switch (Channel)
bogdanm	0:9b334a45a8ff	915	{
bogdanm	0:9b334a45a8ff	916	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	917	{
bogdanm	0:9b334a45a8ff	918	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	919	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	920	}
bogdanm	0:9b334a45a8ff	921	break;
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	924	{
bogdanm	0:9b334a45a8ff	925	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	926	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	927	}
bogdanm	0:9b334a45a8ff	928	break;
bogdanm	0:9b334a45a8ff	929
bogdanm	0:9b334a45a8ff	930	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	931	{
bogdanm	0:9b334a45a8ff	932	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	933	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	934	}
bogdanm	0:9b334a45a8ff	935	break;
bogdanm	0:9b334a45a8ff	936
bogdanm	0:9b334a45a8ff	937	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	938	{
bogdanm	0:9b334a45a8ff	939	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	940	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	941	}
bogdanm	0:9b334a45a8ff	942	break;
bogdanm	0:9b334a45a8ff	943
bogdanm	0:9b334a45a8ff	944	default:
bogdanm	0:9b334a45a8ff	945	break;
bogdanm	0:9b334a45a8ff	946	}
bogdanm	0:9b334a45a8ff	947
bogdanm	0:9b334a45a8ff	948	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	949	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	950
bogdanm	0:9b334a45a8ff	951	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	952	{
bogdanm	0:9b334a45a8ff	953	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	954	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	955	}
bogdanm	0:9b334a45a8ff	956
bogdanm	0:9b334a45a8ff	957	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	958	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	/* Change the htim state */
bogdanm	0:9b334a45a8ff	961	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	/* Return function status */
bogdanm	0:9b334a45a8ff	964	return HAL_OK;
bogdanm	0:9b334a45a8ff	965	}
bogdanm	0:9b334a45a8ff	966
bogdanm	0:9b334a45a8ff	967	/**
bogdanm	0:9b334a45a8ff	968	* @}
bogdanm	0:9b334a45a8ff	969	*/
bogdanm	0:9b334a45a8ff	970
bogdanm	0:9b334a45a8ff	971	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
bogdanm	0:9b334a45a8ff	972	* @brief Time PWM functions
bogdanm	0:9b334a45a8ff	973	*
bogdanm	0:9b334a45a8ff	974	@verbatim
bogdanm	0:9b334a45a8ff	975	==============================================================================
bogdanm	0:9b334a45a8ff	976	##### Time PWM functions #####
bogdanm	0:9b334a45a8ff	977	==============================================================================
bogdanm	0:9b334a45a8ff	978	[..]
bogdanm	0:9b334a45a8ff	979	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	980	(+) Initialize and configure the TIM OPWM.
bogdanm	0:9b334a45a8ff	981	(+) De-initialize the TIM PWM.
bogdanm	0:9b334a45a8ff	982	(+) Start the Time PWM.
bogdanm	0:9b334a45a8ff	983	(+) Stop the Time PWM.
bogdanm	0:9b334a45a8ff	984	(+) Start the Time PWM and enable interrupt.
bogdanm	0:9b334a45a8ff	985	(+) Stop the Time PWM and disable interrupt.
bogdanm	0:9b334a45a8ff	986	(+) Start the Time PWM and enable DMA transfer.
bogdanm	0:9b334a45a8ff	987	(+) Stop the Time PWM and disable DMA transfer.
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	@endverbatim
bogdanm	0:9b334a45a8ff	990	* @{
bogdanm	0:9b334a45a8ff	991	*/
bogdanm	0:9b334a45a8ff	992	/**
bogdanm	0:9b334a45a8ff	993	* @brief Initializes the TIM PWM Time Base according to the specified
bogdanm	0:9b334a45a8ff	994	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	995	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	996	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	997	* @retval HAL status
bogdanm	0:9b334a45a8ff	998	*/
bogdanm	0:9b334a45a8ff	999	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1000	{
bogdanm	0:9b334a45a8ff	1001	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1002	if(htim == NULL)
bogdanm	0:9b334a45a8ff	1003	{
bogdanm	0:9b334a45a8ff	1004	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1005	}
bogdanm	0:9b334a45a8ff	1006
bogdanm	0:9b334a45a8ff	1007	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1008	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1009	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1010	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1013	{
bogdanm	0:9b334a45a8ff	1014	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	1015	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	1016	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1017	HAL_TIM_PWM_MspInit(htim);
bogdanm	0:9b334a45a8ff	1018	}
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1021	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/* Init the base time for the PWM */
bogdanm	0:9b334a45a8ff	1024	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1027	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1028
bogdanm	0:9b334a45a8ff	1029	return HAL_OK;
bogdanm	0:9b334a45a8ff	1030	}
bogdanm	0:9b334a45a8ff	1031
bogdanm	0:9b334a45a8ff	1032	/**
bogdanm	0:9b334a45a8ff	1033	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	1034	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1035	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1036	* @retval HAL status
bogdanm	0:9b334a45a8ff	1037	*/
bogdanm	0:9b334a45a8ff	1038	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1039	{
bogdanm	0:9b334a45a8ff	1040	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1041	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1044
bogdanm	0:9b334a45a8ff	1045	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1046	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1049	HAL_TIM_PWM_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1050
bogdanm	0:9b334a45a8ff	1051	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1052	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/* Release Lock */
bogdanm	0:9b334a45a8ff	1055	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	return HAL_OK;
bogdanm	0:9b334a45a8ff	1058	}
bogdanm	0:9b334a45a8ff	1059
bogdanm	0:9b334a45a8ff	1060	/**
bogdanm	0:9b334a45a8ff	1061	* @brief Initializes the TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1062	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1063	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1064	* @retval None
bogdanm	0:9b334a45a8ff	1065	*/
bogdanm	0:9b334a45a8ff	1066	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1067	{
mbed_official	83:a036322b8637	1068	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1069	UNUSED(htim);
mbed_official	83:a036322b8637	1070
bogdanm	0:9b334a45a8ff	1071	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1072	the HAL_TIM_PWM_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1073	*/
bogdanm	0:9b334a45a8ff	1074	}
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	/**
bogdanm	0:9b334a45a8ff	1077	* @brief DeInitializes TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1078	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1079	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1080	* @retval None
bogdanm	0:9b334a45a8ff	1081	*/
bogdanm	0:9b334a45a8ff	1082	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1083	{
mbed_official	83:a036322b8637	1084	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1085	UNUSED(htim);
mbed_official	83:a036322b8637	1086
bogdanm	0:9b334a45a8ff	1087	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1088	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1089	*/
bogdanm	0:9b334a45a8ff	1090	}
bogdanm	0:9b334a45a8ff	1091
bogdanm	0:9b334a45a8ff	1092	/**
bogdanm	0:9b334a45a8ff	1093	* @brief Starts the PWM signal generation.
bogdanm	0:9b334a45a8ff	1094	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1095	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1096	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1097	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1098	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1099	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1100	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1101	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1102	* @retval HAL status
bogdanm	0:9b334a45a8ff	1103	*/
bogdanm	0:9b334a45a8ff	1104	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1105	{
bogdanm	0:9b334a45a8ff	1106	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1107	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1110	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1113	{
bogdanm	0:9b334a45a8ff	1114	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1115	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1116	}
bogdanm	0:9b334a45a8ff	1117
bogdanm	0:9b334a45a8ff	1118	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1119	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1120
bogdanm	0:9b334a45a8ff	1121	/* Return function status */
bogdanm	0:9b334a45a8ff	1122	return HAL_OK;
bogdanm	0:9b334a45a8ff	1123	}
bogdanm	0:9b334a45a8ff	1124
bogdanm	0:9b334a45a8ff	1125	/**
bogdanm	0:9b334a45a8ff	1126	* @brief Stops the PWM signal generation.
bogdanm	0:9b334a45a8ff	1127	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1128	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1129	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1130	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1131	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1132	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1133	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1134	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1135	* @retval HAL status
bogdanm	0:9b334a45a8ff	1136	*/
bogdanm	0:9b334a45a8ff	1137	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1138	{
bogdanm	0:9b334a45a8ff	1139	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1140	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1141
bogdanm	0:9b334a45a8ff	1142	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1143	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1144
bogdanm	0:9b334a45a8ff	1145	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1146	{
bogdanm	0:9b334a45a8ff	1147	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	1148	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1149	}
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1152	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1155	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	/* Return function status */
bogdanm	0:9b334a45a8ff	1158	return HAL_OK;
bogdanm	0:9b334a45a8ff	1159	}
bogdanm	0:9b334a45a8ff	1160
bogdanm	0:9b334a45a8ff	1161	/**
bogdanm	0:9b334a45a8ff	1162	* @brief Starts the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1163	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1164	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1165	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	1166	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1167	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1168	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1169	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1170	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1171	* @retval HAL status
bogdanm	0:9b334a45a8ff	1172	*/
bogdanm	0:9b334a45a8ff	1173	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1174	{
bogdanm	0:9b334a45a8ff	1175	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1176	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	switch (Channel)
bogdanm	0:9b334a45a8ff	1179	{
bogdanm	0:9b334a45a8ff	1180	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1181	{
bogdanm	0:9b334a45a8ff	1182	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1183	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1184	}
bogdanm	0:9b334a45a8ff	1185	break;
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1188	{
bogdanm	0:9b334a45a8ff	1189	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1190	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1191	}
bogdanm	0:9b334a45a8ff	1192	break;
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1195	{
bogdanm	0:9b334a45a8ff	1196	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1197	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1198	}
bogdanm	0:9b334a45a8ff	1199	break;
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1202	{
bogdanm	0:9b334a45a8ff	1203	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1204	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1205	}
bogdanm	0:9b334a45a8ff	1206	break;
bogdanm	0:9b334a45a8ff	1207
bogdanm	0:9b334a45a8ff	1208	default:
bogdanm	0:9b334a45a8ff	1209	break;
bogdanm	0:9b334a45a8ff	1210	}
bogdanm	0:9b334a45a8ff	1211
bogdanm	0:9b334a45a8ff	1212	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1213	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1214
bogdanm	0:9b334a45a8ff	1215	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1216	{
bogdanm	0:9b334a45a8ff	1217	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1218	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1219	}
bogdanm	0:9b334a45a8ff	1220
bogdanm	0:9b334a45a8ff	1221	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1222	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1223
bogdanm	0:9b334a45a8ff	1224	/* Return function status */
bogdanm	0:9b334a45a8ff	1225	return HAL_OK;
bogdanm	0:9b334a45a8ff	1226	}
bogdanm	0:9b334a45a8ff	1227
bogdanm	0:9b334a45a8ff	1228	/**
bogdanm	0:9b334a45a8ff	1229	* @brief Stops the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1230	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1231	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1232	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1233	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1234	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1235	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1236	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1237	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1238	* @retval HAL status
bogdanm	0:9b334a45a8ff	1239	*/
bogdanm	0:9b334a45a8ff	1240	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1241	{
bogdanm	0:9b334a45a8ff	1242	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1243	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1244
bogdanm	0:9b334a45a8ff	1245	switch (Channel)
bogdanm	0:9b334a45a8ff	1246	{
bogdanm	0:9b334a45a8ff	1247	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1248	{
bogdanm	0:9b334a45a8ff	1249	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1250	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1251	}
bogdanm	0:9b334a45a8ff	1252	break;
bogdanm	0:9b334a45a8ff	1253
bogdanm	0:9b334a45a8ff	1254	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1255	{
bogdanm	0:9b334a45a8ff	1256	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1257	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1258	}
bogdanm	0:9b334a45a8ff	1259	break;
bogdanm	0:9b334a45a8ff	1260
bogdanm	0:9b334a45a8ff	1261	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1262	{
bogdanm	0:9b334a45a8ff	1263	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1264	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1265	}
bogdanm	0:9b334a45a8ff	1266	break;
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1269	{
bogdanm	0:9b334a45a8ff	1270	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1271	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1272	}
bogdanm	0:9b334a45a8ff	1273	break;
bogdanm	0:9b334a45a8ff	1274
bogdanm	0:9b334a45a8ff	1275	default:
bogdanm	0:9b334a45a8ff	1276	break;
bogdanm	0:9b334a45a8ff	1277	}
bogdanm	0:9b334a45a8ff	1278
bogdanm	0:9b334a45a8ff	1279	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1280	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1281
bogdanm	0:9b334a45a8ff	1282	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1283	{
bogdanm	0:9b334a45a8ff	1284	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	1285	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1286	}
bogdanm	0:9b334a45a8ff	1287
bogdanm	0:9b334a45a8ff	1288	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1289	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1290
bogdanm	0:9b334a45a8ff	1291	/* Return function status */
bogdanm	0:9b334a45a8ff	1292	return HAL_OK;
bogdanm	0:9b334a45a8ff	1293	}
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	/**
bogdanm	0:9b334a45a8ff	1296	* @brief Starts the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1297	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1298	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1299	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1300	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1301	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1302	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1303	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1304	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1305	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	1306	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	1307	* @retval HAL status
bogdanm	0:9b334a45a8ff	1308	*/
bogdanm	0:9b334a45a8ff	1309	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1310	{
bogdanm	0:9b334a45a8ff	1311	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1312	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1313
bogdanm	0:9b334a45a8ff	1314	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1315	{
bogdanm	0:9b334a45a8ff	1316	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1317	}
bogdanm	0:9b334a45a8ff	1318	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1319	{
bogdanm	0:9b334a45a8ff	1320	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1321	{
bogdanm	0:9b334a45a8ff	1322	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1323	}
bogdanm	0:9b334a45a8ff	1324	else
bogdanm	0:9b334a45a8ff	1325	{
bogdanm	0:9b334a45a8ff	1326	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1327	}
bogdanm	0:9b334a45a8ff	1328	}
bogdanm	0:9b334a45a8ff	1329	switch (Channel)
bogdanm	0:9b334a45a8ff	1330	{
bogdanm	0:9b334a45a8ff	1331	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1332	{
bogdanm	0:9b334a45a8ff	1333	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1334	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1335
bogdanm	0:9b334a45a8ff	1336	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1337	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1338
bogdanm	0:9b334a45a8ff	1339	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1340	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1343	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1344	}
bogdanm	0:9b334a45a8ff	1345	break;
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1348	{
bogdanm	0:9b334a45a8ff	1349	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1350	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1353	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1354
bogdanm	0:9b334a45a8ff	1355	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1356	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	1357
bogdanm	0:9b334a45a8ff	1358	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1359	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1360	}
bogdanm	0:9b334a45a8ff	1361	break;
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1364	{
bogdanm	0:9b334a45a8ff	1365	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1366	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1369	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1372	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	1373
bogdanm	0:9b334a45a8ff	1374	/* Enable the TIM Output Capture/Compare 3 request */
bogdanm	0:9b334a45a8ff	1375	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1376	}
bogdanm	0:9b334a45a8ff	1377	break;
bogdanm	0:9b334a45a8ff	1378
bogdanm	0:9b334a45a8ff	1379	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1380	{
bogdanm	0:9b334a45a8ff	1381	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1382	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1383
bogdanm	0:9b334a45a8ff	1384	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1385	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1388	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	1389
bogdanm	0:9b334a45a8ff	1390	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1391	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1392	}
bogdanm	0:9b334a45a8ff	1393	break;
bogdanm	0:9b334a45a8ff	1394
bogdanm	0:9b334a45a8ff	1395	default:
bogdanm	0:9b334a45a8ff	1396	break;
bogdanm	0:9b334a45a8ff	1397	}
bogdanm	0:9b334a45a8ff	1398
bogdanm	0:9b334a45a8ff	1399	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1400	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1401
bogdanm	0:9b334a45a8ff	1402	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1403	{
bogdanm	0:9b334a45a8ff	1404	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1405	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1406	}
bogdanm	0:9b334a45a8ff	1407
bogdanm	0:9b334a45a8ff	1408	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1409	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1410
bogdanm	0:9b334a45a8ff	1411	/* Return function status */
bogdanm	0:9b334a45a8ff	1412	return HAL_OK;
bogdanm	0:9b334a45a8ff	1413	}
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	/**
bogdanm	0:9b334a45a8ff	1416	* @brief Stops the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1417	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1418	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1419	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1420	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1421	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1422	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1423	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1424	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1425	* @retval HAL status
bogdanm	0:9b334a45a8ff	1426	*/
bogdanm	0:9b334a45a8ff	1427	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1428	{
bogdanm	0:9b334a45a8ff	1429	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1430	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1431
bogdanm	0:9b334a45a8ff	1432	switch (Channel)
bogdanm	0:9b334a45a8ff	1433	{
bogdanm	0:9b334a45a8ff	1434	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1435	{
bogdanm	0:9b334a45a8ff	1436	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1437	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1438	}
bogdanm	0:9b334a45a8ff	1439	break;
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1442	{
bogdanm	0:9b334a45a8ff	1443	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1444	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1445	}
bogdanm	0:9b334a45a8ff	1446	break;
bogdanm	0:9b334a45a8ff	1447
bogdanm	0:9b334a45a8ff	1448	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1449	{
bogdanm	0:9b334a45a8ff	1450	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1451	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1452	}
bogdanm	0:9b334a45a8ff	1453	break;
bogdanm	0:9b334a45a8ff	1454
bogdanm	0:9b334a45a8ff	1455	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1456	{
bogdanm	0:9b334a45a8ff	1457	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1458	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1459	}
bogdanm	0:9b334a45a8ff	1460	break;
bogdanm	0:9b334a45a8ff	1461
bogdanm	0:9b334a45a8ff	1462	default:
bogdanm	0:9b334a45a8ff	1463	break;
bogdanm	0:9b334a45a8ff	1464	}
bogdanm	0:9b334a45a8ff	1465
bogdanm	0:9b334a45a8ff	1466	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1467	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1468
bogdanm	0:9b334a45a8ff	1469	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1470	{
bogdanm	0:9b334a45a8ff	1471	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	1472	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1473	}
bogdanm	0:9b334a45a8ff	1474
bogdanm	0:9b334a45a8ff	1475	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1476	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1477
bogdanm	0:9b334a45a8ff	1478	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1479	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1480
bogdanm	0:9b334a45a8ff	1481	/* Return function status */
bogdanm	0:9b334a45a8ff	1482	return HAL_OK;
bogdanm	0:9b334a45a8ff	1483	}
bogdanm	0:9b334a45a8ff	1484
bogdanm	0:9b334a45a8ff	1485	/**
bogdanm	0:9b334a45a8ff	1486	* @}
bogdanm	0:9b334a45a8ff	1487	*/
bogdanm	0:9b334a45a8ff	1488
bogdanm	0:9b334a45a8ff	1489	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
bogdanm	0:9b334a45a8ff	1490	* @brief Time Input Capture functions
bogdanm	0:9b334a45a8ff	1491	*
bogdanm	0:9b334a45a8ff	1492	@verbatim
bogdanm	0:9b334a45a8ff	1493	==============================================================================
bogdanm	0:9b334a45a8ff	1494	##### Time Input Capture functions #####
bogdanm	0:9b334a45a8ff	1495	==============================================================================
bogdanm	0:9b334a45a8ff	1496	[..]
bogdanm	0:9b334a45a8ff	1497	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1498	(+) Initialize and configure the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1499	(+) De-initialize the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1500	(+) Start the Time Input Capture.
bogdanm	0:9b334a45a8ff	1501	(+) Stop the Time Input Capture.
bogdanm	0:9b334a45a8ff	1502	(+) Start the Time Input Capture and enable interrupt.
bogdanm	0:9b334a45a8ff	1503	(+) Stop the Time Input Capture and disable interrupt.
bogdanm	0:9b334a45a8ff	1504	(+) Start the Time Input Capture and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1505	(+) Stop the Time Input Capture and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1506
bogdanm	0:9b334a45a8ff	1507	@endverbatim
bogdanm	0:9b334a45a8ff	1508	* @{
bogdanm	0:9b334a45a8ff	1509	*/
bogdanm	0:9b334a45a8ff	1510	/**
bogdanm	0:9b334a45a8ff	1511	* @brief Initializes the TIM Input Capture Time base according to the specified
bogdanm	0:9b334a45a8ff	1512	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	1513	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1514	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1515	* @retval HAL status
bogdanm	0:9b334a45a8ff	1516	*/
bogdanm	0:9b334a45a8ff	1517	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1518	{
bogdanm	0:9b334a45a8ff	1519	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1520	if(htim == NULL)
bogdanm	0:9b334a45a8ff	1521	{
bogdanm	0:9b334a45a8ff	1522	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1523	}
bogdanm	0:9b334a45a8ff	1524
bogdanm	0:9b334a45a8ff	1525	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1526	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1527	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1528	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1529
bogdanm	0:9b334a45a8ff	1530	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1531	{
bogdanm	0:9b334a45a8ff	1532	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	1533	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	1534	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1535	HAL_TIM_IC_MspInit(htim);
bogdanm	0:9b334a45a8ff	1536	}
bogdanm	0:9b334a45a8ff	1537
bogdanm	0:9b334a45a8ff	1538	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1539	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1540
bogdanm	0:9b334a45a8ff	1541	/* Init the base time for the input capture */
bogdanm	0:9b334a45a8ff	1542	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1543
bogdanm	0:9b334a45a8ff	1544	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1545	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1546
bogdanm	0:9b334a45a8ff	1547	return HAL_OK;
bogdanm	0:9b334a45a8ff	1548	}
bogdanm	0:9b334a45a8ff	1549
bogdanm	0:9b334a45a8ff	1550	/**
bogdanm	0:9b334a45a8ff	1551	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	1552	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1553	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1554	* @retval HAL status
bogdanm	0:9b334a45a8ff	1555	*/
bogdanm	0:9b334a45a8ff	1556	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1557	{
bogdanm	0:9b334a45a8ff	1558	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1559	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1562
bogdanm	0:9b334a45a8ff	1563	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1564	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1565
bogdanm	0:9b334a45a8ff	1566	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1567	HAL_TIM_IC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1568
bogdanm	0:9b334a45a8ff	1569	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1570	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1571
bogdanm	0:9b334a45a8ff	1572	/* Release Lock */
bogdanm	0:9b334a45a8ff	1573	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1574
bogdanm	0:9b334a45a8ff	1575	return HAL_OK;
bogdanm	0:9b334a45a8ff	1576	}
bogdanm	0:9b334a45a8ff	1577
bogdanm	0:9b334a45a8ff	1578	/**
bogdanm	0:9b334a45a8ff	1579	* @brief Initializes the TIM INput Capture MSP.
bogdanm	0:9b334a45a8ff	1580	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1581	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1582	* @retval None
bogdanm	0:9b334a45a8ff	1583	*/
bogdanm	0:9b334a45a8ff	1584	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1585	{
mbed_official	83:a036322b8637	1586	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1587	UNUSED(htim);
mbed_official	83:a036322b8637	1588
bogdanm	0:9b334a45a8ff	1589	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1590	the HAL_TIM_IC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1591	*/
bogdanm	0:9b334a45a8ff	1592	}
bogdanm	0:9b334a45a8ff	1593
bogdanm	0:9b334a45a8ff	1594	/**
bogdanm	0:9b334a45a8ff	1595	* @brief DeInitializes TIM Input Capture MSP.
bogdanm	0:9b334a45a8ff	1596	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1597	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1598	* @retval None
bogdanm	0:9b334a45a8ff	1599	*/
bogdanm	0:9b334a45a8ff	1600	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1601	{
mbed_official	83:a036322b8637	1602	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1603	UNUSED(htim);
mbed_official	83:a036322b8637	1604
bogdanm	0:9b334a45a8ff	1605	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1606	the HAL_TIM_IC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1607	*/
bogdanm	0:9b334a45a8ff	1608	}
bogdanm	0:9b334a45a8ff	1609
bogdanm	0:9b334a45a8ff	1610	/**
bogdanm	0:9b334a45a8ff	1611	* @brief Starts the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1612	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1613	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1614	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1615	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1616	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1617	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1618	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1619	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1620	* @retval HAL status
bogdanm	0:9b334a45a8ff	1621	*/
bogdanm	0:9b334a45a8ff	1622	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1623	{
bogdanm	0:9b334a45a8ff	1624	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1625	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1626
bogdanm	0:9b334a45a8ff	1627	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1628	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1629
bogdanm	0:9b334a45a8ff	1630	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1631	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1632
bogdanm	0:9b334a45a8ff	1633	/* Return function status */
bogdanm	0:9b334a45a8ff	1634	return HAL_OK;
bogdanm	0:9b334a45a8ff	1635	}
bogdanm	0:9b334a45a8ff	1636
bogdanm	0:9b334a45a8ff	1637	/**
bogdanm	0:9b334a45a8ff	1638	* @brief Stops the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1639	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1640	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1641	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1642	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1643	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1644	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1645	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1646	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1647	* @retval HAL status
bogdanm	0:9b334a45a8ff	1648	*/
bogdanm	0:9b334a45a8ff	1649	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1650	{
bogdanm	0:9b334a45a8ff	1651	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1652	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1653
bogdanm	0:9b334a45a8ff	1654	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1655	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1656
bogdanm	0:9b334a45a8ff	1657	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1658	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1659
bogdanm	0:9b334a45a8ff	1660	/* Return function status */
bogdanm	0:9b334a45a8ff	1661	return HAL_OK;
bogdanm	0:9b334a45a8ff	1662	}
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664	/**
bogdanm	0:9b334a45a8ff	1665	* @brief Starts the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1666	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1667	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1668	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1669	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1670	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1671	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1672	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1673	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1674	* @retval HAL status
bogdanm	0:9b334a45a8ff	1675	*/
bogdanm	0:9b334a45a8ff	1676	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1677	{
bogdanm	0:9b334a45a8ff	1678	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1679	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1680
bogdanm	0:9b334a45a8ff	1681	switch (Channel)
bogdanm	0:9b334a45a8ff	1682	{
bogdanm	0:9b334a45a8ff	1683	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1684	{
bogdanm	0:9b334a45a8ff	1685	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1686	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1687	}
bogdanm	0:9b334a45a8ff	1688	break;
bogdanm	0:9b334a45a8ff	1689
bogdanm	0:9b334a45a8ff	1690	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1691	{
bogdanm	0:9b334a45a8ff	1692	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1693	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1694	}
bogdanm	0:9b334a45a8ff	1695	break;
bogdanm	0:9b334a45a8ff	1696
bogdanm	0:9b334a45a8ff	1697	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1698	{
bogdanm	0:9b334a45a8ff	1699	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1700	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1701	}
bogdanm	0:9b334a45a8ff	1702	break;
bogdanm	0:9b334a45a8ff	1703
bogdanm	0:9b334a45a8ff	1704	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1705	{
bogdanm	0:9b334a45a8ff	1706	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1707	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1708	}
bogdanm	0:9b334a45a8ff	1709	break;
bogdanm	0:9b334a45a8ff	1710
bogdanm	0:9b334a45a8ff	1711	default:
bogdanm	0:9b334a45a8ff	1712	break;
bogdanm	0:9b334a45a8ff	1713	}
bogdanm	0:9b334a45a8ff	1714	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1715	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1718	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1719
bogdanm	0:9b334a45a8ff	1720	/* Return function status */
bogdanm	0:9b334a45a8ff	1721	return HAL_OK;
bogdanm	0:9b334a45a8ff	1722	}
bogdanm	0:9b334a45a8ff	1723
bogdanm	0:9b334a45a8ff	1724	/**
bogdanm	0:9b334a45a8ff	1725	* @brief Stops the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1726	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1727	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1728	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1729	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1730	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1731	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1732	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1733	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1734	* @retval HAL status
bogdanm	0:9b334a45a8ff	1735	*/
bogdanm	0:9b334a45a8ff	1736	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1737	{
bogdanm	0:9b334a45a8ff	1738	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1739	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1740
bogdanm	0:9b334a45a8ff	1741	switch (Channel)
bogdanm	0:9b334a45a8ff	1742	{
bogdanm	0:9b334a45a8ff	1743	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1744	{
bogdanm	0:9b334a45a8ff	1745	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1746	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1747	}
bogdanm	0:9b334a45a8ff	1748	break;
bogdanm	0:9b334a45a8ff	1749
bogdanm	0:9b334a45a8ff	1750	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1751	{
bogdanm	0:9b334a45a8ff	1752	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1753	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1754	}
bogdanm	0:9b334a45a8ff	1755	break;
bogdanm	0:9b334a45a8ff	1756
bogdanm	0:9b334a45a8ff	1757	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1758	{
bogdanm	0:9b334a45a8ff	1759	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1760	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1761	}
bogdanm	0:9b334a45a8ff	1762	break;
bogdanm	0:9b334a45a8ff	1763
bogdanm	0:9b334a45a8ff	1764	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1765	{
bogdanm	0:9b334a45a8ff	1766	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1767	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1768	}
bogdanm	0:9b334a45a8ff	1769	break;
bogdanm	0:9b334a45a8ff	1770
bogdanm	0:9b334a45a8ff	1771	default:
bogdanm	0:9b334a45a8ff	1772	break;
bogdanm	0:9b334a45a8ff	1773	}
bogdanm	0:9b334a45a8ff	1774
bogdanm	0:9b334a45a8ff	1775	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1776	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1777
bogdanm	0:9b334a45a8ff	1778	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1779	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1780
bogdanm	0:9b334a45a8ff	1781	/* Return function status */
bogdanm	0:9b334a45a8ff	1782	return HAL_OK;
bogdanm	0:9b334a45a8ff	1783	}
bogdanm	0:9b334a45a8ff	1784
bogdanm	0:9b334a45a8ff	1785	/**
bogdanm	0:9b334a45a8ff	1786	* @brief Starts the TIM Input Capture measurement on in DMA mode.
bogdanm	0:9b334a45a8ff	1787	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1788	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1789	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1790	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1791	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1792	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1793	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1794	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1795	* @param pData: The destination Buffer address.
bogdanm	0:9b334a45a8ff	1796	* @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	1797	* @retval HAL status
bogdanm	0:9b334a45a8ff	1798	*/
bogdanm	0:9b334a45a8ff	1799	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1800	{
bogdanm	0:9b334a45a8ff	1801	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1802	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1803	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1804
bogdanm	0:9b334a45a8ff	1805	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1806	{
bogdanm	0:9b334a45a8ff	1807	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1808	}
bogdanm	0:9b334a45a8ff	1809	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1810	{
bogdanm	0:9b334a45a8ff	1811	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1812	{
bogdanm	0:9b334a45a8ff	1813	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1814	}
bogdanm	0:9b334a45a8ff	1815	else
bogdanm	0:9b334a45a8ff	1816	{
bogdanm	0:9b334a45a8ff	1817	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1818	}
bogdanm	0:9b334a45a8ff	1819	}
bogdanm	0:9b334a45a8ff	1820
bogdanm	0:9b334a45a8ff	1821	switch (Channel)
bogdanm	0:9b334a45a8ff	1822	{
bogdanm	0:9b334a45a8ff	1823	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1824	{
bogdanm	0:9b334a45a8ff	1825	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1826	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1827
bogdanm	0:9b334a45a8ff	1828	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1829	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1830
bogdanm	0:9b334a45a8ff	1831	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1832	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1835	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1836	}
bogdanm	0:9b334a45a8ff	1837	break;
bogdanm	0:9b334a45a8ff	1838
bogdanm	0:9b334a45a8ff	1839	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1840	{
bogdanm	0:9b334a45a8ff	1841	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1842	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1843
bogdanm	0:9b334a45a8ff	1844	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1845	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1846
bogdanm	0:9b334a45a8ff	1847	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1848	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1849
bogdanm	0:9b334a45a8ff	1850	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1851	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1852	}
bogdanm	0:9b334a45a8ff	1853	break;
bogdanm	0:9b334a45a8ff	1854
bogdanm	0:9b334a45a8ff	1855	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1856	{
bogdanm	0:9b334a45a8ff	1857	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1858	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1859
bogdanm	0:9b334a45a8ff	1860	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1861	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1862
bogdanm	0:9b334a45a8ff	1863	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1864	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1865
bogdanm	0:9b334a45a8ff	1866	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1867	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1868	}
bogdanm	0:9b334a45a8ff	1869	break;
bogdanm	0:9b334a45a8ff	1870
bogdanm	0:9b334a45a8ff	1871	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1872	{
bogdanm	0:9b334a45a8ff	1873	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1874	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1875
bogdanm	0:9b334a45a8ff	1876	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1877	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1878
bogdanm	0:9b334a45a8ff	1879	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1880	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1881
bogdanm	0:9b334a45a8ff	1882	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1883	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1884	}
bogdanm	0:9b334a45a8ff	1885	break;
bogdanm	0:9b334a45a8ff	1886
bogdanm	0:9b334a45a8ff	1887	default:
bogdanm	0:9b334a45a8ff	1888	break;
bogdanm	0:9b334a45a8ff	1889	}
bogdanm	0:9b334a45a8ff	1890
bogdanm	0:9b334a45a8ff	1891	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1892	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1893
bogdanm	0:9b334a45a8ff	1894	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1895	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1896
bogdanm	0:9b334a45a8ff	1897	/* Return function status */
bogdanm	0:9b334a45a8ff	1898	return HAL_OK;
bogdanm	0:9b334a45a8ff	1899	}
bogdanm	0:9b334a45a8ff	1900
bogdanm	0:9b334a45a8ff	1901	/**
bogdanm	0:9b334a45a8ff	1902	* @brief Stops the TIM Input Capture measurement on in DMA mode.
bogdanm	0:9b334a45a8ff	1903	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1904	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1905	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1906	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1907	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1908	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1909	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1910	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1911	* @retval HAL status
bogdanm	0:9b334a45a8ff	1912	*/
bogdanm	0:9b334a45a8ff	1913	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1914	{
bogdanm	0:9b334a45a8ff	1915	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1916	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1917	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1918
bogdanm	0:9b334a45a8ff	1919	switch (Channel)
bogdanm	0:9b334a45a8ff	1920	{
bogdanm	0:9b334a45a8ff	1921	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1922	{
bogdanm	0:9b334a45a8ff	1923	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1924	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1925	}
bogdanm	0:9b334a45a8ff	1926	break;
bogdanm	0:9b334a45a8ff	1927
bogdanm	0:9b334a45a8ff	1928	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1929	{
bogdanm	0:9b334a45a8ff	1930	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1931	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1932	}
bogdanm	0:9b334a45a8ff	1933	break;
bogdanm	0:9b334a45a8ff	1934
bogdanm	0:9b334a45a8ff	1935	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1936	{
bogdanm	0:9b334a45a8ff	1937	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1938	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1939	}
bogdanm	0:9b334a45a8ff	1940	break;
bogdanm	0:9b334a45a8ff	1941
bogdanm	0:9b334a45a8ff	1942	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1943	{
bogdanm	0:9b334a45a8ff	1944	/* Disable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1945	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1946	}
bogdanm	0:9b334a45a8ff	1947	break;
bogdanm	0:9b334a45a8ff	1948
bogdanm	0:9b334a45a8ff	1949	default:
bogdanm	0:9b334a45a8ff	1950	break;
bogdanm	0:9b334a45a8ff	1951	}
bogdanm	0:9b334a45a8ff	1952
bogdanm	0:9b334a45a8ff	1953	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1954	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1955
bogdanm	0:9b334a45a8ff	1956	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1957	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1958
bogdanm	0:9b334a45a8ff	1959	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1960	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1961
bogdanm	0:9b334a45a8ff	1962	/* Return function status */
bogdanm	0:9b334a45a8ff	1963	return HAL_OK;
bogdanm	0:9b334a45a8ff	1964	}
bogdanm	0:9b334a45a8ff	1965	/**
bogdanm	0:9b334a45a8ff	1966	* @}
bogdanm	0:9b334a45a8ff	1967	*/
bogdanm	0:9b334a45a8ff	1968
bogdanm	0:9b334a45a8ff	1969	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
bogdanm	0:9b334a45a8ff	1970	* @brief Time One Pulse functions
bogdanm	0:9b334a45a8ff	1971	*
bogdanm	0:9b334a45a8ff	1972	@verbatim
bogdanm	0:9b334a45a8ff	1973	==============================================================================
bogdanm	0:9b334a45a8ff	1974	##### Time One Pulse functions #####
bogdanm	0:9b334a45a8ff	1975	==============================================================================
bogdanm	0:9b334a45a8ff	1976	[..]
bogdanm	0:9b334a45a8ff	1977	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1978	(+) Initialize and configure the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1979	(+) De-initialize the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1980	(+) Start the Time One Pulse.
bogdanm	0:9b334a45a8ff	1981	(+) Stop the Time One Pulse.
bogdanm	0:9b334a45a8ff	1982	(+) Start the Time One Pulse and enable interrupt.
bogdanm	0:9b334a45a8ff	1983	(+) Stop the Time One Pulse and disable interrupt.
bogdanm	0:9b334a45a8ff	1984	(+) Start the Time One Pulse and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1985	(+) Stop the Time One Pulse and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1986
bogdanm	0:9b334a45a8ff	1987	@endverbatim
bogdanm	0:9b334a45a8ff	1988	* @{
bogdanm	0:9b334a45a8ff	1989	*/
bogdanm	0:9b334a45a8ff	1990	/**
bogdanm	0:9b334a45a8ff	1991	* @brief Initializes the TIM One Pulse Time Base according to the specified
bogdanm	0:9b334a45a8ff	1992	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	1993	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1994	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1995	* @param OnePulseMode: Select the One pulse mode.
bogdanm	0:9b334a45a8ff	1996	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1997	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
bogdanm	0:9b334a45a8ff	1998	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
bogdanm	0:9b334a45a8ff	1999	* @retval HAL status
bogdanm	0:9b334a45a8ff	2000	*/
bogdanm	0:9b334a45a8ff	2001	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
bogdanm	0:9b334a45a8ff	2002	{
bogdanm	0:9b334a45a8ff	2003	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	2004	if(htim == NULL)
bogdanm	0:9b334a45a8ff	2005	{
bogdanm	0:9b334a45a8ff	2006	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2007	}
bogdanm	0:9b334a45a8ff	2008
bogdanm	0:9b334a45a8ff	2009	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2010	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2011	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	2012	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	2013	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
bogdanm	0:9b334a45a8ff	2014
bogdanm	0:9b334a45a8ff	2015	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	2016	{
bogdanm	0:9b334a45a8ff	2017	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	2018	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	2019	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	2020	HAL_TIM_OnePulse_MspInit(htim);
bogdanm	0:9b334a45a8ff	2021	}
bogdanm	0:9b334a45a8ff	2022
bogdanm	0:9b334a45a8ff	2023	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	2024	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2025
bogdanm	0:9b334a45a8ff	2026	/* Configure the Time base in the One Pulse Mode */
bogdanm	0:9b334a45a8ff	2027	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	2028
bogdanm	0:9b334a45a8ff	2029	/* Reset the OPM Bit */
bogdanm	0:9b334a45a8ff	2030	htim->Instance->CR1 &= ~TIM_CR1_OPM;
bogdanm	0:9b334a45a8ff	2031
bogdanm	0:9b334a45a8ff	2032	/* Configure the OPM Mode */
bogdanm	0:9b334a45a8ff	2033	htim->Instance->CR1 \|= OnePulseMode;
bogdanm	0:9b334a45a8ff	2034
bogdanm	0:9b334a45a8ff	2035	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	2036	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2037
bogdanm	0:9b334a45a8ff	2038	return HAL_OK;
bogdanm	0:9b334a45a8ff	2039	}
bogdanm	0:9b334a45a8ff	2040
bogdanm	0:9b334a45a8ff	2041	/**
bogdanm	0:9b334a45a8ff	2042	* @brief DeInitializes the TIM One Pulse
bogdanm	0:9b334a45a8ff	2043	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2044	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2045	* @retval HAL status
bogdanm	0:9b334a45a8ff	2046	*/
bogdanm	0:9b334a45a8ff	2047	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2048	{
bogdanm	0:9b334a45a8ff	2049	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2050	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2051
bogdanm	0:9b334a45a8ff	2052	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2053
bogdanm	0:9b334a45a8ff	2054	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	2055	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2056
bogdanm	0:9b334a45a8ff	2057	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	2058	HAL_TIM_OnePulse_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	2059
bogdanm	0:9b334a45a8ff	2060	/* Change TIM state */
bogdanm	0:9b334a45a8ff	2061	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	2062
bogdanm	0:9b334a45a8ff	2063	/* Release Lock */
bogdanm	0:9b334a45a8ff	2064	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2065
bogdanm	0:9b334a45a8ff	2066	return HAL_OK;
bogdanm	0:9b334a45a8ff	2067	}
bogdanm	0:9b334a45a8ff	2068
bogdanm	0:9b334a45a8ff	2069	/**
bogdanm	0:9b334a45a8ff	2070	* @brief Initializes the TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	2071	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2072	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2073	* @retval None
bogdanm	0:9b334a45a8ff	2074	*/
bogdanm	0:9b334a45a8ff	2075	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2076	{
mbed_official	83:a036322b8637	2077	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	2078	UNUSED(htim);
mbed_official	83:a036322b8637	2079
bogdanm	0:9b334a45a8ff	2080	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2081	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2082	*/
bogdanm	0:9b334a45a8ff	2083	}
bogdanm	0:9b334a45a8ff	2084
bogdanm	0:9b334a45a8ff	2085	/**
bogdanm	0:9b334a45a8ff	2086	* @brief DeInitializes TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	2087	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2088	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2089	* @retval None
bogdanm	0:9b334a45a8ff	2090	*/
bogdanm	0:9b334a45a8ff	2091	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2092	{
mbed_official	83:a036322b8637	2093	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	2094	UNUSED(htim);
mbed_official	83:a036322b8637	2095
bogdanm	0:9b334a45a8ff	2096	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2097	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2098	*/
bogdanm	0:9b334a45a8ff	2099	}
bogdanm	0:9b334a45a8ff	2100
bogdanm	0:9b334a45a8ff	2101	/**
bogdanm	0:9b334a45a8ff	2102	* @brief Starts the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2103	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2104	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2105	* @param OutputChannel : TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2106	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2107	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2108	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2109	* @retval HAL status
bogdanm	0:9b334a45a8ff	2110	*/
bogdanm	0:9b334a45a8ff	2111	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2112	{
bogdanm	0:9b334a45a8ff	2113	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2114	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2115	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2116	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2117	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2118
bogdanm	0:9b334a45a8ff	2119	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2120	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2121
bogdanm	0:9b334a45a8ff	2122	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2123	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2124
bogdanm	0:9b334a45a8ff	2125	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2126	{
bogdanm	0:9b334a45a8ff	2127	/* Enable the main output */
bogdanm	0:9b334a45a8ff	2128	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2129	}
bogdanm	0:9b334a45a8ff	2130
bogdanm	0:9b334a45a8ff	2131	/* Return function status */
bogdanm	0:9b334a45a8ff	2132	return HAL_OK;
bogdanm	0:9b334a45a8ff	2133	}
bogdanm	0:9b334a45a8ff	2134
bogdanm	0:9b334a45a8ff	2135	/**
bogdanm	0:9b334a45a8ff	2136	* @brief Stops the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2137	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2138	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2139	* @param OutputChannel : TIM Channels to be disable.
bogdanm	0:9b334a45a8ff	2140	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2141	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2142	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2143	* @retval HAL status
bogdanm	0:9b334a45a8ff	2144	*/
bogdanm	0:9b334a45a8ff	2145	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2146	{
bogdanm	0:9b334a45a8ff	2147	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2148	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2149	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2150	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2151	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2152
bogdanm	0:9b334a45a8ff	2153	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2154	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2155
bogdanm	0:9b334a45a8ff	2156	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2157	{
bogdanm	0:9b334a45a8ff	2158	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	2159	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2160	}
bogdanm	0:9b334a45a8ff	2161
bogdanm	0:9b334a45a8ff	2162	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2163	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2164
bogdanm	0:9b334a45a8ff	2165	/* Return function status */
bogdanm	0:9b334a45a8ff	2166	return HAL_OK;
bogdanm	0:9b334a45a8ff	2167	}
bogdanm	0:9b334a45a8ff	2168
bogdanm	0:9b334a45a8ff	2169	/**
bogdanm	0:9b334a45a8ff	2170	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2171	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2172	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2173	* @param OutputChannel : TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2174	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2175	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2176	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2177	* @retval HAL status
bogdanm	0:9b334a45a8ff	2178	*/
bogdanm	0:9b334a45a8ff	2179	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2180	{
bogdanm	0:9b334a45a8ff	2181	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2182	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2183	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2184	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2185	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2186
bogdanm	0:9b334a45a8ff	2187	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2188	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2189
bogdanm	0:9b334a45a8ff	2190	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2191	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2192
bogdanm	0:9b334a45a8ff	2193	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2194	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2195
bogdanm	0:9b334a45a8ff	2196	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2197	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2198
bogdanm	0:9b334a45a8ff	2199	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2200	{
bogdanm	0:9b334a45a8ff	2201	/* Enable the main output */
bogdanm	0:9b334a45a8ff	2202	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2203	}
bogdanm	0:9b334a45a8ff	2204
bogdanm	0:9b334a45a8ff	2205	/* Return function status */
bogdanm	0:9b334a45a8ff	2206	return HAL_OK;
bogdanm	0:9b334a45a8ff	2207	}
bogdanm	0:9b334a45a8ff	2208
bogdanm	0:9b334a45a8ff	2209	/**
bogdanm	0:9b334a45a8ff	2210	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2211	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2212	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2213	* @param OutputChannel : TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2214	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2215	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2216	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2217	* @retval HAL status
bogdanm	0:9b334a45a8ff	2218	*/
bogdanm	0:9b334a45a8ff	2219	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2220	{
bogdanm	0:9b334a45a8ff	2221	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2222	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2223
bogdanm	0:9b334a45a8ff	2224	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2225	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2226
bogdanm	0:9b334a45a8ff	2227	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2228	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2229	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2230	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2231	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2232	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2233	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2234
bogdanm	0:9b334a45a8ff	2235	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2236	{
bogdanm	0:9b334a45a8ff	2237	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	2238	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2239	}
bogdanm	0:9b334a45a8ff	2240
bogdanm	0:9b334a45a8ff	2241	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2242	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2243
bogdanm	0:9b334a45a8ff	2244	/* Return function status */
bogdanm	0:9b334a45a8ff	2245	return HAL_OK;
bogdanm	0:9b334a45a8ff	2246	}
bogdanm	0:9b334a45a8ff	2247
bogdanm	0:9b334a45a8ff	2248	/**
bogdanm	0:9b334a45a8ff	2249	* @}
bogdanm	0:9b334a45a8ff	2250	*/
bogdanm	0:9b334a45a8ff	2251
bogdanm	0:9b334a45a8ff	2252	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
bogdanm	0:9b334a45a8ff	2253	* @brief Time Encoder functions
bogdanm	0:9b334a45a8ff	2254	*
bogdanm	0:9b334a45a8ff	2255	@verbatim
bogdanm	0:9b334a45a8ff	2256	==============================================================================
bogdanm	0:9b334a45a8ff	2257	##### Time Encoder functions #####
bogdanm	0:9b334a45a8ff	2258	==============================================================================
bogdanm	0:9b334a45a8ff	2259	[..]
bogdanm	0:9b334a45a8ff	2260	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2261	(+) Initialize and configure the TIM Encoder.
bogdanm	0:9b334a45a8ff	2262	(+) De-initialize the TIM Encoder.
bogdanm	0:9b334a45a8ff	2263	(+) Start the Time Encoder.
bogdanm	0:9b334a45a8ff	2264	(+) Stop the Time Encoder.
bogdanm	0:9b334a45a8ff	2265	(+) Start the Time Encoder and enable interrupt.
bogdanm	0:9b334a45a8ff	2266	(+) Stop the Time Encoder and disable interrupt.
bogdanm	0:9b334a45a8ff	2267	(+) Start the Time Encoder and enable DMA transfer.
bogdanm	0:9b334a45a8ff	2268	(+) Stop the Time Encoder and disable DMA transfer.
bogdanm	0:9b334a45a8ff	2269
bogdanm	0:9b334a45a8ff	2270	@endverbatim
bogdanm	0:9b334a45a8ff	2271	* @{
bogdanm	0:9b334a45a8ff	2272	*/
bogdanm	0:9b334a45a8ff	2273	/**
bogdanm	0:9b334a45a8ff	2274	* @brief Initializes the TIM Encoder Interface and create the associated handle.
bogdanm	0:9b334a45a8ff	2275	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2276	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2277	* @param sConfig: TIM Encoder Interface configuration structure
bogdanm	0:9b334a45a8ff	2278	* @retval HAL status
bogdanm	0:9b334a45a8ff	2279	*/
bogdanm	0:9b334a45a8ff	2280	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
bogdanm	0:9b334a45a8ff	2281	{
bogdanm	0:9b334a45a8ff	2282	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	2283	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	2284	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	2285
bogdanm	0:9b334a45a8ff	2286	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	2287	if(htim == NULL)
bogdanm	0:9b334a45a8ff	2288	{
bogdanm	0:9b334a45a8ff	2289	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2290	}
bogdanm	0:9b334a45a8ff	2291
bogdanm	0:9b334a45a8ff	2292	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2293	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2294	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
bogdanm	0:9b334a45a8ff	2295	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
bogdanm	0:9b334a45a8ff	2296	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
bogdanm	0:9b334a45a8ff	2297	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
bogdanm	0:9b334a45a8ff	2298	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
bogdanm	0:9b334a45a8ff	2299	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
bogdanm	0:9b334a45a8ff	2300	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
bogdanm	0:9b334a45a8ff	2301	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
bogdanm	0:9b334a45a8ff	2302	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
bogdanm	0:9b334a45a8ff	2303
bogdanm	0:9b334a45a8ff	2304	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	2305	{
bogdanm	0:9b334a45a8ff	2306	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	2307	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	2308	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	2309	HAL_TIM_Encoder_MspInit(htim);
bogdanm	0:9b334a45a8ff	2310	}
bogdanm	0:9b334a45a8ff	2311
bogdanm	0:9b334a45a8ff	2312	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	2313	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2314
bogdanm	0:9b334a45a8ff	2315	/* Reset the SMS bits */
bogdanm	0:9b334a45a8ff	2316	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	2317
bogdanm	0:9b334a45a8ff	2318	/* Configure the Time base in the Encoder Mode */
bogdanm	0:9b334a45a8ff	2319	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	2320
bogdanm	0:9b334a45a8ff	2321	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	2322	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	2323
bogdanm	0:9b334a45a8ff	2324	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	2325	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	2326
bogdanm	0:9b334a45a8ff	2327	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	2328	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	2329
bogdanm	0:9b334a45a8ff	2330	/* Set the encoder Mode */
bogdanm	0:9b334a45a8ff	2331	tmpsmcr \|= sConfig->EncoderMode;
bogdanm	0:9b334a45a8ff	2332
bogdanm	0:9b334a45a8ff	2333	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
bogdanm	0:9b334a45a8ff	2334	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
bogdanm	0:9b334a45a8ff	2335	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
bogdanm	0:9b334a45a8ff	2336
bogdanm	0:9b334a45a8ff	2337	/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
bogdanm	0:9b334a45a8ff	2338	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
bogdanm	0:9b334a45a8ff	2339	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	2340	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
bogdanm	0:9b334a45a8ff	2341	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
bogdanm	0:9b334a45a8ff	2342
bogdanm	0:9b334a45a8ff	2343	/* Set the TI1 and the TI2 Polarities */
bogdanm	0:9b334a45a8ff	2344	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
bogdanm	0:9b334a45a8ff	2345	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	2346	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
bogdanm	0:9b334a45a8ff	2347
bogdanm	0:9b334a45a8ff	2348	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	2349	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	2350
bogdanm	0:9b334a45a8ff	2351	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	2352	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	2353
bogdanm	0:9b334a45a8ff	2354	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	2355	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	2356
bogdanm	0:9b334a45a8ff	2357	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	2358	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2359
bogdanm	0:9b334a45a8ff	2360	return HAL_OK;
bogdanm	0:9b334a45a8ff	2361	}
bogdanm	0:9b334a45a8ff	2362
bogdanm	0:9b334a45a8ff	2363	/**
bogdanm	0:9b334a45a8ff	2364	* @brief DeInitializes the TIM Encoder interface
bogdanm	0:9b334a45a8ff	2365	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2366	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2367	* @retval HAL status
bogdanm	0:9b334a45a8ff	2368	*/
bogdanm	0:9b334a45a8ff	2369	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2370	{
bogdanm	0:9b334a45a8ff	2371	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2372	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2373
bogdanm	0:9b334a45a8ff	2374	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2375
bogdanm	0:9b334a45a8ff	2376	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	2377	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2378
bogdanm	0:9b334a45a8ff	2379	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	2380	HAL_TIM_Encoder_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	2381
bogdanm	0:9b334a45a8ff	2382	/* Change TIM state */
bogdanm	0:9b334a45a8ff	2383	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	2384
bogdanm	0:9b334a45a8ff	2385	/* Release Lock */
bogdanm	0:9b334a45a8ff	2386	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2387
bogdanm	0:9b334a45a8ff	2388	return HAL_OK;
bogdanm	0:9b334a45a8ff	2389	}
bogdanm	0:9b334a45a8ff	2390
bogdanm	0:9b334a45a8ff	2391	/**
bogdanm	0:9b334a45a8ff	2392	* @brief Initializes the TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2393	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2394	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2395	* @retval None
bogdanm	0:9b334a45a8ff	2396	*/
bogdanm	0:9b334a45a8ff	2397	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2398	{
mbed_official	83:a036322b8637	2399	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	2400	UNUSED(htim);
mbed_official	83:a036322b8637	2401
bogdanm	0:9b334a45a8ff	2402	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2403	the HAL_TIM_Encoder_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2404	*/
bogdanm	0:9b334a45a8ff	2405	}
bogdanm	0:9b334a45a8ff	2406
bogdanm	0:9b334a45a8ff	2407	/**
bogdanm	0:9b334a45a8ff	2408	* @brief DeInitializes TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2409	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2410	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2411	* @retval None
bogdanm	0:9b334a45a8ff	2412	*/
bogdanm	0:9b334a45a8ff	2413	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2414	{
mbed_official	83:a036322b8637	2415	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	2416	UNUSED(htim);
mbed_official	83:a036322b8637	2417
bogdanm	0:9b334a45a8ff	2418	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2419	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2420	*/
bogdanm	0:9b334a45a8ff	2421	}
bogdanm	0:9b334a45a8ff	2422
bogdanm	0:9b334a45a8ff	2423	/**
bogdanm	0:9b334a45a8ff	2424	* @brief Starts the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2425	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2426	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2427	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2428	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2429	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2430	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2431	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2432	* @retval HAL status
bogdanm	0:9b334a45a8ff	2433	*/
bogdanm	0:9b334a45a8ff	2434	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2435	{
bogdanm	0:9b334a45a8ff	2436	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2437	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2438
bogdanm	0:9b334a45a8ff	2439	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2440	switch (Channel)
bogdanm	0:9b334a45a8ff	2441	{
bogdanm	0:9b334a45a8ff	2442	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2443	{
bogdanm	0:9b334a45a8ff	2444	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2445	break;
bogdanm	0:9b334a45a8ff	2446	}
bogdanm	0:9b334a45a8ff	2447	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2448	{
bogdanm	0:9b334a45a8ff	2449	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2450	break;
bogdanm	0:9b334a45a8ff	2451	}
bogdanm	0:9b334a45a8ff	2452	default :
bogdanm	0:9b334a45a8ff	2453	{
bogdanm	0:9b334a45a8ff	2454	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2455	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2456	break;
bogdanm	0:9b334a45a8ff	2457	}
bogdanm	0:9b334a45a8ff	2458	}
bogdanm	0:9b334a45a8ff	2459	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2460	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2461
bogdanm	0:9b334a45a8ff	2462	/* Return function status */
bogdanm	0:9b334a45a8ff	2463	return HAL_OK;
bogdanm	0:9b334a45a8ff	2464	}
bogdanm	0:9b334a45a8ff	2465
bogdanm	0:9b334a45a8ff	2466	/**
bogdanm	0:9b334a45a8ff	2467	* @brief Stops the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2468	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2469	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2470	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	2471	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2472	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2473	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2474	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2475	* @retval HAL status
bogdanm	0:9b334a45a8ff	2476	*/
bogdanm	0:9b334a45a8ff	2477	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2478	{
bogdanm	0:9b334a45a8ff	2479	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2480	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2481
bogdanm	0:9b334a45a8ff	2482	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2483	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2484	switch (Channel)
bogdanm	0:9b334a45a8ff	2485	{
bogdanm	0:9b334a45a8ff	2486	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2487	{
bogdanm	0:9b334a45a8ff	2488	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2489	break;
bogdanm	0:9b334a45a8ff	2490	}
bogdanm	0:9b334a45a8ff	2491	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2492	{
bogdanm	0:9b334a45a8ff	2493	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2494	break;
bogdanm	0:9b334a45a8ff	2495	}
bogdanm	0:9b334a45a8ff	2496	default :
bogdanm	0:9b334a45a8ff	2497	{
bogdanm	0:9b334a45a8ff	2498	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2499	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2500	break;
bogdanm	0:9b334a45a8ff	2501	}
bogdanm	0:9b334a45a8ff	2502	}
bogdanm	0:9b334a45a8ff	2503	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2504	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2505
bogdanm	0:9b334a45a8ff	2506	/* Return function status */
bogdanm	0:9b334a45a8ff	2507	return HAL_OK;
bogdanm	0:9b334a45a8ff	2508	}
bogdanm	0:9b334a45a8ff	2509
bogdanm	0:9b334a45a8ff	2510	/**
bogdanm	0:9b334a45a8ff	2511	* @brief Starts the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2512	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2513	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2514	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2515	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2516	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2517	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2518	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2519	* @retval HAL status
bogdanm	0:9b334a45a8ff	2520	*/
bogdanm	0:9b334a45a8ff	2521	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2522	{
bogdanm	0:9b334a45a8ff	2523	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2524	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2525
bogdanm	0:9b334a45a8ff	2526	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2527	/* Enable the capture compare Interrupts 1 and/or 2 */
bogdanm	0:9b334a45a8ff	2528	switch (Channel)
bogdanm	0:9b334a45a8ff	2529	{
bogdanm	0:9b334a45a8ff	2530	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2531	{
bogdanm	0:9b334a45a8ff	2532	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2533	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2534	break;
bogdanm	0:9b334a45a8ff	2535	}
bogdanm	0:9b334a45a8ff	2536	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2537	{
bogdanm	0:9b334a45a8ff	2538	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2539	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2540	break;
bogdanm	0:9b334a45a8ff	2541	}
bogdanm	0:9b334a45a8ff	2542	default :
bogdanm	0:9b334a45a8ff	2543	{
bogdanm	0:9b334a45a8ff	2544	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2545	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2546	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2547	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2548	break;
bogdanm	0:9b334a45a8ff	2549	}
bogdanm	0:9b334a45a8ff	2550	}
bogdanm	0:9b334a45a8ff	2551
bogdanm	0:9b334a45a8ff	2552	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2553	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2554
bogdanm	0:9b334a45a8ff	2555	/* Return function status */
bogdanm	0:9b334a45a8ff	2556	return HAL_OK;
bogdanm	0:9b334a45a8ff	2557	}
bogdanm	0:9b334a45a8ff	2558
bogdanm	0:9b334a45a8ff	2559	/**
bogdanm	0:9b334a45a8ff	2560	* @brief Stops the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2561	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2562	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2563	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	2564	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2565	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2566	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2567	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2568	* @retval HAL status
bogdanm	0:9b334a45a8ff	2569	*/
bogdanm	0:9b334a45a8ff	2570	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2571	{
bogdanm	0:9b334a45a8ff	2572	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2573	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2574
bogdanm	0:9b334a45a8ff	2575	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2576	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2577	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2578	{
bogdanm	0:9b334a45a8ff	2579	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2580
bogdanm	0:9b334a45a8ff	2581	/* Disable the capture compare Interrupts 1 */
bogdanm	0:9b334a45a8ff	2582	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2583	}
bogdanm	0:9b334a45a8ff	2584	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2585	{
bogdanm	0:9b334a45a8ff	2586	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2587
bogdanm	0:9b334a45a8ff	2588	/* Disable the capture compare Interrupts 2 */
bogdanm	0:9b334a45a8ff	2589	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2590	}
bogdanm	0:9b334a45a8ff	2591	else
bogdanm	0:9b334a45a8ff	2592	{
bogdanm	0:9b334a45a8ff	2593	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2594	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2595
bogdanm	0:9b334a45a8ff	2596	/* Disable the capture compare Interrupts 1 and 2 */
bogdanm	0:9b334a45a8ff	2597	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2598	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2599	}
bogdanm	0:9b334a45a8ff	2600
bogdanm	0:9b334a45a8ff	2601	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2602	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2603
bogdanm	0:9b334a45a8ff	2604	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2605	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2606
bogdanm	0:9b334a45a8ff	2607	/* Return function status */
bogdanm	0:9b334a45a8ff	2608	return HAL_OK;
bogdanm	0:9b334a45a8ff	2609	}
bogdanm	0:9b334a45a8ff	2610
bogdanm	0:9b334a45a8ff	2611	/**
bogdanm	0:9b334a45a8ff	2612	* @brief Starts the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2613	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2614	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2615	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2616	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2617	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2618	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2619	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2620	* @param pData1: The destination Buffer address for IC1.
bogdanm	0:9b334a45a8ff	2621	* @param pData2: The destination Buffer address for IC2.
bogdanm	0:9b334a45a8ff	2622	* @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	2623	* @retval HAL status
bogdanm	0:9b334a45a8ff	2624	*/
bogdanm	0:9b334a45a8ff	2625	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
bogdanm	0:9b334a45a8ff	2626	{
bogdanm	0:9b334a45a8ff	2627	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2628	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2629
bogdanm	0:9b334a45a8ff	2630	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	2631	{
bogdanm	0:9b334a45a8ff	2632	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2633	}
bogdanm	0:9b334a45a8ff	2634	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	2635	{
bogdanm	0:9b334a45a8ff	2636	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
bogdanm	0:9b334a45a8ff	2637	{
bogdanm	0:9b334a45a8ff	2638	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2639	}
bogdanm	0:9b334a45a8ff	2640	else
bogdanm	0:9b334a45a8ff	2641	{
bogdanm	0:9b334a45a8ff	2642	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2643	}
bogdanm	0:9b334a45a8ff	2644	}
bogdanm	0:9b334a45a8ff	2645
bogdanm	0:9b334a45a8ff	2646	switch (Channel)
bogdanm	0:9b334a45a8ff	2647	{
bogdanm	0:9b334a45a8ff	2648	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2649	{
bogdanm	0:9b334a45a8ff	2650	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2651	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2652
bogdanm	0:9b334a45a8ff	2653	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2654	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2655
bogdanm	0:9b334a45a8ff	2656	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2657	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
bogdanm	0:9b334a45a8ff	2658
bogdanm	0:9b334a45a8ff	2659	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2660	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2661
bogdanm	0:9b334a45a8ff	2662	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2663	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2664
bogdanm	0:9b334a45a8ff	2665	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2666	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2667	}
bogdanm	0:9b334a45a8ff	2668	break;
bogdanm	0:9b334a45a8ff	2669
bogdanm	0:9b334a45a8ff	2670	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2671	{
bogdanm	0:9b334a45a8ff	2672	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2673	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2674
bogdanm	0:9b334a45a8ff	2675	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2676	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
bogdanm	0:9b334a45a8ff	2677	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2678	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2679
bogdanm	0:9b334a45a8ff	2680	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2681	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2682
bogdanm	0:9b334a45a8ff	2683	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2684	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2685
bogdanm	0:9b334a45a8ff	2686	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2687	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2688	}
bogdanm	0:9b334a45a8ff	2689	break;
bogdanm	0:9b334a45a8ff	2690
bogdanm	0:9b334a45a8ff	2691	case TIM_CHANNEL_ALL:
bogdanm	0:9b334a45a8ff	2692	{
bogdanm	0:9b334a45a8ff	2693	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2694	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2695
bogdanm	0:9b334a45a8ff	2696	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2697	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2698
bogdanm	0:9b334a45a8ff	2699	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2700	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
bogdanm	0:9b334a45a8ff	2701
bogdanm	0:9b334a45a8ff	2702	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2703	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2704
bogdanm	0:9b334a45a8ff	2705	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2706	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2707
bogdanm	0:9b334a45a8ff	2708	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2709	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2710
bogdanm	0:9b334a45a8ff	2711	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2712	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2713
bogdanm	0:9b334a45a8ff	2714	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2715	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2716	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2717
bogdanm	0:9b334a45a8ff	2718	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2719	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2720	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2721	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2722	}
bogdanm	0:9b334a45a8ff	2723	break;
bogdanm	0:9b334a45a8ff	2724
bogdanm	0:9b334a45a8ff	2725	default:
bogdanm	0:9b334a45a8ff	2726	break;
bogdanm	0:9b334a45a8ff	2727	}
bogdanm	0:9b334a45a8ff	2728	/* Return function status */
bogdanm	0:9b334a45a8ff	2729	return HAL_OK;
bogdanm	0:9b334a45a8ff	2730	}
bogdanm	0:9b334a45a8ff	2731
bogdanm	0:9b334a45a8ff	2732	/**
bogdanm	0:9b334a45a8ff	2733	* @brief Stops the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2734	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2735	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2736	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2737	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2738	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2739	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2740	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2741	* @retval HAL status
bogdanm	0:9b334a45a8ff	2742	*/
bogdanm	0:9b334a45a8ff	2743	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2744	{
bogdanm	0:9b334a45a8ff	2745	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2746	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2747
bogdanm	0:9b334a45a8ff	2748	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2749	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2750	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2751	{
bogdanm	0:9b334a45a8ff	2752	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2753
bogdanm	0:9b334a45a8ff	2754	/* Disable the capture compare DMA Request 1 */
bogdanm	0:9b334a45a8ff	2755	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2756	}
bogdanm	0:9b334a45a8ff	2757	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2758	{
bogdanm	0:9b334a45a8ff	2759	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2760
bogdanm	0:9b334a45a8ff	2761	/* Disable the capture compare DMA Request 2 */
bogdanm	0:9b334a45a8ff	2762	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2763	}
bogdanm	0:9b334a45a8ff	2764	else
bogdanm	0:9b334a45a8ff	2765	{
bogdanm	0:9b334a45a8ff	2766	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2767	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2768
bogdanm	0:9b334a45a8ff	2769	/* Disable the capture compare DMA Request 1 and 2 */
bogdanm	0:9b334a45a8ff	2770	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2771	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2772	}
bogdanm	0:9b334a45a8ff	2773
bogdanm	0:9b334a45a8ff	2774	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2775	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2776
bogdanm	0:9b334a45a8ff	2777	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2778	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2779
bogdanm	0:9b334a45a8ff	2780	/* Return function status */
bogdanm	0:9b334a45a8ff	2781	return HAL_OK;
bogdanm	0:9b334a45a8ff	2782	}
bogdanm	0:9b334a45a8ff	2783
bogdanm	0:9b334a45a8ff	2784	/**
bogdanm	0:9b334a45a8ff	2785	* @}
bogdanm	0:9b334a45a8ff	2786	*/
bogdanm	0:9b334a45a8ff	2787	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
bogdanm	0:9b334a45a8ff	2788	* @brief IRQ handler management
bogdanm	0:9b334a45a8ff	2789	*
bogdanm	0:9b334a45a8ff	2790	@verbatim
bogdanm	0:9b334a45a8ff	2791	==============================================================================
bogdanm	0:9b334a45a8ff	2792	##### IRQ handler management #####
bogdanm	0:9b334a45a8ff	2793	==============================================================================
bogdanm	0:9b334a45a8ff	2794	[..]
bogdanm	0:9b334a45a8ff	2795	This section provides Timer IRQ handler function.
bogdanm	0:9b334a45a8ff	2796
bogdanm	0:9b334a45a8ff	2797	@endverbatim
bogdanm	0:9b334a45a8ff	2798	* @{
bogdanm	0:9b334a45a8ff	2799	*/
bogdanm	0:9b334a45a8ff	2800	/**
bogdanm	0:9b334a45a8ff	2801	* @brief This function handles TIM interrupts requests.
bogdanm	0:9b334a45a8ff	2802	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2803	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2804	* @retval None
bogdanm	0:9b334a45a8ff	2805	*/
bogdanm	0:9b334a45a8ff	2806	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2807	{
bogdanm	0:9b334a45a8ff	2808	/* Capture compare 1 event */
bogdanm	0:9b334a45a8ff	2809	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
bogdanm	0:9b334a45a8ff	2810	{
bogdanm	0:9b334a45a8ff	2811	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
bogdanm	0:9b334a45a8ff	2812	{
bogdanm	0:9b334a45a8ff	2813	{
bogdanm	0:9b334a45a8ff	2814	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2815	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	2816
bogdanm	0:9b334a45a8ff	2817	/* Input capture event */
bogdanm	0:9b334a45a8ff	2818	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
bogdanm	0:9b334a45a8ff	2819	{
bogdanm	0:9b334a45a8ff	2820	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2821	}
bogdanm	0:9b334a45a8ff	2822	/* Output compare event */
bogdanm	0:9b334a45a8ff	2823	else
bogdanm	0:9b334a45a8ff	2824	{
bogdanm	0:9b334a45a8ff	2825	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2826	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2827	}
bogdanm	0:9b334a45a8ff	2828	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2829	}
bogdanm	0:9b334a45a8ff	2830	}
bogdanm	0:9b334a45a8ff	2831	}
bogdanm	0:9b334a45a8ff	2832	/* Capture compare 2 event */
bogdanm	0:9b334a45a8ff	2833	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
bogdanm	0:9b334a45a8ff	2834	{
bogdanm	0:9b334a45a8ff	2835	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
bogdanm	0:9b334a45a8ff	2836	{
bogdanm	0:9b334a45a8ff	2837	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2838	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	2839	/* Input capture event */
bogdanm	0:9b334a45a8ff	2840	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
bogdanm	0:9b334a45a8ff	2841	{
bogdanm	0:9b334a45a8ff	2842	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2843	}
bogdanm	0:9b334a45a8ff	2844	/* Output compare event */
bogdanm	0:9b334a45a8ff	2845	else
bogdanm	0:9b334a45a8ff	2846	{
bogdanm	0:9b334a45a8ff	2847	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2848	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2849	}
bogdanm	0:9b334a45a8ff	2850	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2851	}
bogdanm	0:9b334a45a8ff	2852	}
bogdanm	0:9b334a45a8ff	2853	/* Capture compare 3 event */
bogdanm	0:9b334a45a8ff	2854	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
bogdanm	0:9b334a45a8ff	2855	{
bogdanm	0:9b334a45a8ff	2856	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
bogdanm	0:9b334a45a8ff	2857	{
bogdanm	0:9b334a45a8ff	2858	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	2859	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	2860	/* Input capture event */
bogdanm	0:9b334a45a8ff	2861	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
bogdanm	0:9b334a45a8ff	2862	{
bogdanm	0:9b334a45a8ff	2863	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2864	}
bogdanm	0:9b334a45a8ff	2865	/* Output compare event */
bogdanm	0:9b334a45a8ff	2866	else
bogdanm	0:9b334a45a8ff	2867	{
bogdanm	0:9b334a45a8ff	2868	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2869	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2870	}
bogdanm	0:9b334a45a8ff	2871	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2872	}
bogdanm	0:9b334a45a8ff	2873	}
bogdanm	0:9b334a45a8ff	2874	/* Capture compare 4 event */
bogdanm	0:9b334a45a8ff	2875	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
bogdanm	0:9b334a45a8ff	2876	{
bogdanm	0:9b334a45a8ff	2877	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
bogdanm	0:9b334a45a8ff	2878	{
bogdanm	0:9b334a45a8ff	2879	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	2880	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	2881	/* Input capture event */
bogdanm	0:9b334a45a8ff	2882	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
bogdanm	0:9b334a45a8ff	2883	{
bogdanm	0:9b334a45a8ff	2884	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2885	}
bogdanm	0:9b334a45a8ff	2886	/* Output compare event */
bogdanm	0:9b334a45a8ff	2887	else
bogdanm	0:9b334a45a8ff	2888	{
bogdanm	0:9b334a45a8ff	2889	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2890	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2891	}
bogdanm	0:9b334a45a8ff	2892	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2893	}
bogdanm	0:9b334a45a8ff	2894	}
bogdanm	0:9b334a45a8ff	2895	/* TIM Update event */
bogdanm	0:9b334a45a8ff	2896	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
bogdanm	0:9b334a45a8ff	2897	{
bogdanm	0:9b334a45a8ff	2898	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
bogdanm	0:9b334a45a8ff	2899	{
bogdanm	0:9b334a45a8ff	2900	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	2901	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2902	}
bogdanm	0:9b334a45a8ff	2903	}
bogdanm	0:9b334a45a8ff	2904	/* TIM Break input event */
bogdanm	0:9b334a45a8ff	2905	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
bogdanm	0:9b334a45a8ff	2906	{
bogdanm	0:9b334a45a8ff	2907	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
bogdanm	0:9b334a45a8ff	2908	{
bogdanm	0:9b334a45a8ff	2909	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	2910	HAL_TIMEx_BreakCallback(htim);
bogdanm	0:9b334a45a8ff	2911	}
bogdanm	0:9b334a45a8ff	2912	}
bogdanm	0:9b334a45a8ff	2913
bogdanm	0:9b334a45a8ff	2914	/* TIM Break input event */
bogdanm	0:9b334a45a8ff	2915	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
bogdanm	0:9b334a45a8ff	2916	{
bogdanm	0:9b334a45a8ff	2917	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
bogdanm	0:9b334a45a8ff	2918	{
bogdanm	0:9b334a45a8ff	2919	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	2920	HAL_TIMEx_BreakCallback(htim);
bogdanm	0:9b334a45a8ff	2921	}
bogdanm	0:9b334a45a8ff	2922	}
bogdanm	0:9b334a45a8ff	2923
bogdanm	0:9b334a45a8ff	2924	/* TIM Trigger detection event */
bogdanm	0:9b334a45a8ff	2925	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
bogdanm	0:9b334a45a8ff	2926	{
bogdanm	0:9b334a45a8ff	2927	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
bogdanm	0:9b334a45a8ff	2928	{
bogdanm	0:9b334a45a8ff	2929	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	2930	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	2931	}
bogdanm	0:9b334a45a8ff	2932	}
bogdanm	0:9b334a45a8ff	2933	/* TIM commutation event */
bogdanm	0:9b334a45a8ff	2934	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
bogdanm	0:9b334a45a8ff	2935	{
bogdanm	0:9b334a45a8ff	2936	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
bogdanm	0:9b334a45a8ff	2937	{
bogdanm	0:9b334a45a8ff	2938	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
bogdanm	0:9b334a45a8ff	2939	HAL_TIMEx_CommutationCallback(htim);
bogdanm	0:9b334a45a8ff	2940	}
bogdanm	0:9b334a45a8ff	2941	}
bogdanm	0:9b334a45a8ff	2942	}
bogdanm	0:9b334a45a8ff	2943
bogdanm	0:9b334a45a8ff	2944	/**
bogdanm	0:9b334a45a8ff	2945	* @}
bogdanm	0:9b334a45a8ff	2946	*/
bogdanm	0:9b334a45a8ff	2947
bogdanm	0:9b334a45a8ff	2948	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
bogdanm	0:9b334a45a8ff	2949	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	2950	*
bogdanm	0:9b334a45a8ff	2951	@verbatim
bogdanm	0:9b334a45a8ff	2952	==============================================================================
bogdanm	0:9b334a45a8ff	2953	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	2954	==============================================================================
bogdanm	0:9b334a45a8ff	2955	[..]
bogdanm	0:9b334a45a8ff	2956	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2957	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
bogdanm	0:9b334a45a8ff	2958	(+) Configure External Clock source.
bogdanm	0:9b334a45a8ff	2959	(+) Configure Complementary channels, break features and dead time.
bogdanm	0:9b334a45a8ff	2960	(+) Configure Master and the Slave synchronization.
bogdanm	0:9b334a45a8ff	2961	(+) Configure the DMA Burst Mode.
bogdanm	0:9b334a45a8ff	2962
bogdanm	0:9b334a45a8ff	2963	@endverbatim
bogdanm	0:9b334a45a8ff	2964	* @{
bogdanm	0:9b334a45a8ff	2965	*/
bogdanm	0:9b334a45a8ff	2966
bogdanm	0:9b334a45a8ff	2967	/**
bogdanm	0:9b334a45a8ff	2968	* @brief Initializes the TIM Output Compare Channels according to the specified
bogdanm	0:9b334a45a8ff	2969	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	2970	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2971	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2972	* @param sConfig: TIM Output Compare configuration structure
bogdanm	0:9b334a45a8ff	2973	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2974	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2975	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2976	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2977	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	2978	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	2979	* @retval HAL status
bogdanm	0:9b334a45a8ff	2980	*/
bogdanm	0:9b334a45a8ff	2981	__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2982	{
bogdanm	0:9b334a45a8ff	2983	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2984	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	2985	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	2986	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	2987
bogdanm	0:9b334a45a8ff	2988	/* Check input state */
bogdanm	0:9b334a45a8ff	2989	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2990
bogdanm	0:9b334a45a8ff	2991	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2992
bogdanm	0:9b334a45a8ff	2993	switch (Channel)
bogdanm	0:9b334a45a8ff	2994	{
bogdanm	0:9b334a45a8ff	2995	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2996	{
bogdanm	0:9b334a45a8ff	2997	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2998	/* Configure the TIM Channel 1 in Output Compare */
bogdanm	0:9b334a45a8ff	2999	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3000	}
bogdanm	0:9b334a45a8ff	3001	break;
bogdanm	0:9b334a45a8ff	3002
bogdanm	0:9b334a45a8ff	3003	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3004	{
bogdanm	0:9b334a45a8ff	3005	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3006	/* Configure the TIM Channel 2 in Output Compare */
bogdanm	0:9b334a45a8ff	3007	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3008	}
bogdanm	0:9b334a45a8ff	3009	break;
bogdanm	0:9b334a45a8ff	3010
bogdanm	0:9b334a45a8ff	3011	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3012	{
bogdanm	0:9b334a45a8ff	3013	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3014	/* Configure the TIM Channel 3 in Output Compare */
bogdanm	0:9b334a45a8ff	3015	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3016	}
bogdanm	0:9b334a45a8ff	3017	break;
bogdanm	0:9b334a45a8ff	3018
bogdanm	0:9b334a45a8ff	3019	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3020	{
bogdanm	0:9b334a45a8ff	3021	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3022	/* Configure the TIM Channel 4 in Output Compare */
bogdanm	0:9b334a45a8ff	3023	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3024	}
bogdanm	0:9b334a45a8ff	3025	break;
bogdanm	0:9b334a45a8ff	3026
bogdanm	0:9b334a45a8ff	3027	default:
bogdanm	0:9b334a45a8ff	3028	break;
bogdanm	0:9b334a45a8ff	3029	}
bogdanm	0:9b334a45a8ff	3030	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3031
bogdanm	0:9b334a45a8ff	3032	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3033
bogdanm	0:9b334a45a8ff	3034	return HAL_OK;
bogdanm	0:9b334a45a8ff	3035	}
bogdanm	0:9b334a45a8ff	3036
bogdanm	0:9b334a45a8ff	3037	/**
bogdanm	0:9b334a45a8ff	3038	* @brief Initializes the TIM Input Capture Channels according to the specified
bogdanm	0:9b334a45a8ff	3039	* parameters in the TIM_IC_InitTypeDef.
bogdanm	0:9b334a45a8ff	3040	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3041	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3042	* @param sConfig: TIM Input Capture configuration structure
bogdanm	0:9b334a45a8ff	3043	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	3044	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3045	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3046	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3047	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	3048	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	3049	* @retval HAL status
bogdanm	0:9b334a45a8ff	3050	*/
bogdanm	0:9b334a45a8ff	3051	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3052	{
bogdanm	0:9b334a45a8ff	3053	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3054	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3055	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
bogdanm	0:9b334a45a8ff	3056	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
bogdanm	0:9b334a45a8ff	3057	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
bogdanm	0:9b334a45a8ff	3058	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
bogdanm	0:9b334a45a8ff	3059
bogdanm	0:9b334a45a8ff	3060	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3061
bogdanm	0:9b334a45a8ff	3062	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3063
bogdanm	0:9b334a45a8ff	3064	if (Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	3065	{
bogdanm	0:9b334a45a8ff	3066	/* TI1 Configuration */
bogdanm	0:9b334a45a8ff	3067	TIM_TI1_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3068	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3069	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3070	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3071
bogdanm	0:9b334a45a8ff	3072	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	3073	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	3074
bogdanm	0:9b334a45a8ff	3075	/* Set the IC1PSC value */
bogdanm	0:9b334a45a8ff	3076	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	3077	}
bogdanm	0:9b334a45a8ff	3078	else if (Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	3079	{
bogdanm	0:9b334a45a8ff	3080	/* TI2 Configuration */
bogdanm	0:9b334a45a8ff	3081	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3082
bogdanm	0:9b334a45a8ff	3083	TIM_TI2_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3084	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3085	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3086	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3087
bogdanm	0:9b334a45a8ff	3088	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	3089	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	3090
bogdanm	0:9b334a45a8ff	3091	/* Set the IC2PSC value */
bogdanm	0:9b334a45a8ff	3092	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	3093	}
bogdanm	0:9b334a45a8ff	3094	else if (Channel == TIM_CHANNEL_3)
bogdanm	0:9b334a45a8ff	3095	{
bogdanm	0:9b334a45a8ff	3096	/* TI3 Configuration */
bogdanm	0:9b334a45a8ff	3097	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3098
bogdanm	0:9b334a45a8ff	3099	TIM_TI3_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3100	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3101	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3102	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3103
bogdanm	0:9b334a45a8ff	3104	/* Reset the IC3PSC Bits */
bogdanm	0:9b334a45a8ff	3105	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
bogdanm	0:9b334a45a8ff	3106
bogdanm	0:9b334a45a8ff	3107	/* Set the IC3PSC value */
bogdanm	0:9b334a45a8ff	3108	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	3109	}
bogdanm	0:9b334a45a8ff	3110	else
bogdanm	0:9b334a45a8ff	3111	{
bogdanm	0:9b334a45a8ff	3112	/* TI4 Configuration */
bogdanm	0:9b334a45a8ff	3113	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3114
bogdanm	0:9b334a45a8ff	3115	TIM_TI4_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3116	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3117	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3118	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3119
bogdanm	0:9b334a45a8ff	3120	/* Reset the IC4PSC Bits */
bogdanm	0:9b334a45a8ff	3121	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
bogdanm	0:9b334a45a8ff	3122
bogdanm	0:9b334a45a8ff	3123	/* Set the IC4PSC value */
bogdanm	0:9b334a45a8ff	3124	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	3125	}
bogdanm	0:9b334a45a8ff	3126
bogdanm	0:9b334a45a8ff	3127	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3128
bogdanm	0:9b334a45a8ff	3129	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3130
bogdanm	0:9b334a45a8ff	3131	return HAL_OK;
bogdanm	0:9b334a45a8ff	3132	}
bogdanm	0:9b334a45a8ff	3133
bogdanm	0:9b334a45a8ff	3134	/**
bogdanm	0:9b334a45a8ff	3135	* @brief Initializes the TIM PWM channels according to the specified
bogdanm	0:9b334a45a8ff	3136	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	3137	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3138	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3139	* @param sConfig: TIM PWM configuration structure
bogdanm	0:9b334a45a8ff	3140	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	3141	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3142	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3143	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3144	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	3145	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	3146	* @retval HAL status
bogdanm	0:9b334a45a8ff	3147	*/
bogdanm	0:9b334a45a8ff	3148	__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3149	{
bogdanm	0:9b334a45a8ff	3150	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3151
bogdanm	0:9b334a45a8ff	3152	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3153	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	3154	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	3155	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	3156	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
bogdanm	0:9b334a45a8ff	3157
bogdanm	0:9b334a45a8ff	3158	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3159
bogdanm	0:9b334a45a8ff	3160	switch (Channel)
bogdanm	0:9b334a45a8ff	3161	{
bogdanm	0:9b334a45a8ff	3162	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3163	{
bogdanm	0:9b334a45a8ff	3164	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3165	/* Configure the Channel 1 in PWM mode */
bogdanm	0:9b334a45a8ff	3166	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3167
bogdanm	0:9b334a45a8ff	3168	/* Set the Preload enable bit for channel1 */
bogdanm	0:9b334a45a8ff	3169	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
bogdanm	0:9b334a45a8ff	3170
bogdanm	0:9b334a45a8ff	3171	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3172	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
bogdanm	0:9b334a45a8ff	3173	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3174	}
bogdanm	0:9b334a45a8ff	3175	break;
bogdanm	0:9b334a45a8ff	3176
bogdanm	0:9b334a45a8ff	3177	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3178	{
bogdanm	0:9b334a45a8ff	3179	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3180	/* Configure the Channel 2 in PWM mode */
bogdanm	0:9b334a45a8ff	3181	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3182
bogdanm	0:9b334a45a8ff	3183	/* Set the Preload enable bit for channel2 */
bogdanm	0:9b334a45a8ff	3184	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
bogdanm	0:9b334a45a8ff	3185
bogdanm	0:9b334a45a8ff	3186	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3187	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
bogdanm	0:9b334a45a8ff	3188	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3189	}
bogdanm	0:9b334a45a8ff	3190	break;
bogdanm	0:9b334a45a8ff	3191
bogdanm	0:9b334a45a8ff	3192	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3193	{
bogdanm	0:9b334a45a8ff	3194	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3195	/* Configure the Channel 3 in PWM mode */
bogdanm	0:9b334a45a8ff	3196	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3197
bogdanm	0:9b334a45a8ff	3198	/* Set the Preload enable bit for channel3 */
bogdanm	0:9b334a45a8ff	3199	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
bogdanm	0:9b334a45a8ff	3200
bogdanm	0:9b334a45a8ff	3201	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3202	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
bogdanm	0:9b334a45a8ff	3203	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3204	}
bogdanm	0:9b334a45a8ff	3205	break;
bogdanm	0:9b334a45a8ff	3206
bogdanm	0:9b334a45a8ff	3207	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3208	{
bogdanm	0:9b334a45a8ff	3209	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3210	/* Configure the Channel 4 in PWM mode */
bogdanm	0:9b334a45a8ff	3211	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3212
bogdanm	0:9b334a45a8ff	3213	/* Set the Preload enable bit for channel4 */
bogdanm	0:9b334a45a8ff	3214	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
bogdanm	0:9b334a45a8ff	3215
bogdanm	0:9b334a45a8ff	3216	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3217	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
bogdanm	0:9b334a45a8ff	3218	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3219	}
bogdanm	0:9b334a45a8ff	3220	break;
bogdanm	0:9b334a45a8ff	3221
bogdanm	0:9b334a45a8ff	3222	default:
bogdanm	0:9b334a45a8ff	3223	break;
bogdanm	0:9b334a45a8ff	3224	}
bogdanm	0:9b334a45a8ff	3225
bogdanm	0:9b334a45a8ff	3226	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3227
bogdanm	0:9b334a45a8ff	3228	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3229
bogdanm	0:9b334a45a8ff	3230	return HAL_OK;
bogdanm	0:9b334a45a8ff	3231	}
bogdanm	0:9b334a45a8ff	3232
bogdanm	0:9b334a45a8ff	3233	/**
bogdanm	0:9b334a45a8ff	3234	* @brief Initializes the TIM One Pulse Channels according to the specified
bogdanm	0:9b334a45a8ff	3235	* parameters in the TIM_OnePulse_InitTypeDef.
bogdanm	0:9b334a45a8ff	3236	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3237	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3238	* @param sConfig: TIM One Pulse configuration structure
bogdanm	0:9b334a45a8ff	3239	* @param OutputChannel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	3240	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3241	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3242	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3243	* @param InputChannel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	3244	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3245	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3246	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3247	* @retval HAL status
bogdanm	0:9b334a45a8ff	3248	*/
bogdanm	0:9b334a45a8ff	3249	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
bogdanm	0:9b334a45a8ff	3250	{
bogdanm	0:9b334a45a8ff	3251	TIM_OC_InitTypeDef temp1;
bogdanm	0:9b334a45a8ff	3252
bogdanm	0:9b334a45a8ff	3253	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3254	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
bogdanm	0:9b334a45a8ff	3255	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
bogdanm	0:9b334a45a8ff	3256
bogdanm	0:9b334a45a8ff	3257	if(OutputChannel != InputChannel)
bogdanm	0:9b334a45a8ff	3258	{
bogdanm	0:9b334a45a8ff	3259	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3260
bogdanm	0:9b334a45a8ff	3261	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3262
bogdanm	0:9b334a45a8ff	3263	/* Extract the Output compare configuration from sConfig structure */
bogdanm	0:9b334a45a8ff	3264	temp1.OCMode = sConfig->OCMode;
bogdanm	0:9b334a45a8ff	3265	temp1.Pulse = sConfig->Pulse;
bogdanm	0:9b334a45a8ff	3266	temp1.OCPolarity = sConfig->OCPolarity;
bogdanm	0:9b334a45a8ff	3267	temp1.OCNPolarity = sConfig->OCNPolarity;
bogdanm	0:9b334a45a8ff	3268	temp1.OCIdleState = sConfig->OCIdleState;
bogdanm	0:9b334a45a8ff	3269	temp1.OCNIdleState = sConfig->OCNIdleState;
bogdanm	0:9b334a45a8ff	3270
bogdanm	0:9b334a45a8ff	3271	switch (OutputChannel)
bogdanm	0:9b334a45a8ff	3272	{
bogdanm	0:9b334a45a8ff	3273	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3274	{
bogdanm	0:9b334a45a8ff	3275	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3276
bogdanm	0:9b334a45a8ff	3277	TIM_OC1_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3278	}
bogdanm	0:9b334a45a8ff	3279	break;
bogdanm	0:9b334a45a8ff	3280	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3281	{
bogdanm	0:9b334a45a8ff	3282	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3283
bogdanm	0:9b334a45a8ff	3284	TIM_OC2_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3285	}
bogdanm	0:9b334a45a8ff	3286	break;
bogdanm	0:9b334a45a8ff	3287	default:
bogdanm	0:9b334a45a8ff	3288	break;
bogdanm	0:9b334a45a8ff	3289	}
bogdanm	0:9b334a45a8ff	3290	switch (InputChannel)
bogdanm	0:9b334a45a8ff	3291	{
bogdanm	0:9b334a45a8ff	3292	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3293	{
bogdanm	0:9b334a45a8ff	3294	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3295
bogdanm	0:9b334a45a8ff	3296	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3297	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3298
bogdanm	0:9b334a45a8ff	3299	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	3300	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	3301
bogdanm	0:9b334a45a8ff	3302	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3303	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3304	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
bogdanm	0:9b334a45a8ff	3305
bogdanm	0:9b334a45a8ff	3306	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3307	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3308	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3309	}
bogdanm	0:9b334a45a8ff	3310	break;
bogdanm	0:9b334a45a8ff	3311	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3312	{
bogdanm	0:9b334a45a8ff	3313	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3314
bogdanm	0:9b334a45a8ff	3315	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3316	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3317
bogdanm	0:9b334a45a8ff	3318	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	3319	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	3320
bogdanm	0:9b334a45a8ff	3321	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3322	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3323	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
bogdanm	0:9b334a45a8ff	3324
bogdanm	0:9b334a45a8ff	3325	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3326	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3327	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3328	}
bogdanm	0:9b334a45a8ff	3329	break;
bogdanm	0:9b334a45a8ff	3330
bogdanm	0:9b334a45a8ff	3331	default:
bogdanm	0:9b334a45a8ff	3332	break;
bogdanm	0:9b334a45a8ff	3333	}
bogdanm	0:9b334a45a8ff	3334
bogdanm	0:9b334a45a8ff	3335	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3336
bogdanm	0:9b334a45a8ff	3337	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3338
bogdanm	0:9b334a45a8ff	3339	return HAL_OK;
bogdanm	0:9b334a45a8ff	3340	}
bogdanm	0:9b334a45a8ff	3341	else
bogdanm	0:9b334a45a8ff	3342	{
bogdanm	0:9b334a45a8ff	3343	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3344	}
bogdanm	0:9b334a45a8ff	3345	}
bogdanm	0:9b334a45a8ff	3346
bogdanm	0:9b334a45a8ff	3347	/**
bogdanm	0:9b334a45a8ff	3348	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
bogdanm	0:9b334a45a8ff	3349	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3350	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3351	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
bogdanm	0:9b334a45a8ff	3352	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3353	* @arg TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	3354	* @arg TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	3355	* @arg TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	3356	* @arg TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	3357	* @arg TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	3358	* @arg TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	3359	* @arg TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	3360	* @arg TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	3361	* @arg TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	3362	* @arg TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	3363	* @arg TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	3364	* @arg TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	3365	* @arg TIM_DMABASE_RCR
bogdanm	0:9b334a45a8ff	3366	* @arg TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	3367	* @arg TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	3368	* @arg TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	3369	* @arg TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	3370	* @arg TIM_DMABASE_BDTR
bogdanm	0:9b334a45a8ff	3371	* @arg TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	3372	* @param BurstRequestSrc: TIM DMA Request sources.
bogdanm	0:9b334a45a8ff	3373	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3374	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3375	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3376	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3377	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3378	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3379	* @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm	0:9b334a45a8ff	3380	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3381	* @param BurstBuffer: The Buffer address.
bogdanm	0:9b334a45a8ff	3382	* @param BurstLength: DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3383	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
bogdanm	0:9b334a45a8ff	3384	* @retval HAL status
bogdanm	0:9b334a45a8ff	3385	*/
bogdanm	0:9b334a45a8ff	3386	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3387	uint32_t* BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3388	{
bogdanm	0:9b334a45a8ff	3389	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3390	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3391	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3392	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3393	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3394
bogdanm	0:9b334a45a8ff	3395	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3396	{
bogdanm	0:9b334a45a8ff	3397	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3398	}
bogdanm	0:9b334a45a8ff	3399	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3400	{
bogdanm	0:9b334a45a8ff	3401	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3402	{
bogdanm	0:9b334a45a8ff	3403	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3404	}
bogdanm	0:9b334a45a8ff	3405	else
bogdanm	0:9b334a45a8ff	3406	{
bogdanm	0:9b334a45a8ff	3407	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3408	}
bogdanm	0:9b334a45a8ff	3409	}
bogdanm	0:9b334a45a8ff	3410	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3411	{
bogdanm	0:9b334a45a8ff	3412	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3413	{
bogdanm	0:9b334a45a8ff	3414	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3415	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3416
bogdanm	0:9b334a45a8ff	3417	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3418	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3419
bogdanm	0:9b334a45a8ff	3420	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3421	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3422	}
bogdanm	0:9b334a45a8ff	3423	break;
bogdanm	0:9b334a45a8ff	3424	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3425	{
bogdanm	0:9b334a45a8ff	3426	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3427	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3428
bogdanm	0:9b334a45a8ff	3429	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3430	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3431
bogdanm	0:9b334a45a8ff	3432	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3433	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3434	}
bogdanm	0:9b334a45a8ff	3435	break;
bogdanm	0:9b334a45a8ff	3436	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3437	{
bogdanm	0:9b334a45a8ff	3438	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3439	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3440
bogdanm	0:9b334a45a8ff	3441	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3442	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3443
bogdanm	0:9b334a45a8ff	3444	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3445	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3446	}
bogdanm	0:9b334a45a8ff	3447	break;
bogdanm	0:9b334a45a8ff	3448	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3449	{
bogdanm	0:9b334a45a8ff	3450	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3451	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3452
bogdanm	0:9b334a45a8ff	3453	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3454	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3455
bogdanm	0:9b334a45a8ff	3456	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3457	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3458	}
bogdanm	0:9b334a45a8ff	3459	break;
bogdanm	0:9b334a45a8ff	3460	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3461	{
bogdanm	0:9b334a45a8ff	3462	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3463	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3464
bogdanm	0:9b334a45a8ff	3465	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3466	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3467
bogdanm	0:9b334a45a8ff	3468	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3469	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3470	}
bogdanm	0:9b334a45a8ff	3471	break;
bogdanm	0:9b334a45a8ff	3472	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3473	{
bogdanm	0:9b334a45a8ff	3474	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3475	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	3476
bogdanm	0:9b334a45a8ff	3477	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3478	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3479
bogdanm	0:9b334a45a8ff	3480	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3481	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3482	}
bogdanm	0:9b334a45a8ff	3483	break;
bogdanm	0:9b334a45a8ff	3484	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3485	{
bogdanm	0:9b334a45a8ff	3486	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3487	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3488
bogdanm	0:9b334a45a8ff	3489	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3490	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3491
bogdanm	0:9b334a45a8ff	3492	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3493	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3494	}
bogdanm	0:9b334a45a8ff	3495	break;
bogdanm	0:9b334a45a8ff	3496	default:
bogdanm	0:9b334a45a8ff	3497	break;
bogdanm	0:9b334a45a8ff	3498	}
bogdanm	0:9b334a45a8ff	3499	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3500	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3501
bogdanm	0:9b334a45a8ff	3502	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3503	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3504
bogdanm	0:9b334a45a8ff	3505	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3506
bogdanm	0:9b334a45a8ff	3507	/* Return function status */
bogdanm	0:9b334a45a8ff	3508	return HAL_OK;
bogdanm	0:9b334a45a8ff	3509	}
bogdanm	0:9b334a45a8ff	3510
bogdanm	0:9b334a45a8ff	3511	/**
bogdanm	0:9b334a45a8ff	3512	* @brief Stops the TIM DMA Burst mode
bogdanm	0:9b334a45a8ff	3513	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3514	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3515	* @param BurstRequestSrc: TIM DMA Request sources to disable
bogdanm	0:9b334a45a8ff	3516	* @retval HAL status
bogdanm	0:9b334a45a8ff	3517	*/
bogdanm	0:9b334a45a8ff	3518	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3519	{
bogdanm	0:9b334a45a8ff	3520	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3521	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3522
bogdanm	0:9b334a45a8ff	3523	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3524	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3525	{
bogdanm	0:9b334a45a8ff	3526	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3527	{
bogdanm	0:9b334a45a8ff	3528	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3529	}
bogdanm	0:9b334a45a8ff	3530	break;
bogdanm	0:9b334a45a8ff	3531	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3532	{
bogdanm	0:9b334a45a8ff	3533	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3534	}
bogdanm	0:9b334a45a8ff	3535	break;
bogdanm	0:9b334a45a8ff	3536	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3537	{
bogdanm	0:9b334a45a8ff	3538	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3539	}
bogdanm	0:9b334a45a8ff	3540	break;
bogdanm	0:9b334a45a8ff	3541	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3542	{
bogdanm	0:9b334a45a8ff	3543	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3544	}
bogdanm	0:9b334a45a8ff	3545	break;
bogdanm	0:9b334a45a8ff	3546	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3547	{
bogdanm	0:9b334a45a8ff	3548	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3549	}
bogdanm	0:9b334a45a8ff	3550	break;
bogdanm	0:9b334a45a8ff	3551	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3552	{
bogdanm	0:9b334a45a8ff	3553	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm	0:9b334a45a8ff	3554	}
bogdanm	0:9b334a45a8ff	3555	break;
bogdanm	0:9b334a45a8ff	3556	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3557	{
bogdanm	0:9b334a45a8ff	3558	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3559	}
bogdanm	0:9b334a45a8ff	3560	break;
bogdanm	0:9b334a45a8ff	3561	default:
bogdanm	0:9b334a45a8ff	3562	break;
bogdanm	0:9b334a45a8ff	3563	}
bogdanm	0:9b334a45a8ff	3564
bogdanm	0:9b334a45a8ff	3565	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3566	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3567
bogdanm	0:9b334a45a8ff	3568	/* Return function status */
bogdanm	0:9b334a45a8ff	3569	return HAL_OK;
bogdanm	0:9b334a45a8ff	3570	}
bogdanm	0:9b334a45a8ff	3571
bogdanm	0:9b334a45a8ff	3572	/**
bogdanm	0:9b334a45a8ff	3573	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
bogdanm	0:9b334a45a8ff	3574	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3575	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3576	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
bogdanm	0:9b334a45a8ff	3577	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3578	* @arg TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	3579	* @arg TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	3580	* @arg TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	3581	* @arg TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	3582	* @arg TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	3583	* @arg TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	3584	* @arg TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	3585	* @arg TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	3586	* @arg TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	3587	* @arg TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	3588	* @arg TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	3589	* @arg TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	3590	* @arg TIM_DMABASE_RCR
bogdanm	0:9b334a45a8ff	3591	* @arg TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	3592	* @arg TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	3593	* @arg TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	3594	* @arg TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	3595	* @arg TIM_DMABASE_BDTR
bogdanm	0:9b334a45a8ff	3596	* @arg TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	3597	* @param BurstRequestSrc: TIM DMA Request sources.
bogdanm	0:9b334a45a8ff	3598	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3599	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3600	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3601	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3602	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3603	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3604	* @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm	0:9b334a45a8ff	3605	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3606	* @param BurstBuffer: The Buffer address.
bogdanm	0:9b334a45a8ff	3607	* @param BurstLength: DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3608	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
bogdanm	0:9b334a45a8ff	3609	* @retval HAL status
bogdanm	0:9b334a45a8ff	3610	*/
bogdanm	0:9b334a45a8ff	3611	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3612	uint32_t *BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3613	{
bogdanm	0:9b334a45a8ff	3614	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3615	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3616	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3617	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3618	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3619
bogdanm	0:9b334a45a8ff	3620	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3621	{
bogdanm	0:9b334a45a8ff	3622	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3623	}
bogdanm	0:9b334a45a8ff	3624	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3625	{
bogdanm	0:9b334a45a8ff	3626	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3627	{
bogdanm	0:9b334a45a8ff	3628	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3629	}
bogdanm	0:9b334a45a8ff	3630	else
bogdanm	0:9b334a45a8ff	3631	{
bogdanm	0:9b334a45a8ff	3632	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3633	}
bogdanm	0:9b334a45a8ff	3634	}
bogdanm	0:9b334a45a8ff	3635	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3636	{
bogdanm	0:9b334a45a8ff	3637	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3638	{
bogdanm	0:9b334a45a8ff	3639	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3640	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3641
bogdanm	0:9b334a45a8ff	3642	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3643	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3644
bogdanm	0:9b334a45a8ff	3645	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3646	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3647	}
bogdanm	0:9b334a45a8ff	3648	break;
bogdanm	0:9b334a45a8ff	3649	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3650	{
bogdanm	0:9b334a45a8ff	3651	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3652	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3653
bogdanm	0:9b334a45a8ff	3654	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3655	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3656
bogdanm	0:9b334a45a8ff	3657	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3658	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3659	}
bogdanm	0:9b334a45a8ff	3660	break;
bogdanm	0:9b334a45a8ff	3661	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3662	{
bogdanm	0:9b334a45a8ff	3663	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3664	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3665
bogdanm	0:9b334a45a8ff	3666	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3667	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3668
bogdanm	0:9b334a45a8ff	3669	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3670	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3671	}
bogdanm	0:9b334a45a8ff	3672	break;
bogdanm	0:9b334a45a8ff	3673	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3674	{
bogdanm	0:9b334a45a8ff	3675	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3676	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3677
bogdanm	0:9b334a45a8ff	3678	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3679	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3680
bogdanm	0:9b334a45a8ff	3681	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3682	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3683	}
bogdanm	0:9b334a45a8ff	3684	break;
bogdanm	0:9b334a45a8ff	3685	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3686	{
bogdanm	0:9b334a45a8ff	3687	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3688	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3689
bogdanm	0:9b334a45a8ff	3690	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3691	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3692
bogdanm	0:9b334a45a8ff	3693	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3694	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3695	}
bogdanm	0:9b334a45a8ff	3696	break;
bogdanm	0:9b334a45a8ff	3697	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3698	{
bogdanm	0:9b334a45a8ff	3699	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3700	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	3701
bogdanm	0:9b334a45a8ff	3702	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3703	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3704
bogdanm	0:9b334a45a8ff	3705	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3706	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3707	}
bogdanm	0:9b334a45a8ff	3708	break;
bogdanm	0:9b334a45a8ff	3709	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3710	{
bogdanm	0:9b334a45a8ff	3711	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3712	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3713
bogdanm	0:9b334a45a8ff	3714	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3715	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3716
bogdanm	0:9b334a45a8ff	3717	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3718	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3719	}
bogdanm	0:9b334a45a8ff	3720	break;
bogdanm	0:9b334a45a8ff	3721	default:
bogdanm	0:9b334a45a8ff	3722	break;
bogdanm	0:9b334a45a8ff	3723	}
bogdanm	0:9b334a45a8ff	3724
bogdanm	0:9b334a45a8ff	3725	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3726	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3727
bogdanm	0:9b334a45a8ff	3728	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3729	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3730
bogdanm	0:9b334a45a8ff	3731	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3732
bogdanm	0:9b334a45a8ff	3733	/* Return function status */
bogdanm	0:9b334a45a8ff	3734	return HAL_OK;
bogdanm	0:9b334a45a8ff	3735	}
bogdanm	0:9b334a45a8ff	3736
bogdanm	0:9b334a45a8ff	3737	/**
bogdanm	0:9b334a45a8ff	3738	* @brief Stop the DMA burst reading
bogdanm	0:9b334a45a8ff	3739	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3740	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3741	* @param BurstRequestSrc: TIM DMA Request sources to disable.
bogdanm	0:9b334a45a8ff	3742	* @retval HAL status
bogdanm	0:9b334a45a8ff	3743	*/
bogdanm	0:9b334a45a8ff	3744	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3745	{
bogdanm	0:9b334a45a8ff	3746	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3747	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3748
bogdanm	0:9b334a45a8ff	3749	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3750	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3751	{
bogdanm	0:9b334a45a8ff	3752	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3753	{
bogdanm	0:9b334a45a8ff	3754	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3755	}
bogdanm	0:9b334a45a8ff	3756	break;
bogdanm	0:9b334a45a8ff	3757	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3758	{
bogdanm	0:9b334a45a8ff	3759	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3760	}
bogdanm	0:9b334a45a8ff	3761	break;
bogdanm	0:9b334a45a8ff	3762	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3763	{
bogdanm	0:9b334a45a8ff	3764	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3765	}
bogdanm	0:9b334a45a8ff	3766	break;
bogdanm	0:9b334a45a8ff	3767	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3768	{
bogdanm	0:9b334a45a8ff	3769	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3770	}
bogdanm	0:9b334a45a8ff	3771	break;
bogdanm	0:9b334a45a8ff	3772	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3773	{
bogdanm	0:9b334a45a8ff	3774	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3775	}
bogdanm	0:9b334a45a8ff	3776	break;
bogdanm	0:9b334a45a8ff	3777	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3778	{
bogdanm	0:9b334a45a8ff	3779	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm	0:9b334a45a8ff	3780	}
bogdanm	0:9b334a45a8ff	3781	break;
bogdanm	0:9b334a45a8ff	3782	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3783	{
bogdanm	0:9b334a45a8ff	3784	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3785	}
bogdanm	0:9b334a45a8ff	3786	break;
bogdanm	0:9b334a45a8ff	3787	default:
bogdanm	0:9b334a45a8ff	3788	break;
bogdanm	0:9b334a45a8ff	3789	}
bogdanm	0:9b334a45a8ff	3790
bogdanm	0:9b334a45a8ff	3791	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3792	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3793
bogdanm	0:9b334a45a8ff	3794	/* Return function status */
bogdanm	0:9b334a45a8ff	3795	return HAL_OK;
bogdanm	0:9b334a45a8ff	3796	}
bogdanm	0:9b334a45a8ff	3797
bogdanm	0:9b334a45a8ff	3798	/**
bogdanm	0:9b334a45a8ff	3799	* @brief Generate a software event
bogdanm	0:9b334a45a8ff	3800	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3801	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3802	* @param EventSource: specifies the event source.
bogdanm	0:9b334a45a8ff	3803	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3804	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
bogdanm	0:9b334a45a8ff	3805	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
bogdanm	0:9b334a45a8ff	3806	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
bogdanm	0:9b334a45a8ff	3807	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
bogdanm	0:9b334a45a8ff	3808	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
bogdanm	0:9b334a45a8ff	3809	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
bogdanm	0:9b334a45a8ff	3810	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
bogdanm	0:9b334a45a8ff	3811	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
bogdanm	0:9b334a45a8ff	3812	* @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
bogdanm	0:9b334a45a8ff	3813	* @note TIM6 and TIM7 can only generate an update event.
bogdanm	0:9b334a45a8ff	3814	* @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
bogdanm	0:9b334a45a8ff	3815	* @retval HAL status
bogdanm	0:9b334a45a8ff	3816	*/
bogdanm	0:9b334a45a8ff	3817
bogdanm	0:9b334a45a8ff	3818	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
bogdanm	0:9b334a45a8ff	3819	{
bogdanm	0:9b334a45a8ff	3820	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3821	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3822	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
bogdanm	0:9b334a45a8ff	3823
bogdanm	0:9b334a45a8ff	3824	/* Process Locked */
bogdanm	0:9b334a45a8ff	3825	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3826
bogdanm	0:9b334a45a8ff	3827	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3828	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3829
bogdanm	0:9b334a45a8ff	3830	/* Set the event sources */
bogdanm	0:9b334a45a8ff	3831	htim->Instance->EGR = EventSource;
bogdanm	0:9b334a45a8ff	3832
bogdanm	0:9b334a45a8ff	3833	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3834	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3835
bogdanm	0:9b334a45a8ff	3836	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3837
bogdanm	0:9b334a45a8ff	3838	/* Return function status */
bogdanm	0:9b334a45a8ff	3839	return HAL_OK;
bogdanm	0:9b334a45a8ff	3840	}
bogdanm	0:9b334a45a8ff	3841
bogdanm	0:9b334a45a8ff	3842	/**
bogdanm	0:9b334a45a8ff	3843	* @brief Configures the OCRef clear feature
bogdanm	0:9b334a45a8ff	3844	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3845	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3846	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3847	* contains the OCREF clear feature and parameters for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3848	* @param Channel: specifies the TIM Channel.
bogdanm	0:9b334a45a8ff	3849	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3850	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3851	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3852	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	3853	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	3854	* @retval HAL status
bogdanm	0:9b334a45a8ff	3855	*/
bogdanm	0:9b334a45a8ff	3856	__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3857	{
bogdanm	0:9b334a45a8ff	3858	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3859	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3860	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	3861	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
bogdanm	0:9b334a45a8ff	3862
bogdanm	0:9b334a45a8ff	3863	/* Process Locked */
bogdanm	0:9b334a45a8ff	3864	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3865
bogdanm	0:9b334a45a8ff	3866	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3867
bogdanm	0:9b334a45a8ff	3868	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
bogdanm	0:9b334a45a8ff	3869	{
bogdanm	0:9b334a45a8ff	3870	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
bogdanm	0:9b334a45a8ff	3871	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
bogdanm	0:9b334a45a8ff	3872	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
bogdanm	0:9b334a45a8ff	3873
bogdanm	0:9b334a45a8ff	3874	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3875	sClearInputConfig->ClearInputPrescaler,
bogdanm	0:9b334a45a8ff	3876	sClearInputConfig->ClearInputPolarity,
bogdanm	0:9b334a45a8ff	3877	sClearInputConfig->ClearInputFilter);
bogdanm	0:9b334a45a8ff	3878	}
bogdanm	0:9b334a45a8ff	3879
bogdanm	0:9b334a45a8ff	3880	switch (Channel)
bogdanm	0:9b334a45a8ff	3881	{
bogdanm	0:9b334a45a8ff	3882	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3883	{
bogdanm	0:9b334a45a8ff	3884	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3885	{
bogdanm	0:9b334a45a8ff	3886	/* Enable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3887	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3888	}
bogdanm	0:9b334a45a8ff	3889	else
bogdanm	0:9b334a45a8ff	3890	{
bogdanm	0:9b334a45a8ff	3891	/* Disable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3892	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3893	}
bogdanm	0:9b334a45a8ff	3894	}
bogdanm	0:9b334a45a8ff	3895	break;
bogdanm	0:9b334a45a8ff	3896	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3897	{
bogdanm	0:9b334a45a8ff	3898	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3899	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3900	{
bogdanm	0:9b334a45a8ff	3901	/* Enable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3902	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3903	}
bogdanm	0:9b334a45a8ff	3904	else
bogdanm	0:9b334a45a8ff	3905	{
bogdanm	0:9b334a45a8ff	3906	/* Disable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3907	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3908	}
bogdanm	0:9b334a45a8ff	3909	}
bogdanm	0:9b334a45a8ff	3910	break;
bogdanm	0:9b334a45a8ff	3911	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3912	{
bogdanm	0:9b334a45a8ff	3913	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3914	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3915	{
bogdanm	0:9b334a45a8ff	3916	/* Enable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3917	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3918	}
bogdanm	0:9b334a45a8ff	3919	else
bogdanm	0:9b334a45a8ff	3920	{
bogdanm	0:9b334a45a8ff	3921	/* Disable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3922	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3923	}
bogdanm	0:9b334a45a8ff	3924	}
bogdanm	0:9b334a45a8ff	3925	break;
bogdanm	0:9b334a45a8ff	3926	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3927	{
bogdanm	0:9b334a45a8ff	3928	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3929	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3930	{
bogdanm	0:9b334a45a8ff	3931	/* Enable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3932	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3933	}
bogdanm	0:9b334a45a8ff	3934	else
bogdanm	0:9b334a45a8ff	3935	{
bogdanm	0:9b334a45a8ff	3936	/* Disable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3937	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3938	}
bogdanm	0:9b334a45a8ff	3939	}
bogdanm	0:9b334a45a8ff	3940	break;
bogdanm	0:9b334a45a8ff	3941	default:
bogdanm	0:9b334a45a8ff	3942	break;
bogdanm	0:9b334a45a8ff	3943	}
bogdanm	0:9b334a45a8ff	3944
bogdanm	0:9b334a45a8ff	3945	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3946
bogdanm	0:9b334a45a8ff	3947	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3948
bogdanm	0:9b334a45a8ff	3949	return HAL_OK;
bogdanm	0:9b334a45a8ff	3950	}
bogdanm	0:9b334a45a8ff	3951
bogdanm	0:9b334a45a8ff	3952	/**
bogdanm	0:9b334a45a8ff	3953	* @brief Configures the clock source to be used
bogdanm	0:9b334a45a8ff	3954	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3955	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3956	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3957	* contains the clock source information for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3958	* @retval HAL status
bogdanm	0:9b334a45a8ff	3959	*/
bogdanm	0:9b334a45a8ff	3960	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
bogdanm	0:9b334a45a8ff	3961	{
bogdanm	0:9b334a45a8ff	3962	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	3963
bogdanm	0:9b334a45a8ff	3964	/* Process Locked */
bogdanm	0:9b334a45a8ff	3965	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3966
bogdanm	0:9b334a45a8ff	3967	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3968
bogdanm	0:9b334a45a8ff	3969	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3970	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
bogdanm	0:9b334a45a8ff	3971
bogdanm	0:9b334a45a8ff	3972	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
bogdanm	0:9b334a45a8ff	3973	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	3974	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	3975	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	3976	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3977
bogdanm	0:9b334a45a8ff	3978	switch (sClockSourceConfig->ClockSource)
bogdanm	0:9b334a45a8ff	3979	{
bogdanm	0:9b334a45a8ff	3980	case TIM_CLOCKSOURCE_INTERNAL:
bogdanm	0:9b334a45a8ff	3981	{
bogdanm	0:9b334a45a8ff	3982	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3983	/* Disable slave mode to clock the prescaler directly with the internal clock */
bogdanm	0:9b334a45a8ff	3984	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3985	}
bogdanm	0:9b334a45a8ff	3986	break;
bogdanm	0:9b334a45a8ff	3987
bogdanm	0:9b334a45a8ff	3988	case TIM_CLOCKSOURCE_ETRMODE1:
bogdanm	0:9b334a45a8ff	3989	{
bogdanm	0:9b334a45a8ff	3990	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official	83:a036322b8637	3991	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	83:a036322b8637	3992	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official	83:a036322b8637	3993	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
bogdanm	0:9b334a45a8ff	3994	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	3995	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3996	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	3997	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3998	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3999	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	4000	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	4001	/* Reset the SMS and TS Bits */
bogdanm	0:9b334a45a8ff	4002	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	4003	/* Select the External clock mode1 and the ETRF trigger */
bogdanm	0:9b334a45a8ff	4004	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
bogdanm	0:9b334a45a8ff	4005	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	4006	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	4007	}
bogdanm	0:9b334a45a8ff	4008	break;
bogdanm	0:9b334a45a8ff	4009
bogdanm	0:9b334a45a8ff	4010	case TIM_CLOCKSOURCE_ETRMODE2:
bogdanm	0:9b334a45a8ff	4011	{
bogdanm	0:9b334a45a8ff	4012	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official	83:a036322b8637	4013	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	83:a036322b8637	4014	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official	83:a036322b8637	4015	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	83:a036322b8637	4016
bogdanm	0:9b334a45a8ff	4017	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	4018	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	4019	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	4020	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	4021	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	4022	/* Enable the External clock mode2 */
bogdanm	0:9b334a45a8ff	4023	htim->Instance->SMCR \|= TIM_SMCR_ECE;
bogdanm	0:9b334a45a8ff	4024	}
bogdanm	0:9b334a45a8ff	4025	break;
bogdanm	0:9b334a45a8ff	4026
bogdanm	0:9b334a45a8ff	4027	case TIM_CLOCKSOURCE_TI1:
bogdanm	0:9b334a45a8ff	4028	{
bogdanm	0:9b334a45a8ff	4029	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official	83:a036322b8637	4030
mbed_official	83:a036322b8637	4031	/* Check TI1 input conditioning related parameters */
mbed_official	83:a036322b8637	4032	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	83:a036322b8637	4033	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	83:a036322b8637	4034
bogdanm	0:9b334a45a8ff	4035	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4036	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	4037	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	4038	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
bogdanm	0:9b334a45a8ff	4039	}
bogdanm	0:9b334a45a8ff	4040	break;
bogdanm	0:9b334a45a8ff	4041	case TIM_CLOCKSOURCE_TI2:
bogdanm	0:9b334a45a8ff	4042	{
bogdanm	0:9b334a45a8ff	4043	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official	83:a036322b8637	4044
mbed_official	83:a036322b8637	4045	/* Check TI1 input conditioning related parameters */
mbed_official	83:a036322b8637	4046	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	83:a036322b8637	4047	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	83:a036322b8637	4048
bogdanm	0:9b334a45a8ff	4049	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4050	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	4051	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	4052	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
bogdanm	0:9b334a45a8ff	4053	}
bogdanm	0:9b334a45a8ff	4054	break;
bogdanm	0:9b334a45a8ff	4055	case TIM_CLOCKSOURCE_TI1ED:
bogdanm	0:9b334a45a8ff	4056	{
bogdanm	0:9b334a45a8ff	4057	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official	83:a036322b8637	4058	/* Check TI1 input conditioning related parameters */
mbed_official	83:a036322b8637	4059	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	83:a036322b8637	4060	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	83:a036322b8637	4061
bogdanm	0:9b334a45a8ff	4062	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4063	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	4064	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	4065	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
bogdanm	0:9b334a45a8ff	4066	}
bogdanm	0:9b334a45a8ff	4067	break;
bogdanm	0:9b334a45a8ff	4068	case TIM_CLOCKSOURCE_ITR0:
bogdanm	0:9b334a45a8ff	4069	{
bogdanm	0:9b334a45a8ff	4070	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4071	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
bogdanm	0:9b334a45a8ff	4072	}
bogdanm	0:9b334a45a8ff	4073	break;
bogdanm	0:9b334a45a8ff	4074	case TIM_CLOCKSOURCE_ITR1:
bogdanm	0:9b334a45a8ff	4075	{
bogdanm	0:9b334a45a8ff	4076	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4077	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
bogdanm	0:9b334a45a8ff	4078	}
bogdanm	0:9b334a45a8ff	4079	break;
bogdanm	0:9b334a45a8ff	4080	case TIM_CLOCKSOURCE_ITR2:
bogdanm	0:9b334a45a8ff	4081	{
bogdanm	0:9b334a45a8ff	4082	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4083	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
bogdanm	0:9b334a45a8ff	4084	}
bogdanm	0:9b334a45a8ff	4085	break;
bogdanm	0:9b334a45a8ff	4086	case TIM_CLOCKSOURCE_ITR3:
bogdanm	0:9b334a45a8ff	4087	{
bogdanm	0:9b334a45a8ff	4088	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4089	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
bogdanm	0:9b334a45a8ff	4090	}
bogdanm	0:9b334a45a8ff	4091	break;
bogdanm	0:9b334a45a8ff	4092
bogdanm	0:9b334a45a8ff	4093	default:
bogdanm	0:9b334a45a8ff	4094	break;
bogdanm	0:9b334a45a8ff	4095	}
bogdanm	0:9b334a45a8ff	4096	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4097
bogdanm	0:9b334a45a8ff	4098	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4099
bogdanm	0:9b334a45a8ff	4100	return HAL_OK;
bogdanm	0:9b334a45a8ff	4101	}
bogdanm	0:9b334a45a8ff	4102
bogdanm	0:9b334a45a8ff	4103	/**
bogdanm	0:9b334a45a8ff	4104	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
bogdanm	0:9b334a45a8ff	4105	* or a XOR combination between CH1_input, CH2_input & CH3_input
bogdanm	0:9b334a45a8ff	4106	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4107	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4108	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
bogdanm	0:9b334a45a8ff	4109	* output of a XOR gate.
bogdanm	0:9b334a45a8ff	4110	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4111	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
bogdanm	0:9b334a45a8ff	4112	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
bogdanm	0:9b334a45a8ff	4113	* pins are connected to the TI1 input (XOR combination)
bogdanm	0:9b334a45a8ff	4114	* @retval HAL status
bogdanm	0:9b334a45a8ff	4115	*/
bogdanm	0:9b334a45a8ff	4116	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
bogdanm	0:9b334a45a8ff	4117	{
bogdanm	0:9b334a45a8ff	4118	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4119
bogdanm	0:9b334a45a8ff	4120	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4121	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4122	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
bogdanm	0:9b334a45a8ff	4123
bogdanm	0:9b334a45a8ff	4124	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4125	tmpcr2 = htim->Instance->CR2;
bogdanm	0:9b334a45a8ff	4126
bogdanm	0:9b334a45a8ff	4127	/* Reset the TI1 selection */
bogdanm	0:9b334a45a8ff	4128	tmpcr2 &= ~TIM_CR2_TI1S;
bogdanm	0:9b334a45a8ff	4129
bogdanm	0:9b334a45a8ff	4130	/* Set the TI1 selection */
bogdanm	0:9b334a45a8ff	4131	tmpcr2 \|= TI1_Selection;
bogdanm	0:9b334a45a8ff	4132
bogdanm	0:9b334a45a8ff	4133	/* Write to TIMxCR2 */
bogdanm	0:9b334a45a8ff	4134	htim->Instance->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4135
bogdanm	0:9b334a45a8ff	4136	return HAL_OK;
bogdanm	0:9b334a45a8ff	4137	}
bogdanm	0:9b334a45a8ff	4138
bogdanm	0:9b334a45a8ff	4139	/**
bogdanm	0:9b334a45a8ff	4140	* @brief Configures the TIM in Slave mode
bogdanm	0:9b334a45a8ff	4141	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4142	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4143	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	4144	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	4145	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	4146	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	4147	* @retval HAL status
bogdanm	0:9b334a45a8ff	4148	*/
bogdanm	0:9b334a45a8ff	4149	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
bogdanm	0:9b334a45a8ff	4150	{
bogdanm	0:9b334a45a8ff	4151	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	4152	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4153	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4154
bogdanm	0:9b334a45a8ff	4155	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4156	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4157	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm	0:9b334a45a8ff	4158	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm	0:9b334a45a8ff	4159
bogdanm	0:9b334a45a8ff	4160	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4161
bogdanm	0:9b334a45a8ff	4162	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	4163
bogdanm	0:9b334a45a8ff	4164	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	4165	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	4166
bogdanm	0:9b334a45a8ff	4167	/* Reset the Trigger Selection Bits */
bogdanm	0:9b334a45a8ff	4168	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	4169	/* Set the Input Trigger source */
bogdanm	0:9b334a45a8ff	4170	tmpsmcr \|= sSlaveConfig->InputTrigger;
bogdanm	0:9b334a45a8ff	4171
bogdanm	0:9b334a45a8ff	4172	/* Reset the slave mode Bits */
bogdanm	0:9b334a45a8ff	4173	tmpsmcr &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	4174	/* Set the slave mode */
bogdanm	0:9b334a45a8ff	4175	tmpsmcr \|= sSlaveConfig->SlaveMode;
bogdanm	0:9b334a45a8ff	4176
bogdanm	0:9b334a45a8ff	4177	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	4178	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	4179
bogdanm	0:9b334a45a8ff	4180	/* Configure the trigger prescaler, filter, and polarity */
bogdanm	0:9b334a45a8ff	4181	switch (sSlaveConfig->InputTrigger)
bogdanm	0:9b334a45a8ff	4182	{
bogdanm	0:9b334a45a8ff	4183	case TIM_TS_ETRF:
bogdanm	0:9b334a45a8ff	4184	{
bogdanm	0:9b334a45a8ff	4185	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4186	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4187	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
bogdanm	0:9b334a45a8ff	4188	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4189	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4190	/* Configure the ETR Trigger source */
bogdanm	0:9b334a45a8ff	4191	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	4192	sSlaveConfig->TriggerPrescaler,
bogdanm	0:9b334a45a8ff	4193	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4194	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4195	}
bogdanm	0:9b334a45a8ff	4196	break;
bogdanm	0:9b334a45a8ff	4197
bogdanm	0:9b334a45a8ff	4198	case TIM_TS_TI1F_ED:
bogdanm	0:9b334a45a8ff	4199	{
bogdanm	0:9b334a45a8ff	4200	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4201	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4202	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4203
bogdanm	0:9b334a45a8ff	4204	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4205	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	4206	htim->Instance->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4207	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	4208
bogdanm	0:9b334a45a8ff	4209	/* Set the filter */
bogdanm	0:9b334a45a8ff	4210	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	4211	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
bogdanm	0:9b334a45a8ff	4212
bogdanm	0:9b334a45a8ff	4213	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4214	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	4215	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4216
bogdanm	0:9b334a45a8ff	4217	}
bogdanm	0:9b334a45a8ff	4218	break;
bogdanm	0:9b334a45a8ff	4219
bogdanm	0:9b334a45a8ff	4220	case TIM_TS_TI1FP1:
bogdanm	0:9b334a45a8ff	4221	{
bogdanm	0:9b334a45a8ff	4222	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4223	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4224	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4225	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4226
bogdanm	0:9b334a45a8ff	4227	/* Configure TI1 Filter and Polarity */
bogdanm	0:9b334a45a8ff	4228	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4229	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4230	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4231	}
bogdanm	0:9b334a45a8ff	4232	break;
bogdanm	0:9b334a45a8ff	4233
bogdanm	0:9b334a45a8ff	4234	case TIM_TS_TI2FP2:
bogdanm	0:9b334a45a8ff	4235	{
bogdanm	0:9b334a45a8ff	4236	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4237	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4238	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4239	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4240
bogdanm	0:9b334a45a8ff	4241	/* Configure TI2 Filter and Polarity */
bogdanm	0:9b334a45a8ff	4242	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4243	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4244	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4245	}
bogdanm	0:9b334a45a8ff	4246	break;
bogdanm	0:9b334a45a8ff	4247
bogdanm	0:9b334a45a8ff	4248	case TIM_TS_ITR0:
bogdanm	0:9b334a45a8ff	4249	{
bogdanm	0:9b334a45a8ff	4250	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4251	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4252	}
bogdanm	0:9b334a45a8ff	4253	break;
bogdanm	0:9b334a45a8ff	4254
bogdanm	0:9b334a45a8ff	4255	case TIM_TS_ITR1:
bogdanm	0:9b334a45a8ff	4256	{
bogdanm	0:9b334a45a8ff	4257	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4258	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4259	}
bogdanm	0:9b334a45a8ff	4260	break;
bogdanm	0:9b334a45a8ff	4261
bogdanm	0:9b334a45a8ff	4262	case TIM_TS_ITR2:
bogdanm	0:9b334a45a8ff	4263	{
bogdanm	0:9b334a45a8ff	4264	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4265	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4266	}
bogdanm	0:9b334a45a8ff	4267	break;
bogdanm	0:9b334a45a8ff	4268
bogdanm	0:9b334a45a8ff	4269	case TIM_TS_ITR3:
bogdanm	0:9b334a45a8ff	4270	{
bogdanm	0:9b334a45a8ff	4271	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4272	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4273	}
bogdanm	0:9b334a45a8ff	4274	break;
bogdanm	0:9b334a45a8ff	4275
bogdanm	0:9b334a45a8ff	4276	default:
bogdanm	0:9b334a45a8ff	4277	break;
bogdanm	0:9b334a45a8ff	4278	}
bogdanm	0:9b334a45a8ff	4279
bogdanm	0:9b334a45a8ff	4280	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4281
bogdanm	0:9b334a45a8ff	4282	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4283
bogdanm	0:9b334a45a8ff	4284	return HAL_OK;
bogdanm	0:9b334a45a8ff	4285	}
bogdanm	0:9b334a45a8ff	4286
bogdanm	0:9b334a45a8ff	4287	/**
bogdanm	0:9b334a45a8ff	4288	* @brief Configures the TIM in Slave mode in interrupt mode
bogdanm	0:9b334a45a8ff	4289	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	4290	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	4291	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	4292	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	4293	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	4294	* @retval HAL status
bogdanm	0:9b334a45a8ff	4295	*/
bogdanm	0:9b334a45a8ff	4296	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	4297	TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm	0:9b334a45a8ff	4298	{
bogdanm	0:9b334a45a8ff	4299	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4300	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4301	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm	0:9b334a45a8ff	4302	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm	0:9b334a45a8ff	4303
bogdanm	0:9b334a45a8ff	4304	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4305
bogdanm	0:9b334a45a8ff	4306	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	4307
bogdanm	0:9b334a45a8ff	4308	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
bogdanm	0:9b334a45a8ff	4309
bogdanm	0:9b334a45a8ff	4310	/* Enable Trigger Interrupt */
bogdanm	0:9b334a45a8ff	4311	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	4312
bogdanm	0:9b334a45a8ff	4313	/* Disable Trigger DMA request */
bogdanm	0:9b334a45a8ff	4314	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
bogdanm	0:9b334a45a8ff	4315
bogdanm	0:9b334a45a8ff	4316	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4317
bogdanm	0:9b334a45a8ff	4318	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4319
bogdanm	0:9b334a45a8ff	4320	return HAL_OK;
bogdanm	0:9b334a45a8ff	4321	}
bogdanm	0:9b334a45a8ff	4322
bogdanm	0:9b334a45a8ff	4323	/**
bogdanm	0:9b334a45a8ff	4324	* @brief Read the captured value from Capture Compare unit
bogdanm	0:9b334a45a8ff	4325	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4326	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4327	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	4328	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4329	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	4330	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	4331	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	4332	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	4333	* @retval Captured value
bogdanm	0:9b334a45a8ff	4334	*/
bogdanm	0:9b334a45a8ff	4335	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	4336	{
bogdanm	0:9b334a45a8ff	4337	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	4338
bogdanm	0:9b334a45a8ff	4339	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4340
bogdanm	0:9b334a45a8ff	4341	switch (Channel)
bogdanm	0:9b334a45a8ff	4342	{
bogdanm	0:9b334a45a8ff	4343	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	4344	{
bogdanm	0:9b334a45a8ff	4345	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4346	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4347
bogdanm	0:9b334a45a8ff	4348	/* Return the capture 1 value */
bogdanm	0:9b334a45a8ff	4349	tmpreg = htim->Instance->CCR1;
bogdanm	0:9b334a45a8ff	4350
bogdanm	0:9b334a45a8ff	4351	break;
bogdanm	0:9b334a45a8ff	4352	}
bogdanm	0:9b334a45a8ff	4353	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	4354	{
bogdanm	0:9b334a45a8ff	4355	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4356	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4357
bogdanm	0:9b334a45a8ff	4358	/* Return the capture 2 value */
bogdanm	0:9b334a45a8ff	4359	tmpreg = htim->Instance->CCR2;
bogdanm	0:9b334a45a8ff	4360
bogdanm	0:9b334a45a8ff	4361	break;
bogdanm	0:9b334a45a8ff	4362	}
bogdanm	0:9b334a45a8ff	4363
bogdanm	0:9b334a45a8ff	4364	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	4365	{
bogdanm	0:9b334a45a8ff	4366	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4367	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4368
bogdanm	0:9b334a45a8ff	4369	/* Return the capture 3 value */
bogdanm	0:9b334a45a8ff	4370	tmpreg = htim->Instance->CCR3;
bogdanm	0:9b334a45a8ff	4371
bogdanm	0:9b334a45a8ff	4372	break;
bogdanm	0:9b334a45a8ff	4373	}
bogdanm	0:9b334a45a8ff	4374
bogdanm	0:9b334a45a8ff	4375	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	4376	{
bogdanm	0:9b334a45a8ff	4377	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4378	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4379
bogdanm	0:9b334a45a8ff	4380	/* Return the capture 4 value */
bogdanm	0:9b334a45a8ff	4381	tmpreg = htim->Instance->CCR4;
bogdanm	0:9b334a45a8ff	4382
bogdanm	0:9b334a45a8ff	4383	break;
bogdanm	0:9b334a45a8ff	4384	}
bogdanm	0:9b334a45a8ff	4385
bogdanm	0:9b334a45a8ff	4386	default:
bogdanm	0:9b334a45a8ff	4387	break;
bogdanm	0:9b334a45a8ff	4388	}
bogdanm	0:9b334a45a8ff	4389
bogdanm	0:9b334a45a8ff	4390	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4391	return tmpreg;
bogdanm	0:9b334a45a8ff	4392	}
bogdanm	0:9b334a45a8ff	4393
bogdanm	0:9b334a45a8ff	4394	/**
bogdanm	0:9b334a45a8ff	4395	* @}
bogdanm	0:9b334a45a8ff	4396	*/
bogdanm	0:9b334a45a8ff	4397
bogdanm	0:9b334a45a8ff	4398	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
bogdanm	0:9b334a45a8ff	4399	* @brief TIM Callbacks functions
bogdanm	0:9b334a45a8ff	4400	*
bogdanm	0:9b334a45a8ff	4401	@verbatim
bogdanm	0:9b334a45a8ff	4402	==============================================================================
bogdanm	0:9b334a45a8ff	4403	##### TIM Callbacks functions #####
bogdanm	0:9b334a45a8ff	4404	==============================================================================
bogdanm	0:9b334a45a8ff	4405	[..]
bogdanm	0:9b334a45a8ff	4406	This section provides TIM callback functions:
bogdanm	0:9b334a45a8ff	4407	(+) Timer Period elapsed callback
bogdanm	0:9b334a45a8ff	4408	(+) Timer Output Compare callback
bogdanm	0:9b334a45a8ff	4409	(+) Timer Input capture callback
bogdanm	0:9b334a45a8ff	4410	(+) Timer Trigger callback
bogdanm	0:9b334a45a8ff	4411	(+) Timer Error callback
bogdanm	0:9b334a45a8ff	4412
bogdanm	0:9b334a45a8ff	4413	@endverbatim
bogdanm	0:9b334a45a8ff	4414	* @{
bogdanm	0:9b334a45a8ff	4415	*/
bogdanm	0:9b334a45a8ff	4416
bogdanm	0:9b334a45a8ff	4417	/**
bogdanm	0:9b334a45a8ff	4418	* @brief Period elapsed callback in non blocking mode
bogdanm	0:9b334a45a8ff	4419	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4420	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4421	* @retval None
bogdanm	0:9b334a45a8ff	4422	*/
bogdanm	0:9b334a45a8ff	4423	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4424	{
mbed_official	83:a036322b8637	4425	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	4426	UNUSED(htim);
mbed_official	83:a036322b8637	4427
bogdanm	0:9b334a45a8ff	4428	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4429	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4430	*/
bogdanm	0:9b334a45a8ff	4431
bogdanm	0:9b334a45a8ff	4432	}
bogdanm	0:9b334a45a8ff	4433	/**
bogdanm	0:9b334a45a8ff	4434	* @brief Output Compare callback in non blocking mode
bogdanm	0:9b334a45a8ff	4435	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4436	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4437	* @retval None
bogdanm	0:9b334a45a8ff	4438	*/
bogdanm	0:9b334a45a8ff	4439	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4440	{
mbed_official	83:a036322b8637	4441	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	4442	UNUSED(htim);
mbed_official	83:a036322b8637	4443
bogdanm	0:9b334a45a8ff	4444	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4445	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4446	*/
bogdanm	0:9b334a45a8ff	4447	}
bogdanm	0:9b334a45a8ff	4448	/**
bogdanm	0:9b334a45a8ff	4449	* @brief Input Capture callback in non blocking mode
bogdanm	0:9b334a45a8ff	4450	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4451	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4452	* @retval None
bogdanm	0:9b334a45a8ff	4453	*/
bogdanm	0:9b334a45a8ff	4454	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4455	{
mbed_official	83:a036322b8637	4456	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	4457	UNUSED(htim);
mbed_official	83:a036322b8637	4458
bogdanm	0:9b334a45a8ff	4459	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4460	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4461	*/
bogdanm	0:9b334a45a8ff	4462	}
bogdanm	0:9b334a45a8ff	4463
bogdanm	0:9b334a45a8ff	4464	/**
bogdanm	0:9b334a45a8ff	4465	* @brief PWM Pulse finished callback in non blocking mode
bogdanm	0:9b334a45a8ff	4466	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4467	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4468	* @retval None
bogdanm	0:9b334a45a8ff	4469	*/
bogdanm	0:9b334a45a8ff	4470	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4471	{
mbed_official	83:a036322b8637	4472	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	4473	UNUSED(htim);
mbed_official	83:a036322b8637	4474
bogdanm	0:9b334a45a8ff	4475	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4476	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4477	*/
bogdanm	0:9b334a45a8ff	4478	}
bogdanm	0:9b334a45a8ff	4479
bogdanm	0:9b334a45a8ff	4480	/**
bogdanm	0:9b334a45a8ff	4481	* @brief Hall Trigger detection callback in non blocking mode
bogdanm	0:9b334a45a8ff	4482	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4483	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4484	* @retval None
bogdanm	0:9b334a45a8ff	4485	*/
bogdanm	0:9b334a45a8ff	4486	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4487	{
mbed_official	83:a036322b8637	4488	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	4489	UNUSED(htim);
mbed_official	83:a036322b8637	4490
bogdanm	0:9b334a45a8ff	4491	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4492	the HAL_TIM_TriggerCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4493	*/
bogdanm	0:9b334a45a8ff	4494	}
bogdanm	0:9b334a45a8ff	4495
bogdanm	0:9b334a45a8ff	4496	/**
bogdanm	0:9b334a45a8ff	4497	* @brief Timer error callback in non blocking mode
bogdanm	0:9b334a45a8ff	4498	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4499	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4500	* @retval None
bogdanm	0:9b334a45a8ff	4501	*/
bogdanm	0:9b334a45a8ff	4502	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4503	{
mbed_official	83:a036322b8637	4504	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	4505	UNUSED(htim);
mbed_official	83:a036322b8637	4506
bogdanm	0:9b334a45a8ff	4507	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4508	the HAL_TIM_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4509	*/
bogdanm	0:9b334a45a8ff	4510	}
bogdanm	0:9b334a45a8ff	4511
bogdanm	0:9b334a45a8ff	4512	/**
bogdanm	0:9b334a45a8ff	4513	* @}
bogdanm	0:9b334a45a8ff	4514	*/
bogdanm	0:9b334a45a8ff	4515
bogdanm	0:9b334a45a8ff	4516	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
bogdanm	0:9b334a45a8ff	4517	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	4518	*
bogdanm	0:9b334a45a8ff	4519	@verbatim
bogdanm	0:9b334a45a8ff	4520	==============================================================================
bogdanm	0:9b334a45a8ff	4521	##### Peripheral State functions #####
bogdanm	0:9b334a45a8ff	4522	==============================================================================
bogdanm	0:9b334a45a8ff	4523	[..]
bogdanm	0:9b334a45a8ff	4524	This subsection permits to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	4525	and the data flow.
bogdanm	0:9b334a45a8ff	4526
bogdanm	0:9b334a45a8ff	4527	@endverbatim
bogdanm	0:9b334a45a8ff	4528	* @{
bogdanm	0:9b334a45a8ff	4529	*/
bogdanm	0:9b334a45a8ff	4530
bogdanm	0:9b334a45a8ff	4531	/**
bogdanm	0:9b334a45a8ff	4532	* @brief Return the TIM Base state
bogdanm	0:9b334a45a8ff	4533	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4534	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4535	* @retval HAL state
bogdanm	0:9b334a45a8ff	4536	*/
bogdanm	0:9b334a45a8ff	4537	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4538	{
bogdanm	0:9b334a45a8ff	4539	return htim->State;
bogdanm	0:9b334a45a8ff	4540	}
bogdanm	0:9b334a45a8ff	4541
bogdanm	0:9b334a45a8ff	4542	/**
bogdanm	0:9b334a45a8ff	4543	* @brief Return the TIM OC state
bogdanm	0:9b334a45a8ff	4544	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4545	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4546	* @retval HAL state
bogdanm	0:9b334a45a8ff	4547	*/
bogdanm	0:9b334a45a8ff	4548	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4549	{
bogdanm	0:9b334a45a8ff	4550	return htim->State;
bogdanm	0:9b334a45a8ff	4551	}
bogdanm	0:9b334a45a8ff	4552
bogdanm	0:9b334a45a8ff	4553	/**
bogdanm	0:9b334a45a8ff	4554	* @brief Return the TIM PWM state
bogdanm	0:9b334a45a8ff	4555	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4556	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4557	* @retval HAL state
bogdanm	0:9b334a45a8ff	4558	*/
bogdanm	0:9b334a45a8ff	4559	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4560	{
bogdanm	0:9b334a45a8ff	4561	return htim->State;
bogdanm	0:9b334a45a8ff	4562	}
bogdanm	0:9b334a45a8ff	4563
bogdanm	0:9b334a45a8ff	4564	/**
bogdanm	0:9b334a45a8ff	4565	* @brief Return the TIM Input Capture state
bogdanm	0:9b334a45a8ff	4566	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4567	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4568	* @retval HAL state
bogdanm	0:9b334a45a8ff	4569	*/
bogdanm	0:9b334a45a8ff	4570	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4571	{
bogdanm	0:9b334a45a8ff	4572	return htim->State;
bogdanm	0:9b334a45a8ff	4573	}
bogdanm	0:9b334a45a8ff	4574
bogdanm	0:9b334a45a8ff	4575	/**
bogdanm	0:9b334a45a8ff	4576	* @brief Return the TIM One Pulse Mode state
bogdanm	0:9b334a45a8ff	4577	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4578	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4579	* @retval HAL state
bogdanm	0:9b334a45a8ff	4580	*/
bogdanm	0:9b334a45a8ff	4581	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4582	{
bogdanm	0:9b334a45a8ff	4583	return htim->State;
bogdanm	0:9b334a45a8ff	4584	}
bogdanm	0:9b334a45a8ff	4585
bogdanm	0:9b334a45a8ff	4586	/**
bogdanm	0:9b334a45a8ff	4587	* @brief Return the TIM Encoder Mode state
bogdanm	0:9b334a45a8ff	4588	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4589	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4590	* @retval HAL state
bogdanm	0:9b334a45a8ff	4591	*/
bogdanm	0:9b334a45a8ff	4592	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4593	{
bogdanm	0:9b334a45a8ff	4594	return htim->State;
bogdanm	0:9b334a45a8ff	4595	}
bogdanm	0:9b334a45a8ff	4596
bogdanm	0:9b334a45a8ff	4597	/**
bogdanm	0:9b334a45a8ff	4598	* @}
bogdanm	0:9b334a45a8ff	4599	*/
bogdanm	0:9b334a45a8ff	4600
bogdanm	0:9b334a45a8ff	4601	/**
bogdanm	0:9b334a45a8ff	4602	* @brief TIM DMA error callback
bogdanm	0:9b334a45a8ff	4603	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4604	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4605	* @retval None
bogdanm	0:9b334a45a8ff	4606	*/
bogdanm	0:9b334a45a8ff	4607	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4608	{
bogdanm	0:9b334a45a8ff	4609	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4610
bogdanm	0:9b334a45a8ff	4611	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4612
bogdanm	0:9b334a45a8ff	4613	HAL_TIM_ErrorCallback(htim);
bogdanm	0:9b334a45a8ff	4614	}
bogdanm	0:9b334a45a8ff	4615
bogdanm	0:9b334a45a8ff	4616	/**
bogdanm	0:9b334a45a8ff	4617	* @brief TIM DMA Delay Pulse complete callback.
bogdanm	0:9b334a45a8ff	4618	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4619	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4620	* @retval None
bogdanm	0:9b334a45a8ff	4621	*/
bogdanm	0:9b334a45a8ff	4622	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4623	{
bogdanm	0:9b334a45a8ff	4624	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4625
bogdanm	0:9b334a45a8ff	4626	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4627
bogdanm	0:9b334a45a8ff	4628	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4629	{
bogdanm	0:9b334a45a8ff	4630	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4631	}
bogdanm	0:9b334a45a8ff	4632	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4633	{
bogdanm	0:9b334a45a8ff	4634	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4635	}
bogdanm	0:9b334a45a8ff	4636	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4637	{
bogdanm	0:9b334a45a8ff	4638	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4639	}
bogdanm	0:9b334a45a8ff	4640	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4641	{
bogdanm	0:9b334a45a8ff	4642	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4643	}
bogdanm	0:9b334a45a8ff	4644
bogdanm	0:9b334a45a8ff	4645	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	4646
bogdanm	0:9b334a45a8ff	4647	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4648	}
bogdanm	0:9b334a45a8ff	4649	/**
bogdanm	0:9b334a45a8ff	4650	* @brief TIM DMA Capture complete callback.
bogdanm	0:9b334a45a8ff	4651	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4652	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4653	* @retval None
bogdanm	0:9b334a45a8ff	4654	*/
bogdanm	0:9b334a45a8ff	4655	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4656	{
bogdanm	0:9b334a45a8ff	4657	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4658
bogdanm	0:9b334a45a8ff	4659	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4660
bogdanm	0:9b334a45a8ff	4661	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4662	{
bogdanm	0:9b334a45a8ff	4663	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4664	}
bogdanm	0:9b334a45a8ff	4665	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4666	{
bogdanm	0:9b334a45a8ff	4667	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4668	}
bogdanm	0:9b334a45a8ff	4669	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4670	{
bogdanm	0:9b334a45a8ff	4671	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4672	}
bogdanm	0:9b334a45a8ff	4673	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4674	{
bogdanm	0:9b334a45a8ff	4675	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4676	}
bogdanm	0:9b334a45a8ff	4677
bogdanm	0:9b334a45a8ff	4678	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	4679
bogdanm	0:9b334a45a8ff	4680	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4681
bogdanm	0:9b334a45a8ff	4682	}
bogdanm	0:9b334a45a8ff	4683
bogdanm	0:9b334a45a8ff	4684	/**
bogdanm	0:9b334a45a8ff	4685	* @brief TIM DMA Period Elapse complete callback.
bogdanm	0:9b334a45a8ff	4686	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4687	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4688	* @retval None
bogdanm	0:9b334a45a8ff	4689	*/
bogdanm	0:9b334a45a8ff	4690	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4691	{
bogdanm	0:9b334a45a8ff	4692	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4693
bogdanm	0:9b334a45a8ff	4694	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4695
bogdanm	0:9b334a45a8ff	4696	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	4697	}
bogdanm	0:9b334a45a8ff	4698
bogdanm	0:9b334a45a8ff	4699	/**
bogdanm	0:9b334a45a8ff	4700	* @brief TIM DMA Trigger callback.
bogdanm	0:9b334a45a8ff	4701	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4702	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4703	* @retval None
bogdanm	0:9b334a45a8ff	4704	*/
bogdanm	0:9b334a45a8ff	4705	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4706	{
bogdanm	0:9b334a45a8ff	4707	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4708
bogdanm	0:9b334a45a8ff	4709	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4710
bogdanm	0:9b334a45a8ff	4711	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	4712	}
bogdanm	0:9b334a45a8ff	4713
bogdanm	0:9b334a45a8ff	4714	/**
bogdanm	0:9b334a45a8ff	4715	* @brief Time Base configuration
bogdanm	0:9b334a45a8ff	4716	* @param TIMx: TIM peripheral
bogdanm	0:9b334a45a8ff	4717	* @param Structure: pointer on TIM Time Base required parameters
bogdanm	0:9b334a45a8ff	4718	* @retval None
bogdanm	0:9b334a45a8ff	4719	*/
bogdanm	0:9b334a45a8ff	4720	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
bogdanm	0:9b334a45a8ff	4721	{
bogdanm	0:9b334a45a8ff	4722	uint32_t tmpcr1 = 0;
bogdanm	0:9b334a45a8ff	4723	tmpcr1 = TIMx->CR1;
bogdanm	0:9b334a45a8ff	4724
bogdanm	0:9b334a45a8ff	4725	/* Set TIM Time Base Unit parameters ---------------------------------------*/
bogdanm	0:9b334a45a8ff	4726	if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4727	{
bogdanm	0:9b334a45a8ff	4728	/* Select the Counter Mode */
bogdanm	0:9b334a45a8ff	4729	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
bogdanm	0:9b334a45a8ff	4730	tmpcr1 \|= Structure->CounterMode;
bogdanm	0:9b334a45a8ff	4731	}
bogdanm	0:9b334a45a8ff	4732
bogdanm	0:9b334a45a8ff	4733	if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4734	{
bogdanm	0:9b334a45a8ff	4735	/* Set the clock division */
bogdanm	0:9b334a45a8ff	4736	tmpcr1 &= ~TIM_CR1_CKD;
bogdanm	0:9b334a45a8ff	4737	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
bogdanm	0:9b334a45a8ff	4738	}
bogdanm	0:9b334a45a8ff	4739
bogdanm	0:9b334a45a8ff	4740	TIMx->CR1 = tmpcr1;
bogdanm	0:9b334a45a8ff	4741
bogdanm	0:9b334a45a8ff	4742	/* Set the Auto-reload value */
bogdanm	0:9b334a45a8ff	4743	TIMx->ARR = (uint32_t)Structure->Period ;
bogdanm	0:9b334a45a8ff	4744
bogdanm	0:9b334a45a8ff	4745	/* Set the Prescaler value */
bogdanm	0:9b334a45a8ff	4746	TIMx->PSC = (uint32_t)Structure->Prescaler;
bogdanm	0:9b334a45a8ff	4747
bogdanm	0:9b334a45a8ff	4748	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4749	{
bogdanm	0:9b334a45a8ff	4750	/* Set the Repetition Counter value */
bogdanm	0:9b334a45a8ff	4751	TIMx->RCR = Structure->RepetitionCounter;
bogdanm	0:9b334a45a8ff	4752	}
bogdanm	0:9b334a45a8ff	4753
bogdanm	0:9b334a45a8ff	4754	/* Generate an update event to reload the Prescaler
bogdanm	0:9b334a45a8ff	4755	and the repetition counter(only for TIM1 and TIM8) value immediately */
bogdanm	0:9b334a45a8ff	4756	TIMx->EGR = TIM_EGR_UG;
bogdanm	0:9b334a45a8ff	4757	}
bogdanm	0:9b334a45a8ff	4758
bogdanm	0:9b334a45a8ff	4759	/**
bogdanm	0:9b334a45a8ff	4760	* @brief Time Output Compare 1 configuration
bogdanm	0:9b334a45a8ff	4761	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4762	* @param OC_Config: The output configuration structure
bogdanm	0:9b334a45a8ff	4763	* @retval None
bogdanm	0:9b334a45a8ff	4764	*/
bogdanm	0:9b334a45a8ff	4765	void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4766	{
bogdanm	0:9b334a45a8ff	4767	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4768	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4769	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4770
bogdanm	0:9b334a45a8ff	4771	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4772	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4773
bogdanm	0:9b334a45a8ff	4774	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4775	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4776	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4777	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4778
bogdanm	0:9b334a45a8ff	4779	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4780	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4781
bogdanm	0:9b334a45a8ff	4782	/* Reset the Output Compare Mode Bits */
bogdanm	0:9b334a45a8ff	4783	tmpccmrx &= ~TIM_CCMR1_OC1M;
bogdanm	0:9b334a45a8ff	4784	tmpccmrx &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	4785	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4786	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4787
bogdanm	0:9b334a45a8ff	4788	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4789	tmpccer &= ~TIM_CCER_CC1P;
bogdanm	0:9b334a45a8ff	4790	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4791	tmpccer \|= OC_Config->OCPolarity;
bogdanm	0:9b334a45a8ff	4792
bogdanm	0:9b334a45a8ff	4793
bogdanm	0:9b334a45a8ff	4794	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4795	{
bogdanm	0:9b334a45a8ff	4796	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4797	tmpccer &= ~TIM_CCER_CC1NP;
bogdanm	0:9b334a45a8ff	4798	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4799	tmpccer \|= OC_Config->OCNPolarity;
bogdanm	0:9b334a45a8ff	4800	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4801	tmpccer &= ~TIM_CCER_CC1NE;
bogdanm	0:9b334a45a8ff	4802
bogdanm	0:9b334a45a8ff	4803	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4804	tmpcr2 &= ~TIM_CR2_OIS1;
bogdanm	0:9b334a45a8ff	4805	tmpcr2 &= ~TIM_CR2_OIS1N;
bogdanm	0:9b334a45a8ff	4806	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4807	tmpcr2 \|= OC_Config->OCIdleState;
bogdanm	0:9b334a45a8ff	4808	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4809	tmpcr2 \|= OC_Config->OCNIdleState;
bogdanm	0:9b334a45a8ff	4810	}
bogdanm	0:9b334a45a8ff	4811	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4812	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4813
bogdanm	0:9b334a45a8ff	4814	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4815	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4816
bogdanm	0:9b334a45a8ff	4817	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4818	TIMx->CCR1 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4819
bogdanm	0:9b334a45a8ff	4820	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4821	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4822	}
bogdanm	0:9b334a45a8ff	4823
bogdanm	0:9b334a45a8ff	4824	/**
bogdanm	0:9b334a45a8ff	4825	* @brief Time Output Compare 2 configuration
bogdanm	0:9b334a45a8ff	4826	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4827	* @param OC_Config: The output configuration structure
bogdanm	0:9b334a45a8ff	4828	* @retval None
bogdanm	0:9b334a45a8ff	4829	*/
bogdanm	0:9b334a45a8ff	4830	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4831	{
bogdanm	0:9b334a45a8ff	4832	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4833	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4834	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4835
bogdanm	0:9b334a45a8ff	4836	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4837	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	4838
bogdanm	0:9b334a45a8ff	4839	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4840	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4841	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4842	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4843
bogdanm	0:9b334a45a8ff	4844	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4845	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4846
bogdanm	0:9b334a45a8ff	4847	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4848	tmpccmrx &= ~TIM_CCMR1_OC2M;
bogdanm	0:9b334a45a8ff	4849	tmpccmrx &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	4850
bogdanm	0:9b334a45a8ff	4851	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4852	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4853
bogdanm	0:9b334a45a8ff	4854	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4855	tmpccer &= ~TIM_CCER_CC2P;
bogdanm	0:9b334a45a8ff	4856	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4857	tmpccer \|= (OC_Config->OCPolarity << 4);
bogdanm	0:9b334a45a8ff	4858
bogdanm	0:9b334a45a8ff	4859	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4860	{
bogdanm	0:9b334a45a8ff	4861	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4862
bogdanm	0:9b334a45a8ff	4863	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4864	tmpccer &= ~TIM_CCER_CC2NP;
bogdanm	0:9b334a45a8ff	4865	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4866	tmpccer \|= (OC_Config->OCNPolarity << 4);
bogdanm	0:9b334a45a8ff	4867	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4868	tmpccer &= ~TIM_CCER_CC2NE;
bogdanm	0:9b334a45a8ff	4869
bogdanm	0:9b334a45a8ff	4870	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4871	tmpcr2 &= ~TIM_CR2_OIS2;
bogdanm	0:9b334a45a8ff	4872	tmpcr2 &= ~TIM_CR2_OIS2N;
bogdanm	0:9b334a45a8ff	4873	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4874	tmpcr2 \|= (OC_Config->OCIdleState << 2);
bogdanm	0:9b334a45a8ff	4875	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4876	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
bogdanm	0:9b334a45a8ff	4877	}
bogdanm	0:9b334a45a8ff	4878	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4879	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4880
bogdanm	0:9b334a45a8ff	4881	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4882	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4883
bogdanm	0:9b334a45a8ff	4884	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4885	TIMx->CCR2 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4886
bogdanm	0:9b334a45a8ff	4887	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4888	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4889	}
bogdanm	0:9b334a45a8ff	4890
bogdanm	0:9b334a45a8ff	4891	/**
bogdanm	0:9b334a45a8ff	4892	* @brief Time Output Compare 3 configuration
bogdanm	0:9b334a45a8ff	4893	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4894	* @param OC_Config: The output configuration structure
bogdanm	0:9b334a45a8ff	4895	* @retval None
bogdanm	0:9b334a45a8ff	4896	*/
bogdanm	0:9b334a45a8ff	4897	void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4898	{
bogdanm	0:9b334a45a8ff	4899	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4900	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4901	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4902
bogdanm	0:9b334a45a8ff	4903	/* Disable the Channel 3: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4904	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	4905
bogdanm	0:9b334a45a8ff	4906	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4907	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4908	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4909	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4910
bogdanm	0:9b334a45a8ff	4911	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4912	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4913
bogdanm	0:9b334a45a8ff	4914	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4915	tmpccmrx &= ~TIM_CCMR2_OC3M;
bogdanm	0:9b334a45a8ff	4916	tmpccmrx &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	4917	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4918	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4919
bogdanm	0:9b334a45a8ff	4920	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4921	tmpccer &= ~TIM_CCER_CC3P;
bogdanm	0:9b334a45a8ff	4922	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4923	tmpccer \|= (OC_Config->OCPolarity << 8);
bogdanm	0:9b334a45a8ff	4924
bogdanm	0:9b334a45a8ff	4925	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4926	{
bogdanm	0:9b334a45a8ff	4927	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4928
bogdanm	0:9b334a45a8ff	4929	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4930	tmpccer &= ~TIM_CCER_CC3NP;
bogdanm	0:9b334a45a8ff	4931	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4932	tmpccer \|= (OC_Config->OCNPolarity << 8);
bogdanm	0:9b334a45a8ff	4933	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4934	tmpccer &= ~TIM_CCER_CC3NE;
bogdanm	0:9b334a45a8ff	4935
bogdanm	0:9b334a45a8ff	4936	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4937	tmpcr2 &= ~TIM_CR2_OIS3;
bogdanm	0:9b334a45a8ff	4938	tmpcr2 &= ~TIM_CR2_OIS3N;
bogdanm	0:9b334a45a8ff	4939	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4940	tmpcr2 \|= (OC_Config->OCIdleState << 4);
bogdanm	0:9b334a45a8ff	4941	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4942	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
bogdanm	0:9b334a45a8ff	4943	}
bogdanm	0:9b334a45a8ff	4944	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4945	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4946
bogdanm	0:9b334a45a8ff	4947	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	4948	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4949
bogdanm	0:9b334a45a8ff	4950	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4951	TIMx->CCR3 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4952
bogdanm	0:9b334a45a8ff	4953	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4954	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4955	}
bogdanm	0:9b334a45a8ff	4956
bogdanm	0:9b334a45a8ff	4957	/**
bogdanm	0:9b334a45a8ff	4958	* @brief Time Output Compare 4 configuration
bogdanm	0:9b334a45a8ff	4959	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4960	* @param OC_Config: The output configuration structure
bogdanm	0:9b334a45a8ff	4961	* @retval None
bogdanm	0:9b334a45a8ff	4962	*/
bogdanm	0:9b334a45a8ff	4963	void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4964	{
bogdanm	0:9b334a45a8ff	4965	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4966	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4967	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4968
bogdanm	0:9b334a45a8ff	4969	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	4970	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	4971
bogdanm	0:9b334a45a8ff	4972	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4973	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4974	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4975	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4976
bogdanm	0:9b334a45a8ff	4977	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4978	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4979
bogdanm	0:9b334a45a8ff	4980	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4981	tmpccmrx &= ~TIM_CCMR2_OC4M;
bogdanm	0:9b334a45a8ff	4982	tmpccmrx &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	4983
bogdanm	0:9b334a45a8ff	4984	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4985	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4986
bogdanm	0:9b334a45a8ff	4987	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4988	tmpccer &= ~TIM_CCER_CC4P;
bogdanm	0:9b334a45a8ff	4989	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4990	tmpccer \|= (OC_Config->OCPolarity << 12);
bogdanm	0:9b334a45a8ff	4991
bogdanm	0:9b334a45a8ff	4992	/if((TIMx == TIM1) \|\| (TIMx == TIM8))/
bogdanm	0:9b334a45a8ff	4993	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4994	{
bogdanm	0:9b334a45a8ff	4995	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4996	/* Reset the Output Compare IDLE State */
bogdanm	0:9b334a45a8ff	4997	tmpcr2 &= ~TIM_CR2_OIS4;
bogdanm	0:9b334a45a8ff	4998	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4999	tmpcr2 \|= (OC_Config->OCIdleState << 6);
bogdanm	0:9b334a45a8ff	5000	}
bogdanm	0:9b334a45a8ff	5001	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	5002	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	5003
bogdanm	0:9b334a45a8ff	5004	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	5005	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	5006
bogdanm	0:9b334a45a8ff	5007	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	5008	TIMx->CCR4 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	5009
bogdanm	0:9b334a45a8ff	5010	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	5011	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5012	}
bogdanm	0:9b334a45a8ff	5013
bogdanm	0:9b334a45a8ff	5014	/**
bogdanm	0:9b334a45a8ff	5015	* @brief Time Output Compare 4 configuration
bogdanm	0:9b334a45a8ff	5016	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	5017	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	5018	* @param sSlaveConfig: The slave configuration structure
bogdanm	0:9b334a45a8ff	5019	* @retval None
bogdanm	0:9b334a45a8ff	5020	*/
bogdanm	0:9b334a45a8ff	5021	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	5022	TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm	0:9b334a45a8ff	5023	{
bogdanm	0:9b334a45a8ff	5024	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	5025	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5026	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5027
bogdanm	0:9b334a45a8ff	5028	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	5029	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	5030
bogdanm	0:9b334a45a8ff	5031	/* Reset the Trigger Selection Bits */
bogdanm	0:9b334a45a8ff	5032	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	5033	/* Set the Input Trigger source */
bogdanm	0:9b334a45a8ff	5034	tmpsmcr \|= sSlaveConfig->InputTrigger;
bogdanm	0:9b334a45a8ff	5035
bogdanm	0:9b334a45a8ff	5036	/* Reset the slave mode Bits */
bogdanm	0:9b334a45a8ff	5037	tmpsmcr &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	5038	/* Set the slave mode */
bogdanm	0:9b334a45a8ff	5039	tmpsmcr \|= sSlaveConfig->SlaveMode;
bogdanm	0:9b334a45a8ff	5040
bogdanm	0:9b334a45a8ff	5041	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	5042	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	5043
bogdanm	0:9b334a45a8ff	5044	/* Configure the trigger prescaler, filter, and polarity */
bogdanm	0:9b334a45a8ff	5045	switch (sSlaveConfig->InputTrigger)
bogdanm	0:9b334a45a8ff	5046	{
bogdanm	0:9b334a45a8ff	5047	case TIM_TS_ETRF:
bogdanm	0:9b334a45a8ff	5048	{
bogdanm	0:9b334a45a8ff	5049	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5050	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5051	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
bogdanm	0:9b334a45a8ff	5052	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	5053	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	5054	/* Configure the ETR Trigger source */
bogdanm	0:9b334a45a8ff	5055	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	5056	sSlaveConfig->TriggerPrescaler,
bogdanm	0:9b334a45a8ff	5057	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	5058	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	5059	}
bogdanm	0:9b334a45a8ff	5060	break;
bogdanm	0:9b334a45a8ff	5061
bogdanm	0:9b334a45a8ff	5062	case TIM_TS_TI1F_ED:
bogdanm	0:9b334a45a8ff	5063	{
bogdanm	0:9b334a45a8ff	5064	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5065	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5066	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	5067	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	5068
bogdanm	0:9b334a45a8ff	5069	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	5070	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	5071	htim->Instance->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	5072	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	5073
bogdanm	0:9b334a45a8ff	5074	/* Set the filter */
bogdanm	0:9b334a45a8ff	5075	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	5076	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
bogdanm	0:9b334a45a8ff	5077
bogdanm	0:9b334a45a8ff	5078	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5079	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	5080	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5081
bogdanm	0:9b334a45a8ff	5082	}
bogdanm	0:9b334a45a8ff	5083	break;
bogdanm	0:9b334a45a8ff	5084
bogdanm	0:9b334a45a8ff	5085	case TIM_TS_TI1FP1:
bogdanm	0:9b334a45a8ff	5086	{
bogdanm	0:9b334a45a8ff	5087	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5088	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5089	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	5090	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	5091
bogdanm	0:9b334a45a8ff	5092	/* Configure TI1 Filter and Polarity */
bogdanm	0:9b334a45a8ff	5093	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	5094	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	5095	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	5096	}
bogdanm	0:9b334a45a8ff	5097	break;
bogdanm	0:9b334a45a8ff	5098
bogdanm	0:9b334a45a8ff	5099	case TIM_TS_TI2FP2:
bogdanm	0:9b334a45a8ff	5100	{
bogdanm	0:9b334a45a8ff	5101	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5102	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5103	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	5104	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	5105
bogdanm	0:9b334a45a8ff	5106	/* Configure TI2 Filter and Polarity */
bogdanm	0:9b334a45a8ff	5107	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	5108	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	5109	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	5110	}
bogdanm	0:9b334a45a8ff	5111	break;
bogdanm	0:9b334a45a8ff	5112
bogdanm	0:9b334a45a8ff	5113	case TIM_TS_ITR0:
bogdanm	0:9b334a45a8ff	5114	{
bogdanm	0:9b334a45a8ff	5115	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5116	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5117	}
bogdanm	0:9b334a45a8ff	5118	break;
bogdanm	0:9b334a45a8ff	5119
bogdanm	0:9b334a45a8ff	5120	case TIM_TS_ITR1:
bogdanm	0:9b334a45a8ff	5121	{
bogdanm	0:9b334a45a8ff	5122	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5123	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5124	}
bogdanm	0:9b334a45a8ff	5125	break;
bogdanm	0:9b334a45a8ff	5126
bogdanm	0:9b334a45a8ff	5127	case TIM_TS_ITR2:
bogdanm	0:9b334a45a8ff	5128	{
bogdanm	0:9b334a45a8ff	5129	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5130	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5131	}
bogdanm	0:9b334a45a8ff	5132	break;
bogdanm	0:9b334a45a8ff	5133
bogdanm	0:9b334a45a8ff	5134	case TIM_TS_ITR3:
bogdanm	0:9b334a45a8ff	5135	{
bogdanm	0:9b334a45a8ff	5136	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5137	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5138	}
bogdanm	0:9b334a45a8ff	5139	break;
bogdanm	0:9b334a45a8ff	5140
bogdanm	0:9b334a45a8ff	5141	default:
bogdanm	0:9b334a45a8ff	5142	break;
bogdanm	0:9b334a45a8ff	5143	}
bogdanm	0:9b334a45a8ff	5144	}
bogdanm	0:9b334a45a8ff	5145
bogdanm	0:9b334a45a8ff	5146	/**
bogdanm	0:9b334a45a8ff	5147	* @brief Configure the TI1 as Input.
bogdanm	0:9b334a45a8ff	5148	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	5149	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5150	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5151	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5152	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5153	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5154	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5155	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5156	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
bogdanm	0:9b334a45a8ff	5157	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
bogdanm	0:9b334a45a8ff	5158	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5159	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5160	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5161	* @retval None
bogdanm	0:9b334a45a8ff	5162	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
bogdanm	0:9b334a45a8ff	5163	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
bogdanm	0:9b334a45a8ff	5164	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5165	*/
bogdanm	0:9b334a45a8ff	5166	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5167	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5168	{
bogdanm	0:9b334a45a8ff	5169	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5170	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5171
bogdanm	0:9b334a45a8ff	5172	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	5173	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	5174	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5175	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5176
bogdanm	0:9b334a45a8ff	5177	/* Select the Input */
bogdanm	0:9b334a45a8ff	5178	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	5179	{
bogdanm	0:9b334a45a8ff	5180	tmpccmr1 &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	5181	tmpccmr1 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	5182	}
bogdanm	0:9b334a45a8ff	5183	else
bogdanm	0:9b334a45a8ff	5184	{
bogdanm	0:9b334a45a8ff	5185	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
bogdanm	0:9b334a45a8ff	5186	}
bogdanm	0:9b334a45a8ff	5187
bogdanm	0:9b334a45a8ff	5188	/* Set the filter */
bogdanm	0:9b334a45a8ff	5189	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	5190	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
bogdanm	0:9b334a45a8ff	5191
bogdanm	0:9b334a45a8ff	5192	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	5193	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	5194	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
bogdanm	0:9b334a45a8ff	5195
bogdanm	0:9b334a45a8ff	5196	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5197	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	5198	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5199	}
bogdanm	0:9b334a45a8ff	5200
bogdanm	0:9b334a45a8ff	5201	/**
bogdanm	0:9b334a45a8ff	5202	* @brief Configure the Polarity and Filter for TI1.
bogdanm	0:9b334a45a8ff	5203	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	5204	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5205	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5206	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5207	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5208	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5209	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5210	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5211	* @retval None
bogdanm	0:9b334a45a8ff	5212	*/
bogdanm	0:9b334a45a8ff	5213	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5214	{
bogdanm	0:9b334a45a8ff	5215	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5216	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5217
bogdanm	0:9b334a45a8ff	5218	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	5219	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5220	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	5221	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5222
bogdanm	0:9b334a45a8ff	5223	/* Set the filter */
bogdanm	0:9b334a45a8ff	5224	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	5225	tmpccmr1 \|= (TIM_ICFilter << 4);
bogdanm	0:9b334a45a8ff	5226
bogdanm	0:9b334a45a8ff	5227	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	5228	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	5229	tmpccer \|= TIM_ICPolarity;
bogdanm	0:9b334a45a8ff	5230
bogdanm	0:9b334a45a8ff	5231	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5232	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	5233	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5234	}
bogdanm	0:9b334a45a8ff	5235
bogdanm	0:9b334a45a8ff	5236	/**
bogdanm	0:9b334a45a8ff	5237	* @brief Configure the TI2 as Input.
bogdanm	0:9b334a45a8ff	5238	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5239	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5240	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5241	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5242	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5243	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5244	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5245	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5246	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
bogdanm	0:9b334a45a8ff	5247	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
bogdanm	0:9b334a45a8ff	5248	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5249	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5250	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5251	* @retval None
bogdanm	0:9b334a45a8ff	5252	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
bogdanm	0:9b334a45a8ff	5253	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
bogdanm	0:9b334a45a8ff	5254	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5255	*/
bogdanm	0:9b334a45a8ff	5256	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5257	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5258	{
bogdanm	0:9b334a45a8ff	5259	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5260	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5261
bogdanm	0:9b334a45a8ff	5262	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	5263	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	5264	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5265	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5266
bogdanm	0:9b334a45a8ff	5267	/* Select the Input */
bogdanm	0:9b334a45a8ff	5268	tmpccmr1 &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	5269	tmpccmr1 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	5270
bogdanm	0:9b334a45a8ff	5271	/* Set the filter */
bogdanm	0:9b334a45a8ff	5272	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	5273	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	5274
bogdanm	0:9b334a45a8ff	5275	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	5276	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	5277	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
bogdanm	0:9b334a45a8ff	5278
bogdanm	0:9b334a45a8ff	5279	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5280	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	5281	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5282	}
bogdanm	0:9b334a45a8ff	5283
bogdanm	0:9b334a45a8ff	5284	/**
bogdanm	0:9b334a45a8ff	5285	* @brief Configure the Polarity and Filter for TI2.
bogdanm	0:9b334a45a8ff	5286	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	5287	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5288	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5289	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5290	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5291	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5292	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5293	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5294	* @retval None
bogdanm	0:9b334a45a8ff	5295	*/
bogdanm	0:9b334a45a8ff	5296	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5297	{
bogdanm	0:9b334a45a8ff	5298	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5299	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5300
bogdanm	0:9b334a45a8ff	5301	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	5302	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	5303	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5304	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5305
bogdanm	0:9b334a45a8ff	5306	/* Set the filter */
bogdanm	0:9b334a45a8ff	5307	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	5308	tmpccmr1 \|= (TIM_ICFilter << 12);
bogdanm	0:9b334a45a8ff	5309
bogdanm	0:9b334a45a8ff	5310	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	5311	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	5312	tmpccer \|= (TIM_ICPolarity << 4);
bogdanm	0:9b334a45a8ff	5313
bogdanm	0:9b334a45a8ff	5314	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5315	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	5316	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5317	}
bogdanm	0:9b334a45a8ff	5318
bogdanm	0:9b334a45a8ff	5319	/**
bogdanm	0:9b334a45a8ff	5320	* @brief Configure the TI3 as Input.
bogdanm	0:9b334a45a8ff	5321	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5322	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5323	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5324	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5325	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5326	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5327	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5328	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5329	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
bogdanm	0:9b334a45a8ff	5330	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
bogdanm	0:9b334a45a8ff	5331	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5332	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5333	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5334	* @retval None
bogdanm	0:9b334a45a8ff	5335	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
bogdanm	0:9b334a45a8ff	5336	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm	0:9b334a45a8ff	5337	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5338	*/
bogdanm	0:9b334a45a8ff	5339	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5340	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5341	{
bogdanm	0:9b334a45a8ff	5342	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	5343	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5344
bogdanm	0:9b334a45a8ff	5345	/* Disable the Channel 3: Reset the CC3E Bit */
bogdanm	0:9b334a45a8ff	5346	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	5347	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	5348	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5349
bogdanm	0:9b334a45a8ff	5350	/* Select the Input */
bogdanm	0:9b334a45a8ff	5351	tmpccmr2 &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	5352	tmpccmr2 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	5353
bogdanm	0:9b334a45a8ff	5354	/* Set the filter */
bogdanm	0:9b334a45a8ff	5355	tmpccmr2 &= ~TIM_CCMR2_IC3F;
bogdanm	0:9b334a45a8ff	5356	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
bogdanm	0:9b334a45a8ff	5357
bogdanm	0:9b334a45a8ff	5358	/* Select the Polarity and set the CC3E Bit */
bogdanm	0:9b334a45a8ff	5359	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
bogdanm	0:9b334a45a8ff	5360	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
bogdanm	0:9b334a45a8ff	5361
bogdanm	0:9b334a45a8ff	5362	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	5363	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	5364	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5365	}
bogdanm	0:9b334a45a8ff	5366
bogdanm	0:9b334a45a8ff	5367	/**
bogdanm	0:9b334a45a8ff	5368	* @brief Configure the TI4 as Input.
bogdanm	0:9b334a45a8ff	5369	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5370	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5371	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5372	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5373	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5374	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5375	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5376	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5377	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
bogdanm	0:9b334a45a8ff	5378	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
bogdanm	0:9b334a45a8ff	5379	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5380	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5381	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5382	* @retval None
bogdanm	0:9b334a45a8ff	5383	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
bogdanm	0:9b334a45a8ff	5384	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm	0:9b334a45a8ff	5385	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5386	*/
bogdanm	0:9b334a45a8ff	5387	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5388	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5389	{
bogdanm	0:9b334a45a8ff	5390	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	5391	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5392
bogdanm	0:9b334a45a8ff	5393	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	5394	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	5395	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	5396	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5397
bogdanm	0:9b334a45a8ff	5398	/* Select the Input */
bogdanm	0:9b334a45a8ff	5399	tmpccmr2 &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	5400	tmpccmr2 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	5401
bogdanm	0:9b334a45a8ff	5402	/* Set the filter */
bogdanm	0:9b334a45a8ff	5403	tmpccmr2 &= ~TIM_CCMR2_IC4F;
bogdanm	0:9b334a45a8ff	5404	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
bogdanm	0:9b334a45a8ff	5405
bogdanm	0:9b334a45a8ff	5406	/* Select the Polarity and set the CC4E Bit */
bogdanm	0:9b334a45a8ff	5407	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
bogdanm	0:9b334a45a8ff	5408	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
bogdanm	0:9b334a45a8ff	5409
bogdanm	0:9b334a45a8ff	5410	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	5411	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	5412	TIMx->CCER = tmpccer ;
bogdanm	0:9b334a45a8ff	5413	}
bogdanm	0:9b334a45a8ff	5414
bogdanm	0:9b334a45a8ff	5415	/**
bogdanm	0:9b334a45a8ff	5416	* @brief Selects the Input Trigger source
bogdanm	0:9b334a45a8ff	5417	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5418	* @param TIM_ITRx: The Input Trigger source.
bogdanm	0:9b334a45a8ff	5419	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5420	* @arg TIM_TS_ITR0: Internal Trigger 0
bogdanm	0:9b334a45a8ff	5421	* @arg TIM_TS_ITR1: Internal Trigger 1
bogdanm	0:9b334a45a8ff	5422	* @arg TIM_TS_ITR2: Internal Trigger 2
bogdanm	0:9b334a45a8ff	5423	* @arg TIM_TS_ITR3: Internal Trigger 3
bogdanm	0:9b334a45a8ff	5424	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
bogdanm	0:9b334a45a8ff	5425	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
bogdanm	0:9b334a45a8ff	5426	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
bogdanm	0:9b334a45a8ff	5427	* @arg TIM_TS_ETRF: External Trigger input
bogdanm	0:9b334a45a8ff	5428	* @retval None
bogdanm	0:9b334a45a8ff	5429	*/
bogdanm	0:9b334a45a8ff	5430	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
bogdanm	0:9b334a45a8ff	5431	{
bogdanm	0:9b334a45a8ff	5432	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	5433
bogdanm	0:9b334a45a8ff	5434	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	5435	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	5436	/* Reset the TS Bits */
bogdanm	0:9b334a45a8ff	5437	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	5438	/* Set the Input Trigger source and the slave mode*/
bogdanm	0:9b334a45a8ff	5439	tmpsmcr \|= TIM_ITRx \| TIM_SLAVEMODE_EXTERNAL1;
bogdanm	0:9b334a45a8ff	5440	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	5441	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	5442	}
bogdanm	0:9b334a45a8ff	5443
bogdanm	0:9b334a45a8ff	5444	/**
bogdanm	0:9b334a45a8ff	5445	* @brief Configures the TIMx External Trigger (ETR).
bogdanm	0:9b334a45a8ff	5446	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5447	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
bogdanm	0:9b334a45a8ff	5448	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5449	* @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
bogdanm	0:9b334a45a8ff	5450	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
bogdanm	0:9b334a45a8ff	5451	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
bogdanm	0:9b334a45a8ff	5452	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
bogdanm	0:9b334a45a8ff	5453	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
bogdanm	0:9b334a45a8ff	5454	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5455	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
bogdanm	0:9b334a45a8ff	5456	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
bogdanm	0:9b334a45a8ff	5457	* @param ExtTRGFilter: External Trigger Filter.
bogdanm	0:9b334a45a8ff	5458	* This parameter must be a value between 0x00 and 0x0F
bogdanm	0:9b334a45a8ff	5459	* @retval None
bogdanm	0:9b334a45a8ff	5460	*/
bogdanm	0:9b334a45a8ff	5461	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm	0:9b334a45a8ff	5462	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
bogdanm	0:9b334a45a8ff	5463	{
bogdanm	0:9b334a45a8ff	5464	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	5465
bogdanm	0:9b334a45a8ff	5466	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	5467
bogdanm	0:9b334a45a8ff	5468	/* Reset the ETR Bits */
bogdanm	0:9b334a45a8ff	5469	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	5470
bogdanm	0:9b334a45a8ff	5471	/* Set the Prescaler, the Filter value and the Polarity */
bogdanm	0:9b334a45a8ff	5472	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
bogdanm	0:9b334a45a8ff	5473
bogdanm	0:9b334a45a8ff	5474	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	5475	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	5476	}
bogdanm	0:9b334a45a8ff	5477
bogdanm	0:9b334a45a8ff	5478	/**
bogdanm	0:9b334a45a8ff	5479	* @brief Enables or disables the TIM Capture Compare Channel x.
bogdanm	0:9b334a45a8ff	5480	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5481	* @param Channel: specifies the TIM Channel
bogdanm	0:9b334a45a8ff	5482	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5483	* @arg TIM_Channel_1: TIM Channel 1
bogdanm	0:9b334a45a8ff	5484	* @arg TIM_Channel_2: TIM Channel 2
bogdanm	0:9b334a45a8ff	5485	* @arg TIM_Channel_3: TIM Channel 3
bogdanm	0:9b334a45a8ff	5486	* @arg TIM_Channel_4: TIM Channel 4
bogdanm	0:9b334a45a8ff	5487	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
bogdanm	0:9b334a45a8ff	5488	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
bogdanm	0:9b334a45a8ff	5489	* @retval None
bogdanm	0:9b334a45a8ff	5490	*/
bogdanm	0:9b334a45a8ff	5491	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
bogdanm	0:9b334a45a8ff	5492	{
bogdanm	0:9b334a45a8ff	5493	uint32_t tmp = 0;
bogdanm	0:9b334a45a8ff	5494
bogdanm	0:9b334a45a8ff	5495	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5496	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
bogdanm	0:9b334a45a8ff	5497	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	5498
bogdanm	0:9b334a45a8ff	5499	tmp = TIM_CCER_CC1E << Channel;
bogdanm	0:9b334a45a8ff	5500
bogdanm	0:9b334a45a8ff	5501	/* Reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	5502	TIMx->CCER &= ~tmp;
bogdanm	0:9b334a45a8ff	5503
bogdanm	0:9b334a45a8ff	5504	/* Set or reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	5505	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
bogdanm	0:9b334a45a8ff	5506	}
bogdanm	0:9b334a45a8ff	5507
bogdanm	0:9b334a45a8ff	5508
bogdanm	0:9b334a45a8ff	5509	/**
bogdanm	0:9b334a45a8ff	5510	* @}
bogdanm	0:9b334a45a8ff	5511	*/
bogdanm	0:9b334a45a8ff	5512
bogdanm	0:9b334a45a8ff	5513	#endif /* HAL_TIM_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	5514	/**
bogdanm	0:9b334a45a8ff	5515	* @}
bogdanm	0:9b334a45a8ff	5516	*/
bogdanm	0:9b334a45a8ff	5517
bogdanm	0:9b334a45a8ff	5518	/**
bogdanm	0:9b334a45a8ff	5519	* @}
bogdanm	0:9b334a45a8ff	5520	*/
bogdanm	0:9b334a45a8ff	5521	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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