mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 83:a036322b8637

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f7xx_hal_tim.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.1
bogdanm	0:9b334a45a8ff	6	* @date 25-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief TIM HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Timer (TIM) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Time Base Initialization
bogdanm	0:9b334a45a8ff	11	* + Time Base Start
bogdanm	0:9b334a45a8ff	12	* + Time Base Start Interruption
bogdanm	0:9b334a45a8ff	13	* + Time Base Start DMA
bogdanm	0:9b334a45a8ff	14	* + Time Output Compare/PWM Initialization
bogdanm	0:9b334a45a8ff	15	* + Time Output Compare/PWM Channel Configuration
bogdanm	0:9b334a45a8ff	16	* + Time Output Compare/PWM Start
bogdanm	0:9b334a45a8ff	17	* + Time Output Compare/PWM Start Interruption
bogdanm	0:9b334a45a8ff	18	* + Time Output Compare/PWM Start DMA
bogdanm	0:9b334a45a8ff	19	* + Time Input Capture Initialization
bogdanm	0:9b334a45a8ff	20	* + Time Input Capture Channel Configuration
bogdanm	0:9b334a45a8ff	21	* + Time Input Capture Start
bogdanm	0:9b334a45a8ff	22	* + Time Input Capture Start Interruption
bogdanm	0:9b334a45a8ff	23	* + Time Input Capture Start DMA
bogdanm	0:9b334a45a8ff	24	* + Time One Pulse Initialization
bogdanm	0:9b334a45a8ff	25	* + Time One Pulse Channel Configuration
bogdanm	0:9b334a45a8ff	26	* + Time One Pulse Start
bogdanm	0:9b334a45a8ff	27	* + Time Encoder Interface Initialization
bogdanm	0:9b334a45a8ff	28	* + Time Encoder Interface Start
bogdanm	0:9b334a45a8ff	29	* + Time Encoder Interface Start Interruption
bogdanm	0:9b334a45a8ff	30	* + Time Encoder Interface Start DMA
bogdanm	0:9b334a45a8ff	31	* + Commutation Event configuration with Interruption and DMA
bogdanm	0:9b334a45a8ff	32	* + Time OCRef clear configuration
bogdanm	0:9b334a45a8ff	33	* + Time External Clock configuration
bogdanm	0:9b334a45a8ff	34	@verbatim
bogdanm	0:9b334a45a8ff	35	==============================================================================
bogdanm	0:9b334a45a8ff	36	##### TIMER Generic features #####
bogdanm	0:9b334a45a8ff	37	==============================================================================
bogdanm	0:9b334a45a8ff	38	[..] The Timer features include:
bogdanm	0:9b334a45a8ff	39	(#) 16-bit up, down, up/down auto-reload counter.
bogdanm	0:9b334a45a8ff	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
bogdanm	0:9b334a45a8ff	41	counter clock frequency either by any factor between 1 and 65536.
bogdanm	0:9b334a45a8ff	42	(#) Up to 4 independent channels for:
bogdanm	0:9b334a45a8ff	43	(++) Input Capture
bogdanm	0:9b334a45a8ff	44	(++) Output Compare
bogdanm	0:9b334a45a8ff	45	(++) PWM generation (Edge and Center-aligned Mode)
bogdanm	0:9b334a45a8ff	46	(++) One-pulse mode output
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	49	==============================================================================
bogdanm	0:9b334a45a8ff	50	[..]
bogdanm	0:9b334a45a8ff	51	(#) Initialize the TIM low level resources by implementing the following functions
bogdanm	0:9b334a45a8ff	52	depending from feature used :
bogdanm	0:9b334a45a8ff	53	(++) Time Base : HAL_TIM_Base_MspInit()
bogdanm	0:9b334a45a8ff	54	(++) Input Capture : HAL_TIM_IC_MspInit()
bogdanm	0:9b334a45a8ff	55	(++) Output Compare : HAL_TIM_OC_MspInit()
bogdanm	0:9b334a45a8ff	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
bogdanm	0:9b334a45a8ff	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
bogdanm	0:9b334a45a8ff	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	(#) Initialize the TIM low level resources :
bogdanm	0:9b334a45a8ff	61	(##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	62	(##) TIM pins configuration
bogdanm	0:9b334a45a8ff	63	(+++) Enable the clock for the TIM GPIOs using the following function:
bogdanm	0:9b334a45a8ff	64	__GPIOx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	(#) The external Clock can be configured, if needed (the default clock is the
bogdanm	0:9b334a45a8ff	68	internal clock from the APBx), using the following function:
bogdanm	0:9b334a45a8ff	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
bogdanm	0:9b334a45a8ff	70	any start function.
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	(#) Configure the TIM in the desired functioning mode using one of the
bogdanm	0:9b334a45a8ff	73	initialization function of this driver:
bogdanm	0:9b334a45a8ff	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
bogdanm	0:9b334a45a8ff	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
bogdanm	0:9b334a45a8ff	76	Output Compare signal.
bogdanm	0:9b334a45a8ff	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
bogdanm	0:9b334a45a8ff	78	PWM signal.
bogdanm	0:9b334a45a8ff	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
bogdanm	0:9b334a45a8ff	80	external signal.
bogdanm	0:9b334a45a8ff	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
bogdanm	0:9b334a45a8ff	82	in One Pulse Mode.
bogdanm	0:9b334a45a8ff	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
bogdanm	0:9b334a45a8ff	84
bogdanm	0:9b334a45a8ff	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
bogdanm	0:9b334a45a8ff	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
bogdanm	0:9b334a45a8ff	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
bogdanm	0:9b334a45a8ff	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
bogdanm	0:9b334a45a8ff	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
bogdanm	0:9b334a45a8ff	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
bogdanm	0:9b334a45a8ff	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	(#) The DMA Burst is managed with the two following functions:
bogdanm	0:9b334a45a8ff	94	HAL_TIM_DMABurst_WriteStart()
bogdanm	0:9b334a45a8ff	95	HAL_TIM_DMABurst_ReadStart()
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97	@endverbatim
bogdanm	0:9b334a45a8ff	98	******************************************************************************
bogdanm	0:9b334a45a8ff	99	* @attention
bogdanm	0:9b334a45a8ff	100	*
bogdanm	0:9b334a45a8ff	101	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	102	*
bogdanm	0:9b334a45a8ff	103	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	104	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	105	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	106	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	108	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	109	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	111	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	112	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	113	*
bogdanm	0:9b334a45a8ff	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	124	*
bogdanm	0:9b334a45a8ff	125	******************************************************************************
bogdanm	0:9b334a45a8ff	126	*/
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	129	#include "stm32f7xx_hal.h"
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	/** @addtogroup STM32F7xx_HAL_Driver
bogdanm	0:9b334a45a8ff	132	* @{
bogdanm	0:9b334a45a8ff	133	*/
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	/** @defgroup TIM TIM
bogdanm	0:9b334a45a8ff	136	* @brief TIM HAL module driver
bogdanm	0:9b334a45a8ff	137	* @{
bogdanm	0:9b334a45a8ff	138	*/
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	#ifdef HAL_TIM_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	143	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	144	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	145	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	146	/** @addtogroup TIM_Private_Functions
bogdanm	0:9b334a45a8ff	147	* @{
bogdanm	0:9b334a45a8ff	148	*/
bogdanm	0:9b334a45a8ff	149	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	150	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	151	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	152	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	153	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	154	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	155	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	156	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	157	uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
bogdanm	0:9b334a45a8ff	160	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	161	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	162	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	163	TIM_SlaveConfigTypeDef * sSlaveConfig);
bogdanm	0:9b334a45a8ff	164	/**
bogdanm	0:9b334a45a8ff	165	* @}
bogdanm	0:9b334a45a8ff	166	*/
bogdanm	0:9b334a45a8ff	167
bogdanm	0:9b334a45a8ff	168	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	169	/** @defgroup TIM_Exported_Functions TIM Exported Functions
bogdanm	0:9b334a45a8ff	170	* @{
bogdanm	0:9b334a45a8ff	171	*/
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
bogdanm	0:9b334a45a8ff	174	* @brief Time Base functions
bogdanm	0:9b334a45a8ff	175	*
bogdanm	0:9b334a45a8ff	176	@verbatim
bogdanm	0:9b334a45a8ff	177	==============================================================================
bogdanm	0:9b334a45a8ff	178	##### Time Base functions #####
bogdanm	0:9b334a45a8ff	179	==============================================================================
bogdanm	0:9b334a45a8ff	180	[..]
bogdanm	0:9b334a45a8ff	181	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	182	(+) Initialize and configure the TIM base.
bogdanm	0:9b334a45a8ff	183	(+) De-initialize the TIM base.
bogdanm	0:9b334a45a8ff	184	(+) Start the Time Base.
bogdanm	0:9b334a45a8ff	185	(+) Stop the Time Base.
bogdanm	0:9b334a45a8ff	186	(+) Start the Time Base and enable interrupt.
bogdanm	0:9b334a45a8ff	187	(+) Stop the Time Base and disable interrupt.
bogdanm	0:9b334a45a8ff	188	(+) Start the Time Base and enable DMA transfer.
bogdanm	0:9b334a45a8ff	189	(+) Stop the Time Base and disable DMA transfer.
bogdanm	0:9b334a45a8ff	190
bogdanm	0:9b334a45a8ff	191	@endverbatim
bogdanm	0:9b334a45a8ff	192	* @{
bogdanm	0:9b334a45a8ff	193	*/
bogdanm	0:9b334a45a8ff	194	/**
bogdanm	0:9b334a45a8ff	195	* @brief Initializes the TIM Time base Unit according to the specified
bogdanm	0:9b334a45a8ff	196	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	197	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	198	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	199	* @retval HAL status
bogdanm	0:9b334a45a8ff	200	*/
bogdanm	0:9b334a45a8ff	201	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	202	{
bogdanm	0:9b334a45a8ff	203	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	204	if(htim == NULL)
bogdanm	0:9b334a45a8ff	205	{
bogdanm	0:9b334a45a8ff	206	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	207	}
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	/* Check the parameters */
bogdanm	0:9b334a45a8ff	210	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	211	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	212	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	215	{
bogdanm	0:9b334a45a8ff	216	/* Init the low level hardware : GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	217	HAL_TIM_Base_MspInit(htim);
bogdanm	0:9b334a45a8ff	218	}
bogdanm	0:9b334a45a8ff	219
bogdanm	0:9b334a45a8ff	220	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	221	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	/* Set the Time Base configuration */
bogdanm	0:9b334a45a8ff	224	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	227	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	return HAL_OK;
bogdanm	0:9b334a45a8ff	230	}
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	/**
bogdanm	0:9b334a45a8ff	233	* @brief DeInitializes the TIM Base peripheral
bogdanm	0:9b334a45a8ff	234	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	235	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	236	* @retval HAL status
bogdanm	0:9b334a45a8ff	237	*/
bogdanm	0:9b334a45a8ff	238	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	239	{
bogdanm	0:9b334a45a8ff	240	/* Check the parameters */
bogdanm	0:9b334a45a8ff	241	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	246	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	249	HAL_TIM_Base_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	250
bogdanm	0:9b334a45a8ff	251	/* Change TIM state */
bogdanm	0:9b334a45a8ff	252	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	253
bogdanm	0:9b334a45a8ff	254	/* Release Lock */
bogdanm	0:9b334a45a8ff	255	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	256
bogdanm	0:9b334a45a8ff	257	return HAL_OK;
bogdanm	0:9b334a45a8ff	258	}
bogdanm	0:9b334a45a8ff	259
bogdanm	0:9b334a45a8ff	260	/**
bogdanm	0:9b334a45a8ff	261	* @brief Initializes the TIM Base MSP.
bogdanm	0:9b334a45a8ff	262	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	263	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	264	* @retval None
bogdanm	0:9b334a45a8ff	265	*/
bogdanm	0:9b334a45a8ff	266	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	267	{
bogdanm	0:9b334a45a8ff	268	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	269	the HAL_TIM_Base_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	270	*/
bogdanm	0:9b334a45a8ff	271	}
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/**
bogdanm	0:9b334a45a8ff	274	* @brief DeInitializes TIM Base MSP.
bogdanm	0:9b334a45a8ff	275	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	276	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	277	* @retval None
bogdanm	0:9b334a45a8ff	278	*/
bogdanm	0:9b334a45a8ff	279	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	280	{
bogdanm	0:9b334a45a8ff	281	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	282	the HAL_TIM_Base_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	283	*/
bogdanm	0:9b334a45a8ff	284	}
bogdanm	0:9b334a45a8ff	285
bogdanm	0:9b334a45a8ff	286	/**
bogdanm	0:9b334a45a8ff	287	* @brief Starts the TIM Base generation.
bogdanm	0:9b334a45a8ff	288	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	289	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	290	* @retval HAL status
bogdanm	0:9b334a45a8ff	291	*/
bogdanm	0:9b334a45a8ff	292	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	293	{
bogdanm	0:9b334a45a8ff	294	/* Check the parameters */
bogdanm	0:9b334a45a8ff	295	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	298	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	299
bogdanm	0:9b334a45a8ff	300	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	301	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	304	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/* Return function status */
bogdanm	0:9b334a45a8ff	307	return HAL_OK;
bogdanm	0:9b334a45a8ff	308	}
bogdanm	0:9b334a45a8ff	309
bogdanm	0:9b334a45a8ff	310	/**
bogdanm	0:9b334a45a8ff	311	* @brief Stops the TIM Base generation.
bogdanm	0:9b334a45a8ff	312	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	313	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	314	* @retval HAL status
bogdanm	0:9b334a45a8ff	315	*/
bogdanm	0:9b334a45a8ff	316	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	317	{
bogdanm	0:9b334a45a8ff	318	/* Check the parameters */
bogdanm	0:9b334a45a8ff	319	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	322	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	325	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	/* Change the TIM state*/
bogdanm	0:9b334a45a8ff	328	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/* Return function status */
bogdanm	0:9b334a45a8ff	331	return HAL_OK;
bogdanm	0:9b334a45a8ff	332	}
bogdanm	0:9b334a45a8ff	333
bogdanm	0:9b334a45a8ff	334	/**
bogdanm	0:9b334a45a8ff	335	* @brief Starts the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	336	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	337	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	338	* @retval HAL status
bogdanm	0:9b334a45a8ff	339	*/
bogdanm	0:9b334a45a8ff	340	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	341	{
bogdanm	0:9b334a45a8ff	342	/* Check the parameters */
bogdanm	0:9b334a45a8ff	343	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/* Enable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	346	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	349	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	/* Return function status */
bogdanm	0:9b334a45a8ff	352	return HAL_OK;
bogdanm	0:9b334a45a8ff	353	}
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/**
bogdanm	0:9b334a45a8ff	356	* @brief Stops the TIM Base generation in interrupt mode.
bogdanm	0:9b334a45a8ff	357	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	358	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	359	* @retval HAL status
bogdanm	0:9b334a45a8ff	360	*/
bogdanm	0:9b334a45a8ff	361	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	362	{
bogdanm	0:9b334a45a8ff	363	/* Check the parameters */
bogdanm	0:9b334a45a8ff	364	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	365	/* Disable the TIM Update interrupt */
bogdanm	0:9b334a45a8ff	366	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	369	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	/* Return function status */
bogdanm	0:9b334a45a8ff	372	return HAL_OK;
bogdanm	0:9b334a45a8ff	373	}
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	/**
bogdanm	0:9b334a45a8ff	376	* @brief Starts the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	377	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	378	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	379	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	380	* @param Length: The length of data to be transferred from memory to peripheral.
bogdanm	0:9b334a45a8ff	381	* @retval HAL status
bogdanm	0:9b334a45a8ff	382	*/
bogdanm	0:9b334a45a8ff	383	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	384	{
bogdanm	0:9b334a45a8ff	385	/* Check the parameters */
bogdanm	0:9b334a45a8ff	386	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	387
bogdanm	0:9b334a45a8ff	388	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	389	{
bogdanm	0:9b334a45a8ff	390	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	391	}
bogdanm	0:9b334a45a8ff	392	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	393	{
bogdanm	0:9b334a45a8ff	394	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	395	{
bogdanm	0:9b334a45a8ff	396	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	397	}
bogdanm	0:9b334a45a8ff	398	else
bogdanm	0:9b334a45a8ff	399	{
bogdanm	0:9b334a45a8ff	400	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	401	}
bogdanm	0:9b334a45a8ff	402	}
bogdanm	0:9b334a45a8ff	403	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	404	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	407	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	408
bogdanm	0:9b334a45a8ff	409	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	410	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	/* Enable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	413	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	416	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	/* Return function status */
bogdanm	0:9b334a45a8ff	419	return HAL_OK;
bogdanm	0:9b334a45a8ff	420	}
bogdanm	0:9b334a45a8ff	421
bogdanm	0:9b334a45a8ff	422	/**
bogdanm	0:9b334a45a8ff	423	* @brief Stops the TIM Base generation in DMA mode.
bogdanm	0:9b334a45a8ff	424	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	425	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	426	* @retval HAL status
bogdanm	0:9b334a45a8ff	427	*/
bogdanm	0:9b334a45a8ff	428	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	429	{
bogdanm	0:9b334a45a8ff	430	/* Check the parameters */
bogdanm	0:9b334a45a8ff	431	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	434	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm	0:9b334a45a8ff	435
bogdanm	0:9b334a45a8ff	436	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	437	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	/* Change the htim state */
bogdanm	0:9b334a45a8ff	440	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	441
bogdanm	0:9b334a45a8ff	442	/* Return function status */
bogdanm	0:9b334a45a8ff	443	return HAL_OK;
bogdanm	0:9b334a45a8ff	444	}
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	/**
bogdanm	0:9b334a45a8ff	447	* @}
bogdanm	0:9b334a45a8ff	448	*/
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
bogdanm	0:9b334a45a8ff	451	* @brief Time Output Compare functions
bogdanm	0:9b334a45a8ff	452	*
bogdanm	0:9b334a45a8ff	453	@verbatim
bogdanm	0:9b334a45a8ff	454	==============================================================================
bogdanm	0:9b334a45a8ff	455	##### Time Output Compare functions #####
bogdanm	0:9b334a45a8ff	456	==============================================================================
bogdanm	0:9b334a45a8ff	457	[..]
bogdanm	0:9b334a45a8ff	458	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	459	(+) Initialize and configure the TIM Output Compare.
bogdanm	0:9b334a45a8ff	460	(+) De-initialize the TIM Output Compare.
bogdanm	0:9b334a45a8ff	461	(+) Start the Time Output Compare.
bogdanm	0:9b334a45a8ff	462	(+) Stop the Time Output Compare.
bogdanm	0:9b334a45a8ff	463	(+) Start the Time Output Compare and enable interrupt.
bogdanm	0:9b334a45a8ff	464	(+) Stop the Time Output Compare and disable interrupt.
bogdanm	0:9b334a45a8ff	465	(+) Start the Time Output Compare and enable DMA transfer.
bogdanm	0:9b334a45a8ff	466	(+) Stop the Time Output Compare and disable DMA transfer.
bogdanm	0:9b334a45a8ff	467
bogdanm	0:9b334a45a8ff	468	@endverbatim
bogdanm	0:9b334a45a8ff	469	* @{
bogdanm	0:9b334a45a8ff	470	*/
bogdanm	0:9b334a45a8ff	471	/**
bogdanm	0:9b334a45a8ff	472	* @brief Initializes the TIM Output Compare according to the specified
bogdanm	0:9b334a45a8ff	473	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	474	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	475	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	476	* @retval HAL status
bogdanm	0:9b334a45a8ff	477	*/
bogdanm	0:9b334a45a8ff	478	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
bogdanm	0:9b334a45a8ff	479	{
bogdanm	0:9b334a45a8ff	480	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	481	if(htim == NULL)
bogdanm	0:9b334a45a8ff	482	{
bogdanm	0:9b334a45a8ff	483	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	484	}
bogdanm	0:9b334a45a8ff	485
bogdanm	0:9b334a45a8ff	486	/* Check the parameters */
bogdanm	0:9b334a45a8ff	487	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	488	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	489	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	490
bogdanm	0:9b334a45a8ff	491	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	492	{
bogdanm	0:9b334a45a8ff	493	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	494	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	495	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	496	HAL_TIM_OC_MspInit(htim);
bogdanm	0:9b334a45a8ff	497	}
bogdanm	0:9b334a45a8ff	498
bogdanm	0:9b334a45a8ff	499	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	500	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	501
bogdanm	0:9b334a45a8ff	502	/* Init the base time for the Output Compare */
bogdanm	0:9b334a45a8ff	503	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	504
bogdanm	0:9b334a45a8ff	505	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	506	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	507
bogdanm	0:9b334a45a8ff	508	return HAL_OK;
bogdanm	0:9b334a45a8ff	509	}
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	/**
bogdanm	0:9b334a45a8ff	512	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	513	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	514	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	515	* @retval HAL status
bogdanm	0:9b334a45a8ff	516	*/
bogdanm	0:9b334a45a8ff	517	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	518	{
bogdanm	0:9b334a45a8ff	519	/* Check the parameters */
bogdanm	0:9b334a45a8ff	520	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	521
bogdanm	0:9b334a45a8ff	522	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	525	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	528	HAL_TIM_OC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/* Change TIM state */
bogdanm	0:9b334a45a8ff	531	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	532
bogdanm	0:9b334a45a8ff	533	/* Release Lock */
bogdanm	0:9b334a45a8ff	534	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	return HAL_OK;
bogdanm	0:9b334a45a8ff	537	}
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	/**
bogdanm	0:9b334a45a8ff	540	* @brief Initializes the TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	541	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	542	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	543	* @retval None
bogdanm	0:9b334a45a8ff	544	*/
bogdanm	0:9b334a45a8ff	545	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	546	{
bogdanm	0:9b334a45a8ff	547	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	548	the HAL_TIM_OC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	549	*/
bogdanm	0:9b334a45a8ff	550	}
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	/**
bogdanm	0:9b334a45a8ff	553	* @brief DeInitializes TIM Output Compare MSP.
bogdanm	0:9b334a45a8ff	554	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	555	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	556	* @retval None
bogdanm	0:9b334a45a8ff	557	*/
bogdanm	0:9b334a45a8ff	558	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	559	{
bogdanm	0:9b334a45a8ff	560	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	561	the HAL_TIM_OC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	562	*/
bogdanm	0:9b334a45a8ff	563	}
bogdanm	0:9b334a45a8ff	564
bogdanm	0:9b334a45a8ff	565	/**
bogdanm	0:9b334a45a8ff	566	* @brief Starts the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	567	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	568	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	569	* @param Channel: TIM Channel to be enabled.
bogdanm	0:9b334a45a8ff	570	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	571	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	572	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	573	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	574	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	575	* @retval HAL status
bogdanm	0:9b334a45a8ff	576	*/
bogdanm	0:9b334a45a8ff	577	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	578	{
bogdanm	0:9b334a45a8ff	579	/* Check the parameters */
bogdanm	0:9b334a45a8ff	580	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	581
bogdanm	0:9b334a45a8ff	582	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	583	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	584
bogdanm	0:9b334a45a8ff	585	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	586	{
bogdanm	0:9b334a45a8ff	587	/* Enable the main output */
bogdanm	0:9b334a45a8ff	588	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	589	}
bogdanm	0:9b334a45a8ff	590
bogdanm	0:9b334a45a8ff	591	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	592	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594	/* Return function status */
bogdanm	0:9b334a45a8ff	595	return HAL_OK;
bogdanm	0:9b334a45a8ff	596	}
bogdanm	0:9b334a45a8ff	597
bogdanm	0:9b334a45a8ff	598	/**
bogdanm	0:9b334a45a8ff	599	* @brief Stops the TIM Output Compare signal generation.
bogdanm	0:9b334a45a8ff	600	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	601	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	602	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	603	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	604	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	605	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	606	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	607	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	608	* @retval HAL status
bogdanm	0:9b334a45a8ff	609	*/
bogdanm	0:9b334a45a8ff	610	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	611	{
bogdanm	0:9b334a45a8ff	612	/* Check the parameters */
bogdanm	0:9b334a45a8ff	613	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	614
bogdanm	0:9b334a45a8ff	615	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	616	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	617
bogdanm	0:9b334a45a8ff	618	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	619	{
bogdanm	0:9b334a45a8ff	620	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	621	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	622	}
bogdanm	0:9b334a45a8ff	623
bogdanm	0:9b334a45a8ff	624	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	625	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	/* Return function status */
bogdanm	0:9b334a45a8ff	628	return HAL_OK;
bogdanm	0:9b334a45a8ff	629	}
bogdanm	0:9b334a45a8ff	630
bogdanm	0:9b334a45a8ff	631	/**
bogdanm	0:9b334a45a8ff	632	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	633	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	634	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	635	* @param Channel: TIM Channel to be enabled.
bogdanm	0:9b334a45a8ff	636	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	637	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	638	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	639	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	640	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	641	* @retval HAL status
bogdanm	0:9b334a45a8ff	642	*/
bogdanm	0:9b334a45a8ff	643	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	644	{
bogdanm	0:9b334a45a8ff	645	/* Check the parameters */
bogdanm	0:9b334a45a8ff	646	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	switch (Channel)
bogdanm	0:9b334a45a8ff	649	{
bogdanm	0:9b334a45a8ff	650	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	651	{
bogdanm	0:9b334a45a8ff	652	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	653	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	654	}
bogdanm	0:9b334a45a8ff	655	break;
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	658	{
bogdanm	0:9b334a45a8ff	659	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	660	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	661	}
bogdanm	0:9b334a45a8ff	662	break;
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	665	{
bogdanm	0:9b334a45a8ff	666	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	667	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	668	}
bogdanm	0:9b334a45a8ff	669	break;
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	672	{
bogdanm	0:9b334a45a8ff	673	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	674	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	675	}
bogdanm	0:9b334a45a8ff	676	break;
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	default:
bogdanm	0:9b334a45a8ff	679	break;
bogdanm	0:9b334a45a8ff	680	}
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	683	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	684
bogdanm	0:9b334a45a8ff	685	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	686	{
bogdanm	0:9b334a45a8ff	687	/* Enable the main output */
bogdanm	0:9b334a45a8ff	688	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	689	}
bogdanm	0:9b334a45a8ff	690
bogdanm	0:9b334a45a8ff	691	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	692	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	/* Return function status */
bogdanm	0:9b334a45a8ff	695	return HAL_OK;
bogdanm	0:9b334a45a8ff	696	}
bogdanm	0:9b334a45a8ff	697
bogdanm	0:9b334a45a8ff	698	/**
bogdanm	0:9b334a45a8ff	699	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	700	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	701	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	702	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	703	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	704	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	705	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	706	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	707	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	708	* @retval HAL status
bogdanm	0:9b334a45a8ff	709	*/
bogdanm	0:9b334a45a8ff	710	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	/* Check the parameters */
bogdanm	0:9b334a45a8ff	713	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	switch (Channel)
bogdanm	0:9b334a45a8ff	716	{
bogdanm	0:9b334a45a8ff	717	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	718	{
bogdanm	0:9b334a45a8ff	719	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	720	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	721	}
bogdanm	0:9b334a45a8ff	722	break;
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	725	{
bogdanm	0:9b334a45a8ff	726	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	727	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	728	}
bogdanm	0:9b334a45a8ff	729	break;
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	732	{
bogdanm	0:9b334a45a8ff	733	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	734	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	735	}
bogdanm	0:9b334a45a8ff	736	break;
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	739	{
bogdanm	0:9b334a45a8ff	740	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	741	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	742	}
bogdanm	0:9b334a45a8ff	743	break;
bogdanm	0:9b334a45a8ff	744
bogdanm	0:9b334a45a8ff	745	default:
bogdanm	0:9b334a45a8ff	746	break;
bogdanm	0:9b334a45a8ff	747	}
bogdanm	0:9b334a45a8ff	748
bogdanm	0:9b334a45a8ff	749	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	750	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	751
bogdanm	0:9b334a45a8ff	752	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	753	{
bogdanm	0:9b334a45a8ff	754	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	755	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	756	}
bogdanm	0:9b334a45a8ff	757
bogdanm	0:9b334a45a8ff	758	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	759	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	760
bogdanm	0:9b334a45a8ff	761	/* Return function status */
bogdanm	0:9b334a45a8ff	762	return HAL_OK;
bogdanm	0:9b334a45a8ff	763	}
bogdanm	0:9b334a45a8ff	764
bogdanm	0:9b334a45a8ff	765	/**
bogdanm	0:9b334a45a8ff	766	* @brief Starts the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	767	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	768	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	769	* @param Channel: TIM Channel to be enabled.
bogdanm	0:9b334a45a8ff	770	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	771	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	772	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	773	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	774	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	775	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	776	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	777	* @retval HAL status
bogdanm	0:9b334a45a8ff	778	*/
bogdanm	0:9b334a45a8ff	779	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	780	{
bogdanm	0:9b334a45a8ff	781	/* Check the parameters */
bogdanm	0:9b334a45a8ff	782	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	783
bogdanm	0:9b334a45a8ff	784	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	785	{
bogdanm	0:9b334a45a8ff	786	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	787	}
bogdanm	0:9b334a45a8ff	788	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	789	{
bogdanm	0:9b334a45a8ff	790	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	791	{
bogdanm	0:9b334a45a8ff	792	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	793	}
bogdanm	0:9b334a45a8ff	794	else
bogdanm	0:9b334a45a8ff	795	{
bogdanm	0:9b334a45a8ff	796	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	797	}
bogdanm	0:9b334a45a8ff	798	}
bogdanm	0:9b334a45a8ff	799	switch (Channel)
bogdanm	0:9b334a45a8ff	800	{
bogdanm	0:9b334a45a8ff	801	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	802	{
bogdanm	0:9b334a45a8ff	803	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	804	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	805
bogdanm	0:9b334a45a8ff	806	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	807	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	808
bogdanm	0:9b334a45a8ff	809	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	810	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	811
bogdanm	0:9b334a45a8ff	812	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	813	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	814	}
bogdanm	0:9b334a45a8ff	815	break;
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	818	{
bogdanm	0:9b334a45a8ff	819	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	820	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	823	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	826	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	829	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	830	}
bogdanm	0:9b334a45a8ff	831	break;
bogdanm	0:9b334a45a8ff	832
bogdanm	0:9b334a45a8ff	833	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	834	{
bogdanm	0:9b334a45a8ff	835	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	836	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	839	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	840
bogdanm	0:9b334a45a8ff	841	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	842	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	845	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	846	}
bogdanm	0:9b334a45a8ff	847	break;
bogdanm	0:9b334a45a8ff	848
bogdanm	0:9b334a45a8ff	849	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	850	{
bogdanm	0:9b334a45a8ff	851	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	852	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	855	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	858	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	861	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	862	}
bogdanm	0:9b334a45a8ff	863	break;
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	default:
bogdanm	0:9b334a45a8ff	866	break;
bogdanm	0:9b334a45a8ff	867	}
bogdanm	0:9b334a45a8ff	868
bogdanm	0:9b334a45a8ff	869	/* Enable the Output compare channel */
bogdanm	0:9b334a45a8ff	870	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	871
bogdanm	0:9b334a45a8ff	872	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	873	{
bogdanm	0:9b334a45a8ff	874	/* Enable the main output */
bogdanm	0:9b334a45a8ff	875	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	876	}
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	879	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	880
bogdanm	0:9b334a45a8ff	881	/* Return function status */
bogdanm	0:9b334a45a8ff	882	return HAL_OK;
bogdanm	0:9b334a45a8ff	883	}
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	/**
bogdanm	0:9b334a45a8ff	886	* @brief Stops the TIM Output Compare signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	887	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	888	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	889	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	890	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	891	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	892	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	893	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	894	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	895	* @retval HAL status
bogdanm	0:9b334a45a8ff	896	*/
bogdanm	0:9b334a45a8ff	897	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	898	{
bogdanm	0:9b334a45a8ff	899	/* Check the parameters */
bogdanm	0:9b334a45a8ff	900	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	901
bogdanm	0:9b334a45a8ff	902	switch (Channel)
bogdanm	0:9b334a45a8ff	903	{
bogdanm	0:9b334a45a8ff	904	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	905	{
bogdanm	0:9b334a45a8ff	906	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	907	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	908	}
bogdanm	0:9b334a45a8ff	909	break;
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	912	{
bogdanm	0:9b334a45a8ff	913	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	914	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	915	}
bogdanm	0:9b334a45a8ff	916	break;
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	919	{
bogdanm	0:9b334a45a8ff	920	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	921	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	922	}
bogdanm	0:9b334a45a8ff	923	break;
bogdanm	0:9b334a45a8ff	924
bogdanm	0:9b334a45a8ff	925	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	926	{
bogdanm	0:9b334a45a8ff	927	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	928	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	929	}
bogdanm	0:9b334a45a8ff	930	break;
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	default:
bogdanm	0:9b334a45a8ff	933	break;
bogdanm	0:9b334a45a8ff	934	}
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936	/* Disable the Output compare channel */
bogdanm	0:9b334a45a8ff	937	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	938
bogdanm	0:9b334a45a8ff	939	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	940	{
bogdanm	0:9b334a45a8ff	941	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	942	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	943	}
bogdanm	0:9b334a45a8ff	944
bogdanm	0:9b334a45a8ff	945	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	946	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	947
bogdanm	0:9b334a45a8ff	948	/* Change the htim state */
bogdanm	0:9b334a45a8ff	949	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	950
bogdanm	0:9b334a45a8ff	951	/* Return function status */
bogdanm	0:9b334a45a8ff	952	return HAL_OK;
bogdanm	0:9b334a45a8ff	953	}
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	/**
bogdanm	0:9b334a45a8ff	956	* @}
bogdanm	0:9b334a45a8ff	957	*/
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
bogdanm	0:9b334a45a8ff	960	* @brief Time PWM functions
bogdanm	0:9b334a45a8ff	961	*
bogdanm	0:9b334a45a8ff	962	@verbatim
bogdanm	0:9b334a45a8ff	963	==============================================================================
bogdanm	0:9b334a45a8ff	964	##### Time PWM functions #####
bogdanm	0:9b334a45a8ff	965	==============================================================================
bogdanm	0:9b334a45a8ff	966	[..]
bogdanm	0:9b334a45a8ff	967	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	968	(+) Initialize and configure the TIM OPWM.
bogdanm	0:9b334a45a8ff	969	(+) De-initialize the TIM PWM.
bogdanm	0:9b334a45a8ff	970	(+) Start the Time PWM.
bogdanm	0:9b334a45a8ff	971	(+) Stop the Time PWM.
bogdanm	0:9b334a45a8ff	972	(+) Start the Time PWM and enable interrupt.
bogdanm	0:9b334a45a8ff	973	(+) Stop the Time PWM and disable interrupt.
bogdanm	0:9b334a45a8ff	974	(+) Start the Time PWM and enable DMA transfer.
bogdanm	0:9b334a45a8ff	975	(+) Stop the Time PWM and disable DMA transfer.
bogdanm	0:9b334a45a8ff	976
bogdanm	0:9b334a45a8ff	977	@endverbatim
bogdanm	0:9b334a45a8ff	978	* @{
bogdanm	0:9b334a45a8ff	979	*/
bogdanm	0:9b334a45a8ff	980	/**
bogdanm	0:9b334a45a8ff	981	* @brief Initializes the TIM PWM Time Base according to the specified
bogdanm	0:9b334a45a8ff	982	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	983	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	984	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	985	* @retval HAL status
bogdanm	0:9b334a45a8ff	986	*/
bogdanm	0:9b334a45a8ff	987	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	988	{
bogdanm	0:9b334a45a8ff	989	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	990	if(htim == NULL)
bogdanm	0:9b334a45a8ff	991	{
bogdanm	0:9b334a45a8ff	992	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	993	}
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995	/* Check the parameters */
bogdanm	0:9b334a45a8ff	996	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	997	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	998	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	999
bogdanm	0:9b334a45a8ff	1000	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1001	{
bogdanm	0:9b334a45a8ff	1002	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	1003	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	1004	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1005	HAL_TIM_PWM_MspInit(htim);
bogdanm	0:9b334a45a8ff	1006	}
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1009	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1010
bogdanm	0:9b334a45a8ff	1011	/* Init the base time for the PWM */
bogdanm	0:9b334a45a8ff	1012	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1015	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	return HAL_OK;
bogdanm	0:9b334a45a8ff	1018	}
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	/**
bogdanm	0:9b334a45a8ff	1021	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	1022	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1023	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1024	* @retval HAL status
bogdanm	0:9b334a45a8ff	1025	*/
bogdanm	0:9b334a45a8ff	1026	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1027	{
bogdanm	0:9b334a45a8ff	1028	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1029	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1032
bogdanm	0:9b334a45a8ff	1033	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1034	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1035
bogdanm	0:9b334a45a8ff	1036	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1037	HAL_TIM_PWM_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1040	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1041
bogdanm	0:9b334a45a8ff	1042	/* Release Lock */
bogdanm	0:9b334a45a8ff	1043	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1044
bogdanm	0:9b334a45a8ff	1045	return HAL_OK;
bogdanm	0:9b334a45a8ff	1046	}
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	/**
bogdanm	0:9b334a45a8ff	1049	* @brief Initializes the TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1050	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1051	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1052	* @retval None
bogdanm	0:9b334a45a8ff	1053	*/
bogdanm	0:9b334a45a8ff	1054	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1055	{
bogdanm	0:9b334a45a8ff	1056	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1057	the HAL_TIM_PWM_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1058	*/
bogdanm	0:9b334a45a8ff	1059	}
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	/**
bogdanm	0:9b334a45a8ff	1062	* @brief DeInitializes TIM PWM MSP.
bogdanm	0:9b334a45a8ff	1063	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1064	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1065	* @retval None
bogdanm	0:9b334a45a8ff	1066	*/
bogdanm	0:9b334a45a8ff	1067	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1068	{
bogdanm	0:9b334a45a8ff	1069	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1070	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1071	*/
bogdanm	0:9b334a45a8ff	1072	}
bogdanm	0:9b334a45a8ff	1073
bogdanm	0:9b334a45a8ff	1074	/**
bogdanm	0:9b334a45a8ff	1075	* @brief Starts the PWM signal generation.
bogdanm	0:9b334a45a8ff	1076	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1077	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1078	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1079	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1080	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1081	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1082	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1083	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1084	* @retval HAL status
bogdanm	0:9b334a45a8ff	1085	*/
bogdanm	0:9b334a45a8ff	1086	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1087	{
bogdanm	0:9b334a45a8ff	1088	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1089	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1092	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1093
bogdanm	0:9b334a45a8ff	1094	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1095	{
bogdanm	0:9b334a45a8ff	1096	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1097	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1098	}
bogdanm	0:9b334a45a8ff	1099
bogdanm	0:9b334a45a8ff	1100	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1101	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	/* Return function status */
bogdanm	0:9b334a45a8ff	1104	return HAL_OK;
bogdanm	0:9b334a45a8ff	1105	}
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	/**
bogdanm	0:9b334a45a8ff	1108	* @brief Stops the PWM signal generation.
bogdanm	0:9b334a45a8ff	1109	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1110	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1111	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1112	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1113	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1114	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1115	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1116	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1117	* @retval HAL status
bogdanm	0:9b334a45a8ff	1118	*/
bogdanm	0:9b334a45a8ff	1119	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1120	{
bogdanm	0:9b334a45a8ff	1121	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1122	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1125	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1126
bogdanm	0:9b334a45a8ff	1127	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1128	{
bogdanm	0:9b334a45a8ff	1129	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	1130	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1131	}
bogdanm	0:9b334a45a8ff	1132
bogdanm	0:9b334a45a8ff	1133	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1134	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1135
bogdanm	0:9b334a45a8ff	1136	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1137	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1138
bogdanm	0:9b334a45a8ff	1139	/* Return function status */
bogdanm	0:9b334a45a8ff	1140	return HAL_OK;
bogdanm	0:9b334a45a8ff	1141	}
bogdanm	0:9b334a45a8ff	1142
bogdanm	0:9b334a45a8ff	1143	/**
bogdanm	0:9b334a45a8ff	1144	* @brief Starts the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1145	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1146	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1147	* @param Channel: TIM Channel to be disabled.
bogdanm	0:9b334a45a8ff	1148	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1149	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1150	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1151	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1152	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1153	* @retval HAL status
bogdanm	0:9b334a45a8ff	1154	*/
bogdanm	0:9b334a45a8ff	1155	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1156	{
bogdanm	0:9b334a45a8ff	1157	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1158	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1159
bogdanm	0:9b334a45a8ff	1160	switch (Channel)
bogdanm	0:9b334a45a8ff	1161	{
bogdanm	0:9b334a45a8ff	1162	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1163	{
bogdanm	0:9b334a45a8ff	1164	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1165	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1166	}
bogdanm	0:9b334a45a8ff	1167	break;
bogdanm	0:9b334a45a8ff	1168
bogdanm	0:9b334a45a8ff	1169	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1170	{
bogdanm	0:9b334a45a8ff	1171	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1172	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1173	}
bogdanm	0:9b334a45a8ff	1174	break;
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1177	{
bogdanm	0:9b334a45a8ff	1178	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1179	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1180	}
bogdanm	0:9b334a45a8ff	1181	break;
bogdanm	0:9b334a45a8ff	1182
bogdanm	0:9b334a45a8ff	1183	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1184	{
bogdanm	0:9b334a45a8ff	1185	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1186	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1187	}
bogdanm	0:9b334a45a8ff	1188	break;
bogdanm	0:9b334a45a8ff	1189
bogdanm	0:9b334a45a8ff	1190	default:
bogdanm	0:9b334a45a8ff	1191	break;
bogdanm	0:9b334a45a8ff	1192	}
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1195	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1196
bogdanm	0:9b334a45a8ff	1197	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1198	{
bogdanm	0:9b334a45a8ff	1199	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1200	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1201	}
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1204	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206	/* Return function status */
bogdanm	0:9b334a45a8ff	1207	return HAL_OK;
bogdanm	0:9b334a45a8ff	1208	}
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	/**
bogdanm	0:9b334a45a8ff	1211	* @brief Stops the PWM signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	1212	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1213	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1214	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1215	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1216	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1217	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1218	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1219	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1220	* @retval HAL status
bogdanm	0:9b334a45a8ff	1221	*/
bogdanm	0:9b334a45a8ff	1222	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1223	{
bogdanm	0:9b334a45a8ff	1224	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1225	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	switch (Channel)
bogdanm	0:9b334a45a8ff	1228	{
bogdanm	0:9b334a45a8ff	1229	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1230	{
bogdanm	0:9b334a45a8ff	1231	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1232	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1233	}
bogdanm	0:9b334a45a8ff	1234	break;
bogdanm	0:9b334a45a8ff	1235
bogdanm	0:9b334a45a8ff	1236	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1237	{
bogdanm	0:9b334a45a8ff	1238	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1239	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1240	}
bogdanm	0:9b334a45a8ff	1241	break;
bogdanm	0:9b334a45a8ff	1242
bogdanm	0:9b334a45a8ff	1243	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1244	{
bogdanm	0:9b334a45a8ff	1245	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1246	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1247	}
bogdanm	0:9b334a45a8ff	1248	break;
bogdanm	0:9b334a45a8ff	1249
bogdanm	0:9b334a45a8ff	1250	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1251	{
bogdanm	0:9b334a45a8ff	1252	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1253	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1254	}
bogdanm	0:9b334a45a8ff	1255	break;
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257	default:
bogdanm	0:9b334a45a8ff	1258	break;
bogdanm	0:9b334a45a8ff	1259	}
bogdanm	0:9b334a45a8ff	1260
bogdanm	0:9b334a45a8ff	1261	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1262	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1265	{
bogdanm	0:9b334a45a8ff	1266	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	1267	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1268	}
bogdanm	0:9b334a45a8ff	1269
bogdanm	0:9b334a45a8ff	1270	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1271	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1272
bogdanm	0:9b334a45a8ff	1273	/* Return function status */
bogdanm	0:9b334a45a8ff	1274	return HAL_OK;
bogdanm	0:9b334a45a8ff	1275	}
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277	/**
bogdanm	0:9b334a45a8ff	1278	* @brief Starts the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1279	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1280	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1281	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1282	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1283	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1284	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1285	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1286	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1287	* @param pData: The source Buffer address.
bogdanm	0:9b334a45a8ff	1288	* @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	1289	* @retval HAL status
bogdanm	0:9b334a45a8ff	1290	*/
bogdanm	0:9b334a45a8ff	1291	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1292	{
bogdanm	0:9b334a45a8ff	1293	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1294	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1297	{
bogdanm	0:9b334a45a8ff	1298	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1299	}
bogdanm	0:9b334a45a8ff	1300	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1301	{
bogdanm	0:9b334a45a8ff	1302	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1303	{
bogdanm	0:9b334a45a8ff	1304	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1305	}
bogdanm	0:9b334a45a8ff	1306	else
bogdanm	0:9b334a45a8ff	1307	{
bogdanm	0:9b334a45a8ff	1308	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1309	}
bogdanm	0:9b334a45a8ff	1310	}
bogdanm	0:9b334a45a8ff	1311	switch (Channel)
bogdanm	0:9b334a45a8ff	1312	{
bogdanm	0:9b334a45a8ff	1313	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1314	{
bogdanm	0:9b334a45a8ff	1315	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1316	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1319	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1322	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	1323
bogdanm	0:9b334a45a8ff	1324	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1325	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1326	}
bogdanm	0:9b334a45a8ff	1327	break;
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1330	{
bogdanm	0:9b334a45a8ff	1331	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1332	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1335	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1336
bogdanm	0:9b334a45a8ff	1337	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1338	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	1339
bogdanm	0:9b334a45a8ff	1340	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1341	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1342	}
bogdanm	0:9b334a45a8ff	1343	break;
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1346	{
bogdanm	0:9b334a45a8ff	1347	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1348	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1349
bogdanm	0:9b334a45a8ff	1350	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1351	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1352
bogdanm	0:9b334a45a8ff	1353	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1354	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	1355
bogdanm	0:9b334a45a8ff	1356	/* Enable the TIM Output Capture/Compare 3 request */
bogdanm	0:9b334a45a8ff	1357	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1358	}
bogdanm	0:9b334a45a8ff	1359	break;
bogdanm	0:9b334a45a8ff	1360
bogdanm	0:9b334a45a8ff	1361	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1362	{
bogdanm	0:9b334a45a8ff	1363	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1364	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1367	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1368
bogdanm	0:9b334a45a8ff	1369	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1370	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1373	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1374	}
bogdanm	0:9b334a45a8ff	1375	break;
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	default:
bogdanm	0:9b334a45a8ff	1378	break;
bogdanm	0:9b334a45a8ff	1379	}
bogdanm	0:9b334a45a8ff	1380
bogdanm	0:9b334a45a8ff	1381	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1382	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1383
bogdanm	0:9b334a45a8ff	1384	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1385	{
bogdanm	0:9b334a45a8ff	1386	/* Enable the main output */
bogdanm	0:9b334a45a8ff	1387	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1388	}
bogdanm	0:9b334a45a8ff	1389
bogdanm	0:9b334a45a8ff	1390	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1391	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1392
bogdanm	0:9b334a45a8ff	1393	/* Return function status */
bogdanm	0:9b334a45a8ff	1394	return HAL_OK;
bogdanm	0:9b334a45a8ff	1395	}
bogdanm	0:9b334a45a8ff	1396
bogdanm	0:9b334a45a8ff	1397	/**
bogdanm	0:9b334a45a8ff	1398	* @brief Stops the TIM PWM signal generation in DMA mode.
bogdanm	0:9b334a45a8ff	1399	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1400	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1401	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1402	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1403	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1404	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1405	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1406	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1407	* @retval HAL status
bogdanm	0:9b334a45a8ff	1408	*/
bogdanm	0:9b334a45a8ff	1409	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1410	{
bogdanm	0:9b334a45a8ff	1411	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1412	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1413
bogdanm	0:9b334a45a8ff	1414	switch (Channel)
bogdanm	0:9b334a45a8ff	1415	{
bogdanm	0:9b334a45a8ff	1416	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1417	{
bogdanm	0:9b334a45a8ff	1418	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1419	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1420	}
bogdanm	0:9b334a45a8ff	1421	break;
bogdanm	0:9b334a45a8ff	1422
bogdanm	0:9b334a45a8ff	1423	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1424	{
bogdanm	0:9b334a45a8ff	1425	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1426	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1427	}
bogdanm	0:9b334a45a8ff	1428	break;
bogdanm	0:9b334a45a8ff	1429
bogdanm	0:9b334a45a8ff	1430	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1431	{
bogdanm	0:9b334a45a8ff	1432	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1433	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1434	}
bogdanm	0:9b334a45a8ff	1435	break;
bogdanm	0:9b334a45a8ff	1436
bogdanm	0:9b334a45a8ff	1437	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1438	{
bogdanm	0:9b334a45a8ff	1439	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1440	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1441	}
bogdanm	0:9b334a45a8ff	1442	break;
bogdanm	0:9b334a45a8ff	1443
bogdanm	0:9b334a45a8ff	1444	default:
bogdanm	0:9b334a45a8ff	1445	break;
bogdanm	0:9b334a45a8ff	1446	}
bogdanm	0:9b334a45a8ff	1447
bogdanm	0:9b334a45a8ff	1448	/* Disable the Capture compare channel */
bogdanm	0:9b334a45a8ff	1449	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1450
bogdanm	0:9b334a45a8ff	1451	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	1452	{
bogdanm	0:9b334a45a8ff	1453	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	1454	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1455	}
bogdanm	0:9b334a45a8ff	1456
bogdanm	0:9b334a45a8ff	1457	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1458	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1459
bogdanm	0:9b334a45a8ff	1460	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1461	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1462
bogdanm	0:9b334a45a8ff	1463	/* Return function status */
bogdanm	0:9b334a45a8ff	1464	return HAL_OK;
bogdanm	0:9b334a45a8ff	1465	}
bogdanm	0:9b334a45a8ff	1466
bogdanm	0:9b334a45a8ff	1467	/**
bogdanm	0:9b334a45a8ff	1468	* @}
bogdanm	0:9b334a45a8ff	1469	*/
bogdanm	0:9b334a45a8ff	1470
bogdanm	0:9b334a45a8ff	1471	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
bogdanm	0:9b334a45a8ff	1472	* @brief Time Input Capture functions
bogdanm	0:9b334a45a8ff	1473	*
bogdanm	0:9b334a45a8ff	1474	@verbatim
bogdanm	0:9b334a45a8ff	1475	==============================================================================
bogdanm	0:9b334a45a8ff	1476	##### Time Input Capture functions #####
bogdanm	0:9b334a45a8ff	1477	==============================================================================
bogdanm	0:9b334a45a8ff	1478	[..]
bogdanm	0:9b334a45a8ff	1479	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1480	(+) Initialize and configure the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1481	(+) De-initialize the TIM Input Capture.
bogdanm	0:9b334a45a8ff	1482	(+) Start the Time Input Capture.
bogdanm	0:9b334a45a8ff	1483	(+) Stop the Time Input Capture.
bogdanm	0:9b334a45a8ff	1484	(+) Start the Time Input Capture and enable interrupt.
bogdanm	0:9b334a45a8ff	1485	(+) Stop the Time Input Capture and disable interrupt.
bogdanm	0:9b334a45a8ff	1486	(+) Start the Time Input Capture and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1487	(+) Stop the Time Input Capture and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1488
bogdanm	0:9b334a45a8ff	1489	@endverbatim
bogdanm	0:9b334a45a8ff	1490	* @{
bogdanm	0:9b334a45a8ff	1491	*/
bogdanm	0:9b334a45a8ff	1492	/**
bogdanm	0:9b334a45a8ff	1493	* @brief Initializes the TIM Input Capture Time base according to the specified
bogdanm	0:9b334a45a8ff	1494	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	1495	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1496	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1497	* @retval HAL status
bogdanm	0:9b334a45a8ff	1498	*/
bogdanm	0:9b334a45a8ff	1499	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1500	{
bogdanm	0:9b334a45a8ff	1501	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1502	if(htim == NULL)
bogdanm	0:9b334a45a8ff	1503	{
bogdanm	0:9b334a45a8ff	1504	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1505	}
bogdanm	0:9b334a45a8ff	1506
bogdanm	0:9b334a45a8ff	1507	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1508	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1509	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1510	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1511
bogdanm	0:9b334a45a8ff	1512	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1513	{
bogdanm	0:9b334a45a8ff	1514	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	1515	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	1516	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1517	HAL_TIM_IC_MspInit(htim);
bogdanm	0:9b334a45a8ff	1518	}
bogdanm	0:9b334a45a8ff	1519
bogdanm	0:9b334a45a8ff	1520	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	1521	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1522
bogdanm	0:9b334a45a8ff	1523	/* Init the base time for the input capture */
bogdanm	0:9b334a45a8ff	1524	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	1525
bogdanm	0:9b334a45a8ff	1526	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	1527	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1528
bogdanm	0:9b334a45a8ff	1529	return HAL_OK;
bogdanm	0:9b334a45a8ff	1530	}
bogdanm	0:9b334a45a8ff	1531
bogdanm	0:9b334a45a8ff	1532	/**
bogdanm	0:9b334a45a8ff	1533	* @brief DeInitializes the TIM peripheral
bogdanm	0:9b334a45a8ff	1534	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1535	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1536	* @retval HAL status
bogdanm	0:9b334a45a8ff	1537	*/
bogdanm	0:9b334a45a8ff	1538	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1539	{
bogdanm	0:9b334a45a8ff	1540	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1541	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1542
bogdanm	0:9b334a45a8ff	1543	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1544
bogdanm	0:9b334a45a8ff	1545	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	1546	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1547
bogdanm	0:9b334a45a8ff	1548	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1549	HAL_TIM_IC_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	1550
bogdanm	0:9b334a45a8ff	1551	/* Change TIM state */
bogdanm	0:9b334a45a8ff	1552	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	1553
bogdanm	0:9b334a45a8ff	1554	/* Release Lock */
bogdanm	0:9b334a45a8ff	1555	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1556
bogdanm	0:9b334a45a8ff	1557	return HAL_OK;
bogdanm	0:9b334a45a8ff	1558	}
bogdanm	0:9b334a45a8ff	1559
bogdanm	0:9b334a45a8ff	1560	/**
bogdanm	0:9b334a45a8ff	1561	* @brief Initializes the TIM INput Capture MSP.
bogdanm	0:9b334a45a8ff	1562	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1563	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1564	* @retval None
bogdanm	0:9b334a45a8ff	1565	*/
bogdanm	0:9b334a45a8ff	1566	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1567	{
bogdanm	0:9b334a45a8ff	1568	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1569	the HAL_TIM_IC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1570	*/
bogdanm	0:9b334a45a8ff	1571	}
bogdanm	0:9b334a45a8ff	1572
bogdanm	0:9b334a45a8ff	1573	/**
bogdanm	0:9b334a45a8ff	1574	* @brief DeInitializes TIM Input Capture MSP.
bogdanm	0:9b334a45a8ff	1575	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1576	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1577	* @retval None
bogdanm	0:9b334a45a8ff	1578	*/
bogdanm	0:9b334a45a8ff	1579	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1580	{
bogdanm	0:9b334a45a8ff	1581	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1582	the HAL_TIM_IC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	1583	*/
bogdanm	0:9b334a45a8ff	1584	}
bogdanm	0:9b334a45a8ff	1585
bogdanm	0:9b334a45a8ff	1586	/**
bogdanm	0:9b334a45a8ff	1587	* @brief Starts the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1588	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1589	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1590	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1591	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1592	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1593	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1594	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1595	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1596	* @retval HAL status
bogdanm	0:9b334a45a8ff	1597	*/
bogdanm	0:9b334a45a8ff	1598	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1599	{
bogdanm	0:9b334a45a8ff	1600	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1601	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1604	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1607	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/* Return function status */
bogdanm	0:9b334a45a8ff	1610	return HAL_OK;
bogdanm	0:9b334a45a8ff	1611	}
bogdanm	0:9b334a45a8ff	1612
bogdanm	0:9b334a45a8ff	1613	/**
bogdanm	0:9b334a45a8ff	1614	* @brief Stops the TIM Input Capture measurement.
bogdanm	0:9b334a45a8ff	1615	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1616	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1617	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1618	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1619	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1620	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1621	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1622	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1623	* @retval HAL status
bogdanm	0:9b334a45a8ff	1624	*/
bogdanm	0:9b334a45a8ff	1625	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1626	{
bogdanm	0:9b334a45a8ff	1627	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1628	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1629
bogdanm	0:9b334a45a8ff	1630	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1631	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1632
bogdanm	0:9b334a45a8ff	1633	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1634	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1635
bogdanm	0:9b334a45a8ff	1636	/* Return function status */
bogdanm	0:9b334a45a8ff	1637	return HAL_OK;
bogdanm	0:9b334a45a8ff	1638	}
bogdanm	0:9b334a45a8ff	1639
bogdanm	0:9b334a45a8ff	1640	/**
bogdanm	0:9b334a45a8ff	1641	* @brief Starts the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1642	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1643	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1644	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1645	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1646	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1647	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1648	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1649	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1650	* @retval HAL status
bogdanm	0:9b334a45a8ff	1651	*/
bogdanm	0:9b334a45a8ff	1652	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1653	{
bogdanm	0:9b334a45a8ff	1654	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1655	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1656
bogdanm	0:9b334a45a8ff	1657	switch (Channel)
bogdanm	0:9b334a45a8ff	1658	{
bogdanm	0:9b334a45a8ff	1659	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1660	{
bogdanm	0:9b334a45a8ff	1661	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1662	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1663	}
bogdanm	0:9b334a45a8ff	1664	break;
bogdanm	0:9b334a45a8ff	1665
bogdanm	0:9b334a45a8ff	1666	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1667	{
bogdanm	0:9b334a45a8ff	1668	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1669	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1670	}
bogdanm	0:9b334a45a8ff	1671	break;
bogdanm	0:9b334a45a8ff	1672
bogdanm	0:9b334a45a8ff	1673	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1674	{
bogdanm	0:9b334a45a8ff	1675	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1676	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1677	}
bogdanm	0:9b334a45a8ff	1678	break;
bogdanm	0:9b334a45a8ff	1679
bogdanm	0:9b334a45a8ff	1680	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1681	{
bogdanm	0:9b334a45a8ff	1682	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1683	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1684	}
bogdanm	0:9b334a45a8ff	1685	break;
bogdanm	0:9b334a45a8ff	1686
bogdanm	0:9b334a45a8ff	1687	default:
bogdanm	0:9b334a45a8ff	1688	break;
bogdanm	0:9b334a45a8ff	1689	}
bogdanm	0:9b334a45a8ff	1690	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1691	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1692
bogdanm	0:9b334a45a8ff	1693	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1694	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1695
bogdanm	0:9b334a45a8ff	1696	/* Return function status */
bogdanm	0:9b334a45a8ff	1697	return HAL_OK;
bogdanm	0:9b334a45a8ff	1698	}
bogdanm	0:9b334a45a8ff	1699
bogdanm	0:9b334a45a8ff	1700	/**
bogdanm	0:9b334a45a8ff	1701	* @brief Stops the TIM Input Capture measurement in interrupt mode.
bogdanm	0:9b334a45a8ff	1702	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1703	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1704	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1705	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1706	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1707	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1708	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1709	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1710	* @retval HAL status
bogdanm	0:9b334a45a8ff	1711	*/
bogdanm	0:9b334a45a8ff	1712	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1713	{
bogdanm	0:9b334a45a8ff	1714	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1715	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	switch (Channel)
bogdanm	0:9b334a45a8ff	1718	{
bogdanm	0:9b334a45a8ff	1719	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1720	{
bogdanm	0:9b334a45a8ff	1721	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1722	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1723	}
bogdanm	0:9b334a45a8ff	1724	break;
bogdanm	0:9b334a45a8ff	1725
bogdanm	0:9b334a45a8ff	1726	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1727	{
bogdanm	0:9b334a45a8ff	1728	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1729	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1730	}
bogdanm	0:9b334a45a8ff	1731	break;
bogdanm	0:9b334a45a8ff	1732
bogdanm	0:9b334a45a8ff	1733	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1734	{
bogdanm	0:9b334a45a8ff	1735	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1736	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1737	}
bogdanm	0:9b334a45a8ff	1738	break;
bogdanm	0:9b334a45a8ff	1739
bogdanm	0:9b334a45a8ff	1740	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1741	{
bogdanm	0:9b334a45a8ff	1742	/* Disable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1743	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1744	}
bogdanm	0:9b334a45a8ff	1745	break;
bogdanm	0:9b334a45a8ff	1746
bogdanm	0:9b334a45a8ff	1747	default:
bogdanm	0:9b334a45a8ff	1748	break;
bogdanm	0:9b334a45a8ff	1749	}
bogdanm	0:9b334a45a8ff	1750
bogdanm	0:9b334a45a8ff	1751	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1752	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1753
bogdanm	0:9b334a45a8ff	1754	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1755	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1756
bogdanm	0:9b334a45a8ff	1757	/* Return function status */
bogdanm	0:9b334a45a8ff	1758	return HAL_OK;
bogdanm	0:9b334a45a8ff	1759	}
bogdanm	0:9b334a45a8ff	1760
bogdanm	0:9b334a45a8ff	1761	/**
bogdanm	0:9b334a45a8ff	1762	* @brief Starts the TIM Input Capture measurement on in DMA mode.
bogdanm	0:9b334a45a8ff	1763	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1764	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1765	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	1766	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1767	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1768	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1769	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1770	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1771	* @param pData: The destination Buffer address.
bogdanm	0:9b334a45a8ff	1772	* @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	1773	* @retval HAL status
bogdanm	0:9b334a45a8ff	1774	*/
bogdanm	0:9b334a45a8ff	1775	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1776	{
bogdanm	0:9b334a45a8ff	1777	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1778	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1779	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1780
bogdanm	0:9b334a45a8ff	1781	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1782	{
bogdanm	0:9b334a45a8ff	1783	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1784	}
bogdanm	0:9b334a45a8ff	1785	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1786	{
bogdanm	0:9b334a45a8ff	1787	if((pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1788	{
bogdanm	0:9b334a45a8ff	1789	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1790	}
bogdanm	0:9b334a45a8ff	1791	else
bogdanm	0:9b334a45a8ff	1792	{
bogdanm	0:9b334a45a8ff	1793	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1794	}
bogdanm	0:9b334a45a8ff	1795	}
bogdanm	0:9b334a45a8ff	1796
bogdanm	0:9b334a45a8ff	1797	switch (Channel)
bogdanm	0:9b334a45a8ff	1798	{
bogdanm	0:9b334a45a8ff	1799	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1800	{
bogdanm	0:9b334a45a8ff	1801	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1802	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1803
bogdanm	0:9b334a45a8ff	1804	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1805	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1806
bogdanm	0:9b334a45a8ff	1807	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1808	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1809
bogdanm	0:9b334a45a8ff	1810	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1811	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1812	}
bogdanm	0:9b334a45a8ff	1813	break;
bogdanm	0:9b334a45a8ff	1814
bogdanm	0:9b334a45a8ff	1815	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1816	{
bogdanm	0:9b334a45a8ff	1817	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1818	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1819
bogdanm	0:9b334a45a8ff	1820	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1821	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1822
bogdanm	0:9b334a45a8ff	1823	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1824	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1825
bogdanm	0:9b334a45a8ff	1826	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1827	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1828	}
bogdanm	0:9b334a45a8ff	1829	break;
bogdanm	0:9b334a45a8ff	1830
bogdanm	0:9b334a45a8ff	1831	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1832	{
bogdanm	0:9b334a45a8ff	1833	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1834	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1835
bogdanm	0:9b334a45a8ff	1836	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1837	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1838
bogdanm	0:9b334a45a8ff	1839	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1840	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1841
bogdanm	0:9b334a45a8ff	1842	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1843	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1844	}
bogdanm	0:9b334a45a8ff	1845	break;
bogdanm	0:9b334a45a8ff	1846
bogdanm	0:9b334a45a8ff	1847	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1848	{
bogdanm	0:9b334a45a8ff	1849	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1850	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	1851
bogdanm	0:9b334a45a8ff	1852	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1853	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1854
bogdanm	0:9b334a45a8ff	1855	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	1856	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1857
bogdanm	0:9b334a45a8ff	1858	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1859	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1860	}
bogdanm	0:9b334a45a8ff	1861	break;
bogdanm	0:9b334a45a8ff	1862
bogdanm	0:9b334a45a8ff	1863	default:
bogdanm	0:9b334a45a8ff	1864	break;
bogdanm	0:9b334a45a8ff	1865	}
bogdanm	0:9b334a45a8ff	1866
bogdanm	0:9b334a45a8ff	1867	/* Enable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1868	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	1869
bogdanm	0:9b334a45a8ff	1870	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1871	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1872
bogdanm	0:9b334a45a8ff	1873	/* Return function status */
bogdanm	0:9b334a45a8ff	1874	return HAL_OK;
bogdanm	0:9b334a45a8ff	1875	}
bogdanm	0:9b334a45a8ff	1876
bogdanm	0:9b334a45a8ff	1877	/**
bogdanm	0:9b334a45a8ff	1878	* @brief Stops the TIM Input Capture measurement on in DMA mode.
bogdanm	0:9b334a45a8ff	1879	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1880	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1881	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	1882	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1883	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1884	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1885	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1886	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1887	* @retval HAL status
bogdanm	0:9b334a45a8ff	1888	*/
bogdanm	0:9b334a45a8ff	1889	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1890	{
bogdanm	0:9b334a45a8ff	1891	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1892	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1893	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1894
bogdanm	0:9b334a45a8ff	1895	switch (Channel)
bogdanm	0:9b334a45a8ff	1896	{
bogdanm	0:9b334a45a8ff	1897	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1898	{
bogdanm	0:9b334a45a8ff	1899	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1900	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1901	}
bogdanm	0:9b334a45a8ff	1902	break;
bogdanm	0:9b334a45a8ff	1903
bogdanm	0:9b334a45a8ff	1904	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1905	{
bogdanm	0:9b334a45a8ff	1906	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1907	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1908	}
bogdanm	0:9b334a45a8ff	1909	break;
bogdanm	0:9b334a45a8ff	1910
bogdanm	0:9b334a45a8ff	1911	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1912	{
bogdanm	0:9b334a45a8ff	1913	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1914	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1915	}
bogdanm	0:9b334a45a8ff	1916	break;
bogdanm	0:9b334a45a8ff	1917
bogdanm	0:9b334a45a8ff	1918	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1919	{
bogdanm	0:9b334a45a8ff	1920	/* Disable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1921	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1922	}
bogdanm	0:9b334a45a8ff	1923	break;
bogdanm	0:9b334a45a8ff	1924
bogdanm	0:9b334a45a8ff	1925	default:
bogdanm	0:9b334a45a8ff	1926	break;
bogdanm	0:9b334a45a8ff	1927	}
bogdanm	0:9b334a45a8ff	1928
bogdanm	0:9b334a45a8ff	1929	/* Disable the Input Capture channel */
bogdanm	0:9b334a45a8ff	1930	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	1931
bogdanm	0:9b334a45a8ff	1932	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1933	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1934
bogdanm	0:9b334a45a8ff	1935	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1936	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1937
bogdanm	0:9b334a45a8ff	1938	/* Return function status */
bogdanm	0:9b334a45a8ff	1939	return HAL_OK;
bogdanm	0:9b334a45a8ff	1940	}
bogdanm	0:9b334a45a8ff	1941	/**
bogdanm	0:9b334a45a8ff	1942	* @}
bogdanm	0:9b334a45a8ff	1943	*/
bogdanm	0:9b334a45a8ff	1944
bogdanm	0:9b334a45a8ff	1945	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
bogdanm	0:9b334a45a8ff	1946	* @brief Time One Pulse functions
bogdanm	0:9b334a45a8ff	1947	*
bogdanm	0:9b334a45a8ff	1948	@verbatim
bogdanm	0:9b334a45a8ff	1949	==============================================================================
bogdanm	0:9b334a45a8ff	1950	##### Time One Pulse functions #####
bogdanm	0:9b334a45a8ff	1951	==============================================================================
bogdanm	0:9b334a45a8ff	1952	[..]
bogdanm	0:9b334a45a8ff	1953	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1954	(+) Initialize and configure the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1955	(+) De-initialize the TIM One Pulse.
bogdanm	0:9b334a45a8ff	1956	(+) Start the Time One Pulse.
bogdanm	0:9b334a45a8ff	1957	(+) Stop the Time One Pulse.
bogdanm	0:9b334a45a8ff	1958	(+) Start the Time One Pulse and enable interrupt.
bogdanm	0:9b334a45a8ff	1959	(+) Stop the Time One Pulse and disable interrupt.
bogdanm	0:9b334a45a8ff	1960	(+) Start the Time One Pulse and enable DMA transfer.
bogdanm	0:9b334a45a8ff	1961	(+) Stop the Time One Pulse and disable DMA transfer.
bogdanm	0:9b334a45a8ff	1962
bogdanm	0:9b334a45a8ff	1963	@endverbatim
bogdanm	0:9b334a45a8ff	1964	* @{
bogdanm	0:9b334a45a8ff	1965	*/
bogdanm	0:9b334a45a8ff	1966	/**
bogdanm	0:9b334a45a8ff	1967	* @brief Initializes the TIM One Pulse Time Base according to the specified
bogdanm	0:9b334a45a8ff	1968	* parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	1969	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1970	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	1971	* @param OnePulseMode: Select the One pulse mode.
bogdanm	0:9b334a45a8ff	1972	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1973	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
bogdanm	0:9b334a45a8ff	1974	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
bogdanm	0:9b334a45a8ff	1975	* @retval HAL status
bogdanm	0:9b334a45a8ff	1976	*/
bogdanm	0:9b334a45a8ff	1977	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
bogdanm	0:9b334a45a8ff	1978	{
bogdanm	0:9b334a45a8ff	1979	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	1980	if(htim == NULL)
bogdanm	0:9b334a45a8ff	1981	{
bogdanm	0:9b334a45a8ff	1982	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1983	}
bogdanm	0:9b334a45a8ff	1984
bogdanm	0:9b334a45a8ff	1985	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1986	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1987	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	1988	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	1989	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
bogdanm	0:9b334a45a8ff	1990
bogdanm	0:9b334a45a8ff	1991	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1992	{
bogdanm	0:9b334a45a8ff	1993	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	1994	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	1995	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	1996	HAL_TIM_OnePulse_MspInit(htim);
bogdanm	0:9b334a45a8ff	1997	}
bogdanm	0:9b334a45a8ff	1998
bogdanm	0:9b334a45a8ff	1999	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	2000	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2001
bogdanm	0:9b334a45a8ff	2002	/* Configure the Time base in the One Pulse Mode */
bogdanm	0:9b334a45a8ff	2003	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	2004
bogdanm	0:9b334a45a8ff	2005	/* Reset the OPM Bit */
bogdanm	0:9b334a45a8ff	2006	htim->Instance->CR1 &= ~TIM_CR1_OPM;
bogdanm	0:9b334a45a8ff	2007
bogdanm	0:9b334a45a8ff	2008	/* Configure the OPM Mode */
bogdanm	0:9b334a45a8ff	2009	htim->Instance->CR1 \|= OnePulseMode;
bogdanm	0:9b334a45a8ff	2010
bogdanm	0:9b334a45a8ff	2011	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	2012	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2013
bogdanm	0:9b334a45a8ff	2014	return HAL_OK;
bogdanm	0:9b334a45a8ff	2015	}
bogdanm	0:9b334a45a8ff	2016
bogdanm	0:9b334a45a8ff	2017	/**
bogdanm	0:9b334a45a8ff	2018	* @brief DeInitializes the TIM One Pulse
bogdanm	0:9b334a45a8ff	2019	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2020	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2021	* @retval HAL status
bogdanm	0:9b334a45a8ff	2022	*/
bogdanm	0:9b334a45a8ff	2023	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2024	{
bogdanm	0:9b334a45a8ff	2025	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2026	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2027
bogdanm	0:9b334a45a8ff	2028	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2029
bogdanm	0:9b334a45a8ff	2030	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	2031	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2032
bogdanm	0:9b334a45a8ff	2033	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	2034	HAL_TIM_OnePulse_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	2035
bogdanm	0:9b334a45a8ff	2036	/* Change TIM state */
bogdanm	0:9b334a45a8ff	2037	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	2038
bogdanm	0:9b334a45a8ff	2039	/* Release Lock */
bogdanm	0:9b334a45a8ff	2040	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2041
bogdanm	0:9b334a45a8ff	2042	return HAL_OK;
bogdanm	0:9b334a45a8ff	2043	}
bogdanm	0:9b334a45a8ff	2044
bogdanm	0:9b334a45a8ff	2045	/**
bogdanm	0:9b334a45a8ff	2046	* @brief Initializes the TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	2047	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2048	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2049	* @retval None
bogdanm	0:9b334a45a8ff	2050	*/
bogdanm	0:9b334a45a8ff	2051	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2052	{
bogdanm	0:9b334a45a8ff	2053	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2054	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2055	*/
bogdanm	0:9b334a45a8ff	2056	}
bogdanm	0:9b334a45a8ff	2057
bogdanm	0:9b334a45a8ff	2058	/**
bogdanm	0:9b334a45a8ff	2059	* @brief DeInitializes TIM One Pulse MSP.
bogdanm	0:9b334a45a8ff	2060	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2061	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2062	* @retval None
bogdanm	0:9b334a45a8ff	2063	*/
bogdanm	0:9b334a45a8ff	2064	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2065	{
bogdanm	0:9b334a45a8ff	2066	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2067	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2068	*/
bogdanm	0:9b334a45a8ff	2069	}
bogdanm	0:9b334a45a8ff	2070
bogdanm	0:9b334a45a8ff	2071	/**
bogdanm	0:9b334a45a8ff	2072	* @brief Starts the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2073	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2074	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2075	* @param OutputChannel : TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2076	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2077	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2078	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2079	* @retval HAL status
bogdanm	0:9b334a45a8ff	2080	*/
bogdanm	0:9b334a45a8ff	2081	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2082	{
bogdanm	0:9b334a45a8ff	2083	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2084	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2085	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2086	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2087	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2088
bogdanm	0:9b334a45a8ff	2089	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2090	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2091
bogdanm	0:9b334a45a8ff	2092	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2093	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2094
bogdanm	0:9b334a45a8ff	2095	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2096	{
bogdanm	0:9b334a45a8ff	2097	/* Enable the main output */
bogdanm	0:9b334a45a8ff	2098	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2099	}
bogdanm	0:9b334a45a8ff	2100
bogdanm	0:9b334a45a8ff	2101	/* Return function status */
bogdanm	0:9b334a45a8ff	2102	return HAL_OK;
bogdanm	0:9b334a45a8ff	2103	}
bogdanm	0:9b334a45a8ff	2104
bogdanm	0:9b334a45a8ff	2105	/**
bogdanm	0:9b334a45a8ff	2106	* @brief Stops the TIM One Pulse signal generation.
bogdanm	0:9b334a45a8ff	2107	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2108	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2109	* @param OutputChannel : TIM Channels to be disable.
bogdanm	0:9b334a45a8ff	2110	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2111	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2112	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2113	* @retval HAL status
bogdanm	0:9b334a45a8ff	2114	*/
bogdanm	0:9b334a45a8ff	2115	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2116	{
bogdanm	0:9b334a45a8ff	2117	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2118	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2119	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2120	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2121	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2122
bogdanm	0:9b334a45a8ff	2123	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2124	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2125
bogdanm	0:9b334a45a8ff	2126	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2127	{
bogdanm	0:9b334a45a8ff	2128	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	2129	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2130	}
bogdanm	0:9b334a45a8ff	2131
bogdanm	0:9b334a45a8ff	2132	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2133	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2134
bogdanm	0:9b334a45a8ff	2135	/* Return function status */
bogdanm	0:9b334a45a8ff	2136	return HAL_OK;
bogdanm	0:9b334a45a8ff	2137	}
bogdanm	0:9b334a45a8ff	2138
bogdanm	0:9b334a45a8ff	2139	/**
bogdanm	0:9b334a45a8ff	2140	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2141	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2142	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2143	* @param OutputChannel : TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2144	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2145	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2146	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2147	* @retval HAL status
bogdanm	0:9b334a45a8ff	2148	*/
bogdanm	0:9b334a45a8ff	2149	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2150	{
bogdanm	0:9b334a45a8ff	2151	/* Enable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2152	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2153	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2154	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2155	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm	0:9b334a45a8ff	2156
bogdanm	0:9b334a45a8ff	2157	No need to enable the counter, it's enabled automatically by hardware
bogdanm	0:9b334a45a8ff	2158	(the counter starts in response to a stimulus and generate a pulse */
bogdanm	0:9b334a45a8ff	2159
bogdanm	0:9b334a45a8ff	2160	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2161	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2162
bogdanm	0:9b334a45a8ff	2163	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2164	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2165
bogdanm	0:9b334a45a8ff	2166	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2167	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2168
bogdanm	0:9b334a45a8ff	2169	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2170	{
bogdanm	0:9b334a45a8ff	2171	/* Enable the main output */
bogdanm	0:9b334a45a8ff	2172	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2173	}
bogdanm	0:9b334a45a8ff	2174
bogdanm	0:9b334a45a8ff	2175	/* Return function status */
bogdanm	0:9b334a45a8ff	2176	return HAL_OK;
bogdanm	0:9b334a45a8ff	2177	}
bogdanm	0:9b334a45a8ff	2178
bogdanm	0:9b334a45a8ff	2179	/**
bogdanm	0:9b334a45a8ff	2180	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
bogdanm	0:9b334a45a8ff	2181	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2182	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2183	* @param OutputChannel : TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2184	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2185	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2186	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2187	* @retval HAL status
bogdanm	0:9b334a45a8ff	2188	*/
bogdanm	0:9b334a45a8ff	2189	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	2190	{
bogdanm	0:9b334a45a8ff	2191	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	2192	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2193
bogdanm	0:9b334a45a8ff	2194	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	2195	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2196
bogdanm	0:9b334a45a8ff	2197	/* Disable the Capture compare and the Input Capture channels
bogdanm	0:9b334a45a8ff	2198	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2199	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm	0:9b334a45a8ff	2200	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm	0:9b334a45a8ff	2201	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm	0:9b334a45a8ff	2202	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2203	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2204
bogdanm	0:9b334a45a8ff	2205	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
bogdanm	0:9b334a45a8ff	2206	{
bogdanm	0:9b334a45a8ff	2207	/* Disable the Main Output */
bogdanm	0:9b334a45a8ff	2208	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2209	}
bogdanm	0:9b334a45a8ff	2210
bogdanm	0:9b334a45a8ff	2211	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2212	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2213
bogdanm	0:9b334a45a8ff	2214	/* Return function status */
bogdanm	0:9b334a45a8ff	2215	return HAL_OK;
bogdanm	0:9b334a45a8ff	2216	}
bogdanm	0:9b334a45a8ff	2217
bogdanm	0:9b334a45a8ff	2218	/**
bogdanm	0:9b334a45a8ff	2219	* @}
bogdanm	0:9b334a45a8ff	2220	*/
bogdanm	0:9b334a45a8ff	2221
bogdanm	0:9b334a45a8ff	2222	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
bogdanm	0:9b334a45a8ff	2223	* @brief Time Encoder functions
bogdanm	0:9b334a45a8ff	2224	*
bogdanm	0:9b334a45a8ff	2225	@verbatim
bogdanm	0:9b334a45a8ff	2226	==============================================================================
bogdanm	0:9b334a45a8ff	2227	##### Time Encoder functions #####
bogdanm	0:9b334a45a8ff	2228	==============================================================================
bogdanm	0:9b334a45a8ff	2229	[..]
bogdanm	0:9b334a45a8ff	2230	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2231	(+) Initialize and configure the TIM Encoder.
bogdanm	0:9b334a45a8ff	2232	(+) De-initialize the TIM Encoder.
bogdanm	0:9b334a45a8ff	2233	(+) Start the Time Encoder.
bogdanm	0:9b334a45a8ff	2234	(+) Stop the Time Encoder.
bogdanm	0:9b334a45a8ff	2235	(+) Start the Time Encoder and enable interrupt.
bogdanm	0:9b334a45a8ff	2236	(+) Stop the Time Encoder and disable interrupt.
bogdanm	0:9b334a45a8ff	2237	(+) Start the Time Encoder and enable DMA transfer.
bogdanm	0:9b334a45a8ff	2238	(+) Stop the Time Encoder and disable DMA transfer.
bogdanm	0:9b334a45a8ff	2239
bogdanm	0:9b334a45a8ff	2240	@endverbatim
bogdanm	0:9b334a45a8ff	2241	* @{
bogdanm	0:9b334a45a8ff	2242	*/
bogdanm	0:9b334a45a8ff	2243	/**
bogdanm	0:9b334a45a8ff	2244	* @brief Initializes the TIM Encoder Interface and create the associated handle.
bogdanm	0:9b334a45a8ff	2245	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2246	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2247	* @param sConfig: TIM Encoder Interface configuration structure
bogdanm	0:9b334a45a8ff	2248	* @retval HAL status
bogdanm	0:9b334a45a8ff	2249	*/
bogdanm	0:9b334a45a8ff	2250	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
bogdanm	0:9b334a45a8ff	2251	{
bogdanm	0:9b334a45a8ff	2252	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	2253	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	2254	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	2255
bogdanm	0:9b334a45a8ff	2256	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	2257	if(htim == NULL)
bogdanm	0:9b334a45a8ff	2258	{
bogdanm	0:9b334a45a8ff	2259	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2260	}
bogdanm	0:9b334a45a8ff	2261
bogdanm	0:9b334a45a8ff	2262	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2263	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2264	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
bogdanm	0:9b334a45a8ff	2265	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
bogdanm	0:9b334a45a8ff	2266	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
bogdanm	0:9b334a45a8ff	2267	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
bogdanm	0:9b334a45a8ff	2268	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
bogdanm	0:9b334a45a8ff	2269	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
bogdanm	0:9b334a45a8ff	2270	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
bogdanm	0:9b334a45a8ff	2271	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
bogdanm	0:9b334a45a8ff	2272	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
bogdanm	0:9b334a45a8ff	2273
bogdanm	0:9b334a45a8ff	2274	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	2275	{
bogdanm	0:9b334a45a8ff	2276	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	2277	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	2278	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	2279	HAL_TIM_Encoder_MspInit(htim);
bogdanm	0:9b334a45a8ff	2280	}
bogdanm	0:9b334a45a8ff	2281
bogdanm	0:9b334a45a8ff	2282	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	2283	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2284
bogdanm	0:9b334a45a8ff	2285	/* Reset the SMS bits */
bogdanm	0:9b334a45a8ff	2286	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	2287
bogdanm	0:9b334a45a8ff	2288	/* Configure the Time base in the Encoder Mode */
bogdanm	0:9b334a45a8ff	2289	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	2290
bogdanm	0:9b334a45a8ff	2291	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	2292	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	2293
bogdanm	0:9b334a45a8ff	2294	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	2295	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	2296
bogdanm	0:9b334a45a8ff	2297	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	2298	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	2299
bogdanm	0:9b334a45a8ff	2300	/* Set the encoder Mode */
bogdanm	0:9b334a45a8ff	2301	tmpsmcr \|= sConfig->EncoderMode;
bogdanm	0:9b334a45a8ff	2302
bogdanm	0:9b334a45a8ff	2303	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
bogdanm	0:9b334a45a8ff	2304	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
bogdanm	0:9b334a45a8ff	2305	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
bogdanm	0:9b334a45a8ff	2306
bogdanm	0:9b334a45a8ff	2307	/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
bogdanm	0:9b334a45a8ff	2308	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
bogdanm	0:9b334a45a8ff	2309	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	2310	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
bogdanm	0:9b334a45a8ff	2311	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
bogdanm	0:9b334a45a8ff	2312
bogdanm	0:9b334a45a8ff	2313	/* Set the TI1 and the TI2 Polarities */
bogdanm	0:9b334a45a8ff	2314	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
bogdanm	0:9b334a45a8ff	2315	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	2316	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
bogdanm	0:9b334a45a8ff	2317
bogdanm	0:9b334a45a8ff	2318	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	2319	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	2320
bogdanm	0:9b334a45a8ff	2321	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	2322	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	2323
bogdanm	0:9b334a45a8ff	2324	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	2325	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	2326
bogdanm	0:9b334a45a8ff	2327	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	2328	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2329
bogdanm	0:9b334a45a8ff	2330	return HAL_OK;
bogdanm	0:9b334a45a8ff	2331	}
bogdanm	0:9b334a45a8ff	2332
bogdanm	0:9b334a45a8ff	2333	/**
bogdanm	0:9b334a45a8ff	2334	* @brief DeInitializes the TIM Encoder interface
bogdanm	0:9b334a45a8ff	2335	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2336	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2337	* @retval HAL status
bogdanm	0:9b334a45a8ff	2338	*/
bogdanm	0:9b334a45a8ff	2339	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2340	{
bogdanm	0:9b334a45a8ff	2341	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2342	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2343
bogdanm	0:9b334a45a8ff	2344	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2345
bogdanm	0:9b334a45a8ff	2346	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	2347	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2348
bogdanm	0:9b334a45a8ff	2349	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	2350	HAL_TIM_Encoder_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	2351
bogdanm	0:9b334a45a8ff	2352	/* Change TIM state */
bogdanm	0:9b334a45a8ff	2353	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	2354
bogdanm	0:9b334a45a8ff	2355	/* Release Lock */
bogdanm	0:9b334a45a8ff	2356	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	2357
bogdanm	0:9b334a45a8ff	2358	return HAL_OK;
bogdanm	0:9b334a45a8ff	2359	}
bogdanm	0:9b334a45a8ff	2360
bogdanm	0:9b334a45a8ff	2361	/**
bogdanm	0:9b334a45a8ff	2362	* @brief Initializes the TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2363	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2364	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2365	* @retval None
bogdanm	0:9b334a45a8ff	2366	*/
bogdanm	0:9b334a45a8ff	2367	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2368	{
bogdanm	0:9b334a45a8ff	2369	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2370	the HAL_TIM_Encoder_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2371	*/
bogdanm	0:9b334a45a8ff	2372	}
bogdanm	0:9b334a45a8ff	2373
bogdanm	0:9b334a45a8ff	2374	/**
bogdanm	0:9b334a45a8ff	2375	* @brief DeInitializes TIM Encoder Interface MSP.
bogdanm	0:9b334a45a8ff	2376	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2377	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2378	* @retval None
bogdanm	0:9b334a45a8ff	2379	*/
bogdanm	0:9b334a45a8ff	2380	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2381	{
bogdanm	0:9b334a45a8ff	2382	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2383	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	2384	*/
bogdanm	0:9b334a45a8ff	2385	}
bogdanm	0:9b334a45a8ff	2386
bogdanm	0:9b334a45a8ff	2387	/**
bogdanm	0:9b334a45a8ff	2388	* @brief Starts the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2389	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2390	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2391	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2392	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2393	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2394	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2395	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2396	* @retval HAL status
bogdanm	0:9b334a45a8ff	2397	*/
bogdanm	0:9b334a45a8ff	2398	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2399	{
bogdanm	0:9b334a45a8ff	2400	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2401	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2402
bogdanm	0:9b334a45a8ff	2403	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2404	switch (Channel)
bogdanm	0:9b334a45a8ff	2405	{
bogdanm	0:9b334a45a8ff	2406	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2407	{
bogdanm	0:9b334a45a8ff	2408	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2409	break;
bogdanm	0:9b334a45a8ff	2410	}
bogdanm	0:9b334a45a8ff	2411	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2412	{
bogdanm	0:9b334a45a8ff	2413	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2414	break;
bogdanm	0:9b334a45a8ff	2415	}
bogdanm	0:9b334a45a8ff	2416	default :
bogdanm	0:9b334a45a8ff	2417	{
bogdanm	0:9b334a45a8ff	2418	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2419	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2420	break;
bogdanm	0:9b334a45a8ff	2421	}
bogdanm	0:9b334a45a8ff	2422	}
bogdanm	0:9b334a45a8ff	2423	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2424	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2425
bogdanm	0:9b334a45a8ff	2426	/* Return function status */
bogdanm	0:9b334a45a8ff	2427	return HAL_OK;
bogdanm	0:9b334a45a8ff	2428	}
bogdanm	0:9b334a45a8ff	2429
bogdanm	0:9b334a45a8ff	2430	/**
bogdanm	0:9b334a45a8ff	2431	* @brief Stops the TIM Encoder Interface.
bogdanm	0:9b334a45a8ff	2432	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2433	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2434	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	2435	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2436	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2437	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2438	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2439	* @retval HAL status
bogdanm	0:9b334a45a8ff	2440	*/
bogdanm	0:9b334a45a8ff	2441	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2442	{
bogdanm	0:9b334a45a8ff	2443	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2444	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2445
bogdanm	0:9b334a45a8ff	2446	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2447	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2448	switch (Channel)
bogdanm	0:9b334a45a8ff	2449	{
bogdanm	0:9b334a45a8ff	2450	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2451	{
bogdanm	0:9b334a45a8ff	2452	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2453	break;
bogdanm	0:9b334a45a8ff	2454	}
bogdanm	0:9b334a45a8ff	2455	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2456	{
bogdanm	0:9b334a45a8ff	2457	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2458	break;
bogdanm	0:9b334a45a8ff	2459	}
bogdanm	0:9b334a45a8ff	2460	default :
bogdanm	0:9b334a45a8ff	2461	{
bogdanm	0:9b334a45a8ff	2462	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2463	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2464	break;
bogdanm	0:9b334a45a8ff	2465	}
bogdanm	0:9b334a45a8ff	2466	}
bogdanm	0:9b334a45a8ff	2467	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2468	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2469
bogdanm	0:9b334a45a8ff	2470	/* Return function status */
bogdanm	0:9b334a45a8ff	2471	return HAL_OK;
bogdanm	0:9b334a45a8ff	2472	}
bogdanm	0:9b334a45a8ff	2473
bogdanm	0:9b334a45a8ff	2474	/**
bogdanm	0:9b334a45a8ff	2475	* @brief Starts the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2476	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2477	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2478	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2479	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2480	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2481	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2482	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2483	* @retval HAL status
bogdanm	0:9b334a45a8ff	2484	*/
bogdanm	0:9b334a45a8ff	2485	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2486	{
bogdanm	0:9b334a45a8ff	2487	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2488	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2489
bogdanm	0:9b334a45a8ff	2490	/* Enable the encoder interface channels */
bogdanm	0:9b334a45a8ff	2491	/* Enable the capture compare Interrupts 1 and/or 2 */
bogdanm	0:9b334a45a8ff	2492	switch (Channel)
bogdanm	0:9b334a45a8ff	2493	{
bogdanm	0:9b334a45a8ff	2494	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2495	{
bogdanm	0:9b334a45a8ff	2496	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2497	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2498	break;
bogdanm	0:9b334a45a8ff	2499	}
bogdanm	0:9b334a45a8ff	2500	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2501	{
bogdanm	0:9b334a45a8ff	2502	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2503	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2504	break;
bogdanm	0:9b334a45a8ff	2505	}
bogdanm	0:9b334a45a8ff	2506	default :
bogdanm	0:9b334a45a8ff	2507	{
bogdanm	0:9b334a45a8ff	2508	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2509	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2510	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2511	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2512	break;
bogdanm	0:9b334a45a8ff	2513	}
bogdanm	0:9b334a45a8ff	2514	}
bogdanm	0:9b334a45a8ff	2515
bogdanm	0:9b334a45a8ff	2516	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2517	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2518
bogdanm	0:9b334a45a8ff	2519	/* Return function status */
bogdanm	0:9b334a45a8ff	2520	return HAL_OK;
bogdanm	0:9b334a45a8ff	2521	}
bogdanm	0:9b334a45a8ff	2522
bogdanm	0:9b334a45a8ff	2523	/**
bogdanm	0:9b334a45a8ff	2524	* @brief Stops the TIM Encoder Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	2525	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2526	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2527	* @param Channel: TIM Channels to be disabled.
bogdanm	0:9b334a45a8ff	2528	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2529	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2530	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2531	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2532	* @retval HAL status
bogdanm	0:9b334a45a8ff	2533	*/
bogdanm	0:9b334a45a8ff	2534	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2535	{
bogdanm	0:9b334a45a8ff	2536	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2537	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2538
bogdanm	0:9b334a45a8ff	2539	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2540	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2541	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2542	{
bogdanm	0:9b334a45a8ff	2543	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2544
bogdanm	0:9b334a45a8ff	2545	/* Disable the capture compare Interrupts 1 */
bogdanm	0:9b334a45a8ff	2546	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2547	}
bogdanm	0:9b334a45a8ff	2548	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2549	{
bogdanm	0:9b334a45a8ff	2550	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2551
bogdanm	0:9b334a45a8ff	2552	/* Disable the capture compare Interrupts 2 */
bogdanm	0:9b334a45a8ff	2553	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2554	}
bogdanm	0:9b334a45a8ff	2555	else
bogdanm	0:9b334a45a8ff	2556	{
bogdanm	0:9b334a45a8ff	2557	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2558	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2559
bogdanm	0:9b334a45a8ff	2560	/* Disable the capture compare Interrupts 1 and 2 */
bogdanm	0:9b334a45a8ff	2561	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2562	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2563	}
bogdanm	0:9b334a45a8ff	2564
bogdanm	0:9b334a45a8ff	2565	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2566	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2567
bogdanm	0:9b334a45a8ff	2568	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2569	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2570
bogdanm	0:9b334a45a8ff	2571	/* Return function status */
bogdanm	0:9b334a45a8ff	2572	return HAL_OK;
bogdanm	0:9b334a45a8ff	2573	}
bogdanm	0:9b334a45a8ff	2574
bogdanm	0:9b334a45a8ff	2575	/**
bogdanm	0:9b334a45a8ff	2576	* @brief Starts the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2577	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2578	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2579	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2580	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2581	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2582	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2583	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2584	* @param pData1: The destination Buffer address for IC1.
bogdanm	0:9b334a45a8ff	2585	* @param pData2: The destination Buffer address for IC2.
bogdanm	0:9b334a45a8ff	2586	* @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	2587	* @retval HAL status
bogdanm	0:9b334a45a8ff	2588	*/
bogdanm	0:9b334a45a8ff	2589	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
bogdanm	0:9b334a45a8ff	2590	{
bogdanm	0:9b334a45a8ff	2591	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2592	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2593
bogdanm	0:9b334a45a8ff	2594	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	2595	{
bogdanm	0:9b334a45a8ff	2596	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2597	}
bogdanm	0:9b334a45a8ff	2598	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	2599	{
bogdanm	0:9b334a45a8ff	2600	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
bogdanm	0:9b334a45a8ff	2601	{
bogdanm	0:9b334a45a8ff	2602	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2603	}
bogdanm	0:9b334a45a8ff	2604	else
bogdanm	0:9b334a45a8ff	2605	{
bogdanm	0:9b334a45a8ff	2606	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2607	}
bogdanm	0:9b334a45a8ff	2608	}
bogdanm	0:9b334a45a8ff	2609
bogdanm	0:9b334a45a8ff	2610	switch (Channel)
bogdanm	0:9b334a45a8ff	2611	{
bogdanm	0:9b334a45a8ff	2612	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2613	{
bogdanm	0:9b334a45a8ff	2614	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2615	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2616
bogdanm	0:9b334a45a8ff	2617	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2618	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2619
bogdanm	0:9b334a45a8ff	2620	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2621	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
bogdanm	0:9b334a45a8ff	2622
bogdanm	0:9b334a45a8ff	2623	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2624	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2625
bogdanm	0:9b334a45a8ff	2626	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2627	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2628
bogdanm	0:9b334a45a8ff	2629	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2630	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2631	}
bogdanm	0:9b334a45a8ff	2632	break;
bogdanm	0:9b334a45a8ff	2633
bogdanm	0:9b334a45a8ff	2634	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2635	{
bogdanm	0:9b334a45a8ff	2636	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2637	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2638
bogdanm	0:9b334a45a8ff	2639	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2640	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
bogdanm	0:9b334a45a8ff	2641	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2642	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2643
bogdanm	0:9b334a45a8ff	2644	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2645	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2646
bogdanm	0:9b334a45a8ff	2647	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2648	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2649
bogdanm	0:9b334a45a8ff	2650	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2651	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2652	}
bogdanm	0:9b334a45a8ff	2653	break;
bogdanm	0:9b334a45a8ff	2654
bogdanm	0:9b334a45a8ff	2655	case TIM_CHANNEL_ALL:
bogdanm	0:9b334a45a8ff	2656	{
bogdanm	0:9b334a45a8ff	2657	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2658	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2659
bogdanm	0:9b334a45a8ff	2660	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2661	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2662
bogdanm	0:9b334a45a8ff	2663	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2664	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
bogdanm	0:9b334a45a8ff	2665
bogdanm	0:9b334a45a8ff	2666	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	2667	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	2668
bogdanm	0:9b334a45a8ff	2669	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2670	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	2671
bogdanm	0:9b334a45a8ff	2672	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	2673	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm	0:9b334a45a8ff	2674
bogdanm	0:9b334a45a8ff	2675	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	2676	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	2677
bogdanm	0:9b334a45a8ff	2678	/* Enable the Capture compare channel */
bogdanm	0:9b334a45a8ff	2679	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2680	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	2681
bogdanm	0:9b334a45a8ff	2682	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2683	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2684	/* Enable the TIM Input Capture DMA request */
bogdanm	0:9b334a45a8ff	2685	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2686	}
bogdanm	0:9b334a45a8ff	2687	break;
bogdanm	0:9b334a45a8ff	2688
bogdanm	0:9b334a45a8ff	2689	default:
bogdanm	0:9b334a45a8ff	2690	break;
bogdanm	0:9b334a45a8ff	2691	}
bogdanm	0:9b334a45a8ff	2692	/* Return function status */
bogdanm	0:9b334a45a8ff	2693	return HAL_OK;
bogdanm	0:9b334a45a8ff	2694	}
bogdanm	0:9b334a45a8ff	2695
bogdanm	0:9b334a45a8ff	2696	/**
bogdanm	0:9b334a45a8ff	2697	* @brief Stops the TIM Encoder Interface in DMA mode.
bogdanm	0:9b334a45a8ff	2698	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2699	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2700	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2701	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2702	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2703	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2704	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm	0:9b334a45a8ff	2705	* @retval HAL status
bogdanm	0:9b334a45a8ff	2706	*/
bogdanm	0:9b334a45a8ff	2707	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2708	{
bogdanm	0:9b334a45a8ff	2709	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2710	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2711
bogdanm	0:9b334a45a8ff	2712	/* Disable the Input Capture channels 1 and 2
bogdanm	0:9b334a45a8ff	2713	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm	0:9b334a45a8ff	2714	if(Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	2715	{
bogdanm	0:9b334a45a8ff	2716	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2717
bogdanm	0:9b334a45a8ff	2718	/* Disable the capture compare DMA Request 1 */
bogdanm	0:9b334a45a8ff	2719	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2720	}
bogdanm	0:9b334a45a8ff	2721	else if(Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	2722	{
bogdanm	0:9b334a45a8ff	2723	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2724
bogdanm	0:9b334a45a8ff	2725	/* Disable the capture compare DMA Request 2 */
bogdanm	0:9b334a45a8ff	2726	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2727	}
bogdanm	0:9b334a45a8ff	2728	else
bogdanm	0:9b334a45a8ff	2729	{
bogdanm	0:9b334a45a8ff	2730	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2731	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	2732
bogdanm	0:9b334a45a8ff	2733	/* Disable the capture compare DMA Request 1 and 2 */
bogdanm	0:9b334a45a8ff	2734	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	2735	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	2736	}
bogdanm	0:9b334a45a8ff	2737
bogdanm	0:9b334a45a8ff	2738	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	2739	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	2740
bogdanm	0:9b334a45a8ff	2741	/* Change the htim state */
bogdanm	0:9b334a45a8ff	2742	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2743
bogdanm	0:9b334a45a8ff	2744	/* Return function status */
bogdanm	0:9b334a45a8ff	2745	return HAL_OK;
bogdanm	0:9b334a45a8ff	2746	}
bogdanm	0:9b334a45a8ff	2747
bogdanm	0:9b334a45a8ff	2748	/**
bogdanm	0:9b334a45a8ff	2749	* @}
bogdanm	0:9b334a45a8ff	2750	*/
bogdanm	0:9b334a45a8ff	2751	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
bogdanm	0:9b334a45a8ff	2752	* @brief IRQ handler management
bogdanm	0:9b334a45a8ff	2753	*
bogdanm	0:9b334a45a8ff	2754	@verbatim
bogdanm	0:9b334a45a8ff	2755	==============================================================================
bogdanm	0:9b334a45a8ff	2756	##### IRQ handler management #####
bogdanm	0:9b334a45a8ff	2757	==============================================================================
bogdanm	0:9b334a45a8ff	2758	[..]
bogdanm	0:9b334a45a8ff	2759	This section provides Timer IRQ handler function.
bogdanm	0:9b334a45a8ff	2760
bogdanm	0:9b334a45a8ff	2761	@endverbatim
bogdanm	0:9b334a45a8ff	2762	* @{
bogdanm	0:9b334a45a8ff	2763	*/
bogdanm	0:9b334a45a8ff	2764	/**
bogdanm	0:9b334a45a8ff	2765	* @brief This function handles TIM interrupts requests.
bogdanm	0:9b334a45a8ff	2766	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2767	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2768	* @retval None
bogdanm	0:9b334a45a8ff	2769	*/
bogdanm	0:9b334a45a8ff	2770	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	2771	{
bogdanm	0:9b334a45a8ff	2772	/* Capture compare 1 event */
bogdanm	0:9b334a45a8ff	2773	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
bogdanm	0:9b334a45a8ff	2774	{
bogdanm	0:9b334a45a8ff	2775	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
bogdanm	0:9b334a45a8ff	2776	{
bogdanm	0:9b334a45a8ff	2777	{
bogdanm	0:9b334a45a8ff	2778	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	2779	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	2780
bogdanm	0:9b334a45a8ff	2781	/* Input capture event */
bogdanm	0:9b334a45a8ff	2782	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
bogdanm	0:9b334a45a8ff	2783	{
bogdanm	0:9b334a45a8ff	2784	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2785	}
bogdanm	0:9b334a45a8ff	2786	/* Output compare event */
bogdanm	0:9b334a45a8ff	2787	else
bogdanm	0:9b334a45a8ff	2788	{
bogdanm	0:9b334a45a8ff	2789	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2790	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2791	}
bogdanm	0:9b334a45a8ff	2792	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2793	}
bogdanm	0:9b334a45a8ff	2794	}
bogdanm	0:9b334a45a8ff	2795	}
bogdanm	0:9b334a45a8ff	2796	/* Capture compare 2 event */
bogdanm	0:9b334a45a8ff	2797	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
bogdanm	0:9b334a45a8ff	2798	{
bogdanm	0:9b334a45a8ff	2799	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
bogdanm	0:9b334a45a8ff	2800	{
bogdanm	0:9b334a45a8ff	2801	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	2802	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	2803	/* Input capture event */
bogdanm	0:9b334a45a8ff	2804	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
bogdanm	0:9b334a45a8ff	2805	{
bogdanm	0:9b334a45a8ff	2806	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2807	}
bogdanm	0:9b334a45a8ff	2808	/* Output compare event */
bogdanm	0:9b334a45a8ff	2809	else
bogdanm	0:9b334a45a8ff	2810	{
bogdanm	0:9b334a45a8ff	2811	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2812	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2813	}
bogdanm	0:9b334a45a8ff	2814	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2815	}
bogdanm	0:9b334a45a8ff	2816	}
bogdanm	0:9b334a45a8ff	2817	/* Capture compare 3 event */
bogdanm	0:9b334a45a8ff	2818	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
bogdanm	0:9b334a45a8ff	2819	{
bogdanm	0:9b334a45a8ff	2820	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
bogdanm	0:9b334a45a8ff	2821	{
bogdanm	0:9b334a45a8ff	2822	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	2823	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	2824	/* Input capture event */
bogdanm	0:9b334a45a8ff	2825	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
bogdanm	0:9b334a45a8ff	2826	{
bogdanm	0:9b334a45a8ff	2827	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2828	}
bogdanm	0:9b334a45a8ff	2829	/* Output compare event */
bogdanm	0:9b334a45a8ff	2830	else
bogdanm	0:9b334a45a8ff	2831	{
bogdanm	0:9b334a45a8ff	2832	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2833	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2834	}
bogdanm	0:9b334a45a8ff	2835	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2836	}
bogdanm	0:9b334a45a8ff	2837	}
bogdanm	0:9b334a45a8ff	2838	/* Capture compare 4 event */
bogdanm	0:9b334a45a8ff	2839	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
bogdanm	0:9b334a45a8ff	2840	{
bogdanm	0:9b334a45a8ff	2841	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
bogdanm	0:9b334a45a8ff	2842	{
bogdanm	0:9b334a45a8ff	2843	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	2844	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	2845	/* Input capture event */
bogdanm	0:9b334a45a8ff	2846	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
bogdanm	0:9b334a45a8ff	2847	{
bogdanm	0:9b334a45a8ff	2848	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	2849	}
bogdanm	0:9b334a45a8ff	2850	/* Output compare event */
bogdanm	0:9b334a45a8ff	2851	else
bogdanm	0:9b334a45a8ff	2852	{
bogdanm	0:9b334a45a8ff	2853	HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2854	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	2855	}
bogdanm	0:9b334a45a8ff	2856	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	2857	}
bogdanm	0:9b334a45a8ff	2858	}
bogdanm	0:9b334a45a8ff	2859	/* TIM Update event */
bogdanm	0:9b334a45a8ff	2860	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
bogdanm	0:9b334a45a8ff	2861	{
bogdanm	0:9b334a45a8ff	2862	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
bogdanm	0:9b334a45a8ff	2863	{
bogdanm	0:9b334a45a8ff	2864	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
bogdanm	0:9b334a45a8ff	2865	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	2866	}
bogdanm	0:9b334a45a8ff	2867	}
bogdanm	0:9b334a45a8ff	2868	/* TIM Break input event */
bogdanm	0:9b334a45a8ff	2869	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
bogdanm	0:9b334a45a8ff	2870	{
bogdanm	0:9b334a45a8ff	2871	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
bogdanm	0:9b334a45a8ff	2872	{
bogdanm	0:9b334a45a8ff	2873	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	2874	HAL_TIMEx_BreakCallback(htim);
bogdanm	0:9b334a45a8ff	2875	}
bogdanm	0:9b334a45a8ff	2876	}
bogdanm	0:9b334a45a8ff	2877
bogdanm	0:9b334a45a8ff	2878	/* TIM Break input event */
bogdanm	0:9b334a45a8ff	2879	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
bogdanm	0:9b334a45a8ff	2880	{
bogdanm	0:9b334a45a8ff	2881	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
bogdanm	0:9b334a45a8ff	2882	{
bogdanm	0:9b334a45a8ff	2883	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	2884	HAL_TIMEx_BreakCallback(htim);
bogdanm	0:9b334a45a8ff	2885	}
bogdanm	0:9b334a45a8ff	2886	}
bogdanm	0:9b334a45a8ff	2887
bogdanm	0:9b334a45a8ff	2888	/* TIM Trigger detection event */
bogdanm	0:9b334a45a8ff	2889	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
bogdanm	0:9b334a45a8ff	2890	{
bogdanm	0:9b334a45a8ff	2891	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
bogdanm	0:9b334a45a8ff	2892	{
bogdanm	0:9b334a45a8ff	2893	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	2894	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	2895	}
bogdanm	0:9b334a45a8ff	2896	}
bogdanm	0:9b334a45a8ff	2897	/* TIM commutation event */
bogdanm	0:9b334a45a8ff	2898	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
bogdanm	0:9b334a45a8ff	2899	{
bogdanm	0:9b334a45a8ff	2900	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
bogdanm	0:9b334a45a8ff	2901	{
bogdanm	0:9b334a45a8ff	2902	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
bogdanm	0:9b334a45a8ff	2903	HAL_TIMEx_CommutationCallback(htim);
bogdanm	0:9b334a45a8ff	2904	}
bogdanm	0:9b334a45a8ff	2905	}
bogdanm	0:9b334a45a8ff	2906	}
bogdanm	0:9b334a45a8ff	2907
bogdanm	0:9b334a45a8ff	2908	/**
bogdanm	0:9b334a45a8ff	2909	* @}
bogdanm	0:9b334a45a8ff	2910	*/
bogdanm	0:9b334a45a8ff	2911
bogdanm	0:9b334a45a8ff	2912	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
bogdanm	0:9b334a45a8ff	2913	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	2914	*
bogdanm	0:9b334a45a8ff	2915	@verbatim
bogdanm	0:9b334a45a8ff	2916	==============================================================================
bogdanm	0:9b334a45a8ff	2917	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	2918	==============================================================================
bogdanm	0:9b334a45a8ff	2919	[..]
bogdanm	0:9b334a45a8ff	2920	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2921	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
bogdanm	0:9b334a45a8ff	2922	(+) Configure External Clock source.
bogdanm	0:9b334a45a8ff	2923	(+) Configure Complementary channels, break features and dead time.
bogdanm	0:9b334a45a8ff	2924	(+) Configure Master and the Slave synchronization.
bogdanm	0:9b334a45a8ff	2925	(+) Configure the DMA Burst Mode.
bogdanm	0:9b334a45a8ff	2926
bogdanm	0:9b334a45a8ff	2927	@endverbatim
bogdanm	0:9b334a45a8ff	2928	* @{
bogdanm	0:9b334a45a8ff	2929	*/
bogdanm	0:9b334a45a8ff	2930
bogdanm	0:9b334a45a8ff	2931	/**
bogdanm	0:9b334a45a8ff	2932	* @brief Initializes the TIM Output Compare Channels according to the specified
bogdanm	0:9b334a45a8ff	2933	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	2934	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2935	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	2936	* @param sConfig: TIM Output Compare configuration structure
bogdanm	0:9b334a45a8ff	2937	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	2938	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2939	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	2940	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	2941	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	2942	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	2943	* @retval HAL status
bogdanm	0:9b334a45a8ff	2944	*/
bogdanm	0:9b334a45a8ff	2945	__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	2946	{
bogdanm	0:9b334a45a8ff	2947	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2948	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	2949	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	2950	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	2951	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm	0:9b334a45a8ff	2952	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm	0:9b334a45a8ff	2953	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm	0:9b334a45a8ff	2954
bogdanm	0:9b334a45a8ff	2955	/* Check input state */
bogdanm	0:9b334a45a8ff	2956	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	2957
bogdanm	0:9b334a45a8ff	2958	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2959
bogdanm	0:9b334a45a8ff	2960	switch (Channel)
bogdanm	0:9b334a45a8ff	2961	{
bogdanm	0:9b334a45a8ff	2962	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	2963	{
bogdanm	0:9b334a45a8ff	2964	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2965	/* Configure the TIM Channel 1 in Output Compare */
bogdanm	0:9b334a45a8ff	2966	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2967	}
bogdanm	0:9b334a45a8ff	2968	break;
bogdanm	0:9b334a45a8ff	2969
bogdanm	0:9b334a45a8ff	2970	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	2971	{
bogdanm	0:9b334a45a8ff	2972	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2973	/* Configure the TIM Channel 2 in Output Compare */
bogdanm	0:9b334a45a8ff	2974	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2975	}
bogdanm	0:9b334a45a8ff	2976	break;
bogdanm	0:9b334a45a8ff	2977
bogdanm	0:9b334a45a8ff	2978	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	2979	{
bogdanm	0:9b334a45a8ff	2980	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2981	/* Configure the TIM Channel 3 in Output Compare */
bogdanm	0:9b334a45a8ff	2982	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2983	}
bogdanm	0:9b334a45a8ff	2984	break;
bogdanm	0:9b334a45a8ff	2985
bogdanm	0:9b334a45a8ff	2986	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	2987	{
bogdanm	0:9b334a45a8ff	2988	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	2989	/* Configure the TIM Channel 4 in Output Compare */
bogdanm	0:9b334a45a8ff	2990	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	2991	}
bogdanm	0:9b334a45a8ff	2992	break;
bogdanm	0:9b334a45a8ff	2993
bogdanm	0:9b334a45a8ff	2994	default:
bogdanm	0:9b334a45a8ff	2995	break;
bogdanm	0:9b334a45a8ff	2996	}
bogdanm	0:9b334a45a8ff	2997	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	2998
bogdanm	0:9b334a45a8ff	2999	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3000
bogdanm	0:9b334a45a8ff	3001	return HAL_OK;
bogdanm	0:9b334a45a8ff	3002	}
bogdanm	0:9b334a45a8ff	3003
bogdanm	0:9b334a45a8ff	3004	/**
bogdanm	0:9b334a45a8ff	3005	* @brief Initializes the TIM Input Capture Channels according to the specified
bogdanm	0:9b334a45a8ff	3006	* parameters in the TIM_IC_InitTypeDef.
bogdanm	0:9b334a45a8ff	3007	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3008	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3009	* @param sConfig: TIM Input Capture configuration structure
bogdanm	0:9b334a45a8ff	3010	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	3011	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3012	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3013	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3014	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	3015	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	3016	* @retval HAL status
bogdanm	0:9b334a45a8ff	3017	*/
bogdanm	0:9b334a45a8ff	3018	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3019	{
bogdanm	0:9b334a45a8ff	3020	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3021	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3022	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
bogdanm	0:9b334a45a8ff	3023	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
bogdanm	0:9b334a45a8ff	3024	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
bogdanm	0:9b334a45a8ff	3025	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
bogdanm	0:9b334a45a8ff	3026
bogdanm	0:9b334a45a8ff	3027	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3028
bogdanm	0:9b334a45a8ff	3029	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3030
bogdanm	0:9b334a45a8ff	3031	if (Channel == TIM_CHANNEL_1)
bogdanm	0:9b334a45a8ff	3032	{
bogdanm	0:9b334a45a8ff	3033	/* TI1 Configuration */
bogdanm	0:9b334a45a8ff	3034	TIM_TI1_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3035	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3036	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3037	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3038
bogdanm	0:9b334a45a8ff	3039	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	3040	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	3041
bogdanm	0:9b334a45a8ff	3042	/* Set the IC1PSC value */
bogdanm	0:9b334a45a8ff	3043	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	3044	}
bogdanm	0:9b334a45a8ff	3045	else if (Channel == TIM_CHANNEL_2)
bogdanm	0:9b334a45a8ff	3046	{
bogdanm	0:9b334a45a8ff	3047	/* TI2 Configuration */
bogdanm	0:9b334a45a8ff	3048	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3049
bogdanm	0:9b334a45a8ff	3050	TIM_TI2_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3051	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3052	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3053	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3054
bogdanm	0:9b334a45a8ff	3055	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	3056	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	3057
bogdanm	0:9b334a45a8ff	3058	/* Set the IC2PSC value */
bogdanm	0:9b334a45a8ff	3059	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	3060	}
bogdanm	0:9b334a45a8ff	3061	else if (Channel == TIM_CHANNEL_3)
bogdanm	0:9b334a45a8ff	3062	{
bogdanm	0:9b334a45a8ff	3063	/* TI3 Configuration */
bogdanm	0:9b334a45a8ff	3064	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3065
bogdanm	0:9b334a45a8ff	3066	TIM_TI3_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3067	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3068	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3069	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3070
bogdanm	0:9b334a45a8ff	3071	/* Reset the IC3PSC Bits */
bogdanm	0:9b334a45a8ff	3072	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
bogdanm	0:9b334a45a8ff	3073
bogdanm	0:9b334a45a8ff	3074	/* Set the IC3PSC value */
bogdanm	0:9b334a45a8ff	3075	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
bogdanm	0:9b334a45a8ff	3076	}
bogdanm	0:9b334a45a8ff	3077	else
bogdanm	0:9b334a45a8ff	3078	{
bogdanm	0:9b334a45a8ff	3079	/* TI4 Configuration */
bogdanm	0:9b334a45a8ff	3080	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3081
bogdanm	0:9b334a45a8ff	3082	TIM_TI4_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3083	sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3084	sConfig->ICSelection,
bogdanm	0:9b334a45a8ff	3085	sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3086
bogdanm	0:9b334a45a8ff	3087	/* Reset the IC4PSC Bits */
bogdanm	0:9b334a45a8ff	3088	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
bogdanm	0:9b334a45a8ff	3089
bogdanm	0:9b334a45a8ff	3090	/* Set the IC4PSC value */
bogdanm	0:9b334a45a8ff	3091	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
bogdanm	0:9b334a45a8ff	3092	}
bogdanm	0:9b334a45a8ff	3093
bogdanm	0:9b334a45a8ff	3094	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3095
bogdanm	0:9b334a45a8ff	3096	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3097
bogdanm	0:9b334a45a8ff	3098	return HAL_OK;
bogdanm	0:9b334a45a8ff	3099	}
bogdanm	0:9b334a45a8ff	3100
bogdanm	0:9b334a45a8ff	3101	/**
bogdanm	0:9b334a45a8ff	3102	* @brief Initializes the TIM PWM channels according to the specified
bogdanm	0:9b334a45a8ff	3103	* parameters in the TIM_OC_InitTypeDef.
bogdanm	0:9b334a45a8ff	3104	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3105	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3106	* @param sConfig: TIM PWM configuration structure
bogdanm	0:9b334a45a8ff	3107	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	3108	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3109	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3110	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3111	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	3112	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	3113	* @retval HAL status
bogdanm	0:9b334a45a8ff	3114	*/
bogdanm	0:9b334a45a8ff	3115	__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3116	{
bogdanm	0:9b334a45a8ff	3117	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3118
bogdanm	0:9b334a45a8ff	3119	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3120	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	3121	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
bogdanm	0:9b334a45a8ff	3122	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm	0:9b334a45a8ff	3123	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm	0:9b334a45a8ff	3124	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm	0:9b334a45a8ff	3125	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm	0:9b334a45a8ff	3126	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
bogdanm	0:9b334a45a8ff	3127
bogdanm	0:9b334a45a8ff	3128	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3129
bogdanm	0:9b334a45a8ff	3130	switch (Channel)
bogdanm	0:9b334a45a8ff	3131	{
bogdanm	0:9b334a45a8ff	3132	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3133	{
bogdanm	0:9b334a45a8ff	3134	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3135	/* Configure the Channel 1 in PWM mode */
bogdanm	0:9b334a45a8ff	3136	TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3137
bogdanm	0:9b334a45a8ff	3138	/* Set the Preload enable bit for channel1 */
bogdanm	0:9b334a45a8ff	3139	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
bogdanm	0:9b334a45a8ff	3140
bogdanm	0:9b334a45a8ff	3141	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3142	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
bogdanm	0:9b334a45a8ff	3143	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3144	}
bogdanm	0:9b334a45a8ff	3145	break;
bogdanm	0:9b334a45a8ff	3146
bogdanm	0:9b334a45a8ff	3147	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3148	{
bogdanm	0:9b334a45a8ff	3149	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3150	/* Configure the Channel 2 in PWM mode */
bogdanm	0:9b334a45a8ff	3151	TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3152
bogdanm	0:9b334a45a8ff	3153	/* Set the Preload enable bit for channel2 */
bogdanm	0:9b334a45a8ff	3154	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
bogdanm	0:9b334a45a8ff	3155
bogdanm	0:9b334a45a8ff	3156	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3157	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
bogdanm	0:9b334a45a8ff	3158	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3159	}
bogdanm	0:9b334a45a8ff	3160	break;
bogdanm	0:9b334a45a8ff	3161
bogdanm	0:9b334a45a8ff	3162	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3163	{
bogdanm	0:9b334a45a8ff	3164	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3165	/* Configure the Channel 3 in PWM mode */
bogdanm	0:9b334a45a8ff	3166	TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3167
bogdanm	0:9b334a45a8ff	3168	/* Set the Preload enable bit for channel3 */
bogdanm	0:9b334a45a8ff	3169	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
bogdanm	0:9b334a45a8ff	3170
bogdanm	0:9b334a45a8ff	3171	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3172	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
bogdanm	0:9b334a45a8ff	3173	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
bogdanm	0:9b334a45a8ff	3174	}
bogdanm	0:9b334a45a8ff	3175	break;
bogdanm	0:9b334a45a8ff	3176
bogdanm	0:9b334a45a8ff	3177	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3178	{
bogdanm	0:9b334a45a8ff	3179	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3180	/* Configure the Channel 4 in PWM mode */
bogdanm	0:9b334a45a8ff	3181	TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm	0:9b334a45a8ff	3182
bogdanm	0:9b334a45a8ff	3183	/* Set the Preload enable bit for channel4 */
bogdanm	0:9b334a45a8ff	3184	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
bogdanm	0:9b334a45a8ff	3185
bogdanm	0:9b334a45a8ff	3186	/* Configure the Output Fast mode */
bogdanm	0:9b334a45a8ff	3187	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
bogdanm	0:9b334a45a8ff	3188	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
bogdanm	0:9b334a45a8ff	3189	}
bogdanm	0:9b334a45a8ff	3190	break;
bogdanm	0:9b334a45a8ff	3191
bogdanm	0:9b334a45a8ff	3192	default:
bogdanm	0:9b334a45a8ff	3193	break;
bogdanm	0:9b334a45a8ff	3194	}
bogdanm	0:9b334a45a8ff	3195
bogdanm	0:9b334a45a8ff	3196	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3197
bogdanm	0:9b334a45a8ff	3198	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3199
bogdanm	0:9b334a45a8ff	3200	return HAL_OK;
bogdanm	0:9b334a45a8ff	3201	}
bogdanm	0:9b334a45a8ff	3202
bogdanm	0:9b334a45a8ff	3203	/**
bogdanm	0:9b334a45a8ff	3204	* @brief Initializes the TIM One Pulse Channels according to the specified
bogdanm	0:9b334a45a8ff	3205	* parameters in the TIM_OnePulse_InitTypeDef.
bogdanm	0:9b334a45a8ff	3206	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3207	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3208	* @param sConfig: TIM One Pulse configuration structure
bogdanm	0:9b334a45a8ff	3209	* @param OutputChannel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	3210	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3211	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3212	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3213	* @param InputChannel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	3214	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3215	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3216	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3217	* @retval HAL status
bogdanm	0:9b334a45a8ff	3218	*/
bogdanm	0:9b334a45a8ff	3219	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
bogdanm	0:9b334a45a8ff	3220	{
bogdanm	0:9b334a45a8ff	3221	TIM_OC_InitTypeDef temp1;
bogdanm	0:9b334a45a8ff	3222
bogdanm	0:9b334a45a8ff	3223	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3224	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
bogdanm	0:9b334a45a8ff	3225	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
bogdanm	0:9b334a45a8ff	3226
bogdanm	0:9b334a45a8ff	3227	if(OutputChannel != InputChannel)
bogdanm	0:9b334a45a8ff	3228	{
bogdanm	0:9b334a45a8ff	3229	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3230
bogdanm	0:9b334a45a8ff	3231	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3232
bogdanm	0:9b334a45a8ff	3233	/* Extract the Output compare configuration from sConfig structure */
bogdanm	0:9b334a45a8ff	3234	temp1.OCMode = sConfig->OCMode;
bogdanm	0:9b334a45a8ff	3235	temp1.Pulse = sConfig->Pulse;
bogdanm	0:9b334a45a8ff	3236	temp1.OCPolarity = sConfig->OCPolarity;
bogdanm	0:9b334a45a8ff	3237	temp1.OCNPolarity = sConfig->OCNPolarity;
bogdanm	0:9b334a45a8ff	3238	temp1.OCIdleState = sConfig->OCIdleState;
bogdanm	0:9b334a45a8ff	3239	temp1.OCNIdleState = sConfig->OCNIdleState;
bogdanm	0:9b334a45a8ff	3240
bogdanm	0:9b334a45a8ff	3241	switch (OutputChannel)
bogdanm	0:9b334a45a8ff	3242	{
bogdanm	0:9b334a45a8ff	3243	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3244	{
bogdanm	0:9b334a45a8ff	3245	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3246
bogdanm	0:9b334a45a8ff	3247	TIM_OC1_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3248	}
bogdanm	0:9b334a45a8ff	3249	break;
bogdanm	0:9b334a45a8ff	3250	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3251	{
bogdanm	0:9b334a45a8ff	3252	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3253
bogdanm	0:9b334a45a8ff	3254	TIM_OC2_SetConfig(htim->Instance, &temp1);
bogdanm	0:9b334a45a8ff	3255	}
bogdanm	0:9b334a45a8ff	3256	break;
bogdanm	0:9b334a45a8ff	3257	default:
bogdanm	0:9b334a45a8ff	3258	break;
bogdanm	0:9b334a45a8ff	3259	}
bogdanm	0:9b334a45a8ff	3260	switch (InputChannel)
bogdanm	0:9b334a45a8ff	3261	{
bogdanm	0:9b334a45a8ff	3262	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3263	{
bogdanm	0:9b334a45a8ff	3264	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3265
bogdanm	0:9b334a45a8ff	3266	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3267	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3268
bogdanm	0:9b334a45a8ff	3269	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	3270	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	3271
bogdanm	0:9b334a45a8ff	3272	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3273	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3274	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
bogdanm	0:9b334a45a8ff	3275
bogdanm	0:9b334a45a8ff	3276	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3277	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3278	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3279	}
bogdanm	0:9b334a45a8ff	3280	break;
bogdanm	0:9b334a45a8ff	3281	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3282	{
bogdanm	0:9b334a45a8ff	3283	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3284
bogdanm	0:9b334a45a8ff	3285	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm	0:9b334a45a8ff	3286	sConfig->ICSelection, sConfig->ICFilter);
bogdanm	0:9b334a45a8ff	3287
bogdanm	0:9b334a45a8ff	3288	/* Reset the IC2PSC Bits */
bogdanm	0:9b334a45a8ff	3289	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm	0:9b334a45a8ff	3290
bogdanm	0:9b334a45a8ff	3291	/* Select the Trigger source */
bogdanm	0:9b334a45a8ff	3292	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	3293	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
bogdanm	0:9b334a45a8ff	3294
bogdanm	0:9b334a45a8ff	3295	/* Select the Slave Mode */
bogdanm	0:9b334a45a8ff	3296	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3297	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
bogdanm	0:9b334a45a8ff	3298	}
bogdanm	0:9b334a45a8ff	3299	break;
bogdanm	0:9b334a45a8ff	3300
bogdanm	0:9b334a45a8ff	3301	default:
bogdanm	0:9b334a45a8ff	3302	break;
bogdanm	0:9b334a45a8ff	3303	}
bogdanm	0:9b334a45a8ff	3304
bogdanm	0:9b334a45a8ff	3305	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3306
bogdanm	0:9b334a45a8ff	3307	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3308
bogdanm	0:9b334a45a8ff	3309	return HAL_OK;
bogdanm	0:9b334a45a8ff	3310	}
bogdanm	0:9b334a45a8ff	3311	else
bogdanm	0:9b334a45a8ff	3312	{
bogdanm	0:9b334a45a8ff	3313	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3314	}
bogdanm	0:9b334a45a8ff	3315	}
bogdanm	0:9b334a45a8ff	3316
bogdanm	0:9b334a45a8ff	3317	/**
bogdanm	0:9b334a45a8ff	3318	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
bogdanm	0:9b334a45a8ff	3319	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3320	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3321	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
bogdanm	0:9b334a45a8ff	3322	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3323	* @arg TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	3324	* @arg TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	3325	* @arg TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	3326	* @arg TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	3327	* @arg TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	3328	* @arg TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	3329	* @arg TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	3330	* @arg TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	3331	* @arg TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	3332	* @arg TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	3333	* @arg TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	3334	* @arg TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	3335	* @arg TIM_DMABASE_RCR
bogdanm	0:9b334a45a8ff	3336	* @arg TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	3337	* @arg TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	3338	* @arg TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	3339	* @arg TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	3340	* @arg TIM_DMABASE_BDTR
bogdanm	0:9b334a45a8ff	3341	* @arg TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	3342	* @param BurstRequestSrc: TIM DMA Request sources.
bogdanm	0:9b334a45a8ff	3343	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3344	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3345	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3346	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3347	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3348	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3349	* @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm	0:9b334a45a8ff	3350	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3351	* @param BurstBuffer: The Buffer address.
bogdanm	0:9b334a45a8ff	3352	* @param BurstLength: DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3353	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
bogdanm	0:9b334a45a8ff	3354	* @retval HAL status
bogdanm	0:9b334a45a8ff	3355	*/
bogdanm	0:9b334a45a8ff	3356	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3357	uint32_t* BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3358	{
bogdanm	0:9b334a45a8ff	3359	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3360	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3361	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3362	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3363	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3364
bogdanm	0:9b334a45a8ff	3365	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3366	{
bogdanm	0:9b334a45a8ff	3367	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3368	}
bogdanm	0:9b334a45a8ff	3369	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3370	{
bogdanm	0:9b334a45a8ff	3371	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3372	{
bogdanm	0:9b334a45a8ff	3373	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3374	}
bogdanm	0:9b334a45a8ff	3375	else
bogdanm	0:9b334a45a8ff	3376	{
bogdanm	0:9b334a45a8ff	3377	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3378	}
bogdanm	0:9b334a45a8ff	3379	}
bogdanm	0:9b334a45a8ff	3380	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3381	{
bogdanm	0:9b334a45a8ff	3382	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3383	{
bogdanm	0:9b334a45a8ff	3384	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3385	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3386
bogdanm	0:9b334a45a8ff	3387	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3388	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3389
bogdanm	0:9b334a45a8ff	3390	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3391	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3392	}
bogdanm	0:9b334a45a8ff	3393	break;
bogdanm	0:9b334a45a8ff	3394	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3395	{
bogdanm	0:9b334a45a8ff	3396	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3397	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3398
bogdanm	0:9b334a45a8ff	3399	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3400	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3401
bogdanm	0:9b334a45a8ff	3402	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3403	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3404	}
bogdanm	0:9b334a45a8ff	3405	break;
bogdanm	0:9b334a45a8ff	3406	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3407	{
bogdanm	0:9b334a45a8ff	3408	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3409	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3410
bogdanm	0:9b334a45a8ff	3411	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3412	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3413
bogdanm	0:9b334a45a8ff	3414	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3415	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3416	}
bogdanm	0:9b334a45a8ff	3417	break;
bogdanm	0:9b334a45a8ff	3418	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3419	{
bogdanm	0:9b334a45a8ff	3420	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3421	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3422
bogdanm	0:9b334a45a8ff	3423	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3424	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3425
bogdanm	0:9b334a45a8ff	3426	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3427	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3428	}
bogdanm	0:9b334a45a8ff	3429	break;
bogdanm	0:9b334a45a8ff	3430	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3431	{
bogdanm	0:9b334a45a8ff	3432	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3433	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	3434
bogdanm	0:9b334a45a8ff	3435	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3436	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3437
bogdanm	0:9b334a45a8ff	3438	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3439	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3440	}
bogdanm	0:9b334a45a8ff	3441	break;
bogdanm	0:9b334a45a8ff	3442	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3443	{
bogdanm	0:9b334a45a8ff	3444	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3445	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	3446
bogdanm	0:9b334a45a8ff	3447	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3448	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3449
bogdanm	0:9b334a45a8ff	3450	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3451	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3452	}
bogdanm	0:9b334a45a8ff	3453	break;
bogdanm	0:9b334a45a8ff	3454	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3455	{
bogdanm	0:9b334a45a8ff	3456	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3457	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3458
bogdanm	0:9b334a45a8ff	3459	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3460	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3461
bogdanm	0:9b334a45a8ff	3462	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3463	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3464	}
bogdanm	0:9b334a45a8ff	3465	break;
bogdanm	0:9b334a45a8ff	3466	default:
bogdanm	0:9b334a45a8ff	3467	break;
bogdanm	0:9b334a45a8ff	3468	}
bogdanm	0:9b334a45a8ff	3469	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3470	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3471
bogdanm	0:9b334a45a8ff	3472	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3473	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3474
bogdanm	0:9b334a45a8ff	3475	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3476
bogdanm	0:9b334a45a8ff	3477	/* Return function status */
bogdanm	0:9b334a45a8ff	3478	return HAL_OK;
bogdanm	0:9b334a45a8ff	3479	}
bogdanm	0:9b334a45a8ff	3480
bogdanm	0:9b334a45a8ff	3481	/**
bogdanm	0:9b334a45a8ff	3482	* @brief Stops the TIM DMA Burst mode
bogdanm	0:9b334a45a8ff	3483	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3484	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3485	* @param BurstRequestSrc: TIM DMA Request sources to disable
bogdanm	0:9b334a45a8ff	3486	* @retval HAL status
bogdanm	0:9b334a45a8ff	3487	*/
bogdanm	0:9b334a45a8ff	3488	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3489	{
bogdanm	0:9b334a45a8ff	3490	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3491	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3492
bogdanm	0:9b334a45a8ff	3493	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3494	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3495	{
bogdanm	0:9b334a45a8ff	3496	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3497	{
bogdanm	0:9b334a45a8ff	3498	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3499	}
bogdanm	0:9b334a45a8ff	3500	break;
bogdanm	0:9b334a45a8ff	3501	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3502	{
bogdanm	0:9b334a45a8ff	3503	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3504	}
bogdanm	0:9b334a45a8ff	3505	break;
bogdanm	0:9b334a45a8ff	3506	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3507	{
bogdanm	0:9b334a45a8ff	3508	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3509	}
bogdanm	0:9b334a45a8ff	3510	break;
bogdanm	0:9b334a45a8ff	3511	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3512	{
bogdanm	0:9b334a45a8ff	3513	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3514	}
bogdanm	0:9b334a45a8ff	3515	break;
bogdanm	0:9b334a45a8ff	3516	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3517	{
bogdanm	0:9b334a45a8ff	3518	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3519	}
bogdanm	0:9b334a45a8ff	3520	break;
bogdanm	0:9b334a45a8ff	3521	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3522	{
bogdanm	0:9b334a45a8ff	3523	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm	0:9b334a45a8ff	3524	}
bogdanm	0:9b334a45a8ff	3525	break;
bogdanm	0:9b334a45a8ff	3526	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3527	{
bogdanm	0:9b334a45a8ff	3528	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3529	}
bogdanm	0:9b334a45a8ff	3530	break;
bogdanm	0:9b334a45a8ff	3531	default:
bogdanm	0:9b334a45a8ff	3532	break;
bogdanm	0:9b334a45a8ff	3533	}
bogdanm	0:9b334a45a8ff	3534
bogdanm	0:9b334a45a8ff	3535	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3536	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3537
bogdanm	0:9b334a45a8ff	3538	/* Return function status */
bogdanm	0:9b334a45a8ff	3539	return HAL_OK;
bogdanm	0:9b334a45a8ff	3540	}
bogdanm	0:9b334a45a8ff	3541
bogdanm	0:9b334a45a8ff	3542	/**
bogdanm	0:9b334a45a8ff	3543	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
bogdanm	0:9b334a45a8ff	3544	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3545	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3546	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
bogdanm	0:9b334a45a8ff	3547	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3548	* @arg TIM_DMABASE_CR1
bogdanm	0:9b334a45a8ff	3549	* @arg TIM_DMABASE_CR2
bogdanm	0:9b334a45a8ff	3550	* @arg TIM_DMABASE_SMCR
bogdanm	0:9b334a45a8ff	3551	* @arg TIM_DMABASE_DIER
bogdanm	0:9b334a45a8ff	3552	* @arg TIM_DMABASE_SR
bogdanm	0:9b334a45a8ff	3553	* @arg TIM_DMABASE_EGR
bogdanm	0:9b334a45a8ff	3554	* @arg TIM_DMABASE_CCMR1
bogdanm	0:9b334a45a8ff	3555	* @arg TIM_DMABASE_CCMR2
bogdanm	0:9b334a45a8ff	3556	* @arg TIM_DMABASE_CCER
bogdanm	0:9b334a45a8ff	3557	* @arg TIM_DMABASE_CNT
bogdanm	0:9b334a45a8ff	3558	* @arg TIM_DMABASE_PSC
bogdanm	0:9b334a45a8ff	3559	* @arg TIM_DMABASE_ARR
bogdanm	0:9b334a45a8ff	3560	* @arg TIM_DMABASE_RCR
bogdanm	0:9b334a45a8ff	3561	* @arg TIM_DMABASE_CCR1
bogdanm	0:9b334a45a8ff	3562	* @arg TIM_DMABASE_CCR2
bogdanm	0:9b334a45a8ff	3563	* @arg TIM_DMABASE_CCR3
bogdanm	0:9b334a45a8ff	3564	* @arg TIM_DMABASE_CCR4
bogdanm	0:9b334a45a8ff	3565	* @arg TIM_DMABASE_BDTR
bogdanm	0:9b334a45a8ff	3566	* @arg TIM_DMABASE_DCR
bogdanm	0:9b334a45a8ff	3567	* @param BurstRequestSrc: TIM DMA Request sources.
bogdanm	0:9b334a45a8ff	3568	* This parameters can be on of the following values:
bogdanm	0:9b334a45a8ff	3569	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm	0:9b334a45a8ff	3570	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm	0:9b334a45a8ff	3571	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm	0:9b334a45a8ff	3572	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm	0:9b334a45a8ff	3573	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm	0:9b334a45a8ff	3574	* @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm	0:9b334a45a8ff	3575	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm	0:9b334a45a8ff	3576	* @param BurstBuffer: The Buffer address.
bogdanm	0:9b334a45a8ff	3577	* @param BurstLength: DMA Burst length. This parameter can be one value
bogdanm	0:9b334a45a8ff	3578	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
bogdanm	0:9b334a45a8ff	3579	* @retval HAL status
bogdanm	0:9b334a45a8ff	3580	*/
bogdanm	0:9b334a45a8ff	3581	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm	0:9b334a45a8ff	3582	uint32_t *BurstBuffer, uint32_t BurstLength)
bogdanm	0:9b334a45a8ff	3583	{
bogdanm	0:9b334a45a8ff	3584	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3585	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3586	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm	0:9b334a45a8ff	3587	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3588	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm	0:9b334a45a8ff	3589
bogdanm	0:9b334a45a8ff	3590	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	3591	{
bogdanm	0:9b334a45a8ff	3592	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	3593	}
bogdanm	0:9b334a45a8ff	3594	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	3595	{
bogdanm	0:9b334a45a8ff	3596	if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm	0:9b334a45a8ff	3597	{
bogdanm	0:9b334a45a8ff	3598	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3599	}
bogdanm	0:9b334a45a8ff	3600	else
bogdanm	0:9b334a45a8ff	3601	{
bogdanm	0:9b334a45a8ff	3602	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3603	}
bogdanm	0:9b334a45a8ff	3604	}
bogdanm	0:9b334a45a8ff	3605	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3606	{
bogdanm	0:9b334a45a8ff	3607	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3608	{
bogdanm	0:9b334a45a8ff	3609	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3610	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm	0:9b334a45a8ff	3611
bogdanm	0:9b334a45a8ff	3612	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3613	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3614
bogdanm	0:9b334a45a8ff	3615	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3616	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3617	}
bogdanm	0:9b334a45a8ff	3618	break;
bogdanm	0:9b334a45a8ff	3619	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3620	{
bogdanm	0:9b334a45a8ff	3621	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3622	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3623
bogdanm	0:9b334a45a8ff	3624	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3625	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3626
bogdanm	0:9b334a45a8ff	3627	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3628	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3629	}
bogdanm	0:9b334a45a8ff	3630	break;
bogdanm	0:9b334a45a8ff	3631	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3632	{
bogdanm	0:9b334a45a8ff	3633	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3634	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3635
bogdanm	0:9b334a45a8ff	3636	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3637	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3638
bogdanm	0:9b334a45a8ff	3639	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3640	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3641	}
bogdanm	0:9b334a45a8ff	3642	break;
bogdanm	0:9b334a45a8ff	3643	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3644	{
bogdanm	0:9b334a45a8ff	3645	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3646	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3647
bogdanm	0:9b334a45a8ff	3648	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3649	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3650
bogdanm	0:9b334a45a8ff	3651	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3652	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3653	}
bogdanm	0:9b334a45a8ff	3654	break;
bogdanm	0:9b334a45a8ff	3655	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3656	{
bogdanm	0:9b334a45a8ff	3657	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3658	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	3659
bogdanm	0:9b334a45a8ff	3660	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3661	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3662
bogdanm	0:9b334a45a8ff	3663	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3664	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3665	}
bogdanm	0:9b334a45a8ff	3666	break;
bogdanm	0:9b334a45a8ff	3667	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3668	{
bogdanm	0:9b334a45a8ff	3669	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3670	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	3671
bogdanm	0:9b334a45a8ff	3672	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3673	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3674
bogdanm	0:9b334a45a8ff	3675	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3676	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3677	}
bogdanm	0:9b334a45a8ff	3678	break;
bogdanm	0:9b334a45a8ff	3679	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3680	{
bogdanm	0:9b334a45a8ff	3681	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	3682	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm	0:9b334a45a8ff	3683
bogdanm	0:9b334a45a8ff	3684	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	3685	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
bogdanm	0:9b334a45a8ff	3686
bogdanm	0:9b334a45a8ff	3687	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	3688	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm	0:9b334a45a8ff	3689	}
bogdanm	0:9b334a45a8ff	3690	break;
bogdanm	0:9b334a45a8ff	3691	default:
bogdanm	0:9b334a45a8ff	3692	break;
bogdanm	0:9b334a45a8ff	3693	}
bogdanm	0:9b334a45a8ff	3694
bogdanm	0:9b334a45a8ff	3695	/* configure the DMA Burst Mode */
bogdanm	0:9b334a45a8ff	3696	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
bogdanm	0:9b334a45a8ff	3697
bogdanm	0:9b334a45a8ff	3698	/* Enable the TIM DMA Request */
bogdanm	0:9b334a45a8ff	3699	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3700
bogdanm	0:9b334a45a8ff	3701	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3702
bogdanm	0:9b334a45a8ff	3703	/* Return function status */
bogdanm	0:9b334a45a8ff	3704	return HAL_OK;
bogdanm	0:9b334a45a8ff	3705	}
bogdanm	0:9b334a45a8ff	3706
bogdanm	0:9b334a45a8ff	3707	/**
bogdanm	0:9b334a45a8ff	3708	* @brief Stop the DMA burst reading
bogdanm	0:9b334a45a8ff	3709	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3710	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3711	* @param BurstRequestSrc: TIM DMA Request sources to disable.
bogdanm	0:9b334a45a8ff	3712	* @retval HAL status
bogdanm	0:9b334a45a8ff	3713	*/
bogdanm	0:9b334a45a8ff	3714	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3715	{
bogdanm	0:9b334a45a8ff	3716	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3717	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm	0:9b334a45a8ff	3718
bogdanm	0:9b334a45a8ff	3719	/* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm	0:9b334a45a8ff	3720	switch(BurstRequestSrc)
bogdanm	0:9b334a45a8ff	3721	{
bogdanm	0:9b334a45a8ff	3722	case TIM_DMA_UPDATE:
bogdanm	0:9b334a45a8ff	3723	{
bogdanm	0:9b334a45a8ff	3724	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm	0:9b334a45a8ff	3725	}
bogdanm	0:9b334a45a8ff	3726	break;
bogdanm	0:9b334a45a8ff	3727	case TIM_DMA_CC1:
bogdanm	0:9b334a45a8ff	3728	{
bogdanm	0:9b334a45a8ff	3729	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm	0:9b334a45a8ff	3730	}
bogdanm	0:9b334a45a8ff	3731	break;
bogdanm	0:9b334a45a8ff	3732	case TIM_DMA_CC2:
bogdanm	0:9b334a45a8ff	3733	{
bogdanm	0:9b334a45a8ff	3734	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm	0:9b334a45a8ff	3735	}
bogdanm	0:9b334a45a8ff	3736	break;
bogdanm	0:9b334a45a8ff	3737	case TIM_DMA_CC3:
bogdanm	0:9b334a45a8ff	3738	{
bogdanm	0:9b334a45a8ff	3739	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm	0:9b334a45a8ff	3740	}
bogdanm	0:9b334a45a8ff	3741	break;
bogdanm	0:9b334a45a8ff	3742	case TIM_DMA_CC4:
bogdanm	0:9b334a45a8ff	3743	{
bogdanm	0:9b334a45a8ff	3744	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm	0:9b334a45a8ff	3745	}
bogdanm	0:9b334a45a8ff	3746	break;
bogdanm	0:9b334a45a8ff	3747	case TIM_DMA_COM:
bogdanm	0:9b334a45a8ff	3748	{
bogdanm	0:9b334a45a8ff	3749	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm	0:9b334a45a8ff	3750	}
bogdanm	0:9b334a45a8ff	3751	break;
bogdanm	0:9b334a45a8ff	3752	case TIM_DMA_TRIGGER:
bogdanm	0:9b334a45a8ff	3753	{
bogdanm	0:9b334a45a8ff	3754	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm	0:9b334a45a8ff	3755	}
bogdanm	0:9b334a45a8ff	3756	break;
bogdanm	0:9b334a45a8ff	3757	default:
bogdanm	0:9b334a45a8ff	3758	break;
bogdanm	0:9b334a45a8ff	3759	}
bogdanm	0:9b334a45a8ff	3760
bogdanm	0:9b334a45a8ff	3761	/* Disable the TIM Update DMA request */
bogdanm	0:9b334a45a8ff	3762	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm	0:9b334a45a8ff	3763
bogdanm	0:9b334a45a8ff	3764	/* Return function status */
bogdanm	0:9b334a45a8ff	3765	return HAL_OK;
bogdanm	0:9b334a45a8ff	3766	}
bogdanm	0:9b334a45a8ff	3767
bogdanm	0:9b334a45a8ff	3768	/**
bogdanm	0:9b334a45a8ff	3769	* @brief Generate a software event
bogdanm	0:9b334a45a8ff	3770	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3771	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3772	* @param EventSource: specifies the event source.
bogdanm	0:9b334a45a8ff	3773	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3774	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
bogdanm	0:9b334a45a8ff	3775	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
bogdanm	0:9b334a45a8ff	3776	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
bogdanm	0:9b334a45a8ff	3777	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
bogdanm	0:9b334a45a8ff	3778	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
bogdanm	0:9b334a45a8ff	3779	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
bogdanm	0:9b334a45a8ff	3780	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
bogdanm	0:9b334a45a8ff	3781	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
bogdanm	0:9b334a45a8ff	3782	* @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
bogdanm	0:9b334a45a8ff	3783	* @note TIM6 and TIM7 can only generate an update event.
bogdanm	0:9b334a45a8ff	3784	* @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
bogdanm	0:9b334a45a8ff	3785	* @retval HAL status
bogdanm	0:9b334a45a8ff	3786	*/
bogdanm	0:9b334a45a8ff	3787
bogdanm	0:9b334a45a8ff	3788	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
bogdanm	0:9b334a45a8ff	3789	{
bogdanm	0:9b334a45a8ff	3790	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3791	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3792	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
bogdanm	0:9b334a45a8ff	3793
bogdanm	0:9b334a45a8ff	3794	/* Process Locked */
bogdanm	0:9b334a45a8ff	3795	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3796
bogdanm	0:9b334a45a8ff	3797	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3798	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3799
bogdanm	0:9b334a45a8ff	3800	/* Set the event sources */
bogdanm	0:9b334a45a8ff	3801	htim->Instance->EGR = EventSource;
bogdanm	0:9b334a45a8ff	3802
bogdanm	0:9b334a45a8ff	3803	/* Change the TIM state */
bogdanm	0:9b334a45a8ff	3804	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3805
bogdanm	0:9b334a45a8ff	3806	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3807
bogdanm	0:9b334a45a8ff	3808	/* Return function status */
bogdanm	0:9b334a45a8ff	3809	return HAL_OK;
bogdanm	0:9b334a45a8ff	3810	}
bogdanm	0:9b334a45a8ff	3811
bogdanm	0:9b334a45a8ff	3812	/**
bogdanm	0:9b334a45a8ff	3813	* @brief Configures the OCRef clear feature
bogdanm	0:9b334a45a8ff	3814	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3815	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3816	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3817	* contains the OCREF clear feature and parameters for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3818	* @param Channel: specifies the TIM Channel.
bogdanm	0:9b334a45a8ff	3819	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3820	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	3821	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	3822	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	3823	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	3824	* @retval HAL status
bogdanm	0:9b334a45a8ff	3825	*/
bogdanm	0:9b334a45a8ff	3826	__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
bogdanm	0:9b334a45a8ff	3827	{
bogdanm	0:9b334a45a8ff	3828	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3829	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3830	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	3831	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
bogdanm	0:9b334a45a8ff	3832
bogdanm	0:9b334a45a8ff	3833	/* Process Locked */
bogdanm	0:9b334a45a8ff	3834	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3835
bogdanm	0:9b334a45a8ff	3836	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3837
bogdanm	0:9b334a45a8ff	3838	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
bogdanm	0:9b334a45a8ff	3839	{
bogdanm	0:9b334a45a8ff	3840	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
bogdanm	0:9b334a45a8ff	3841	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
bogdanm	0:9b334a45a8ff	3842	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
bogdanm	0:9b334a45a8ff	3843
bogdanm	0:9b334a45a8ff	3844	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3845	sClearInputConfig->ClearInputPrescaler,
bogdanm	0:9b334a45a8ff	3846	sClearInputConfig->ClearInputPolarity,
bogdanm	0:9b334a45a8ff	3847	sClearInputConfig->ClearInputFilter);
bogdanm	0:9b334a45a8ff	3848	}
bogdanm	0:9b334a45a8ff	3849
bogdanm	0:9b334a45a8ff	3850	switch (Channel)
bogdanm	0:9b334a45a8ff	3851	{
bogdanm	0:9b334a45a8ff	3852	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	3853	{
bogdanm	0:9b334a45a8ff	3854	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3855	{
bogdanm	0:9b334a45a8ff	3856	/* Enable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3857	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3858	}
bogdanm	0:9b334a45a8ff	3859	else
bogdanm	0:9b334a45a8ff	3860	{
bogdanm	0:9b334a45a8ff	3861	/* Disable the Ocref clear feature for Channel 1 */
bogdanm	0:9b334a45a8ff	3862	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
bogdanm	0:9b334a45a8ff	3863	}
bogdanm	0:9b334a45a8ff	3864	}
bogdanm	0:9b334a45a8ff	3865	break;
bogdanm	0:9b334a45a8ff	3866	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	3867	{
bogdanm	0:9b334a45a8ff	3868	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3869	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3870	{
bogdanm	0:9b334a45a8ff	3871	/* Enable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3872	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3873	}
bogdanm	0:9b334a45a8ff	3874	else
bogdanm	0:9b334a45a8ff	3875	{
bogdanm	0:9b334a45a8ff	3876	/* Disable the Ocref clear feature for Channel 2 */
bogdanm	0:9b334a45a8ff	3877	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
bogdanm	0:9b334a45a8ff	3878	}
bogdanm	0:9b334a45a8ff	3879	}
bogdanm	0:9b334a45a8ff	3880	break;
bogdanm	0:9b334a45a8ff	3881	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	3882	{
bogdanm	0:9b334a45a8ff	3883	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3884	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3885	{
bogdanm	0:9b334a45a8ff	3886	/* Enable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3887	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3888	}
bogdanm	0:9b334a45a8ff	3889	else
bogdanm	0:9b334a45a8ff	3890	{
bogdanm	0:9b334a45a8ff	3891	/* Disable the Ocref clear feature for Channel 3 */
bogdanm	0:9b334a45a8ff	3892	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
bogdanm	0:9b334a45a8ff	3893	}
bogdanm	0:9b334a45a8ff	3894	}
bogdanm	0:9b334a45a8ff	3895	break;
bogdanm	0:9b334a45a8ff	3896	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	3897	{
bogdanm	0:9b334a45a8ff	3898	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3899	if(sClearInputConfig->ClearInputState != RESET)
bogdanm	0:9b334a45a8ff	3900	{
bogdanm	0:9b334a45a8ff	3901	/* Enable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3902	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3903	}
bogdanm	0:9b334a45a8ff	3904	else
bogdanm	0:9b334a45a8ff	3905	{
bogdanm	0:9b334a45a8ff	3906	/* Disable the Ocref clear feature for Channel 4 */
bogdanm	0:9b334a45a8ff	3907	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
bogdanm	0:9b334a45a8ff	3908	}
bogdanm	0:9b334a45a8ff	3909	}
bogdanm	0:9b334a45a8ff	3910	break;
bogdanm	0:9b334a45a8ff	3911	default:
bogdanm	0:9b334a45a8ff	3912	break;
bogdanm	0:9b334a45a8ff	3913	}
bogdanm	0:9b334a45a8ff	3914
bogdanm	0:9b334a45a8ff	3915	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	3916
bogdanm	0:9b334a45a8ff	3917	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	3918
bogdanm	0:9b334a45a8ff	3919	return HAL_OK;
bogdanm	0:9b334a45a8ff	3920	}
bogdanm	0:9b334a45a8ff	3921
bogdanm	0:9b334a45a8ff	3922	/**
bogdanm	0:9b334a45a8ff	3923	* @brief Configures the clock source to be used
bogdanm	0:9b334a45a8ff	3924	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3925	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	3926	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	3927	* contains the clock source information for the TIM peripheral.
bogdanm	0:9b334a45a8ff	3928	* @retval HAL status
bogdanm	0:9b334a45a8ff	3929	*/
bogdanm	0:9b334a45a8ff	3930	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
bogdanm	0:9b334a45a8ff	3931	{
bogdanm	0:9b334a45a8ff	3932	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	3933
bogdanm	0:9b334a45a8ff	3934	/* Process Locked */
bogdanm	0:9b334a45a8ff	3935	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	3936
bogdanm	0:9b334a45a8ff	3937	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	3938
bogdanm	0:9b334a45a8ff	3939	/* Check the parameters */
bogdanm	0:9b334a45a8ff	3940	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
bogdanm	0:9b334a45a8ff	3941	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
bogdanm	0:9b334a45a8ff	3942	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
bogdanm	0:9b334a45a8ff	3943	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
bogdanm	0:9b334a45a8ff	3944
bogdanm	0:9b334a45a8ff	3945	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
bogdanm	0:9b334a45a8ff	3946	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	3947	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	3948	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	3949	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3950
bogdanm	0:9b334a45a8ff	3951	switch (sClockSourceConfig->ClockSource)
bogdanm	0:9b334a45a8ff	3952	{
bogdanm	0:9b334a45a8ff	3953	case TIM_CLOCKSOURCE_INTERNAL:
bogdanm	0:9b334a45a8ff	3954	{
bogdanm	0:9b334a45a8ff	3955	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3956	/* Disable slave mode to clock the prescaler directly with the internal clock */
bogdanm	0:9b334a45a8ff	3957	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	3958	}
bogdanm	0:9b334a45a8ff	3959	break;
bogdanm	0:9b334a45a8ff	3960
bogdanm	0:9b334a45a8ff	3961	case TIM_CLOCKSOURCE_ETRMODE1:
bogdanm	0:9b334a45a8ff	3962	{
bogdanm	0:9b334a45a8ff	3963	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3964	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	3965	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3966	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	3967	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3968	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3969	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	3970	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	3971	/* Reset the SMS and TS Bits */
bogdanm	0:9b334a45a8ff	3972	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
bogdanm	0:9b334a45a8ff	3973	/* Select the External clock mode1 and the ETRF trigger */
bogdanm	0:9b334a45a8ff	3974	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
bogdanm	0:9b334a45a8ff	3975	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	3976	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	3977	}
bogdanm	0:9b334a45a8ff	3978	break;
bogdanm	0:9b334a45a8ff	3979
bogdanm	0:9b334a45a8ff	3980	case TIM_CLOCKSOURCE_ETRMODE2:
bogdanm	0:9b334a45a8ff	3981	{
bogdanm	0:9b334a45a8ff	3982	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3983	/* Configure the ETR Clock source */
bogdanm	0:9b334a45a8ff	3984	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	3985	sClockSourceConfig->ClockPrescaler,
bogdanm	0:9b334a45a8ff	3986	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3987	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3988	/* Enable the External clock mode2 */
bogdanm	0:9b334a45a8ff	3989	htim->Instance->SMCR \|= TIM_SMCR_ECE;
bogdanm	0:9b334a45a8ff	3990	}
bogdanm	0:9b334a45a8ff	3991	break;
bogdanm	0:9b334a45a8ff	3992
bogdanm	0:9b334a45a8ff	3993	case TIM_CLOCKSOURCE_TI1:
bogdanm	0:9b334a45a8ff	3994	{
bogdanm	0:9b334a45a8ff	3995	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	3996	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	3997	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	3998	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	3999	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
bogdanm	0:9b334a45a8ff	4000	}
bogdanm	0:9b334a45a8ff	4001	break;
bogdanm	0:9b334a45a8ff	4002	case TIM_CLOCKSOURCE_TI2:
bogdanm	0:9b334a45a8ff	4003	{
bogdanm	0:9b334a45a8ff	4004	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4005	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4006	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	4007	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	4008	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
bogdanm	0:9b334a45a8ff	4009	}
bogdanm	0:9b334a45a8ff	4010	break;
bogdanm	0:9b334a45a8ff	4011	case TIM_CLOCKSOURCE_TI1ED:
bogdanm	0:9b334a45a8ff	4012	{
bogdanm	0:9b334a45a8ff	4013	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4014	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4015	sClockSourceConfig->ClockPolarity,
bogdanm	0:9b334a45a8ff	4016	sClockSourceConfig->ClockFilter);
bogdanm	0:9b334a45a8ff	4017	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
bogdanm	0:9b334a45a8ff	4018	}
bogdanm	0:9b334a45a8ff	4019	break;
bogdanm	0:9b334a45a8ff	4020	case TIM_CLOCKSOURCE_ITR0:
bogdanm	0:9b334a45a8ff	4021	{
bogdanm	0:9b334a45a8ff	4022	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4023	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
bogdanm	0:9b334a45a8ff	4024	}
bogdanm	0:9b334a45a8ff	4025	break;
bogdanm	0:9b334a45a8ff	4026	case TIM_CLOCKSOURCE_ITR1:
bogdanm	0:9b334a45a8ff	4027	{
bogdanm	0:9b334a45a8ff	4028	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4029	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
bogdanm	0:9b334a45a8ff	4030	}
bogdanm	0:9b334a45a8ff	4031	break;
bogdanm	0:9b334a45a8ff	4032	case TIM_CLOCKSOURCE_ITR2:
bogdanm	0:9b334a45a8ff	4033	{
bogdanm	0:9b334a45a8ff	4034	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4035	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
bogdanm	0:9b334a45a8ff	4036	}
bogdanm	0:9b334a45a8ff	4037	break;
bogdanm	0:9b334a45a8ff	4038	case TIM_CLOCKSOURCE_ITR3:
bogdanm	0:9b334a45a8ff	4039	{
bogdanm	0:9b334a45a8ff	4040	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4041	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
bogdanm	0:9b334a45a8ff	4042	}
bogdanm	0:9b334a45a8ff	4043	break;
bogdanm	0:9b334a45a8ff	4044
bogdanm	0:9b334a45a8ff	4045	default:
bogdanm	0:9b334a45a8ff	4046	break;
bogdanm	0:9b334a45a8ff	4047	}
bogdanm	0:9b334a45a8ff	4048	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4049
bogdanm	0:9b334a45a8ff	4050	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4051
bogdanm	0:9b334a45a8ff	4052	return HAL_OK;
bogdanm	0:9b334a45a8ff	4053	}
bogdanm	0:9b334a45a8ff	4054
bogdanm	0:9b334a45a8ff	4055	/**
bogdanm	0:9b334a45a8ff	4056	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
bogdanm	0:9b334a45a8ff	4057	* or a XOR combination between CH1_input, CH2_input & CH3_input
bogdanm	0:9b334a45a8ff	4058	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4059	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4060	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
bogdanm	0:9b334a45a8ff	4061	* output of a XOR gate.
bogdanm	0:9b334a45a8ff	4062	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4063	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
bogdanm	0:9b334a45a8ff	4064	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
bogdanm	0:9b334a45a8ff	4065	* pins are connected to the TI1 input (XOR combination)
bogdanm	0:9b334a45a8ff	4066	* @retval HAL status
bogdanm	0:9b334a45a8ff	4067	*/
bogdanm	0:9b334a45a8ff	4068	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
bogdanm	0:9b334a45a8ff	4069	{
bogdanm	0:9b334a45a8ff	4070	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4071
bogdanm	0:9b334a45a8ff	4072	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4073	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4074	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
bogdanm	0:9b334a45a8ff	4075
bogdanm	0:9b334a45a8ff	4076	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4077	tmpcr2 = htim->Instance->CR2;
bogdanm	0:9b334a45a8ff	4078
bogdanm	0:9b334a45a8ff	4079	/* Reset the TI1 selection */
bogdanm	0:9b334a45a8ff	4080	tmpcr2 &= ~TIM_CR2_TI1S;
bogdanm	0:9b334a45a8ff	4081
bogdanm	0:9b334a45a8ff	4082	/* Set the TI1 selection */
bogdanm	0:9b334a45a8ff	4083	tmpcr2 \|= TI1_Selection;
bogdanm	0:9b334a45a8ff	4084
bogdanm	0:9b334a45a8ff	4085	/* Write to TIMxCR2 */
bogdanm	0:9b334a45a8ff	4086	htim->Instance->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4087
bogdanm	0:9b334a45a8ff	4088	return HAL_OK;
bogdanm	0:9b334a45a8ff	4089	}
bogdanm	0:9b334a45a8ff	4090
bogdanm	0:9b334a45a8ff	4091	/**
bogdanm	0:9b334a45a8ff	4092	* @brief Configures the TIM in Slave mode
bogdanm	0:9b334a45a8ff	4093	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4094	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4095	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	4096	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	4097	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	4098	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	4099	* @retval HAL status
bogdanm	0:9b334a45a8ff	4100	*/
bogdanm	0:9b334a45a8ff	4101	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
bogdanm	0:9b334a45a8ff	4102	{
bogdanm	0:9b334a45a8ff	4103	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	4104	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4105	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4106
bogdanm	0:9b334a45a8ff	4107	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4108	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4109	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm	0:9b334a45a8ff	4110	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm	0:9b334a45a8ff	4111
bogdanm	0:9b334a45a8ff	4112	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4113
bogdanm	0:9b334a45a8ff	4114	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	4115
bogdanm	0:9b334a45a8ff	4116	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	4117	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	4118
bogdanm	0:9b334a45a8ff	4119	/* Reset the Trigger Selection Bits */
bogdanm	0:9b334a45a8ff	4120	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	4121	/* Set the Input Trigger source */
bogdanm	0:9b334a45a8ff	4122	tmpsmcr \|= sSlaveConfig->InputTrigger;
bogdanm	0:9b334a45a8ff	4123
bogdanm	0:9b334a45a8ff	4124	/* Reset the slave mode Bits */
bogdanm	0:9b334a45a8ff	4125	tmpsmcr &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	4126	/* Set the slave mode */
bogdanm	0:9b334a45a8ff	4127	tmpsmcr \|= sSlaveConfig->SlaveMode;
bogdanm	0:9b334a45a8ff	4128
bogdanm	0:9b334a45a8ff	4129	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	4130	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	4131
bogdanm	0:9b334a45a8ff	4132	/* Configure the trigger prescaler, filter, and polarity */
bogdanm	0:9b334a45a8ff	4133	switch (sSlaveConfig->InputTrigger)
bogdanm	0:9b334a45a8ff	4134	{
bogdanm	0:9b334a45a8ff	4135	case TIM_TS_ETRF:
bogdanm	0:9b334a45a8ff	4136	{
bogdanm	0:9b334a45a8ff	4137	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4138	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4139	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
bogdanm	0:9b334a45a8ff	4140	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4141	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4142	/* Configure the ETR Trigger source */
bogdanm	0:9b334a45a8ff	4143	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	4144	sSlaveConfig->TriggerPrescaler,
bogdanm	0:9b334a45a8ff	4145	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4146	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4147	}
bogdanm	0:9b334a45a8ff	4148	break;
bogdanm	0:9b334a45a8ff	4149
bogdanm	0:9b334a45a8ff	4150	case TIM_TS_TI1F_ED:
bogdanm	0:9b334a45a8ff	4151	{
bogdanm	0:9b334a45a8ff	4152	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4153	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4154	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4155
bogdanm	0:9b334a45a8ff	4156	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4157	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	4158	htim->Instance->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4159	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	4160
bogdanm	0:9b334a45a8ff	4161	/* Set the filter */
bogdanm	0:9b334a45a8ff	4162	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	4163	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
bogdanm	0:9b334a45a8ff	4164
bogdanm	0:9b334a45a8ff	4165	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	4166	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	4167	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4168
bogdanm	0:9b334a45a8ff	4169	}
bogdanm	0:9b334a45a8ff	4170	break;
bogdanm	0:9b334a45a8ff	4171
bogdanm	0:9b334a45a8ff	4172	case TIM_TS_TI1FP1:
bogdanm	0:9b334a45a8ff	4173	{
bogdanm	0:9b334a45a8ff	4174	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4175	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4176	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4177	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4178
bogdanm	0:9b334a45a8ff	4179	/* Configure TI1 Filter and Polarity */
bogdanm	0:9b334a45a8ff	4180	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4181	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4182	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4183	}
bogdanm	0:9b334a45a8ff	4184	break;
bogdanm	0:9b334a45a8ff	4185
bogdanm	0:9b334a45a8ff	4186	case TIM_TS_TI2FP2:
bogdanm	0:9b334a45a8ff	4187	{
bogdanm	0:9b334a45a8ff	4188	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4189	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4190	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4191	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4192
bogdanm	0:9b334a45a8ff	4193	/* Configure TI2 Filter and Polarity */
bogdanm	0:9b334a45a8ff	4194	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	4195	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4196	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4197	}
bogdanm	0:9b334a45a8ff	4198	break;
bogdanm	0:9b334a45a8ff	4199
bogdanm	0:9b334a45a8ff	4200	case TIM_TS_ITR0:
bogdanm	0:9b334a45a8ff	4201	{
bogdanm	0:9b334a45a8ff	4202	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4203	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4204	}
bogdanm	0:9b334a45a8ff	4205	break;
bogdanm	0:9b334a45a8ff	4206
bogdanm	0:9b334a45a8ff	4207	case TIM_TS_ITR1:
bogdanm	0:9b334a45a8ff	4208	{
bogdanm	0:9b334a45a8ff	4209	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4210	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4211	}
bogdanm	0:9b334a45a8ff	4212	break;
bogdanm	0:9b334a45a8ff	4213
bogdanm	0:9b334a45a8ff	4214	case TIM_TS_ITR2:
bogdanm	0:9b334a45a8ff	4215	{
bogdanm	0:9b334a45a8ff	4216	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4217	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4218	}
bogdanm	0:9b334a45a8ff	4219	break;
bogdanm	0:9b334a45a8ff	4220
bogdanm	0:9b334a45a8ff	4221	case TIM_TS_ITR3:
bogdanm	0:9b334a45a8ff	4222	{
bogdanm	0:9b334a45a8ff	4223	/* Check the parameter */
bogdanm	0:9b334a45a8ff	4224	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4225	}
bogdanm	0:9b334a45a8ff	4226	break;
bogdanm	0:9b334a45a8ff	4227
bogdanm	0:9b334a45a8ff	4228	default:
bogdanm	0:9b334a45a8ff	4229	break;
bogdanm	0:9b334a45a8ff	4230	}
bogdanm	0:9b334a45a8ff	4231
bogdanm	0:9b334a45a8ff	4232	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4233
bogdanm	0:9b334a45a8ff	4234	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4235
bogdanm	0:9b334a45a8ff	4236	return HAL_OK;
bogdanm	0:9b334a45a8ff	4237	}
bogdanm	0:9b334a45a8ff	4238
bogdanm	0:9b334a45a8ff	4239	/**
bogdanm	0:9b334a45a8ff	4240	* @brief Configures the TIM in Slave mode in interrupt mode
bogdanm	0:9b334a45a8ff	4241	* @param htim: TIM handle.
bogdanm	0:9b334a45a8ff	4242	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	4243	* contains the selected trigger (internal trigger input, filtered
bogdanm	0:9b334a45a8ff	4244	* timer input or external trigger input) and the ) and the Slave
bogdanm	0:9b334a45a8ff	4245	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm	0:9b334a45a8ff	4246	* @retval HAL status
bogdanm	0:9b334a45a8ff	4247	*/
bogdanm	0:9b334a45a8ff	4248	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	4249	TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm	0:9b334a45a8ff	4250	{
bogdanm	0:9b334a45a8ff	4251	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4252	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4253	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm	0:9b334a45a8ff	4254	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm	0:9b334a45a8ff	4255
bogdanm	0:9b334a45a8ff	4256	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4257
bogdanm	0:9b334a45a8ff	4258	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	4259
bogdanm	0:9b334a45a8ff	4260	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
bogdanm	0:9b334a45a8ff	4261
bogdanm	0:9b334a45a8ff	4262	/* Enable Trigger Interrupt */
bogdanm	0:9b334a45a8ff	4263	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
bogdanm	0:9b334a45a8ff	4264
bogdanm	0:9b334a45a8ff	4265	/* Disable Trigger DMA request */
bogdanm	0:9b334a45a8ff	4266	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
bogdanm	0:9b334a45a8ff	4267
bogdanm	0:9b334a45a8ff	4268	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4269
bogdanm	0:9b334a45a8ff	4270	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4271
bogdanm	0:9b334a45a8ff	4272	return HAL_OK;
bogdanm	0:9b334a45a8ff	4273	}
bogdanm	0:9b334a45a8ff	4274
bogdanm	0:9b334a45a8ff	4275	/**
bogdanm	0:9b334a45a8ff	4276	* @brief Read the captured value from Capture Compare unit
bogdanm	0:9b334a45a8ff	4277	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4278	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4279	* @param Channel: TIM Channels to be enabled.
bogdanm	0:9b334a45a8ff	4280	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4281	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	4282	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	4283	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	4284	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	4285	* @retval Captured value
bogdanm	0:9b334a45a8ff	4286	*/
bogdanm	0:9b334a45a8ff	4287	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	4288	{
bogdanm	0:9b334a45a8ff	4289	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	4290
bogdanm	0:9b334a45a8ff	4291	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	4292
bogdanm	0:9b334a45a8ff	4293	switch (Channel)
bogdanm	0:9b334a45a8ff	4294	{
bogdanm	0:9b334a45a8ff	4295	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	4296	{
bogdanm	0:9b334a45a8ff	4297	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4298	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4299
bogdanm	0:9b334a45a8ff	4300	/* Return the capture 1 value */
bogdanm	0:9b334a45a8ff	4301	tmpreg = htim->Instance->CCR1;
bogdanm	0:9b334a45a8ff	4302
bogdanm	0:9b334a45a8ff	4303	break;
bogdanm	0:9b334a45a8ff	4304	}
bogdanm	0:9b334a45a8ff	4305	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	4306	{
bogdanm	0:9b334a45a8ff	4307	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4308	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4309
bogdanm	0:9b334a45a8ff	4310	/* Return the capture 2 value */
bogdanm	0:9b334a45a8ff	4311	tmpreg = htim->Instance->CCR2;
bogdanm	0:9b334a45a8ff	4312
bogdanm	0:9b334a45a8ff	4313	break;
bogdanm	0:9b334a45a8ff	4314	}
bogdanm	0:9b334a45a8ff	4315
bogdanm	0:9b334a45a8ff	4316	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	4317	{
bogdanm	0:9b334a45a8ff	4318	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4319	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4320
bogdanm	0:9b334a45a8ff	4321	/* Return the capture 3 value */
bogdanm	0:9b334a45a8ff	4322	tmpreg = htim->Instance->CCR3;
bogdanm	0:9b334a45a8ff	4323
bogdanm	0:9b334a45a8ff	4324	break;
bogdanm	0:9b334a45a8ff	4325	}
bogdanm	0:9b334a45a8ff	4326
bogdanm	0:9b334a45a8ff	4327	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	4328	{
bogdanm	0:9b334a45a8ff	4329	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4330	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4331
bogdanm	0:9b334a45a8ff	4332	/* Return the capture 4 value */
bogdanm	0:9b334a45a8ff	4333	tmpreg = htim->Instance->CCR4;
bogdanm	0:9b334a45a8ff	4334
bogdanm	0:9b334a45a8ff	4335	break;
bogdanm	0:9b334a45a8ff	4336	}
bogdanm	0:9b334a45a8ff	4337
bogdanm	0:9b334a45a8ff	4338	default:
bogdanm	0:9b334a45a8ff	4339	break;
bogdanm	0:9b334a45a8ff	4340	}
bogdanm	0:9b334a45a8ff	4341
bogdanm	0:9b334a45a8ff	4342	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	4343	return tmpreg;
bogdanm	0:9b334a45a8ff	4344	}
bogdanm	0:9b334a45a8ff	4345
bogdanm	0:9b334a45a8ff	4346	/**
bogdanm	0:9b334a45a8ff	4347	* @}
bogdanm	0:9b334a45a8ff	4348	*/
bogdanm	0:9b334a45a8ff	4349
bogdanm	0:9b334a45a8ff	4350	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
bogdanm	0:9b334a45a8ff	4351	* @brief TIM Callbacks functions
bogdanm	0:9b334a45a8ff	4352	*
bogdanm	0:9b334a45a8ff	4353	@verbatim
bogdanm	0:9b334a45a8ff	4354	==============================================================================
bogdanm	0:9b334a45a8ff	4355	##### TIM Callbacks functions #####
bogdanm	0:9b334a45a8ff	4356	==============================================================================
bogdanm	0:9b334a45a8ff	4357	[..]
bogdanm	0:9b334a45a8ff	4358	This section provides TIM callback functions:
bogdanm	0:9b334a45a8ff	4359	(+) Timer Period elapsed callback
bogdanm	0:9b334a45a8ff	4360	(+) Timer Output Compare callback
bogdanm	0:9b334a45a8ff	4361	(+) Timer Input capture callback
bogdanm	0:9b334a45a8ff	4362	(+) Timer Trigger callback
bogdanm	0:9b334a45a8ff	4363	(+) Timer Error callback
bogdanm	0:9b334a45a8ff	4364
bogdanm	0:9b334a45a8ff	4365	@endverbatim
bogdanm	0:9b334a45a8ff	4366	* @{
bogdanm	0:9b334a45a8ff	4367	*/
bogdanm	0:9b334a45a8ff	4368
bogdanm	0:9b334a45a8ff	4369	/**
bogdanm	0:9b334a45a8ff	4370	* @brief Period elapsed callback in non blocking mode
bogdanm	0:9b334a45a8ff	4371	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4372	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4373	* @retval None
bogdanm	0:9b334a45a8ff	4374	*/
bogdanm	0:9b334a45a8ff	4375	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4376	{
bogdanm	0:9b334a45a8ff	4377	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4378	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4379	*/
bogdanm	0:9b334a45a8ff	4380
bogdanm	0:9b334a45a8ff	4381	}
bogdanm	0:9b334a45a8ff	4382	/**
bogdanm	0:9b334a45a8ff	4383	* @brief Output Compare callback in non blocking mode
bogdanm	0:9b334a45a8ff	4384	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4385	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4386	* @retval None
bogdanm	0:9b334a45a8ff	4387	*/
bogdanm	0:9b334a45a8ff	4388	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4389	{
bogdanm	0:9b334a45a8ff	4390	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4391	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4392	*/
bogdanm	0:9b334a45a8ff	4393	}
bogdanm	0:9b334a45a8ff	4394	/**
bogdanm	0:9b334a45a8ff	4395	* @brief Input Capture callback in non blocking mode
bogdanm	0:9b334a45a8ff	4396	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4397	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4398	* @retval None
bogdanm	0:9b334a45a8ff	4399	*/
bogdanm	0:9b334a45a8ff	4400	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4401	{
bogdanm	0:9b334a45a8ff	4402	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4403	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4404	*/
bogdanm	0:9b334a45a8ff	4405	}
bogdanm	0:9b334a45a8ff	4406
bogdanm	0:9b334a45a8ff	4407	/**
bogdanm	0:9b334a45a8ff	4408	* @brief PWM Pulse finished callback in non blocking mode
bogdanm	0:9b334a45a8ff	4409	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4410	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4411	* @retval None
bogdanm	0:9b334a45a8ff	4412	*/
bogdanm	0:9b334a45a8ff	4413	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4414	{
bogdanm	0:9b334a45a8ff	4415	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4416	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4417	*/
bogdanm	0:9b334a45a8ff	4418	}
bogdanm	0:9b334a45a8ff	4419
bogdanm	0:9b334a45a8ff	4420	/**
bogdanm	0:9b334a45a8ff	4421	* @brief Hall Trigger detection callback in non blocking mode
bogdanm	0:9b334a45a8ff	4422	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4423	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4424	* @retval None
bogdanm	0:9b334a45a8ff	4425	*/
bogdanm	0:9b334a45a8ff	4426	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4427	{
bogdanm	0:9b334a45a8ff	4428	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4429	the HAL_TIM_TriggerCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4430	*/
bogdanm	0:9b334a45a8ff	4431	}
bogdanm	0:9b334a45a8ff	4432
bogdanm	0:9b334a45a8ff	4433	/**
bogdanm	0:9b334a45a8ff	4434	* @brief Timer error callback in non blocking mode
bogdanm	0:9b334a45a8ff	4435	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4436	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4437	* @retval None
bogdanm	0:9b334a45a8ff	4438	*/
bogdanm	0:9b334a45a8ff	4439	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4440	{
bogdanm	0:9b334a45a8ff	4441	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	4442	the HAL_TIM_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	4443	*/
bogdanm	0:9b334a45a8ff	4444	}
bogdanm	0:9b334a45a8ff	4445
bogdanm	0:9b334a45a8ff	4446	/**
bogdanm	0:9b334a45a8ff	4447	* @}
bogdanm	0:9b334a45a8ff	4448	*/
bogdanm	0:9b334a45a8ff	4449
bogdanm	0:9b334a45a8ff	4450	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
bogdanm	0:9b334a45a8ff	4451	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	4452	*
bogdanm	0:9b334a45a8ff	4453	@verbatim
bogdanm	0:9b334a45a8ff	4454	==============================================================================
bogdanm	0:9b334a45a8ff	4455	##### Peripheral State functions #####
bogdanm	0:9b334a45a8ff	4456	==============================================================================
bogdanm	0:9b334a45a8ff	4457	[..]
bogdanm	0:9b334a45a8ff	4458	This subsection permits to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	4459	and the data flow.
bogdanm	0:9b334a45a8ff	4460
bogdanm	0:9b334a45a8ff	4461	@endverbatim
bogdanm	0:9b334a45a8ff	4462	* @{
bogdanm	0:9b334a45a8ff	4463	*/
bogdanm	0:9b334a45a8ff	4464
bogdanm	0:9b334a45a8ff	4465	/**
bogdanm	0:9b334a45a8ff	4466	* @brief Return the TIM Base state
bogdanm	0:9b334a45a8ff	4467	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4468	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4469	* @retval HAL state
bogdanm	0:9b334a45a8ff	4470	*/
bogdanm	0:9b334a45a8ff	4471	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4472	{
bogdanm	0:9b334a45a8ff	4473	return htim->State;
bogdanm	0:9b334a45a8ff	4474	}
bogdanm	0:9b334a45a8ff	4475
bogdanm	0:9b334a45a8ff	4476	/**
bogdanm	0:9b334a45a8ff	4477	* @brief Return the TIM OC state
bogdanm	0:9b334a45a8ff	4478	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4479	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4480	* @retval HAL state
bogdanm	0:9b334a45a8ff	4481	*/
bogdanm	0:9b334a45a8ff	4482	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4483	{
bogdanm	0:9b334a45a8ff	4484	return htim->State;
bogdanm	0:9b334a45a8ff	4485	}
bogdanm	0:9b334a45a8ff	4486
bogdanm	0:9b334a45a8ff	4487	/**
bogdanm	0:9b334a45a8ff	4488	* @brief Return the TIM PWM state
bogdanm	0:9b334a45a8ff	4489	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4490	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4491	* @retval HAL state
bogdanm	0:9b334a45a8ff	4492	*/
bogdanm	0:9b334a45a8ff	4493	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4494	{
bogdanm	0:9b334a45a8ff	4495	return htim->State;
bogdanm	0:9b334a45a8ff	4496	}
bogdanm	0:9b334a45a8ff	4497
bogdanm	0:9b334a45a8ff	4498	/**
bogdanm	0:9b334a45a8ff	4499	* @brief Return the TIM Input Capture state
bogdanm	0:9b334a45a8ff	4500	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4501	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4502	* @retval HAL state
bogdanm	0:9b334a45a8ff	4503	*/
bogdanm	0:9b334a45a8ff	4504	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4505	{
bogdanm	0:9b334a45a8ff	4506	return htim->State;
bogdanm	0:9b334a45a8ff	4507	}
bogdanm	0:9b334a45a8ff	4508
bogdanm	0:9b334a45a8ff	4509	/**
bogdanm	0:9b334a45a8ff	4510	* @brief Return the TIM One Pulse Mode state
bogdanm	0:9b334a45a8ff	4511	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4512	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4513	* @retval HAL state
bogdanm	0:9b334a45a8ff	4514	*/
bogdanm	0:9b334a45a8ff	4515	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4516	{
bogdanm	0:9b334a45a8ff	4517	return htim->State;
bogdanm	0:9b334a45a8ff	4518	}
bogdanm	0:9b334a45a8ff	4519
bogdanm	0:9b334a45a8ff	4520	/**
bogdanm	0:9b334a45a8ff	4521	* @brief Return the TIM Encoder Mode state
bogdanm	0:9b334a45a8ff	4522	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4523	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4524	* @retval HAL state
bogdanm	0:9b334a45a8ff	4525	*/
bogdanm	0:9b334a45a8ff	4526	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	4527	{
bogdanm	0:9b334a45a8ff	4528	return htim->State;
bogdanm	0:9b334a45a8ff	4529	}
bogdanm	0:9b334a45a8ff	4530
bogdanm	0:9b334a45a8ff	4531	/**
bogdanm	0:9b334a45a8ff	4532	* @}
bogdanm	0:9b334a45a8ff	4533	*/
bogdanm	0:9b334a45a8ff	4534
bogdanm	0:9b334a45a8ff	4535	/**
bogdanm	0:9b334a45a8ff	4536	* @brief TIM DMA error callback
bogdanm	0:9b334a45a8ff	4537	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4538	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4539	* @retval None
bogdanm	0:9b334a45a8ff	4540	*/
bogdanm	0:9b334a45a8ff	4541	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4542	{
bogdanm	0:9b334a45a8ff	4543	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4544
bogdanm	0:9b334a45a8ff	4545	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4546
bogdanm	0:9b334a45a8ff	4547	HAL_TIM_ErrorCallback(htim);
bogdanm	0:9b334a45a8ff	4548	}
bogdanm	0:9b334a45a8ff	4549
bogdanm	0:9b334a45a8ff	4550	/**
bogdanm	0:9b334a45a8ff	4551	* @brief TIM DMA Delay Pulse complete callback.
bogdanm	0:9b334a45a8ff	4552	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4553	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4554	* @retval None
bogdanm	0:9b334a45a8ff	4555	*/
bogdanm	0:9b334a45a8ff	4556	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4557	{
bogdanm	0:9b334a45a8ff	4558	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4559
bogdanm	0:9b334a45a8ff	4560	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4561
bogdanm	0:9b334a45a8ff	4562	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4563	{
bogdanm	0:9b334a45a8ff	4564	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4565	}
bogdanm	0:9b334a45a8ff	4566	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4567	{
bogdanm	0:9b334a45a8ff	4568	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4569	}
bogdanm	0:9b334a45a8ff	4570	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4571	{
bogdanm	0:9b334a45a8ff	4572	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4573	}
bogdanm	0:9b334a45a8ff	4574	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4575	{
bogdanm	0:9b334a45a8ff	4576	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4577	}
bogdanm	0:9b334a45a8ff	4578
bogdanm	0:9b334a45a8ff	4579	HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm	0:9b334a45a8ff	4580
bogdanm	0:9b334a45a8ff	4581	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4582	}
bogdanm	0:9b334a45a8ff	4583	/**
bogdanm	0:9b334a45a8ff	4584	* @brief TIM DMA Capture complete callback.
bogdanm	0:9b334a45a8ff	4585	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4586	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4587	* @retval None
bogdanm	0:9b334a45a8ff	4588	*/
bogdanm	0:9b334a45a8ff	4589	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4590	{
bogdanm	0:9b334a45a8ff	4591	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4592
bogdanm	0:9b334a45a8ff	4593	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4594
bogdanm	0:9b334a45a8ff	4595	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm	0:9b334a45a8ff	4596	{
bogdanm	0:9b334a45a8ff	4597	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm	0:9b334a45a8ff	4598	}
bogdanm	0:9b334a45a8ff	4599	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm	0:9b334a45a8ff	4600	{
bogdanm	0:9b334a45a8ff	4601	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm	0:9b334a45a8ff	4602	}
bogdanm	0:9b334a45a8ff	4603	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm	0:9b334a45a8ff	4604	{
bogdanm	0:9b334a45a8ff	4605	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm	0:9b334a45a8ff	4606	}
bogdanm	0:9b334a45a8ff	4607	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm	0:9b334a45a8ff	4608	{
bogdanm	0:9b334a45a8ff	4609	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm	0:9b334a45a8ff	4610	}
bogdanm	0:9b334a45a8ff	4611
bogdanm	0:9b334a45a8ff	4612	HAL_TIM_IC_CaptureCallback(htim);
bogdanm	0:9b334a45a8ff	4613
bogdanm	0:9b334a45a8ff	4614	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm	0:9b334a45a8ff	4615
bogdanm	0:9b334a45a8ff	4616	}
bogdanm	0:9b334a45a8ff	4617
bogdanm	0:9b334a45a8ff	4618	/**
bogdanm	0:9b334a45a8ff	4619	* @brief TIM DMA Period Elapse complete callback.
bogdanm	0:9b334a45a8ff	4620	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4621	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4622	* @retval None
bogdanm	0:9b334a45a8ff	4623	*/
bogdanm	0:9b334a45a8ff	4624	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4625	{
bogdanm	0:9b334a45a8ff	4626	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4627
bogdanm	0:9b334a45a8ff	4628	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4629
bogdanm	0:9b334a45a8ff	4630	HAL_TIM_PeriodElapsedCallback(htim);
bogdanm	0:9b334a45a8ff	4631	}
bogdanm	0:9b334a45a8ff	4632
bogdanm	0:9b334a45a8ff	4633	/**
bogdanm	0:9b334a45a8ff	4634	* @brief TIM DMA Trigger callback.
bogdanm	0:9b334a45a8ff	4635	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4636	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	4637	* @retval None
bogdanm	0:9b334a45a8ff	4638	*/
bogdanm	0:9b334a45a8ff	4639	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	4640	{
bogdanm	0:9b334a45a8ff	4641	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	4642
bogdanm	0:9b334a45a8ff	4643	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	4644
bogdanm	0:9b334a45a8ff	4645	HAL_TIM_TriggerCallback(htim);
bogdanm	0:9b334a45a8ff	4646	}
bogdanm	0:9b334a45a8ff	4647
bogdanm	0:9b334a45a8ff	4648	/**
bogdanm	0:9b334a45a8ff	4649	* @brief Time Base configuration
bogdanm	0:9b334a45a8ff	4650	* @param TIMx: TIM peripheral
bogdanm	0:9b334a45a8ff	4651	* @param Structure: pointer on TIM Time Base required parameters
bogdanm	0:9b334a45a8ff	4652	* @retval None
bogdanm	0:9b334a45a8ff	4653	*/
bogdanm	0:9b334a45a8ff	4654	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
bogdanm	0:9b334a45a8ff	4655	{
bogdanm	0:9b334a45a8ff	4656	uint32_t tmpcr1 = 0;
bogdanm	0:9b334a45a8ff	4657	tmpcr1 = TIMx->CR1;
bogdanm	0:9b334a45a8ff	4658
bogdanm	0:9b334a45a8ff	4659	/* Set TIM Time Base Unit parameters ---------------------------------------*/
bogdanm	0:9b334a45a8ff	4660	if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4661	{
bogdanm	0:9b334a45a8ff	4662	/* Select the Counter Mode */
bogdanm	0:9b334a45a8ff	4663	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
bogdanm	0:9b334a45a8ff	4664	tmpcr1 \|= Structure->CounterMode;
bogdanm	0:9b334a45a8ff	4665	}
bogdanm	0:9b334a45a8ff	4666
bogdanm	0:9b334a45a8ff	4667	if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4668	{
bogdanm	0:9b334a45a8ff	4669	/* Set the clock division */
bogdanm	0:9b334a45a8ff	4670	tmpcr1 &= ~TIM_CR1_CKD;
bogdanm	0:9b334a45a8ff	4671	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
bogdanm	0:9b334a45a8ff	4672	}
bogdanm	0:9b334a45a8ff	4673
bogdanm	0:9b334a45a8ff	4674	TIMx->CR1 = tmpcr1;
bogdanm	0:9b334a45a8ff	4675
bogdanm	0:9b334a45a8ff	4676	/* Set the Auto-reload value */
bogdanm	0:9b334a45a8ff	4677	TIMx->ARR = (uint32_t)Structure->Period ;
bogdanm	0:9b334a45a8ff	4678
bogdanm	0:9b334a45a8ff	4679	/* Set the Prescaler value */
bogdanm	0:9b334a45a8ff	4680	TIMx->PSC = (uint32_t)Structure->Prescaler;
bogdanm	0:9b334a45a8ff	4681
bogdanm	0:9b334a45a8ff	4682	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4683	{
bogdanm	0:9b334a45a8ff	4684	/* Set the Repetition Counter value */
bogdanm	0:9b334a45a8ff	4685	TIMx->RCR = Structure->RepetitionCounter;
bogdanm	0:9b334a45a8ff	4686	}
bogdanm	0:9b334a45a8ff	4687
bogdanm	0:9b334a45a8ff	4688	/* Generate an update event to reload the Prescaler
bogdanm	0:9b334a45a8ff	4689	and the repetition counter(only for TIM1 and TIM8) value immediately */
bogdanm	0:9b334a45a8ff	4690	TIMx->EGR = TIM_EGR_UG;
bogdanm	0:9b334a45a8ff	4691	}
bogdanm	0:9b334a45a8ff	4692
bogdanm	0:9b334a45a8ff	4693	/**
bogdanm	0:9b334a45a8ff	4694	* @brief Time Output Compare 1 configuration
bogdanm	0:9b334a45a8ff	4695	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4696	* @param OC_Config: The output configuration structure
bogdanm	0:9b334a45a8ff	4697	* @retval None
bogdanm	0:9b334a45a8ff	4698	*/
bogdanm	0:9b334a45a8ff	4699	void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4700	{
bogdanm	0:9b334a45a8ff	4701	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4702	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4703	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4704
bogdanm	0:9b334a45a8ff	4705	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	4706	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	4707
bogdanm	0:9b334a45a8ff	4708	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4709	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4710	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4711	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4712
bogdanm	0:9b334a45a8ff	4713	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4714	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4715
bogdanm	0:9b334a45a8ff	4716	/* Reset the Output Compare Mode Bits */
bogdanm	0:9b334a45a8ff	4717	tmpccmrx &= ~TIM_CCMR1_OC1M;
bogdanm	0:9b334a45a8ff	4718	tmpccmrx &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	4719	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4720	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4721
bogdanm	0:9b334a45a8ff	4722	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4723	tmpccer &= ~TIM_CCER_CC1P;
bogdanm	0:9b334a45a8ff	4724	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4725	tmpccer \|= OC_Config->OCPolarity;
bogdanm	0:9b334a45a8ff	4726
bogdanm	0:9b334a45a8ff	4727
bogdanm	0:9b334a45a8ff	4728	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4729	{
bogdanm	0:9b334a45a8ff	4730	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4731	tmpccer &= ~TIM_CCER_CC1NP;
bogdanm	0:9b334a45a8ff	4732	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4733	tmpccer \|= OC_Config->OCNPolarity;
bogdanm	0:9b334a45a8ff	4734	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4735	tmpccer &= ~TIM_CCER_CC1NE;
bogdanm	0:9b334a45a8ff	4736
bogdanm	0:9b334a45a8ff	4737	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4738	tmpcr2 &= ~TIM_CR2_OIS1;
bogdanm	0:9b334a45a8ff	4739	tmpcr2 &= ~TIM_CR2_OIS1N;
bogdanm	0:9b334a45a8ff	4740	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4741	tmpcr2 \|= OC_Config->OCIdleState;
bogdanm	0:9b334a45a8ff	4742	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4743	tmpcr2 \|= OC_Config->OCNIdleState;
bogdanm	0:9b334a45a8ff	4744	}
bogdanm	0:9b334a45a8ff	4745	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4746	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4747
bogdanm	0:9b334a45a8ff	4748	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4749	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4750
bogdanm	0:9b334a45a8ff	4751	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4752	TIMx->CCR1 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4753
bogdanm	0:9b334a45a8ff	4754	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4755	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4756	}
bogdanm	0:9b334a45a8ff	4757
bogdanm	0:9b334a45a8ff	4758	/**
bogdanm	0:9b334a45a8ff	4759	* @brief Time Output Compare 2 configuration
bogdanm	0:9b334a45a8ff	4760	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4761	* @param OC_Config: The output configuration structure
bogdanm	0:9b334a45a8ff	4762	* @retval None
bogdanm	0:9b334a45a8ff	4763	*/
bogdanm	0:9b334a45a8ff	4764	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4765	{
bogdanm	0:9b334a45a8ff	4766	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4767	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4768	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4769
bogdanm	0:9b334a45a8ff	4770	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4771	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	4772
bogdanm	0:9b334a45a8ff	4773	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4774	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4775	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4776	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4777
bogdanm	0:9b334a45a8ff	4778	/* Get the TIMx CCMR1 register value */
bogdanm	0:9b334a45a8ff	4779	tmpccmrx = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	4780
bogdanm	0:9b334a45a8ff	4781	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4782	tmpccmrx &= ~TIM_CCMR1_OC2M;
bogdanm	0:9b334a45a8ff	4783	tmpccmrx &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	4784
bogdanm	0:9b334a45a8ff	4785	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4786	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4787
bogdanm	0:9b334a45a8ff	4788	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4789	tmpccer &= ~TIM_CCER_CC2P;
bogdanm	0:9b334a45a8ff	4790	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4791	tmpccer \|= (OC_Config->OCPolarity << 4);
bogdanm	0:9b334a45a8ff	4792
bogdanm	0:9b334a45a8ff	4793	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4794	{
bogdanm	0:9b334a45a8ff	4795	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4796	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4797	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4798
bogdanm	0:9b334a45a8ff	4799	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4800	tmpccer &= ~TIM_CCER_CC2NP;
bogdanm	0:9b334a45a8ff	4801	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4802	tmpccer \|= (OC_Config->OCNPolarity << 4);
bogdanm	0:9b334a45a8ff	4803	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4804	tmpccer &= ~TIM_CCER_CC2NE;
bogdanm	0:9b334a45a8ff	4805
bogdanm	0:9b334a45a8ff	4806	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4807	tmpcr2 &= ~TIM_CR2_OIS2;
bogdanm	0:9b334a45a8ff	4808	tmpcr2 &= ~TIM_CR2_OIS2N;
bogdanm	0:9b334a45a8ff	4809	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4810	tmpcr2 \|= (OC_Config->OCIdleState << 2);
bogdanm	0:9b334a45a8ff	4811	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4812	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
bogdanm	0:9b334a45a8ff	4813	}
bogdanm	0:9b334a45a8ff	4814	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4815	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4816
bogdanm	0:9b334a45a8ff	4817	/* Write to TIMx CCMR1 */
bogdanm	0:9b334a45a8ff	4818	TIMx->CCMR1 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4819
bogdanm	0:9b334a45a8ff	4820	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4821	TIMx->CCR2 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4822
bogdanm	0:9b334a45a8ff	4823	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4824	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4825	}
bogdanm	0:9b334a45a8ff	4826
bogdanm	0:9b334a45a8ff	4827	/**
bogdanm	0:9b334a45a8ff	4828	* @brief Time Output Compare 3 configuration
bogdanm	0:9b334a45a8ff	4829	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4830	* @param OC_Config: The output configuration structure
bogdanm	0:9b334a45a8ff	4831	* @retval None
bogdanm	0:9b334a45a8ff	4832	*/
bogdanm	0:9b334a45a8ff	4833	void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4834	{
bogdanm	0:9b334a45a8ff	4835	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4836	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4837	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4838
bogdanm	0:9b334a45a8ff	4839	/* Disable the Channel 3: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	4840	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	4841
bogdanm	0:9b334a45a8ff	4842	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4843	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4844	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4845	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4846
bogdanm	0:9b334a45a8ff	4847	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4848	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4849
bogdanm	0:9b334a45a8ff	4850	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4851	tmpccmrx &= ~TIM_CCMR2_OC3M;
bogdanm	0:9b334a45a8ff	4852	tmpccmrx &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	4853	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4854	tmpccmrx \|= OC_Config->OCMode;
bogdanm	0:9b334a45a8ff	4855
bogdanm	0:9b334a45a8ff	4856	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4857	tmpccer &= ~TIM_CCER_CC3P;
bogdanm	0:9b334a45a8ff	4858	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4859	tmpccer \|= (OC_Config->OCPolarity << 8);
bogdanm	0:9b334a45a8ff	4860
bogdanm	0:9b334a45a8ff	4861	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4862	{
bogdanm	0:9b334a45a8ff	4863	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm	0:9b334a45a8ff	4864	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm	0:9b334a45a8ff	4865	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4866
bogdanm	0:9b334a45a8ff	4867	/* Reset the Output N Polarity level */
bogdanm	0:9b334a45a8ff	4868	tmpccer &= ~TIM_CCER_CC3NP;
bogdanm	0:9b334a45a8ff	4869	/* Set the Output N Polarity */
bogdanm	0:9b334a45a8ff	4870	tmpccer \|= (OC_Config->OCNPolarity << 8);
bogdanm	0:9b334a45a8ff	4871	/* Reset the Output N State */
bogdanm	0:9b334a45a8ff	4872	tmpccer &= ~TIM_CCER_CC3NE;
bogdanm	0:9b334a45a8ff	4873
bogdanm	0:9b334a45a8ff	4874	/* Reset the Output Compare and Output Compare N IDLE State */
bogdanm	0:9b334a45a8ff	4875	tmpcr2 &= ~TIM_CR2_OIS3;
bogdanm	0:9b334a45a8ff	4876	tmpcr2 &= ~TIM_CR2_OIS3N;
bogdanm	0:9b334a45a8ff	4877	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4878	tmpcr2 \|= (OC_Config->OCIdleState << 4);
bogdanm	0:9b334a45a8ff	4879	/* Set the Output N Idle state */
bogdanm	0:9b334a45a8ff	4880	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
bogdanm	0:9b334a45a8ff	4881	}
bogdanm	0:9b334a45a8ff	4882	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4883	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4884
bogdanm	0:9b334a45a8ff	4885	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	4886	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4887
bogdanm	0:9b334a45a8ff	4888	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4889	TIMx->CCR3 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4890
bogdanm	0:9b334a45a8ff	4891	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4892	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4893	}
bogdanm	0:9b334a45a8ff	4894
bogdanm	0:9b334a45a8ff	4895	/**
bogdanm	0:9b334a45a8ff	4896	* @brief Time Output Compare 4 configuration
bogdanm	0:9b334a45a8ff	4897	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	4898	* @param OC_Config: The output configuration structure
bogdanm	0:9b334a45a8ff	4899	* @retval None
bogdanm	0:9b334a45a8ff	4900	*/
bogdanm	0:9b334a45a8ff	4901	void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
bogdanm	0:9b334a45a8ff	4902	{
bogdanm	0:9b334a45a8ff	4903	uint32_t tmpccmrx = 0;
bogdanm	0:9b334a45a8ff	4904	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4905	uint32_t tmpcr2 = 0;
bogdanm	0:9b334a45a8ff	4906
bogdanm	0:9b334a45a8ff	4907	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	4908	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	4909
bogdanm	0:9b334a45a8ff	4910	/* Get the TIMx CCER register value */
bogdanm	0:9b334a45a8ff	4911	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	4912	/* Get the TIMx CR2 register value */
bogdanm	0:9b334a45a8ff	4913	tmpcr2 = TIMx->CR2;
bogdanm	0:9b334a45a8ff	4914
bogdanm	0:9b334a45a8ff	4915	/* Get the TIMx CCMR2 register value */
bogdanm	0:9b334a45a8ff	4916	tmpccmrx = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	4917
bogdanm	0:9b334a45a8ff	4918	/* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm	0:9b334a45a8ff	4919	tmpccmrx &= ~TIM_CCMR2_OC4M;
bogdanm	0:9b334a45a8ff	4920	tmpccmrx &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	4921
bogdanm	0:9b334a45a8ff	4922	/* Select the Output Compare Mode */
bogdanm	0:9b334a45a8ff	4923	tmpccmrx \|= (OC_Config->OCMode << 8);
bogdanm	0:9b334a45a8ff	4924
bogdanm	0:9b334a45a8ff	4925	/* Reset the Output Polarity level */
bogdanm	0:9b334a45a8ff	4926	tmpccer &= ~TIM_CCER_CC4P;
bogdanm	0:9b334a45a8ff	4927	/* Set the Output Compare Polarity */
bogdanm	0:9b334a45a8ff	4928	tmpccer \|= (OC_Config->OCPolarity << 12);
bogdanm	0:9b334a45a8ff	4929
bogdanm	0:9b334a45a8ff	4930	/if((TIMx == TIM1) \|\| (TIMx == TIM8))/
bogdanm	0:9b334a45a8ff	4931	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	4932	{
bogdanm	0:9b334a45a8ff	4933	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm	0:9b334a45a8ff	4934	/* Reset the Output Compare IDLE State */
bogdanm	0:9b334a45a8ff	4935	tmpcr2 &= ~TIM_CR2_OIS4;
bogdanm	0:9b334a45a8ff	4936	/* Set the Output Idle state */
bogdanm	0:9b334a45a8ff	4937	tmpcr2 \|= (OC_Config->OCIdleState << 6);
bogdanm	0:9b334a45a8ff	4938	}
bogdanm	0:9b334a45a8ff	4939	/* Write to TIMx CR2 */
bogdanm	0:9b334a45a8ff	4940	TIMx->CR2 = tmpcr2;
bogdanm	0:9b334a45a8ff	4941
bogdanm	0:9b334a45a8ff	4942	/* Write to TIMx CCMR2 */
bogdanm	0:9b334a45a8ff	4943	TIMx->CCMR2 = tmpccmrx;
bogdanm	0:9b334a45a8ff	4944
bogdanm	0:9b334a45a8ff	4945	/* Set the Capture Compare Register value */
bogdanm	0:9b334a45a8ff	4946	TIMx->CCR4 = OC_Config->Pulse;
bogdanm	0:9b334a45a8ff	4947
bogdanm	0:9b334a45a8ff	4948	/* Write to TIMx CCER */
bogdanm	0:9b334a45a8ff	4949	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	4950	}
bogdanm	0:9b334a45a8ff	4951
bogdanm	0:9b334a45a8ff	4952	/**
bogdanm	0:9b334a45a8ff	4953	* @brief Time Output Compare 4 configuration
bogdanm	0:9b334a45a8ff	4954	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4955	* the configuration information for TIM module.
bogdanm	0:9b334a45a8ff	4956	* @param sSlaveConfig: The slave configuration structure
bogdanm	0:9b334a45a8ff	4957	* @retval None
bogdanm	0:9b334a45a8ff	4958	*/
bogdanm	0:9b334a45a8ff	4959	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	4960	TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm	0:9b334a45a8ff	4961	{
bogdanm	0:9b334a45a8ff	4962	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	4963	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	4964	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	4965
bogdanm	0:9b334a45a8ff	4966	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	4967	tmpsmcr = htim->Instance->SMCR;
bogdanm	0:9b334a45a8ff	4968
bogdanm	0:9b334a45a8ff	4969	/* Reset the Trigger Selection Bits */
bogdanm	0:9b334a45a8ff	4970	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	4971	/* Set the Input Trigger source */
bogdanm	0:9b334a45a8ff	4972	tmpsmcr \|= sSlaveConfig->InputTrigger;
bogdanm	0:9b334a45a8ff	4973
bogdanm	0:9b334a45a8ff	4974	/* Reset the slave mode Bits */
bogdanm	0:9b334a45a8ff	4975	tmpsmcr &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	4976	/* Set the slave mode */
bogdanm	0:9b334a45a8ff	4977	tmpsmcr \|= sSlaveConfig->SlaveMode;
bogdanm	0:9b334a45a8ff	4978
bogdanm	0:9b334a45a8ff	4979	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	4980	htim->Instance->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	4981
bogdanm	0:9b334a45a8ff	4982	/* Configure the trigger prescaler, filter, and polarity */
bogdanm	0:9b334a45a8ff	4983	switch (sSlaveConfig->InputTrigger)
bogdanm	0:9b334a45a8ff	4984	{
bogdanm	0:9b334a45a8ff	4985	case TIM_TS_ETRF:
bogdanm	0:9b334a45a8ff	4986	{
bogdanm	0:9b334a45a8ff	4987	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4988	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	4989	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
bogdanm	0:9b334a45a8ff	4990	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	4991	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	4992	/* Configure the ETR Trigger source */
bogdanm	0:9b334a45a8ff	4993	TIM_ETR_SetConfig(htim->Instance,
bogdanm	0:9b334a45a8ff	4994	sSlaveConfig->TriggerPrescaler,
bogdanm	0:9b334a45a8ff	4995	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	4996	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	4997	}
bogdanm	0:9b334a45a8ff	4998	break;
bogdanm	0:9b334a45a8ff	4999
bogdanm	0:9b334a45a8ff	5000	case TIM_TS_TI1F_ED:
bogdanm	0:9b334a45a8ff	5001	{
bogdanm	0:9b334a45a8ff	5002	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5003	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5004	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	5005	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	5006
bogdanm	0:9b334a45a8ff	5007	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	5008	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	5009	htim->Instance->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	5010	tmpccmr1 = htim->Instance->CCMR1;
bogdanm	0:9b334a45a8ff	5011
bogdanm	0:9b334a45a8ff	5012	/* Set the filter */
bogdanm	0:9b334a45a8ff	5013	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	5014	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
bogdanm	0:9b334a45a8ff	5015
bogdanm	0:9b334a45a8ff	5016	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5017	htim->Instance->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	5018	htim->Instance->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5019
bogdanm	0:9b334a45a8ff	5020	}
bogdanm	0:9b334a45a8ff	5021	break;
bogdanm	0:9b334a45a8ff	5022
bogdanm	0:9b334a45a8ff	5023	case TIM_TS_TI1FP1:
bogdanm	0:9b334a45a8ff	5024	{
bogdanm	0:9b334a45a8ff	5025	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5026	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5027	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	5028	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	5029
bogdanm	0:9b334a45a8ff	5030	/* Configure TI1 Filter and Polarity */
bogdanm	0:9b334a45a8ff	5031	TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	5032	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	5033	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	5034	}
bogdanm	0:9b334a45a8ff	5035	break;
bogdanm	0:9b334a45a8ff	5036
bogdanm	0:9b334a45a8ff	5037	case TIM_TS_TI2FP2:
bogdanm	0:9b334a45a8ff	5038	{
bogdanm	0:9b334a45a8ff	5039	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5040	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5041	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm	0:9b334a45a8ff	5042	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm	0:9b334a45a8ff	5043
bogdanm	0:9b334a45a8ff	5044	/* Configure TI2 Filter and Polarity */
bogdanm	0:9b334a45a8ff	5045	TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm	0:9b334a45a8ff	5046	sSlaveConfig->TriggerPolarity,
bogdanm	0:9b334a45a8ff	5047	sSlaveConfig->TriggerFilter);
bogdanm	0:9b334a45a8ff	5048	}
bogdanm	0:9b334a45a8ff	5049	break;
bogdanm	0:9b334a45a8ff	5050
bogdanm	0:9b334a45a8ff	5051	case TIM_TS_ITR0:
bogdanm	0:9b334a45a8ff	5052	{
bogdanm	0:9b334a45a8ff	5053	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5054	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5055	}
bogdanm	0:9b334a45a8ff	5056	break;
bogdanm	0:9b334a45a8ff	5057
bogdanm	0:9b334a45a8ff	5058	case TIM_TS_ITR1:
bogdanm	0:9b334a45a8ff	5059	{
bogdanm	0:9b334a45a8ff	5060	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5061	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5062	}
bogdanm	0:9b334a45a8ff	5063	break;
bogdanm	0:9b334a45a8ff	5064
bogdanm	0:9b334a45a8ff	5065	case TIM_TS_ITR2:
bogdanm	0:9b334a45a8ff	5066	{
bogdanm	0:9b334a45a8ff	5067	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5068	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5069	}
bogdanm	0:9b334a45a8ff	5070	break;
bogdanm	0:9b334a45a8ff	5071
bogdanm	0:9b334a45a8ff	5072	case TIM_TS_ITR3:
bogdanm	0:9b334a45a8ff	5073	{
bogdanm	0:9b334a45a8ff	5074	/* Check the parameter */
bogdanm	0:9b334a45a8ff	5075	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	5076	}
bogdanm	0:9b334a45a8ff	5077	break;
bogdanm	0:9b334a45a8ff	5078
bogdanm	0:9b334a45a8ff	5079	default:
bogdanm	0:9b334a45a8ff	5080	break;
bogdanm	0:9b334a45a8ff	5081	}
bogdanm	0:9b334a45a8ff	5082	}
bogdanm	0:9b334a45a8ff	5083
bogdanm	0:9b334a45a8ff	5084	/**
bogdanm	0:9b334a45a8ff	5085	* @brief Configure the TI1 as Input.
bogdanm	0:9b334a45a8ff	5086	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	5087	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5088	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5089	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5090	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5091	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5092	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5093	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5094	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
bogdanm	0:9b334a45a8ff	5095	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
bogdanm	0:9b334a45a8ff	5096	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5097	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5098	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5099	* @retval None
bogdanm	0:9b334a45a8ff	5100	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
bogdanm	0:9b334a45a8ff	5101	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
bogdanm	0:9b334a45a8ff	5102	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5103	*/
bogdanm	0:9b334a45a8ff	5104	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5105	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5106	{
bogdanm	0:9b334a45a8ff	5107	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5108	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5109
bogdanm	0:9b334a45a8ff	5110	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	5111	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	5112	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5113	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5114
bogdanm	0:9b334a45a8ff	5115	/* Select the Input */
bogdanm	0:9b334a45a8ff	5116	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
bogdanm	0:9b334a45a8ff	5117	{
bogdanm	0:9b334a45a8ff	5118	tmpccmr1 &= ~TIM_CCMR1_CC1S;
bogdanm	0:9b334a45a8ff	5119	tmpccmr1 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	5120	}
bogdanm	0:9b334a45a8ff	5121	else
bogdanm	0:9b334a45a8ff	5122	{
bogdanm	0:9b334a45a8ff	5123	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
bogdanm	0:9b334a45a8ff	5124	}
bogdanm	0:9b334a45a8ff	5125
bogdanm	0:9b334a45a8ff	5126	/* Set the filter */
bogdanm	0:9b334a45a8ff	5127	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	5128	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
bogdanm	0:9b334a45a8ff	5129
bogdanm	0:9b334a45a8ff	5130	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	5131	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	5132	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
bogdanm	0:9b334a45a8ff	5133
bogdanm	0:9b334a45a8ff	5134	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5135	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	5136	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5137	}
bogdanm	0:9b334a45a8ff	5138
bogdanm	0:9b334a45a8ff	5139	/**
bogdanm	0:9b334a45a8ff	5140	* @brief Configure the Polarity and Filter for TI1.
bogdanm	0:9b334a45a8ff	5141	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	5142	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5143	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5144	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5145	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5146	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5147	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5148	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5149	* @retval None
bogdanm	0:9b334a45a8ff	5150	*/
bogdanm	0:9b334a45a8ff	5151	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5152	{
bogdanm	0:9b334a45a8ff	5153	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5154	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5155
bogdanm	0:9b334a45a8ff	5156	/* Disable the Channel 1: Reset the CC1E Bit */
bogdanm	0:9b334a45a8ff	5157	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5158	TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm	0:9b334a45a8ff	5159	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5160
bogdanm	0:9b334a45a8ff	5161	/* Set the filter */
bogdanm	0:9b334a45a8ff	5162	tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm	0:9b334a45a8ff	5163	tmpccmr1 \|= (TIM_ICFilter << 4);
bogdanm	0:9b334a45a8ff	5164
bogdanm	0:9b334a45a8ff	5165	/* Select the Polarity and set the CC1E Bit */
bogdanm	0:9b334a45a8ff	5166	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
bogdanm	0:9b334a45a8ff	5167	tmpccer \|= TIM_ICPolarity;
bogdanm	0:9b334a45a8ff	5168
bogdanm	0:9b334a45a8ff	5169	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5170	TIMx->CCMR1 = tmpccmr1;
bogdanm	0:9b334a45a8ff	5171	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5172	}
bogdanm	0:9b334a45a8ff	5173
bogdanm	0:9b334a45a8ff	5174	/**
bogdanm	0:9b334a45a8ff	5175	* @brief Configure the TI2 as Input.
bogdanm	0:9b334a45a8ff	5176	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5177	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5178	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5179	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5180	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5181	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5182	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5183	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5184	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
bogdanm	0:9b334a45a8ff	5185	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
bogdanm	0:9b334a45a8ff	5186	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5187	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5188	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5189	* @retval None
bogdanm	0:9b334a45a8ff	5190	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
bogdanm	0:9b334a45a8ff	5191	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
bogdanm	0:9b334a45a8ff	5192	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5193	*/
bogdanm	0:9b334a45a8ff	5194	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5195	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5196	{
bogdanm	0:9b334a45a8ff	5197	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5198	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5199
bogdanm	0:9b334a45a8ff	5200	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	5201	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	5202	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5203	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5204
bogdanm	0:9b334a45a8ff	5205	/* Select the Input */
bogdanm	0:9b334a45a8ff	5206	tmpccmr1 &= ~TIM_CCMR1_CC2S;
bogdanm	0:9b334a45a8ff	5207	tmpccmr1 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	5208
bogdanm	0:9b334a45a8ff	5209	/* Set the filter */
bogdanm	0:9b334a45a8ff	5210	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	5211	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
bogdanm	0:9b334a45a8ff	5212
bogdanm	0:9b334a45a8ff	5213	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	5214	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	5215	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
bogdanm	0:9b334a45a8ff	5216
bogdanm	0:9b334a45a8ff	5217	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5218	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	5219	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5220	}
bogdanm	0:9b334a45a8ff	5221
bogdanm	0:9b334a45a8ff	5222	/**
bogdanm	0:9b334a45a8ff	5223	* @brief Configure the Polarity and Filter for TI2.
bogdanm	0:9b334a45a8ff	5224	* @param TIMx to select the TIM peripheral.
bogdanm	0:9b334a45a8ff	5225	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5226	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5227	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5228	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5229	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5230	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5231	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5232	* @retval None
bogdanm	0:9b334a45a8ff	5233	*/
bogdanm	0:9b334a45a8ff	5234	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5235	{
bogdanm	0:9b334a45a8ff	5236	uint32_t tmpccmr1 = 0;
bogdanm	0:9b334a45a8ff	5237	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5238
bogdanm	0:9b334a45a8ff	5239	/* Disable the Channel 2: Reset the CC2E Bit */
bogdanm	0:9b334a45a8ff	5240	TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm	0:9b334a45a8ff	5241	tmpccmr1 = TIMx->CCMR1;
bogdanm	0:9b334a45a8ff	5242	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5243
bogdanm	0:9b334a45a8ff	5244	/* Set the filter */
bogdanm	0:9b334a45a8ff	5245	tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm	0:9b334a45a8ff	5246	tmpccmr1 \|= (TIM_ICFilter << 12);
bogdanm	0:9b334a45a8ff	5247
bogdanm	0:9b334a45a8ff	5248	/* Select the Polarity and set the CC2E Bit */
bogdanm	0:9b334a45a8ff	5249	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
bogdanm	0:9b334a45a8ff	5250	tmpccer \|= (TIM_ICPolarity << 4);
bogdanm	0:9b334a45a8ff	5251
bogdanm	0:9b334a45a8ff	5252	/* Write to TIMx CCMR1 and CCER registers */
bogdanm	0:9b334a45a8ff	5253	TIMx->CCMR1 = tmpccmr1 ;
bogdanm	0:9b334a45a8ff	5254	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5255	}
bogdanm	0:9b334a45a8ff	5256
bogdanm	0:9b334a45a8ff	5257	/**
bogdanm	0:9b334a45a8ff	5258	* @brief Configure the TI3 as Input.
bogdanm	0:9b334a45a8ff	5259	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5260	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5261	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5262	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5263	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5264	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5265	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5266	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5267	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
bogdanm	0:9b334a45a8ff	5268	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
bogdanm	0:9b334a45a8ff	5269	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5270	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5271	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5272	* @retval None
bogdanm	0:9b334a45a8ff	5273	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
bogdanm	0:9b334a45a8ff	5274	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm	0:9b334a45a8ff	5275	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5276	*/
bogdanm	0:9b334a45a8ff	5277	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5278	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5279	{
bogdanm	0:9b334a45a8ff	5280	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	5281	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5282
bogdanm	0:9b334a45a8ff	5283	/* Disable the Channel 3: Reset the CC3E Bit */
bogdanm	0:9b334a45a8ff	5284	TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm	0:9b334a45a8ff	5285	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	5286	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5287
bogdanm	0:9b334a45a8ff	5288	/* Select the Input */
bogdanm	0:9b334a45a8ff	5289	tmpccmr2 &= ~TIM_CCMR2_CC3S;
bogdanm	0:9b334a45a8ff	5290	tmpccmr2 \|= TIM_ICSelection;
bogdanm	0:9b334a45a8ff	5291
bogdanm	0:9b334a45a8ff	5292	/* Set the filter */
bogdanm	0:9b334a45a8ff	5293	tmpccmr2 &= ~TIM_CCMR2_IC3F;
bogdanm	0:9b334a45a8ff	5294	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
bogdanm	0:9b334a45a8ff	5295
bogdanm	0:9b334a45a8ff	5296	/* Select the Polarity and set the CC3E Bit */
bogdanm	0:9b334a45a8ff	5297	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
bogdanm	0:9b334a45a8ff	5298	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
bogdanm	0:9b334a45a8ff	5299
bogdanm	0:9b334a45a8ff	5300	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	5301	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	5302	TIMx->CCER = tmpccer;
bogdanm	0:9b334a45a8ff	5303	}
bogdanm	0:9b334a45a8ff	5304
bogdanm	0:9b334a45a8ff	5305	/**
bogdanm	0:9b334a45a8ff	5306	* @brief Configure the TI4 as Input.
bogdanm	0:9b334a45a8ff	5307	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5308	* @param TIM_ICPolarity : The Input Polarity.
bogdanm	0:9b334a45a8ff	5309	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5310	* @arg TIM_ICPolarity_Rising
bogdanm	0:9b334a45a8ff	5311	* @arg TIM_ICPolarity_Falling
bogdanm	0:9b334a45a8ff	5312	* @arg TIM_ICPolarity_BothEdge
bogdanm	0:9b334a45a8ff	5313	* @param TIM_ICSelection: specifies the input to be used.
bogdanm	0:9b334a45a8ff	5314	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5315	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
bogdanm	0:9b334a45a8ff	5316	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
bogdanm	0:9b334a45a8ff	5317	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
bogdanm	0:9b334a45a8ff	5318	* @param TIM_ICFilter: Specifies the Input Capture Filter.
bogdanm	0:9b334a45a8ff	5319	* This parameter must be a value between 0x00 and 0x0F.
bogdanm	0:9b334a45a8ff	5320	* @retval None
bogdanm	0:9b334a45a8ff	5321	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
bogdanm	0:9b334a45a8ff	5322	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm	0:9b334a45a8ff	5323	* protected against un-initialized filter and polarity values.
bogdanm	0:9b334a45a8ff	5324	*/
bogdanm	0:9b334a45a8ff	5325	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm	0:9b334a45a8ff	5326	uint32_t TIM_ICFilter)
bogdanm	0:9b334a45a8ff	5327	{
bogdanm	0:9b334a45a8ff	5328	uint32_t tmpccmr2 = 0;
bogdanm	0:9b334a45a8ff	5329	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	5330
bogdanm	0:9b334a45a8ff	5331	/* Disable the Channel 4: Reset the CC4E Bit */
bogdanm	0:9b334a45a8ff	5332	TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm	0:9b334a45a8ff	5333	tmpccmr2 = TIMx->CCMR2;
bogdanm	0:9b334a45a8ff	5334	tmpccer = TIMx->CCER;
bogdanm	0:9b334a45a8ff	5335
bogdanm	0:9b334a45a8ff	5336	/* Select the Input */
bogdanm	0:9b334a45a8ff	5337	tmpccmr2 &= ~TIM_CCMR2_CC4S;
bogdanm	0:9b334a45a8ff	5338	tmpccmr2 \|= (TIM_ICSelection << 8);
bogdanm	0:9b334a45a8ff	5339
bogdanm	0:9b334a45a8ff	5340	/* Set the filter */
bogdanm	0:9b334a45a8ff	5341	tmpccmr2 &= ~TIM_CCMR2_IC4F;
bogdanm	0:9b334a45a8ff	5342	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
bogdanm	0:9b334a45a8ff	5343
bogdanm	0:9b334a45a8ff	5344	/* Select the Polarity and set the CC4E Bit */
bogdanm	0:9b334a45a8ff	5345	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
bogdanm	0:9b334a45a8ff	5346	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
bogdanm	0:9b334a45a8ff	5347
bogdanm	0:9b334a45a8ff	5348	/* Write to TIMx CCMR2 and CCER registers */
bogdanm	0:9b334a45a8ff	5349	TIMx->CCMR2 = tmpccmr2;
bogdanm	0:9b334a45a8ff	5350	TIMx->CCER = tmpccer ;
bogdanm	0:9b334a45a8ff	5351	}
bogdanm	0:9b334a45a8ff	5352
bogdanm	0:9b334a45a8ff	5353	/**
bogdanm	0:9b334a45a8ff	5354	* @brief Selects the Input Trigger source
bogdanm	0:9b334a45a8ff	5355	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5356	* @param TIM_ITRx: The Input Trigger source.
bogdanm	0:9b334a45a8ff	5357	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5358	* @arg TIM_TS_ITR0: Internal Trigger 0
bogdanm	0:9b334a45a8ff	5359	* @arg TIM_TS_ITR1: Internal Trigger 1
bogdanm	0:9b334a45a8ff	5360	* @arg TIM_TS_ITR2: Internal Trigger 2
bogdanm	0:9b334a45a8ff	5361	* @arg TIM_TS_ITR3: Internal Trigger 3
bogdanm	0:9b334a45a8ff	5362	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
bogdanm	0:9b334a45a8ff	5363	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
bogdanm	0:9b334a45a8ff	5364	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
bogdanm	0:9b334a45a8ff	5365	* @arg TIM_TS_ETRF: External Trigger input
bogdanm	0:9b334a45a8ff	5366	* @retval None
bogdanm	0:9b334a45a8ff	5367	*/
bogdanm	0:9b334a45a8ff	5368	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
bogdanm	0:9b334a45a8ff	5369	{
bogdanm	0:9b334a45a8ff	5370	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	5371
bogdanm	0:9b334a45a8ff	5372	/* Get the TIMx SMCR register value */
bogdanm	0:9b334a45a8ff	5373	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	5374	/* Reset the TS Bits */
bogdanm	0:9b334a45a8ff	5375	tmpsmcr &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	5376	/* Set the Input Trigger source and the slave mode*/
bogdanm	0:9b334a45a8ff	5377	tmpsmcr \|= TIM_ITRx \| TIM_SLAVEMODE_EXTERNAL1;
bogdanm	0:9b334a45a8ff	5378	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	5379	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	5380	}
bogdanm	0:9b334a45a8ff	5381
bogdanm	0:9b334a45a8ff	5382	/**
bogdanm	0:9b334a45a8ff	5383	* @brief Configures the TIMx External Trigger (ETR).
bogdanm	0:9b334a45a8ff	5384	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5385	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
bogdanm	0:9b334a45a8ff	5386	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5387	* @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
bogdanm	0:9b334a45a8ff	5388	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
bogdanm	0:9b334a45a8ff	5389	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
bogdanm	0:9b334a45a8ff	5390	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
bogdanm	0:9b334a45a8ff	5391	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
bogdanm	0:9b334a45a8ff	5392	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5393	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
bogdanm	0:9b334a45a8ff	5394	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
bogdanm	0:9b334a45a8ff	5395	* @param ExtTRGFilter: External Trigger Filter.
bogdanm	0:9b334a45a8ff	5396	* This parameter must be a value between 0x00 and 0x0F
bogdanm	0:9b334a45a8ff	5397	* @retval None
bogdanm	0:9b334a45a8ff	5398	*/
bogdanm	0:9b334a45a8ff	5399	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm	0:9b334a45a8ff	5400	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
bogdanm	0:9b334a45a8ff	5401	{
bogdanm	0:9b334a45a8ff	5402	uint32_t tmpsmcr = 0;
bogdanm	0:9b334a45a8ff	5403
bogdanm	0:9b334a45a8ff	5404	tmpsmcr = TIMx->SMCR;
bogdanm	0:9b334a45a8ff	5405
bogdanm	0:9b334a45a8ff	5406	/* Reset the ETR Bits */
bogdanm	0:9b334a45a8ff	5407	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
bogdanm	0:9b334a45a8ff	5408
bogdanm	0:9b334a45a8ff	5409	/* Set the Prescaler, the Filter value and the Polarity */
bogdanm	0:9b334a45a8ff	5410	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
bogdanm	0:9b334a45a8ff	5411
bogdanm	0:9b334a45a8ff	5412	/* Write to TIMx SMCR */
bogdanm	0:9b334a45a8ff	5413	TIMx->SMCR = tmpsmcr;
bogdanm	0:9b334a45a8ff	5414	}
bogdanm	0:9b334a45a8ff	5415
bogdanm	0:9b334a45a8ff	5416	/**
bogdanm	0:9b334a45a8ff	5417	* @brief Enables or disables the TIM Capture Compare Channel x.
bogdanm	0:9b334a45a8ff	5418	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	5419	* @param Channel: specifies the TIM Channel
bogdanm	0:9b334a45a8ff	5420	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	5421	* @arg TIM_Channel_1: TIM Channel 1
bogdanm	0:9b334a45a8ff	5422	* @arg TIM_Channel_2: TIM Channel 2
bogdanm	0:9b334a45a8ff	5423	* @arg TIM_Channel_3: TIM Channel 3
bogdanm	0:9b334a45a8ff	5424	* @arg TIM_Channel_4: TIM Channel 4
bogdanm	0:9b334a45a8ff	5425	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
bogdanm	0:9b334a45a8ff	5426	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
bogdanm	0:9b334a45a8ff	5427	* @retval None
bogdanm	0:9b334a45a8ff	5428	*/
bogdanm	0:9b334a45a8ff	5429	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
bogdanm	0:9b334a45a8ff	5430	{
bogdanm	0:9b334a45a8ff	5431	uint32_t tmp = 0;
bogdanm	0:9b334a45a8ff	5432
bogdanm	0:9b334a45a8ff	5433	/* Check the parameters */
bogdanm	0:9b334a45a8ff	5434	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
bogdanm	0:9b334a45a8ff	5435	assert_param(IS_TIM_CHANNELS(Channel));
bogdanm	0:9b334a45a8ff	5436
bogdanm	0:9b334a45a8ff	5437	tmp = TIM_CCER_CC1E << Channel;
bogdanm	0:9b334a45a8ff	5438
bogdanm	0:9b334a45a8ff	5439	/* Reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	5440	TIMx->CCER &= ~tmp;
bogdanm	0:9b334a45a8ff	5441
bogdanm	0:9b334a45a8ff	5442	/* Set or reset the CCxE Bit */
bogdanm	0:9b334a45a8ff	5443	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
bogdanm	0:9b334a45a8ff	5444	}
bogdanm	0:9b334a45a8ff	5445
bogdanm	0:9b334a45a8ff	5446
bogdanm	0:9b334a45a8ff	5447	/**
bogdanm	0:9b334a45a8ff	5448	* @}
bogdanm	0:9b334a45a8ff	5449	*/
bogdanm	0:9b334a45a8ff	5450
bogdanm	0:9b334a45a8ff	5451	#endif /* HAL_TIM_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	5452	/**
bogdanm	0:9b334a45a8ff	5453	* @}
bogdanm	0:9b334a45a8ff	5454	*/
bogdanm	0:9b334a45a8ff	5455
bogdanm	0:9b334a45a8ff	5456	/**
bogdanm	0:9b334a45a8ff	5457	* @}
bogdanm	0:9b334a45a8ff	5458	*/
bogdanm	0:9b334a45a8ff	5459	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
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Commits:	130
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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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