en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
83:a036322b8637 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_sdram.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 83:a036322b8637 5 * @version V1.0.4
mbed_official 83:a036322b8637 6 * @date 09-December-2015
bogdanm 0:9b334a45a8ff 7 * @brief SDRAM HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive SDRAM memories mounted
bogdanm 0:9b334a45a8ff 9 * as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control SDRAM memories. It uses the FMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with SDRAM devices.
bogdanm 0:9b334a45a8ff 19 The following sequence should be followed to configure the FMC to interface
bogdanm 0:9b334a45a8ff 20 with SDRAM memories:
bogdanm 0:9b334a45a8ff 21
bogdanm 0:9b334a45a8ff 22 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
bogdanm 0:9b334a45a8ff 23 SDRAM_HandleTypeDef hdsram
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
bogdanm 0:9b334a45a8ff 26 values of the structure member.
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
bogdanm 0:9b334a45a8ff 29 base register instance for NOR or SDRAM device
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
bogdanm 0:9b334a45a8ff 32 FMC_SDRAM_TimingTypeDef Timing;
bogdanm 0:9b334a45a8ff 33 and fill its fields with the allowed values of the structure member.
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
bogdanm 0:9b334a45a8ff 36 performs the following sequence:
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
bogdanm 0:9b334a45a8ff 39 (##) Control register configuration using the FMC SDRAM interface function
bogdanm 0:9b334a45a8ff 40 FMC_SDRAM_Init()
bogdanm 0:9b334a45a8ff 41 (##) Timing register configuration using the FMC SDRAM interface function
bogdanm 0:9b334a45a8ff 42 FMC_SDRAM_Timing_Init()
bogdanm 0:9b334a45a8ff 43 (##) Program the SDRAM external device by applying its initialization sequence
bogdanm 0:9b334a45a8ff 44 according to the device plugged in your hardware. This step is mandatory
bogdanm 0:9b334a45a8ff 45 for accessing the SDRAM device.
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 (#) At this stage you can perform read/write accesses from/to the memory connected
bogdanm 0:9b334a45a8ff 48 to the SDRAM Bank. You can perform either polling or DMA transfer using the
bogdanm 0:9b334a45a8ff 49 following APIs:
bogdanm 0:9b334a45a8ff 50 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
bogdanm 0:9b334a45a8ff 51 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
bogdanm 0:9b334a45a8ff 54 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
bogdanm 0:9b334a45a8ff 55 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
bogdanm 0:9b334a45a8ff 56 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
bogdanm 0:9b334a45a8ff 57 structure.
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 (#) You can continuously monitor the SDRAM device HAL state by calling the function
bogdanm 0:9b334a45a8ff 60 HAL_SDRAM_GetState()
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 @endverbatim
bogdanm 0:9b334a45a8ff 63 ******************************************************************************
bogdanm 0:9b334a45a8ff 64 * @attention
bogdanm 0:9b334a45a8ff 65 *
bogdanm 0:9b334a45a8ff 66 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 67 *
bogdanm 0:9b334a45a8ff 68 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 69 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 70 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 71 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 72 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 73 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 74 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 75 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 76 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 77 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 78 *
bogdanm 0:9b334a45a8ff 79 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 80 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 82 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 86 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 87 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 89 *
bogdanm 0:9b334a45a8ff 90 ******************************************************************************
bogdanm 0:9b334a45a8ff 91 */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 94 #include "stm32f7xx_hal.h"
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 97 * @{
bogdanm 0:9b334a45a8ff 98 */
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 /** @defgroup SDRAM SDRAM
bogdanm 0:9b334a45a8ff 101 * @brief SDRAM driver modules
bogdanm 0:9b334a45a8ff 102 * @{
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104 #ifdef HAL_SDRAM_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 107 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 108 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 109 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 110 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 111 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 112 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
bogdanm 0:9b334a45a8ff 113 * @{
bogdanm 0:9b334a45a8ff 114 */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 117 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 118 *
bogdanm 0:9b334a45a8ff 119 @verbatim
bogdanm 0:9b334a45a8ff 120 ==============================================================================
bogdanm 0:9b334a45a8ff 121 ##### SDRAM Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 122 ==============================================================================
bogdanm 0:9b334a45a8ff 123 [..]
bogdanm 0:9b334a45a8ff 124 This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 125 the SDRAM memory
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 @endverbatim
bogdanm 0:9b334a45a8ff 128 * @{
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /**
bogdanm 0:9b334a45a8ff 132 * @brief Performs the SDRAM device initialization sequence.
bogdanm 0:9b334a45a8ff 133 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 134 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 135 * @param Timing: Pointer to SDRAM control timing structure
bogdanm 0:9b334a45a8ff 136 * @retval HAL status
bogdanm 0:9b334a45a8ff 137 */
bogdanm 0:9b334a45a8ff 138 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
bogdanm 0:9b334a45a8ff 139 {
bogdanm 0:9b334a45a8ff 140 /* Check the SDRAM handle parameter */
bogdanm 0:9b334a45a8ff 141 if(hsdram == NULL)
bogdanm 0:9b334a45a8ff 142 {
bogdanm 0:9b334a45a8ff 143 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 144 }
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 if(hsdram->State == HAL_SDRAM_STATE_RESET)
bogdanm 0:9b334a45a8ff 147 {
bogdanm 0:9b334a45a8ff 148 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 149 hsdram->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 150 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 151 HAL_SDRAM_MspInit(hsdram);
bogdanm 0:9b334a45a8ff 152 }
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 /* Initialize the SDRAM controller state */
bogdanm 0:9b334a45a8ff 155 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 /* Initialize SDRAM control Interface */
bogdanm 0:9b334a45a8ff 158 FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 /* Initialize SDRAM timing Interface */
bogdanm 0:9b334a45a8ff 161 FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 /* Update the SDRAM controller state */
bogdanm 0:9b334a45a8ff 164 hsdram->State = HAL_SDRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 return HAL_OK;
bogdanm 0:9b334a45a8ff 167 }
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 /**
bogdanm 0:9b334a45a8ff 170 * @brief Perform the SDRAM device initialization sequence.
bogdanm 0:9b334a45a8ff 171 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 172 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 173 * @retval HAL status
bogdanm 0:9b334a45a8ff 174 */
bogdanm 0:9b334a45a8ff 175 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 176 {
bogdanm 0:9b334a45a8ff 177 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 178 HAL_SDRAM_MspDeInit(hsdram);
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /* Configure the SDRAM registers with their reset values */
bogdanm 0:9b334a45a8ff 181 FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /* Reset the SDRAM controller state */
bogdanm 0:9b334a45a8ff 184 hsdram->State = HAL_SDRAM_STATE_RESET;
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /* Release Lock */
bogdanm 0:9b334a45a8ff 187 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 return HAL_OK;
bogdanm 0:9b334a45a8ff 190 }
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 /**
bogdanm 0:9b334a45a8ff 193 * @brief SDRAM MSP Init.
bogdanm 0:9b334a45a8ff 194 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 195 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 196 * @retval None
bogdanm 0:9b334a45a8ff 197 */
bogdanm 0:9b334a45a8ff 198 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 199 {
mbed_official 83:a036322b8637 200 /* Prevent unused argument(s) compilation warning */
mbed_official 83:a036322b8637 201 UNUSED(hsdram);
mbed_official 83:a036322b8637 202
bogdanm 0:9b334a45a8ff 203 /* NOTE: This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 204 the HAL_SDRAM_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 205 */
bogdanm 0:9b334a45a8ff 206 }
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 /**
bogdanm 0:9b334a45a8ff 209 * @brief SDRAM MSP DeInit.
bogdanm 0:9b334a45a8ff 210 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 211 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 212 * @retval None
bogdanm 0:9b334a45a8ff 213 */
bogdanm 0:9b334a45a8ff 214 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 215 {
mbed_official 83:a036322b8637 216 /* Prevent unused argument(s) compilation warning */
mbed_official 83:a036322b8637 217 UNUSED(hsdram);
mbed_official 83:a036322b8637 218
bogdanm 0:9b334a45a8ff 219 /* NOTE: This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 220 the HAL_SDRAM_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 221 */
bogdanm 0:9b334a45a8ff 222 }
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /**
bogdanm 0:9b334a45a8ff 225 * @brief This function handles SDRAM refresh error interrupt request.
bogdanm 0:9b334a45a8ff 226 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 227 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 228 * @retval HAL status
bogdanm 0:9b334a45a8ff 229 */
bogdanm 0:9b334a45a8ff 230 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 231 {
bogdanm 0:9b334a45a8ff 232 /* Check SDRAM interrupt Rising edge flag */
bogdanm 0:9b334a45a8ff 233 if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
bogdanm 0:9b334a45a8ff 234 {
bogdanm 0:9b334a45a8ff 235 /* SDRAM refresh error interrupt callback */
bogdanm 0:9b334a45a8ff 236 HAL_SDRAM_RefreshErrorCallback(hsdram);
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 /* Clear SDRAM refresh error interrupt pending bit */
bogdanm 0:9b334a45a8ff 239 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
bogdanm 0:9b334a45a8ff 240 }
bogdanm 0:9b334a45a8ff 241 }
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 /**
bogdanm 0:9b334a45a8ff 244 * @brief SDRAM Refresh error callback.
bogdanm 0:9b334a45a8ff 245 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 246 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 247 * @retval None
bogdanm 0:9b334a45a8ff 248 */
bogdanm 0:9b334a45a8ff 249 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 250 {
mbed_official 83:a036322b8637 251 /* Prevent unused argument(s) compilation warning */
mbed_official 83:a036322b8637 252 UNUSED(hsdram);
mbed_official 83:a036322b8637 253
bogdanm 0:9b334a45a8ff 254 /* NOTE: This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 255 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 256 */
bogdanm 0:9b334a45a8ff 257 }
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /**
bogdanm 0:9b334a45a8ff 260 * @brief DMA transfer complete callback.
bogdanm 0:9b334a45a8ff 261 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 262 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 263 * @retval None
bogdanm 0:9b334a45a8ff 264 */
bogdanm 0:9b334a45a8ff 265 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 266 {
mbed_official 83:a036322b8637 267 /* Prevent unused argument(s) compilation warning */
mbed_official 83:a036322b8637 268 UNUSED(hdma);
mbed_official 83:a036322b8637 269
bogdanm 0:9b334a45a8ff 270 /* NOTE: This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 271 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 272 */
bogdanm 0:9b334a45a8ff 273 }
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 /**
bogdanm 0:9b334a45a8ff 276 * @brief DMA transfer complete error callback.
bogdanm 0:9b334a45a8ff 277 * @param hdma: DMA handle
bogdanm 0:9b334a45a8ff 278 * @retval None
bogdanm 0:9b334a45a8ff 279 */
bogdanm 0:9b334a45a8ff 280 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 281 {
mbed_official 83:a036322b8637 282 /* Prevent unused argument(s) compilation warning */
mbed_official 83:a036322b8637 283 UNUSED(hdma);
mbed_official 83:a036322b8637 284
bogdanm 0:9b334a45a8ff 285 /* NOTE: This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 286 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 287 */
bogdanm 0:9b334a45a8ff 288 }
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290 /**
bogdanm 0:9b334a45a8ff 291 * @}
bogdanm 0:9b334a45a8ff 292 */
bogdanm 0:9b334a45a8ff 293
bogdanm 0:9b334a45a8ff 294 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
bogdanm 0:9b334a45a8ff 295 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 296 *
bogdanm 0:9b334a45a8ff 297 @verbatim
bogdanm 0:9b334a45a8ff 298 ==============================================================================
bogdanm 0:9b334a45a8ff 299 ##### SDRAM Input and Output functions #####
bogdanm 0:9b334a45a8ff 300 ==============================================================================
bogdanm 0:9b334a45a8ff 301 [..]
bogdanm 0:9b334a45a8ff 302 This section provides functions allowing to use and control the SDRAM memory
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 @endverbatim
bogdanm 0:9b334a45a8ff 305 * @{
bogdanm 0:9b334a45a8ff 306 */
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /**
bogdanm 0:9b334a45a8ff 309 * @brief Reads 8-bit data buffer from the SDRAM memory.
bogdanm 0:9b334a45a8ff 310 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 311 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 312 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 313 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 314 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 315 * @retval HAL status
bogdanm 0:9b334a45a8ff 316 */
bogdanm 0:9b334a45a8ff 317 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 318 {
bogdanm 0:9b334a45a8ff 319 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 /* Process Locked */
bogdanm 0:9b334a45a8ff 322 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 323
bogdanm 0:9b334a45a8ff 324 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 325 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 326 {
bogdanm 0:9b334a45a8ff 327 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 328 }
bogdanm 0:9b334a45a8ff 329 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
bogdanm 0:9b334a45a8ff 330 {
bogdanm 0:9b334a45a8ff 331 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 332 }
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 /* Read data from source */
bogdanm 0:9b334a45a8ff 335 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 336 {
bogdanm 0:9b334a45a8ff 337 *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
bogdanm 0:9b334a45a8ff 338 pDstBuffer++;
bogdanm 0:9b334a45a8ff 339 pSdramAddress++;
bogdanm 0:9b334a45a8ff 340 }
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 343 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 return HAL_OK;
bogdanm 0:9b334a45a8ff 346 }
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 /**
bogdanm 0:9b334a45a8ff 350 * @brief Writes 8-bit data buffer to SDRAM memory.
bogdanm 0:9b334a45a8ff 351 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 352 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 353 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 354 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 355 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 356 * @retval HAL status
bogdanm 0:9b334a45a8ff 357 */
bogdanm 0:9b334a45a8ff 358 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 359 {
bogdanm 0:9b334a45a8ff 360 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
bogdanm 0:9b334a45a8ff 361 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /* Process Locked */
bogdanm 0:9b334a45a8ff 364 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 367 tmp = hsdram->State;
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 if(tmp == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 370 {
bogdanm 0:9b334a45a8ff 371 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 372 }
bogdanm 0:9b334a45a8ff 373 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
bogdanm 0:9b334a45a8ff 374 {
bogdanm 0:9b334a45a8ff 375 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 376 }
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 /* Write data to memory */
bogdanm 0:9b334a45a8ff 379 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 380 {
bogdanm 0:9b334a45a8ff 381 *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 382 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 383 pSdramAddress++;
bogdanm 0:9b334a45a8ff 384 }
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 387 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 return HAL_OK;
bogdanm 0:9b334a45a8ff 390 }
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 /**
bogdanm 0:9b334a45a8ff 394 * @brief Reads 16-bit data buffer from the SDRAM memory.
bogdanm 0:9b334a45a8ff 395 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 396 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 397 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 398 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 399 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 400 * @retval HAL status
bogdanm 0:9b334a45a8ff 401 */
bogdanm 0:9b334a45a8ff 402 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 403 {
bogdanm 0:9b334a45a8ff 404 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 /* Process Locked */
bogdanm 0:9b334a45a8ff 407 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 410 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 411 {
bogdanm 0:9b334a45a8ff 412 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 413 }
bogdanm 0:9b334a45a8ff 414 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
bogdanm 0:9b334a45a8ff 415 {
bogdanm 0:9b334a45a8ff 416 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 417 }
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /* Read data from source */
bogdanm 0:9b334a45a8ff 420 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 421 {
bogdanm 0:9b334a45a8ff 422 *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
bogdanm 0:9b334a45a8ff 423 pDstBuffer++;
bogdanm 0:9b334a45a8ff 424 pSdramAddress++;
bogdanm 0:9b334a45a8ff 425 }
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 428 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 return HAL_OK;
bogdanm 0:9b334a45a8ff 431 }
bogdanm 0:9b334a45a8ff 432
bogdanm 0:9b334a45a8ff 433 /**
bogdanm 0:9b334a45a8ff 434 * @brief Writes 16-bit data buffer to SDRAM memory.
bogdanm 0:9b334a45a8ff 435 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 436 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 437 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 438 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 439 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 440 * @retval HAL status
bogdanm 0:9b334a45a8ff 441 */
bogdanm 0:9b334a45a8ff 442 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 443 {
bogdanm 0:9b334a45a8ff 444 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
bogdanm 0:9b334a45a8ff 445 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 /* Process Locked */
bogdanm 0:9b334a45a8ff 448 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 451 tmp = hsdram->State;
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 if(tmp == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 454 {
bogdanm 0:9b334a45a8ff 455 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 456 }
bogdanm 0:9b334a45a8ff 457 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
bogdanm 0:9b334a45a8ff 458 {
bogdanm 0:9b334a45a8ff 459 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 460 }
bogdanm 0:9b334a45a8ff 461
bogdanm 0:9b334a45a8ff 462 /* Write data to memory */
bogdanm 0:9b334a45a8ff 463 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 464 {
bogdanm 0:9b334a45a8ff 465 *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 466 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 467 pSdramAddress++;
bogdanm 0:9b334a45a8ff 468 }
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 471 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 return HAL_OK;
bogdanm 0:9b334a45a8ff 474 }
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /**
bogdanm 0:9b334a45a8ff 477 * @brief Reads 32-bit data buffer from the SDRAM memory.
bogdanm 0:9b334a45a8ff 478 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 479 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 480 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 481 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 482 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 483 * @retval HAL status
bogdanm 0:9b334a45a8ff 484 */
bogdanm 0:9b334a45a8ff 485 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 486 {
bogdanm 0:9b334a45a8ff 487 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 /* Process Locked */
bogdanm 0:9b334a45a8ff 490 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 491
bogdanm 0:9b334a45a8ff 492 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 493 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 494 {
bogdanm 0:9b334a45a8ff 495 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 496 }
bogdanm 0:9b334a45a8ff 497 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
bogdanm 0:9b334a45a8ff 498 {
bogdanm 0:9b334a45a8ff 499 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 500 }
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /* Read data from source */
bogdanm 0:9b334a45a8ff 503 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 504 {
bogdanm 0:9b334a45a8ff 505 *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
bogdanm 0:9b334a45a8ff 506 pDstBuffer++;
bogdanm 0:9b334a45a8ff 507 pSdramAddress++;
bogdanm 0:9b334a45a8ff 508 }
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 511 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 return HAL_OK;
bogdanm 0:9b334a45a8ff 514 }
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 /**
bogdanm 0:9b334a45a8ff 517 * @brief Writes 32-bit data buffer to SDRAM memory.
bogdanm 0:9b334a45a8ff 518 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 519 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 520 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 521 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 522 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 523 * @retval HAL status
bogdanm 0:9b334a45a8ff 524 */
bogdanm 0:9b334a45a8ff 525 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 526 {
bogdanm 0:9b334a45a8ff 527 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
bogdanm 0:9b334a45a8ff 528 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /* Process Locked */
bogdanm 0:9b334a45a8ff 531 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 534 tmp = hsdram->State;
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 if(tmp == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 537 {
bogdanm 0:9b334a45a8ff 538 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 539 }
bogdanm 0:9b334a45a8ff 540 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
bogdanm 0:9b334a45a8ff 541 {
bogdanm 0:9b334a45a8ff 542 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 543 }
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 /* Write data to memory */
bogdanm 0:9b334a45a8ff 546 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 547 {
bogdanm 0:9b334a45a8ff 548 *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 549 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 550 pSdramAddress++;
bogdanm 0:9b334a45a8ff 551 }
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 554 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 return HAL_OK;
bogdanm 0:9b334a45a8ff 557 }
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /**
bogdanm 0:9b334a45a8ff 560 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
bogdanm 0:9b334a45a8ff 561 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 562 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 563 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 564 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 565 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 566 * @retval HAL status
bogdanm 0:9b334a45a8ff 567 */
bogdanm 0:9b334a45a8ff 568 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 569 {
bogdanm 0:9b334a45a8ff 570 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 /* Process Locked */
bogdanm 0:9b334a45a8ff 573 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 576 tmp = hsdram->State;
bogdanm 0:9b334a45a8ff 577
bogdanm 0:9b334a45a8ff 578 if(tmp == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 579 {
bogdanm 0:9b334a45a8ff 580 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 581 }
bogdanm 0:9b334a45a8ff 582 else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
bogdanm 0:9b334a45a8ff 583 {
bogdanm 0:9b334a45a8ff 584 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 585 }
bogdanm 0:9b334a45a8ff 586
bogdanm 0:9b334a45a8ff 587 /* Configure DMA user callbacks */
bogdanm 0:9b334a45a8ff 588 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
bogdanm 0:9b334a45a8ff 589 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 592 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 595 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 return HAL_OK;
bogdanm 0:9b334a45a8ff 598 }
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 /**
bogdanm 0:9b334a45a8ff 601 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
bogdanm 0:9b334a45a8ff 602 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 603 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 604 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 605 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 606 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 607 * @retval HAL status
bogdanm 0:9b334a45a8ff 608 */
bogdanm 0:9b334a45a8ff 609 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 610 {
bogdanm 0:9b334a45a8ff 611 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 /* Process Locked */
bogdanm 0:9b334a45a8ff 614 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 617 tmp = hsdram->State;
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619 if(tmp == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 620 {
bogdanm 0:9b334a45a8ff 621 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 622 }
bogdanm 0:9b334a45a8ff 623 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
bogdanm 0:9b334a45a8ff 624 {
bogdanm 0:9b334a45a8ff 625 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 626 }
bogdanm 0:9b334a45a8ff 627
bogdanm 0:9b334a45a8ff 628 /* Configure DMA user callbacks */
bogdanm 0:9b334a45a8ff 629 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
bogdanm 0:9b334a45a8ff 630 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 633 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
bogdanm 0:9b334a45a8ff 634
bogdanm 0:9b334a45a8ff 635 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 636 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 return HAL_OK;
bogdanm 0:9b334a45a8ff 639 }
bogdanm 0:9b334a45a8ff 640
bogdanm 0:9b334a45a8ff 641 /**
bogdanm 0:9b334a45a8ff 642 * @}
bogdanm 0:9b334a45a8ff 643 */
bogdanm 0:9b334a45a8ff 644
bogdanm 0:9b334a45a8ff 645 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
bogdanm 0:9b334a45a8ff 646 * @brief management functions
bogdanm 0:9b334a45a8ff 647 *
bogdanm 0:9b334a45a8ff 648 @verbatim
bogdanm 0:9b334a45a8ff 649 ==============================================================================
bogdanm 0:9b334a45a8ff 650 ##### SDRAM Control functions #####
bogdanm 0:9b334a45a8ff 651 ==============================================================================
bogdanm 0:9b334a45a8ff 652 [..]
bogdanm 0:9b334a45a8ff 653 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 654 the SDRAM interface.
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656 @endverbatim
bogdanm 0:9b334a45a8ff 657 * @{
bogdanm 0:9b334a45a8ff 658 */
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660 /**
bogdanm 0:9b334a45a8ff 661 * @brief Enables dynamically SDRAM write protection.
bogdanm 0:9b334a45a8ff 662 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 663 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 664 * @retval HAL status
bogdanm 0:9b334a45a8ff 665 */
bogdanm 0:9b334a45a8ff 666 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 667 {
bogdanm 0:9b334a45a8ff 668 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 669 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 670 {
bogdanm 0:9b334a45a8ff 671 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 672 }
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 675 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 /* Enable write protection */
bogdanm 0:9b334a45a8ff 678 FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
bogdanm 0:9b334a45a8ff 679
bogdanm 0:9b334a45a8ff 680 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 681 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683 return HAL_OK;
bogdanm 0:9b334a45a8ff 684 }
bogdanm 0:9b334a45a8ff 685
bogdanm 0:9b334a45a8ff 686 /**
bogdanm 0:9b334a45a8ff 687 * @brief Disables dynamically SDRAM write protection.
bogdanm 0:9b334a45a8ff 688 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 689 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 690 * @retval HAL status
bogdanm 0:9b334a45a8ff 691 */
bogdanm 0:9b334a45a8ff 692 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 693 {
bogdanm 0:9b334a45a8ff 694 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 695 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 696 {
bogdanm 0:9b334a45a8ff 697 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 698 }
bogdanm 0:9b334a45a8ff 699
bogdanm 0:9b334a45a8ff 700 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 701 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 702
bogdanm 0:9b334a45a8ff 703 /* Disable write protection */
bogdanm 0:9b334a45a8ff 704 FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 707 hsdram->State = HAL_SDRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 708
bogdanm 0:9b334a45a8ff 709 return HAL_OK;
bogdanm 0:9b334a45a8ff 710 }
bogdanm 0:9b334a45a8ff 711
bogdanm 0:9b334a45a8ff 712 /**
bogdanm 0:9b334a45a8ff 713 * @brief Sends Command to the SDRAM bank.
bogdanm 0:9b334a45a8ff 714 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 715 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 716 * @param Command: SDRAM command structure
bogdanm 0:9b334a45a8ff 717 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 718 * @retval HAL status
bogdanm 0:9b334a45a8ff 719 */
bogdanm 0:9b334a45a8ff 720 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 721 {
bogdanm 0:9b334a45a8ff 722 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 723 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 724 {
bogdanm 0:9b334a45a8ff 725 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 726 }
bogdanm 0:9b334a45a8ff 727
bogdanm 0:9b334a45a8ff 728 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 729 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 730
bogdanm 0:9b334a45a8ff 731 /* Send SDRAM command */
bogdanm 0:9b334a45a8ff 732 FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
bogdanm 0:9b334a45a8ff 733
bogdanm 0:9b334a45a8ff 734 /* Update the SDRAM controller state state */
bogdanm 0:9b334a45a8ff 735 if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
bogdanm 0:9b334a45a8ff 736 {
bogdanm 0:9b334a45a8ff 737 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
bogdanm 0:9b334a45a8ff 738 }
bogdanm 0:9b334a45a8ff 739 else
bogdanm 0:9b334a45a8ff 740 {
bogdanm 0:9b334a45a8ff 741 hsdram->State = HAL_SDRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 742 }
bogdanm 0:9b334a45a8ff 743
bogdanm 0:9b334a45a8ff 744 return HAL_OK;
bogdanm 0:9b334a45a8ff 745 }
bogdanm 0:9b334a45a8ff 746
bogdanm 0:9b334a45a8ff 747 /**
bogdanm 0:9b334a45a8ff 748 * @brief Programs the SDRAM Memory Refresh rate.
bogdanm 0:9b334a45a8ff 749 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 750 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 751 * @param RefreshRate: The SDRAM refresh rate value
bogdanm 0:9b334a45a8ff 752 * @retval HAL status
bogdanm 0:9b334a45a8ff 753 */
bogdanm 0:9b334a45a8ff 754 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
bogdanm 0:9b334a45a8ff 755 {
bogdanm 0:9b334a45a8ff 756 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 757 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 758 {
bogdanm 0:9b334a45a8ff 759 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 760 }
bogdanm 0:9b334a45a8ff 761
bogdanm 0:9b334a45a8ff 762 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 763 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 764
bogdanm 0:9b334a45a8ff 765 /* Program the refresh rate */
bogdanm 0:9b334a45a8ff 766 FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
bogdanm 0:9b334a45a8ff 767
bogdanm 0:9b334a45a8ff 768 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 769 hsdram->State = HAL_SDRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 return HAL_OK;
bogdanm 0:9b334a45a8ff 772 }
bogdanm 0:9b334a45a8ff 773
bogdanm 0:9b334a45a8ff 774 /**
bogdanm 0:9b334a45a8ff 775 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
bogdanm 0:9b334a45a8ff 776 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 777 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 778 * @param AutoRefreshNumber: The SDRAM auto Refresh number
bogdanm 0:9b334a45a8ff 779 * @retval HAL status
bogdanm 0:9b334a45a8ff 780 */
bogdanm 0:9b334a45a8ff 781 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
bogdanm 0:9b334a45a8ff 782 {
bogdanm 0:9b334a45a8ff 783 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 784 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 785 {
bogdanm 0:9b334a45a8ff 786 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 787 }
bogdanm 0:9b334a45a8ff 788
bogdanm 0:9b334a45a8ff 789 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 790 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 791
bogdanm 0:9b334a45a8ff 792 /* Set the Auto-Refresh number */
bogdanm 0:9b334a45a8ff 793 FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
bogdanm 0:9b334a45a8ff 794
bogdanm 0:9b334a45a8ff 795 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 796 hsdram->State = HAL_SDRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 797
bogdanm 0:9b334a45a8ff 798 return HAL_OK;
bogdanm 0:9b334a45a8ff 799 }
bogdanm 0:9b334a45a8ff 800
bogdanm 0:9b334a45a8ff 801 /**
bogdanm 0:9b334a45a8ff 802 * @brief Returns the SDRAM memory current mode.
bogdanm 0:9b334a45a8ff 803 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 804 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 805 * @retval The SDRAM memory mode.
bogdanm 0:9b334a45a8ff 806 */
bogdanm 0:9b334a45a8ff 807 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 808 {
bogdanm 0:9b334a45a8ff 809 /* Return the SDRAM memory current mode */
bogdanm 0:9b334a45a8ff 810 return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
bogdanm 0:9b334a45a8ff 811 }
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813 /**
bogdanm 0:9b334a45a8ff 814 * @}
bogdanm 0:9b334a45a8ff 815 */
bogdanm 0:9b334a45a8ff 816
bogdanm 0:9b334a45a8ff 817 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
bogdanm 0:9b334a45a8ff 818 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 819 *
bogdanm 0:9b334a45a8ff 820 @verbatim
bogdanm 0:9b334a45a8ff 821 ==============================================================================
bogdanm 0:9b334a45a8ff 822 ##### SDRAM State functions #####
bogdanm 0:9b334a45a8ff 823 ==============================================================================
bogdanm 0:9b334a45a8ff 824 [..]
bogdanm 0:9b334a45a8ff 825 This subsection permits to get in run-time the status of the SDRAM controller
bogdanm 0:9b334a45a8ff 826 and the data flow.
bogdanm 0:9b334a45a8ff 827
bogdanm 0:9b334a45a8ff 828 @endverbatim
bogdanm 0:9b334a45a8ff 829 * @{
bogdanm 0:9b334a45a8ff 830 */
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 /**
bogdanm 0:9b334a45a8ff 833 * @brief Returns the SDRAM state.
bogdanm 0:9b334a45a8ff 834 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 835 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 836 * @retval HAL state
bogdanm 0:9b334a45a8ff 837 */
bogdanm 0:9b334a45a8ff 838 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 839 {
bogdanm 0:9b334a45a8ff 840 return hsdram->State;
bogdanm 0:9b334a45a8ff 841 }
bogdanm 0:9b334a45a8ff 842
bogdanm 0:9b334a45a8ff 843 /**
bogdanm 0:9b334a45a8ff 844 * @}
bogdanm 0:9b334a45a8ff 845 */
bogdanm 0:9b334a45a8ff 846
bogdanm 0:9b334a45a8ff 847 /**
bogdanm 0:9b334a45a8ff 848 * @}
bogdanm 0:9b334a45a8ff 849 */
bogdanm 0:9b334a45a8ff 850 #endif /* HAL_SDRAM_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 851 /**
bogdanm 0:9b334a45a8ff 852 * @}
bogdanm 0:9b334a45a8ff 853 */
bogdanm 0:9b334a45a8ff 854
bogdanm 0:9b334a45a8ff 855 /**
bogdanm 0:9b334a45a8ff 856 * @}
bogdanm 0:9b334a45a8ff 857 */
bogdanm 0:9b334a45a8ff 858
bogdanm 0:9b334a45a8ff 859 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/