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fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
83:a036322b8637
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_sdram.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.1
bogdanm 0:9b334a45a8ff 6 * @date 25-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief SDRAM HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive SDRAM memories mounted
bogdanm 0:9b334a45a8ff 9 * as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control SDRAM memories. It uses the FMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with SDRAM devices.
bogdanm 0:9b334a45a8ff 19 The following sequence should be followed to configure the FMC to interface
bogdanm 0:9b334a45a8ff 20 with SDRAM memories:
bogdanm 0:9b334a45a8ff 21
bogdanm 0:9b334a45a8ff 22 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
bogdanm 0:9b334a45a8ff 23 SDRAM_HandleTypeDef hdsram
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
bogdanm 0:9b334a45a8ff 26 values of the structure member.
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
bogdanm 0:9b334a45a8ff 29 base register instance for NOR or SDRAM device
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
bogdanm 0:9b334a45a8ff 32 FMC_SDRAM_TimingTypeDef Timing;
bogdanm 0:9b334a45a8ff 33 and fill its fields with the allowed values of the structure member.
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
bogdanm 0:9b334a45a8ff 36 performs the following sequence:
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
bogdanm 0:9b334a45a8ff 39 (##) Control register configuration using the FMC SDRAM interface function
bogdanm 0:9b334a45a8ff 40 FMC_SDRAM_Init()
bogdanm 0:9b334a45a8ff 41 (##) Timing register configuration using the FMC SDRAM interface function
bogdanm 0:9b334a45a8ff 42 FMC_SDRAM_Timing_Init()
bogdanm 0:9b334a45a8ff 43 (##) Program the SDRAM external device by applying its initialization sequence
bogdanm 0:9b334a45a8ff 44 according to the device plugged in your hardware. This step is mandatory
bogdanm 0:9b334a45a8ff 45 for accessing the SDRAM device.
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 (#) At this stage you can perform read/write accesses from/to the memory connected
bogdanm 0:9b334a45a8ff 48 to the SDRAM Bank. You can perform either polling or DMA transfer using the
bogdanm 0:9b334a45a8ff 49 following APIs:
bogdanm 0:9b334a45a8ff 50 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
bogdanm 0:9b334a45a8ff 51 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
bogdanm 0:9b334a45a8ff 54 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
bogdanm 0:9b334a45a8ff 55 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
bogdanm 0:9b334a45a8ff 56 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
bogdanm 0:9b334a45a8ff 57 structure.
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 (#) You can continuously monitor the SDRAM device HAL state by calling the function
bogdanm 0:9b334a45a8ff 60 HAL_SDRAM_GetState()
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 @endverbatim
bogdanm 0:9b334a45a8ff 63 ******************************************************************************
bogdanm 0:9b334a45a8ff 64 * @attention
bogdanm 0:9b334a45a8ff 65 *
bogdanm 0:9b334a45a8ff 66 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 67 *
bogdanm 0:9b334a45a8ff 68 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 69 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 70 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 71 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 72 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 73 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 74 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 75 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 76 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 77 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 78 *
bogdanm 0:9b334a45a8ff 79 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 80 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 82 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 86 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 87 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 89 *
bogdanm 0:9b334a45a8ff 90 ******************************************************************************
bogdanm 0:9b334a45a8ff 91 */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 94 #include "stm32f7xx_hal.h"
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 97 * @{
bogdanm 0:9b334a45a8ff 98 */
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 /** @defgroup SDRAM SDRAM
bogdanm 0:9b334a45a8ff 101 * @brief SDRAM driver modules
bogdanm 0:9b334a45a8ff 102 * @{
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104 #ifdef HAL_SDRAM_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 107 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 108 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 109 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 110 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 111 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 112 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
bogdanm 0:9b334a45a8ff 113 * @{
bogdanm 0:9b334a45a8ff 114 */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 117 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 118 *
bogdanm 0:9b334a45a8ff 119 @verbatim
bogdanm 0:9b334a45a8ff 120 ==============================================================================
bogdanm 0:9b334a45a8ff 121 ##### SDRAM Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 122 ==============================================================================
bogdanm 0:9b334a45a8ff 123 [..]
bogdanm 0:9b334a45a8ff 124 This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 125 the SDRAM memory
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 @endverbatim
bogdanm 0:9b334a45a8ff 128 * @{
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /**
bogdanm 0:9b334a45a8ff 132 * @brief Performs the SDRAM device initialization sequence.
bogdanm 0:9b334a45a8ff 133 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 134 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 135 * @param Timing: Pointer to SDRAM control timing structure
bogdanm 0:9b334a45a8ff 136 * @retval HAL status
bogdanm 0:9b334a45a8ff 137 */
bogdanm 0:9b334a45a8ff 138 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
bogdanm 0:9b334a45a8ff 139 {
bogdanm 0:9b334a45a8ff 140 /* Check the SDRAM handle parameter */
bogdanm 0:9b334a45a8ff 141 if(hsdram == NULL)
bogdanm 0:9b334a45a8ff 142 {
bogdanm 0:9b334a45a8ff 143 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 144 }
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 if(hsdram->State == HAL_SDRAM_STATE_RESET)
bogdanm 0:9b334a45a8ff 147 {
bogdanm 0:9b334a45a8ff 148 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 149 hsdram->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 150 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 151 HAL_SDRAM_MspInit(hsdram);
bogdanm 0:9b334a45a8ff 152 }
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 /* Initialize the SDRAM controller state */
bogdanm 0:9b334a45a8ff 155 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 /* Initialize SDRAM control Interface */
bogdanm 0:9b334a45a8ff 158 FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 /* Initialize SDRAM timing Interface */
bogdanm 0:9b334a45a8ff 161 FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 /* Update the SDRAM controller state */
bogdanm 0:9b334a45a8ff 164 hsdram->State = HAL_SDRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 return HAL_OK;
bogdanm 0:9b334a45a8ff 167 }
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 /**
bogdanm 0:9b334a45a8ff 170 * @brief Perform the SDRAM device initialization sequence.
bogdanm 0:9b334a45a8ff 171 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 172 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 173 * @retval HAL status
bogdanm 0:9b334a45a8ff 174 */
bogdanm 0:9b334a45a8ff 175 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 176 {
bogdanm 0:9b334a45a8ff 177 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 178 HAL_SDRAM_MspDeInit(hsdram);
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /* Configure the SDRAM registers with their reset values */
bogdanm 0:9b334a45a8ff 181 FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /* Reset the SDRAM controller state */
bogdanm 0:9b334a45a8ff 184 hsdram->State = HAL_SDRAM_STATE_RESET;
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /* Release Lock */
bogdanm 0:9b334a45a8ff 187 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 return HAL_OK;
bogdanm 0:9b334a45a8ff 190 }
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 /**
bogdanm 0:9b334a45a8ff 193 * @brief SDRAM MSP Init.
bogdanm 0:9b334a45a8ff 194 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 195 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 196 * @retval None
bogdanm 0:9b334a45a8ff 197 */
bogdanm 0:9b334a45a8ff 198 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 199 {
bogdanm 0:9b334a45a8ff 200 /* NOTE: This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 201 the HAL_SDRAM_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 202 */
bogdanm 0:9b334a45a8ff 203 }
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 /**
bogdanm 0:9b334a45a8ff 206 * @brief SDRAM MSP DeInit.
bogdanm 0:9b334a45a8ff 207 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 208 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 209 * @retval None
bogdanm 0:9b334a45a8ff 210 */
bogdanm 0:9b334a45a8ff 211 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 212 {
bogdanm 0:9b334a45a8ff 213 /* NOTE: This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 214 the HAL_SDRAM_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 215 */
bogdanm 0:9b334a45a8ff 216 }
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /**
bogdanm 0:9b334a45a8ff 219 * @brief This function handles SDRAM refresh error interrupt request.
bogdanm 0:9b334a45a8ff 220 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 221 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 222 * @retval HAL status
bogdanm 0:9b334a45a8ff 223 */
bogdanm 0:9b334a45a8ff 224 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 225 {
bogdanm 0:9b334a45a8ff 226 /* Check SDRAM interrupt Rising edge flag */
bogdanm 0:9b334a45a8ff 227 if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
bogdanm 0:9b334a45a8ff 228 {
bogdanm 0:9b334a45a8ff 229 /* SDRAM refresh error interrupt callback */
bogdanm 0:9b334a45a8ff 230 HAL_SDRAM_RefreshErrorCallback(hsdram);
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /* Clear SDRAM refresh error interrupt pending bit */
bogdanm 0:9b334a45a8ff 233 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
bogdanm 0:9b334a45a8ff 234 }
bogdanm 0:9b334a45a8ff 235 }
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /**
bogdanm 0:9b334a45a8ff 238 * @brief SDRAM Refresh error callback.
bogdanm 0:9b334a45a8ff 239 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 240 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 241 * @retval None
bogdanm 0:9b334a45a8ff 242 */
bogdanm 0:9b334a45a8ff 243 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 244 {
bogdanm 0:9b334a45a8ff 245 /* NOTE: This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 246 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 247 */
bogdanm 0:9b334a45a8ff 248 }
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 /**
bogdanm 0:9b334a45a8ff 251 * @brief DMA transfer complete callback.
bogdanm 0:9b334a45a8ff 252 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 253 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 254 * @retval None
bogdanm 0:9b334a45a8ff 255 */
bogdanm 0:9b334a45a8ff 256 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 257 {
bogdanm 0:9b334a45a8ff 258 /* NOTE: This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 259 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 260 */
bogdanm 0:9b334a45a8ff 261 }
bogdanm 0:9b334a45a8ff 262
bogdanm 0:9b334a45a8ff 263 /**
bogdanm 0:9b334a45a8ff 264 * @brief DMA transfer complete error callback.
bogdanm 0:9b334a45a8ff 265 * @param hdma: DMA handle
bogdanm 0:9b334a45a8ff 266 * @retval None
bogdanm 0:9b334a45a8ff 267 */
bogdanm 0:9b334a45a8ff 268 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 269 {
bogdanm 0:9b334a45a8ff 270 /* NOTE: This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 271 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 272 */
bogdanm 0:9b334a45a8ff 273 }
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 /**
bogdanm 0:9b334a45a8ff 276 * @}
bogdanm 0:9b334a45a8ff 277 */
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
bogdanm 0:9b334a45a8ff 280 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 281 *
bogdanm 0:9b334a45a8ff 282 @verbatim
bogdanm 0:9b334a45a8ff 283 ==============================================================================
bogdanm 0:9b334a45a8ff 284 ##### SDRAM Input and Output functions #####
bogdanm 0:9b334a45a8ff 285 ==============================================================================
bogdanm 0:9b334a45a8ff 286 [..]
bogdanm 0:9b334a45a8ff 287 This section provides functions allowing to use and control the SDRAM memory
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 @endverbatim
bogdanm 0:9b334a45a8ff 290 * @{
bogdanm 0:9b334a45a8ff 291 */
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 /**
bogdanm 0:9b334a45a8ff 294 * @brief Reads 8-bit data buffer from the SDRAM memory.
bogdanm 0:9b334a45a8ff 295 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 296 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 297 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 298 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 299 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 300 * @retval HAL status
bogdanm 0:9b334a45a8ff 301 */
bogdanm 0:9b334a45a8ff 302 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 303 {
bogdanm 0:9b334a45a8ff 304 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
bogdanm 0:9b334a45a8ff 305
bogdanm 0:9b334a45a8ff 306 /* Process Locked */
bogdanm 0:9b334a45a8ff 307 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 310 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 311 {
bogdanm 0:9b334a45a8ff 312 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 313 }
bogdanm 0:9b334a45a8ff 314 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
bogdanm 0:9b334a45a8ff 315 {
bogdanm 0:9b334a45a8ff 316 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 317 }
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319 /* Read data from source */
bogdanm 0:9b334a45a8ff 320 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 321 {
bogdanm 0:9b334a45a8ff 322 *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
bogdanm 0:9b334a45a8ff 323 pDstBuffer++;
bogdanm 0:9b334a45a8ff 324 pSdramAddress++;
bogdanm 0:9b334a45a8ff 325 }
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 328 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 return HAL_OK;
bogdanm 0:9b334a45a8ff 331 }
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 /**
bogdanm 0:9b334a45a8ff 335 * @brief Writes 8-bit data buffer to SDRAM memory.
bogdanm 0:9b334a45a8ff 336 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 337 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 338 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 339 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 340 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 341 * @retval HAL status
bogdanm 0:9b334a45a8ff 342 */
bogdanm 0:9b334a45a8ff 343 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 344 {
bogdanm 0:9b334a45a8ff 345 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
bogdanm 0:9b334a45a8ff 346 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 /* Process Locked */
bogdanm 0:9b334a45a8ff 349 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 352 tmp = hsdram->State;
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 if(tmp == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 355 {
bogdanm 0:9b334a45a8ff 356 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 357 }
bogdanm 0:9b334a45a8ff 358 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
bogdanm 0:9b334a45a8ff 359 {
bogdanm 0:9b334a45a8ff 360 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 361 }
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /* Write data to memory */
bogdanm 0:9b334a45a8ff 364 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 365 {
bogdanm 0:9b334a45a8ff 366 *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 367 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 368 pSdramAddress++;
bogdanm 0:9b334a45a8ff 369 }
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 372 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 return HAL_OK;
bogdanm 0:9b334a45a8ff 375 }
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 /**
bogdanm 0:9b334a45a8ff 379 * @brief Reads 16-bit data buffer from the SDRAM memory.
bogdanm 0:9b334a45a8ff 380 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 381 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 382 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 383 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 384 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 385 * @retval HAL status
bogdanm 0:9b334a45a8ff 386 */
bogdanm 0:9b334a45a8ff 387 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 388 {
bogdanm 0:9b334a45a8ff 389 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 /* Process Locked */
bogdanm 0:9b334a45a8ff 392 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 395 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 396 {
bogdanm 0:9b334a45a8ff 397 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 398 }
bogdanm 0:9b334a45a8ff 399 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
bogdanm 0:9b334a45a8ff 400 {
bogdanm 0:9b334a45a8ff 401 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 402 }
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 /* Read data from source */
bogdanm 0:9b334a45a8ff 405 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 406 {
bogdanm 0:9b334a45a8ff 407 *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
bogdanm 0:9b334a45a8ff 408 pDstBuffer++;
bogdanm 0:9b334a45a8ff 409 pSdramAddress++;
bogdanm 0:9b334a45a8ff 410 }
bogdanm 0:9b334a45a8ff 411
bogdanm 0:9b334a45a8ff 412 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 413 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 414
bogdanm 0:9b334a45a8ff 415 return HAL_OK;
bogdanm 0:9b334a45a8ff 416 }
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 /**
bogdanm 0:9b334a45a8ff 419 * @brief Writes 16-bit data buffer to SDRAM memory.
bogdanm 0:9b334a45a8ff 420 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 421 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 422 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 423 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 424 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 425 * @retval HAL status
bogdanm 0:9b334a45a8ff 426 */
bogdanm 0:9b334a45a8ff 427 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 428 {
bogdanm 0:9b334a45a8ff 429 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
bogdanm 0:9b334a45a8ff 430 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /* Process Locked */
bogdanm 0:9b334a45a8ff 433 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 436 tmp = hsdram->State;
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 if(tmp == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 439 {
bogdanm 0:9b334a45a8ff 440 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 441 }
bogdanm 0:9b334a45a8ff 442 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
bogdanm 0:9b334a45a8ff 443 {
bogdanm 0:9b334a45a8ff 444 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 445 }
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 /* Write data to memory */
bogdanm 0:9b334a45a8ff 448 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 449 {
bogdanm 0:9b334a45a8ff 450 *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 451 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 452 pSdramAddress++;
bogdanm 0:9b334a45a8ff 453 }
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 456 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 return HAL_OK;
bogdanm 0:9b334a45a8ff 459 }
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /**
bogdanm 0:9b334a45a8ff 462 * @brief Reads 32-bit data buffer from the SDRAM memory.
bogdanm 0:9b334a45a8ff 463 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 464 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 465 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 466 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 467 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 468 * @retval HAL status
bogdanm 0:9b334a45a8ff 469 */
bogdanm 0:9b334a45a8ff 470 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 471 {
bogdanm 0:9b334a45a8ff 472 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 /* Process Locked */
bogdanm 0:9b334a45a8ff 475 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 478 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 479 {
bogdanm 0:9b334a45a8ff 480 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 481 }
bogdanm 0:9b334a45a8ff 482 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
bogdanm 0:9b334a45a8ff 483 {
bogdanm 0:9b334a45a8ff 484 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 485 }
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 /* Read data from source */
bogdanm 0:9b334a45a8ff 488 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 489 {
bogdanm 0:9b334a45a8ff 490 *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
bogdanm 0:9b334a45a8ff 491 pDstBuffer++;
bogdanm 0:9b334a45a8ff 492 pSdramAddress++;
bogdanm 0:9b334a45a8ff 493 }
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 496 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 return HAL_OK;
bogdanm 0:9b334a45a8ff 499 }
bogdanm 0:9b334a45a8ff 500
bogdanm 0:9b334a45a8ff 501 /**
bogdanm 0:9b334a45a8ff 502 * @brief Writes 32-bit data buffer to SDRAM memory.
bogdanm 0:9b334a45a8ff 503 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 504 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 505 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 506 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 507 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 508 * @retval HAL status
bogdanm 0:9b334a45a8ff 509 */
bogdanm 0:9b334a45a8ff 510 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 511 {
bogdanm 0:9b334a45a8ff 512 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
bogdanm 0:9b334a45a8ff 513 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 514
bogdanm 0:9b334a45a8ff 515 /* Process Locked */
bogdanm 0:9b334a45a8ff 516 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 519 tmp = hsdram->State;
bogdanm 0:9b334a45a8ff 520
bogdanm 0:9b334a45a8ff 521 if(tmp == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 522 {
bogdanm 0:9b334a45a8ff 523 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 524 }
bogdanm 0:9b334a45a8ff 525 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
bogdanm 0:9b334a45a8ff 526 {
bogdanm 0:9b334a45a8ff 527 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 528 }
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /* Write data to memory */
bogdanm 0:9b334a45a8ff 531 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 532 {
bogdanm 0:9b334a45a8ff 533 *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 534 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 535 pSdramAddress++;
bogdanm 0:9b334a45a8ff 536 }
bogdanm 0:9b334a45a8ff 537
bogdanm 0:9b334a45a8ff 538 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 539 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 return HAL_OK;
bogdanm 0:9b334a45a8ff 542 }
bogdanm 0:9b334a45a8ff 543
bogdanm 0:9b334a45a8ff 544 /**
bogdanm 0:9b334a45a8ff 545 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
bogdanm 0:9b334a45a8ff 546 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 547 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 548 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 549 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 550 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 551 * @retval HAL status
bogdanm 0:9b334a45a8ff 552 */
bogdanm 0:9b334a45a8ff 553 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 554 {
bogdanm 0:9b334a45a8ff 555 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 /* Process Locked */
bogdanm 0:9b334a45a8ff 558 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 561 tmp = hsdram->State;
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 if(tmp == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 564 {
bogdanm 0:9b334a45a8ff 565 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 566 }
bogdanm 0:9b334a45a8ff 567 else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
bogdanm 0:9b334a45a8ff 568 {
bogdanm 0:9b334a45a8ff 569 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 570 }
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 /* Configure DMA user callbacks */
bogdanm 0:9b334a45a8ff 573 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
bogdanm 0:9b334a45a8ff 574 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 577 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 580 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582 return HAL_OK;
bogdanm 0:9b334a45a8ff 583 }
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 /**
bogdanm 0:9b334a45a8ff 586 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
bogdanm 0:9b334a45a8ff 587 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 588 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 589 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 590 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 591 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 592 * @retval HAL status
bogdanm 0:9b334a45a8ff 593 */
bogdanm 0:9b334a45a8ff 594 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 595 {
bogdanm 0:9b334a45a8ff 596 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 597
bogdanm 0:9b334a45a8ff 598 /* Process Locked */
bogdanm 0:9b334a45a8ff 599 __HAL_LOCK(hsdram);
bogdanm 0:9b334a45a8ff 600
bogdanm 0:9b334a45a8ff 601 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 602 tmp = hsdram->State;
bogdanm 0:9b334a45a8ff 603
bogdanm 0:9b334a45a8ff 604 if(tmp == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 605 {
bogdanm 0:9b334a45a8ff 606 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 607 }
bogdanm 0:9b334a45a8ff 608 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
bogdanm 0:9b334a45a8ff 609 {
bogdanm 0:9b334a45a8ff 610 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 611 }
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 /* Configure DMA user callbacks */
bogdanm 0:9b334a45a8ff 614 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
bogdanm 0:9b334a45a8ff 615 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 618 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
bogdanm 0:9b334a45a8ff 619
bogdanm 0:9b334a45a8ff 620 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 621 __HAL_UNLOCK(hsdram);
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 return HAL_OK;
bogdanm 0:9b334a45a8ff 624 }
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /**
bogdanm 0:9b334a45a8ff 627 * @}
bogdanm 0:9b334a45a8ff 628 */
bogdanm 0:9b334a45a8ff 629
bogdanm 0:9b334a45a8ff 630 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
bogdanm 0:9b334a45a8ff 631 * @brief management functions
bogdanm 0:9b334a45a8ff 632 *
bogdanm 0:9b334a45a8ff 633 @verbatim
bogdanm 0:9b334a45a8ff 634 ==============================================================================
bogdanm 0:9b334a45a8ff 635 ##### SDRAM Control functions #####
bogdanm 0:9b334a45a8ff 636 ==============================================================================
bogdanm 0:9b334a45a8ff 637 [..]
bogdanm 0:9b334a45a8ff 638 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 639 the SDRAM interface.
bogdanm 0:9b334a45a8ff 640
bogdanm 0:9b334a45a8ff 641 @endverbatim
bogdanm 0:9b334a45a8ff 642 * @{
bogdanm 0:9b334a45a8ff 643 */
bogdanm 0:9b334a45a8ff 644
bogdanm 0:9b334a45a8ff 645 /**
bogdanm 0:9b334a45a8ff 646 * @brief Enables dynamically SDRAM write protection.
bogdanm 0:9b334a45a8ff 647 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 648 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 649 * @retval HAL status
bogdanm 0:9b334a45a8ff 650 */
bogdanm 0:9b334a45a8ff 651 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 652 {
bogdanm 0:9b334a45a8ff 653 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 654 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 655 {
bogdanm 0:9b334a45a8ff 656 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 657 }
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 660 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 661
bogdanm 0:9b334a45a8ff 662 /* Enable write protection */
bogdanm 0:9b334a45a8ff 663 FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
bogdanm 0:9b334a45a8ff 664
bogdanm 0:9b334a45a8ff 665 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 666 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
bogdanm 0:9b334a45a8ff 667
bogdanm 0:9b334a45a8ff 668 return HAL_OK;
bogdanm 0:9b334a45a8ff 669 }
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 /**
bogdanm 0:9b334a45a8ff 672 * @brief Disables dynamically SDRAM write protection.
bogdanm 0:9b334a45a8ff 673 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 674 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 675 * @retval HAL status
bogdanm 0:9b334a45a8ff 676 */
bogdanm 0:9b334a45a8ff 677 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 678 {
bogdanm 0:9b334a45a8ff 679 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 680 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 681 {
bogdanm 0:9b334a45a8ff 682 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 683 }
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 686 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 /* Disable write protection */
bogdanm 0:9b334a45a8ff 689 FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
bogdanm 0:9b334a45a8ff 690
bogdanm 0:9b334a45a8ff 691 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 692 hsdram->State = HAL_SDRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 693
bogdanm 0:9b334a45a8ff 694 return HAL_OK;
bogdanm 0:9b334a45a8ff 695 }
bogdanm 0:9b334a45a8ff 696
bogdanm 0:9b334a45a8ff 697 /**
bogdanm 0:9b334a45a8ff 698 * @brief Sends Command to the SDRAM bank.
bogdanm 0:9b334a45a8ff 699 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 700 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 701 * @param Command: SDRAM command structure
bogdanm 0:9b334a45a8ff 702 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 703 * @retval HAL status
bogdanm 0:9b334a45a8ff 704 */
bogdanm 0:9b334a45a8ff 705 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 706 {
bogdanm 0:9b334a45a8ff 707 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 708 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 709 {
bogdanm 0:9b334a45a8ff 710 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 711 }
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 714 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 /* Send SDRAM command */
bogdanm 0:9b334a45a8ff 717 FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
bogdanm 0:9b334a45a8ff 718
bogdanm 0:9b334a45a8ff 719 /* Update the SDRAM controller state state */
bogdanm 0:9b334a45a8ff 720 if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
bogdanm 0:9b334a45a8ff 721 {
bogdanm 0:9b334a45a8ff 722 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
bogdanm 0:9b334a45a8ff 723 }
bogdanm 0:9b334a45a8ff 724 else
bogdanm 0:9b334a45a8ff 725 {
bogdanm 0:9b334a45a8ff 726 hsdram->State = HAL_SDRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 727 }
bogdanm 0:9b334a45a8ff 728
bogdanm 0:9b334a45a8ff 729 return HAL_OK;
bogdanm 0:9b334a45a8ff 730 }
bogdanm 0:9b334a45a8ff 731
bogdanm 0:9b334a45a8ff 732 /**
bogdanm 0:9b334a45a8ff 733 * @brief Programs the SDRAM Memory Refresh rate.
bogdanm 0:9b334a45a8ff 734 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 735 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 736 * @param RefreshRate: The SDRAM refresh rate value
bogdanm 0:9b334a45a8ff 737 * @retval HAL status
bogdanm 0:9b334a45a8ff 738 */
bogdanm 0:9b334a45a8ff 739 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
bogdanm 0:9b334a45a8ff 740 {
bogdanm 0:9b334a45a8ff 741 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 742 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 743 {
bogdanm 0:9b334a45a8ff 744 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 745 }
bogdanm 0:9b334a45a8ff 746
bogdanm 0:9b334a45a8ff 747 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 748 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 /* Program the refresh rate */
bogdanm 0:9b334a45a8ff 751 FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
bogdanm 0:9b334a45a8ff 752
bogdanm 0:9b334a45a8ff 753 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 754 hsdram->State = HAL_SDRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 755
bogdanm 0:9b334a45a8ff 756 return HAL_OK;
bogdanm 0:9b334a45a8ff 757 }
bogdanm 0:9b334a45a8ff 758
bogdanm 0:9b334a45a8ff 759 /**
bogdanm 0:9b334a45a8ff 760 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
bogdanm 0:9b334a45a8ff 761 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 762 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 763 * @param AutoRefreshNumber: The SDRAM auto Refresh number
bogdanm 0:9b334a45a8ff 764 * @retval HAL status
bogdanm 0:9b334a45a8ff 765 */
bogdanm 0:9b334a45a8ff 766 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
bogdanm 0:9b334a45a8ff 767 {
bogdanm 0:9b334a45a8ff 768 /* Check the SDRAM controller state */
bogdanm 0:9b334a45a8ff 769 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
bogdanm 0:9b334a45a8ff 770 {
bogdanm 0:9b334a45a8ff 771 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 772 }
bogdanm 0:9b334a45a8ff 773
bogdanm 0:9b334a45a8ff 774 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 775 hsdram->State = HAL_SDRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 776
bogdanm 0:9b334a45a8ff 777 /* Set the Auto-Refresh number */
bogdanm 0:9b334a45a8ff 778 FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
bogdanm 0:9b334a45a8ff 779
bogdanm 0:9b334a45a8ff 780 /* Update the SDRAM state */
bogdanm 0:9b334a45a8ff 781 hsdram->State = HAL_SDRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 782
bogdanm 0:9b334a45a8ff 783 return HAL_OK;
bogdanm 0:9b334a45a8ff 784 }
bogdanm 0:9b334a45a8ff 785
bogdanm 0:9b334a45a8ff 786 /**
bogdanm 0:9b334a45a8ff 787 * @brief Returns the SDRAM memory current mode.
bogdanm 0:9b334a45a8ff 788 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 789 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 790 * @retval The SDRAM memory mode.
bogdanm 0:9b334a45a8ff 791 */
bogdanm 0:9b334a45a8ff 792 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 793 {
bogdanm 0:9b334a45a8ff 794 /* Return the SDRAM memory current mode */
bogdanm 0:9b334a45a8ff 795 return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
bogdanm 0:9b334a45a8ff 796 }
bogdanm 0:9b334a45a8ff 797
bogdanm 0:9b334a45a8ff 798 /**
bogdanm 0:9b334a45a8ff 799 * @}
bogdanm 0:9b334a45a8ff 800 */
bogdanm 0:9b334a45a8ff 801
bogdanm 0:9b334a45a8ff 802 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
bogdanm 0:9b334a45a8ff 803 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 804 *
bogdanm 0:9b334a45a8ff 805 @verbatim
bogdanm 0:9b334a45a8ff 806 ==============================================================================
bogdanm 0:9b334a45a8ff 807 ##### SDRAM State functions #####
bogdanm 0:9b334a45a8ff 808 ==============================================================================
bogdanm 0:9b334a45a8ff 809 [..]
bogdanm 0:9b334a45a8ff 810 This subsection permits to get in run-time the status of the SDRAM controller
bogdanm 0:9b334a45a8ff 811 and the data flow.
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813 @endverbatim
bogdanm 0:9b334a45a8ff 814 * @{
bogdanm 0:9b334a45a8ff 815 */
bogdanm 0:9b334a45a8ff 816
bogdanm 0:9b334a45a8ff 817 /**
bogdanm 0:9b334a45a8ff 818 * @brief Returns the SDRAM state.
bogdanm 0:9b334a45a8ff 819 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 820 * the configuration information for SDRAM module.
bogdanm 0:9b334a45a8ff 821 * @retval HAL state
bogdanm 0:9b334a45a8ff 822 */
bogdanm 0:9b334a45a8ff 823 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
bogdanm 0:9b334a45a8ff 824 {
bogdanm 0:9b334a45a8ff 825 return hsdram->State;
bogdanm 0:9b334a45a8ff 826 }
bogdanm 0:9b334a45a8ff 827
bogdanm 0:9b334a45a8ff 828 /**
bogdanm 0:9b334a45a8ff 829 * @}
bogdanm 0:9b334a45a8ff 830 */
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 /**
bogdanm 0:9b334a45a8ff 833 * @}
bogdanm 0:9b334a45a8ff 834 */
bogdanm 0:9b334a45a8ff 835 #endif /* HAL_SDRAM_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 836 /**
bogdanm 0:9b334a45a8ff 837 * @}
bogdanm 0:9b334a45a8ff 838 */
bogdanm 0:9b334a45a8ff 839
bogdanm 0:9b334a45a8ff 840 /**
bogdanm 0:9b334a45a8ff 841 * @}
bogdanm 0:9b334a45a8ff 842 */
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/