mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 83:a036322b8637

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f7xx_hal_qspi.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	83:a036322b8637	5	* @version V1.0.4
mbed_official	83:a036322b8637	6	* @date 09-December-2015
bogdanm	0:9b334a45a8ff	7	* @brief QSPI HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the QuadSPI interface (QSPI).
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + Indirect functional mode management
bogdanm	0:9b334a45a8ff	12	* + Memory-mapped functional mode management
bogdanm	0:9b334a45a8ff	13	* + Auto-polling functional mode management
bogdanm	0:9b334a45a8ff	14	* + Interrupts and flags management
bogdanm	0:9b334a45a8ff	15	* + DMA channel configuration for indirect functional mode
bogdanm	0:9b334a45a8ff	16	* + Errors management and abort functionality
bogdanm	0:9b334a45a8ff	17	*
bogdanm	0:9b334a45a8ff	18	*
bogdanm	0:9b334a45a8ff	19	@verbatim
bogdanm	0:9b334a45a8ff	20	===============================================================================
bogdanm	0:9b334a45a8ff	21	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	22	===============================================================================
bogdanm	0:9b334a45a8ff	23	[..]
bogdanm	0:9b334a45a8ff	24	* Initialization *
bogdanm	0:9b334a45a8ff	25	======================
bogdanm	0:9b334a45a8ff	26	[..]
bogdanm	0:9b334a45a8ff	27	(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
bogdanm	0:9b334a45a8ff	28	(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
bogdanm	0:9b334a45a8ff	29	(++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
bogdanm	0:9b334a45a8ff	30	(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
bogdanm	0:9b334a45a8ff	31	(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
bogdanm	0:9b334a45a8ff	32	(++) If interrupt mode is used, enable and configure QuadSPI global
bogdanm	0:9b334a45a8ff	33	interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
bogdanm	0:9b334a45a8ff	34	(++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
bogdanm	0:9b334a45a8ff	35	with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
bogdanm	0:9b334a45a8ff	36	link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
bogdanm	0:9b334a45a8ff	37	DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
bogdanm	0:9b334a45a8ff	38	(#) Configure the flash size, the clock prescaler, the fifo threshold, the
bogdanm	0:9b334a45a8ff	39	clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	* Indirect functional mode *
bogdanm	0:9b334a45a8ff	42	================================
bogdanm	0:9b334a45a8ff	43	[..]
bogdanm	0:9b334a45a8ff	44	(#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
bogdanm	0:9b334a45a8ff	45	functions :
bogdanm	0:9b334a45a8ff	46	(++) Instruction phase : the mode used and if present the instruction opcode.
bogdanm	0:9b334a45a8ff	47	(++) Address phase : the mode used and if present the size and the address value.
bogdanm	0:9b334a45a8ff	48	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
bogdanm	0:9b334a45a8ff	49	bytes values.
bogdanm	0:9b334a45a8ff	50	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
bogdanm	0:9b334a45a8ff	51	(++) Data phase : the mode used and if present the number of bytes.
bogdanm	0:9b334a45a8ff	52	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
bogdanm	0:9b334a45a8ff	53	if activated.
bogdanm	0:9b334a45a8ff	54	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
bogdanm	0:9b334a45a8ff	55	(#) If no data is required for the command, it is sent directly to the memory :
bogdanm	0:9b334a45a8ff	56	(++) In polling mode, the output of the function is done when the transfer is complete.
bogdanm	0:9b334a45a8ff	57	(++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	58	(#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
bogdanm	0:9b334a45a8ff	59	HAL_QSPI_Transmit_IT() after the command configuration :
bogdanm	0:9b334a45a8ff	60	(++) In polling mode, the output of the function is done when the transfer is complete.
bogdanm	0:9b334a45a8ff	61	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
bogdanm	0:9b334a45a8ff	62	is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	63	(++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
bogdanm	0:9b334a45a8ff	64	HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	65	(#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
bogdanm	0:9b334a45a8ff	66	HAL_QSPI_Receive_IT() after the command configuration :
bogdanm	0:9b334a45a8ff	67	(++) In polling mode, the output of the function is done when the transfer is complete.
bogdanm	0:9b334a45a8ff	68	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
bogdanm	0:9b334a45a8ff	69	is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	70	(++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
bogdanm	0:9b334a45a8ff	71	HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	* Auto-polling functional mode *
bogdanm	0:9b334a45a8ff	74	====================================
bogdanm	0:9b334a45a8ff	75	[..]
bogdanm	0:9b334a45a8ff	76	(#) Configure the command sequence and the auto-polling functional mode using the
bogdanm	0:9b334a45a8ff	77	HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
bogdanm	0:9b334a45a8ff	78	(++) Instruction phase : the mode used and if present the instruction opcode.
bogdanm	0:9b334a45a8ff	79	(++) Address phase : the mode used and if present the size and the address value.
bogdanm	0:9b334a45a8ff	80	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
bogdanm	0:9b334a45a8ff	81	bytes values.
bogdanm	0:9b334a45a8ff	82	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
bogdanm	0:9b334a45a8ff	83	(++) Data phase : the mode used.
bogdanm	0:9b334a45a8ff	84	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
bogdanm	0:9b334a45a8ff	85	if activated.
bogdanm	0:9b334a45a8ff	86	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
bogdanm	0:9b334a45a8ff	87	(++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
bogdanm	0:9b334a45a8ff	88	the polling interval and the automatic stop activation.
bogdanm	0:9b334a45a8ff	89	(#) After the configuration :
bogdanm	0:9b334a45a8ff	90	(++) In polling mode, the output of the function is done when the status match is reached. The
bogdanm	0:9b334a45a8ff	91	automatic stop is activated to avoid an infinite loop.
bogdanm	0:9b334a45a8ff	92	(++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	* Memory-mapped functional mode *
bogdanm	0:9b334a45a8ff	95	=====================================
bogdanm	0:9b334a45a8ff	96	[..]
bogdanm	0:9b334a45a8ff	97	(#) Configure the command sequence and the memory-mapped functional mode using the
bogdanm	0:9b334a45a8ff	98	HAL_QSPI_MemoryMapped() functions :
bogdanm	0:9b334a45a8ff	99	(++) Instruction phase : the mode used and if present the instruction opcode.
bogdanm	0:9b334a45a8ff	100	(++) Address phase : the mode used and the size.
bogdanm	0:9b334a45a8ff	101	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
bogdanm	0:9b334a45a8ff	102	bytes values.
bogdanm	0:9b334a45a8ff	103	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
bogdanm	0:9b334a45a8ff	104	(++) Data phase : the mode used.
bogdanm	0:9b334a45a8ff	105	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
bogdanm	0:9b334a45a8ff	106	if activated.
bogdanm	0:9b334a45a8ff	107	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
bogdanm	0:9b334a45a8ff	108	(++) The timeout activation and the timeout period.
bogdanm	0:9b334a45a8ff	109	(#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
bogdanm	0:9b334a45a8ff	110	the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112	* Errors management and abort functionality *
bogdanm	0:9b334a45a8ff	113	==================================================
bogdanm	0:9b334a45a8ff	114	[..]
bogdanm	0:9b334a45a8ff	115	(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
bogdanm	0:9b334a45a8ff	116	(#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
bogdanm	0:9b334a45a8ff	117	(#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	* Workarounds linked to Silicon Limitation *
bogdanm	0:9b334a45a8ff	120	====================================================
bogdanm	0:9b334a45a8ff	121	[..]
bogdanm	0:9b334a45a8ff	122	(#) Workarounds Implemented inside HAL Driver
bogdanm	0:9b334a45a8ff	123	(++) Extra data written in the FIFO at the end of a read transfer
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125	@endverbatim
bogdanm	0:9b334a45a8ff	126	******************************************************************************
bogdanm	0:9b334a45a8ff	127	* @attention
bogdanm	0:9b334a45a8ff	128	*
bogdanm	0:9b334a45a8ff	129	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	130	*
bogdanm	0:9b334a45a8ff	131	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	132	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	133	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	134	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	135	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	136	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	137	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	138	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	139	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	140	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	141	*
bogdanm	0:9b334a45a8ff	142	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	143	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	144	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	145	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	146	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	147	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	148	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	149	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	150	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	151	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	152	*
bogdanm	0:9b334a45a8ff	153	******************************************************************************
bogdanm	0:9b334a45a8ff	154	*/
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	157	#include "stm32f7xx_hal.h"
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	/** @addtogroup STM32F7xx_HAL_Driver
bogdanm	0:9b334a45a8ff	160	* @{
bogdanm	0:9b334a45a8ff	161	*/
bogdanm	0:9b334a45a8ff	162
bogdanm	0:9b334a45a8ff	163	/** @defgroup QSPI QSPI
bogdanm	0:9b334a45a8ff	164	* @brief HAL QSPI module driver
bogdanm	0:9b334a45a8ff	165	* @{
bogdanm	0:9b334a45a8ff	166	*/
bogdanm	0:9b334a45a8ff	167	#ifdef HAL_QSPI_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	170	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	171	/** @addtogroup QSPI_Private_Constants
bogdanm	0:9b334a45a8ff	172	* @{
bogdanm	0:9b334a45a8ff	173	*/
bogdanm	0:9b334a45a8ff	174	#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /!<Indirect write mode/
bogdanm	0:9b334a45a8ff	175	#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /!<Indirect read mode/
bogdanm	0:9b334a45a8ff	176	#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /!<Automatic polling mode/
bogdanm	0:9b334a45a8ff	177	#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /!<Memory-mapped mode/
bogdanm	0:9b334a45a8ff	178	/**
bogdanm	0:9b334a45a8ff	179	* @}
bogdanm	0:9b334a45a8ff	180	*/
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	183	/** @addtogroup QSPI_Private_Macros QSPI Private Macros
bogdanm	0:9b334a45a8ff	184	* @{
bogdanm	0:9b334a45a8ff	185	*/
bogdanm	0:9b334a45a8ff	186	#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) \|\| \
bogdanm	0:9b334a45a8ff	187	((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) \|\| \
bogdanm	0:9b334a45a8ff	188	((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) \|\| \
bogdanm	0:9b334a45a8ff	189	((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
bogdanm	0:9b334a45a8ff	190	/**
bogdanm	0:9b334a45a8ff	191	* @}
bogdanm	0:9b334a45a8ff	192	*/
bogdanm	0:9b334a45a8ff	193
bogdanm	0:9b334a45a8ff	194	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	195	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	196	/** @addtogroup QSPI_Private_Functions QSPI Private Functions
bogdanm	0:9b334a45a8ff	197	* @{
bogdanm	0:9b334a45a8ff	198	*/
bogdanm	0:9b334a45a8ff	199	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	200	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	201	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	202	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	203	static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	204	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	205	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode);
bogdanm	0:9b334a45a8ff	206	/**
bogdanm	0:9b334a45a8ff	207	* @}
bogdanm	0:9b334a45a8ff	208	*/
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
bogdanm	0:9b334a45a8ff	213	* @{
bogdanm	0:9b334a45a8ff	214	*/
bogdanm	0:9b334a45a8ff	215
bogdanm	0:9b334a45a8ff	216	/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	217	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	218	*
bogdanm	0:9b334a45a8ff	219	@verbatim
bogdanm	0:9b334a45a8ff	220	===============================================================================
bogdanm	0:9b334a45a8ff	221	##### Initialization and Configuration functions #####
bogdanm	0:9b334a45a8ff	222	===============================================================================
bogdanm	0:9b334a45a8ff	223	[..]
bogdanm	0:9b334a45a8ff	224	This subsection provides a set of functions allowing to :
bogdanm	0:9b334a45a8ff	225	(+) Initialize the QuadSPI.
bogdanm	0:9b334a45a8ff	226	(+) De-initialize the QuadSPI.
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	@endverbatim
bogdanm	0:9b334a45a8ff	229	* @{
bogdanm	0:9b334a45a8ff	230	*/
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	/**
bogdanm	0:9b334a45a8ff	233	* @brief Initializes the QSPI mode according to the specified parameters
bogdanm	0:9b334a45a8ff	234	* in the QSPI_InitTypeDef and creates the associated handle.
bogdanm	0:9b334a45a8ff	235	* @param hqspi: qspi handle
bogdanm	0:9b334a45a8ff	236	* @retval HAL status
bogdanm	0:9b334a45a8ff	237	*/
bogdanm	0:9b334a45a8ff	238	HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	239	{
bogdanm	0:9b334a45a8ff	240	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	/* Check the QSPI handle allocation */
bogdanm	0:9b334a45a8ff	243	if(hqspi == NULL)
bogdanm	0:9b334a45a8ff	244	{
bogdanm	0:9b334a45a8ff	245	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	246	}
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248	/* Check the parameters */
bogdanm	0:9b334a45a8ff	249	assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
bogdanm	0:9b334a45a8ff	250	assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
bogdanm	0:9b334a45a8ff	251	assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
bogdanm	0:9b334a45a8ff	252	assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
bogdanm	0:9b334a45a8ff	253	assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
bogdanm	0:9b334a45a8ff	254	assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
bogdanm	0:9b334a45a8ff	255	assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
bogdanm	0:9b334a45a8ff	256	assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
bogdanm	0:9b334a45a8ff	259	{
bogdanm	0:9b334a45a8ff	260	assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
bogdanm	0:9b334a45a8ff	261	}
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263	/* Process locked */
bogdanm	0:9b334a45a8ff	264	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	265
bogdanm	0:9b334a45a8ff	266	if(hqspi->State == HAL_QSPI_STATE_RESET)
bogdanm	0:9b334a45a8ff	267	{
bogdanm	0:9b334a45a8ff	268	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	269	hqspi->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	270
bogdanm	0:9b334a45a8ff	271	/* Init the low level hardware : GPIO, CLOCK */
bogdanm	0:9b334a45a8ff	272	HAL_QSPI_MspInit(hqspi);
bogdanm	0:9b334a45a8ff	273
bogdanm	0:9b334a45a8ff	274	/* Configure the default timeout for the QSPI memory access */
bogdanm	0:9b334a45a8ff	275	HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
bogdanm	0:9b334a45a8ff	276	}
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	/* Configure QSPI FIFO Threshold */
bogdanm	0:9b334a45a8ff	279	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	282	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	if(status == HAL_OK)
bogdanm	0:9b334a45a8ff	285	{
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287	/* Configure QSPI Clock Prescaler and Sample Shift */
bogdanm	0:9b334a45a8ff	288	MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER \| QUADSPI_CR_SSHIFT \| QUADSPI_CR_FSEL \| QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)\| hqspi->Init.SampleShifting \| hqspi->Init.FlashID\| hqspi->Init.DualFlash ));
bogdanm	0:9b334a45a8ff	289
bogdanm	0:9b334a45a8ff	290	/* Configure QSPI Flash Size, CS High Time and Clock Mode */
bogdanm	0:9b334a45a8ff	291	MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE \| QUADSPI_DCR_CSHT \| QUADSPI_DCR_CKMODE),
bogdanm	0:9b334a45a8ff	292	((hqspi->Init.FlashSize << 16) \| hqspi->Init.ChipSelectHighTime \| hqspi->Init.ClockMode));
bogdanm	0:9b334a45a8ff	293
bogdanm	0:9b334a45a8ff	294	/* Enable the QSPI peripheral */
bogdanm	0:9b334a45a8ff	295	__HAL_QSPI_ENABLE(hqspi);
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/* Set QSPI error code to none */
bogdanm	0:9b334a45a8ff	298	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	299
bogdanm	0:9b334a45a8ff	300	/* Initialize the QSPI state */
bogdanm	0:9b334a45a8ff	301	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	302	}
bogdanm	0:9b334a45a8ff	303
bogdanm	0:9b334a45a8ff	304	/* Release Lock */
bogdanm	0:9b334a45a8ff	305	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	306
bogdanm	0:9b334a45a8ff	307	/* Return function status */
bogdanm	0:9b334a45a8ff	308	return status;
bogdanm	0:9b334a45a8ff	309	}
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	/**
bogdanm	0:9b334a45a8ff	312	* @brief DeInitializes the QSPI peripheral
bogdanm	0:9b334a45a8ff	313	* @param hqspi: qspi handle
bogdanm	0:9b334a45a8ff	314	* @retval HAL status
bogdanm	0:9b334a45a8ff	315	*/
bogdanm	0:9b334a45a8ff	316	HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	317	{
bogdanm	0:9b334a45a8ff	318	/* Check the QSPI handle allocation */
bogdanm	0:9b334a45a8ff	319	if(hqspi == NULL)
bogdanm	0:9b334a45a8ff	320	{
bogdanm	0:9b334a45a8ff	321	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	322	}
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324	/* Process locked */
bogdanm	0:9b334a45a8ff	325	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	/* Disable the QSPI Peripheral Clock */
bogdanm	0:9b334a45a8ff	328	__HAL_QSPI_DISABLE(hqspi);
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	331	HAL_QSPI_MspDeInit(hqspi);
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	/* Set QSPI error code to none */
bogdanm	0:9b334a45a8ff	334	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	/* Initialize the QSPI state */
bogdanm	0:9b334a45a8ff	337	hqspi->State = HAL_QSPI_STATE_RESET;
bogdanm	0:9b334a45a8ff	338
bogdanm	0:9b334a45a8ff	339	/* Release Lock */
bogdanm	0:9b334a45a8ff	340	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	return HAL_OK;
bogdanm	0:9b334a45a8ff	343	}
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/**
bogdanm	0:9b334a45a8ff	346	* @brief QSPI MSP Init
bogdanm	0:9b334a45a8ff	347	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	348	* @retval None
bogdanm	0:9b334a45a8ff	349	*/
bogdanm	0:9b334a45a8ff	350	__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	351	{
mbed_official	83:a036322b8637	352	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	353	UNUSED(hqspi);
mbed_official	83:a036322b8637	354
bogdanm	0:9b334a45a8ff	355	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	356	the HAL_QSPI_MspInit can be implemented in the user file
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358	}
bogdanm	0:9b334a45a8ff	359
bogdanm	0:9b334a45a8ff	360	/**
bogdanm	0:9b334a45a8ff	361	* @brief QSPI MSP DeInit
bogdanm	0:9b334a45a8ff	362	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	363	* @retval None
bogdanm	0:9b334a45a8ff	364	*/
bogdanm	0:9b334a45a8ff	365	__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	366	{
mbed_official	83:a036322b8637	367	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	368	UNUSED(hqspi);
mbed_official	83:a036322b8637	369
bogdanm	0:9b334a45a8ff	370	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	371	the HAL_QSPI_MspDeInit can be implemented in the user file
bogdanm	0:9b334a45a8ff	372	*/
bogdanm	0:9b334a45a8ff	373	}
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	/**
bogdanm	0:9b334a45a8ff	376	* @}
bogdanm	0:9b334a45a8ff	377	*/
bogdanm	0:9b334a45a8ff	378
bogdanm	0:9b334a45a8ff	379	/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	380	* @brief QSPI Transmit/Receive functions
bogdanm	0:9b334a45a8ff	381	*
bogdanm	0:9b334a45a8ff	382	@verbatim
bogdanm	0:9b334a45a8ff	383	===============================================================================
bogdanm	0:9b334a45a8ff	384	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	385	===============================================================================
bogdanm	0:9b334a45a8ff	386	[..]
bogdanm	0:9b334a45a8ff	387	This subsection provides a set of functions allowing to :
bogdanm	0:9b334a45a8ff	388	(+) Handle the interrupts.
bogdanm	0:9b334a45a8ff	389	(+) Handle the command sequence.
bogdanm	0:9b334a45a8ff	390	(+) Transmit data in blocking, interrupt or DMA mode.
bogdanm	0:9b334a45a8ff	391	(+) Receive data in blocking, interrupt or DMA mode.
bogdanm	0:9b334a45a8ff	392	(+) Manage the auto-polling functional mode.
bogdanm	0:9b334a45a8ff	393	(+) Manage the memory-mapped functional mode.
bogdanm	0:9b334a45a8ff	394
bogdanm	0:9b334a45a8ff	395	@endverbatim
bogdanm	0:9b334a45a8ff	396	* @{
bogdanm	0:9b334a45a8ff	397	*/
bogdanm	0:9b334a45a8ff	398
bogdanm	0:9b334a45a8ff	399	/**
bogdanm	0:9b334a45a8ff	400	* @brief This function handles QSPI interrupt request.
bogdanm	0:9b334a45a8ff	401	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	402	* @retval None.
bogdanm	0:9b334a45a8ff	403	*/
bogdanm	0:9b334a45a8ff	404	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	405	{
bogdanm	0:9b334a45a8ff	406	__IO uint32_t *data_reg;
bogdanm	0:9b334a45a8ff	407	uint32_t flag = 0, itsource = 0;
bogdanm	0:9b334a45a8ff	408
bogdanm	0:9b334a45a8ff	409	/* QSPI FIFO Threshold interrupt occurred ----------------------------------*/
bogdanm	0:9b334a45a8ff	410	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
bogdanm	0:9b334a45a8ff	411	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
bogdanm	0:9b334a45a8ff	412
bogdanm	0:9b334a45a8ff	413	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	414	{
bogdanm	0:9b334a45a8ff	415	data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	416
bogdanm	0:9b334a45a8ff	417	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
bogdanm	0:9b334a45a8ff	418	{
bogdanm	0:9b334a45a8ff	419	/* Transmission process */
bogdanm	0:9b334a45a8ff	420	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
bogdanm	0:9b334a45a8ff	421	{
bogdanm	0:9b334a45a8ff	422	if (hqspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	423	{
bogdanm	0:9b334a45a8ff	424	/* Fill the FIFO until it is full */
bogdanm	0:9b334a45a8ff	425	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
bogdanm	0:9b334a45a8ff	426	hqspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	427	}
bogdanm	0:9b334a45a8ff	428	else
bogdanm	0:9b334a45a8ff	429	{
bogdanm	0:9b334a45a8ff	430	/* No more data available for the transfer */
bogdanm	0:9b334a45a8ff	431	break;
bogdanm	0:9b334a45a8ff	432	}
bogdanm	0:9b334a45a8ff	433	}
bogdanm	0:9b334a45a8ff	434	}
bogdanm	0:9b334a45a8ff	435	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
bogdanm	0:9b334a45a8ff	436	{
bogdanm	0:9b334a45a8ff	437	/* Receiving Process */
bogdanm	0:9b334a45a8ff	438	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
bogdanm	0:9b334a45a8ff	439	{
bogdanm	0:9b334a45a8ff	440	if (hqspi->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	441	{
bogdanm	0:9b334a45a8ff	442	/* Read the FIFO until it is empty */
bogdanm	0:9b334a45a8ff	443	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
bogdanm	0:9b334a45a8ff	444	hqspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	445	}
bogdanm	0:9b334a45a8ff	446	else
bogdanm	0:9b334a45a8ff	447	{
bogdanm	0:9b334a45a8ff	448	/* All data have been received for the transfer */
bogdanm	0:9b334a45a8ff	449	break;
bogdanm	0:9b334a45a8ff	450	}
bogdanm	0:9b334a45a8ff	451	}
bogdanm	0:9b334a45a8ff	452	}
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/* FIFO Threshold callback */
bogdanm	0:9b334a45a8ff	455	HAL_QSPI_FifoThresholdCallback(hqspi);
bogdanm	0:9b334a45a8ff	456	}
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	/* QSPI Transfer Complete interrupt occurred -------------------------------*/
bogdanm	0:9b334a45a8ff	459	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	460	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	461
bogdanm	0:9b334a45a8ff	462	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	463	{
bogdanm	0:9b334a45a8ff	464	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	465	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	466
bogdanm	0:9b334a45a8ff	467	/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
bogdanm	0:9b334a45a8ff	468	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470	/* Transfer complete callback */
bogdanm	0:9b334a45a8ff	471	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
bogdanm	0:9b334a45a8ff	472	{
bogdanm	0:9b334a45a8ff	473	/* Clear Busy bit */
bogdanm	0:9b334a45a8ff	474	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	475
bogdanm	0:9b334a45a8ff	476	/* TX Complete callback */
bogdanm	0:9b334a45a8ff	477	HAL_QSPI_TxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	478	}
bogdanm	0:9b334a45a8ff	479	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
bogdanm	0:9b334a45a8ff	480	{
bogdanm	0:9b334a45a8ff	481	data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	482	while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
bogdanm	0:9b334a45a8ff	483	{
bogdanm	0:9b334a45a8ff	484	if (hqspi->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	485	{
bogdanm	0:9b334a45a8ff	486	/* Read the last data received in the FIFO until it is empty */
bogdanm	0:9b334a45a8ff	487	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
bogdanm	0:9b334a45a8ff	488	hqspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	489	}
bogdanm	0:9b334a45a8ff	490	else
bogdanm	0:9b334a45a8ff	491	{
bogdanm	0:9b334a45a8ff	492	/* All data have been received for the transfer */
bogdanm	0:9b334a45a8ff	493	break;
bogdanm	0:9b334a45a8ff	494	}
bogdanm	0:9b334a45a8ff	495	}
bogdanm	0:9b334a45a8ff	496
bogdanm	0:9b334a45a8ff	497	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
bogdanm	0:9b334a45a8ff	498	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	499
bogdanm	0:9b334a45a8ff	500	/* RX Complete callback */
bogdanm	0:9b334a45a8ff	501	HAL_QSPI_RxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	502	}
bogdanm	0:9b334a45a8ff	503	else if(hqspi->State == HAL_QSPI_STATE_BUSY)
bogdanm	0:9b334a45a8ff	504	{
bogdanm	0:9b334a45a8ff	505	/* Command Complete callback */
bogdanm	0:9b334a45a8ff	506	HAL_QSPI_CmdCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	507	}
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509	/* Change state of QSPI */
bogdanm	0:9b334a45a8ff	510	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	511	}
bogdanm	0:9b334a45a8ff	512
bogdanm	0:9b334a45a8ff	513	/* QSPI Status Match interrupt occurred ------------------------------------*/
bogdanm	0:9b334a45a8ff	514	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
bogdanm	0:9b334a45a8ff	515	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	518	{
bogdanm	0:9b334a45a8ff	519	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	520	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
bogdanm	0:9b334a45a8ff	521
bogdanm	0:9b334a45a8ff	522	/* Check if the automatic poll mode stop is activated */
bogdanm	0:9b334a45a8ff	523	if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
bogdanm	0:9b334a45a8ff	524	{
bogdanm	0:9b334a45a8ff	525	/* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
bogdanm	0:9b334a45a8ff	526	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_FT \| QSPI_IT_TE);
bogdanm	0:9b334a45a8ff	527
bogdanm	0:9b334a45a8ff	528	/* Change state of QSPI */
bogdanm	0:9b334a45a8ff	529	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	530	}
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	/* Status match callback */
bogdanm	0:9b334a45a8ff	533	HAL_QSPI_StatusMatchCallback(hqspi);
bogdanm	0:9b334a45a8ff	534	}
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	/* QSPI Transfer Error interrupt occurred ----------------------------------*/
bogdanm	0:9b334a45a8ff	537	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
bogdanm	0:9b334a45a8ff	538	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
bogdanm	0:9b334a45a8ff	539
bogdanm	0:9b334a45a8ff	540	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	541	{
bogdanm	0:9b334a45a8ff	542	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	543	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545	/* Disable all the QSPI Interrupts */
bogdanm	0:9b334a45a8ff	546	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
bogdanm	0:9b334a45a8ff	547
bogdanm	0:9b334a45a8ff	548	/* Set error code */
bogdanm	0:9b334a45a8ff	549	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TRANSFER;
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551	/* Change state of QSPI */
bogdanm	0:9b334a45a8ff	552	hqspi->State = HAL_QSPI_STATE_ERROR;
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	/* Error callback */
bogdanm	0:9b334a45a8ff	555	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	556	}
bogdanm	0:9b334a45a8ff	557
bogdanm	0:9b334a45a8ff	558	/* QSPI Time out interrupt occurred -----------------------------------------*/
bogdanm	0:9b334a45a8ff	559	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
bogdanm	0:9b334a45a8ff	560	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
bogdanm	0:9b334a45a8ff	561
bogdanm	0:9b334a45a8ff	562	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	563	{
bogdanm	0:9b334a45a8ff	564	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	565	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	/* Time out callback */
bogdanm	0:9b334a45a8ff	568	HAL_QSPI_TimeOutCallback(hqspi);
bogdanm	0:9b334a45a8ff	569	}
bogdanm	0:9b334a45a8ff	570	}
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	/**
bogdanm	0:9b334a45a8ff	573	* @brief Sets the command configuration.
bogdanm	0:9b334a45a8ff	574	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	575	* @param cmd : structure that contains the command configuration information
bogdanm	0:9b334a45a8ff	576	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	577	* @note This function is used only in Indirect Read or Write Modes
bogdanm	0:9b334a45a8ff	578	* @retval HAL status
bogdanm	0:9b334a45a8ff	579	*/
bogdanm	0:9b334a45a8ff	580	HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	581	{
bogdanm	0:9b334a45a8ff	582	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584	/* Check the parameters */
bogdanm	0:9b334a45a8ff	585	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	586	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	587	{
bogdanm	0:9b334a45a8ff	588	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	589	}
bogdanm	0:9b334a45a8ff	590
bogdanm	0:9b334a45a8ff	591	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	592	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	593	{
bogdanm	0:9b334a45a8ff	594	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	595	}
bogdanm	0:9b334a45a8ff	596
bogdanm	0:9b334a45a8ff	597	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	598	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	599	{
bogdanm	0:9b334a45a8ff	600	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	601	}
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	604	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	605
bogdanm	0:9b334a45a8ff	606	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	607	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	608	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	/* Process locked */
bogdanm	0:9b334a45a8ff	611	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	612
bogdanm	0:9b334a45a8ff	613	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	614	{
bogdanm	0:9b334a45a8ff	615	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	618	hqspi->State = HAL_QSPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	619
bogdanm	0:9b334a45a8ff	620	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	621	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
bogdanm	0:9b334a45a8ff	622
bogdanm	0:9b334a45a8ff	623	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	624	{
bogdanm	0:9b334a45a8ff	625	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	626	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	627
bogdanm	0:9b334a45a8ff	628	if (cmd->DataMode == QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	629	{
bogdanm	0:9b334a45a8ff	630	/* When there is no data phase, the transfer start as soon as the configuration is done
bogdanm	0:9b334a45a8ff	631	so wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	632	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	633	{
bogdanm	0:9b334a45a8ff	634	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	635	}
bogdanm	0:9b334a45a8ff	636	else
bogdanm	0:9b334a45a8ff	637	{
bogdanm	0:9b334a45a8ff	638	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	641	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	642	}
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	}
bogdanm	0:9b334a45a8ff	645	else
bogdanm	0:9b334a45a8ff	646	{
bogdanm	0:9b334a45a8ff	647	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	648	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	649	}
bogdanm	0:9b334a45a8ff	650	}
bogdanm	0:9b334a45a8ff	651	}
bogdanm	0:9b334a45a8ff	652	else
bogdanm	0:9b334a45a8ff	653	{
bogdanm	0:9b334a45a8ff	654	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	655	}
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657	/* Process unlocked */
bogdanm	0:9b334a45a8ff	658	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	659
bogdanm	0:9b334a45a8ff	660	/* Return function status */
bogdanm	0:9b334a45a8ff	661	return status;
bogdanm	0:9b334a45a8ff	662	}
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	/**
bogdanm	0:9b334a45a8ff	665	* @brief Sets the command configuration in interrupt mode.
bogdanm	0:9b334a45a8ff	666	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	667	* @param cmd : structure that contains the command configuration information
bogdanm	0:9b334a45a8ff	668	* @note This function is used only in Indirect Read or Write Modes
bogdanm	0:9b334a45a8ff	669	* @retval HAL status
bogdanm	0:9b334a45a8ff	670	*/
bogdanm	0:9b334a45a8ff	671	HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd)
bogdanm	0:9b334a45a8ff	672	{
bogdanm	0:9b334a45a8ff	673	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	674
bogdanm	0:9b334a45a8ff	675	/* Check the parameters */
bogdanm	0:9b334a45a8ff	676	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	677	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	678	{
bogdanm	0:9b334a45a8ff	679	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	680	}
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	683	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	684	{
bogdanm	0:9b334a45a8ff	685	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	686	}
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	689	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	690	{
bogdanm	0:9b334a45a8ff	691	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	692	}
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	695	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	698	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	699	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	700
bogdanm	0:9b334a45a8ff	701	/* Process locked */
bogdanm	0:9b334a45a8ff	702	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	705	{
bogdanm	0:9b334a45a8ff	706	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	709	hqspi->State = HAL_QSPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	710
bogdanm	0:9b334a45a8ff	711	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	712	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	713
bogdanm	0:9b334a45a8ff	714	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	715	{
bogdanm	0:9b334a45a8ff	716	if (cmd->DataMode == QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	717	{
bogdanm	0:9b334a45a8ff	718	/* When there is no data phase, the transfer start as soon as the configuration is done
bogdanm	0:9b334a45a8ff	719	so activate TC and TE interrupts */
bogdanm	0:9b334a45a8ff	720	/* Enable the QSPI Transfer Error Interrupt */
bogdanm	0:9b334a45a8ff	721	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	722	}
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	725	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727	if (cmd->DataMode != QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	728	{
bogdanm	0:9b334a45a8ff	729	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	730	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	731	}
bogdanm	0:9b334a45a8ff	732	}
bogdanm	0:9b334a45a8ff	733	}
bogdanm	0:9b334a45a8ff	734	else
bogdanm	0:9b334a45a8ff	735	{
bogdanm	0:9b334a45a8ff	736	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	737	}
bogdanm	0:9b334a45a8ff	738
bogdanm	0:9b334a45a8ff	739	/* Process unlocked */
bogdanm	0:9b334a45a8ff	740	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	741
bogdanm	0:9b334a45a8ff	742	/* Return function status */
bogdanm	0:9b334a45a8ff	743	return status;
bogdanm	0:9b334a45a8ff	744	}
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	/**
bogdanm	0:9b334a45a8ff	747	* @brief Transmit an amount of data in blocking mode.
bogdanm	0:9b334a45a8ff	748	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	749	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	750	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	751	* @note This function is used only in Indirect Write Mode
bogdanm	0:9b334a45a8ff	752	* @retval HAL status
bogdanm	0:9b334a45a8ff	753	*/
bogdanm	0:9b334a45a8ff	754	HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	755	{
bogdanm	0:9b334a45a8ff	756	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	757	__IO uint32_t *data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	758
bogdanm	0:9b334a45a8ff	759	/* Process locked */
bogdanm	0:9b334a45a8ff	760	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	763	{
bogdanm	0:9b334a45a8ff	764	if(pData != NULL )
bogdanm	0:9b334a45a8ff	765	{
bogdanm	0:9b334a45a8ff	766	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	767
bogdanm	0:9b334a45a8ff	768	/* Update state */
bogdanm	0:9b334a45a8ff	769	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
bogdanm	0:9b334a45a8ff	770
bogdanm	0:9b334a45a8ff	771	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	772	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	773	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	774	hqspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	/* Configure QSPI: CCR register with functional as indirect write */
bogdanm	0:9b334a45a8ff	777	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	778
bogdanm	0:9b334a45a8ff	779	while(hqspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	780	{
bogdanm	0:9b334a45a8ff	781	/* Wait until FT flag is set to send data */
bogdanm	0:9b334a45a8ff	782	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	783	{
bogdanm	0:9b334a45a8ff	784	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	785	break;
bogdanm	0:9b334a45a8ff	786	}
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
bogdanm	0:9b334a45a8ff	789	hqspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	790	}
bogdanm	0:9b334a45a8ff	791
bogdanm	0:9b334a45a8ff	792	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	793	{
bogdanm	0:9b334a45a8ff	794	/* Wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	795	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	796	{
bogdanm	0:9b334a45a8ff	797	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	798	}
bogdanm	0:9b334a45a8ff	799	else
bogdanm	0:9b334a45a8ff	800	{
bogdanm	0:9b334a45a8ff	801	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	802	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	803
bogdanm	0:9b334a45a8ff	804	/* Clear Busy bit */
bogdanm	0:9b334a45a8ff	805	status = HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	806	}
bogdanm	0:9b334a45a8ff	807	}
bogdanm	0:9b334a45a8ff	808
bogdanm	0:9b334a45a8ff	809	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	810	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	811	}
bogdanm	0:9b334a45a8ff	812	else
bogdanm	0:9b334a45a8ff	813	{
bogdanm	0:9b334a45a8ff	814	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	815	}
bogdanm	0:9b334a45a8ff	816	}
bogdanm	0:9b334a45a8ff	817	else
bogdanm	0:9b334a45a8ff	818	{
bogdanm	0:9b334a45a8ff	819	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	820	}
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822	/* Process unlocked */
bogdanm	0:9b334a45a8ff	823	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	return status;
bogdanm	0:9b334a45a8ff	826	}
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828
bogdanm	0:9b334a45a8ff	829	/**
bogdanm	0:9b334a45a8ff	830	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	831	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	832	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	833	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	834	* @note This function is used only in Indirect Read Mode
bogdanm	0:9b334a45a8ff	835	* @retval HAL status
bogdanm	0:9b334a45a8ff	836	*/
bogdanm	0:9b334a45a8ff	837	HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	838	{
bogdanm	0:9b334a45a8ff	839	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	840	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
bogdanm	0:9b334a45a8ff	841	__IO uint32_t *data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	842
bogdanm	0:9b334a45a8ff	843	/* Process locked */
bogdanm	0:9b334a45a8ff	844	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	847	{
bogdanm	0:9b334a45a8ff	848	if(pData != NULL )
bogdanm	0:9b334a45a8ff	849	{
bogdanm	0:9b334a45a8ff	850	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	/* Update state */
bogdanm	0:9b334a45a8ff	853	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
bogdanm	0:9b334a45a8ff	854
bogdanm	0:9b334a45a8ff	855	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	856	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	857	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	858	hqspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	/* Configure QSPI: CCR register with functional as indirect read */
bogdanm	0:9b334a45a8ff	861	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
bogdanm	0:9b334a45a8ff	862
bogdanm	0:9b334a45a8ff	863	/* Start the transfer by re-writing the address in AR register */
bogdanm	0:9b334a45a8ff	864	WRITE_REG(hqspi->Instance->AR, addr_reg);
bogdanm	0:9b334a45a8ff	865
bogdanm	0:9b334a45a8ff	866	while(hqspi->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	867	{
bogdanm	0:9b334a45a8ff	868	/* Wait until FT or TC flag is set to read received data */
bogdanm	0:9b334a45a8ff	869	if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT \| QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	870	{
bogdanm	0:9b334a45a8ff	871	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	872	break;
bogdanm	0:9b334a45a8ff	873	}
bogdanm	0:9b334a45a8ff	874
bogdanm	0:9b334a45a8ff	875	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
bogdanm	0:9b334a45a8ff	876	hqspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	877	}
bogdanm	0:9b334a45a8ff	878
bogdanm	0:9b334a45a8ff	879	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	880	{
bogdanm	0:9b334a45a8ff	881	/* Wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	882	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	883	{
bogdanm	0:9b334a45a8ff	884	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	885	}
bogdanm	0:9b334a45a8ff	886	else
bogdanm	0:9b334a45a8ff	887	{
bogdanm	0:9b334a45a8ff	888	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	889	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	890
bogdanm	0:9b334a45a8ff	891	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
bogdanm	0:9b334a45a8ff	892	status = HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	893	}
bogdanm	0:9b334a45a8ff	894	}
bogdanm	0:9b334a45a8ff	895
bogdanm	0:9b334a45a8ff	896	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	897	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	898	}
bogdanm	0:9b334a45a8ff	899	else
bogdanm	0:9b334a45a8ff	900	{
bogdanm	0:9b334a45a8ff	901	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	902	}
bogdanm	0:9b334a45a8ff	903	}
bogdanm	0:9b334a45a8ff	904	else
bogdanm	0:9b334a45a8ff	905	{
bogdanm	0:9b334a45a8ff	906	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	907	}
bogdanm	0:9b334a45a8ff	908
bogdanm	0:9b334a45a8ff	909	/* Process unlocked */
bogdanm	0:9b334a45a8ff	910	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	911
bogdanm	0:9b334a45a8ff	912	return status;
bogdanm	0:9b334a45a8ff	913	}
bogdanm	0:9b334a45a8ff	914
bogdanm	0:9b334a45a8ff	915	/**
bogdanm	0:9b334a45a8ff	916	* @brief Send an amount of data in interrupt mode
bogdanm	0:9b334a45a8ff	917	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	918	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	919	* @note This function is used only in Indirect Write Mode
bogdanm	0:9b334a45a8ff	920	* @retval HAL status
bogdanm	0:9b334a45a8ff	921	*/
bogdanm	0:9b334a45a8ff	922	HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	923	{
bogdanm	0:9b334a45a8ff	924	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	925
bogdanm	0:9b334a45a8ff	926	/* Process locked */
bogdanm	0:9b334a45a8ff	927	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	930	{
bogdanm	0:9b334a45a8ff	931	if(pData != NULL )
bogdanm	0:9b334a45a8ff	932	{
bogdanm	0:9b334a45a8ff	933	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	/* Update state */
bogdanm	0:9b334a45a8ff	936	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	939	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	940	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	941	hqspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	942
bogdanm	0:9b334a45a8ff	943	/* Configure QSPI: CCR register with functional as indirect write */
bogdanm	0:9b334a45a8ff	944	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	945
bogdanm	0:9b334a45a8ff	946	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
bogdanm	0:9b334a45a8ff	947	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	948
bogdanm	0:9b334a45a8ff	949	}
bogdanm	0:9b334a45a8ff	950	else
bogdanm	0:9b334a45a8ff	951	{
bogdanm	0:9b334a45a8ff	952	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	953	}
bogdanm	0:9b334a45a8ff	954	}
bogdanm	0:9b334a45a8ff	955	else
bogdanm	0:9b334a45a8ff	956	{
bogdanm	0:9b334a45a8ff	957	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	958	}
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	/* Process unlocked */
bogdanm	0:9b334a45a8ff	961	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	return status;
bogdanm	0:9b334a45a8ff	964	}
bogdanm	0:9b334a45a8ff	965
bogdanm	0:9b334a45a8ff	966	/**
bogdanm	0:9b334a45a8ff	967	* @brief Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	968	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	969	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	970	* @note This function is used only in Indirect Read Mode
bogdanm	0:9b334a45a8ff	971	* @retval HAL status
bogdanm	0:9b334a45a8ff	972	*/
bogdanm	0:9b334a45a8ff	973	HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	974	{
bogdanm	0:9b334a45a8ff	975	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	976	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
bogdanm	0:9b334a45a8ff	977
bogdanm	0:9b334a45a8ff	978	/* Process locked */
bogdanm	0:9b334a45a8ff	979	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	980
bogdanm	0:9b334a45a8ff	981	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	982	{
bogdanm	0:9b334a45a8ff	983	if(pData != NULL )
bogdanm	0:9b334a45a8ff	984	{
bogdanm	0:9b334a45a8ff	985	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	986
bogdanm	0:9b334a45a8ff	987	/* Update state */
bogdanm	0:9b334a45a8ff	988	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
bogdanm	0:9b334a45a8ff	989
bogdanm	0:9b334a45a8ff	990	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	991	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	992	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	993	hqspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995	/* Configure QSPI: CCR register with functional as indirect read */
bogdanm	0:9b334a45a8ff	996	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	/* Start the transfer by re-writing the address in AR register */
bogdanm	0:9b334a45a8ff	999	WRITE_REG(hqspi->Instance->AR, addr_reg);
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
bogdanm	0:9b334a45a8ff	1002	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	1003	}
bogdanm	0:9b334a45a8ff	1004	else
bogdanm	0:9b334a45a8ff	1005	{
bogdanm	0:9b334a45a8ff	1006	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1007	}
bogdanm	0:9b334a45a8ff	1008	}
bogdanm	0:9b334a45a8ff	1009	else
bogdanm	0:9b334a45a8ff	1010	{
bogdanm	0:9b334a45a8ff	1011	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1012	}
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1015	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	return status;
bogdanm	0:9b334a45a8ff	1018	}
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	/**
bogdanm	0:9b334a45a8ff	1021	* @brief Sends an amount of data in non blocking mode with DMA.
bogdanm	0:9b334a45a8ff	1022	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1023	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1024	* @note This function is used only in Indirect Write Mode
bogdanm	0:9b334a45a8ff	1025	* @retval HAL status
bogdanm	0:9b334a45a8ff	1026	*/
bogdanm	0:9b334a45a8ff	1027	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	1028	{
bogdanm	0:9b334a45a8ff	1029	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	1030	uint32_t *tmp;
bogdanm	0:9b334a45a8ff	1031
bogdanm	0:9b334a45a8ff	1032	/* Process locked */
bogdanm	0:9b334a45a8ff	1033	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1036	{
bogdanm	0:9b334a45a8ff	1037	if(pData != NULL )
bogdanm	0:9b334a45a8ff	1038	{
bogdanm	0:9b334a45a8ff	1039	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1040
bogdanm	0:9b334a45a8ff	1041	/* Update state */
bogdanm	0:9b334a45a8ff	1042	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
bogdanm	0:9b334a45a8ff	1043
bogdanm	0:9b334a45a8ff	1044	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	1045	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1046	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1047	hqspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	/* Configure QSPI: CCR register with functional mode as indirect write */
bogdanm	0:9b334a45a8ff	1050	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	1051
bogdanm	0:9b334a45a8ff	1052	/* Set the QSPI DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1053	hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
bogdanm	0:9b334a45a8ff	1054
bogdanm	0:9b334a45a8ff	1055	/* Set the QSPI DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1056	hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
bogdanm	0:9b334a45a8ff	1057
bogdanm	0:9b334a45a8ff	1058	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1059	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	/* Configure the direction of the DMA */
bogdanm	0:9b334a45a8ff	1062	hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
bogdanm	0:9b334a45a8ff	1063	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
bogdanm	0:9b334a45a8ff	1064
bogdanm	0:9b334a45a8ff	1065	/* Enable the QSPI transmit DMA Channel */
bogdanm	0:9b334a45a8ff	1066	tmp = (uint32_t*)&pData;
bogdanm	0:9b334a45a8ff	1067	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
bogdanm	0:9b334a45a8ff	1068
bogdanm	0:9b334a45a8ff	1069	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1070	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1071	}
bogdanm	0:9b334a45a8ff	1072	else
bogdanm	0:9b334a45a8ff	1073	{
bogdanm	0:9b334a45a8ff	1074	status = HAL_OK;
bogdanm	0:9b334a45a8ff	1075	}
bogdanm	0:9b334a45a8ff	1076	}
bogdanm	0:9b334a45a8ff	1077	else
bogdanm	0:9b334a45a8ff	1078	{
bogdanm	0:9b334a45a8ff	1079	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1080	}
bogdanm	0:9b334a45a8ff	1081
bogdanm	0:9b334a45a8ff	1082	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1083	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1084
bogdanm	0:9b334a45a8ff	1085	return status;
bogdanm	0:9b334a45a8ff	1086	}
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	/**
bogdanm	0:9b334a45a8ff	1089	* @brief Receives an amount of data in non blocking mode with DMA.
bogdanm	0:9b334a45a8ff	1090	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1091	* @param pData: pointer to data buffer.
bogdanm	0:9b334a45a8ff	1092	* @note This function is used only in Indirect Read Mode
bogdanm	0:9b334a45a8ff	1093	* @retval HAL status
bogdanm	0:9b334a45a8ff	1094	*/
bogdanm	0:9b334a45a8ff	1095	HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	1096	{
bogdanm	0:9b334a45a8ff	1097	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	1098	uint32_t *tmp;
bogdanm	0:9b334a45a8ff	1099	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	/* Process locked */
bogdanm	0:9b334a45a8ff	1102	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1103
bogdanm	0:9b334a45a8ff	1104	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1105	{
bogdanm	0:9b334a45a8ff	1106	if(pData != NULL )
bogdanm	0:9b334a45a8ff	1107	{
bogdanm	0:9b334a45a8ff	1108	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1109
bogdanm	0:9b334a45a8ff	1110	/* Update state */
bogdanm	0:9b334a45a8ff	1111	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
bogdanm	0:9b334a45a8ff	1112
bogdanm	0:9b334a45a8ff	1113	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	1114	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1115	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1116	hqspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1117
bogdanm	0:9b334a45a8ff	1118	/* Set the QSPI DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1119	hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
bogdanm	0:9b334a45a8ff	1120
bogdanm	0:9b334a45a8ff	1121	/* Set the QSPI DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1122	hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1125	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
bogdanm	0:9b334a45a8ff	1126
bogdanm	0:9b334a45a8ff	1127	/* Configure the direction of the DMA */
bogdanm	0:9b334a45a8ff	1128	hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
bogdanm	0:9b334a45a8ff	1129	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
bogdanm	0:9b334a45a8ff	1130
bogdanm	0:9b334a45a8ff	1131	/* Enable the DMA Channel */
bogdanm	0:9b334a45a8ff	1132	tmp = (uint32_t*)&pData;
bogdanm	0:9b334a45a8ff	1133	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)tmp, hqspi->RxXferSize);
bogdanm	0:9b334a45a8ff	1134
bogdanm	0:9b334a45a8ff	1135	/* Configure QSPI: CCR register with functional as indirect read */
bogdanm	0:9b334a45a8ff	1136	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
bogdanm	0:9b334a45a8ff	1137
bogdanm	0:9b334a45a8ff	1138	/* Start the transfer by re-writing the address in AR register */
bogdanm	0:9b334a45a8ff	1139	WRITE_REG(hqspi->Instance->AR, addr_reg);
bogdanm	0:9b334a45a8ff	1140
bogdanm	0:9b334a45a8ff	1141	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1142	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1143	}
bogdanm	0:9b334a45a8ff	1144	else
bogdanm	0:9b334a45a8ff	1145	{
bogdanm	0:9b334a45a8ff	1146	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1147	}
bogdanm	0:9b334a45a8ff	1148	}
bogdanm	0:9b334a45a8ff	1149	else
bogdanm	0:9b334a45a8ff	1150	{
bogdanm	0:9b334a45a8ff	1151	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1152	}
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1155	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	return status;
bogdanm	0:9b334a45a8ff	1158	}
bogdanm	0:9b334a45a8ff	1159
bogdanm	0:9b334a45a8ff	1160	/**
bogdanm	0:9b334a45a8ff	1161	* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
bogdanm	0:9b334a45a8ff	1162	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1163	* @param cmd: structure that contains the command configuration information.
bogdanm	0:9b334a45a8ff	1164	* @param cfg: structure that contains the polling configuration information.
bogdanm	0:9b334a45a8ff	1165	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	1166	* @note This function is used only in Automatic Polling Mode
bogdanm	0:9b334a45a8ff	1167	* @retval HAL status
bogdanm	0:9b334a45a8ff	1168	*/
bogdanm	0:9b334a45a8ff	1169	HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1170	{
bogdanm	0:9b334a45a8ff	1171	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1172
bogdanm	0:9b334a45a8ff	1173	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1174	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	1175	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1176	{
mbed_official	83:a036322b8637	1177	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	1178	}
mbed_official	83:a036322b8637	1179
bogdanm	0:9b334a45a8ff	1180	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	1181	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1182	{
bogdanm	0:9b334a45a8ff	1183	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	1184	}
mbed_official	83:a036322b8637	1185
bogdanm	0:9b334a45a8ff	1186	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	1187	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1188	{
bogdanm	0:9b334a45a8ff	1189	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	1190	}
mbed_official	83:a036322b8637	1191
bogdanm	0:9b334a45a8ff	1192	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	1193	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
mbed_official	83:a036322b8637	1194
bogdanm	0:9b334a45a8ff	1195	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	1196	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	1197	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
mbed_official	83:a036322b8637	1198
bogdanm	0:9b334a45a8ff	1199	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
bogdanm	0:9b334a45a8ff	1200	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
bogdanm	0:9b334a45a8ff	1201	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	/* Process locked */
bogdanm	0:9b334a45a8ff	1204	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1207	{
mbed_official	83:a036322b8637	1208
mbed_official	83:a036322b8637	1209	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1210
mbed_official	83:a036322b8637	1211	/* Update state */
mbed_official	83:a036322b8637	1212	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
bogdanm	0:9b334a45a8ff	1213
mbed_official	83:a036322b8637	1214	/* Wait till BUSY flag reset */
mbed_official	83:a036322b8637	1215	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
bogdanm	0:9b334a45a8ff	1216
mbed_official	83:a036322b8637	1217	if (status == HAL_OK)
mbed_official	83:a036322b8637	1218	{
mbed_official	83:a036322b8637	1219	/* Configure QSPI: PSMAR register with the status match value */
mbed_official	83:a036322b8637	1220	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
mbed_official	83:a036322b8637	1221
mbed_official	83:a036322b8637	1222	/* Configure QSPI: PSMKR register with the status mask value */
mbed_official	83:a036322b8637	1223	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
mbed_official	83:a036322b8637	1224
mbed_official	83:a036322b8637	1225	/* Configure QSPI: PIR register with the interval value */
mbed_official	83:a036322b8637	1226	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
mbed_official	83:a036322b8637	1227
mbed_official	83:a036322b8637	1228	/* Configure QSPI: CR register with Match mode and Automatic stop enabled
mbed_official	83:a036322b8637	1229	(otherwise there will be an infinite loop in blocking mode) */
mbed_official	83:a036322b8637	1230	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
mbed_official	83:a036322b8637	1231	(cfg->MatchMode \| QSPI_AUTOMATIC_STOP_ENABLE));
mbed_official	83:a036322b8637	1232
mbed_official	83:a036322b8637	1233	/* Call the configuration function */
mbed_official	83:a036322b8637	1234	cmd->NbData = cfg->StatusBytesSize;
mbed_official	83:a036322b8637	1235	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
mbed_official	83:a036322b8637	1236
mbed_official	83:a036322b8637	1237	/* Wait until SM flag is set to go back in idle state */
mbed_official	83:a036322b8637	1238	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
mbed_official	83:a036322b8637	1239	{
mbed_official	83:a036322b8637	1240	status = HAL_TIMEOUT;
mbed_official	83:a036322b8637	1241	}
mbed_official	83:a036322b8637	1242	else
mbed_official	83:a036322b8637	1243	{
mbed_official	83:a036322b8637	1244	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
mbed_official	83:a036322b8637	1245
mbed_official	83:a036322b8637	1246	/* Update state */
mbed_official	83:a036322b8637	1247	hqspi->State = HAL_QSPI_STATE_READY;
mbed_official	83:a036322b8637	1248	}
bogdanm	0:9b334a45a8ff	1249	}
bogdanm	0:9b334a45a8ff	1250	}
bogdanm	0:9b334a45a8ff	1251	else
bogdanm	0:9b334a45a8ff	1252	{
bogdanm	0:9b334a45a8ff	1253	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1254	}
bogdanm	0:9b334a45a8ff	1255	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1256	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1257
bogdanm	0:9b334a45a8ff	1258	/* Return function status */
bogdanm	0:9b334a45a8ff	1259	return status;
bogdanm	0:9b334a45a8ff	1260	}
bogdanm	0:9b334a45a8ff	1261
bogdanm	0:9b334a45a8ff	1262	/**
mbed_official	83:a036322b8637	1263	* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
mbed_official	83:a036322b8637	1264	* @param hqspi: QSPI handle
mbed_official	83:a036322b8637	1265	* @param cmd: structure that contains the command configuration information.
mbed_official	83:a036322b8637	1266	* @param cfg: structure that contains the polling configuration information.
mbed_official	83:a036322b8637	1267	* @note This function is used only in Automatic Polling Mode
mbed_official	83:a036322b8637	1268	* @retval HAL status
mbed_official	83:a036322b8637	1269	*/
bogdanm	0:9b334a45a8ff	1270	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg)
bogdanm	0:9b334a45a8ff	1271	{
bogdanm	0:9b334a45a8ff	1272	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1275	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	1276	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1277	{
bogdanm	0:9b334a45a8ff	1278	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	1279	}
mbed_official	83:a036322b8637	1280
bogdanm	0:9b334a45a8ff	1281	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	1282	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1283	{
bogdanm	0:9b334a45a8ff	1284	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	1285	}
mbed_official	83:a036322b8637	1286
bogdanm	0:9b334a45a8ff	1287	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	1288	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1289	{
bogdanm	0:9b334a45a8ff	1290	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	1291	}
mbed_official	83:a036322b8637	1292
bogdanm	0:9b334a45a8ff	1293	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	1294	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
mbed_official	83:a036322b8637	1295
bogdanm	0:9b334a45a8ff	1296	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	1297	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	1298	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
mbed_official	83:a036322b8637	1299
bogdanm	0:9b334a45a8ff	1300	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
bogdanm	0:9b334a45a8ff	1301	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
bogdanm	0:9b334a45a8ff	1302	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
bogdanm	0:9b334a45a8ff	1303	assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
bogdanm	0:9b334a45a8ff	1304
bogdanm	0:9b334a45a8ff	1305	/* Process locked */
bogdanm	0:9b334a45a8ff	1306	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1307
mbed_official	83:a036322b8637	1308	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1309	{
bogdanm	0:9b334a45a8ff	1310	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/* Update state */
bogdanm	0:9b334a45a8ff	1313	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	1316	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	1317
mbed_official	83:a036322b8637	1318	if (status == HAL_OK)
mbed_official	83:a036322b8637	1319	{
mbed_official	83:a036322b8637	1320	/* Configure QSPI: PSMAR register with the status match value */
mbed_official	83:a036322b8637	1321	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
mbed_official	83:a036322b8637	1322
mbed_official	83:a036322b8637	1323	/* Configure QSPI: PSMKR register with the status mask value */
mbed_official	83:a036322b8637	1324	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
mbed_official	83:a036322b8637	1325
mbed_official	83:a036322b8637	1326	/* Configure QSPI: PIR register with the interval value */
mbed_official	83:a036322b8637	1327	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
mbed_official	83:a036322b8637	1328
mbed_official	83:a036322b8637	1329	/* Configure QSPI: CR register with Match mode and Automatic stop mode */
mbed_official	83:a036322b8637	1330	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
mbed_official	83:a036322b8637	1331	(cfg->MatchMode \| cfg->AutomaticStop));
mbed_official	83:a036322b8637	1332
mbed_official	83:a036322b8637	1333	/* Clear interrupt */
mbed_official	83:a036322b8637	1334	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_SM);
mbed_official	83:a036322b8637	1335
mbed_official	83:a036322b8637	1336	/* Enable the QSPI Transfer Error and status match Interrupt */
mbed_official	83:a036322b8637	1337	__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
mbed_official	83:a036322b8637	1338
mbed_official	83:a036322b8637	1339	/* Call the configuration function */
mbed_official	83:a036322b8637	1340	cmd->NbData = cfg->StatusBytesSize;
mbed_official	83:a036322b8637	1341	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
mbed_official	83:a036322b8637	1342	}
bogdanm	0:9b334a45a8ff	1343	}
bogdanm	0:9b334a45a8ff	1344	else
bogdanm	0:9b334a45a8ff	1345	{
bogdanm	0:9b334a45a8ff	1346	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1347	}
mbed_official	83:a036322b8637	1348
bogdanm	0:9b334a45a8ff	1349	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1350	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	/* Return function status */
bogdanm	0:9b334a45a8ff	1353	return status;
bogdanm	0:9b334a45a8ff	1354	}
bogdanm	0:9b334a45a8ff	1355
bogdanm	0:9b334a45a8ff	1356	/**
bogdanm	0:9b334a45a8ff	1357	* @brief Configure the Memory Mapped mode.
bogdanm	0:9b334a45a8ff	1358	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1359	* @param cmd: structure that contains the command configuration information.
bogdanm	0:9b334a45a8ff	1360	* @param cfg: structure that contains the memory mapped configuration information.
bogdanm	0:9b334a45a8ff	1361	* @note This function is used only in Memory mapped Mode
bogdanm	0:9b334a45a8ff	1362	* @retval HAL status
bogdanm	0:9b334a45a8ff	1363	*/
bogdanm	0:9b334a45a8ff	1364	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg)
bogdanm	0:9b334a45a8ff	1365	{
bogdanm	0:9b334a45a8ff	1366	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1369	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	1370	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1371	{
bogdanm	0:9b334a45a8ff	1372	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	1373	}
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	1376	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1377	{
bogdanm	0:9b334a45a8ff	1378	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	1379	}
bogdanm	0:9b334a45a8ff	1380
bogdanm	0:9b334a45a8ff	1381	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	1382	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1383	{
bogdanm	0:9b334a45a8ff	1384	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	1385	}
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	1388	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	1389
bogdanm	0:9b334a45a8ff	1390	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	1391	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	1392	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	1393
bogdanm	0:9b334a45a8ff	1394	assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
bogdanm	0:9b334a45a8ff	1395
bogdanm	0:9b334a45a8ff	1396	/* Process locked */
bogdanm	0:9b334a45a8ff	1397	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1398
bogdanm	0:9b334a45a8ff	1399	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1400	{
bogdanm	0:9b334a45a8ff	1401	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1402
bogdanm	0:9b334a45a8ff	1403	/* Update state */
bogdanm	0:9b334a45a8ff	1404	hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	1407	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	1410	{
bogdanm	0:9b334a45a8ff	1411	/* Configure QSPI: CR register with time out counter enable */
bogdanm	0:9b334a45a8ff	1412	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
bogdanm	0:9b334a45a8ff	1413
bogdanm	0:9b334a45a8ff	1414	if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
bogdanm	0:9b334a45a8ff	1415	{
bogdanm	0:9b334a45a8ff	1416	assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
bogdanm	0:9b334a45a8ff	1417
bogdanm	0:9b334a45a8ff	1418	/* Configure QSPI: LPTR register with the low-power time out value */
bogdanm	0:9b334a45a8ff	1419	WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	/* Enable the QSPI TimeOut Interrupt */
bogdanm	0:9b334a45a8ff	1422	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
bogdanm	0:9b334a45a8ff	1423	}
bogdanm	0:9b334a45a8ff	1424
bogdanm	0:9b334a45a8ff	1425	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	1426	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
bogdanm	0:9b334a45a8ff	1427
bogdanm	0:9b334a45a8ff	1428	}
bogdanm	0:9b334a45a8ff	1429	}
bogdanm	0:9b334a45a8ff	1430	else
bogdanm	0:9b334a45a8ff	1431	{
bogdanm	0:9b334a45a8ff	1432	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	}
bogdanm	0:9b334a45a8ff	1435
bogdanm	0:9b334a45a8ff	1436	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1437	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1438
bogdanm	0:9b334a45a8ff	1439	/* Return function status */
bogdanm	0:9b334a45a8ff	1440	return status;
bogdanm	0:9b334a45a8ff	1441	}
bogdanm	0:9b334a45a8ff	1442
bogdanm	0:9b334a45a8ff	1443	/**
bogdanm	0:9b334a45a8ff	1444	* @brief Transfer Error callbacks
bogdanm	0:9b334a45a8ff	1445	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1446	* @retval None
bogdanm	0:9b334a45a8ff	1447	*/
bogdanm	0:9b334a45a8ff	1448	__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1449	{
mbed_official	83:a036322b8637	1450	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1451	UNUSED(hqspi);
mbed_official	83:a036322b8637	1452
bogdanm	0:9b334a45a8ff	1453	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1454	the HAL_QSPI_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1455	*/
bogdanm	0:9b334a45a8ff	1456	}
bogdanm	0:9b334a45a8ff	1457
bogdanm	0:9b334a45a8ff	1458	/**
bogdanm	0:9b334a45a8ff	1459	* @brief Command completed callbacks.
bogdanm	0:9b334a45a8ff	1460	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1461	* @retval None
bogdanm	0:9b334a45a8ff	1462	*/
bogdanm	0:9b334a45a8ff	1463	__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1464	{
mbed_official	83:a036322b8637	1465	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1466	UNUSED(hqspi);
mbed_official	83:a036322b8637	1467
bogdanm	0:9b334a45a8ff	1468	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1469	the HAL_QSPI_CmdCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1470	*/
bogdanm	0:9b334a45a8ff	1471	}
bogdanm	0:9b334a45a8ff	1472
bogdanm	0:9b334a45a8ff	1473	/**
bogdanm	0:9b334a45a8ff	1474	* @brief Rx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1475	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1476	* @retval None
bogdanm	0:9b334a45a8ff	1477	*/
bogdanm	0:9b334a45a8ff	1478	__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1479	{
mbed_official	83:a036322b8637	1480	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1481	UNUSED(hqspi);
mbed_official	83:a036322b8637	1482
bogdanm	0:9b334a45a8ff	1483	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1484	the HAL_QSPI_RxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1485	*/
bogdanm	0:9b334a45a8ff	1486	}
bogdanm	0:9b334a45a8ff	1487
bogdanm	0:9b334a45a8ff	1488	/**
bogdanm	0:9b334a45a8ff	1489	* @brief Tx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1490	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1491	* @retval None
bogdanm	0:9b334a45a8ff	1492	*/
bogdanm	0:9b334a45a8ff	1493	__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1494	{
mbed_official	83:a036322b8637	1495	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1496	UNUSED(hqspi);
mbed_official	83:a036322b8637	1497
bogdanm	0:9b334a45a8ff	1498	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1499	the HAL_QSPI_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1500	*/
bogdanm	0:9b334a45a8ff	1501	}
bogdanm	0:9b334a45a8ff	1502
bogdanm	0:9b334a45a8ff	1503	/**
bogdanm	0:9b334a45a8ff	1504	* @brief Rx Half Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1505	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1506	* @retval None
bogdanm	0:9b334a45a8ff	1507	*/
bogdanm	0:9b334a45a8ff	1508	__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1509	{
mbed_official	83:a036322b8637	1510	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1511	UNUSED(hqspi);
mbed_official	83:a036322b8637	1512
bogdanm	0:9b334a45a8ff	1513	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1514	the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1515	*/
bogdanm	0:9b334a45a8ff	1516	}
bogdanm	0:9b334a45a8ff	1517
bogdanm	0:9b334a45a8ff	1518	/**
bogdanm	0:9b334a45a8ff	1519	* @brief Tx Half Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1520	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1521	* @retval None
bogdanm	0:9b334a45a8ff	1522	*/
bogdanm	0:9b334a45a8ff	1523	__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1524	{
mbed_official	83:a036322b8637	1525	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1526	UNUSED(hqspi);
mbed_official	83:a036322b8637	1527
bogdanm	0:9b334a45a8ff	1528	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1529	the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1530	*/
bogdanm	0:9b334a45a8ff	1531	}
bogdanm	0:9b334a45a8ff	1532
bogdanm	0:9b334a45a8ff	1533	/**
bogdanm	0:9b334a45a8ff	1534	* @brief FIFO Threshold callbacks
bogdanm	0:9b334a45a8ff	1535	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1536	* @retval None
bogdanm	0:9b334a45a8ff	1537	*/
bogdanm	0:9b334a45a8ff	1538	__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1539	{
mbed_official	83:a036322b8637	1540	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1541	UNUSED(hqspi);
mbed_official	83:a036322b8637	1542
bogdanm	0:9b334a45a8ff	1543	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1544	the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1545	*/
bogdanm	0:9b334a45a8ff	1546	}
bogdanm	0:9b334a45a8ff	1547
bogdanm	0:9b334a45a8ff	1548	/**
bogdanm	0:9b334a45a8ff	1549	* @brief Status Match callbacks
bogdanm	0:9b334a45a8ff	1550	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1551	* @retval None
bogdanm	0:9b334a45a8ff	1552	*/
bogdanm	0:9b334a45a8ff	1553	__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1554	{
mbed_official	83:a036322b8637	1555	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1556	UNUSED(hqspi);
mbed_official	83:a036322b8637	1557
bogdanm	0:9b334a45a8ff	1558	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1559	the HAL_QSPI_StatusMatchCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1560	*/
bogdanm	0:9b334a45a8ff	1561	}
bogdanm	0:9b334a45a8ff	1562
bogdanm	0:9b334a45a8ff	1563	/**
bogdanm	0:9b334a45a8ff	1564	* @brief Timeout callbacks
bogdanm	0:9b334a45a8ff	1565	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1566	* @retval None
bogdanm	0:9b334a45a8ff	1567	*/
bogdanm	0:9b334a45a8ff	1568	__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1569	{
mbed_official	83:a036322b8637	1570	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1571	UNUSED(hqspi);
mbed_official	83:a036322b8637	1572
bogdanm	0:9b334a45a8ff	1573	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1574	the HAL_QSPI_TimeOutCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1575	*/
bogdanm	0:9b334a45a8ff	1576	}
bogdanm	0:9b334a45a8ff	1577
bogdanm	0:9b334a45a8ff	1578	/**
bogdanm	0:9b334a45a8ff	1579	* @}
bogdanm	0:9b334a45a8ff	1580	*/
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582	/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
bogdanm	0:9b334a45a8ff	1583	* @brief QSPI control and State functions
bogdanm	0:9b334a45a8ff	1584	*
bogdanm	0:9b334a45a8ff	1585	@verbatim
bogdanm	0:9b334a45a8ff	1586	===============================================================================
bogdanm	0:9b334a45a8ff	1587	##### Peripheral Control and State functions #####
bogdanm	0:9b334a45a8ff	1588	===============================================================================
bogdanm	0:9b334a45a8ff	1589	[..]
bogdanm	0:9b334a45a8ff	1590	This subsection provides a set of functions allowing to :
bogdanm	0:9b334a45a8ff	1591	(+) Check in run-time the state of the driver.
bogdanm	0:9b334a45a8ff	1592	(+) Check the error code set during last operation.
bogdanm	0:9b334a45a8ff	1593	(+) Abort any operation.
bogdanm	0:9b334a45a8ff	1594	.....
bogdanm	0:9b334a45a8ff	1595	@endverbatim
bogdanm	0:9b334a45a8ff	1596	* @{
bogdanm	0:9b334a45a8ff	1597	*/
bogdanm	0:9b334a45a8ff	1598
bogdanm	0:9b334a45a8ff	1599	/**
bogdanm	0:9b334a45a8ff	1600	* @brief Return the QSPI state.
bogdanm	0:9b334a45a8ff	1601	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1602	* @retval HAL state
bogdanm	0:9b334a45a8ff	1603	*/
bogdanm	0:9b334a45a8ff	1604	HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1605	{
bogdanm	0:9b334a45a8ff	1606	return hqspi->State;
bogdanm	0:9b334a45a8ff	1607	}
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/**
bogdanm	0:9b334a45a8ff	1610	* @brief Return the QSPI error code
bogdanm	0:9b334a45a8ff	1611	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1612	* @retval QSPI Error Code
bogdanm	0:9b334a45a8ff	1613	*/
bogdanm	0:9b334a45a8ff	1614	uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1615	{
bogdanm	0:9b334a45a8ff	1616	return hqspi->ErrorCode;
bogdanm	0:9b334a45a8ff	1617	}
bogdanm	0:9b334a45a8ff	1618
bogdanm	0:9b334a45a8ff	1619	/**
bogdanm	0:9b334a45a8ff	1620	* @brief Abort the current transmission
bogdanm	0:9b334a45a8ff	1621	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1622	* @retval HAL status
bogdanm	0:9b334a45a8ff	1623	*/
bogdanm	0:9b334a45a8ff	1624	HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1625	{
bogdanm	0:9b334a45a8ff	1626	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1627
bogdanm	0:9b334a45a8ff	1628	/* Configure QSPI: CR register with Abort request */
bogdanm	0:9b334a45a8ff	1629	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
bogdanm	0:9b334a45a8ff	1630
bogdanm	0:9b334a45a8ff	1631	/* Wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	1632	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1633	{
bogdanm	0:9b334a45a8ff	1634	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1635	}
bogdanm	0:9b334a45a8ff	1636	else
bogdanm	0:9b334a45a8ff	1637	{
bogdanm	0:9b334a45a8ff	1638	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	1639
bogdanm	0:9b334a45a8ff	1640	/* Wait until BUSY flag is reset */
bogdanm	0:9b334a45a8ff	1641	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	1642
bogdanm	0:9b334a45a8ff	1643	/* Update state */
bogdanm	0:9b334a45a8ff	1644	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1645	}
bogdanm	0:9b334a45a8ff	1646
bogdanm	0:9b334a45a8ff	1647	return status;
bogdanm	0:9b334a45a8ff	1648	}
bogdanm	0:9b334a45a8ff	1649
bogdanm	0:9b334a45a8ff	1650	/** @brief Set QSPI timeout
bogdanm	0:9b334a45a8ff	1651	* @param hqspi: QSPI handle.
bogdanm	0:9b334a45a8ff	1652	* @param Timeout: Timeout for the QSPI memory access.
bogdanm	0:9b334a45a8ff	1653	* @retval None
bogdanm	0:9b334a45a8ff	1654	*/
bogdanm	0:9b334a45a8ff	1655	void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1656	{
bogdanm	0:9b334a45a8ff	1657	hqspi->Timeout = Timeout;
bogdanm	0:9b334a45a8ff	1658	}
bogdanm	0:9b334a45a8ff	1659
bogdanm	0:9b334a45a8ff	1660	/**
bogdanm	0:9b334a45a8ff	1661	* @}
bogdanm	0:9b334a45a8ff	1662	*/
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1665
bogdanm	0:9b334a45a8ff	1666	/**
bogdanm	0:9b334a45a8ff	1667	* @brief DMA QSPI receive process complete callback.
bogdanm	0:9b334a45a8ff	1668	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	1669	* @retval None
bogdanm	0:9b334a45a8ff	1670	*/
bogdanm	0:9b334a45a8ff	1671	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1672	{
bogdanm	0:9b334a45a8ff	1673	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1674	hqspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1675
bogdanm	0:9b334a45a8ff	1676	/* Wait for QSPI TC Flag */
bogdanm	0:9b334a45a8ff	1677	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1678	{
bogdanm	0:9b334a45a8ff	1679	/* Time out Occurred */
bogdanm	0:9b334a45a8ff	1680	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	1681	}
bogdanm	0:9b334a45a8ff	1682	else
bogdanm	0:9b334a45a8ff	1683	{
bogdanm	0:9b334a45a8ff	1684	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1685	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1686
bogdanm	0:9b334a45a8ff	1687	/* Disable the DMA channel */
bogdanm	0:9b334a45a8ff	1688	HAL_DMA_Abort(hdma);
bogdanm	0:9b334a45a8ff	1689
bogdanm	0:9b334a45a8ff	1690	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	1691	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	1692
bogdanm	0:9b334a45a8ff	1693	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
bogdanm	0:9b334a45a8ff	1694	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	1695
bogdanm	0:9b334a45a8ff	1696	/* Update state */
bogdanm	0:9b334a45a8ff	1697	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1698
bogdanm	0:9b334a45a8ff	1699	HAL_QSPI_RxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1700	}
bogdanm	0:9b334a45a8ff	1701	}
bogdanm	0:9b334a45a8ff	1702
bogdanm	0:9b334a45a8ff	1703	/**
bogdanm	0:9b334a45a8ff	1704	* @brief DMA QSPI transmit process complete callback.
bogdanm	0:9b334a45a8ff	1705	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	1706	* @retval None
bogdanm	0:9b334a45a8ff	1707	*/
bogdanm	0:9b334a45a8ff	1708	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1709	{
bogdanm	0:9b334a45a8ff	1710	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1711	hqspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1712
bogdanm	0:9b334a45a8ff	1713	/* Wait for QSPI TC Flag */
bogdanm	0:9b334a45a8ff	1714	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1715	{
bogdanm	0:9b334a45a8ff	1716	/* Time out Occurred */
bogdanm	0:9b334a45a8ff	1717	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	1718	}
bogdanm	0:9b334a45a8ff	1719	else
bogdanm	0:9b334a45a8ff	1720	{
bogdanm	0:9b334a45a8ff	1721	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1722	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1723
bogdanm	0:9b334a45a8ff	1724	/* Disable the DMA channel */
bogdanm	0:9b334a45a8ff	1725	HAL_DMA_Abort(hdma);
bogdanm	0:9b334a45a8ff	1726
bogdanm	0:9b334a45a8ff	1727	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	1728	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	1729
bogdanm	0:9b334a45a8ff	1730	/* Clear Busy bit */
bogdanm	0:9b334a45a8ff	1731	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	1732
bogdanm	0:9b334a45a8ff	1733	/* Update state */
bogdanm	0:9b334a45a8ff	1734	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1735
bogdanm	0:9b334a45a8ff	1736	HAL_QSPI_TxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1737	}
bogdanm	0:9b334a45a8ff	1738	}
bogdanm	0:9b334a45a8ff	1739
bogdanm	0:9b334a45a8ff	1740	/**
bogdanm	0:9b334a45a8ff	1741	* @brief DMA QSPI receive process half complete callback
bogdanm	0:9b334a45a8ff	1742	* @param hdma : DMA handle
bogdanm	0:9b334a45a8ff	1743	* @retval None
bogdanm	0:9b334a45a8ff	1744	*/
bogdanm	0:9b334a45a8ff	1745	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1746	{
bogdanm	0:9b334a45a8ff	1747	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1748
bogdanm	0:9b334a45a8ff	1749	HAL_QSPI_RxHalfCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1750	}
bogdanm	0:9b334a45a8ff	1751
bogdanm	0:9b334a45a8ff	1752	/**
bogdanm	0:9b334a45a8ff	1753	* @brief DMA QSPI transmit process half complete callback
bogdanm	0:9b334a45a8ff	1754	* @param hdma : DMA handle
bogdanm	0:9b334a45a8ff	1755	* @retval None
bogdanm	0:9b334a45a8ff	1756	*/
bogdanm	0:9b334a45a8ff	1757	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1758	{
bogdanm	0:9b334a45a8ff	1759	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1760
bogdanm	0:9b334a45a8ff	1761	HAL_QSPI_TxHalfCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1762	}
bogdanm	0:9b334a45a8ff	1763
bogdanm	0:9b334a45a8ff	1764	/**
bogdanm	0:9b334a45a8ff	1765	* @brief DMA QSPI communication error callback.
bogdanm	0:9b334a45a8ff	1766	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	1767	* @retval None
bogdanm	0:9b334a45a8ff	1768	*/
bogdanm	0:9b334a45a8ff	1769	static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1770	{
bogdanm	0:9b334a45a8ff	1771	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1772
bogdanm	0:9b334a45a8ff	1773	hqspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1774	hqspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1775	hqspi->State = HAL_QSPI_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1776	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
bogdanm	0:9b334a45a8ff	1777
bogdanm	0:9b334a45a8ff	1778	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	1779	}
bogdanm	0:9b334a45a8ff	1780
bogdanm	0:9b334a45a8ff	1781	/**
bogdanm	0:9b334a45a8ff	1782	* @brief This function wait a flag state until time out.
bogdanm	0:9b334a45a8ff	1783	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1784	* @param Flag: Flag checked
bogdanm	0:9b334a45a8ff	1785	* @param State: Value of the flag expected
bogdanm	0:9b334a45a8ff	1786	* @param Timeout: Duration of the time out
bogdanm	0:9b334a45a8ff	1787	* @retval HAL status
bogdanm	0:9b334a45a8ff	1788	*/
bogdanm	0:9b334a45a8ff	1789	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
bogdanm	0:9b334a45a8ff	1790	FlagStatus State, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1791	{
bogdanm	0:9b334a45a8ff	1792	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1793
bogdanm	0:9b334a45a8ff	1794	/* Wait until flag is in expected state */
bogdanm	0:9b334a45a8ff	1795	while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
bogdanm	0:9b334a45a8ff	1796	{
bogdanm	0:9b334a45a8ff	1797	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	1798	if (Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1799	{
bogdanm	0:9b334a45a8ff	1800	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	1801	{
bogdanm	0:9b334a45a8ff	1802	hqspi->State = HAL_QSPI_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1803	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	1804
bogdanm	0:9b334a45a8ff	1805	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1806	}
bogdanm	0:9b334a45a8ff	1807	}
bogdanm	0:9b334a45a8ff	1808	}
bogdanm	0:9b334a45a8ff	1809	return HAL_OK;
bogdanm	0:9b334a45a8ff	1810	}
bogdanm	0:9b334a45a8ff	1811
bogdanm	0:9b334a45a8ff	1812	/**
bogdanm	0:9b334a45a8ff	1813	* @brief This function configures the communication registers
bogdanm	0:9b334a45a8ff	1814	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1815	* @param cmd: structure that contains the command configuration information
bogdanm	0:9b334a45a8ff	1816	* @param FunctionalMode: functional mode to configured
bogdanm	0:9b334a45a8ff	1817	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1818	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
bogdanm	0:9b334a45a8ff	1819	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
bogdanm	0:9b334a45a8ff	1820	* @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
bogdanm	0:9b334a45a8ff	1821	* @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
bogdanm	0:9b334a45a8ff	1822	* @retval None
bogdanm	0:9b334a45a8ff	1823	*/
bogdanm	0:9b334a45a8ff	1824	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode)
bogdanm	0:9b334a45a8ff	1825	{
bogdanm	0:9b334a45a8ff	1826	assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
bogdanm	0:9b334a45a8ff	1827
bogdanm	0:9b334a45a8ff	1828	if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
bogdanm	0:9b334a45a8ff	1829	{
bogdanm	0:9b334a45a8ff	1830	/* Configure QSPI: DLR register with the number of data to read or write */
bogdanm	0:9b334a45a8ff	1831	WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
bogdanm	0:9b334a45a8ff	1832	}
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1835	{
bogdanm	0:9b334a45a8ff	1836	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1837	{
bogdanm	0:9b334a45a8ff	1838	/* Configure QSPI: ABR register with alternate bytes value */
bogdanm	0:9b334a45a8ff	1839	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
bogdanm	0:9b334a45a8ff	1840
bogdanm	0:9b334a45a8ff	1841	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1842	{
bogdanm	0:9b334a45a8ff	1843	/---- Command with instruction, address and alternate bytes ----/
bogdanm	0:9b334a45a8ff	1844	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1845	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1846	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1847	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
bogdanm	0:9b334a45a8ff	1848	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1849
bogdanm	0:9b334a45a8ff	1850	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1851	{
bogdanm	0:9b334a45a8ff	1852	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1853	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1854	}
bogdanm	0:9b334a45a8ff	1855	}
bogdanm	0:9b334a45a8ff	1856	else
bogdanm	0:9b334a45a8ff	1857	{
bogdanm	0:9b334a45a8ff	1858	/---- Command with instruction and alternate bytes ----/
bogdanm	0:9b334a45a8ff	1859	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1860	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1861	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1862	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1863	cmd->Instruction \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1864	}
bogdanm	0:9b334a45a8ff	1865	}
bogdanm	0:9b334a45a8ff	1866	else
bogdanm	0:9b334a45a8ff	1867	{
bogdanm	0:9b334a45a8ff	1868	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1869	{
bogdanm	0:9b334a45a8ff	1870	/---- Command with instruction and address ----/
bogdanm	0:9b334a45a8ff	1871	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1872	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1873	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1874	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1875	cmd->Instruction \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1876
bogdanm	0:9b334a45a8ff	1877	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1878	{
bogdanm	0:9b334a45a8ff	1879	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1880	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1881	}
bogdanm	0:9b334a45a8ff	1882	}
bogdanm	0:9b334a45a8ff	1883	else
bogdanm	0:9b334a45a8ff	1884	{
bogdanm	0:9b334a45a8ff	1885	/---- Command with only instruction ----/
bogdanm	0:9b334a45a8ff	1886	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1887	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1888	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1889	cmd->AddressMode \| cmd->InstructionMode \| cmd->Instruction \|
bogdanm	0:9b334a45a8ff	1890	FunctionalMode));
bogdanm	0:9b334a45a8ff	1891	}
bogdanm	0:9b334a45a8ff	1892	}
bogdanm	0:9b334a45a8ff	1893	}
bogdanm	0:9b334a45a8ff	1894	else
bogdanm	0:9b334a45a8ff	1895	{
bogdanm	0:9b334a45a8ff	1896	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1897	{
bogdanm	0:9b334a45a8ff	1898	/* Configure QSPI: ABR register with alternate bytes value */
bogdanm	0:9b334a45a8ff	1899	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
bogdanm	0:9b334a45a8ff	1900
bogdanm	0:9b334a45a8ff	1901	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1902	{
bogdanm	0:9b334a45a8ff	1903	/---- Command with address and alternate bytes ----/
bogdanm	0:9b334a45a8ff	1904	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1905	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1906	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1907	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
bogdanm	0:9b334a45a8ff	1908	cmd->InstructionMode \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1909
bogdanm	0:9b334a45a8ff	1910	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1911	{
bogdanm	0:9b334a45a8ff	1912	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1913	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1914	}
bogdanm	0:9b334a45a8ff	1915	}
bogdanm	0:9b334a45a8ff	1916	else
bogdanm	0:9b334a45a8ff	1917	{
bogdanm	0:9b334a45a8ff	1918	/---- Command with only alternate bytes ----/
bogdanm	0:9b334a45a8ff	1919	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1920	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1921	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1922	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1923	FunctionalMode));
bogdanm	0:9b334a45a8ff	1924	}
bogdanm	0:9b334a45a8ff	1925	}
bogdanm	0:9b334a45a8ff	1926	else
bogdanm	0:9b334a45a8ff	1927	{
bogdanm	0:9b334a45a8ff	1928	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1929	{
bogdanm	0:9b334a45a8ff	1930	/---- Command with only address ----/
bogdanm	0:9b334a45a8ff	1931	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1932	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1933	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1934	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1935	FunctionalMode));
bogdanm	0:9b334a45a8ff	1936
bogdanm	0:9b334a45a8ff	1937	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1938	{
bogdanm	0:9b334a45a8ff	1939	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1940	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1941	}
bogdanm	0:9b334a45a8ff	1942	}
bogdanm	0:9b334a45a8ff	1943	else
bogdanm	0:9b334a45a8ff	1944	{
bogdanm	0:9b334a45a8ff	1945	/---- Command with only data phase ----/
bogdanm	0:9b334a45a8ff	1946	if (cmd->DataMode != QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	1947	{
bogdanm	0:9b334a45a8ff	1948	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1949	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1950	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1951	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1952	}
bogdanm	0:9b334a45a8ff	1953	}
bogdanm	0:9b334a45a8ff	1954	}
bogdanm	0:9b334a45a8ff	1955	}
bogdanm	0:9b334a45a8ff	1956	}
bogdanm	0:9b334a45a8ff	1957	/**
bogdanm	0:9b334a45a8ff	1958	* @}
bogdanm	0:9b334a45a8ff	1959	*/
bogdanm	0:9b334a45a8ff	1960
bogdanm	0:9b334a45a8ff	1961	#endif /* HAL_QSPI_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1962	/**
bogdanm	0:9b334a45a8ff	1963	* @}
bogdanm	0:9b334a45a8ff	1964	*/
bogdanm	0:9b334a45a8ff	1965
bogdanm	0:9b334a45a8ff	1966	/**
bogdanm	0:9b334a45a8ff	1967	* @}
bogdanm	0:9b334a45a8ff	1968	*/
bogdanm	0:9b334a45a8ff	1969
bogdanm	0:9b334a45a8ff	1970	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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