mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 83:a036322b8637

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f7xx_hal_qspi.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.1
bogdanm	0:9b334a45a8ff	6	* @date 25-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief QSPI HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the QuadSPI interface (QSPI).
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + Indirect functional mode management
bogdanm	0:9b334a45a8ff	12	* + Memory-mapped functional mode management
bogdanm	0:9b334a45a8ff	13	* + Auto-polling functional mode management
bogdanm	0:9b334a45a8ff	14	* + Interrupts and flags management
bogdanm	0:9b334a45a8ff	15	* + DMA channel configuration for indirect functional mode
bogdanm	0:9b334a45a8ff	16	* + Errors management and abort functionality
bogdanm	0:9b334a45a8ff	17	*
bogdanm	0:9b334a45a8ff	18	*
bogdanm	0:9b334a45a8ff	19	@verbatim
bogdanm	0:9b334a45a8ff	20	===============================================================================
bogdanm	0:9b334a45a8ff	21	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	22	===============================================================================
bogdanm	0:9b334a45a8ff	23	[..]
bogdanm	0:9b334a45a8ff	24	* Initialization *
bogdanm	0:9b334a45a8ff	25	======================
bogdanm	0:9b334a45a8ff	26	[..]
bogdanm	0:9b334a45a8ff	27	(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
bogdanm	0:9b334a45a8ff	28	(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
bogdanm	0:9b334a45a8ff	29	(++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
bogdanm	0:9b334a45a8ff	30	(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
bogdanm	0:9b334a45a8ff	31	(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
bogdanm	0:9b334a45a8ff	32	(++) If interrupt mode is used, enable and configure QuadSPI global
bogdanm	0:9b334a45a8ff	33	interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
bogdanm	0:9b334a45a8ff	34	(++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
bogdanm	0:9b334a45a8ff	35	with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
bogdanm	0:9b334a45a8ff	36	link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
bogdanm	0:9b334a45a8ff	37	DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
bogdanm	0:9b334a45a8ff	38	(#) Configure the flash size, the clock prescaler, the fifo threshold, the
bogdanm	0:9b334a45a8ff	39	clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	* Indirect functional mode *
bogdanm	0:9b334a45a8ff	42	================================
bogdanm	0:9b334a45a8ff	43	[..]
bogdanm	0:9b334a45a8ff	44	(#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
bogdanm	0:9b334a45a8ff	45	functions :
bogdanm	0:9b334a45a8ff	46	(++) Instruction phase : the mode used and if present the instruction opcode.
bogdanm	0:9b334a45a8ff	47	(++) Address phase : the mode used and if present the size and the address value.
bogdanm	0:9b334a45a8ff	48	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
bogdanm	0:9b334a45a8ff	49	bytes values.
bogdanm	0:9b334a45a8ff	50	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
bogdanm	0:9b334a45a8ff	51	(++) Data phase : the mode used and if present the number of bytes.
bogdanm	0:9b334a45a8ff	52	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
bogdanm	0:9b334a45a8ff	53	if activated.
bogdanm	0:9b334a45a8ff	54	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
bogdanm	0:9b334a45a8ff	55	(#) If no data is required for the command, it is sent directly to the memory :
bogdanm	0:9b334a45a8ff	56	(++) In polling mode, the output of the function is done when the transfer is complete.
bogdanm	0:9b334a45a8ff	57	(++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	58	(#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
bogdanm	0:9b334a45a8ff	59	HAL_QSPI_Transmit_IT() after the command configuration :
bogdanm	0:9b334a45a8ff	60	(++) In polling mode, the output of the function is done when the transfer is complete.
bogdanm	0:9b334a45a8ff	61	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
bogdanm	0:9b334a45a8ff	62	is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	63	(++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
bogdanm	0:9b334a45a8ff	64	HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	65	(#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
bogdanm	0:9b334a45a8ff	66	HAL_QSPI_Receive_IT() after the command configuration :
bogdanm	0:9b334a45a8ff	67	(++) In polling mode, the output of the function is done when the transfer is complete.
bogdanm	0:9b334a45a8ff	68	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
bogdanm	0:9b334a45a8ff	69	is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	70	(++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
bogdanm	0:9b334a45a8ff	71	HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	* Auto-polling functional mode *
bogdanm	0:9b334a45a8ff	74	====================================
bogdanm	0:9b334a45a8ff	75	[..]
bogdanm	0:9b334a45a8ff	76	(#) Configure the command sequence and the auto-polling functional mode using the
bogdanm	0:9b334a45a8ff	77	HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
bogdanm	0:9b334a45a8ff	78	(++) Instruction phase : the mode used and if present the instruction opcode.
bogdanm	0:9b334a45a8ff	79	(++) Address phase : the mode used and if present the size and the address value.
bogdanm	0:9b334a45a8ff	80	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
bogdanm	0:9b334a45a8ff	81	bytes values.
bogdanm	0:9b334a45a8ff	82	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
bogdanm	0:9b334a45a8ff	83	(++) Data phase : the mode used.
bogdanm	0:9b334a45a8ff	84	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
bogdanm	0:9b334a45a8ff	85	if activated.
bogdanm	0:9b334a45a8ff	86	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
bogdanm	0:9b334a45a8ff	87	(++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
bogdanm	0:9b334a45a8ff	88	the polling interval and the automatic stop activation.
bogdanm	0:9b334a45a8ff	89	(#) After the configuration :
bogdanm	0:9b334a45a8ff	90	(++) In polling mode, the output of the function is done when the status match is reached. The
bogdanm	0:9b334a45a8ff	91	automatic stop is activated to avoid an infinite loop.
bogdanm	0:9b334a45a8ff	92	(++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	* Memory-mapped functional mode *
bogdanm	0:9b334a45a8ff	95	=====================================
bogdanm	0:9b334a45a8ff	96	[..]
bogdanm	0:9b334a45a8ff	97	(#) Configure the command sequence and the memory-mapped functional mode using the
bogdanm	0:9b334a45a8ff	98	HAL_QSPI_MemoryMapped() functions :
bogdanm	0:9b334a45a8ff	99	(++) Instruction phase : the mode used and if present the instruction opcode.
bogdanm	0:9b334a45a8ff	100	(++) Address phase : the mode used and the size.
bogdanm	0:9b334a45a8ff	101	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
bogdanm	0:9b334a45a8ff	102	bytes values.
bogdanm	0:9b334a45a8ff	103	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
bogdanm	0:9b334a45a8ff	104	(++) Data phase : the mode used.
bogdanm	0:9b334a45a8ff	105	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
bogdanm	0:9b334a45a8ff	106	if activated.
bogdanm	0:9b334a45a8ff	107	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
bogdanm	0:9b334a45a8ff	108	(++) The timeout activation and the timeout period.
bogdanm	0:9b334a45a8ff	109	(#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
bogdanm	0:9b334a45a8ff	110	the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112	* Errors management and abort functionality *
bogdanm	0:9b334a45a8ff	113	==================================================
bogdanm	0:9b334a45a8ff	114	[..]
bogdanm	0:9b334a45a8ff	115	(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
bogdanm	0:9b334a45a8ff	116	(#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
bogdanm	0:9b334a45a8ff	117	(#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	* Workarounds linked to Silicon Limitation *
bogdanm	0:9b334a45a8ff	120	====================================================
bogdanm	0:9b334a45a8ff	121	[..]
bogdanm	0:9b334a45a8ff	122	(#) Workarounds Implemented inside HAL Driver
bogdanm	0:9b334a45a8ff	123	(++) Extra data written in the FIFO at the end of a read transfer
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125	@endverbatim
bogdanm	0:9b334a45a8ff	126	******************************************************************************
bogdanm	0:9b334a45a8ff	127	* @attention
bogdanm	0:9b334a45a8ff	128	*
bogdanm	0:9b334a45a8ff	129	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	130	*
bogdanm	0:9b334a45a8ff	131	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	132	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	133	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	134	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	135	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	136	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	137	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	138	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	139	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	140	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	141	*
bogdanm	0:9b334a45a8ff	142	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	143	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	144	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	145	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	146	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	147	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	148	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	149	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	150	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	151	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	152	*
bogdanm	0:9b334a45a8ff	153	******************************************************************************
bogdanm	0:9b334a45a8ff	154	*/
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	157	#include "stm32f7xx_hal.h"
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	/** @addtogroup STM32F7xx_HAL_Driver
bogdanm	0:9b334a45a8ff	160	* @{
bogdanm	0:9b334a45a8ff	161	*/
bogdanm	0:9b334a45a8ff	162
bogdanm	0:9b334a45a8ff	163	/** @defgroup QSPI QSPI
bogdanm	0:9b334a45a8ff	164	* @brief HAL QSPI module driver
bogdanm	0:9b334a45a8ff	165	* @{
bogdanm	0:9b334a45a8ff	166	*/
bogdanm	0:9b334a45a8ff	167	#ifdef HAL_QSPI_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	170	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	171	/** @addtogroup QSPI_Private_Constants
bogdanm	0:9b334a45a8ff	172	* @{
bogdanm	0:9b334a45a8ff	173	*/
bogdanm	0:9b334a45a8ff	174	#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /!<Indirect write mode/
bogdanm	0:9b334a45a8ff	175	#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /!<Indirect read mode/
bogdanm	0:9b334a45a8ff	176	#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /!<Automatic polling mode/
bogdanm	0:9b334a45a8ff	177	#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /!<Memory-mapped mode/
bogdanm	0:9b334a45a8ff	178	/**
bogdanm	0:9b334a45a8ff	179	* @}
bogdanm	0:9b334a45a8ff	180	*/
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	183	/** @addtogroup QSPI_Private_Macros QSPI Private Macros
bogdanm	0:9b334a45a8ff	184	* @{
bogdanm	0:9b334a45a8ff	185	*/
bogdanm	0:9b334a45a8ff	186	#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) \|\| \
bogdanm	0:9b334a45a8ff	187	((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) \|\| \
bogdanm	0:9b334a45a8ff	188	((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) \|\| \
bogdanm	0:9b334a45a8ff	189	((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
bogdanm	0:9b334a45a8ff	190	/**
bogdanm	0:9b334a45a8ff	191	* @}
bogdanm	0:9b334a45a8ff	192	*/
bogdanm	0:9b334a45a8ff	193
bogdanm	0:9b334a45a8ff	194	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	195	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	196	/** @addtogroup QSPI_Private_Functions QSPI Private Functions
bogdanm	0:9b334a45a8ff	197	* @{
bogdanm	0:9b334a45a8ff	198	*/
bogdanm	0:9b334a45a8ff	199	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	200	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	201	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	202	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	203	static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	204	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	205	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode);
bogdanm	0:9b334a45a8ff	206	/**
bogdanm	0:9b334a45a8ff	207	* @}
bogdanm	0:9b334a45a8ff	208	*/
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
bogdanm	0:9b334a45a8ff	213	* @{
bogdanm	0:9b334a45a8ff	214	*/
bogdanm	0:9b334a45a8ff	215
bogdanm	0:9b334a45a8ff	216	/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	217	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	218	*
bogdanm	0:9b334a45a8ff	219	@verbatim
bogdanm	0:9b334a45a8ff	220	===============================================================================
bogdanm	0:9b334a45a8ff	221	##### Initialization and Configuration functions #####
bogdanm	0:9b334a45a8ff	222	===============================================================================
bogdanm	0:9b334a45a8ff	223	[..]
bogdanm	0:9b334a45a8ff	224	This subsection provides a set of functions allowing to :
bogdanm	0:9b334a45a8ff	225	(+) Initialize the QuadSPI.
bogdanm	0:9b334a45a8ff	226	(+) De-initialize the QuadSPI.
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	@endverbatim
bogdanm	0:9b334a45a8ff	229	* @{
bogdanm	0:9b334a45a8ff	230	*/
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	/**
bogdanm	0:9b334a45a8ff	233	* @brief Initializes the QSPI mode according to the specified parameters
bogdanm	0:9b334a45a8ff	234	* in the QSPI_InitTypeDef and creates the associated handle.
bogdanm	0:9b334a45a8ff	235	* @param hqspi: qspi handle
bogdanm	0:9b334a45a8ff	236	* @retval HAL status
bogdanm	0:9b334a45a8ff	237	*/
bogdanm	0:9b334a45a8ff	238	HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	239	{
bogdanm	0:9b334a45a8ff	240	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	/* Check the QSPI handle allocation */
bogdanm	0:9b334a45a8ff	243	if(hqspi == NULL)
bogdanm	0:9b334a45a8ff	244	{
bogdanm	0:9b334a45a8ff	245	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	246	}
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248	/* Check the parameters */
bogdanm	0:9b334a45a8ff	249	assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
bogdanm	0:9b334a45a8ff	250	assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
bogdanm	0:9b334a45a8ff	251	assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
bogdanm	0:9b334a45a8ff	252	assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
bogdanm	0:9b334a45a8ff	253	assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
bogdanm	0:9b334a45a8ff	254	assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
bogdanm	0:9b334a45a8ff	255	assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
bogdanm	0:9b334a45a8ff	256	assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
bogdanm	0:9b334a45a8ff	259	{
bogdanm	0:9b334a45a8ff	260	assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
bogdanm	0:9b334a45a8ff	261	}
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263	/* Process locked */
bogdanm	0:9b334a45a8ff	264	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	265
bogdanm	0:9b334a45a8ff	266	if(hqspi->State == HAL_QSPI_STATE_RESET)
bogdanm	0:9b334a45a8ff	267	{
bogdanm	0:9b334a45a8ff	268	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	269	hqspi->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	270
bogdanm	0:9b334a45a8ff	271	/* Init the low level hardware : GPIO, CLOCK */
bogdanm	0:9b334a45a8ff	272	HAL_QSPI_MspInit(hqspi);
bogdanm	0:9b334a45a8ff	273
bogdanm	0:9b334a45a8ff	274	/* Configure the default timeout for the QSPI memory access */
bogdanm	0:9b334a45a8ff	275	HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
bogdanm	0:9b334a45a8ff	276	}
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	/* Configure QSPI FIFO Threshold */
bogdanm	0:9b334a45a8ff	279	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	282	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	if(status == HAL_OK)
bogdanm	0:9b334a45a8ff	285	{
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287	/* Configure QSPI Clock Prescaler and Sample Shift */
bogdanm	0:9b334a45a8ff	288	MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER \| QUADSPI_CR_SSHIFT \| QUADSPI_CR_FSEL \| QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)\| hqspi->Init.SampleShifting \| hqspi->Init.FlashID\| hqspi->Init.DualFlash ));
bogdanm	0:9b334a45a8ff	289
bogdanm	0:9b334a45a8ff	290	/* Configure QSPI Flash Size, CS High Time and Clock Mode */
bogdanm	0:9b334a45a8ff	291	MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE \| QUADSPI_DCR_CSHT \| QUADSPI_DCR_CKMODE),
bogdanm	0:9b334a45a8ff	292	((hqspi->Init.FlashSize << 16) \| hqspi->Init.ChipSelectHighTime \| hqspi->Init.ClockMode));
bogdanm	0:9b334a45a8ff	293
bogdanm	0:9b334a45a8ff	294	/* Enable the QSPI peripheral */
bogdanm	0:9b334a45a8ff	295	__HAL_QSPI_ENABLE(hqspi);
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/* Set QSPI error code to none */
bogdanm	0:9b334a45a8ff	298	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	299
bogdanm	0:9b334a45a8ff	300	/* Initialize the QSPI state */
bogdanm	0:9b334a45a8ff	301	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	302	}
bogdanm	0:9b334a45a8ff	303
bogdanm	0:9b334a45a8ff	304	/* Release Lock */
bogdanm	0:9b334a45a8ff	305	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	306
bogdanm	0:9b334a45a8ff	307	/* Return function status */
bogdanm	0:9b334a45a8ff	308	return status;
bogdanm	0:9b334a45a8ff	309	}
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	/**
bogdanm	0:9b334a45a8ff	312	* @brief DeInitializes the QSPI peripheral
bogdanm	0:9b334a45a8ff	313	* @param hqspi: qspi handle
bogdanm	0:9b334a45a8ff	314	* @retval HAL status
bogdanm	0:9b334a45a8ff	315	*/
bogdanm	0:9b334a45a8ff	316	HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	317	{
bogdanm	0:9b334a45a8ff	318	/* Check the QSPI handle allocation */
bogdanm	0:9b334a45a8ff	319	if(hqspi == NULL)
bogdanm	0:9b334a45a8ff	320	{
bogdanm	0:9b334a45a8ff	321	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	322	}
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324	/* Process locked */
bogdanm	0:9b334a45a8ff	325	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	/* Disable the QSPI Peripheral Clock */
bogdanm	0:9b334a45a8ff	328	__HAL_QSPI_DISABLE(hqspi);
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	331	HAL_QSPI_MspDeInit(hqspi);
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	/* Set QSPI error code to none */
bogdanm	0:9b334a45a8ff	334	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	/* Initialize the QSPI state */
bogdanm	0:9b334a45a8ff	337	hqspi->State = HAL_QSPI_STATE_RESET;
bogdanm	0:9b334a45a8ff	338
bogdanm	0:9b334a45a8ff	339	/* Release Lock */
bogdanm	0:9b334a45a8ff	340	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	return HAL_OK;
bogdanm	0:9b334a45a8ff	343	}
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/**
bogdanm	0:9b334a45a8ff	346	* @brief QSPI MSP Init
bogdanm	0:9b334a45a8ff	347	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	348	* @retval None
bogdanm	0:9b334a45a8ff	349	*/
bogdanm	0:9b334a45a8ff	350	__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	351	{
bogdanm	0:9b334a45a8ff	352	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	353	the HAL_QSPI_MspInit can be implemented in the user file
bogdanm	0:9b334a45a8ff	354	*/
bogdanm	0:9b334a45a8ff	355	}
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	/**
bogdanm	0:9b334a45a8ff	358	* @brief QSPI MSP DeInit
bogdanm	0:9b334a45a8ff	359	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	360	* @retval None
bogdanm	0:9b334a45a8ff	361	*/
bogdanm	0:9b334a45a8ff	362	__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	363	{
bogdanm	0:9b334a45a8ff	364	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	365	the HAL_QSPI_MspDeInit can be implemented in the user file
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367	}
bogdanm	0:9b334a45a8ff	368
bogdanm	0:9b334a45a8ff	369	/**
bogdanm	0:9b334a45a8ff	370	* @}
bogdanm	0:9b334a45a8ff	371	*/
bogdanm	0:9b334a45a8ff	372
bogdanm	0:9b334a45a8ff	373	/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	374	* @brief QSPI Transmit/Receive functions
bogdanm	0:9b334a45a8ff	375	*
bogdanm	0:9b334a45a8ff	376	@verbatim
bogdanm	0:9b334a45a8ff	377	===============================================================================
bogdanm	0:9b334a45a8ff	378	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	379	===============================================================================
bogdanm	0:9b334a45a8ff	380	[..]
bogdanm	0:9b334a45a8ff	381	This subsection provides a set of functions allowing to :
bogdanm	0:9b334a45a8ff	382	(+) Handle the interrupts.
bogdanm	0:9b334a45a8ff	383	(+) Handle the command sequence.
bogdanm	0:9b334a45a8ff	384	(+) Transmit data in blocking, interrupt or DMA mode.
bogdanm	0:9b334a45a8ff	385	(+) Receive data in blocking, interrupt or DMA mode.
bogdanm	0:9b334a45a8ff	386	(+) Manage the auto-polling functional mode.
bogdanm	0:9b334a45a8ff	387	(+) Manage the memory-mapped functional mode.
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	@endverbatim
bogdanm	0:9b334a45a8ff	390	* @{
bogdanm	0:9b334a45a8ff	391	*/
bogdanm	0:9b334a45a8ff	392
bogdanm	0:9b334a45a8ff	393	/**
bogdanm	0:9b334a45a8ff	394	* @brief This function handles QSPI interrupt request.
bogdanm	0:9b334a45a8ff	395	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	396	* @retval None.
bogdanm	0:9b334a45a8ff	397	*/
bogdanm	0:9b334a45a8ff	398	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	399	{
bogdanm	0:9b334a45a8ff	400	__IO uint32_t *data_reg;
bogdanm	0:9b334a45a8ff	401	uint32_t flag = 0, itsource = 0;
bogdanm	0:9b334a45a8ff	402
bogdanm	0:9b334a45a8ff	403	/* QSPI FIFO Threshold interrupt occurred ----------------------------------*/
bogdanm	0:9b334a45a8ff	404	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
bogdanm	0:9b334a45a8ff	405	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
bogdanm	0:9b334a45a8ff	406
bogdanm	0:9b334a45a8ff	407	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	408	{
bogdanm	0:9b334a45a8ff	409	data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	410
bogdanm	0:9b334a45a8ff	411	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
bogdanm	0:9b334a45a8ff	412	{
bogdanm	0:9b334a45a8ff	413	/* Transmission process */
bogdanm	0:9b334a45a8ff	414	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
bogdanm	0:9b334a45a8ff	415	{
bogdanm	0:9b334a45a8ff	416	if (hqspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	417	{
bogdanm	0:9b334a45a8ff	418	/* Fill the FIFO until it is full */
bogdanm	0:9b334a45a8ff	419	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
bogdanm	0:9b334a45a8ff	420	hqspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	421	}
bogdanm	0:9b334a45a8ff	422	else
bogdanm	0:9b334a45a8ff	423	{
bogdanm	0:9b334a45a8ff	424	/* No more data available for the transfer */
bogdanm	0:9b334a45a8ff	425	break;
bogdanm	0:9b334a45a8ff	426	}
bogdanm	0:9b334a45a8ff	427	}
bogdanm	0:9b334a45a8ff	428	}
bogdanm	0:9b334a45a8ff	429	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
bogdanm	0:9b334a45a8ff	430	{
bogdanm	0:9b334a45a8ff	431	/* Receiving Process */
bogdanm	0:9b334a45a8ff	432	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
bogdanm	0:9b334a45a8ff	433	{
bogdanm	0:9b334a45a8ff	434	if (hqspi->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	435	{
bogdanm	0:9b334a45a8ff	436	/* Read the FIFO until it is empty */
bogdanm	0:9b334a45a8ff	437	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
bogdanm	0:9b334a45a8ff	438	hqspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	439	}
bogdanm	0:9b334a45a8ff	440	else
bogdanm	0:9b334a45a8ff	441	{
bogdanm	0:9b334a45a8ff	442	/* All data have been received for the transfer */
bogdanm	0:9b334a45a8ff	443	break;
bogdanm	0:9b334a45a8ff	444	}
bogdanm	0:9b334a45a8ff	445	}
bogdanm	0:9b334a45a8ff	446	}
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	/* FIFO Threshold callback */
bogdanm	0:9b334a45a8ff	449	HAL_QSPI_FifoThresholdCallback(hqspi);
bogdanm	0:9b334a45a8ff	450	}
bogdanm	0:9b334a45a8ff	451
bogdanm	0:9b334a45a8ff	452	/* QSPI Transfer Complete interrupt occurred -------------------------------*/
bogdanm	0:9b334a45a8ff	453	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	454	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	455
bogdanm	0:9b334a45a8ff	456	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	457	{
bogdanm	0:9b334a45a8ff	458	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	459	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	460
bogdanm	0:9b334a45a8ff	461	/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
bogdanm	0:9b334a45a8ff	462	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
bogdanm	0:9b334a45a8ff	463
bogdanm	0:9b334a45a8ff	464	/* Transfer complete callback */
bogdanm	0:9b334a45a8ff	465	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
bogdanm	0:9b334a45a8ff	466	{
bogdanm	0:9b334a45a8ff	467	/* Clear Busy bit */
bogdanm	0:9b334a45a8ff	468	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470	/* TX Complete callback */
bogdanm	0:9b334a45a8ff	471	HAL_QSPI_TxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	472	}
bogdanm	0:9b334a45a8ff	473	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
bogdanm	0:9b334a45a8ff	474	{
bogdanm	0:9b334a45a8ff	475	data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	476	while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
bogdanm	0:9b334a45a8ff	477	{
bogdanm	0:9b334a45a8ff	478	if (hqspi->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	479	{
bogdanm	0:9b334a45a8ff	480	/* Read the last data received in the FIFO until it is empty */
bogdanm	0:9b334a45a8ff	481	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
bogdanm	0:9b334a45a8ff	482	hqspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	483	}
bogdanm	0:9b334a45a8ff	484	else
bogdanm	0:9b334a45a8ff	485	{
bogdanm	0:9b334a45a8ff	486	/* All data have been received for the transfer */
bogdanm	0:9b334a45a8ff	487	break;
bogdanm	0:9b334a45a8ff	488	}
bogdanm	0:9b334a45a8ff	489	}
bogdanm	0:9b334a45a8ff	490
bogdanm	0:9b334a45a8ff	491	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
bogdanm	0:9b334a45a8ff	492	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	/* RX Complete callback */
bogdanm	0:9b334a45a8ff	495	HAL_QSPI_RxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	496	}
bogdanm	0:9b334a45a8ff	497	else if(hqspi->State == HAL_QSPI_STATE_BUSY)
bogdanm	0:9b334a45a8ff	498	{
bogdanm	0:9b334a45a8ff	499	/* Command Complete callback */
bogdanm	0:9b334a45a8ff	500	HAL_QSPI_CmdCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	501	}
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/* Change state of QSPI */
bogdanm	0:9b334a45a8ff	504	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	505	}
bogdanm	0:9b334a45a8ff	506
bogdanm	0:9b334a45a8ff	507	/* QSPI Status Match interrupt occurred ------------------------------------*/
bogdanm	0:9b334a45a8ff	508	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
bogdanm	0:9b334a45a8ff	509	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	512	{
bogdanm	0:9b334a45a8ff	513	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	514	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
bogdanm	0:9b334a45a8ff	515
bogdanm	0:9b334a45a8ff	516	/* Check if the automatic poll mode stop is activated */
bogdanm	0:9b334a45a8ff	517	if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
bogdanm	0:9b334a45a8ff	518	{
bogdanm	0:9b334a45a8ff	519	/* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
bogdanm	0:9b334a45a8ff	520	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_FT \| QSPI_IT_TE);
bogdanm	0:9b334a45a8ff	521
bogdanm	0:9b334a45a8ff	522	/* Change state of QSPI */
bogdanm	0:9b334a45a8ff	523	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	524	}
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	/* Status match callback */
bogdanm	0:9b334a45a8ff	527	HAL_QSPI_StatusMatchCallback(hqspi);
bogdanm	0:9b334a45a8ff	528	}
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/* QSPI Transfer Error interrupt occurred ----------------------------------*/
bogdanm	0:9b334a45a8ff	531	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
bogdanm	0:9b334a45a8ff	532	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
bogdanm	0:9b334a45a8ff	533
bogdanm	0:9b334a45a8ff	534	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	535	{
bogdanm	0:9b334a45a8ff	536	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	537	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	/* Disable all the QSPI Interrupts */
bogdanm	0:9b334a45a8ff	540	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	/* Set error code */
bogdanm	0:9b334a45a8ff	543	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TRANSFER;
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545	/* Change state of QSPI */
bogdanm	0:9b334a45a8ff	546	hqspi->State = HAL_QSPI_STATE_ERROR;
bogdanm	0:9b334a45a8ff	547
bogdanm	0:9b334a45a8ff	548	/* Error callback */
bogdanm	0:9b334a45a8ff	549	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	550	}
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	/* QSPI Time out interrupt occurred -----------------------------------------*/
bogdanm	0:9b334a45a8ff	553	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
bogdanm	0:9b334a45a8ff	554	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
bogdanm	0:9b334a45a8ff	555
bogdanm	0:9b334a45a8ff	556	if((flag != RESET) && (itsource != RESET))
bogdanm	0:9b334a45a8ff	557	{
bogdanm	0:9b334a45a8ff	558	/* Clear interrupt */
bogdanm	0:9b334a45a8ff	559	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
bogdanm	0:9b334a45a8ff	560
bogdanm	0:9b334a45a8ff	561	/* Time out callback */
bogdanm	0:9b334a45a8ff	562	HAL_QSPI_TimeOutCallback(hqspi);
bogdanm	0:9b334a45a8ff	563	}
bogdanm	0:9b334a45a8ff	564	}
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566	/**
bogdanm	0:9b334a45a8ff	567	* @brief Sets the command configuration.
bogdanm	0:9b334a45a8ff	568	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	569	* @param cmd : structure that contains the command configuration information
bogdanm	0:9b334a45a8ff	570	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	571	* @note This function is used only in Indirect Read or Write Modes
bogdanm	0:9b334a45a8ff	572	* @retval HAL status
bogdanm	0:9b334a45a8ff	573	*/
bogdanm	0:9b334a45a8ff	574	HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	575	{
bogdanm	0:9b334a45a8ff	576	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	/* Check the parameters */
bogdanm	0:9b334a45a8ff	579	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	580	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	581	{
bogdanm	0:9b334a45a8ff	582	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	583	}
bogdanm	0:9b334a45a8ff	584
bogdanm	0:9b334a45a8ff	585	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	586	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	587	{
bogdanm	0:9b334a45a8ff	588	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	589	}
bogdanm	0:9b334a45a8ff	590
bogdanm	0:9b334a45a8ff	591	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	592	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	593	{
bogdanm	0:9b334a45a8ff	594	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	595	}
bogdanm	0:9b334a45a8ff	596
bogdanm	0:9b334a45a8ff	597	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	598	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	599
bogdanm	0:9b334a45a8ff	600	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	601	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	602	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	603
bogdanm	0:9b334a45a8ff	604	/* Process locked */
bogdanm	0:9b334a45a8ff	605	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	608	{
bogdanm	0:9b334a45a8ff	609	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	610
bogdanm	0:9b334a45a8ff	611	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	612	hqspi->State = HAL_QSPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	613
bogdanm	0:9b334a45a8ff	614	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	615	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	618	{
bogdanm	0:9b334a45a8ff	619	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	620	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622	if (cmd->DataMode == QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	623	{
bogdanm	0:9b334a45a8ff	624	/* When there is no data phase, the transfer start as soon as the configuration is done
bogdanm	0:9b334a45a8ff	625	so wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	626	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	627	{
bogdanm	0:9b334a45a8ff	628	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	629	}
bogdanm	0:9b334a45a8ff	630	else
bogdanm	0:9b334a45a8ff	631	{
bogdanm	0:9b334a45a8ff	632	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	633
bogdanm	0:9b334a45a8ff	634	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	635	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	636	}
bogdanm	0:9b334a45a8ff	637
bogdanm	0:9b334a45a8ff	638	}
bogdanm	0:9b334a45a8ff	639	else
bogdanm	0:9b334a45a8ff	640	{
bogdanm	0:9b334a45a8ff	641	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	642	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	643	}
bogdanm	0:9b334a45a8ff	644	}
bogdanm	0:9b334a45a8ff	645	}
bogdanm	0:9b334a45a8ff	646	else
bogdanm	0:9b334a45a8ff	647	{
bogdanm	0:9b334a45a8ff	648	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	649	}
bogdanm	0:9b334a45a8ff	650
bogdanm	0:9b334a45a8ff	651	/* Process unlocked */
bogdanm	0:9b334a45a8ff	652	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	653
bogdanm	0:9b334a45a8ff	654	/* Return function status */
bogdanm	0:9b334a45a8ff	655	return status;
bogdanm	0:9b334a45a8ff	656	}
bogdanm	0:9b334a45a8ff	657
bogdanm	0:9b334a45a8ff	658	/**
bogdanm	0:9b334a45a8ff	659	* @brief Sets the command configuration in interrupt mode.
bogdanm	0:9b334a45a8ff	660	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	661	* @param cmd : structure that contains the command configuration information
bogdanm	0:9b334a45a8ff	662	* @note This function is used only in Indirect Read or Write Modes
bogdanm	0:9b334a45a8ff	663	* @retval HAL status
bogdanm	0:9b334a45a8ff	664	*/
bogdanm	0:9b334a45a8ff	665	HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd)
bogdanm	0:9b334a45a8ff	666	{
bogdanm	0:9b334a45a8ff	667	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	668
bogdanm	0:9b334a45a8ff	669	/* Check the parameters */
bogdanm	0:9b334a45a8ff	670	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	671	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	672	{
bogdanm	0:9b334a45a8ff	673	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	674	}
bogdanm	0:9b334a45a8ff	675
bogdanm	0:9b334a45a8ff	676	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	677	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	678	{
bogdanm	0:9b334a45a8ff	679	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	680	}
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	683	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	684	{
bogdanm	0:9b334a45a8ff	685	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	686	}
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	689	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	690
bogdanm	0:9b334a45a8ff	691	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	692	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	693	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	694
bogdanm	0:9b334a45a8ff	695	/* Process locked */
bogdanm	0:9b334a45a8ff	696	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	697
bogdanm	0:9b334a45a8ff	698	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	699	{
bogdanm	0:9b334a45a8ff	700	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	701
bogdanm	0:9b334a45a8ff	702	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	703	hqspi->State = HAL_QSPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	704
bogdanm	0:9b334a45a8ff	705	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	706	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	709	{
bogdanm	0:9b334a45a8ff	710	if (cmd->DataMode == QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	/* When there is no data phase, the transfer start as soon as the configuration is done
bogdanm	0:9b334a45a8ff	713	so activate TC and TE interrupts */
bogdanm	0:9b334a45a8ff	714	/* Enable the QSPI Transfer Error Interrupt */
bogdanm	0:9b334a45a8ff	715	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	716	}
bogdanm	0:9b334a45a8ff	717
bogdanm	0:9b334a45a8ff	718	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	719	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	if (cmd->DataMode != QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	722	{
bogdanm	0:9b334a45a8ff	723	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	724	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	725	}
bogdanm	0:9b334a45a8ff	726	}
bogdanm	0:9b334a45a8ff	727	}
bogdanm	0:9b334a45a8ff	728	else
bogdanm	0:9b334a45a8ff	729	{
bogdanm	0:9b334a45a8ff	730	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	731	}
bogdanm	0:9b334a45a8ff	732
bogdanm	0:9b334a45a8ff	733	/* Process unlocked */
bogdanm	0:9b334a45a8ff	734	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736	/* Return function status */
bogdanm	0:9b334a45a8ff	737	return status;
bogdanm	0:9b334a45a8ff	738	}
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	/**
bogdanm	0:9b334a45a8ff	741	* @brief Transmit an amount of data in blocking mode.
bogdanm	0:9b334a45a8ff	742	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	743	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	744	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	745	* @note This function is used only in Indirect Write Mode
bogdanm	0:9b334a45a8ff	746	* @retval HAL status
bogdanm	0:9b334a45a8ff	747	*/
bogdanm	0:9b334a45a8ff	748	HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	749	{
bogdanm	0:9b334a45a8ff	750	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	751	__IO uint32_t *data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	752
bogdanm	0:9b334a45a8ff	753	/* Process locked */
bogdanm	0:9b334a45a8ff	754	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	755
bogdanm	0:9b334a45a8ff	756	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	757	{
bogdanm	0:9b334a45a8ff	758	if(pData != NULL )
bogdanm	0:9b334a45a8ff	759	{
bogdanm	0:9b334a45a8ff	760	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	/* Update state */
bogdanm	0:9b334a45a8ff	763	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
bogdanm	0:9b334a45a8ff	764
bogdanm	0:9b334a45a8ff	765	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	766	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	767	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	768	hqspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	/* Configure QSPI: CCR register with functional as indirect write */
bogdanm	0:9b334a45a8ff	771	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	while(hqspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	774	{
bogdanm	0:9b334a45a8ff	775	/* Wait until FT flag is set to send data */
bogdanm	0:9b334a45a8ff	776	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	777	{
bogdanm	0:9b334a45a8ff	778	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	779	break;
bogdanm	0:9b334a45a8ff	780	}
bogdanm	0:9b334a45a8ff	781
bogdanm	0:9b334a45a8ff	782	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
bogdanm	0:9b334a45a8ff	783	hqspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	784	}
bogdanm	0:9b334a45a8ff	785
bogdanm	0:9b334a45a8ff	786	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	787	{
bogdanm	0:9b334a45a8ff	788	/* Wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	789	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	790	{
bogdanm	0:9b334a45a8ff	791	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	792	}
bogdanm	0:9b334a45a8ff	793	else
bogdanm	0:9b334a45a8ff	794	{
bogdanm	0:9b334a45a8ff	795	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	796	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	797
bogdanm	0:9b334a45a8ff	798	/* Clear Busy bit */
bogdanm	0:9b334a45a8ff	799	status = HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	800	}
bogdanm	0:9b334a45a8ff	801	}
bogdanm	0:9b334a45a8ff	802
bogdanm	0:9b334a45a8ff	803	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	804	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	805	}
bogdanm	0:9b334a45a8ff	806	else
bogdanm	0:9b334a45a8ff	807	{
bogdanm	0:9b334a45a8ff	808	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	809	}
bogdanm	0:9b334a45a8ff	810	}
bogdanm	0:9b334a45a8ff	811	else
bogdanm	0:9b334a45a8ff	812	{
bogdanm	0:9b334a45a8ff	813	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	814	}
bogdanm	0:9b334a45a8ff	815
bogdanm	0:9b334a45a8ff	816	/* Process unlocked */
bogdanm	0:9b334a45a8ff	817	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	818
bogdanm	0:9b334a45a8ff	819	return status;
bogdanm	0:9b334a45a8ff	820	}
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	/**
bogdanm	0:9b334a45a8ff	824	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	825	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	826	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	827	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	828	* @note This function is used only in Indirect Read Mode
bogdanm	0:9b334a45a8ff	829	* @retval HAL status
bogdanm	0:9b334a45a8ff	830	*/
bogdanm	0:9b334a45a8ff	831	HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	832	{
bogdanm	0:9b334a45a8ff	833	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	834	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
bogdanm	0:9b334a45a8ff	835	__IO uint32_t *data_reg = &hqspi->Instance->DR;
bogdanm	0:9b334a45a8ff	836
bogdanm	0:9b334a45a8ff	837	/* Process locked */
bogdanm	0:9b334a45a8ff	838	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	841	{
bogdanm	0:9b334a45a8ff	842	if(pData != NULL )
bogdanm	0:9b334a45a8ff	843	{
bogdanm	0:9b334a45a8ff	844	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	/* Update state */
bogdanm	0:9b334a45a8ff	847	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
bogdanm	0:9b334a45a8ff	848
bogdanm	0:9b334a45a8ff	849	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	850	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	851	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	852	hqspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	/* Configure QSPI: CCR register with functional as indirect read */
bogdanm	0:9b334a45a8ff	855	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/* Start the transfer by re-writing the address in AR register */
bogdanm	0:9b334a45a8ff	858	WRITE_REG(hqspi->Instance->AR, addr_reg);
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	while(hqspi->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	861	{
bogdanm	0:9b334a45a8ff	862	/* Wait until FT or TC flag is set to read received data */
bogdanm	0:9b334a45a8ff	863	if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT \| QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	864	{
bogdanm	0:9b334a45a8ff	865	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	866	break;
bogdanm	0:9b334a45a8ff	867	}
bogdanm	0:9b334a45a8ff	868
bogdanm	0:9b334a45a8ff	869	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
bogdanm	0:9b334a45a8ff	870	hqspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	871	}
bogdanm	0:9b334a45a8ff	872
bogdanm	0:9b334a45a8ff	873	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	874	{
bogdanm	0:9b334a45a8ff	875	/* Wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	876	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	877	{
bogdanm	0:9b334a45a8ff	878	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	879	}
bogdanm	0:9b334a45a8ff	880	else
bogdanm	0:9b334a45a8ff	881	{
bogdanm	0:9b334a45a8ff	882	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	883	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
bogdanm	0:9b334a45a8ff	886	status = HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	887	}
bogdanm	0:9b334a45a8ff	888	}
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/* Update QSPI state */
bogdanm	0:9b334a45a8ff	891	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	892	}
bogdanm	0:9b334a45a8ff	893	else
bogdanm	0:9b334a45a8ff	894	{
bogdanm	0:9b334a45a8ff	895	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	896	}
bogdanm	0:9b334a45a8ff	897	}
bogdanm	0:9b334a45a8ff	898	else
bogdanm	0:9b334a45a8ff	899	{
bogdanm	0:9b334a45a8ff	900	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	901	}
bogdanm	0:9b334a45a8ff	902
bogdanm	0:9b334a45a8ff	903	/* Process unlocked */
bogdanm	0:9b334a45a8ff	904	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	905
bogdanm	0:9b334a45a8ff	906	return status;
bogdanm	0:9b334a45a8ff	907	}
bogdanm	0:9b334a45a8ff	908
bogdanm	0:9b334a45a8ff	909	/**
bogdanm	0:9b334a45a8ff	910	* @brief Send an amount of data in interrupt mode
bogdanm	0:9b334a45a8ff	911	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	912	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	913	* @note This function is used only in Indirect Write Mode
bogdanm	0:9b334a45a8ff	914	* @retval HAL status
bogdanm	0:9b334a45a8ff	915	*/
bogdanm	0:9b334a45a8ff	916	HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	917	{
bogdanm	0:9b334a45a8ff	918	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	919
bogdanm	0:9b334a45a8ff	920	/* Process locked */
bogdanm	0:9b334a45a8ff	921	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	924	{
bogdanm	0:9b334a45a8ff	925	if(pData != NULL )
bogdanm	0:9b334a45a8ff	926	{
bogdanm	0:9b334a45a8ff	927	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	/* Update state */
bogdanm	0:9b334a45a8ff	930	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	933	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	934	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	935	hqspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	936
bogdanm	0:9b334a45a8ff	937	/* Configure QSPI: CCR register with functional as indirect write */
bogdanm	0:9b334a45a8ff	938	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	939
bogdanm	0:9b334a45a8ff	940	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
bogdanm	0:9b334a45a8ff	941	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	942
bogdanm	0:9b334a45a8ff	943	}
bogdanm	0:9b334a45a8ff	944	else
bogdanm	0:9b334a45a8ff	945	{
bogdanm	0:9b334a45a8ff	946	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	947	}
bogdanm	0:9b334a45a8ff	948	}
bogdanm	0:9b334a45a8ff	949	else
bogdanm	0:9b334a45a8ff	950	{
bogdanm	0:9b334a45a8ff	951	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	952	}
bogdanm	0:9b334a45a8ff	953
bogdanm	0:9b334a45a8ff	954	/* Process unlocked */
bogdanm	0:9b334a45a8ff	955	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	956
bogdanm	0:9b334a45a8ff	957	return status;
bogdanm	0:9b334a45a8ff	958	}
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	/**
bogdanm	0:9b334a45a8ff	961	* @brief Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	962	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	963	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	964	* @note This function is used only in Indirect Read Mode
bogdanm	0:9b334a45a8ff	965	* @retval HAL status
bogdanm	0:9b334a45a8ff	966	*/
bogdanm	0:9b334a45a8ff	967	HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	968	{
bogdanm	0:9b334a45a8ff	969	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	970	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/* Process locked */
bogdanm	0:9b334a45a8ff	973	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	974
bogdanm	0:9b334a45a8ff	975	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	976	{
bogdanm	0:9b334a45a8ff	977	if(pData != NULL )
bogdanm	0:9b334a45a8ff	978	{
bogdanm	0:9b334a45a8ff	979	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	980
bogdanm	0:9b334a45a8ff	981	/* Update state */
bogdanm	0:9b334a45a8ff	982	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
bogdanm	0:9b334a45a8ff	983
bogdanm	0:9b334a45a8ff	984	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	985	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	986	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	987	hqspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	/* Configure QSPI: CCR register with functional as indirect read */
bogdanm	0:9b334a45a8ff	990	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	/* Start the transfer by re-writing the address in AR register */
bogdanm	0:9b334a45a8ff	993	WRITE_REG(hqspi->Instance->AR, addr_reg);
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
bogdanm	0:9b334a45a8ff	996	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
bogdanm	0:9b334a45a8ff	997	}
bogdanm	0:9b334a45a8ff	998	else
bogdanm	0:9b334a45a8ff	999	{
bogdanm	0:9b334a45a8ff	1000	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1001	}
bogdanm	0:9b334a45a8ff	1002	}
bogdanm	0:9b334a45a8ff	1003	else
bogdanm	0:9b334a45a8ff	1004	{
bogdanm	0:9b334a45a8ff	1005	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1006	}
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1009	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1010
bogdanm	0:9b334a45a8ff	1011	return status;
bogdanm	0:9b334a45a8ff	1012	}
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/**
bogdanm	0:9b334a45a8ff	1015	* @brief Sends an amount of data in non blocking mode with DMA.
bogdanm	0:9b334a45a8ff	1016	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1017	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1018	* @note This function is used only in Indirect Write Mode
bogdanm	0:9b334a45a8ff	1019	* @retval HAL status
bogdanm	0:9b334a45a8ff	1020	*/
bogdanm	0:9b334a45a8ff	1021	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	1022	{
bogdanm	0:9b334a45a8ff	1023	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	1024	uint32_t *tmp;
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/* Process locked */
bogdanm	0:9b334a45a8ff	1027	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1028
bogdanm	0:9b334a45a8ff	1029	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1030	{
bogdanm	0:9b334a45a8ff	1031	if(pData != NULL )
bogdanm	0:9b334a45a8ff	1032	{
bogdanm	0:9b334a45a8ff	1033	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	/* Update state */
bogdanm	0:9b334a45a8ff	1036	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
bogdanm	0:9b334a45a8ff	1037
bogdanm	0:9b334a45a8ff	1038	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	1039	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1040	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1041	hqspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	/* Configure QSPI: CCR register with functional mode as indirect write */
bogdanm	0:9b334a45a8ff	1044	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
bogdanm	0:9b334a45a8ff	1045
bogdanm	0:9b334a45a8ff	1046	/* Set the QSPI DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1047	hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	/* Set the QSPI DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1050	hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
bogdanm	0:9b334a45a8ff	1051
bogdanm	0:9b334a45a8ff	1052	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1053	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
bogdanm	0:9b334a45a8ff	1054
bogdanm	0:9b334a45a8ff	1055	/* Configure the direction of the DMA */
bogdanm	0:9b334a45a8ff	1056	hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
bogdanm	0:9b334a45a8ff	1057	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
bogdanm	0:9b334a45a8ff	1058
bogdanm	0:9b334a45a8ff	1059	/* Enable the QSPI transmit DMA Channel */
bogdanm	0:9b334a45a8ff	1060	tmp = (uint32_t*)&pData;
bogdanm	0:9b334a45a8ff	1061	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1064	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1065	}
bogdanm	0:9b334a45a8ff	1066	else
bogdanm	0:9b334a45a8ff	1067	{
bogdanm	0:9b334a45a8ff	1068	status = HAL_OK;
bogdanm	0:9b334a45a8ff	1069	}
bogdanm	0:9b334a45a8ff	1070	}
bogdanm	0:9b334a45a8ff	1071	else
bogdanm	0:9b334a45a8ff	1072	{
bogdanm	0:9b334a45a8ff	1073	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1074	}
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1077	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1078
bogdanm	0:9b334a45a8ff	1079	return status;
bogdanm	0:9b334a45a8ff	1080	}
bogdanm	0:9b334a45a8ff	1081
bogdanm	0:9b334a45a8ff	1082	/**
bogdanm	0:9b334a45a8ff	1083	* @brief Receives an amount of data in non blocking mode with DMA.
bogdanm	0:9b334a45a8ff	1084	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1085	* @param pData: pointer to data buffer.
bogdanm	0:9b334a45a8ff	1086	* @note This function is used only in Indirect Read Mode
bogdanm	0:9b334a45a8ff	1087	* @retval HAL status
bogdanm	0:9b334a45a8ff	1088	*/
bogdanm	0:9b334a45a8ff	1089	HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
bogdanm	0:9b334a45a8ff	1090	{
bogdanm	0:9b334a45a8ff	1091	HAL_StatusTypeDef status = HAL_OK;
bogdanm	0:9b334a45a8ff	1092	uint32_t *tmp;
bogdanm	0:9b334a45a8ff	1093	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	/* Process locked */
bogdanm	0:9b334a45a8ff	1096	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1097
bogdanm	0:9b334a45a8ff	1098	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1099	{
bogdanm	0:9b334a45a8ff	1100	if(pData != NULL )
bogdanm	0:9b334a45a8ff	1101	{
bogdanm	0:9b334a45a8ff	1102	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1103
bogdanm	0:9b334a45a8ff	1104	/* Update state */
bogdanm	0:9b334a45a8ff	1105	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	/* Configure counters and size of the handle */
bogdanm	0:9b334a45a8ff	1108	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1109	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
bogdanm	0:9b334a45a8ff	1110	hqspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112	/* Set the QSPI DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1113	hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
bogdanm	0:9b334a45a8ff	1114
bogdanm	0:9b334a45a8ff	1115	/* Set the QSPI DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1116	hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
bogdanm	0:9b334a45a8ff	1117
bogdanm	0:9b334a45a8ff	1118	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1119	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
bogdanm	0:9b334a45a8ff	1120
bogdanm	0:9b334a45a8ff	1121	/* Configure the direction of the DMA */
bogdanm	0:9b334a45a8ff	1122	hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
bogdanm	0:9b334a45a8ff	1123	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
bogdanm	0:9b334a45a8ff	1124
bogdanm	0:9b334a45a8ff	1125	/* Enable the DMA Channel */
bogdanm	0:9b334a45a8ff	1126	tmp = (uint32_t*)&pData;
bogdanm	0:9b334a45a8ff	1127	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)tmp, hqspi->RxXferSize);
bogdanm	0:9b334a45a8ff	1128
bogdanm	0:9b334a45a8ff	1129	/* Configure QSPI: CCR register with functional as indirect read */
bogdanm	0:9b334a45a8ff	1130	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
bogdanm	0:9b334a45a8ff	1131
bogdanm	0:9b334a45a8ff	1132	/* Start the transfer by re-writing the address in AR register */
bogdanm	0:9b334a45a8ff	1133	WRITE_REG(hqspi->Instance->AR, addr_reg);
bogdanm	0:9b334a45a8ff	1134
bogdanm	0:9b334a45a8ff	1135	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1136	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1137	}
bogdanm	0:9b334a45a8ff	1138	else
bogdanm	0:9b334a45a8ff	1139	{
bogdanm	0:9b334a45a8ff	1140	status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1141	}
bogdanm	0:9b334a45a8ff	1142	}
bogdanm	0:9b334a45a8ff	1143	else
bogdanm	0:9b334a45a8ff	1144	{
bogdanm	0:9b334a45a8ff	1145	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1146	}
bogdanm	0:9b334a45a8ff	1147
bogdanm	0:9b334a45a8ff	1148	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1149	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	return status;
bogdanm	0:9b334a45a8ff	1152	}
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	/**
bogdanm	0:9b334a45a8ff	1155	* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
bogdanm	0:9b334a45a8ff	1156	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1157	* @param cmd: structure that contains the command configuration information.
bogdanm	0:9b334a45a8ff	1158	* @param cfg: structure that contains the polling configuration information.
bogdanm	0:9b334a45a8ff	1159	* @param Timeout : Time out duration
bogdanm	0:9b334a45a8ff	1160	* @note This function is used only in Automatic Polling Mode
bogdanm	0:9b334a45a8ff	1161	* @retval HAL status
bogdanm	0:9b334a45a8ff	1162	*/
bogdanm	0:9b334a45a8ff	1163	HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1164	{
bogdanm	0:9b334a45a8ff	1165	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1166
bogdanm	0:9b334a45a8ff	1167	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1168	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	1169	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1170	{
bogdanm	0:9b334a45a8ff	1171	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	1172	}
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	1175	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1176	{
bogdanm	0:9b334a45a8ff	1177	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	1178	}
bogdanm	0:9b334a45a8ff	1179
bogdanm	0:9b334a45a8ff	1180	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	1181	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1182	{
bogdanm	0:9b334a45a8ff	1183	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	1184	}
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	1187	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	1190	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	1191	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
bogdanm	0:9b334a45a8ff	1194	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
bogdanm	0:9b334a45a8ff	1195	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
bogdanm	0:9b334a45a8ff	1196
bogdanm	0:9b334a45a8ff	1197	/* Process locked */
bogdanm	0:9b334a45a8ff	1198	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1199
bogdanm	0:9b334a45a8ff	1200	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1201	{
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1204
bogdanm	0:9b334a45a8ff	1205	/* Update state */
bogdanm	0:9b334a45a8ff	1206	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
bogdanm	0:9b334a45a8ff	1207
bogdanm	0:9b334a45a8ff	1208	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	1209	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
bogdanm	0:9b334a45a8ff	1210
bogdanm	0:9b334a45a8ff	1211	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	1212	{
bogdanm	0:9b334a45a8ff	1213	/* Configure QSPI: PSMAR register with the status match value */
bogdanm	0:9b334a45a8ff	1214	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
bogdanm	0:9b334a45a8ff	1215
bogdanm	0:9b334a45a8ff	1216	/* Configure QSPI: PSMKR register with the status mask value */
bogdanm	0:9b334a45a8ff	1217	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219	/* Configure QSPI: PIR register with the interval value */
bogdanm	0:9b334a45a8ff	1220	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	/* Configure QSPI: CR register with Match mode and Automatic stop enabled
bogdanm	0:9b334a45a8ff	1223	(otherwise there will be an infinite loop in blocking mode) */
bogdanm	0:9b334a45a8ff	1224	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
bogdanm	0:9b334a45a8ff	1225	(cfg->MatchMode \| QSPI_AUTOMATIC_STOP_ENABLE));
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	1228	cmd->NbData = cfg->StatusBytesSize;
bogdanm	0:9b334a45a8ff	1229	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231	/* Wait until SM flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	1232	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1233	{
bogdanm	0:9b334a45a8ff	1234	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1235	}
bogdanm	0:9b334a45a8ff	1236	else
bogdanm	0:9b334a45a8ff	1237	{
bogdanm	0:9b334a45a8ff	1238	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/* Update state */
bogdanm	0:9b334a45a8ff	1241	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1242	}
bogdanm	0:9b334a45a8ff	1243	}
bogdanm	0:9b334a45a8ff	1244	}
bogdanm	0:9b334a45a8ff	1245	else
bogdanm	0:9b334a45a8ff	1246	{
bogdanm	0:9b334a45a8ff	1247	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1248	}
bogdanm	0:9b334a45a8ff	1249	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1250	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1251
bogdanm	0:9b334a45a8ff	1252	/* Return function status */
bogdanm	0:9b334a45a8ff	1253	return status;
bogdanm	0:9b334a45a8ff	1254	}
bogdanm	0:9b334a45a8ff	1255
bogdanm	0:9b334a45a8ff	1256	/**
bogdanm	0:9b334a45a8ff	1257	* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
bogdanm	0:9b334a45a8ff	1258	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1259	* @param cmd: structure that contains the command configuration information.
bogdanm	0:9b334a45a8ff	1260	* @param cfg: structure that contains the polling configuration information.
bogdanm	0:9b334a45a8ff	1261	* @note This function is used only in Automatic Polling Mode
bogdanm	0:9b334a45a8ff	1262	* @retval HAL status
bogdanm	0:9b334a45a8ff	1263	*/
bogdanm	0:9b334a45a8ff	1264	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg)
bogdanm	0:9b334a45a8ff	1265	{
bogdanm	0:9b334a45a8ff	1266	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1269	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	1270	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1271	{
bogdanm	0:9b334a45a8ff	1272	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	1273	}
bogdanm	0:9b334a45a8ff	1274
bogdanm	0:9b334a45a8ff	1275	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	1276	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1277	{
bogdanm	0:9b334a45a8ff	1278	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	1279	}
bogdanm	0:9b334a45a8ff	1280
bogdanm	0:9b334a45a8ff	1281	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	1282	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1283	{
bogdanm	0:9b334a45a8ff	1284	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	1285	}
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	1288	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	1289
bogdanm	0:9b334a45a8ff	1290	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	1291	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	1292	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	1293
bogdanm	0:9b334a45a8ff	1294	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
bogdanm	0:9b334a45a8ff	1295	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
bogdanm	0:9b334a45a8ff	1296	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
bogdanm	0:9b334a45a8ff	1297	assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
bogdanm	0:9b334a45a8ff	1298
bogdanm	0:9b334a45a8ff	1299	/* Process locked */
bogdanm	0:9b334a45a8ff	1300	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1301
bogdanm	0:9b334a45a8ff	1302	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1303	{
bogdanm	0:9b334a45a8ff	1304	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1305
bogdanm	0:9b334a45a8ff	1306	/* Update state */
bogdanm	0:9b334a45a8ff	1307	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
bogdanm	0:9b334a45a8ff	1308
bogdanm	0:9b334a45a8ff	1309	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	1310	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	1313	{
bogdanm	0:9b334a45a8ff	1314	/* Configure QSPI: PSMAR register with the status match value */
bogdanm	0:9b334a45a8ff	1315	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317	/* Configure QSPI: PSMKR register with the status mask value */
bogdanm	0:9b334a45a8ff	1318	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
bogdanm	0:9b334a45a8ff	1319
bogdanm	0:9b334a45a8ff	1320	/* Configure QSPI: PIR register with the interval value */
bogdanm	0:9b334a45a8ff	1321	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
bogdanm	0:9b334a45a8ff	1322
bogdanm	0:9b334a45a8ff	1323	/* Configure QSPI: CR register with Match mode and Automatic stop mode */
bogdanm	0:9b334a45a8ff	1324	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
bogdanm	0:9b334a45a8ff	1325	(cfg->MatchMode \| cfg->AutomaticStop));
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	1328	cmd->NbData = cfg->StatusBytesSize;
bogdanm	0:9b334a45a8ff	1329	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
bogdanm	0:9b334a45a8ff	1330
bogdanm	0:9b334a45a8ff	1331	/* Enable the QSPI Transfer Error, FIFO threshold and status match Interrupt */
bogdanm	0:9b334a45a8ff	1332	__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_FT \| QSPI_IT_SM \| QSPI_IT_TE));
bogdanm	0:9b334a45a8ff	1333	}
bogdanm	0:9b334a45a8ff	1334	}
bogdanm	0:9b334a45a8ff	1335	else
bogdanm	0:9b334a45a8ff	1336	{
bogdanm	0:9b334a45a8ff	1337	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1338	}
bogdanm	0:9b334a45a8ff	1339
bogdanm	0:9b334a45a8ff	1340	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1341	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1342
bogdanm	0:9b334a45a8ff	1343	/* Return function status */
bogdanm	0:9b334a45a8ff	1344	return status;
bogdanm	0:9b334a45a8ff	1345	}
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/**
bogdanm	0:9b334a45a8ff	1348	* @brief Configure the Memory Mapped mode.
bogdanm	0:9b334a45a8ff	1349	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1350	* @param cmd: structure that contains the command configuration information.
bogdanm	0:9b334a45a8ff	1351	* @param cfg: structure that contains the memory mapped configuration information.
bogdanm	0:9b334a45a8ff	1352	* @note This function is used only in Memory mapped Mode
bogdanm	0:9b334a45a8ff	1353	* @retval HAL status
bogdanm	0:9b334a45a8ff	1354	*/
bogdanm	0:9b334a45a8ff	1355	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg)
bogdanm	0:9b334a45a8ff	1356	{
bogdanm	0:9b334a45a8ff	1357	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1358
bogdanm	0:9b334a45a8ff	1359	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1360	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
bogdanm	0:9b334a45a8ff	1361	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1362	{
bogdanm	0:9b334a45a8ff	1363	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
bogdanm	0:9b334a45a8ff	1364	}
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
bogdanm	0:9b334a45a8ff	1367	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1368	{
bogdanm	0:9b334a45a8ff	1369	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
bogdanm	0:9b334a45a8ff	1370	}
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
bogdanm	0:9b334a45a8ff	1373	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1374	{
bogdanm	0:9b334a45a8ff	1375	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
bogdanm	0:9b334a45a8ff	1376	}
bogdanm	0:9b334a45a8ff	1377
bogdanm	0:9b334a45a8ff	1378	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
bogdanm	0:9b334a45a8ff	1379	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
bogdanm	0:9b334a45a8ff	1380
bogdanm	0:9b334a45a8ff	1381	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
bogdanm	0:9b334a45a8ff	1382	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
bogdanm	0:9b334a45a8ff	1383	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
bogdanm	0:9b334a45a8ff	1384
bogdanm	0:9b334a45a8ff	1385	assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	/* Process locked */
bogdanm	0:9b334a45a8ff	1388	__HAL_LOCK(hqspi);
bogdanm	0:9b334a45a8ff	1389
bogdanm	0:9b334a45a8ff	1390	if(hqspi->State == HAL_QSPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1391	{
bogdanm	0:9b334a45a8ff	1392	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1393
bogdanm	0:9b334a45a8ff	1394	/* Update state */
bogdanm	0:9b334a45a8ff	1395	hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
bogdanm	0:9b334a45a8ff	1396
bogdanm	0:9b334a45a8ff	1397	/* Wait till BUSY flag reset */
bogdanm	0:9b334a45a8ff	1398	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	1399
bogdanm	0:9b334a45a8ff	1400	if (status == HAL_OK)
bogdanm	0:9b334a45a8ff	1401	{
bogdanm	0:9b334a45a8ff	1402	/* Configure QSPI: CR register with time out counter enable */
bogdanm	0:9b334a45a8ff	1403	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
bogdanm	0:9b334a45a8ff	1404
bogdanm	0:9b334a45a8ff	1405	if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
bogdanm	0:9b334a45a8ff	1406	{
bogdanm	0:9b334a45a8ff	1407	assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	/* Configure QSPI: LPTR register with the low-power time out value */
bogdanm	0:9b334a45a8ff	1410	WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	/* Enable the QSPI TimeOut Interrupt */
bogdanm	0:9b334a45a8ff	1413	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
bogdanm	0:9b334a45a8ff	1414	}
bogdanm	0:9b334a45a8ff	1415
bogdanm	0:9b334a45a8ff	1416	/* Call the configuration function */
bogdanm	0:9b334a45a8ff	1417	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
bogdanm	0:9b334a45a8ff	1418
bogdanm	0:9b334a45a8ff	1419	}
bogdanm	0:9b334a45a8ff	1420	}
bogdanm	0:9b334a45a8ff	1421	else
bogdanm	0:9b334a45a8ff	1422	{
bogdanm	0:9b334a45a8ff	1423	status = HAL_BUSY;
bogdanm	0:9b334a45a8ff	1424
bogdanm	0:9b334a45a8ff	1425	}
bogdanm	0:9b334a45a8ff	1426
bogdanm	0:9b334a45a8ff	1427	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1428	__HAL_UNLOCK(hqspi);
bogdanm	0:9b334a45a8ff	1429
bogdanm	0:9b334a45a8ff	1430	/* Return function status */
bogdanm	0:9b334a45a8ff	1431	return status;
bogdanm	0:9b334a45a8ff	1432	}
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	/**
bogdanm	0:9b334a45a8ff	1435	* @brief Transfer Error callbacks
bogdanm	0:9b334a45a8ff	1436	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1437	* @retval None
bogdanm	0:9b334a45a8ff	1438	*/
bogdanm	0:9b334a45a8ff	1439	__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1440	{
bogdanm	0:9b334a45a8ff	1441	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1442	the HAL_QSPI_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1443	*/
bogdanm	0:9b334a45a8ff	1444	}
bogdanm	0:9b334a45a8ff	1445
bogdanm	0:9b334a45a8ff	1446	/**
bogdanm	0:9b334a45a8ff	1447	* @brief Command completed callbacks.
bogdanm	0:9b334a45a8ff	1448	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1449	* @retval None
bogdanm	0:9b334a45a8ff	1450	*/
bogdanm	0:9b334a45a8ff	1451	__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1452	{
bogdanm	0:9b334a45a8ff	1453	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1454	the HAL_QSPI_CmdCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1455	*/
bogdanm	0:9b334a45a8ff	1456	}
bogdanm	0:9b334a45a8ff	1457
bogdanm	0:9b334a45a8ff	1458	/**
bogdanm	0:9b334a45a8ff	1459	* @brief Rx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1460	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1461	* @retval None
bogdanm	0:9b334a45a8ff	1462	*/
bogdanm	0:9b334a45a8ff	1463	__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1464	{
bogdanm	0:9b334a45a8ff	1465	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1466	the HAL_QSPI_RxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1467	*/
bogdanm	0:9b334a45a8ff	1468	}
bogdanm	0:9b334a45a8ff	1469
bogdanm	0:9b334a45a8ff	1470	/**
bogdanm	0:9b334a45a8ff	1471	* @brief Tx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1472	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1473	* @retval None
bogdanm	0:9b334a45a8ff	1474	*/
bogdanm	0:9b334a45a8ff	1475	__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1476	{
bogdanm	0:9b334a45a8ff	1477	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1478	the HAL_QSPI_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1479	*/
bogdanm	0:9b334a45a8ff	1480	}
bogdanm	0:9b334a45a8ff	1481
bogdanm	0:9b334a45a8ff	1482	/**
bogdanm	0:9b334a45a8ff	1483	* @brief Rx Half Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1484	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1485	* @retval None
bogdanm	0:9b334a45a8ff	1486	*/
bogdanm	0:9b334a45a8ff	1487	__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1488	{
bogdanm	0:9b334a45a8ff	1489	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1490	the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1491	*/
bogdanm	0:9b334a45a8ff	1492	}
bogdanm	0:9b334a45a8ff	1493
bogdanm	0:9b334a45a8ff	1494	/**
bogdanm	0:9b334a45a8ff	1495	* @brief Tx Half Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	1496	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1497	* @retval None
bogdanm	0:9b334a45a8ff	1498	*/
bogdanm	0:9b334a45a8ff	1499	__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1500	{
bogdanm	0:9b334a45a8ff	1501	/* NOTE: This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1502	the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1503	*/
bogdanm	0:9b334a45a8ff	1504	}
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	/**
bogdanm	0:9b334a45a8ff	1507	* @brief FIFO Threshold callbacks
bogdanm	0:9b334a45a8ff	1508	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1509	* @retval None
bogdanm	0:9b334a45a8ff	1510	*/
bogdanm	0:9b334a45a8ff	1511	__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1512	{
bogdanm	0:9b334a45a8ff	1513	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1514	the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1515	*/
bogdanm	0:9b334a45a8ff	1516	}
bogdanm	0:9b334a45a8ff	1517
bogdanm	0:9b334a45a8ff	1518	/**
bogdanm	0:9b334a45a8ff	1519	* @brief Status Match callbacks
bogdanm	0:9b334a45a8ff	1520	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1521	* @retval None
bogdanm	0:9b334a45a8ff	1522	*/
bogdanm	0:9b334a45a8ff	1523	__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1524	{
bogdanm	0:9b334a45a8ff	1525	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1526	the HAL_QSPI_StatusMatchCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1527	*/
bogdanm	0:9b334a45a8ff	1528	}
bogdanm	0:9b334a45a8ff	1529
bogdanm	0:9b334a45a8ff	1530	/**
bogdanm	0:9b334a45a8ff	1531	* @brief Timeout callbacks
bogdanm	0:9b334a45a8ff	1532	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1533	* @retval None
bogdanm	0:9b334a45a8ff	1534	*/
bogdanm	0:9b334a45a8ff	1535	__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1536	{
bogdanm	0:9b334a45a8ff	1537	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1538	the HAL_QSPI_TimeOutCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1539	*/
bogdanm	0:9b334a45a8ff	1540	}
bogdanm	0:9b334a45a8ff	1541
bogdanm	0:9b334a45a8ff	1542	/**
bogdanm	0:9b334a45a8ff	1543	* @}
bogdanm	0:9b334a45a8ff	1544	*/
bogdanm	0:9b334a45a8ff	1545
bogdanm	0:9b334a45a8ff	1546	/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
bogdanm	0:9b334a45a8ff	1547	* @brief QSPI control and State functions
bogdanm	0:9b334a45a8ff	1548	*
bogdanm	0:9b334a45a8ff	1549	@verbatim
bogdanm	0:9b334a45a8ff	1550	===============================================================================
bogdanm	0:9b334a45a8ff	1551	##### Peripheral Control and State functions #####
bogdanm	0:9b334a45a8ff	1552	===============================================================================
bogdanm	0:9b334a45a8ff	1553	[..]
bogdanm	0:9b334a45a8ff	1554	This subsection provides a set of functions allowing to :
bogdanm	0:9b334a45a8ff	1555	(+) Check in run-time the state of the driver.
bogdanm	0:9b334a45a8ff	1556	(+) Check the error code set during last operation.
bogdanm	0:9b334a45a8ff	1557	(+) Abort any operation.
bogdanm	0:9b334a45a8ff	1558	.....
bogdanm	0:9b334a45a8ff	1559	@endverbatim
bogdanm	0:9b334a45a8ff	1560	* @{
bogdanm	0:9b334a45a8ff	1561	*/
bogdanm	0:9b334a45a8ff	1562
bogdanm	0:9b334a45a8ff	1563	/**
bogdanm	0:9b334a45a8ff	1564	* @brief Return the QSPI state.
bogdanm	0:9b334a45a8ff	1565	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1566	* @retval HAL state
bogdanm	0:9b334a45a8ff	1567	*/
bogdanm	0:9b334a45a8ff	1568	HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1569	{
bogdanm	0:9b334a45a8ff	1570	return hqspi->State;
bogdanm	0:9b334a45a8ff	1571	}
bogdanm	0:9b334a45a8ff	1572
bogdanm	0:9b334a45a8ff	1573	/**
bogdanm	0:9b334a45a8ff	1574	* @brief Return the QSPI error code
bogdanm	0:9b334a45a8ff	1575	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1576	* @retval QSPI Error Code
bogdanm	0:9b334a45a8ff	1577	*/
bogdanm	0:9b334a45a8ff	1578	uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1579	{
bogdanm	0:9b334a45a8ff	1580	return hqspi->ErrorCode;
bogdanm	0:9b334a45a8ff	1581	}
bogdanm	0:9b334a45a8ff	1582
bogdanm	0:9b334a45a8ff	1583	/**
bogdanm	0:9b334a45a8ff	1584	* @brief Abort the current transmission
bogdanm	0:9b334a45a8ff	1585	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1586	* @retval HAL status
bogdanm	0:9b334a45a8ff	1587	*/
bogdanm	0:9b334a45a8ff	1588	HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
bogdanm	0:9b334a45a8ff	1589	{
bogdanm	0:9b334a45a8ff	1590	HAL_StatusTypeDef status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1591
bogdanm	0:9b334a45a8ff	1592	/* Configure QSPI: CR register with Abort request */
bogdanm	0:9b334a45a8ff	1593	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
bogdanm	0:9b334a45a8ff	1594
bogdanm	0:9b334a45a8ff	1595	/* Wait until TC flag is set to go back in idle state */
bogdanm	0:9b334a45a8ff	1596	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1597	{
bogdanm	0:9b334a45a8ff	1598	status = HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1599	}
bogdanm	0:9b334a45a8ff	1600	else
bogdanm	0:9b334a45a8ff	1601	{
bogdanm	0:9b334a45a8ff	1602	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	1603
bogdanm	0:9b334a45a8ff	1604	/* Wait until BUSY flag is reset */
bogdanm	0:9b334a45a8ff	1605	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
bogdanm	0:9b334a45a8ff	1606
bogdanm	0:9b334a45a8ff	1607	/* Update state */
bogdanm	0:9b334a45a8ff	1608	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1609	}
bogdanm	0:9b334a45a8ff	1610
bogdanm	0:9b334a45a8ff	1611	return status;
bogdanm	0:9b334a45a8ff	1612	}
bogdanm	0:9b334a45a8ff	1613
bogdanm	0:9b334a45a8ff	1614	/** @brief Set QSPI timeout
bogdanm	0:9b334a45a8ff	1615	* @param hqspi: QSPI handle.
bogdanm	0:9b334a45a8ff	1616	* @param Timeout: Timeout for the QSPI memory access.
bogdanm	0:9b334a45a8ff	1617	* @retval None
bogdanm	0:9b334a45a8ff	1618	*/
bogdanm	0:9b334a45a8ff	1619	void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1620	{
bogdanm	0:9b334a45a8ff	1621	hqspi->Timeout = Timeout;
bogdanm	0:9b334a45a8ff	1622	}
bogdanm	0:9b334a45a8ff	1623
bogdanm	0:9b334a45a8ff	1624	/**
bogdanm	0:9b334a45a8ff	1625	* @}
bogdanm	0:9b334a45a8ff	1626	*/
bogdanm	0:9b334a45a8ff	1627
bogdanm	0:9b334a45a8ff	1628	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1629
bogdanm	0:9b334a45a8ff	1630	/**
bogdanm	0:9b334a45a8ff	1631	* @brief DMA QSPI receive process complete callback.
bogdanm	0:9b334a45a8ff	1632	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	1633	* @retval None
bogdanm	0:9b334a45a8ff	1634	*/
bogdanm	0:9b334a45a8ff	1635	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1636	{
bogdanm	0:9b334a45a8ff	1637	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1638	hqspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1639
bogdanm	0:9b334a45a8ff	1640	/* Wait for QSPI TC Flag */
bogdanm	0:9b334a45a8ff	1641	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1642	{
bogdanm	0:9b334a45a8ff	1643	/* Time out Occurred */
bogdanm	0:9b334a45a8ff	1644	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	1645	}
bogdanm	0:9b334a45a8ff	1646	else
bogdanm	0:9b334a45a8ff	1647	{
bogdanm	0:9b334a45a8ff	1648	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1649	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1650
bogdanm	0:9b334a45a8ff	1651	/* Disable the DMA channel */
bogdanm	0:9b334a45a8ff	1652	HAL_DMA_Abort(hdma);
bogdanm	0:9b334a45a8ff	1653
bogdanm	0:9b334a45a8ff	1654	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	1655	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	1656
bogdanm	0:9b334a45a8ff	1657	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
bogdanm	0:9b334a45a8ff	1658	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	1659
bogdanm	0:9b334a45a8ff	1660	/* Update state */
bogdanm	0:9b334a45a8ff	1661	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1662
bogdanm	0:9b334a45a8ff	1663	HAL_QSPI_RxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1664	}
bogdanm	0:9b334a45a8ff	1665	}
bogdanm	0:9b334a45a8ff	1666
bogdanm	0:9b334a45a8ff	1667	/**
bogdanm	0:9b334a45a8ff	1668	* @brief DMA QSPI transmit process complete callback.
bogdanm	0:9b334a45a8ff	1669	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	1670	* @retval None
bogdanm	0:9b334a45a8ff	1671	*/
bogdanm	0:9b334a45a8ff	1672	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1673	{
bogdanm	0:9b334a45a8ff	1674	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1675	hqspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1676
bogdanm	0:9b334a45a8ff	1677	/* Wait for QSPI TC Flag */
bogdanm	0:9b334a45a8ff	1678	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1679	{
bogdanm	0:9b334a45a8ff	1680	/* Time out Occurred */
bogdanm	0:9b334a45a8ff	1681	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	1682	}
bogdanm	0:9b334a45a8ff	1683	else
bogdanm	0:9b334a45a8ff	1684	{
bogdanm	0:9b334a45a8ff	1685	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
bogdanm	0:9b334a45a8ff	1686	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
bogdanm	0:9b334a45a8ff	1687
bogdanm	0:9b334a45a8ff	1688	/* Disable the DMA channel */
bogdanm	0:9b334a45a8ff	1689	HAL_DMA_Abort(hdma);
bogdanm	0:9b334a45a8ff	1690
bogdanm	0:9b334a45a8ff	1691	/* Clear Transfer Complete bit */
bogdanm	0:9b334a45a8ff	1692	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
bogdanm	0:9b334a45a8ff	1693
bogdanm	0:9b334a45a8ff	1694	/* Clear Busy bit */
bogdanm	0:9b334a45a8ff	1695	HAL_QSPI_Abort(hqspi);
bogdanm	0:9b334a45a8ff	1696
bogdanm	0:9b334a45a8ff	1697	/* Update state */
bogdanm	0:9b334a45a8ff	1698	hqspi->State = HAL_QSPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1699
bogdanm	0:9b334a45a8ff	1700	HAL_QSPI_TxCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1701	}
bogdanm	0:9b334a45a8ff	1702	}
bogdanm	0:9b334a45a8ff	1703
bogdanm	0:9b334a45a8ff	1704	/**
bogdanm	0:9b334a45a8ff	1705	* @brief DMA QSPI receive process half complete callback
bogdanm	0:9b334a45a8ff	1706	* @param hdma : DMA handle
bogdanm	0:9b334a45a8ff	1707	* @retval None
bogdanm	0:9b334a45a8ff	1708	*/
bogdanm	0:9b334a45a8ff	1709	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1710	{
bogdanm	0:9b334a45a8ff	1711	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1712
bogdanm	0:9b334a45a8ff	1713	HAL_QSPI_RxHalfCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1714	}
bogdanm	0:9b334a45a8ff	1715
bogdanm	0:9b334a45a8ff	1716	/**
bogdanm	0:9b334a45a8ff	1717	* @brief DMA QSPI transmit process half complete callback
bogdanm	0:9b334a45a8ff	1718	* @param hdma : DMA handle
bogdanm	0:9b334a45a8ff	1719	* @retval None
bogdanm	0:9b334a45a8ff	1720	*/
bogdanm	0:9b334a45a8ff	1721	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1722	{
bogdanm	0:9b334a45a8ff	1723	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1724
bogdanm	0:9b334a45a8ff	1725	HAL_QSPI_TxHalfCpltCallback(hqspi);
bogdanm	0:9b334a45a8ff	1726	}
bogdanm	0:9b334a45a8ff	1727
bogdanm	0:9b334a45a8ff	1728	/**
bogdanm	0:9b334a45a8ff	1729	* @brief DMA QSPI communication error callback.
bogdanm	0:9b334a45a8ff	1730	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	1731	* @retval None
bogdanm	0:9b334a45a8ff	1732	*/
bogdanm	0:9b334a45a8ff	1733	static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1734	{
bogdanm	0:9b334a45a8ff	1735	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1736
bogdanm	0:9b334a45a8ff	1737	hqspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1738	hqspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1739	hqspi->State = HAL_QSPI_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1740	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
bogdanm	0:9b334a45a8ff	1741
bogdanm	0:9b334a45a8ff	1742	HAL_QSPI_ErrorCallback(hqspi);
bogdanm	0:9b334a45a8ff	1743	}
bogdanm	0:9b334a45a8ff	1744
bogdanm	0:9b334a45a8ff	1745	/**
bogdanm	0:9b334a45a8ff	1746	* @brief This function wait a flag state until time out.
bogdanm	0:9b334a45a8ff	1747	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1748	* @param Flag: Flag checked
bogdanm	0:9b334a45a8ff	1749	* @param State: Value of the flag expected
bogdanm	0:9b334a45a8ff	1750	* @param Timeout: Duration of the time out
bogdanm	0:9b334a45a8ff	1751	* @retval HAL status
bogdanm	0:9b334a45a8ff	1752	*/
bogdanm	0:9b334a45a8ff	1753	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
bogdanm	0:9b334a45a8ff	1754	FlagStatus State, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1755	{
bogdanm	0:9b334a45a8ff	1756	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1757
bogdanm	0:9b334a45a8ff	1758	/* Wait until flag is in expected state */
bogdanm	0:9b334a45a8ff	1759	while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
bogdanm	0:9b334a45a8ff	1760	{
bogdanm	0:9b334a45a8ff	1761	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	1762	if (Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1763	{
bogdanm	0:9b334a45a8ff	1764	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	1765	{
bogdanm	0:9b334a45a8ff	1766	hqspi->State = HAL_QSPI_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1767	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	1768
bogdanm	0:9b334a45a8ff	1769	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1770	}
bogdanm	0:9b334a45a8ff	1771	}
bogdanm	0:9b334a45a8ff	1772	}
bogdanm	0:9b334a45a8ff	1773	return HAL_OK;
bogdanm	0:9b334a45a8ff	1774	}
bogdanm	0:9b334a45a8ff	1775
bogdanm	0:9b334a45a8ff	1776	/**
bogdanm	0:9b334a45a8ff	1777	* @brief This function configures the communication registers
bogdanm	0:9b334a45a8ff	1778	* @param hqspi: QSPI handle
bogdanm	0:9b334a45a8ff	1779	* @param cmd: structure that contains the command configuration information
bogdanm	0:9b334a45a8ff	1780	* @param FunctionalMode: functional mode to configured
bogdanm	0:9b334a45a8ff	1781	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1782	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
bogdanm	0:9b334a45a8ff	1783	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
bogdanm	0:9b334a45a8ff	1784	* @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
bogdanm	0:9b334a45a8ff	1785	* @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
bogdanm	0:9b334a45a8ff	1786	* @retval None
bogdanm	0:9b334a45a8ff	1787	*/
bogdanm	0:9b334a45a8ff	1788	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode)
bogdanm	0:9b334a45a8ff	1789	{
bogdanm	0:9b334a45a8ff	1790	assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
bogdanm	0:9b334a45a8ff	1791
bogdanm	0:9b334a45a8ff	1792	if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
bogdanm	0:9b334a45a8ff	1793	{
bogdanm	0:9b334a45a8ff	1794	/* Configure QSPI: DLR register with the number of data to read or write */
bogdanm	0:9b334a45a8ff	1795	WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
bogdanm	0:9b334a45a8ff	1796	}
bogdanm	0:9b334a45a8ff	1797
bogdanm	0:9b334a45a8ff	1798	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
bogdanm	0:9b334a45a8ff	1799	{
bogdanm	0:9b334a45a8ff	1800	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1801	{
bogdanm	0:9b334a45a8ff	1802	/* Configure QSPI: ABR register with alternate bytes value */
bogdanm	0:9b334a45a8ff	1803	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
bogdanm	0:9b334a45a8ff	1804
bogdanm	0:9b334a45a8ff	1805	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1806	{
bogdanm	0:9b334a45a8ff	1807	/---- Command with instruction, address and alternate bytes ----/
bogdanm	0:9b334a45a8ff	1808	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1809	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1810	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1811	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
bogdanm	0:9b334a45a8ff	1812	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1813
bogdanm	0:9b334a45a8ff	1814	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1815	{
bogdanm	0:9b334a45a8ff	1816	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1817	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1818	}
bogdanm	0:9b334a45a8ff	1819	}
bogdanm	0:9b334a45a8ff	1820	else
bogdanm	0:9b334a45a8ff	1821	{
bogdanm	0:9b334a45a8ff	1822	/---- Command with instruction and alternate bytes ----/
bogdanm	0:9b334a45a8ff	1823	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1824	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1825	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1826	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1827	cmd->Instruction \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1828	}
bogdanm	0:9b334a45a8ff	1829	}
bogdanm	0:9b334a45a8ff	1830	else
bogdanm	0:9b334a45a8ff	1831	{
bogdanm	0:9b334a45a8ff	1832	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1833	{
bogdanm	0:9b334a45a8ff	1834	/---- Command with instruction and address ----/
bogdanm	0:9b334a45a8ff	1835	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1836	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1837	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1838	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1839	cmd->Instruction \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1840
bogdanm	0:9b334a45a8ff	1841	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1842	{
bogdanm	0:9b334a45a8ff	1843	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1844	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1845	}
bogdanm	0:9b334a45a8ff	1846	}
bogdanm	0:9b334a45a8ff	1847	else
bogdanm	0:9b334a45a8ff	1848	{
bogdanm	0:9b334a45a8ff	1849	/---- Command with only instruction ----/
bogdanm	0:9b334a45a8ff	1850	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1851	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1852	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1853	cmd->AddressMode \| cmd->InstructionMode \| cmd->Instruction \|
bogdanm	0:9b334a45a8ff	1854	FunctionalMode));
bogdanm	0:9b334a45a8ff	1855	}
bogdanm	0:9b334a45a8ff	1856	}
bogdanm	0:9b334a45a8ff	1857	}
bogdanm	0:9b334a45a8ff	1858	else
bogdanm	0:9b334a45a8ff	1859	{
bogdanm	0:9b334a45a8ff	1860	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
bogdanm	0:9b334a45a8ff	1861	{
bogdanm	0:9b334a45a8ff	1862	/* Configure QSPI: ABR register with alternate bytes value */
bogdanm	0:9b334a45a8ff	1863	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
bogdanm	0:9b334a45a8ff	1864
bogdanm	0:9b334a45a8ff	1865	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1866	{
bogdanm	0:9b334a45a8ff	1867	/---- Command with address and alternate bytes ----/
bogdanm	0:9b334a45a8ff	1868	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1869	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1870	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1871	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
bogdanm	0:9b334a45a8ff	1872	cmd->InstructionMode \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1873
bogdanm	0:9b334a45a8ff	1874	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1875	{
bogdanm	0:9b334a45a8ff	1876	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1877	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1878	}
bogdanm	0:9b334a45a8ff	1879	}
bogdanm	0:9b334a45a8ff	1880	else
bogdanm	0:9b334a45a8ff	1881	{
bogdanm	0:9b334a45a8ff	1882	/---- Command with only alternate bytes ----/
bogdanm	0:9b334a45a8ff	1883	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1884	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1885	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
bogdanm	0:9b334a45a8ff	1886	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1887	FunctionalMode));
bogdanm	0:9b334a45a8ff	1888	}
bogdanm	0:9b334a45a8ff	1889	}
bogdanm	0:9b334a45a8ff	1890	else
bogdanm	0:9b334a45a8ff	1891	{
bogdanm	0:9b334a45a8ff	1892	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
bogdanm	0:9b334a45a8ff	1893	{
bogdanm	0:9b334a45a8ff	1894	/---- Command with only address ----/
bogdanm	0:9b334a45a8ff	1895	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1896	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1897	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1898	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
bogdanm	0:9b334a45a8ff	1899	FunctionalMode));
bogdanm	0:9b334a45a8ff	1900
bogdanm	0:9b334a45a8ff	1901	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
bogdanm	0:9b334a45a8ff	1902	{
bogdanm	0:9b334a45a8ff	1903	/* Configure QSPI: AR register with address value */
bogdanm	0:9b334a45a8ff	1904	WRITE_REG(hqspi->Instance->AR, cmd->Address);
bogdanm	0:9b334a45a8ff	1905	}
bogdanm	0:9b334a45a8ff	1906	}
bogdanm	0:9b334a45a8ff	1907	else
bogdanm	0:9b334a45a8ff	1908	{
bogdanm	0:9b334a45a8ff	1909	/---- Command with only data phase ----/
bogdanm	0:9b334a45a8ff	1910	if (cmd->DataMode != QSPI_DATA_NONE)
bogdanm	0:9b334a45a8ff	1911	{
bogdanm	0:9b334a45a8ff	1912	/* Configure QSPI: CCR register with all communications parameters */
bogdanm	0:9b334a45a8ff	1913	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
bogdanm	0:9b334a45a8ff	1914	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
bogdanm	0:9b334a45a8ff	1915	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
bogdanm	0:9b334a45a8ff	1916	}
bogdanm	0:9b334a45a8ff	1917	}
bogdanm	0:9b334a45a8ff	1918	}
bogdanm	0:9b334a45a8ff	1919	}
bogdanm	0:9b334a45a8ff	1920	}
bogdanm	0:9b334a45a8ff	1921	/**
bogdanm	0:9b334a45a8ff	1922	* @}
bogdanm	0:9b334a45a8ff	1923	*/
bogdanm	0:9b334a45a8ff	1924
bogdanm	0:9b334a45a8ff	1925	#endif /* HAL_QSPI_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1926	/**
bogdanm	0:9b334a45a8ff	1927	* @}
bogdanm	0:9b334a45a8ff	1928	*/
bogdanm	0:9b334a45a8ff	1929
bogdanm	0:9b334a45a8ff	1930	/**
bogdanm	0:9b334a45a8ff	1931	* @}
bogdanm	0:9b334a45a8ff	1932	*/
bogdanm	0:9b334a45a8ff	1933
bogdanm	0:9b334a45a8ff	1934	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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